diff options
92 files changed, 5606 insertions, 277 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 8c84196b97..474572f245 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -285,6 +285,7 @@ config ARCH_MPC837X source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig" source "arch/powerpc/cpu/mpc83xx/bats/Kconfig" source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig" menu "Legacy options" diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 91451e7b30..5ce7b794b2 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -13,6 +13,7 @@ #endif #include "lblaw/lblaw.h" +#include "elbc/elbc.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig new file mode 100644 index 0000000000..74c4ff3ed4 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig @@ -0,0 +1,32 @@ +menu "ELBC register setup" + +choice + prompt "OR/BR for NAND SPL" + +config ELBC_BR_OR_NAND_PRELIM_NONE + bool "None" + +config ELBC_BR_OR_NAND_PRELIM_0 + bool "0" + +config ELBC_BR_OR_NAND_PRELIM_1 + bool "1" + +config ELBC_BR_OR_NAND_PRELIM_2 + bool "2" + +config ELBC_BR_OR_NAND_PRELIM_3 + bool "3" + +config ELBC_BR_OR_NAND_PRELIM_4 + bool "4" + +endchoice + +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4" + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 new file mode 100644 index 0000000000..23e81ab0bf --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR0_OR0 + bool "ELBC BR0/OR0" + +if ELBC_BR0_OR0 + +config BR0_OR0_NAME + string "Identifier" + +config BR0_OR0_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR0_PORTSIZE_8BIT + bool "8-bit" + +config BR0_PORTSIZE_16BIT + depends on !BR0_MACHINE_FCM + bool "16-bit" + + +config BR0_PORTSIZE_32BIT + depends on !BR0_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR0_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR0_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR0_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR0_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR0_WRITE_PROTECT + bool "Write-protect" + +config BR0_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR0_MACHINE_GPCM + bool "GPCM" + +config BR0_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR0_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR0_MACHINE_UPMA + select BR0_MACHINE_UPM + bool "UPM (A)" + +config BR0_MACHINE_UPMB + select BR0_MACHINE_UPM + bool "UPM (B)" + +config BR0_MACHINE_UPMC + select BR0_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR0_ATOMIC_NONE + bool "No atomic operations" + +config BR0_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR0_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR0_MACHINE_GPCM || BR0_MACHINE_FCM || BR0_MACHINE_UPM || BR0_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR0_AM_32_KBYTES + depends on !BR0_MACHINE_SDRAM + bool "32 kb" + +config OR0_AM_64_KBYTES + bool "64 kb" + +config OR0_AM_128_KBYTES + bool "128 kb" + +config OR0_AM_256_KBYTES + bool "256 kb" + +config OR0_AM_512_KBYTES + bool "512 kb" + +config OR0_AM_1_MBYTES + bool "1 mb" + +config OR0_AM_2_MBYTES + bool "2 mb" + +config OR0_AM_4_MBYTES + bool "4 mb" + +config OR0_AM_8_MBYTES + bool "8 mb" + +config OR0_AM_16_MBYTES + bool "16 mb" + +config OR0_AM_32_MBYTES + bool "32 mb" + +config OR0_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR0_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR0_AM_256_MBYTES + bool "256 mb" + +config OR0_AM_512_MBYTES + depends on BR0_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR0_AM_1_GBYTES + bool "1 gb" + +config OR0_AM_2_GBYTES + depends on BR0_MACHINE_FCM + bool "2 gb" + +config OR0_AM_4_GBYTES + depends on BR0_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR0_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR0_BCTLD_ASSERTED + bool "Asserted" + +config OR0_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR0_MACHINE_GPCM || BR0_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR0_SCY_0 + bool "No wait states" + +config OR0_SCY_1 + bool "1 wait state" + +config OR0_SCY_2 + bool "2 wait states" + +config OR0_SCY_3 + bool "3 wait states" + +config OR0_SCY_4 + bool "4 wait states" + +config OR0_SCY_5 + bool "5 wait states" + +config OR0_SCY_6 + bool "6 wait states" + +config OR0_SCY_7 + bool "7 wait states" + +config OR0_SCY_8 + depends on BR0_MACHINE_GPCM + bool "8 wait states" + +config OR0_SCY_9 + depends on BR0_MACHINE_GPCM + bool "9 wait states" + +config OR0_SCY_10 + depends on BR0_MACHINE_GPCM + bool "10 wait states" + +config OR0_SCY_11 + depends on BR0_MACHINE_GPCM + bool "11 wait states" + +config OR0_SCY_12 + depends on BR0_MACHINE_GPCM + bool "12 wait states" + +config OR0_SCY_13 + depends on BR0_MACHINE_GPCM + bool "13 wait states" + +config OR0_SCY_14 + depends on BR0_MACHINE_GPCM + bool "14 wait states" + +config OR0_SCY_15 + depends on BR0_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR0_MACHINE_GPCM || BR0_MACHINE_FCM + +if BR0_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR0_CSNT_NORMAL + bool "Normal" + +config OR0_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR0_ACS_SAME_TIME + bool "At the same time" + +config OR0_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR0_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR0_XACS_NORMAL + bool "Normal" + +config OR0_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR0_SETA_INTERNAL + bool "Access is terminated internally" + +config OR0_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR0_MACHINE_GPCM + +if BR0_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR0_PGS_SMALL + bool "Small page device" + +config OR0_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR0_CSCT_1_CYCLE + depends on OR0_TRLX_NORMAL + bool "1 cycle" + +config OR0_CSCT_2_CYCLE + depends on OR0_TRLX_RELAXED + bool "2 cycles" + +config OR0_CSCT_4_CYCLE + depends on OR0_TRLX_NORMAL + bool "4 cycles" + +config OR0_CSCT_8_CYCLE + depends on OR0_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR0_CST_COINCIDENT + depends on OR0_TRLX_NORMAL + bool "Coincident with any command" + +config OR0_CST_QUARTER_CLOCK + depends on OR0_TRLX_NORMAL + bool "0.25 clocks after" + +config OR0_CST_HALF_CLOCK + depends on OR0_TRLX_RELAXED + bool "0.5 clocks after" + +config OR0_CST_ONE_CLOCK + depends on OR0_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR0_CHT_HALF_CLOCK + depends on OR0_TRLX_NORMAL + bool "0.5 clocks before" + +config OR0_CHT_ONE_CLOCK + depends on OR0_TRLX_NORMAL + bool "1 clock before" + +config OR0_CHT_ONE_HALF_CLOCK + depends on OR0_TRLX_RELAXED + bool "1.5 clocks before" + +config OR0_CHT_TWO_CLOCK + depends on OR0_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR0_RST_THREE_QUARTER_CLOCK + depends on OR0_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR0_RST_ONE_HALF_CLOCK + depends on OR0_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR0_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR0_MACHINE_FCM + +if BR0_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR0_BI_BURSTSUPPORT + bool "Support burst access" + +config OR0_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR0_MACHINE_UPM + +if BR0_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR0_COLS_7 + bool "7" + +config OR0_COLS_8 + bool "8" + +config OR0_COLS_9 + bool "9" + +config OR0_COLS_10 + bool "10" + +config OR0_COLS_11 + bool "11" + +config OR0_COLS_12 + bool "12" + +config OR0_COLS_13 + bool "13" + +config OR0_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR0_ROWS_9 + bool "9" + +config OR0_ROWS_10 + bool "10" + +config OR0_ROWS_11 + bool "11" + +config OR0_ROWS_12 + bool "12" + +config OR0_ROWS_13 + bool "13" + +config OR0_ROWS_14 + bool "14" + +config OR0_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR0_PMSEL_BTB + bool "Back-to-back" + +config OR0_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR0_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR0_TRLX_NORMAL + bool "Normal" + +config OR0_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR0_EHTR_NORMAL + depends on OR0_TRLX_NORMAL + bool "Normal" + +config OR0_EHTR_1_CYCLE + depends on OR0_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR0_EHTR_4_CYCLE + depends on OR0_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR0_EHTR_8_CYCLE + depends on OR0_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR0_EAD_NONE + bool "None" + +config OR0_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR0_OR0 + +config BR0_PORTSIZE + hex + default 0x800 if BR0_PORTSIZE_8BIT + default 0x1000 if BR0_PORTSIZE_16BIT + default 0x1800 if BR0_PORTSIZE_32BIT + +config BR0_ERRORCHECKING + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if BR0_ERRORCHECKING_DISABLED + default 0x200 if BR0_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR0_ERRORCHECKING_BOTH + +config BR0_WRITE_PROTECT_BIT + hex + default 0x0 if !BR0_WRITE_PROTECT + default 0x100 if BR0_WRITE_PROTECT + +config BR0_MACHINE + hex + default 0x0 if BR0_MACHINE_GPCM + default 0x20 if BR0_MACHINE_FCM + default 0x60 if BR0_MACHINE_SDRAM + default 0x80 if BR0_MACHINE_UPMA + default 0xa0 if BR0_MACHINE_UPMB + default 0xc0 if BR0_MACHINE_UPMC + +config BR0_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR0_ATOMIC_NONE + default 0x4 if BR0_ATOMIC_RAWA + default 0x8 if BR0_ATOMIC_WARA + +config BR0_VALID_BIT + hex + default 0x0 if !ELBC_BR0_OR0 + default 0x1 if ELBC_BR0_OR0 + +config OR0_AM + hex + default 0xffff8000 if OR0_AM_32_KBYTES && !BR0_MACHINE_SDRAM + default 0xffff0000 if OR0_AM_64_KBYTES + default 0xfffe0000 if OR0_AM_128_KBYTES + default 0xfffc0000 if OR0_AM_256_KBYTES + default 0xfff80000 if OR0_AM_512_KBYTES + default 0xfff00000 if OR0_AM_1_MBYTES + default 0xffe00000 if OR0_AM_2_MBYTES + default 0xffc00000 if OR0_AM_4_MBYTES + default 0xff800000 if OR0_AM_8_MBYTES + default 0xff000000 if OR0_AM_16_MBYTES + default 0xfe000000 if OR0_AM_32_MBYTES + default 0xfc000000 if OR0_AM_64_MBYTES + default 0xf8000000 if OR0_AM_128_MBYTES + default 0xf0000000 if OR0_AM_256_MBYTES + default 0xe0000000 if OR0_AM_512_MBYTES + default 0xc0000000 if OR0_AM_1_GBYTES + default 0x80000000 if OR0_AM_2_GBYTES + default 0x00000000 if OR0_AM_4_GBYTES + +config OR0_XAM + hex + default 0x0 if !OR0_XAM_SET + default 0x6000 if OR0_XAM_SET + +config OR0_BCTLD + hex + default 0x0 if OR0_BCTLD_ASSERTED + default 0x1000 if OR0_BCTLD_NOT_ASSERTED + +config OR0_BI + hex + default 0x0 if !BR0_MACHINE_UPM + default 0x0 if OR0_BI_BURSTSUPPORT + default 0x100 if OR0_BI_BURSTINHIBIT + +config OR0_COLS + hex + default 0x0 if !BR0_MACHINE_SDRAM + default 0x0 if OR0_COLS_7 + default 0x400 if OR0_COLS_8 + default 0x800 if OR0_COLS_9 + default 0xc00 if OR0_COLS_10 + default 0x1000 if OR0_COLS_11 + default 0x1400 if OR0_COLS_12 + default 0x1800 if OR0_COLS_13 + default 0x1c00 if OR0_COLS_14 + +config OR0_ROWS + hex + default 0x0 if !BR0_MACHINE_SDRAM + default 0x0 if OR0_ROWS_9 + default 0x40 if OR0_ROWS_10 + default 0x80 if OR0_ROWS_11 + default 0xc0 if OR0_ROWS_12 + default 0x100 if OR0_ROWS_13 + default 0x140 if OR0_ROWS_14 + default 0x180 if OR0_ROWS_15 + +config OR0_PMSEL + hex + default 0x0 if !BR0_MACHINE_SDRAM + default 0x0 if OR0_PMSEL_BTB + default 0x20 if OR0_PMSEL_KEPT_OPEN + +config OR0_SCY + hex + default 0x0 if !BR0_MACHINE_GPCM && !BR0_MACHINE_FCM + default 0x0 if OR0_SCY_0 + default 0x10 if OR0_SCY_1 + default 0x20 if OR0_SCY_2 + default 0x30 if OR0_SCY_3 + default 0x40 if OR0_SCY_4 + default 0x50 if OR0_SCY_5 + default 0x60 if OR0_SCY_6 + default 0x70 if OR0_SCY_7 + default 0x80 if OR0_SCY_8 + default 0x90 if OR0_SCY_9 + default 0xa0 if OR0_SCY_10 + default 0xb0 if OR0_SCY_11 + default 0xc0 if OR0_SCY_12 + default 0xd0 if OR0_SCY_13 + default 0xe0 if OR0_SCY_14 + default 0xf0 if OR0_SCY_15 + +config OR0_PGS + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_PGS_SMALL + default 0x400 if OR0_PGS_LARGE + +config OR0_CSCT + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_CSCT_1_CYCLE + default 0x0 if OR0_CSCT_2_CYCLE + default 0x200 if OR0_CSCT_4_CYCLE + default 0x200 if OR0_CSCT_8_CYCLE + +config OR0_CST + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_CST_COINCIDENT + default 0x100 if OR0_CST_QUARTER_CLOCK + default 0x0 if OR0_CST_HALF_CLOCK + default 0x100 if OR0_CST_ONE_CLOCK + +config OR0_CHT + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_CHT_HALF_CLOCK + default 0x80 if OR0_CHT_ONE_CLOCK + default 0x0 if OR0_CHT_ONE_HALF_CLOCK + default 0x80 if OR0_CHT_TWO_CLOCK + +config OR0_RST + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_RST_THREE_QUARTER_CLOCK + default 0x8 if OR0_RST_ONE_CLOCK + default 0x0 if OR0_RST_ONE_HALF_CLOCK + +config OR0_CSNT + hex + default 0x0 if !BR0_MACHINE_GPCM + default 0x0 if OR0_CSNT_NORMAL + default 0x800 if OR0_CSNT_EARLIER + +config OR0_ACS + hex + default 0x0 if !BR0_MACHINE_GPCM + default 0x0 if OR0_ACS_SAME_TIME + default 0x400 if OR0_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR0_ACS_HALF_CYCLE_EARLIER + +config OR0_XACS + hex + default 0x0 if !BR0_MACHINE_GPCM + default 0x0 if OR0_XACS_NORMAL + default 0x100 if OR0_XACS_EXTENDED + +config OR0_SETA + hex + default 0x0 if !BR0_MACHINE_GPCM + default 0x0 if OR0_SETA_INTERNAL + default 0x8 if OR0_SETA_EXTERNAL + +config OR0_TRLX + hex + default 0x0 if OR0_TRLX_NORMAL + default 0x4 if OR0_TRLX_RELAXED + +config OR0_EHTR + hex + default 0x0 if OR0_EHTR_NORMAL + default 0x2 if OR0_EHTR_1_CYCLE + default 0x0 if OR0_EHTR_4_CYCLE + default 0x2 if OR0_EHTR_8_CYCLE + +config OR0_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR0_EAD_NONE + default 0x1 if OR0_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 new file mode 100644 index 0000000000..08dcc7dd2b --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR1_OR1 + bool "ELBC BR1/OR1" + +if ELBC_BR1_OR1 + +config BR1_OR1_NAME + string "Identifier" + +config BR1_OR1_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR1_PORTSIZE_8BIT + bool "8-bit" + +config BR1_PORTSIZE_16BIT + depends on !BR1_MACHINE_FCM + bool "16-bit" + + +config BR1_PORTSIZE_32BIT + depends on !BR1_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR1_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR1_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR1_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR1_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR1_WRITE_PROTECT + bool "Write-protect" + +config BR1_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR1_MACHINE_GPCM + bool "GPCM" + +config BR1_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR1_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR1_MACHINE_UPMA + select BR1_MACHINE_UPM + bool "UPM (A)" + +config BR1_MACHINE_UPMB + select BR1_MACHINE_UPM + bool "UPM (B)" + +config BR1_MACHINE_UPMC + select BR1_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR1_ATOMIC_NONE + bool "No atomic operations" + +config BR1_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR1_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR1_MACHINE_GPCM || BR1_MACHINE_FCM || BR1_MACHINE_UPM || BR1_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR1_AM_32_KBYTES + depends on !BR1_MACHINE_SDRAM + bool "32 kb" + +config OR1_AM_64_KBYTES + bool "64 kb" + +config OR1_AM_128_KBYTES + bool "128 kb" + +config OR1_AM_256_KBYTES + bool "256 kb" + +config OR1_AM_512_KBYTES + bool "512 kb" + +config OR1_AM_1_MBYTES + bool "1 mb" + +config OR1_AM_2_MBYTES + bool "2 mb" + +config OR1_AM_4_MBYTES + bool "4 mb" + +config OR1_AM_8_MBYTES + bool "8 mb" + +config OR1_AM_16_MBYTES + bool "16 mb" + +config OR1_AM_32_MBYTES + bool "32 mb" + +config OR1_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR1_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR1_AM_256_MBYTES + bool "256 mb" + +config OR1_AM_512_MBYTES + depends on BR1_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR1_AM_1_GBYTES + bool "1 gb" + +config OR1_AM_2_GBYTES + depends on BR1_MACHINE_FCM + bool "2 gb" + +config OR1_AM_4_GBYTES + depends on BR1_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR1_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR1_BCTLD_ASSERTED + bool "Asserted" + +config OR1_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR1_MACHINE_GPCM || BR1_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR1_SCY_0 + bool "No wait states" + +config OR1_SCY_1 + bool "1 wait state" + +config OR1_SCY_2 + bool "2 wait states" + +config OR1_SCY_3 + bool "3 wait states" + +config OR1_SCY_4 + bool "4 wait states" + +config OR1_SCY_5 + bool "5 wait states" + +config OR1_SCY_6 + bool "6 wait states" + +config OR1_SCY_7 + bool "7 wait states" + +config OR1_SCY_8 + depends on BR1_MACHINE_GPCM + bool "8 wait states" + +config OR1_SCY_9 + depends on BR1_MACHINE_GPCM + bool "9 wait states" + +config OR1_SCY_10 + depends on BR1_MACHINE_GPCM + bool "10 wait states" + +config OR1_SCY_11 + depends on BR1_MACHINE_GPCM + bool "11 wait states" + +config OR1_SCY_12 + depends on BR1_MACHINE_GPCM + bool "12 wait states" + +config OR1_SCY_13 + depends on BR1_MACHINE_GPCM + bool "13 wait states" + +config OR1_SCY_14 + depends on BR1_MACHINE_GPCM + bool "14 wait states" + +config OR1_SCY_15 + depends on BR1_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR1_MACHINE_GPCM || BR1_MACHINE_FCM + +if BR1_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR1_CSNT_NORMAL + bool "Normal" + +config OR1_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR1_ACS_SAME_TIME + bool "At the same time" + +config OR1_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR1_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR1_XACS_NORMAL + bool "Normal" + +config OR1_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR1_SETA_INTERNAL + bool "Access is terminated internally" + +config OR1_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR1_MACHINE_GPCM + +if BR1_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR1_PGS_SMALL + bool "Small page device" + +config OR1_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR1_CSCT_1_CYCLE + depends on OR1_TRLX_NORMAL + bool "1 cycle" + +config OR1_CSCT_2_CYCLE + depends on OR1_TRLX_RELAXED + bool "2 cycles" + +config OR1_CSCT_4_CYCLE + depends on OR1_TRLX_NORMAL + bool "4 cycles" + +config OR1_CSCT_8_CYCLE + depends on OR1_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR1_CST_COINCIDENT + depends on OR1_TRLX_NORMAL + bool "Coincident with any command" + +config OR1_CST_QUARTER_CLOCK + depends on OR1_TRLX_NORMAL + bool "0.25 clocks after" + +config OR1_CST_HALF_CLOCK + depends on OR1_TRLX_RELAXED + bool "0.5 clocks after" + +config OR1_CST_ONE_CLOCK + depends on OR1_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR1_CHT_HALF_CLOCK + depends on OR1_TRLX_NORMAL + bool "0.5 clocks before" + +config OR1_CHT_ONE_CLOCK + depends on OR1_TRLX_NORMAL + bool "1 clock before" + +config OR1_CHT_ONE_HALF_CLOCK + depends on OR1_TRLX_RELAXED + bool "1.5 clocks before" + +config OR1_CHT_TWO_CLOCK + depends on OR1_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR1_RST_THREE_QUARTER_CLOCK + depends on OR1_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR1_RST_ONE_HALF_CLOCK + depends on OR1_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR1_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR1_MACHINE_FCM + +if BR1_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR1_BI_BURSTSUPPORT + bool "Support burst access" + +config OR1_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR1_MACHINE_UPM + +if BR1_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR1_COLS_7 + bool "7" + +config OR1_COLS_8 + bool "8" + +config OR1_COLS_9 + bool "9" + +config OR1_COLS_10 + bool "10" + +config OR1_COLS_11 + bool "11" + +config OR1_COLS_12 + bool "12" + +config OR1_COLS_13 + bool "13" + +config OR1_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR1_ROWS_9 + bool "9" + +config OR1_ROWS_10 + bool "10" + +config OR1_ROWS_11 + bool "11" + +config OR1_ROWS_12 + bool "12" + +config OR1_ROWS_13 + bool "13" + +config OR1_ROWS_14 + bool "14" + +config OR1_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR1_PMSEL_BTB + bool "Back-to-back" + +config OR1_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR1_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR1_TRLX_NORMAL + bool "Normal" + +config OR1_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR1_EHTR_NORMAL + depends on OR1_TRLX_NORMAL + bool "Normal" + +config OR1_EHTR_1_CYCLE + depends on OR1_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR1_EHTR_4_CYCLE + depends on OR1_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR1_EHTR_8_CYCLE + depends on OR1_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR1_EAD_NONE + bool "None" + +config OR1_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR1_OR1 + +config BR1_PORTSIZE + hex + default 0x800 if BR1_PORTSIZE_8BIT + default 0x1000 if BR1_PORTSIZE_16BIT + default 0x1800 if BR1_PORTSIZE_32BIT + +config BR1_ERRORCHECKING + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if BR1_ERRORCHECKING_DISABLED + default 0x200 if BR1_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR1_ERRORCHECKING_BOTH + +config BR1_WRITE_PROTECT_BIT + hex + default 0x0 if !BR1_WRITE_PROTECT + default 0x100 if BR1_WRITE_PROTECT + +config BR1_MACHINE + hex + default 0x0 if BR1_MACHINE_GPCM + default 0x20 if BR1_MACHINE_FCM + default 0x60 if BR1_MACHINE_SDRAM + default 0x80 if BR1_MACHINE_UPMA + default 0xa0 if BR1_MACHINE_UPMB + default 0xc0 if BR1_MACHINE_UPMC + +config BR1_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR1_ATOMIC_NONE + default 0x4 if BR1_ATOMIC_RAWA + default 0x8 if BR1_ATOMIC_WARA + +config BR1_VALID_BIT + hex + default 0x0 if !ELBC_BR1_OR1 + default 0x1 if ELBC_BR1_OR1 + +config OR1_AM + hex + default 0xffff8000 if OR1_AM_32_KBYTES && !BR1_MACHINE_SDRAM + default 0xffff0000 if OR1_AM_64_KBYTES + default 0xfffe0000 if OR1_AM_128_KBYTES + default 0xfffc0000 if OR1_AM_256_KBYTES + default 0xfff80000 if OR1_AM_512_KBYTES + default 0xfff00000 if OR1_AM_1_MBYTES + default 0xffe00000 if OR1_AM_2_MBYTES + default 0xffc00000 if OR1_AM_4_MBYTES + default 0xff800000 if OR1_AM_8_MBYTES + default 0xff000000 if OR1_AM_16_MBYTES + default 0xfe000000 if OR1_AM_32_MBYTES + default 0xfc000000 if OR1_AM_64_MBYTES + default 0xf8000000 if OR1_AM_128_MBYTES + default 0xf0000000 if OR1_AM_256_MBYTES + default 0xe0000000 if OR1_AM_512_MBYTES + default 0xc0000000 if OR1_AM_1_GBYTES + default 0x80000000 if OR1_AM_2_GBYTES + default 0x00000000 if OR1_AM_4_GBYTES + +config OR1_XAM + hex + default 0x0 if !OR1_XAM_SET + default 0x6000 if OR1_XAM_SET + +config OR1_BCTLD + hex + default 0x0 if OR1_BCTLD_ASSERTED + default 0x1000 if OR1_BCTLD_NOT_ASSERTED + +config OR1_BI + hex + default 0x0 if !BR1_MACHINE_UPM + default 0x0 if OR1_BI_BURSTSUPPORT + default 0x100 if OR1_BI_BURSTINHIBIT + +config OR1_COLS + hex + default 0x0 if !BR1_MACHINE_SDRAM + default 0x0 if OR1_COLS_7 + default 0x400 if OR1_COLS_8 + default 0x800 if OR1_COLS_9 + default 0xc00 if OR1_COLS_10 + default 0x1000 if OR1_COLS_11 + default 0x1400 if OR1_COLS_12 + default 0x1800 if OR1_COLS_13 + default 0x1c00 if OR1_COLS_14 + +config OR1_ROWS + hex + default 0x0 if !BR1_MACHINE_SDRAM + default 0x0 if OR1_ROWS_9 + default 0x40 if OR1_ROWS_10 + default 0x80 if OR1_ROWS_11 + default 0xc0 if OR1_ROWS_12 + default 0x100 if OR1_ROWS_13 + default 0x140 if OR1_ROWS_14 + default 0x180 if OR1_ROWS_15 + +config OR1_PMSEL + hex + default 0x0 if !BR1_MACHINE_SDRAM + default 0x0 if OR1_PMSEL_BTB + default 0x20 if OR1_PMSEL_KEPT_OPEN + +config OR1_SCY + hex + default 0x0 if !BR1_MACHINE_GPCM && !BR1_MACHINE_FCM + default 0x0 if OR1_SCY_0 + default 0x10 if OR1_SCY_1 + default 0x20 if OR1_SCY_2 + default 0x30 if OR1_SCY_3 + default 0x40 if OR1_SCY_4 + default 0x50 if OR1_SCY_5 + default 0x60 if OR1_SCY_6 + default 0x70 if OR1_SCY_7 + default 0x80 if OR1_SCY_8 + default 0x90 if OR1_SCY_9 + default 0xa0 if OR1_SCY_10 + default 0xb0 if OR1_SCY_11 + default 0xc0 if OR1_SCY_12 + default 0xd0 if OR1_SCY_13 + default 0xe0 if OR1_SCY_14 + default 0xf0 if OR1_SCY_15 + +config OR1_PGS + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_PGS_SMALL + default 0x400 if OR1_PGS_LARGE + +config OR1_CSCT + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_CSCT_1_CYCLE + default 0x0 if OR1_CSCT_2_CYCLE + default 0x200 if OR1_CSCT_4_CYCLE + default 0x200 if OR1_CSCT_8_CYCLE + +config OR1_CST + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_CST_COINCIDENT + default 0x100 if OR1_CST_QUARTER_CLOCK + default 0x0 if OR1_CST_HALF_CLOCK + default 0x100 if OR1_CST_ONE_CLOCK + +config OR1_CHT + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_CHT_HALF_CLOCK + default 0x80 if OR1_CHT_ONE_CLOCK + default 0x0 if OR1_CHT_ONE_HALF_CLOCK + default 0x80 if OR1_CHT_TWO_CLOCK + +config OR1_RST + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_RST_THREE_QUARTER_CLOCK + default 0x8 if OR1_RST_ONE_CLOCK + default 0x0 if OR1_RST_ONE_HALF_CLOCK + +config OR1_CSNT + hex + default 0x0 if !BR1_MACHINE_GPCM + default 0x0 if OR1_CSNT_NORMAL + default 0x800 if OR1_CSNT_EARLIER + +config OR1_ACS + hex + default 0x0 if !BR1_MACHINE_GPCM + default 0x0 if OR1_ACS_SAME_TIME + default 0x400 if OR1_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR1_ACS_HALF_CYCLE_EARLIER + +config OR1_XACS + hex + default 0x0 if !BR1_MACHINE_GPCM + default 0x0 if OR1_XACS_NORMAL + default 0x100 if OR1_XACS_EXTENDED + +config OR1_SETA + hex + default 0x0 if !BR1_MACHINE_GPCM + default 0x0 if OR1_SETA_INTERNAL + default 0x8 if OR1_SETA_EXTERNAL + +config OR1_TRLX + hex + default 0x0 if OR1_TRLX_NORMAL + default 0x4 if OR1_TRLX_RELAXED + +config OR1_EHTR + hex + default 0x0 if OR1_EHTR_NORMAL + default 0x2 if OR1_EHTR_1_CYCLE + default 0x0 if OR1_EHTR_4_CYCLE + default 0x2 if OR1_EHTR_8_CYCLE + +config OR1_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR1_EAD_NONE + default 0x1 if OR1_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 new file mode 100644 index 0000000000..298d87f5e0 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR2_OR2 + bool "ELBC BR2/OR2" + +if ELBC_BR2_OR2 + +config BR2_OR2_NAME + string "Identifier" + +config BR2_OR2_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR2_PORTSIZE_8BIT + bool "8-bit" + +config BR2_PORTSIZE_16BIT + depends on !BR2_MACHINE_FCM + bool "16-bit" + + +config BR2_PORTSIZE_32BIT + depends on !BR2_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR2_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR2_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR2_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR2_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR2_WRITE_PROTECT + bool "Write-protect" + +config BR2_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR2_MACHINE_GPCM + bool "GPCM" + +config BR2_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR2_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR2_MACHINE_UPMA + select BR2_MACHINE_UPM + bool "UPM (A)" + +config BR2_MACHINE_UPMB + select BR2_MACHINE_UPM + bool "UPM (B)" + +config BR2_MACHINE_UPMC + select BR2_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR2_ATOMIC_NONE + bool "No atomic operations" + +config BR2_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR2_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR2_MACHINE_GPCM || BR2_MACHINE_FCM || BR2_MACHINE_UPM || BR2_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR2_AM_32_KBYTES + depends on !BR2_MACHINE_SDRAM + bool "32 kb" + +config OR2_AM_64_KBYTES + bool "64 kb" + +config OR2_AM_128_KBYTES + bool "128 kb" + +config OR2_AM_256_KBYTES + bool "256 kb" + +config OR2_AM_512_KBYTES + bool "512 kb" + +config OR2_AM_1_MBYTES + bool "1 mb" + +config OR2_AM_2_MBYTES + bool "2 mb" + +config OR2_AM_4_MBYTES + bool "4 mb" + +config OR2_AM_8_MBYTES + bool "8 mb" + +config OR2_AM_16_MBYTES + bool "16 mb" + +config OR2_AM_32_MBYTES + bool "32 mb" + +config OR2_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR2_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR2_AM_256_MBYTES + bool "256 mb" + +config OR2_AM_512_MBYTES + depends on BR2_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR2_AM_1_GBYTES + bool "1 gb" + +config OR2_AM_2_GBYTES + depends on BR2_MACHINE_FCM + bool "2 gb" + +config OR2_AM_4_GBYTES + depends on BR2_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR2_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR2_BCTLD_ASSERTED + bool "Asserted" + +config OR2_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR2_MACHINE_GPCM || BR2_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR2_SCY_0 + bool "No wait states" + +config OR2_SCY_1 + bool "1 wait state" + +config OR2_SCY_2 + bool "2 wait states" + +config OR2_SCY_3 + bool "3 wait states" + +config OR2_SCY_4 + bool "4 wait states" + +config OR2_SCY_5 + bool "5 wait states" + +config OR2_SCY_6 + bool "6 wait states" + +config OR2_SCY_7 + bool "7 wait states" + +config OR2_SCY_8 + depends on BR2_MACHINE_GPCM + bool "8 wait states" + +config OR2_SCY_9 + depends on BR2_MACHINE_GPCM + bool "9 wait states" + +config OR2_SCY_10 + depends on BR2_MACHINE_GPCM + bool "10 wait states" + +config OR2_SCY_11 + depends on BR2_MACHINE_GPCM + bool "11 wait states" + +config OR2_SCY_12 + depends on BR2_MACHINE_GPCM + bool "12 wait states" + +config OR2_SCY_13 + depends on BR2_MACHINE_GPCM + bool "13 wait states" + +config OR2_SCY_14 + depends on BR2_MACHINE_GPCM + bool "14 wait states" + +config OR2_SCY_15 + depends on BR2_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR2_MACHINE_GPCM || BR2_MACHINE_FCM + +if BR2_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR2_CSNT_NORMAL + bool "Normal" + +config OR2_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR2_ACS_SAME_TIME + bool "At the same time" + +config OR2_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR2_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR2_XACS_NORMAL + bool "Normal" + +config OR2_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR2_SETA_INTERNAL + bool "Access is terminated internally" + +config OR2_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR2_MACHINE_GPCM + +if BR2_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR2_PGS_SMALL + bool "Small page device" + +config OR2_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR2_CSCT_1_CYCLE + depends on OR2_TRLX_NORMAL + bool "1 cycle" + +config OR2_CSCT_2_CYCLE + depends on OR2_TRLX_RELAXED + bool "2 cycles" + +config OR2_CSCT_4_CYCLE + depends on OR2_TRLX_NORMAL + bool "4 cycles" + +config OR2_CSCT_8_CYCLE + depends on OR2_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR2_CST_COINCIDENT + depends on OR2_TRLX_NORMAL + bool "Coincident with any command" + +config OR2_CST_QUARTER_CLOCK + depends on OR2_TRLX_NORMAL + bool "0.25 clocks after" + +config OR2_CST_HALF_CLOCK + depends on OR2_TRLX_RELAXED + bool "0.5 clocks after" + +config OR2_CST_ONE_CLOCK + depends on OR2_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR2_CHT_HALF_CLOCK + depends on OR2_TRLX_NORMAL + bool "0.5 clocks before" + +config OR2_CHT_ONE_CLOCK + depends on OR2_TRLX_NORMAL + bool "1 clock before" + +config OR2_CHT_ONE_HALF_CLOCK + depends on OR2_TRLX_RELAXED + bool "1.5 clocks before" + +config OR2_CHT_TWO_CLOCK + depends on OR2_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR2_RST_THREE_QUARTER_CLOCK + depends on OR2_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR2_RST_ONE_HALF_CLOCK + depends on OR2_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR2_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR2_MACHINE_FCM + +if BR2_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR2_BI_BURSTSUPPORT + bool "Support burst access" + +config OR2_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR2_MACHINE_UPM + +if BR2_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR2_COLS_7 + bool "7" + +config OR2_COLS_8 + bool "8" + +config OR2_COLS_9 + bool "9" + +config OR2_COLS_10 + bool "10" + +config OR2_COLS_11 + bool "11" + +config OR2_COLS_12 + bool "12" + +config OR2_COLS_13 + bool "13" + +config OR2_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR2_ROWS_9 + bool "9" + +config OR2_ROWS_10 + bool "10" + +config OR2_ROWS_11 + bool "11" + +config OR2_ROWS_12 + bool "12" + +config OR2_ROWS_13 + bool "13" + +config OR2_ROWS_14 + bool "14" + +config OR2_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR2_PMSEL_BTB + bool "Back-to-back" + +config OR2_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR2_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR2_TRLX_NORMAL + bool "Normal" + +config OR2_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR2_EHTR_NORMAL + depends on OR2_TRLX_NORMAL + bool "Normal" + +config OR2_EHTR_1_CYCLE + depends on OR2_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR2_EHTR_4_CYCLE + depends on OR2_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR2_EHTR_8_CYCLE + depends on OR2_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR2_EAD_NONE + bool "None" + +config OR2_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR2_OR2 + +config BR2_PORTSIZE + hex + default 0x800 if BR2_PORTSIZE_8BIT + default 0x1000 if BR2_PORTSIZE_16BIT + default 0x1800 if BR2_PORTSIZE_32BIT + +config BR2_ERRORCHECKING + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if BR2_ERRORCHECKING_DISABLED + default 0x200 if BR2_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR2_ERRORCHECKING_BOTH + +config BR2_WRITE_PROTECT_BIT + hex + default 0x0 if !BR2_WRITE_PROTECT + default 0x100 if BR2_WRITE_PROTECT + +config BR2_MACHINE + hex + default 0x0 if BR2_MACHINE_GPCM + default 0x20 if BR2_MACHINE_FCM + default 0x60 if BR2_MACHINE_SDRAM + default 0x80 if BR2_MACHINE_UPMA + default 0xa0 if BR2_MACHINE_UPMB + default 0xc0 if BR2_MACHINE_UPMC + +config BR2_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR2_ATOMIC_NONE + default 0x4 if BR2_ATOMIC_RAWA + default 0x8 if BR2_ATOMIC_WARA + +config BR2_VALID_BIT + hex + default 0x0 if !ELBC_BR2_OR2 + default 0x1 if ELBC_BR2_OR2 + +config OR2_AM + hex + default 0xffff8000 if OR2_AM_32_KBYTES && !BR2_MACHINE_SDRAM + default 0xffff0000 if OR2_AM_64_KBYTES + default 0xfffe0000 if OR2_AM_128_KBYTES + default 0xfffc0000 if OR2_AM_256_KBYTES + default 0xfff80000 if OR2_AM_512_KBYTES + default 0xfff00000 if OR2_AM_1_MBYTES + default 0xffe00000 if OR2_AM_2_MBYTES + default 0xffc00000 if OR2_AM_4_MBYTES + default 0xff800000 if OR2_AM_8_MBYTES + default 0xff000000 if OR2_AM_16_MBYTES + default 0xfe000000 if OR2_AM_32_MBYTES + default 0xfc000000 if OR2_AM_64_MBYTES + default 0xf8000000 if OR2_AM_128_MBYTES + default 0xf0000000 if OR2_AM_256_MBYTES + default 0xe0000000 if OR2_AM_512_MBYTES + default 0xc0000000 if OR2_AM_1_GBYTES + default 0x80000000 if OR2_AM_2_GBYTES + default 0x00000000 if OR2_AM_4_GBYTES + +config OR2_XAM + hex + default 0x0 if !OR2_XAM_SET + default 0x6000 if OR2_XAM_SET + +config OR2_BCTLD + hex + default 0x0 if OR2_BCTLD_ASSERTED + default 0x1000 if OR2_BCTLD_NOT_ASSERTED + +config OR2_BI + hex + default 0x0 if !BR2_MACHINE_UPM + default 0x0 if OR2_BI_BURSTSUPPORT + default 0x100 if OR2_BI_BURSTINHIBIT + +config OR2_COLS + hex + default 0x0 if !BR2_MACHINE_SDRAM + default 0x0 if OR2_COLS_7 + default 0x400 if OR2_COLS_8 + default 0x800 if OR2_COLS_9 + default 0xc00 if OR2_COLS_10 + default 0x1000 if OR2_COLS_11 + default 0x1400 if OR2_COLS_12 + default 0x1800 if OR2_COLS_13 + default 0x1c00 if OR2_COLS_14 + +config OR2_ROWS + hex + default 0x0 if !BR2_MACHINE_SDRAM + default 0x0 if OR2_ROWS_9 + default 0x40 if OR2_ROWS_10 + default 0x80 if OR2_ROWS_11 + default 0xc0 if OR2_ROWS_12 + default 0x100 if OR2_ROWS_13 + default 0x140 if OR2_ROWS_14 + default 0x180 if OR2_ROWS_15 + +config OR2_PMSEL + hex + default 0x0 if !BR2_MACHINE_SDRAM + default 0x0 if OR2_PMSEL_BTB + default 0x20 if OR2_PMSEL_KEPT_OPEN + +config OR2_SCY + hex + default 0x0 if !BR2_MACHINE_GPCM && !BR2_MACHINE_FCM + default 0x0 if OR2_SCY_0 + default 0x10 if OR2_SCY_1 + default 0x20 if OR2_SCY_2 + default 0x30 if OR2_SCY_3 + default 0x40 if OR2_SCY_4 + default 0x50 if OR2_SCY_5 + default 0x60 if OR2_SCY_6 + default 0x70 if OR2_SCY_7 + default 0x80 if OR2_SCY_8 + default 0x90 if OR2_SCY_9 + default 0xa0 if OR2_SCY_10 + default 0xb0 if OR2_SCY_11 + default 0xc0 if OR2_SCY_12 + default 0xd0 if OR2_SCY_13 + default 0xe0 if OR2_SCY_14 + default 0xf0 if OR2_SCY_15 + +config OR2_PGS + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_PGS_SMALL + default 0x400 if OR2_PGS_LARGE + +config OR2_CSCT + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_CSCT_1_CYCLE + default 0x0 if OR2_CSCT_2_CYCLE + default 0x200 if OR2_CSCT_4_CYCLE + default 0x200 if OR2_CSCT_8_CYCLE + +config OR2_CST + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_CST_COINCIDENT + default 0x100 if OR2_CST_QUARTER_CLOCK + default 0x0 if OR2_CST_HALF_CLOCK + default 0x100 if OR2_CST_ONE_CLOCK + +config OR2_CHT + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_CHT_HALF_CLOCK + default 0x80 if OR2_CHT_ONE_CLOCK + default 0x0 if OR2_CHT_ONE_HALF_CLOCK + default 0x80 if OR2_CHT_TWO_CLOCK + +config OR2_RST + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_RST_THREE_QUARTER_CLOCK + default 0x8 if OR2_RST_ONE_CLOCK + default 0x0 if OR2_RST_ONE_HALF_CLOCK + +config OR2_CSNT + hex + default 0x0 if !BR2_MACHINE_GPCM + default 0x0 if OR2_CSNT_NORMAL + default 0x800 if OR2_CSNT_EARLIER + +config OR2_ACS + hex + default 0x0 if !BR2_MACHINE_GPCM + default 0x0 if OR2_ACS_SAME_TIME + default 0x400 if OR2_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR2_ACS_HALF_CYCLE_EARLIER + +config OR2_XACS + hex + default 0x0 if !BR2_MACHINE_GPCM + default 0x0 if OR2_XACS_NORMAL + default 0x100 if OR2_XACS_EXTENDED + +config OR2_SETA + hex + default 0x0 if !BR2_MACHINE_GPCM + default 0x0 if OR2_SETA_INTERNAL + default 0x8 if OR2_SETA_EXTERNAL + +config OR2_TRLX + hex + default 0x0 if OR2_TRLX_NORMAL + default 0x4 if OR2_TRLX_RELAXED + +config OR2_EHTR + hex + default 0x0 if OR2_EHTR_NORMAL + default 0x2 if OR2_EHTR_1_CYCLE + default 0x0 if OR2_EHTR_4_CYCLE + default 0x2 if OR2_EHTR_8_CYCLE + +config OR2_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR2_EAD_NONE + default 0x1 if OR2_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 new file mode 100644 index 0000000000..963831bfcb --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR3_OR3 + bool "ELBC BR3/OR3" + +if ELBC_BR3_OR3 + +config BR3_OR3_NAME + string "Identifier" + +config BR3_OR3_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR3_PORTSIZE_8BIT + bool "8-bit" + +config BR3_PORTSIZE_16BIT + depends on !BR3_MACHINE_FCM + bool "16-bit" + + +config BR3_PORTSIZE_32BIT + depends on !BR3_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR3_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR3_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR3_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR3_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR3_WRITE_PROTECT + bool "Write-protect" + +config BR3_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR3_MACHINE_GPCM + bool "GPCM" + +config BR3_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR3_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR3_MACHINE_UPMA + select BR3_MACHINE_UPM + bool "UPM (A)" + +config BR3_MACHINE_UPMB + select BR3_MACHINE_UPM + bool "UPM (B)" + +config BR3_MACHINE_UPMC + select BR3_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR3_ATOMIC_NONE + bool "No atomic operations" + +config BR3_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR3_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR3_MACHINE_GPCM || BR3_MACHINE_FCM || BR3_MACHINE_UPM || BR3_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR3_AM_32_KBYTES + depends on !BR3_MACHINE_SDRAM + bool "32 kb" + +config OR3_AM_64_KBYTES + bool "64 kb" + +config OR3_AM_128_KBYTES + bool "128 kb" + +config OR3_AM_256_KBYTES + bool "256 kb" + +config OR3_AM_512_KBYTES + bool "512 kb" + +config OR3_AM_1_MBYTES + bool "1 mb" + +config OR3_AM_2_MBYTES + bool "2 mb" + +config OR3_AM_4_MBYTES + bool "4 mb" + +config OR3_AM_8_MBYTES + bool "8 mb" + +config OR3_AM_16_MBYTES + bool "16 mb" + +config OR3_AM_32_MBYTES + bool "32 mb" + +config OR3_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR3_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR3_AM_256_MBYTES + bool "256 mb" + +config OR3_AM_512_MBYTES + depends on BR3_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR3_AM_1_GBYTES + bool "1 gb" + +config OR3_AM_2_GBYTES + depends on BR3_MACHINE_FCM + bool "2 gb" + +config OR3_AM_4_GBYTES + depends on BR3_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR3_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR3_BCTLD_ASSERTED + bool "Asserted" + +config OR3_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR3_MACHINE_GPCM || BR3_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR3_SCY_0 + bool "No wait states" + +config OR3_SCY_1 + bool "1 wait state" + +config OR3_SCY_2 + bool "2 wait states" + +config OR3_SCY_3 + bool "3 wait states" + +config OR3_SCY_4 + bool "4 wait states" + +config OR3_SCY_5 + bool "5 wait states" + +config OR3_SCY_6 + bool "6 wait states" + +config OR3_SCY_7 + bool "7 wait states" + +config OR3_SCY_8 + depends on BR3_MACHINE_GPCM + bool "8 wait states" + +config OR3_SCY_9 + depends on BR3_MACHINE_GPCM + bool "9 wait states" + +config OR3_SCY_10 + depends on BR3_MACHINE_GPCM + bool "10 wait states" + +config OR3_SCY_11 + depends on BR3_MACHINE_GPCM + bool "11 wait states" + +config OR3_SCY_12 + depends on BR3_MACHINE_GPCM + bool "12 wait states" + +config OR3_SCY_13 + depends on BR3_MACHINE_GPCM + bool "13 wait states" + +config OR3_SCY_14 + depends on BR3_MACHINE_GPCM + bool "14 wait states" + +config OR3_SCY_15 + depends on BR3_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR3_MACHINE_GPCM || BR3_MACHINE_FCM + +if BR3_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR3_CSNT_NORMAL + bool "Normal" + +config OR3_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR3_ACS_SAME_TIME + bool "At the same time" + +config OR3_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR3_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR3_XACS_NORMAL + bool "Normal" + +config OR3_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR3_SETA_INTERNAL + bool "Access is terminated internally" + +config OR3_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR3_MACHINE_GPCM + +if BR3_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR3_PGS_SMALL + bool "Small page device" + +config OR3_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR3_CSCT_1_CYCLE + depends on OR3_TRLX_NORMAL + bool "1 cycle" + +config OR3_CSCT_2_CYCLE + depends on OR3_TRLX_RELAXED + bool "2 cycles" + +config OR3_CSCT_4_CYCLE + depends on OR3_TRLX_NORMAL + bool "4 cycles" + +config OR3_CSCT_8_CYCLE + depends on OR3_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR3_CST_COINCIDENT + depends on OR3_TRLX_NORMAL + bool "Coincident with any command" + +config OR3_CST_QUARTER_CLOCK + depends on OR3_TRLX_NORMAL + bool "0.25 clocks after" + +config OR3_CST_HALF_CLOCK + depends on OR3_TRLX_RELAXED + bool "0.5 clocks after" + +config OR3_CST_ONE_CLOCK + depends on OR3_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR3_CHT_HALF_CLOCK + depends on OR3_TRLX_NORMAL + bool "0.5 clocks before" + +config OR3_CHT_ONE_CLOCK + depends on OR3_TRLX_NORMAL + bool "1 clock before" + +config OR3_CHT_ONE_HALF_CLOCK + depends on OR3_TRLX_RELAXED + bool "1.5 clocks before" + +config OR3_CHT_TWO_CLOCK + depends on OR3_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR3_RST_THREE_QUARTER_CLOCK + depends on OR3_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR3_RST_ONE_HALF_CLOCK + depends on OR3_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR3_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR3_MACHINE_FCM + +if BR3_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR3_BI_BURSTSUPPORT + bool "Support burst access" + +config OR3_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR3_MACHINE_UPM + +if BR3_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR3_COLS_7 + bool "7" + +config OR3_COLS_8 + bool "8" + +config OR3_COLS_9 + bool "9" + +config OR3_COLS_10 + bool "10" + +config OR3_COLS_11 + bool "11" + +config OR3_COLS_12 + bool "12" + +config OR3_COLS_13 + bool "13" + +config OR3_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR3_ROWS_9 + bool "9" + +config OR3_ROWS_10 + bool "10" + +config OR3_ROWS_11 + bool "11" + +config OR3_ROWS_12 + bool "12" + +config OR3_ROWS_13 + bool "13" + +config OR3_ROWS_14 + bool "14" + +config OR3_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR3_PMSEL_BTB + bool "Back-to-back" + +config OR3_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR3_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR3_TRLX_NORMAL + bool "Normal" + +config OR3_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR3_EHTR_NORMAL + depends on OR3_TRLX_NORMAL + bool "Normal" + +config OR3_EHTR_1_CYCLE + depends on OR3_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR3_EHTR_4_CYCLE + depends on OR3_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR3_EHTR_8_CYCLE + depends on OR3_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR3_EAD_NONE + bool "None" + +config OR3_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR3_OR3 + +config BR3_PORTSIZE + hex + default 0x800 if BR3_PORTSIZE_8BIT + default 0x1000 if BR3_PORTSIZE_16BIT + default 0x1800 if BR3_PORTSIZE_32BIT + +config BR3_ERRORCHECKING + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if BR3_ERRORCHECKING_DISABLED + default 0x200 if BR3_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR3_ERRORCHECKING_BOTH + +config BR3_WRITE_PROTECT_BIT + hex + default 0x0 if !BR3_WRITE_PROTECT + default 0x100 if BR3_WRITE_PROTECT + +config BR3_MACHINE + hex + default 0x0 if BR3_MACHINE_GPCM + default 0x20 if BR3_MACHINE_FCM + default 0x60 if BR3_MACHINE_SDRAM + default 0x80 if BR3_MACHINE_UPMA + default 0xa0 if BR3_MACHINE_UPMB + default 0xc0 if BR3_MACHINE_UPMC + +config BR3_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR3_ATOMIC_NONE + default 0x4 if BR3_ATOMIC_RAWA + default 0x8 if BR3_ATOMIC_WARA + +config BR3_VALID_BIT + hex + default 0x0 if !ELBC_BR3_OR3 + default 0x1 if ELBC_BR3_OR3 + +config OR3_AM + hex + default 0xffff8000 if OR3_AM_32_KBYTES && !BR3_MACHINE_SDRAM + default 0xffff0000 if OR3_AM_64_KBYTES + default 0xfffe0000 if OR3_AM_128_KBYTES + default 0xfffc0000 if OR3_AM_256_KBYTES + default 0xfff80000 if OR3_AM_512_KBYTES + default 0xfff00000 if OR3_AM_1_MBYTES + default 0xffe00000 if OR3_AM_2_MBYTES + default 0xffc00000 if OR3_AM_4_MBYTES + default 0xff800000 if OR3_AM_8_MBYTES + default 0xff000000 if OR3_AM_16_MBYTES + default 0xfe000000 if OR3_AM_32_MBYTES + default 0xfc000000 if OR3_AM_64_MBYTES + default 0xf8000000 if OR3_AM_128_MBYTES + default 0xf0000000 if OR3_AM_256_MBYTES + default 0xe0000000 if OR3_AM_512_MBYTES + default 0xc0000000 if OR3_AM_1_GBYTES + default 0x80000000 if OR3_AM_2_GBYTES + default 0x00000000 if OR3_AM_4_GBYTES + +config OR3_XAM + hex + default 0x0 if !OR3_XAM_SET + default 0x6000 if OR3_XAM_SET + +config OR3_BCTLD + hex + default 0x0 if OR3_BCTLD_ASSERTED + default 0x1000 if OR3_BCTLD_NOT_ASSERTED + +config OR3_BI + hex + default 0x0 if !BR3_MACHINE_UPM + default 0x0 if OR3_BI_BURSTSUPPORT + default 0x100 if OR3_BI_BURSTINHIBIT + +config OR3_COLS + hex + default 0x0 if !BR3_MACHINE_SDRAM + default 0x0 if OR3_COLS_7 + default 0x400 if OR3_COLS_8 + default 0x800 if OR3_COLS_9 + default 0xc00 if OR3_COLS_10 + default 0x1000 if OR3_COLS_11 + default 0x1400 if OR3_COLS_12 + default 0x1800 if OR3_COLS_13 + default 0x1c00 if OR3_COLS_14 + +config OR3_ROWS + hex + default 0x0 if !BR3_MACHINE_SDRAM + default 0x0 if OR3_ROWS_9 + default 0x40 if OR3_ROWS_10 + default 0x80 if OR3_ROWS_11 + default 0xc0 if OR3_ROWS_12 + default 0x100 if OR3_ROWS_13 + default 0x140 if OR3_ROWS_14 + default 0x180 if OR3_ROWS_15 + +config OR3_PMSEL + hex + default 0x0 if !BR3_MACHINE_SDRAM + default 0x0 if OR3_PMSEL_BTB + default 0x20 if OR3_PMSEL_KEPT_OPEN + +config OR3_SCY + hex + default 0x0 if !BR3_MACHINE_GPCM && !BR3_MACHINE_FCM + default 0x0 if OR3_SCY_0 + default 0x10 if OR3_SCY_1 + default 0x20 if OR3_SCY_2 + default 0x30 if OR3_SCY_3 + default 0x40 if OR3_SCY_4 + default 0x50 if OR3_SCY_5 + default 0x60 if OR3_SCY_6 + default 0x70 if OR3_SCY_7 + default 0x80 if OR3_SCY_8 + default 0x90 if OR3_SCY_9 + default 0xa0 if OR3_SCY_10 + default 0xb0 if OR3_SCY_11 + default 0xc0 if OR3_SCY_12 + default 0xd0 if OR3_SCY_13 + default 0xe0 if OR3_SCY_14 + default 0xf0 if OR3_SCY_15 + +config OR3_PGS + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_PGS_SMALL + default 0x400 if OR3_PGS_LARGE + +config OR3_CSCT + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_CSCT_1_CYCLE + default 0x0 if OR3_CSCT_2_CYCLE + default 0x200 if OR3_CSCT_4_CYCLE + default 0x200 if OR3_CSCT_8_CYCLE + +config OR3_CST + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_CST_COINCIDENT + default 0x100 if OR3_CST_QUARTER_CLOCK + default 0x0 if OR3_CST_HALF_CLOCK + default 0x100 if OR3_CST_ONE_CLOCK + +config OR3_CHT + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_CHT_HALF_CLOCK + default 0x80 if OR3_CHT_ONE_CLOCK + default 0x0 if OR3_CHT_ONE_HALF_CLOCK + default 0x80 if OR3_CHT_TWO_CLOCK + +config OR3_RST + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_RST_THREE_QUARTER_CLOCK + default 0x8 if OR3_RST_ONE_CLOCK + default 0x0 if OR3_RST_ONE_HALF_CLOCK + +config OR3_CSNT + hex + default 0x0 if !BR3_MACHINE_GPCM + default 0x0 if OR3_CSNT_NORMAL + default 0x800 if OR3_CSNT_EARLIER + +config OR3_ACS + hex + default 0x0 if !BR3_MACHINE_GPCM + default 0x0 if OR3_ACS_SAME_TIME + default 0x400 if OR3_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR3_ACS_HALF_CYCLE_EARLIER + +config OR3_XACS + hex + default 0x0 if !BR3_MACHINE_GPCM + default 0x0 if OR3_XACS_NORMAL + default 0x100 if OR3_XACS_EXTENDED + +config OR3_SETA + hex + default 0x0 if !BR3_MACHINE_GPCM + default 0x0 if OR3_SETA_INTERNAL + default 0x8 if OR3_SETA_EXTERNAL + +config OR3_TRLX + hex + default 0x0 if OR3_TRLX_NORMAL + default 0x4 if OR3_TRLX_RELAXED + +config OR3_EHTR + hex + default 0x0 if OR3_EHTR_NORMAL + default 0x2 if OR3_EHTR_1_CYCLE + default 0x0 if OR3_EHTR_4_CYCLE + default 0x2 if OR3_EHTR_8_CYCLE + +config OR3_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR3_EAD_NONE + default 0x1 if OR3_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 new file mode 100644 index 0000000000..0063dab962 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR4_OR4 + bool "ELBC BR4/OR4" + +if ELBC_BR4_OR4 + +config BR4_OR4_NAME + string "Identifier" + +config BR4_OR4_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR4_PORTSIZE_8BIT + bool "8-bit" + +config BR4_PORTSIZE_16BIT + depends on !BR4_MACHINE_FCM + bool "16-bit" + + +config BR4_PORTSIZE_32BIT + depends on !BR4_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR4_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR4_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR4_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR4_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR4_WRITE_PROTECT + bool "Write-protect" + +config BR4_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR4_MACHINE_GPCM + bool "GPCM" + +config BR4_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR4_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR4_MACHINE_UPMA + select BR4_MACHINE_UPM + bool "UPM (A)" + +config BR4_MACHINE_UPMB + select BR4_MACHINE_UPM + bool "UPM (B)" + +config BR4_MACHINE_UPMC + select BR4_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR4_ATOMIC_NONE + bool "No atomic operations" + +config BR4_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR4_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR4_MACHINE_GPCM || BR4_MACHINE_FCM || BR4_MACHINE_UPM || BR4_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR4_AM_32_KBYTES + depends on !BR4_MACHINE_SDRAM + bool "32 kb" + +config OR4_AM_64_KBYTES + bool "64 kb" + +config OR4_AM_128_KBYTES + bool "128 kb" + +config OR4_AM_256_KBYTES + bool "256 kb" + +config OR4_AM_512_KBYTES + bool "512 kb" + +config OR4_AM_1_MBYTES + bool "1 mb" + +config OR4_AM_2_MBYTES + bool "2 mb" + +config OR4_AM_4_MBYTES + bool "4 mb" + +config OR4_AM_8_MBYTES + bool "8 mb" + +config OR4_AM_16_MBYTES + bool "16 mb" + +config OR4_AM_32_MBYTES + bool "32 mb" + +config OR4_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR4_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR4_AM_256_MBYTES + bool "256 mb" + +config OR4_AM_512_MBYTES + depends on BR4_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR4_AM_1_GBYTES + bool "1 gb" + +config OR4_AM_2_GBYTES + depends on BR4_MACHINE_FCM + bool "2 gb" + +config OR4_AM_4_GBYTES + depends on BR4_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR4_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR4_BCTLD_ASSERTED + bool "Asserted" + +config OR4_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR4_MACHINE_GPCM || BR4_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR4_SCY_0 + bool "No wait states" + +config OR4_SCY_1 + bool "1 wait state" + +config OR4_SCY_2 + bool "2 wait states" + +config OR4_SCY_3 + bool "3 wait states" + +config OR4_SCY_4 + bool "4 wait states" + +config OR4_SCY_5 + bool "5 wait states" + +config OR4_SCY_6 + bool "6 wait states" + +config OR4_SCY_7 + bool "7 wait states" + +config OR4_SCY_8 + depends on BR4_MACHINE_GPCM + bool "8 wait states" + +config OR4_SCY_9 + depends on BR4_MACHINE_GPCM + bool "9 wait states" + +config OR4_SCY_10 + depends on BR4_MACHINE_GPCM + bool "10 wait states" + +config OR4_SCY_11 + depends on BR4_MACHINE_GPCM + bool "11 wait states" + +config OR4_SCY_12 + depends on BR4_MACHINE_GPCM + bool "12 wait states" + +config OR4_SCY_13 + depends on BR4_MACHINE_GPCM + bool "13 wait states" + +config OR4_SCY_14 + depends on BR4_MACHINE_GPCM + bool "14 wait states" + +config OR4_SCY_15 + depends on BR4_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR4_MACHINE_GPCM || BR4_MACHINE_FCM + +if BR4_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR4_CSNT_NORMAL + bool "Normal" + +config OR4_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR4_ACS_SAME_TIME + bool "At the same time" + +config OR4_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR4_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR4_XACS_NORMAL + bool "Normal" + +config OR4_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR4_SETA_INTERNAL + bool "Access is terminated internally" + +config OR4_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR4_MACHINE_GPCM + +if BR4_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR4_PGS_SMALL + bool "Small page device" + +config OR4_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR4_CSCT_1_CYCLE + depends on OR4_TRLX_NORMAL + bool "1 cycle" + +config OR4_CSCT_2_CYCLE + depends on OR4_TRLX_RELAXED + bool "2 cycles" + +config OR4_CSCT_4_CYCLE + depends on OR4_TRLX_NORMAL + bool "4 cycles" + +config OR4_CSCT_8_CYCLE + depends on OR4_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR4_CST_COINCIDENT + depends on OR4_TRLX_NORMAL + bool "Coincident with any command" + +config OR4_CST_QUARTER_CLOCK + depends on OR4_TRLX_NORMAL + bool "0.25 clocks after" + +config OR4_CST_HALF_CLOCK + depends on OR4_TRLX_RELAXED + bool "0.5 clocks after" + +config OR4_CST_ONE_CLOCK + depends on OR4_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR4_CHT_HALF_CLOCK + depends on OR4_TRLX_NORMAL + bool "0.5 clocks before" + +config OR4_CHT_ONE_CLOCK + depends on OR4_TRLX_NORMAL + bool "1 clock before" + +config OR4_CHT_ONE_HALF_CLOCK + depends on OR4_TRLX_RELAXED + bool "1.5 clocks before" + +config OR4_CHT_TWO_CLOCK + depends on OR4_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR4_RST_THREE_QUARTER_CLOCK + depends on OR4_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR4_RST_ONE_HALF_CLOCK + depends on OR4_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR4_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR4_MACHINE_FCM + +if BR4_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR4_BI_BURSTSUPPORT + bool "Support burst access" + +config OR4_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR4_MACHINE_UPM + +if BR4_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR4_COLS_7 + bool "7" + +config OR4_COLS_8 + bool "8" + +config OR4_COLS_9 + bool "9" + +config OR4_COLS_10 + bool "10" + +config OR4_COLS_11 + bool "11" + +config OR4_COLS_12 + bool "12" + +config OR4_COLS_13 + bool "13" + +config OR4_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR4_ROWS_9 + bool "9" + +config OR4_ROWS_10 + bool "10" + +config OR4_ROWS_11 + bool "11" + +config OR4_ROWS_12 + bool "12" + +config OR4_ROWS_13 + bool "13" + +config OR4_ROWS_14 + bool "14" + +config OR4_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR4_PMSEL_BTB + bool "Back-to-back" + +config OR4_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR4_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR4_TRLX_NORMAL + bool "Normal" + +config OR4_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR4_EHTR_NORMAL + depends on OR4_TRLX_NORMAL + bool "Normal" + +config OR4_EHTR_1_CYCLE + depends on OR4_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR4_EHTR_4_CYCLE + depends on OR4_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR4_EHTR_8_CYCLE + depends on OR4_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR4_EAD_NONE + bool "None" + +config OR4_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR4_OR4 + +config BR4_PORTSIZE + hex + default 0x800 if BR4_PORTSIZE_8BIT + default 0x1000 if BR4_PORTSIZE_16BIT + default 0x1800 if BR4_PORTSIZE_32BIT + +config BR4_ERRORCHECKING + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if BR4_ERRORCHECKING_DISABLED + default 0x200 if BR4_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR4_ERRORCHECKING_BOTH + +config BR4_WRITE_PROTECT_BIT + hex + default 0x0 if !BR4_WRITE_PROTECT + default 0x100 if BR4_WRITE_PROTECT + +config BR4_MACHINE + hex + default 0x0 if BR4_MACHINE_GPCM + default 0x20 if BR4_MACHINE_FCM + default 0x60 if BR4_MACHINE_SDRAM + default 0x80 if BR4_MACHINE_UPMA + default 0xa0 if BR4_MACHINE_UPMB + default 0xc0 if BR4_MACHINE_UPMC + +config BR4_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR4_ATOMIC_NONE + default 0x4 if BR4_ATOMIC_RAWA + default 0x8 if BR4_ATOMIC_WARA + +config BR4_VALID_BIT + hex + default 0x0 if !ELBC_BR4_OR4 + default 0x1 if ELBC_BR4_OR4 + +config OR4_AM + hex + default 0xffff8000 if OR4_AM_32_KBYTES && !BR4_MACHINE_SDRAM + default 0xffff0000 if OR4_AM_64_KBYTES + default 0xfffe0000 if OR4_AM_128_KBYTES + default 0xfffc0000 if OR4_AM_256_KBYTES + default 0xfff80000 if OR4_AM_512_KBYTES + default 0xfff00000 if OR4_AM_1_MBYTES + default 0xffe00000 if OR4_AM_2_MBYTES + default 0xffc00000 if OR4_AM_4_MBYTES + default 0xff800000 if OR4_AM_8_MBYTES + default 0xff000000 if OR4_AM_16_MBYTES + default 0xfe000000 if OR4_AM_32_MBYTES + default 0xfc000000 if OR4_AM_64_MBYTES + default 0xf8000000 if OR4_AM_128_MBYTES + default 0xf0000000 if OR4_AM_256_MBYTES + default 0xe0000000 if OR4_AM_512_MBYTES + default 0xc0000000 if OR4_AM_1_GBYTES + default 0x80000000 if OR4_AM_2_GBYTES + default 0x00000000 if OR4_AM_4_GBYTES + +config OR4_XAM + hex + default 0x0 if !OR4_XAM_SET + default 0x6000 if OR4_XAM_SET + +config OR4_BCTLD + hex + default 0x0 if OR4_BCTLD_ASSERTED + default 0x1000 if OR4_BCTLD_NOT_ASSERTED + +config OR4_BI + hex + default 0x0 if !BR4_MACHINE_UPM + default 0x0 if OR4_BI_BURSTSUPPORT + default 0x100 if OR4_BI_BURSTINHIBIT + +config OR4_COLS + hex + default 0x0 if !BR4_MACHINE_SDRAM + default 0x0 if OR4_COLS_7 + default 0x400 if OR4_COLS_8 + default 0x800 if OR4_COLS_9 + default 0xc00 if OR4_COLS_10 + default 0x1000 if OR4_COLS_11 + default 0x1400 if OR4_COLS_12 + default 0x1800 if OR4_COLS_13 + default 0x1c00 if OR4_COLS_14 + +config OR4_ROWS + hex + default 0x0 if !BR4_MACHINE_SDRAM + default 0x0 if OR4_ROWS_9 + default 0x40 if OR4_ROWS_10 + default 0x80 if OR4_ROWS_11 + default 0xc0 if OR4_ROWS_12 + default 0x100 if OR4_ROWS_13 + default 0x140 if OR4_ROWS_14 + default 0x180 if OR4_ROWS_15 + +config OR4_PMSEL + hex + default 0x0 if !BR4_MACHINE_SDRAM + default 0x0 if OR4_PMSEL_BTB + default 0x20 if OR4_PMSEL_KEPT_OPEN + +config OR4_SCY + hex + default 0x0 if !BR4_MACHINE_GPCM && !BR4_MACHINE_FCM + default 0x0 if OR4_SCY_0 + default 0x10 if OR4_SCY_1 + default 0x20 if OR4_SCY_2 + default 0x30 if OR4_SCY_3 + default 0x40 if OR4_SCY_4 + default 0x50 if OR4_SCY_5 + default 0x60 if OR4_SCY_6 + default 0x70 if OR4_SCY_7 + default 0x80 if OR4_SCY_8 + default 0x90 if OR4_SCY_9 + default 0xa0 if OR4_SCY_10 + default 0xb0 if OR4_SCY_11 + default 0xc0 if OR4_SCY_12 + default 0xd0 if OR4_SCY_13 + default 0xe0 if OR4_SCY_14 + default 0xf0 if OR4_SCY_15 + +config OR4_PGS + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_PGS_SMALL + default 0x400 if OR4_PGS_LARGE + +config OR4_CSCT + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_CSCT_1_CYCLE + default 0x0 if OR4_CSCT_2_CYCLE + default 0x200 if OR4_CSCT_4_CYCLE + default 0x200 if OR4_CSCT_8_CYCLE + +config OR4_CST + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_CST_COINCIDENT + default 0x100 if OR4_CST_QUARTER_CLOCK + default 0x0 if OR4_CST_HALF_CLOCK + default 0x100 if OR4_CST_ONE_CLOCK + +config OR4_CHT + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_CHT_HALF_CLOCK + default 0x80 if OR4_CHT_ONE_CLOCK + default 0x0 if OR4_CHT_ONE_HALF_CLOCK + default 0x80 if OR4_CHT_TWO_CLOCK + +config OR4_RST + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_RST_THREE_QUARTER_CLOCK + default 0x8 if OR4_RST_ONE_CLOCK + default 0x0 if OR4_RST_ONE_HALF_CLOCK + +config OR4_CSNT + hex + default 0x0 if !BR4_MACHINE_GPCM + default 0x0 if OR4_CSNT_NORMAL + default 0x800 if OR4_CSNT_EARLIER + +config OR4_ACS + hex + default 0x0 if !BR4_MACHINE_GPCM + default 0x0 if OR4_ACS_SAME_TIME + default 0x400 if OR4_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR4_ACS_HALF_CYCLE_EARLIER + +config OR4_XACS + hex + default 0x0 if !BR4_MACHINE_GPCM + default 0x0 if OR4_XACS_NORMAL + default 0x100 if OR4_XACS_EXTENDED + +config OR4_SETA + hex + default 0x0 if !BR4_MACHINE_GPCM + default 0x0 if OR4_SETA_INTERNAL + default 0x8 if OR4_SETA_EXTERNAL + +config OR4_TRLX + hex + default 0x0 if OR4_TRLX_NORMAL + default 0x4 if OR4_TRLX_RELAXED + +config OR4_EHTR + hex + default 0x0 if OR4_EHTR_NORMAL + default 0x2 if OR4_EHTR_1_CYCLE + default 0x0 if OR4_EHTR_4_CYCLE + default 0x2 if OR4_EHTR_8_CYCLE + +config OR4_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR4_EAD_NONE + default 0x1 if OR4_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h new file mode 100644 index 0000000000..245fe7c6fb --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h @@ -0,0 +1,186 @@ +#ifdef CONFIG_ELBC_BR0_OR0 +#define CONFIG_SYS_BR0_PRELIM (\ + CONFIG_BR0_OR0_BASE |\ + CONFIG_BR0_PORTSIZE |\ + CONFIG_BR0_ERRORCHECKING |\ + CONFIG_BR0_WRITE_PROTECT_BIT |\ + CONFIG_BR0_MACHINE |\ + CONFIG_BR0_ATOMIC |\ + CONFIG_BR0_VALID_BIT \ +) +#define CONFIG_SYS_OR0_PRELIM (\ + CONFIG_OR0_AM |\ + CONFIG_OR0_XAM |\ + CONFIG_OR0_BCTLD |\ + CONFIG_OR0_BI |\ + CONFIG_OR0_COLS |\ + CONFIG_OR0_ROWS |\ + CONFIG_OR0_PMSEL |\ + CONFIG_OR0_SCY |\ + CONFIG_OR0_PGS |\ + CONFIG_OR0_CSCT |\ + CONFIG_OR0_CST |\ + CONFIG_OR0_CHT |\ + CONFIG_OR0_RST |\ + CONFIG_OR0_CSNT |\ + CONFIG_OR0_ACS |\ + CONFIG_OR0_XACS |\ + CONFIG_OR0_SETA |\ + CONFIG_OR0_TRLX |\ + CONFIG_OR0_EHTR |\ + CONFIG_OR0_EAD \ +) +#endif /* CONFIG_ELBC_BR0_OR0 */ + +#ifdef CONFIG_ELBC_BR1_OR1 +#define CONFIG_SYS_BR1_PRELIM (\ + CONFIG_BR1_OR1_BASE |\ + CONFIG_BR1_PORTSIZE |\ + CONFIG_BR1_ERRORCHECKING |\ + CONFIG_BR1_WRITE_PROTECT_BIT |\ + CONFIG_BR1_MACHINE |\ + CONFIG_BR1_ATOMIC |\ + CONFIG_BR1_VALID_BIT \ +) +#define CONFIG_SYS_OR1_PRELIM (\ + CONFIG_OR1_AM |\ + CONFIG_OR1_XAM |\ + CONFIG_OR1_BCTLD |\ + CONFIG_OR1_BI |\ + CONFIG_OR1_COLS |\ + CONFIG_OR1_ROWS |\ + CONFIG_OR1_PMSEL |\ + CONFIG_OR1_SCY |\ + CONFIG_OR1_PGS |\ + CONFIG_OR1_CSCT |\ + CONFIG_OR1_CST |\ + CONFIG_OR1_CHT |\ + CONFIG_OR1_RST |\ + CONFIG_OR1_CSNT |\ + CONFIG_OR1_ACS |\ + CONFIG_OR1_XACS |\ + CONFIG_OR1_SETA |\ + CONFIG_OR1_TRLX |\ + CONFIG_OR1_EHTR |\ + CONFIG_OR1_EAD \ +) +#endif /* CONFIG_ELBC_BR1_OR1 */ + +#ifdef CONFIG_ELBC_BR2_OR2 +#define CONFIG_SYS_BR2_PRELIM (\ + CONFIG_BR2_OR2_BASE |\ + CONFIG_BR2_PORTSIZE |\ + CONFIG_BR2_ERRORCHECKING |\ + CONFIG_BR2_WRITE_PROTECT_BIT |\ + CONFIG_BR2_MACHINE |\ + CONFIG_BR2_ATOMIC |\ + CONFIG_BR2_VALID_BIT \ +) +#define CONFIG_SYS_OR2_PRELIM (\ + CONFIG_OR2_AM |\ + CONFIG_OR2_XAM |\ + CONFIG_OR2_BCTLD |\ + CONFIG_OR2_BI |\ + CONFIG_OR2_COLS |\ + CONFIG_OR2_ROWS |\ + CONFIG_OR2_PMSEL |\ + CONFIG_OR2_SCY |\ + CONFIG_OR2_PGS |\ + CONFIG_OR2_CSCT |\ + CONFIG_OR2_CST |\ + CONFIG_OR2_CHT |\ + CONFIG_OR2_RST |\ + CONFIG_OR2_CSNT |\ + CONFIG_OR2_ACS |\ + CONFIG_OR2_XACS |\ + CONFIG_OR2_SETA |\ + CONFIG_OR2_TRLX |\ + CONFIG_OR2_EHTR |\ + CONFIG_OR2_EAD \ +) +#endif /* CONFIG_ELBC_BR2_OR2 */ + +#ifdef CONFIG_ELBC_BR3_OR3 +#define CONFIG_SYS_BR3_PRELIM (\ + CONFIG_BR3_OR3_BASE |\ + CONFIG_BR3_PORTSIZE |\ + CONFIG_BR3_ERRORCHECKING |\ + CONFIG_BR3_WRITE_PROTECT_BIT |\ + CONFIG_BR3_MACHINE |\ + CONFIG_BR3_ATOMIC |\ + CONFIG_BR3_VALID_BIT \ +) +#define CONFIG_SYS_OR3_PRELIM (\ + CONFIG_OR3_AM |\ + CONFIG_OR3_XAM |\ + CONFIG_OR3_BCTLD |\ + CONFIG_OR3_BI |\ + CONFIG_OR3_COLS |\ + CONFIG_OR3_ROWS |\ + CONFIG_OR3_PMSEL |\ + CONFIG_OR3_SCY |\ + CONFIG_OR3_PGS |\ + CONFIG_OR3_CSCT |\ + CONFIG_OR3_CST |\ + CONFIG_OR3_CHT |\ + CONFIG_OR3_RST |\ + CONFIG_OR3_CSNT |\ + CONFIG_OR3_ACS |\ + CONFIG_OR3_XACS |\ + CONFIG_OR3_SETA |\ + CONFIG_OR3_TRLX |\ + CONFIG_OR3_EHTR |\ + CONFIG_OR3_EAD \ +) +#endif /* CONFIG_ELBC_BR3_OR3 */ + +#ifdef CONFIG_ELBC_BR4_OR4 +#define CONFIG_SYS_BR4_PRELIM (\ + CONFIG_BR4_OR4_BASE |\ + CONFIG_BR4_PORTSIZE |\ + CONFIG_BR4_ERRORCHECKING |\ + CONFIG_BR4_WRITE_PROTECT_BIT |\ + CONFIG_BR4_MACHINE |\ + CONFIG_BR4_ATOMIC |\ + CONFIG_BR4_VALID_BIT \ +) +#define CONFIG_SYS_OR4_PRELIM (\ + CONFIG_OR4_AM |\ + CONFIG_OR4_XAM |\ + CONFIG_OR4_BCTLD |\ + CONFIG_OR4_BI |\ + CONFIG_OR4_COLS |\ + CONFIG_OR4_ROWS |\ + CONFIG_OR4_PMSEL |\ + CONFIG_OR4_SCY |\ + CONFIG_OR4_PGS |\ + CONFIG_OR4_CSCT |\ + CONFIG_OR4_CST |\ + CONFIG_OR4_CHT |\ + CONFIG_OR4_RST |\ + CONFIG_OR4_CSNT |\ + CONFIG_OR4_ACS |\ + CONFIG_OR4_XACS |\ + CONFIG_OR4_SETA |\ + CONFIG_OR4_TRLX |\ + CONFIG_OR4_EHTR |\ + CONFIG_OR4_EAD \ +) +#endif /* CONFIG_ELBC_BR4_OR4 */ + +#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM +#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM +#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM +#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM +#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM +#endif diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 75eb65010e..b4e2fb1119 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -7,6 +7,7 @@ #include <mpc83xx.h> #include "lblaw/lblaw.h" +#include "elbc/elbc.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 13545fc6ad..c43732f7c5 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -6,6 +6,10 @@ #include <common.h> #include <asm/fsl_lbc.h> +#ifdef CONFIG_MPC83xx +#include "../mpc83xx/elbc/elbc.h" +#endif + #ifdef CONFIG_MPC85xx /* Boards should provide their own version of this if they use lbc sdram */ static void __lbc_sdram_init(void) diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index c4bec090be..62bcf23571 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -20,6 +20,7 @@ #endif #include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h" +#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 38c5d8d532..c38ac328d2 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -86,3 +86,41 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385_BASE" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 5783165e5d..1588adf3d6 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -103,3 +103,53 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_9=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_EHTR_1_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE2800000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="BCSR" +CONFIG_BR3_OR3_BASE=0xFA000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index 2395b8e397..2425256ee3 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -102,3 +102,53 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_9=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_EHTR_1_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE2800000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="BCSR" +CONFIG_BR3_OR3_BASE=0xFA000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index ce97914934..8ee257a54e 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -111,3 +111,53 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="NAND" +CONFIG_BR0_OR0_BASE=0xE2800000 +CONFIG_BR0_ERRORCHECKING_BOTH=y +CONFIG_BR0_MACHINE_FCM=y +CONFIG_BR0_PORTSIZE_8BIT=y +CONFIG_OR0_AM_32_KBYTES=y +CONFIG_OR0_SCY_1=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_CHT_TWO_CLOCK=y +CONFIG_OR0_CSCT_8_CYCLE=y +CONFIG_OR0_CST_ONE_CLOCK=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FLASH" +CONFIG_BR1_OR1_BASE=0xFE000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_8_MBYTES=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_9=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_EHTR_1_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="BCSR" +CONFIG_BR3_OR3_BASE=0xFA000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index 92d33b07db..baca3d799d 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -110,3 +110,53 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="NAND" +CONFIG_BR0_OR0_BASE=0xE2800000 +CONFIG_BR0_ERRORCHECKING_BOTH=y +CONFIG_BR0_MACHINE_FCM=y +CONFIG_BR0_PORTSIZE_8BIT=y +CONFIG_OR0_AM_32_KBYTES=y +CONFIG_OR0_SCY_1=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_CHT_TWO_CLOCK=y +CONFIG_OR0_CSCT_8_CYCLE=y +CONFIG_OR0_CST_ONE_CLOCK=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FLASH" +CONFIG_BR1_OR1_BASE=0xFE000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_8_MBYTES=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_9=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_EHTR_1_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="BCSR" +CONFIG_BR3_OR3_BASE=0xFA000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index b6e43b66aa..b9539893ff 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -109,3 +109,30 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 7243cf67f9..64e6f58f38 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -88,3 +88,17 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index 8cbc14022b..ffc82260ec 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -87,3 +87,56 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index 487d1d8544..911f62de65 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -107,3 +107,56 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index 10ea03422c..7dd02a95c9 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -107,3 +107,56 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index b1afa2fa47..3e3c82b2ef 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -104,3 +104,56 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index a9bb8a7713..4cfa01074d 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -86,3 +86,56 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index 28779bbeb7..a29d3268f7 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -73,3 +73,27 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xE2400000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index a157066968..e3058f0b5e 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -57,6 +57,33 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xF0000000 CONFIG_LBLAW2_NAME="SDRAM" CONFIG_LBLAW2_LENGTH_64_MBYTES=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xE2400000 +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="SDRAM" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_PORTSIZE_32BIT=y +CONFIG_BR2_MACHINE_SDRAM=y +CONFIG_OR2_COLS_9=y +CONFIG_OR2_ROWS_13=y +CONFIG_OR2_EAD_EXTRA=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index 588d9420f1..d45b6489b4 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -73,3 +73,27 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xE2400000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index a38edb5293..e3ca6811cc 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -76,3 +76,27 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_MPC8XXX_SPI=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xE2400000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index 844b897329..cf4ce83307 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -125,3 +125,50 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="VSC7385" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_SETA_EXTERNAL=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="LED" +CONFIG_BR2_OR2_BASE=0xF9000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_2_MBYTES=y +CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_9=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="CF" +CONFIG_BR3_OR3_BASE=0xF0000000 +CONFIG_BR3_MACHINE_UPMA=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BI_BURSTINHIBIT=y diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 91ed6686f8..e0185191bc 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -133,3 +133,50 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="VSC7385" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_SETA_EXTERNAL=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="LED" +CONFIG_BR2_OR2_BASE=0xF9000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_2_MBYTES=y +CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_9=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="CF" +CONFIG_BR3_OR3_BASE=0xF0000000 +CONFIG_BR3_MACHINE_UPMA=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BI_BURSTINHIBIT=y diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index cfa31c7230..0187f4f128 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -132,3 +132,50 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="VSC7385" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_SETA_EXTERNAL=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="LED" +CONFIG_BR2_OR2_BASE=0xF9000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_2_MBYTES=y +CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_9=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="CF" +CONFIG_BR3_OR3_BASE=0xF0000000 +CONFIG_BR3_MACHINE_UPMA=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BI_BURSTINHIBIT=y diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 4cc36a5c7f..b048d5b5d0 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -131,3 +131,44 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="NAND" +CONFIG_BR3_OR3_BASE=0xE0600000 +CONFIG_BR3_ERRORCHECKING_BOTH=y +CONFIG_BR3_MACHINE_FCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BCTLD_NOT_ASSERTED=y +CONFIG_OR3_RST_ONE_CLOCK=y +CONFIG_OR3_SCY_1=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_CHT_TWO_CLOCK=y +CONFIG_OR3_CST_ONE_CLOCK=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig index ba58e49ba2..9e2966b371 100644 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -84,3 +84,44 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="NAND" +CONFIG_BR3_OR3_BASE=0xE0600000 +CONFIG_BR3_ERRORCHECKING_BOTH=y +CONFIG_BR3_MACHINE_FCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BCTLD_NOT_ASSERTED=y +CONFIG_OR3_RST_ONE_CLOCK=y +CONFIG_OR3_SCY_1=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_CHT_TWO_CLOCK=y +CONFIG_OR3_CST_ONE_CLOCK=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index b3c1c87824..9256aac17c 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -107,3 +107,44 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="NAND" +CONFIG_BR3_OR3_BASE=0xE0600000 +CONFIG_BR3_ERRORCHECKING_BOTH=y +CONFIG_BR3_MACHINE_FCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BCTLD_NOT_ASSERTED=y +CONFIG_OR3_RST_ONE_CLOCK=y +CONFIG_OR3_SCY_1=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_CHT_TWO_CLOCK=y +CONFIG_OR3_CST_ONE_CLOCK=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index 07016936d6..95400114f2 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -90,3 +90,39 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_9=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_EHTR_1_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 59d591fa05..a8c69eb6bc 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -133,3 +133,39 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_9=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_EHTR_1_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index fdaded2970..49f0916663 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -134,3 +134,13 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0x80000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_32BIT=y +CONFIG_OR0_AM_1_GBYTES=y +CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 12721f8db4..e2ea71d11a 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -92,3 +92,24 @@ CONFIG_E1000=y CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFFC00000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_4_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="WINDOW1" +CONFIG_BR1_OR1_BASE=0xF0000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_32BIT=y +CONFIG_OR1_AM_256_KBYTES=y +CONFIG_OR1_SETA_EXTERNAL=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index f1aa24683c..7b17f602b6 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -89,3 +89,29 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 22689ef0ac..9a20a0d069 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -87,3 +87,29 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 168564606c..14104a441b 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -119,3 +119,48 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_MPC8XXX_SPI=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFF800000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_8BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_10=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE1000000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_PGS_LARGE=y +CONFIG_OR1_RST_ONE_CLOCK=y +CONFIG_OR1_SCY_4=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="MRAM" +CONFIG_BR2_OR2_BASE=0xE2000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_SCY_7=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="CPLD" +CONFIG_BR3_OR3_BASE=0xE3000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_SCY_1=y +CONFIG_OR3_TRLX_RELAXED=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 088dee63ba..6740c4c8a9 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -143,3 +143,45 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_BCH=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_64_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PAXE" +CONFIG_BR3_OR3_BASE=0xA0000000 +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_2=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_ELBC_BR4_OR4=y +CONFIG_BR4_OR4_NAME="BFTIC3" +CONFIG_BR4_OR4_BASE=0xB0000000 +CONFIG_BR4_PORTSIZE_8BIT=y +CONFIG_OR4_AM_256_MBYTES=y +CONFIG_OR4_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR4_CSNT_EARLIER=y +CONFIG_OR4_EAD_EXTRA=y +CONFIG_OR4_SCY_2=y +CONFIG_OR4_TRLX_RELAXED=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 64ea83fd12..182fa477f8 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -115,3 +115,35 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_64_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PAXE" +CONFIG_BR3_OR3_BASE=0xA0000000 +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_2=y +CONFIG_OR3_TRLX_RELAXED=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 3a88b6a027..678900d05c 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -130,3 +130,45 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_SCY_4=y +CONFIG_OR3_EHTR_NORMAL=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index c818d7e4a1..49780b4b19 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -116,3 +116,37 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 640e0c7c3c..9a57e43d78 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -120,3 +120,33 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_BCH=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_SCY_5=y +CONFIG_OR3_EHTR_NORMAL=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 81579c6b02..78f7de9899 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -130,3 +130,45 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_SCY_4=y +CONFIG_OR3_EHTR_NORMAL=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 709947b539..7256750ea0 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -133,3 +133,40 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_UPMA=y +CONFIG_BR2_PORTSIZE_16BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_SCY_3=y +CONFIG_OR3_TRLX_RELAXED=y diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index b44e04e1ae..ec2e30709c 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -78,3 +78,32 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFC000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_64_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_4=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="SJA1000" +CONFIG_BR1_OR1_BASE=0xFBFF0000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_EHTR_1_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="CPLD" +CONFIG_BR2_OR2_BASE=0xFBFF8000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_SCY_4=y +CONFIG_OR2_EHTR_1_CYCLE=y diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 6f407d56d5..453f85a0e3 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -89,3 +89,17 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFF800000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index 9c0b30f446..b304615630 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -89,3 +89,17 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFF800000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index 05361f76fc..4ec51af9f2 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -67,3 +67,17 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFF800000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 196c44470a..a806e9957f 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -91,3 +91,26 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index c407bed189..3687a28fc3 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -91,3 +91,26 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index 1128950ace..4231a431b8 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -91,3 +91,26 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index f0b2c44efb..afb991ce1e 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -91,3 +91,26 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 10a32178f1..2b16ceb524 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -131,3 +131,40 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_UPMA=y +CONFIG_BR2_PORTSIZE_16BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_SCY_3=y +CONFIG_OR3_TRLX_RELAXED=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 6fada9bdf7..07666c3b50 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -116,3 +116,37 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 1eb21e0e5a..627bf2febf 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -130,3 +130,48 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_SCY_2=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_4_CYCLE=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 1df5195e97..365c4ea858 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -95,3 +95,48 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0x61000000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_BCTLD_NOT_ASSERTED=y +CONFIG_OR1_RST_ONE_CLOCK=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="NVRAM" +CONFIG_BR2_OR2_BASE=0x60000000 +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_3=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="SRAM" +CONFIG_BR3_OR3_BASE=0x62000000 +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_32_MBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 9336dfac5c..072674cbeb 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -94,3 +94,24 @@ CONFIG_TSEC_ENET=y CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF8000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_128_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="WINDOW1" +CONFIG_BR1_OR1_BASE=0xF0000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_32BIT=y +CONFIG_OR1_AM_256_KBYTES=y +CONFIG_OR1_SETA_EXTERNAL=y diff --git a/drivers/mtd/nand/raw/fsl_elbc_spl.c b/drivers/mtd/nand/raw/fsl_elbc_spl.c index 30c3308940..099d86427c 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_spl.c +++ b/drivers/mtd/nand/raw/fsl_elbc_spl.c @@ -14,6 +14,10 @@ #include <asm/fsl_lbc.h> #include <nand.h> +#ifdef CONFIG_MPC83xx +#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h" +#endif + #define WINDOW_SIZE 8192 static void nand_wait(void) diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 185f6490d7..cd78836bcd 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -175,9 +175,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ /* 127 64KB sectors and 8 8KB top sectors per device */ @@ -191,9 +188,6 @@ */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* 0xFFFF8396 */ #ifdef CONFIG_VSC7385_ENET @@ -201,9 +195,6 @@ /* VSC7385 Base address on CS2 */ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -/* VSC7385_BASE */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) /* 0xFFFE09FF */ /* The flash address and size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE 0xFE7FE000 diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 40b0264dbe..93b553c905 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -219,14 +219,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) -/* NAND */ -#define CONFIG_SYS_BR0_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) - -/* FLASH */ -#define CONFIG_SYS_BR1_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) - /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM @@ -235,9 +227,6 @@ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ /* map at 0xFA000000 on LCS3 */ -/* BCSR */ -#define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Vitesse 7385 */ @@ -247,9 +236,6 @@ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -/* VSC7385 */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #endif diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 390ee4eb26..18e056e1b2 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -188,14 +188,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) -/* FLASH*/ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) - -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) - /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM @@ -204,9 +196,6 @@ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ /* map at 0xFA000000 on LCS3 */ -/* BCSR */ -#define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Vitesse 7385 */ #ifdef CONFIG_VSC7385_ENET @@ -215,9 +204,6 @@ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -/* VSC7385 */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #endif diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 97b66415c9..708829dae8 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -177,13 +177,7 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index fd884a1e65..c66e33a247 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -142,9 +142,6 @@ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 41b0223135..ed47bcd5b4 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -133,9 +133,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ @@ -148,9 +145,6 @@ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * Windows to access PIB via local bus @@ -163,17 +157,11 @@ * CS2 on Local Bus, to PIB */ -/* PIB1 */ -#define CONFIG_SYS_BR2_PRELIM (0xF8008000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * CS3 on Local Bus, to PIB */ -/* PIB2 */ -#define CONFIG_SYS_BR3_PRELIM (0xF8010000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * Serial Port diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 4cda1589b6..3e0907dae4 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -123,9 +123,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -148,9 +145,6 @@ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 7f906c38d8..e401c29d6b 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -123,10 +123,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -147,10 +143,6 @@ */ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) - #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ @@ -192,10 +184,6 @@ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 */ -/* SDRAM */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_SDRAM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_SDRAM_XAM | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) | OR_SDRAM_EAD) - /* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. * diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index e90d497f5e..cc62fc3213 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -211,9 +211,6 @@ boards, we say we have two, but don't display a message if we find only one. */ * BRx, ORx, LBLAWBARx, and LBLAWARx */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Vitesse 7385 */ @@ -221,18 +218,12 @@ boards, we say we have two, but don't display a message if we find only one. */ #ifdef CONFIG_VSC7385_ENET -/* VSC7385 */ -#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #endif #define CONFIG_SYS_LED_BASE 0xF9000000 -/* LED */ -#define CONFIG_SYS_BR2_PRELIM (0xF9000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Compact Flash */ @@ -240,9 +231,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_CF_BASE 0xF0000000 -/* CF */ -#define CONFIG_SYS_BR3_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_UPM_BI) #endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e569e63741..a244ae87a2 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -162,9 +162,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -178,9 +175,6 @@ */ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * NAND Flash on the Local Bus @@ -190,9 +184,6 @@ #define CONFIG_SYS_NAND_BASE 0xE0600000 -/* NAND */ -#define CONFIG_SYS_BR3_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST | OR_FCM_TRLX | OR_FCM_EHTR) /* * Serial Port diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index c1898a53a6..006279a58c 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -188,9 +188,6 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -204,9 +201,6 @@ */ #define CONFIG_SYS_NAND_BASE 0xE0600000 -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* Vitesse 7385 */ @@ -214,9 +208,6 @@ #ifdef CONFIG_VSC7385_ENET -/* VSC7385 */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #endif diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index c76df2847d..af03c03786 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -76,9 +76,6 @@ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0x80000000 | BR_MS_GPCM | BR_PS_32 | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_1GB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET) /* disable remaining mappings */ #define CONFIG_SYS_BR1_PRELIM 0x00000000 diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index a7eb5f5295..e9cfeae64d 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -70,15 +70,9 @@ #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFFC00000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_4MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 -/* WINDOW1 */ -#define CONFIG_SYS_BR1_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB | OR_GPCM_SETA) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 3fe72db188..9318e6252a 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -169,9 +169,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -185,9 +182,6 @@ #define CONFIG_SYS_FPGA0_BASE 0xE0600000 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ -/* FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 61f64ebbbc..d86dda18fb 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -142,9 +142,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 #define CONFIG_SYS_FLASH_SIZE 8 -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFF800000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_SCY_10 | OR_GPCM_EHTR_SET | OR_GPCM_TRLX_SET | OR_GPCM_CSNT | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 128 @@ -163,9 +160,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) #define NAND_CACHE_PAGES 64 -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE1000000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_4 | OR_FCM_TRLX | OR_FCM_EHTR | OR_FCM_RST) /* * MRAM setup @@ -175,9 +169,6 @@ #define CONFIG_SYS_OR_TIMING_MRAM -/* MRAM */ -#define CONFIG_SYS_BR2_PRELIM (0xE2000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_7 | OR_GPCM_TRLX_SET) /* * CPLD setup @@ -187,9 +178,6 @@ #define CONFIG_SYS_OR_TIMING_MRAM -/* CPLD */ -#define CONFIG_SYS_BR3_PRELIM (0xE3000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_SCY_1 | OR_GPCM_TRLX_SET) /* * HW-Watchdog diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 5027073d6e..ede8ae6ba5 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -108,9 +108,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -120,9 +117,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -336,9 +330,6 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256 -/* PAXE */ -#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * BFTIC3 on the local bus CS4 @@ -346,9 +337,6 @@ #define CONFIG_SYS_BFTIC3_BASE 0xB0000000 #define CONFIG_SYS_BFTIC3_SIZE 256 -/* BFTIC3 */ -#define CONFIG_SYS_BR4_PRELIM (0xB0000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR4_PRELIM (OR_AM_256MB| OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 84516bb9bb..728c9b199f 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -93,9 +93,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -105,9 +102,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -316,8 +310,5 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256 -/* PAXE */ -#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #endif /* CONFIG */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 678cb6a7cc..f39dbe05b7 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -351,16 +345,10 @@ * Configuration for C2 on the local bus */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) /* * Configuration for C3 on the local bus */ -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_4 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 3e2e425c34..19e415619a 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -345,8 +339,5 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) #endif /* __CONFIG_H */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index ed221e2301..fe4763ce8a 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -120,9 +120,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -132,9 +129,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -400,9 +394,6 @@ * */ -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) /* ethernet port connected to piggy (UEC2) */ #define CONFIG_HAS_ETH1 diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index c1ed71e2af..9302d35949 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -347,12 +341,6 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_4 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #endif /* __CONFIG_H */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 406b6e7824..06c5923ae1 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -112,9 +112,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -124,9 +121,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -389,13 +383,7 @@ * */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB) -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 31bf9971ab..cb7dabd932 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -179,9 +179,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFC000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_4 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 @@ -196,18 +193,12 @@ */ #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000 -/* SJA1000 */ -#define CONFIG_SYS_BR1_PRELIM (0xFBFF0000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_SCY_5 | OR_GPCM_EHTR_SET) /* * CPLD on Local Bus */ #define CONFIG_SYS_CPLD_BASE 0xFBFF8000 -/* CPLD */ -#define CONFIG_SYS_BR2_PRELIM (0xFBFF8000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | OR_GPCM_SCY_4 | OR_GPCM_EHTR_SET) /* * Serial Port diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 42a1e1682d..98770ca0a6 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -98,9 +98,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFF800000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ diff --git a/include/configs/strider.h b/include/configs/strider.h index 1519dad321..dd89ee8c81 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -167,9 +167,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -183,9 +180,6 @@ #define CONFIG_SYS_FPGA0_BASE 0xE0600000 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ -/* FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 6aacbc2077..a65b61bfbf 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -110,9 +110,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -122,9 +119,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -342,13 +336,7 @@ * */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB) -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index b11d49629a..6084e8af60 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -345,8 +339,5 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) #endif /* __CONFIG_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 1bff837198..86aec93ee9 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -347,13 +341,7 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 3a5bcf9c62..4c5dad9dc2 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -153,25 +153,13 @@ #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0x61000000 | BR_PS_8 | BR_DECC_CHK_GEN | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CHT | OR_FCM_SCY_2 | OR_FCM_RST | OR_FCM_TRLX) /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM -/* NVRAM */ -#define CONFIG_SYS_BR2_PRELIM (0x60000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) -/* SRAM */ -#define CONFIG_SYS_BR3_PRELIM (0x62000000 | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * Serial Port diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index dd8aae5117..9b9c1ff54e 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -70,15 +70,9 @@ #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF8000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 -/* WINDOW1 */ -#define CONFIG_SYS_BR1_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB | OR_GPCM_SETA) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ |