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-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c15
-rw-r--r--arch/powerpc/cpu/mpc85xx/interrupts.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/mp.c6
-rw-r--r--arch/powerpc/cpu/mpc85xx/p4080_ids.c8
-rw-r--r--arch/powerpc/cpu/mpc85xx/traps.c2
-rw-r--r--arch/powerpc/cpu/mpc8xxx/cpu.c8
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c1
-rw-r--r--arch/powerpc/include/asm/fsl_liodn.h8
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h10
-rw-r--r--arch/powerpc/include/asm/immap_86xx.h9
-rw-r--r--board/freescale/corenet_ds/corenet_ds.c47
-rw-r--r--board/freescale/corenet_ds/ddr.c18
-rw-r--r--board/freescale/p2020ds/ddr.c4
-rw-r--r--board/ve8313/ve8313.c2
-rw-r--r--common/fdt_support.c58
-rw-r--r--drivers/dma/fsl_dma.c8
-rw-r--r--include/configs/corenet_ds.h2
-rw-r--r--include/configs/ve8313.h1
20 files changed, 113 insertions, 100 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index f15d43c38c..3f80700711 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -74,7 +74,7 @@ int checkcpu (void)
puts("Unicore software on multiprocessor system!!\n"
"To enable mutlticore build define CONFIG_MP\n");
#endif
- volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
printf("CPU%d: ", pic->whoami);
} else {
puts("CPU: ");
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2c3be6dd09..27236a0bad 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -179,7 +179,7 @@ static void corenet_tb_init(void)
volatile ccsr_rcpm_t *rcpm =
(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
volatile ccsr_pic_t *pic =
- (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+ (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
u32 whoami = in_be32(&pic->whoami);
/* Enable the timebase register for this core */
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 8e7b827ffb..45403641cf 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -54,18 +54,19 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
if (reg) {
+ u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
+ val = cpu_to_fdt32(val);
if (*reg == id) {
- fdt_setprop_string(blob, off, "status", "okay");
+ fdt_setprop_string(blob, off, "status",
+ "okay");
} else {
- u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
- val = cpu_to_fdt32(val);
fdt_setprop_string(blob, off, "status",
"disabled");
- fdt_setprop_string(blob, off, "enable-method",
- "spin-table");
- fdt_setprop(blob, off, "cpu-release-addr",
- &val, sizeof(val));
}
+ fdt_setprop_string(blob, off, "enable-method",
+ "spin-table");
+ fdt_setprop(blob, off, "cpu-release-addr",
+ &val, sizeof(val));
} else {
printf ("cpu NULL\n");
}
diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c
index ac8c01ac15..a62b031774 100644
--- a/arch/powerpc/cpu/mpc85xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc85xx/interrupts.c
@@ -35,7 +35,7 @@
int interrupt_init_cpu(unsigned int *decrementer_count)
{
- ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR;
+ ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index e05257cf04..603baef1bd 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -38,7 +38,7 @@ u32 get_my_id()
int cpu_reset(int nr)
{
- volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
out_be32(&pic->pir, 1 << nr);
/* the dummy read works around an errata on early 85xx MP PICs */
(void)in_be32(&pic->pir);
@@ -207,7 +207,7 @@ static void plat_mp_up(unsigned long bootpg)
gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
- pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+ pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
@@ -272,7 +272,7 @@ static void plat_mp_up(unsigned long bootpg)
volatile u32 bpcr;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
u32 devdisr;
int timeout = 10;
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
index 3861146b8b..a6cfaa5971 100644
--- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
@@ -81,10 +81,10 @@ struct liodn_id_table fman2_liodn_tbl[] = {
#endif
struct liodn_id_table sec_liodn_tbl[] = {
- SET_SEC_JQ_LIODN_ENTRY(0, 146, 154),
- SET_SEC_JQ_LIODN_ENTRY(1, 147, 155),
- SET_SEC_JQ_LIODN_ENTRY(2, 178, 186),
- SET_SEC_JQ_LIODN_ENTRY(3, 179, 187),
+ SET_SEC_JR_LIODN_ENTRY(0, 146, 154),
+ SET_SEC_JR_LIODN_ENTRY(1, 147, 155),
+ SET_SEC_JR_LIODN_ENTRY(2, 178, 186),
+ SET_SEC_JR_LIODN_ENTRY(3, 179, 187),
SET_SEC_RTIC_LIODN_ENTRY(a, 144),
SET_SEC_RTIC_LIODN_ENTRY(b, 145),
SET_SEC_RTIC_LIODN_ENTRY(c, 176),
diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c
index 7e96664333..78007177a1 100644
--- a/arch/powerpc/cpu/mpc85xx/traps.c
+++ b/arch/powerpc/cpu/mpc85xx/traps.c
@@ -288,7 +288,7 @@ UnknownException(struct pt_regs *regs)
void
ExtIntException(struct pt_regs *regs)
{
- volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
uint vect;
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 97a94f4cd0..5b30fbdc96 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -110,13 +110,15 @@ struct cpu_type *identify_cpu(u32 ver)
}
int cpu_numcores() {
- ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR;
+ ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
struct cpu_type *cpu = gd->cpu;
/* better to query feature reporting register than just assume 1 */
+#define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00
+#define MPC8xxx_PICFRR_NCPU_SHIFT 8
if (cpu == &cpu_type_unknown)
- return ((in_be32(&pic->frr) & MPC85xx_PICFRR_NCPU_MASK) >>
- MPC85xx_PICFRR_NCPU_SHIFT) + 1;
+ return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
+ MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
return cpu->num_cores;
}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index dccb7aa14b..e82082e74c 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -613,6 +613,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
#if defined(CONFIG_FSL_DDR3)
md_en = popts->mirrored_dimm;
#endif
+ rcw_en = popts->registered_dimm_en;
qd_en = popts->quad_rank_present ? 1 : 0;
ddr->ddr_sdram_cfg_2 = (0
| ((frc_sr & 0x1) << 31)
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index acdc99aee5..4c17fe232e 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -115,11 +115,11 @@ extern void fdt_fixup_liodn(void *blob);
FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \
-#define SET_SEC_JQ_LIODN_ENTRY(jqNum, liodnA, liodnB) \
- SET_LIODN_ENTRY_2("fsl,sec4.0-job-queue", liodnA, liodnB,\
- offsetof(ccsr_sec_t, jqliodnr[jqNum].ls) + \
+#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \
+ SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\
+ offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jqNum)
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
/* This is a bit evil since we treat rtic param as both a string & hex value */
#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index c1382c8c5e..3dd2b7f53a 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -760,8 +760,6 @@ typedef struct ccsr_pic {
u32 eoi; /* End Of IRQ */
u8 res9[3916];
u32 frr; /* Feature Reporting */
-#define MPC85xx_PICFRR_NCPU_MASK 0x00001f00
-#define MPC85xx_PICFRR_NCPU_SHIFT 8
u8 res10[28];
u32 gcr; /* Global Configuration */
#define MPC85xx_PICGCR_RST 0x80000000
@@ -2065,7 +2063,7 @@ typedef struct ccsr_sec {
struct {
u32 ms; /* Job Ring LIODN Register, MS */
u32 ls; /* Job Ring LIODN Register, LS */
- } jqliodnr[4];
+ } jrliodnr[4];
u8 res2[0x30];
struct {
u32 ms; /* RTIC LIODN Register, MS */
@@ -2110,8 +2108,8 @@ typedef struct ccsr_sec {
#define SEC_CTPR_MS_AXI_LIODN 0x08000000
#define SEC_CTPR_MS_QI 0x02000000
#define SEC_RVID_MA 0x0f000000
-#define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000
-#define SEC_CHANUM_MS_JQNUM_SHIFT 28
+#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
+#define SEC_CHANUM_MS_JRNUM_SHIFT 28
#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
#define SEC_CHANUM_MS_DECONUM_SHIFT 24
#endif
@@ -2301,7 +2299,7 @@ typedef struct ccsr_pme {
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
-#define CONFIG_SYS_MPC85xx_PIC_ADDR \
+#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
#define CONFIG_SYS_MPC85xx_CPM_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
index 4bebb68565..4e60cbb7a8 100644
--- a/arch/powerpc/include/asm/immap_86xx.h
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -1250,12 +1250,15 @@ typedef struct immap {
extern immap_t *immr;
-#define CONFIG_SYS_MPC86xx_DDR_OFFSET (0x2000)
+#define CONFIG_SYS_MPC86xx_DDR_OFFSET 0x2000
#define CONFIG_SYS_MPC86xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET)
-#define CONFIG_SYS_MPC86xx_DDR2_OFFSET (0x6000)
+#define CONFIG_SYS_MPC86xx_DDR2_OFFSET 0x6000
#define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET)
-#define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000)
+#define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000
#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
+#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000
+#define CONFIG_SYS_MPC8xxx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET)
+
#define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000
#ifdef CONFIG_MPC8610
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index 3cdefb34ef..48d95d6a63 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -23,6 +23,7 @@
#include <common.h>
#include <command.h>
#include <netdev.h>
+#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
@@ -120,28 +121,6 @@ int board_early_init_r(void)
set_liodns();
setup_portals();
-#ifdef CONFIG_SRIO1
- if (is_serdes_configured(SRIO1)) {
- set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M,
- LAW_TRGT_IF_RIO_1);
- } else {
- printf (" SRIO1: disabled\n");
- }
-#else
- setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */
-#endif
-
-#ifdef CONFIG_SRIO2
- if (is_serdes_configured(SRIO2)) {
- set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M,
- LAW_TRGT_IF_RIO_2);
- } else {
- printf (" SRIO2: disabled\n");
- }
-#else
- setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */
-#endif
-
return 0;
}
@@ -164,10 +143,34 @@ static const char *serdes_clock_to_string(u32 clock)
int misc_init_r(void)
{
serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ __maybe_unused ccsr_gur_t *gur;
u32 actual[NUM_SRDS_BANKS];
unsigned int i;
u8 sw3;
+ gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_SRIO1
+ if (is_serdes_configured(SRIO1)) {
+ set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M,
+ LAW_TRGT_IF_RIO_1);
+ } else {
+ printf (" SRIO1: disabled\n");
+ }
+#else
+ setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */
+#endif
+
+#ifdef CONFIG_SRIO2
+ if (is_serdes_configured(SRIO2)) {
+ set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M,
+ LAW_TRGT_IF_RIO_2);
+ } else {
+ printf (" SRIO2: disabled\n");
+ }
+#else
+ setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */
+#endif
+
/* Warn if the expected SERDES reference clocks don't match the
* actual reference clocks. This needs to be done after calling
* p4080_erratum_serdes8(), since that function may modify the clocks.
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 82b2b4f550..18adf2f9c5 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -66,11 +66,19 @@ typedef struct {
* seem reliable, but errors will appear when memory intensive
* program is run. */
/* XXX: Single rank at 800 MHz is OK. */
-const board_specific_parameters_t board_specific_parameters[][20] = {
+const board_specific_parameters_t board_specific_parameters[][30] = {
{
/* memory controller 0 */
/* lo| hi| num| clk| cpo|wrdata|2T */
/* mhz| mhz|ranks|adjst| | delay| */
+ { 0, 333, 4, 6, 7, 3, 0},
+ {334, 400, 4, 6, 9, 3, 0},
+ {401, 549, 4, 6, 11, 3, 0},
+ {550, 680, 4, 1, 10, 5, 0},
+ {681, 850, 4, 1, 12, 5, 0},
+ {851, 1050, 4, 1, 12, 5, 0},
+ {1051, 1250, 4, 1, 15, 4, 0},
+ {1251, 1350, 4, 1, 15, 4, 0},
{ 0, 333, 2, 6, 7, 3, 0},
{334, 400, 2, 6, 9, 3, 0},
{401, 549, 2, 6, 11, 3, 0},
@@ -90,6 +98,14 @@ const board_specific_parameters_t board_specific_parameters[][20] = {
/* memory controller 1 */
/* lo| hi| num| clk| cpo|wrdata|2T */
/* mhz| mhz|ranks|adjst| | delay| */
+ { 0, 333, 4, 6, 7, 3, 0},
+ {334, 400, 4, 6, 9, 3, 0},
+ {401, 549, 4, 6, 11, 3, 0},
+ {550, 680, 4, 1, 10, 5, 0},
+ {681, 850, 4, 1, 12, 5, 0},
+ {851, 1050, 4, 1, 12, 5, 0},
+ {1051, 1250, 4, 1, 15, 4, 0},
+ {1251, 1350, 4, 1, 15, 4, 0},
{ 0, 333, 2, 6, 7, 3, 0},
{334, 400, 2, 6, 9, 3, 0},
{401, 549, 2, 6, 11, 3, 0},
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
index 30d640fa31..9a1b07554f 100644
--- a/board/freescale/p2020ds/ddr.c
+++ b/board/freescale/p2020ds/ddr.c
@@ -68,7 +68,7 @@ const board_specific_parameters_t board_specific_parameters[][20] = {
{550, 680, 1, 4, 0x1f, 3, 0},
{681, 850, 1, 4, 0x1f, 4, 0}
#else
- { 0, 850, 2, 4, 0x1f, 4, 0},
+ { 0, 850, 2, 6, 0x1f, 4, 0},
{ 0, 850, 1, 4, 0x1f, 4, 0}
#endif
},
@@ -120,7 +120,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
/* Write leveling override */
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xa;
- popts->wrlvl_start = 0x7;
+ popts->wrlvl_start = 0x8;
/* Rtt and Rtt_WR override */
popts->rtt_override = 1;
popts->rtt_override_value = DDR3_RTT_120_OHM;
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index 8ba1b193a4..2272ff0c34 100644
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -101,7 +101,7 @@ static long fixed_sdram(void)
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile fsl_lbus_t *lbc = &im->lbus;
+ volatile fsl_lbc_t *lbc = &im->im_lbc;
u32 msize;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 33336be062..aef4fe23e0 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -874,35 +874,6 @@ static inline u64 of_read_number(const __be32 *cell, int size)
return r;
}
-static int of_n_cells(const void *blob, int nodeoffset, const char *name)
-{
- int np;
- const int *ip;
-
- do {
- np = fdt_parent_offset(blob, nodeoffset);
-
- if (np >= 0)
- nodeoffset = np;
- ip = (int *)fdt_getprop(blob, nodeoffset, name, NULL);
- if (ip)
- return be32_to_cpup(ip);
- } while (np >= 0);
-
- /* No #<NAME>-cells property for the root node */
- return 1;
-}
-
-int of_n_addr_cells(const void *blob, int nodeoffset)
-{
- return of_n_cells(blob, nodeoffset, "#address-cells");
-}
-
-int of_n_size_cells(const void *blob, int nodeoffset)
-{
- return of_n_cells(blob, nodeoffset, "#size-cells");
-}
-
#define PRu64 "%llx"
/* Max address size we deal with */
@@ -928,7 +899,7 @@ static void of_dump_addr(const char *s, const u32 *addr, int na) { }
struct of_bus {
const char *name;
const char *addresses;
- void (*count_cells)(void *blob, int offset,
+ void (*count_cells)(void *blob, int parentoffset,
int *addrc, int *sizec);
u64 (*map)(u32 *addr, const u32 *range,
int na, int ns, int pna);
@@ -936,13 +907,26 @@ struct of_bus {
};
/* Default translator (generic bus) */
-static void of_bus_default_count_cells(void *blob, int offset,
+static void of_bus_default_count_cells(void *blob, int parentoffset,
int *addrc, int *sizec)
{
- if (addrc)
- *addrc = of_n_addr_cells(blob, offset);
- if (sizec)
- *sizec = of_n_size_cells(blob, offset);
+ const u32 *prop;
+
+ if (addrc) {
+ prop = fdt_getprop(blob, parentoffset, "#address-cells", NULL);
+ if (prop)
+ *addrc = be32_to_cpup(prop);
+ else
+ *addrc = 2;
+ }
+
+ if (sizec) {
+ prop = fdt_getprop(blob, parentoffset, "#size-cells", NULL);
+ if (prop)
+ *sizec = be32_to_cpup(prop);
+ else
+ *sizec = 1;
+ }
}
static u64 of_bus_default_map(u32 *addr, const u32 *range,
@@ -1068,7 +1052,7 @@ u64 __of_translate_address(void *blob, int node_offset, const u32 *in_addr,
bus = &of_busses[0];
/* Cound address cells & copy address locally */
- bus->count_cells(blob, node_offset, &na, &ns);
+ bus->count_cells(blob, parent, &na, &ns);
if (!OF_CHECK_COUNTS(na, ns)) {
printf("%s: Bad cell count for %s\n", __FUNCTION__,
fdt_get_name(blob, node_offset, NULL));
@@ -1095,7 +1079,7 @@ u64 __of_translate_address(void *blob, int node_offset, const u32 *in_addr,
/* Get new parent bus and counts */
pbus = &of_busses[0];
- pbus->count_cells(blob, node_offset, &pna, &pns);
+ pbus->count_cells(blob, parent, &pna, &pns);
if (!OF_CHECK_COUNTS(pna, pns)) {
printf("%s: Bad cell count for %s\n", __FUNCTION__,
fdt_get_name(blob, node_offset, NULL));
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index df33e7a3ee..09c18c1929 100644
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -114,8 +114,12 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
while (count) {
xfer_size = MIN(FSL_DMA_MAX_SIZE, count);
- out_dma32(&dma->dar, (uint) dest);
- out_dma32(&dma->sar, (uint) src);
+ out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF));
+ out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF));
+ out_dma32(&dma->satr,
+ in_dma32(&dma->satr) | (u32)((u64)src >> 32));
+ out_dma32(&dma->datr,
+ in_dma32(&dma->datr) | (u32)((u64)dest >> 32));
out_dma32(&dma->bcr, xfer_size);
dma_sync();
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index dd609da8f0..3dcee85d8e 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -124,7 +124,7 @@
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
#define CONFIG_FSL_DDR3
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 1589913a5e..56d24f9014 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -39,6 +39,7 @@
#define CONFIG_VE8313 1
#define CONFIG_PCI 1
+#define CONFIG_FSL_ELBC 1
#define CONFIG_BOARD_EARLY_INIT_F 1
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-03 04:15:32 +0000