diff options
| -rw-r--r-- | arch/arm/mach-rockchip/rk3288-board.c | 35 | ||||
| -rw-r--r-- | configs/chromebook_jerry_defconfig | 1 |
2 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 18fd0dcd207..a354d992da7 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -309,3 +309,38 @@ U_BOOT_CMD( "display information about clocks", "" ); + +#define GRF_SOC_CON2 0xff77024c + +int board_early_init_f(void) +{ + struct udevice *pinctrl; + struct udevice *dev; + int ret; + + /* + * This init is done in SPL, but when chain-loading U-Boot SPL will + * have been skipped. Allow the clock driver to check if it needs + * setting up. + */ + ret = rockchip_get_clk(&dev); + if (ret) { + debug("CLK init failed: %d\n", ret); + return ret; + } + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + return ret; + } + + /* Enable debug UART */ + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); + if (ret) { + debug("%s: Failed to set up console UART\n", __func__); + return ret; + } + rk_setreg(GRF_SOC_CON2, 1 << 0); + + return 0; +} diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 6fc0dcc023f..bb880585e14 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry" CONFIG_SILENT_CONSOLE=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_CMD_IMLS is not set |