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-rw-r--r--arch/arm/cpu/armv7/tegra3/warmboot_avp.c2
-rw-r--r--arch/arm/include/asm/arch-tegra/clk_rst.h1
-rw-r--r--board/chromebook-x86/coreboot/config.mk3
-rw-r--r--board/nvidia/seaboard/chromeos.dtsi2
-rw-r--r--drivers/tpm/generic_lpc_tpm.c85
-rw-r--r--include/configs/coreboot.h16
-rw-r--r--include/configs/seaboard.h3
-rw-r--r--lib/chromeos/crossystem_data.c4
8 files changed, 99 insertions, 17 deletions
diff --git a/arch/arm/cpu/armv7/tegra3/warmboot_avp.c b/arch/arm/cpu/armv7/tegra3/warmboot_avp.c
index 02d320aed75..5281e8f86fd 100644
--- a/arch/arm/cpu/armv7/tegra3/warmboot_avp.c
+++ b/arch/arm/cpu/armv7/tegra3/warmboot_avp.c
@@ -81,7 +81,7 @@ void wb_start(void)
reg = SCLK_SWAKE_FIQ_SRC_CLKM | SCLK_SWAKE_IRQ_SRC_CLKM |
SCLK_SWAKE_RUN_SRC_CLKM | SCLK_SWAKE_IDLE_SRC_CLKM |
- SCLK_SYS_CPU_STATE_RUN;
+ (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
writel(reg, &clkrst->crc_sclk_brst_pol);
/* Update PLLP output dividers for 408 MHz operation */
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index 3233d3b9d0d..d170b3c7237 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -275,7 +275,6 @@ enum {
#define SUPER_CDIV_ENB (1 << 31)
/* CRC_SCLK_BURST_POLICY_0 28h */
-#define SCLK_SYS_CPU_STATE_RUN (2 << 28)
#define SCLK_SWAKE_FIQ_SRC_CLKM (0 << 12)
#define SCLK_SWAKE_IRQ_SRC_CLKM (0 << 8)
#define SCLK_SWAKE_RUN_SRC_CLKM (0 << 4)
diff --git a/board/chromebook-x86/coreboot/config.mk b/board/chromebook-x86/coreboot/config.mk
index 857ee8c4b92..627d4cfaf25 100644
--- a/board/chromebook-x86/coreboot/config.mk
+++ b/board/chromebook-x86/coreboot/config.mk
@@ -36,3 +36,6 @@
HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
LD := $(LD).bfd
+ifdef BUILD_FACTORY_IMAGE
+PLATFORM_CPPFLAGS += -DFACTORY_IMAGE
+endif
diff --git a/board/nvidia/seaboard/chromeos.dtsi b/board/nvidia/seaboard/chromeos.dtsi
index 0088121556e..438af878249 100644
--- a/board/nvidia/seaboard/chromeos.dtsi
+++ b/board/nvidia/seaboard/chromeos.dtsi
@@ -12,7 +12,7 @@
chromeos-config {
twostop; /* Two-stop boot */
twostop-optional; /* One-stop optimization enabled */
- textbase = <0xe08000>; /* Address where U-Boot loads */
+ textbase = <0x108000>; /* Address where U-Boot loads */
/*
* Device and offset for second-stage firmware, in SPI for now
diff --git a/drivers/tpm/generic_lpc_tpm.c b/drivers/tpm/generic_lpc_tpm.c
index 6600f7600a7..323238e0c3c 100644
--- a/drivers/tpm/generic_lpc_tpm.c
+++ b/drivers/tpm/generic_lpc_tpm.c
@@ -102,13 +102,31 @@ struct vendor_name {
struct device_name* dev_names;
};
+static struct device_name atmel_devices[] = {
+ {0x3204, "AT97SC3204"},
+ {0xffff}
+};
+
static struct device_name infineon_devices[] = {
- {0xb, "SLB9635 TT 1.2"},
- {0}
+ {0x000b, "SLB9635 TT 1.2"},
+ {0xffff}
+};
+
+static struct device_name nuvoton_devices[] = {
+ {0x00fe, "NPCT420AA V2"},
+ {0xffff}
+};
+
+static struct device_name stmicro_devices[] = {
+ {0x0000, "ST33ZP24" },
+ {0xffff}
};
static const struct vendor_name vendor_names[] = {
+ {0x1114, "Atmel", atmel_devices},
{0x15d1, "Infineon", infineon_devices},
+ {0x1050, "Nuvoton", nuvoton_devices},
+ {0x104a, "ST Microelectronics", stmicro_devices},
};
/*
@@ -183,6 +201,44 @@ static u32 tis_wait_reg(u8 reg, u8 locality, u8 mask, u8 expected)
}
/*
+ * PC Client Specific TPM Interface Specification section 11.2.12:
+ *
+ * Software must be prepared to send two writes of a "1" to command ready
+ * field: the first to indicate successful read of all the data, thus
+ * clearing the data from the ReadFIFO and freeing the TPM's resources,
+ * and the second to indicate to the TPM it is about to send a new command.
+ *
+ * In practice not all TPMs behave the same so it is necessary to be
+ * flexible when trying to set command ready.
+ *
+ * Returns 0 on success if the TPM is ready for transactions.
+ * Returns TPM_TIMEOUT_ERR if the command ready bit does not get set.
+ */
+static int tis_command_ready(u8 locality)
+{
+ u32 status;
+
+ /* 1st attempt to set command ready */
+ tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS);
+
+ /* Wait for response */
+ status = tpm_read(locality, TIS_REG_STS);
+
+ /* Check if command ready is set yet */
+ if (status & TIS_STS_COMMAND_READY)
+ return 0;
+
+ /* 2nd attempt to set command ready */
+ tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS);
+
+ /* Wait for command ready to get set */
+ status = tis_wait_reg(TIS_REG_STS, locality,
+ TIS_STS_COMMAND_READY, TIS_STS_COMMAND_READY);
+
+ return (status == TPM_TIMEOUT_ERR) ? TPM_TIMEOUT_ERR : 0;
+}
+
+/*
* Probe the TPM device and try determining its manufacturer/device name.
*
* Returns 0 on success (the device is found or was found during an earlier
@@ -190,15 +246,17 @@ static u32 tis_wait_reg(u8 reg, u8 locality, u8 mask, u8 expected)
*/
static u32 tis_probe(void)
{
- u32 didvid = tpm_read(0, TIS_REG_DID_VID);
- int i;
const char *device_name = "unknown";
const char *vendor_name = device_name;
+ struct device_name *dev;
+ u32 didvid;
u16 vid, did;
+ int i;
if (vendor_dev_id)
return 0; /* Already probed. */
+ didvid = tpm_read(0, TIS_REG_DID_VID);
if (!didvid || (didvid == 0xffffffff)) {
printf("%s: No TPM device found\n", __FUNCTION__);
return TPM_DRIVER_ERR;
@@ -213,11 +271,13 @@ static u32 tis_probe(void)
u16 known_did;
if (vid == vendor_names[i].vendor_id) {
vendor_name = vendor_names[i].vendor_name;
+ } else {
+ continue;
}
- while ((known_did = vendor_names[i].dev_names[j].dev_id) != 0) {
+ dev = &vendor_names[i].dev_names[j];
+ while ((known_did = dev->dev_id) != 0xffff) {
if (known_did == did) {
- device_name =
- vendor_names[i].dev_names[j].dev_name;
+ device_name = dev->dev_name;
break;
}
j++;
@@ -225,7 +285,7 @@ static u32 tis_probe(void)
break;
}
/* this will have to be converted into debug printout */
- TPM_DEBUG("Found TPM %s by %s\n", device_name, vendor_name);
+ printf("Found TPM %s by %s\n", device_name, vendor_name);
return 0;
}
@@ -421,7 +481,8 @@ static u32 tis_readresponse(u8 *buffer, u32 *len)
}
/* Tell the TPM that we are done. */
- tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS);
+ if (tis_command_ready(locality) == TPM_TIMEOUT_ERR)
+ return TPM_DRIVER_ERR;
*len = offset;
return 0;
@@ -467,7 +528,11 @@ int tis_open(void)
return TPM_DRIVER_ERR;
}
- tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS);
+ /* Certain TPMs seem to need some delay here or they hang... */
+ udelay(10);
+
+ if (tis_command_ready(locality) == TPM_TIMEOUT_ERR)
+ return TPM_DRIVER_ERR;
return 0;
}
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index fd2c0ccf9fb..939c79a7ffe 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -33,10 +33,19 @@
*/
#define CONFIG_SYS_COREBOOT
#define CONFIG_SHOW_BOOT_PROGRESS
-#define BUILD_CMD_LINE_STUFF 0
#define BUILD_IDE_STUFF 0
-#define BUILD_NETWORK_STUFF 0
-#define BUILD_PART_FS_STUFF 0
+
+#ifdef FACTORY_IMAGE
+#define BUILD_CMD_LINE_STUFF 1
+#define BUILD_NETWORK_STUFF 1
+#define BUILD_PART_FS_STUFF 1
+#define CONFIG_BOOTDELAY -1
+#else
+#define BUILD_CMD_LINE_STUFF 0
+#define BUILD_NETWORK_STUFF 0
+#define BUILD_PART_FS_STUFF 0
+#define CONFIG_BOOTDELAY 0
+#endif
/* FDT support */
#define CONFIG_OF_LIBFDT /* Device tree support */
@@ -333,7 +342,6 @@
/* Boot options */
-#define CONFIG_BOOTDELAY 0 /* -1 to disable auto boot */
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTARGS ""
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 5e68faca3fd..223beaea771 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -38,6 +38,9 @@
#include "tegra2-common.h"
+/* So our flasher can verify that all is well */
+#define CONFIG_CRC32_VERIFY
+
#ifndef CONFIG_OF_CONTROL
/* Things in here are defined by the device tree now. Let it grow! */
diff --git a/lib/chromeos/crossystem_data.c b/lib/chromeos/crossystem_data.c
index df387c1484c..f719a29fee9 100644
--- a/lib/chromeos/crossystem_data.c
+++ b/lib/chromeos/crossystem_data.c
@@ -305,7 +305,11 @@ int crossystem_data_update_acpi(crossystem_data_t *cdata)
len = min(ID_LEN, sizeof(acpi_table->vbt6));
memcpy(acpi_table->vbt6, cdata->readonly_firmware_id, len);
+#ifdef FACTORY_IMAGE
+ acpi_table->vbt7 = 3; /* '3' means 'netboot' to crossystem */
+#else
acpi_table->vbt7 = cdata->firmware_type;
+#endif
acpi_table->vbt8 = RECOVERY_REASON_NONE;
acpi_table->vbt9 = cdata->fmap_offset;