diff options
| -rw-r--r-- | arch/arm/cpu/armv7/tegra2/Makefile | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra2/warmboot.c | 36 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra2/warmboot_avp.S | 402 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra2/warmboot_avp.c | 313 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra2/warmboot_avp.h | 185 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra2/flow.h | 36 |
6 files changed, 420 insertions, 556 deletions
diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile index f9b81a4208..5812da6cac 100644 --- a/arch/arm/cpu/armv7/tegra2/Makefile +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -25,8 +25,10 @@ # The AVP is ARMv4T architecture so we must use special compiler # flags for any files it might use. + CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t +CFLAGS_arch/arm/cpu/armv7/tegra2/warmboot_avp.o += -march=armv4t include $(TOPDIR)/config.mk @@ -36,8 +38,8 @@ SOBJS-y := lowlevel_init.o COBJS-y := ap20.o board.o clock.o display.o pinmux.o power.o pwfm.o \ sys_info.o timer.o -SOBJS-$(CONFIG_TEGRA2_LP0) += warmboot_avp.o COBJS-$(CONFIG_TEGRA2_LP0) += warmboot.o +COBJS-$(CONFIG_TEGRA2_LP0) += warmboot_avp.o SOBJS := $(SOBJS-y) COBJS := $(COBJS-y) diff --git a/arch/arm/cpu/armv7/tegra2/warmboot.c b/arch/arm/cpu/armv7/tegra2/warmboot.c index dfa51e4aec..07f3c8514d 100644 --- a/arch/arm/cpu/armv7/tegra2/warmboot.c +++ b/arch/arm/cpu/armv7/tegra2/warmboot.c @@ -356,9 +356,7 @@ static int sign_wb_code(u32 start, u32 length, int use_zero_key) int warmboot_prepare_code(u32 seg_address, u32 seg_length) { int err = 0; - u32 start; /* start of the actual code */ u32 length; /* length of the signed/encrypt code */ - struct wb_header *src_header; /* Pointer to src WB header */ struct wb_header *dst_header; /* Pointer to dest WB header */ int is_encrypted; /* Segment is encrypted */ int is_signed; /* Segment is signed */ @@ -368,8 +366,7 @@ int warmboot_prepare_code(u32 seg_address, u32 seg_length) determine_crypto_options(&is_encrypted, &is_signed, &use_zero_key); /* Get the actual code limits. */ - start = (u32)wb_start; - length = roundup(((u32)wb_end - start), 16); + length = roundup(((u32)wb_end - (u32)wb_start), 16); /* * The region specified by seg_address must not be in IRAM and must be @@ -387,21 +384,20 @@ int warmboot_prepare_code(u32 seg_address, u32 seg_length) goto fail; } - /* Will the code fit? */ - if (seg_length < length) { + /* Will the code fit? (destination includes wb_header + wb code) */ + if (seg_length < (length + sizeof(struct wb_header))) { err = -EINVAL; goto fail; } - /* Get a pointers to the source and destination region header. */ - src_header = (struct wb_header *)start; dst_header = (struct wb_header *)seg_address; + memset((char *)dst_header, 0, sizeof(struct wb_header)); /* Populate the random_aes_block as requested. */ { - u32 *aes_block = (u32 *)&(src_header->random_aes_block); + u32 *aes_block = (u32 *)&(dst_header->random_aes_block); u32 *end = (u32 *)(((u32)aes_block) + - sizeof(src_header->random_aes_block)); + sizeof(dst_header->random_aes_block)); do { #if defined(RANDOM_AES_BLOCK_IS_RANDOM) @@ -419,11 +415,11 @@ int warmboot_prepare_code(u32 seg_address, u32 seg_length) } /* Populate the header. */ - src_header->length_in_secure = length; - src_header->length_secure = length; - src_header->destination = AP20_WB_RUN_ADDRESS; - src_header->entry_point = AP20_WB_RUN_ADDRESS; - src_header->code_length = length - sizeof(struct wb_header); + dst_header->length_in_secure = length + sizeof(struct wb_header); + dst_header->length_secure = length + sizeof(struct wb_header); + dst_header->destination = AP20_WB_RUN_ADDRESS; + dst_header->entry_point = AP20_WB_RUN_ADDRESS; + dst_header->code_length = length; if (is_encrypted) { printf("!!!! Encryption is not supported !!!!\n"); @@ -431,14 +427,12 @@ int warmboot_prepare_code(u32 seg_address, u32 seg_length) err = -EACCES; goto fail; } else - /* No, just copy the code directly. */ - memcpy(dst_header, src_header, length); - - /* Clear the signature in the destination code segment. */ - memset(&(dst_header->hash), 0, sizeof(dst_header->hash)); + /* copy the wb code directly following dst_header. */ + memcpy((char *)(dst_header+1), (char *)wb_start, length); if (is_signed) - err = sign_wb_code(seg_address, length, use_zero_key); + err = sign_wb_code(seg_address, dst_header->length_in_secure, + use_zero_key); fail: if (err) diff --git a/arch/arm/cpu/armv7/tegra2/warmboot_avp.S b/arch/arm/cpu/armv7/tegra2/warmboot_avp.S deleted file mode 100644 index 3f712acb7d..0000000000 --- a/arch/arm/cpu/armv7/tegra2/warmboot_avp.S +++ /dev/null @@ -1,402 +0,0 @@ -/* - * (C) Copyright 2010 - 2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <asm/arch/tegra2.h> -#include "warmboot_avp.h" - -/* Set non-zero to skip resetting CoreSight */ -#define DEBUG_DO_NOT_RESET_CORESIGHT 0 - - .section .text - .align 4 - -/* ------------------------------------------------------ - * void wb_start(void) - * - * Input: - * - * Output: - * None - * - * Registers Used: - * ALL - * - * Description: - * This function restarts the CPU and then waits for the AVP driver to - * tell it where to transfer control to finish restoration of the AVP state. - * --------------------------------------------------------------------------- - */ - - .globl wb_start -wb_start: - - .word 0, 0, 0, 0 - .word 0, 0, 0, 0 - .word 0, 0, 0, 0 - .word 0, 0, 0, 0 - -start: - ldr r0, =NV_PA_APB_MISC_BASE /* R0 = MISC PA base address */ - ldr r1, =APB_MISC_PP_CONFIG_CTL_JTAG_ENABLE \ - | APB_MISC_PP_CONFIG_CTL_TBE_ENABLE - str r1, [r0, #APB_MISC_PP_CONFIG_CTL_OFFSET] - - /* ----------------------------------------------------------------- - * Load up the base addresses for the register blocks. - * ----------------------------------------------------------------- - */ - ldr r5, =NV_PA_PMC_BASE /* R5 = PMC PA base address */ - ldr r6, =NV_PA_FLOW_BASE /* R6 = FLOW PA base address */ - ldr r7, =NV_PA_TMRUS_BASE /* R7 = TIMERUS PA base address */ - ldr r8, =NV_PA_CLK_RST_BASE /* R8 = CLK PA base address */ - ldr r9, =NV_PA_EVP_BASE /* R9 = EVP PA base address */ - ldr r10,=NV_PA_CSITE_BASE /* R10 = CSITE base address */ - - /* ----------------------------------------------------------------- - * Are we running where we're supposed to be? - * ----------------------------------------------------------------- - */ - - ldr r0, =AP20_WB_RUN_ADDRESS /* R0 = expected load address */ - add r1, pc, #here-(.+8) /* R1 = &here */ - -here: - sub r1, r1, #(here-start) /* R1 = actual load address */ - ldr r2, =NV_PA_PG_UP_BASE /* R2 = PG PA base address */ - ldr r3, [r2, #PG_UP_TAG_OFFSET] /* R3 = processor tag */ - ldr r2, =PG_UP_TAG_AVP /* R2 = AVP processor tag */ - cmp r0, r1 /* Addresses match? */ - cmpeq r2, r3 /* Processor tags match? */ - bne do_reset /* No -- reset the chip */ - - - /* ----------------------------------------------------------------- - * Get a snapshot of the Usec count. This is a good indicator of - * the overhead of BOOTROM after a wake-up event. - * ----------------------------------------------------------------- - */ - - ldr r11, [r7, #TIMERUS_CNTR_1US_OFFSET] - - /* ================================================================== - * BEGIN CPU COMPLEX INITIALIZATON - * ================================================================== - */ - -#if !DEBUG_DO_NOT_RESET_CORESIGHT - - /* ---------------------------------------------------------------- - * Assert CoreSight reset. - * ---------------------------------------------------------------- - */ - - mov r1, #CLK_RST_DEV_U_SET_SET_CSITE_RST - str r1, [r8, #CLK_RST_CTLR_RST_DEV_U_SET_OFFSET] - -#endif /*!DEBUG_DO_NOT_RESET_CORESIGHT */ - - /* Set the drive strength */ - ldr r1, [r8, #CLK_RST_CTLR_OSC_CTRL_OFFSET] - ldr r3, =CLK_RST_CTLR_OSC_CTRL_XOFS_MASK \ - | CLK_RST_CTLR_OSC_CTRL_XOE_MASK - bic r1, r1, r3 - ldr r3, =CLK_RST_CTLR_OSC_CTRL_XOFS_VAL_4 \ - | CLK_RST_CTLR_OSC_CTRL_XOE_ENABLE - orr r3, r1, r3 - str r3, [r8, #CLK_RST_CTLR_OSC_CTRL_OFFSET] - - /* ----------------------------------------------------------------- - * Power up the CPU complex if necessary. - * ----------------------------------------------------------------- - */ - - ldr r3, [r5, #PMC_PWRGATE_STATUS_OFFSET] - tst r3, #PMC_PWRGATE_STATUS_CPU_MASK - - ldreq r2, =PMC_PWRGATE_TOGGLE_PARTID_CPU \ - | PMC_PWRGATE_TOGGLE_START_ENABLE - streq r2, [r5, #PMC_PWRGATE_TOGGLE_OFFSET] - -is_cpu_on: - ldr r3, [r5, #PMC_PWRGATE_STATUS_OFFSET] - tst r3, #PMC_PWRGATE_STATUS_CPU_MASK - beq is_cpu_on - - /* ----------------------------------------------------------------- - * Remove the I/O clamps from the CPU power partition. - * ----------------------------------------------------------------- - */ - - mov r3, #PMC_REMOVE_CLAMPING_CMD_CPU_ENABLE - str r3, [r5, #PMC_REMOVE_CLAMPING_CMD_OFFSET] - - ldr r3, =FLOW_CTLR_HALT_COP_EVENTS_ZERO_VAL_20 \ - | FLOW_CTLR_HALT_COP_EVENTS_MSEC \ - | FLOW_CTLR_HALT_COP_EVENTS_MODE_STOP - str r3, [r6, #FLOW_CTLR_HALT_COP_EVENTS_OFFSET] - - /* ------------------------------------------------------------------ - * Assert CPU complex reset. - * ------------------------------------------------------------------ - */ - - mov r1, #CLK_RST_CTLR_RST_DEV_L_SET_CPU_RST - str r1, [r8, #CLK_RST_CTLR_RST_DEV_L_SET_OFFSET] - - /* ------------------------------------------------------------------ - * Hold both CPUs in reset. - * ------------------------------------------------------------------ - */ - - ldr r3, =CLK_RST_CTLR_RST_CPU_CMPLX_SET_CPURESET0 \ - | CLK_RST_CTLR_RST_CPU_CMPLX_SET_CPURESET1 \ - | CLK_RST_CTLR_RST_CPU_CMPLX_SET_DERESET0 \ - | CLK_RST_CTLR_RST_CPU_CMPLX_SET_DERESET1 \ - | CLK_RST_CTLR_RST_CPU_CMPLX_SET_DBGRESET0 \ - | CLK_RST_CTLR_RST_CPU_CMPLX_SET_DBGRESET1 - str r3, [r8, #CLK_RST_CTLR_RST_CPU_CMPLX_SET_OFFSET] - - /* ------------------------------------------------------------------ - * Halt CPU1 at the flow controller for uni-processor configurations. - * ------------------------------------------------------------------ - */ - - mov r3, #FLOW_CTLR_HALT_CPU1_EVENTS_MODE_FLOW_MODE_STOP - str r3, [r6, #FLOW_CTLR_HALT_CPU1_EVENTS_OFFSET] - - /* ----------------------------------------------------------------- - * Set the CPU reset vector. SCRATCH41 contains the physical - * address of the CPU-side restoration code. - * ----------------------------------------------------------------- - */ - - ldr r3, [r5, #PMC_SCRATCH41_OFFSET] - str r3, [r9, #EVP_CPU_RESET_VECTOR_OFFSET] - - /* ------------------------------------------------------------------ - * Select CPU complex clock source. - * ------------------------------------------------------------------ - */ -#define CPU_CLK_SRC 4 /* 4 = PLLP_OUT0 */ - ldr r3, =(CPU_CLK_SRC << CLK_RST_CTLR_CCLK_CWAKE_FIQ_SOURCE_SHIFT) \ - | (CPU_CLK_SRC << CLK_RST_CTLR_CCLK_CWAKE_IRQ_SOURCE_SHIFT) \ - | (CPU_CLK_SRC << CLK_RST_CTLR_CCLK_CWAKE_RUN_SOURCE_SHIFT) \ - | (CPU_CLK_SRC << CLK_RST_CTLR_CCLK_CWAKE_IDLE_SOURCE_SHIFT) \ - | CLK_RST_CTLR_CCLK_CPU_STATE_RUN - str r3, [r8, #CLK_RST_CTLR_CCLK_BURST_POLICY_OFFSET] -#undef CPU_CLK_SRC - - /* ------------------------------------------------------------------ - * Start the CPU0 clock and stop the CPU1 clock. - * ------------------------------------------------------------------ - */ - - ldr r3, =CLK_RST_CTLR_CPU_CMPLX_CPU_BRIDGE_CLKDIV_BY_4 \ - | CLK_RST_CTLR_CPU_CMPLX_CPU0_CLK_STP_RUN \ - | CLK_RST_CTLR_CPU_CMPLX_CPU1_CLK_STP_STOP - str r3, [r8, #CLK_RST_CTLR_CPU_CMPLX_OFFSET] - - /* ------------------------------------------------------------------ - * Enable the CPU complex clock. - * ------------------------------------------------------------------ - */ - - mov r3, #CLK_RST_CTLR_CLK_ENB_L_SET_CLK_ENB_CPU - str r3, [r8, #CLK_RST_CTLR_CLK_ENB_L_SET_OFFSET] - - /* ----------------------------------------------------------------- - * Make sure the resets were held for at least 2 microseconds. - * ----------------------------------------------------------------- - */ - - add r3, r11, #2 - -wait: - ldr r2, [r7, #TIMERUS_CNTR_1US_OFFSET] - cmp r2, r3 - ble wait - -#if !DEBUG_DO_NOT_RESET_CORESIGHT - - /* ----------------------------------------------------------------- - * De-assert CoreSight reset. - * NOTE: We're leaving the CoreSight clock on the oscillator for - * now. It will be restored to its original clock source - * when the CPU-side restoration code runs. - * ----------------------------------------------------------------- - */ - - mov r1, #CLK_RST_CTLR_RST_DEV_U_CLR_CSITE_RST_MASK - str r1, [r8, #CLK_RST_CTLR_RST_DEV_U_CLR_OFFSET] - -#endif /*!DEBUG_DO_NOT_RESET_CORESIGHT */ - - ldr r1, =0xC5ACCE55 /* R0 = CoreSight unlock value*/ - ldr r2, =CSITE_CPUDBG0_LAR_OFFSET /* R1 = CPU0 lock offset */ - ldr r3, =CSITE_CPUDBG1_LAR_OFFSET /* R2 = CPU1 lock offset */ - str r1, [r10, r2] /* Unlock CPU0 */ - str r1, [r10, r3] /* Unlock CPU1 */ - - /* ----------------------------------------------------------------- - * Sample the microsecond timestamp again. This is the time we must - * use when returning from LP0 for PLL stabilization delays. - * ---------------------------------------------------------------- - */ - - ldr r11, [r7, #TIMERUS_CNTR_1US_OFFSET] - str r11, [r5, #PMC_SCRATCH1_OFFSET] - - /* ----------------------------------------------------------------- - * Get the oscillator frequency. For 19.2 MHz, just use 19 to - * make the calculations easier. - * ----------------------------------------------------------------- - */ - - ldr r4, [r7, #TIMERUS_USEC_CFG_OFFSET] - and r4, r4, #TIMERUS_USEC_CFG_USEC_DIVISOR_MASK - add r4, r4, #1 - cmp r4, #26 - MOVGT r4, #19 - - /* PLLX_BASE.PLLX_DIVM */ - ldr r0, [r5, #PMC_SCRATCH3_OFFSET] - and r2, r0, #PMC_SCRATCH3_PLLX_BASE_DIVM_MASK - cmp r2, r4 - moveq r4, #0 - movne r4, #1 - - /* PLLX_BASE.PLLX_DIVN */ - mov r0, r0, ASR #(PMC_SCRATCH3_PLLX_BASE_DIVN_SHIFT - \ - PMC_SCRATCH3_PLLX_BASE_DIVM_SHIFT) - ldr r3, =PMC_SCRATCH3_PLLX_BASE_DIVN_MASK - and r1, r0, r3 - orr r2, r2, r1, LSL #CLK_RST_CTLR_PLLX_BASE_DIVN_SHIFT - mov r4, r1, LSL r4 - - /* PLLX_BASE.PLLX_DIVP */ - mov r0, r0, ASR #(PMC_SCRATCH3_PLLX_BASE_DIVP_SHIFT - \ - PMC_SCRATCH3_PLLX_BASE_DIVN_SHIFT) - and r1, r0, #PMC_SCRATCH3_PLLX_BASE_DIVP_MASK - orr r2, r2, r1, LSL #CLK_RST_CTLR_PLLX_BASE_DIVP_SHIFT - mov r4, r4, ASR r1 - - /* PLLX_BASE.PLLX_BYPASS_ENABLE | PLLX_BASE.PLLX_ENABLE_DISABLE | - * PLLX_BASE.PLLX_REF_DIS_REF_ENABLE - */ - orr r2, r2, #CLK_RST_CTLR_PLLX_BASE_BYPASS_ENABLE \ - | CLK_RST_CTLR_PLLX_BASE_ENABLE_DISABLE \ - | CLK_RST_CTLR_PLLX_BASE_REF_DIS_REF_ENABLE - - /* PLLX_MISC_DCCON must be set for frequencies > 600 MHz. */ - cmp r4, #600 - movlt r3, #0 - movge r3, #CLK_RST_CTLR_PLLX_MISC_DCCON_DEFAULT - - /* PLLX_MISC_LFCON */ - mov r0, r0, ASR #(PMC_SCRATCH3_PLLX_MISC_LFCON_SHIFT - \ - PMC_SCRATCH3_PLLX_BASE_DIVP_SHIFT) - and r1, r0, #PMC_SCRATCH3_PLLX_MISC_LFCON_MASK - orr r3, r3, r1, LSL #CLK_RST_CTLR_PLLX_MISC_LFCON_SHIFT - - /* PLLX_MISC_CPCON */ - mov r0, r0, ASR #(PMC_SCRATCH3_PLLX_MISC_CPCON_SHIFT - \ - PMC_SCRATCH3_PLLX_MISC_LFCON_SHIFT) - and r1, r0, #PMC_SCRATCH3_PLLX_MISC_LFCON_MASK - orr r3, r3, r1, LSL #CLK_RST_CTLR_PLLX_MISC_CPCON_SHIFT - - str r3, [r8, #CLK_RST_CTLR_PLLX_MISC_OFFSET] - str r2, [r8, #CLK_RST_CTLR_PLLX_BASE_OFFSET] - orr r2, r2, #CLK_RST_CTLR_PLLX_BASE_ENABLE_ENABLE - str r2, [r8, #CLK_RST_CTLR_PLLX_BASE_OFFSET] - BIC r2, r2, #CLK_RST_CTLR_PLLX_BASE_BYPASS_ENABLE - str r2, [r8, #CLK_RST_CTLR_PLLX_BASE_OFFSET] - - mov r3, #0 - str r3, [r6, #FLOW_CTLR_HALT_CPU_EVENTS_OFFSET] - - ldr r3, =CLK_RST_CTLR_RST_CPU_CMPLX_CLR_CPURESET0 \ - | CLK_RST_CTLR_RST_CPU_CMPLX_CLR_DBGRESET0 \ - | CLK_RST_CTLR_RST_CPU_CMPLX_CLR_DERESET0 - str r3, [r8, #CLK_RST_CTLR_RST_CPU_CMPLX_CLR_OFFSET] - - ldr r1, = CLK_RST_CTLR_PLLM_OUT1_RSTN_RESET_DISABLE \ - | CLK_RST_CTLR_PLLM_OUT1_CLKEN_ENABLE \ - | CLK_RST_CTLR_PLLM_OUT1_RATIO_VAL_8 - str r1, [r8, #CLK_RST_CTLR_PLLM_OUT_OFFSET] - - ldr r2, =CLK_RST_CTLR_SCLK_SWAKE_FIQ_SOURCE_PLLM_OUT1 \ - | CLK_RST_CTLR_SCLK_SWAKE_IRQ_SOURCE_PLLM_OUT1 \ - | CLK_RST_CTLR_SCLK_SWAKE_RUN_SOURCE_PLLM_OUT1 \ - | CLK_RST_CTLR_SCLK_SWAKE_IDLE_SOURCE_PLLM_OUT1 \ - | CLK_RST_CTLR_SCLK_SYS_STATE_IDLE - str r2, [r8, #CLK_RST_CTLR_SCLK_BURST_POLICY_OFFSET] - b avp_resume - - .ltorg - .align 4 - -avp_resume: - - mov r1, #CLK_RST_CTLR_RST_DEV_L_CLR_CPU_RST - str r1, [r8, #CLK_RST_CTLR_RST_DEV_L_CLR_OFFSET] - -avp_halt: - - mov r3, #FLOW_CTLR_HALT_COP_EVENTS_MODE_STOP - orr r3, r3, #FLOW_CTLR_HALT_COP_EVENTS_JTAG - str r3, [r6, #FLOW_CTLR_HALT_COP_EVENTS_OFFSET] - b avp_halt - -/* --------------------------------------------------------------------------- - * Prototype: - * do_reset - * - * Input: - * None - * - * Output: - * None - * - * Registers Used: - * All - * - * Description: - * Execution comes here it something goes wrong. The chip is reset and a - * cold boot is performed. - * --------------------------------------------------------------------------- - */ - -do_reset: - - mov r0, #CLK_RST_CTLR_RST_DEVICES_L_SWR_TRIG_SYS_RST - str r0, [r8, #CLK_RST_CTLR_RST_DEVICES_L_OFFSET] - b . - - .ltorg - - .globl wb_end -wb_end: - - .end - - diff --git a/arch/arm/cpu/armv7/tegra2/warmboot_avp.c b/arch/arm/cpu/armv7/tegra2/warmboot_avp.c new file mode 100644 index 0000000000..6065326fa0 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/warmboot_avp.c @@ -0,0 +1,313 @@ +/* + * (C) Copyright 2010 - 2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/pmc.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/flow.h> +#include <asm/arch/warmboot.h> +#include "ap20.h" +#include "warmboot_avp.h" + +#define DEBUG_RESET_CORESIGHT + +union osc_ctrl_reg { + struct { + u32 xoe:1; + u32 xobp:1; + u32 reserved0:2; + u32 xofs:6; + u32 reserved1:2; + u32 xods:5; + u32 reserved2:3; + u32 oscfi_spare:8; + u32 pll_ref_div:2; + u32 osc_freq:2; + }; + u32 word; +}; + +union pllx_base_reg { + struct { + u32 divm:5; + u32 reserved0:3; + u32 divn:10; + u32 reserved1:2; + u32 divp:3; + u32 reserved2:4; + u32 lock:1; + u32 reserved3:1; + u32 ref_dis:1; + u32 enable:1; + u32 bypass:1; + }; + u32 word; +}; + +union pllx_misc_reg { + struct { + u32 vcocon:4; + u32 lfcon:4; + u32 cpcon:4; + u32 lock_sel:6; + u32 reserved0:1; + u32 lock_enable:1; + u32 reserved1:1; + u32 dccon:1; + u32 pts:2; + u32 reserved2:6; + u32 out1_div_byp:1; + u32 out1_inv_clk:1; + }; + u32 word; +}; + +union scratch3_reg { + struct { + u32 pllx_base_divm:5; + u32 pllx_base_divn:10; + u32 pllx_base_divp:3; + u32 pllx_misc_lfcon:4; + u32 pllx_misc_cpcon:4; + }; + u32 word; +}; + +void wb_start(void) +{ + struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + union osc_ctrl_reg osc_ctrl; + union pllx_base_reg pllx_base; + union pllx_misc_reg pllx_misc; + union scratch3_reg scratch3; + u32 reg; + + /* enable JTAG & TBE */ + writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &pmt->pmt_cfg_ctl); + + /* Are we running where we're supposed to be? */ + asm volatile ( + "adr %0, wb_start;" /* reg: wb_start address */ + : "=r"(reg) /* output */ + /* no input, no clobber list */ + ); + + if (reg != AP20_WB_RUN_ADDRESS) + goto do_reset; + + /* Are we running with AVP? */ + if (readl(NV_PA_PG_UP_BASE + PG_UP_TAG_0) != PG_UP_TAG_AVP) + goto do_reset; + +#ifdef DEBUG_RESET_CORESIGHT + /* Assert CoreSight reset */ + reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]); + reg |= SWR_CSITE_RST; + writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]); +#endif + + /* Set the drive strength */ + osc_ctrl.word = readl(&clkrst->crc_osc_ctrl); + osc_ctrl.xofs = 4; + osc_ctrl.xoe = 1; + writel(osc_ctrl.word, &clkrst->crc_osc_ctrl); + + /* Power up the CPU complex if necessary */ + if (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) { + reg = PWRGATE_TOGGLE_PARTID_CPU | PWRGATE_TOGGLE_START; + writel(reg, &pmc->pmc_pwrgate_toggle); + while (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) + ; + } + + /* Remove the I/O clamps from the CPU power partition. */ + reg = readl(&pmc->pmc_remove_clamping); + reg |= CPU_CLMP; + writel(reg, &pmc->pmc_remove_clamping); + + reg = EVENT_ZERO_VAL_20 | EVENT_MSEC | EVENT_MODE_STOP; + writel(reg, &flow->halt_cop_events); + + /* Assert CPU complex reset */ + reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]); + reg |= CPU_RST; + writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]); + + /* Hold both CPUs in reset */ + reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_CPURESET1 | CPU_CMPLX_DERESET0 | + CPU_CMPLX_DERESET1 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DBGRESET1; + writel(reg, &clkrst->crc_cpu_cmplx_set); + + /* Halt CPU1 at the flow controller for uni-processor configurations */ + writel(EVENT_MODE_STOP, &flow->halt_cpu1_events); + + /* + * Set the CPU reset vector. SCRATCH41 contains the physical + * address of the CPU-side restoration code. + */ + reg = readl(&pmc->pmc_scratch41); + writel(reg, EXCEP_VECTOR_CPU_RESET_VECTOR); + + /* Select CPU complex clock source */ + writel(CCLK_PLLP_BURST_POLICY, &clkrst->crc_cclk_brst_pol); + + /* Start the CPU0 clock and stop the CPU1 clock */ + reg = CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 | CPU_CMPLX_CPU0_CLK_STP_RUN | + CPU_CMPLX_CPU1_CLK_STP_STOP; + writel(reg, &clkrst->crc_clk_cpu_cmplx); + + /* Enable the CPU complex clock */ + reg = readl(&clkrst->crc_clk_out_enb[TEGRA_DEV_L]); + reg |= CLK_ENB_CPU; + writel(reg, &clkrst->crc_clk_out_enb[TEGRA_DEV_L]); + + /* Make sure the resets were held for at least 2 microseconds */ + reg = readl(TIMER_USEC_CNTR); + while (readl(TIMER_USEC_CNTR) <= (reg + 2)) + ; + +#ifdef DEBUG_RESET_CORESIGHT + /* + * De-assert CoreSight reset. + * NOTE: We're leaving the CoreSight clock on the oscillator for + * now. It will be restored to its original clock source + * when the CPU-side restoration code runs. + */ + reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]); + reg &= ~SWR_CSITE_RST; + writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]); +#endif + + /* Unlock the CPU CoreSight interfaces */ + reg = 0xC5ACCE55; + writel(reg, CSITE_CPU_DBG0_LAR); + writel(reg, CSITE_CPU_DBG1_LAR); + + /* + * Sample the microsecond timestamp again. This is the time we must + * use when returning from LP0 for PLL stabilization delays. + */ + reg = readl(TIMER_USEC_CNTR); + writel(reg, &pmc->pmc_scratch1); + + pllx_base.word = 0; + pllx_misc.word = 0; + scratch3.word = readl(&pmc->pmc_scratch3); + + /* Get the OSC. For 19.2 MHz, use 19 to make the calculations easier */ + reg = (readl(TIMER_USEC_CFG) & USEC_CFG_DIVISOR_MASK) + 1; + + /* + * According to the TRM, for 19.2MHz OSC, the USEC_DIVISOR is 0x5f, and + * USEC_DIVIDEND is 0x04. So, if USEC_DIVISOR > 26, OSC is 19.2 MHz. + * + * reg is used to calculate the pllx freq, which is used to determine if + * to set dccon or not. + */ + if (reg > 26) + reg = 19; + + /* PLLX_BASE.PLLX_DIVM */ + if (scratch3.pllx_base_divm == reg) + reg = 0; + else + reg = 1; + + /* PLLX_BASE.PLLX_DIVN */ + pllx_base.divn = scratch3.pllx_base_divn; + reg = scratch3.pllx_base_divn << reg; + + /* PLLX_BASE.PLLX_DIVP */ + pllx_base.divp = scratch3.pllx_base_divp; + reg = reg >> scratch3.pllx_base_divp; + + pllx_base.bypass = 1; + + /* PLLX_MISC_DCCON must be set for pllx frequency > 600 MHz. */ + if (reg > 600) + pllx_misc.dccon = 1; + + /* PLLX_MISC_LFCON */ + pllx_misc.lfcon = scratch3.pllx_misc_lfcon; + + /* PLLX_MISC_CPCON */ + pllx_misc.cpcon = scratch3.pllx_misc_cpcon; + + writel(pllx_misc.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_misc); + writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); + + pllx_base.enable = 1; + writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); + pllx_base.bypass = 0; + writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); + + writel(0, flow->halt_cpu_events); + + reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DERESET0; + writel(reg, &clkrst->crc_cpu_cmplx_clr); + + reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE | + PLLM_OUT1_RATIO_VAL_8; + writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out); + + reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 | + SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 | + SCLK_SYS_STATE_IDLE; + writel(reg, &clkrst->crc_sclk_brst_pol); + + /* avp_resume: no return after the write */ + reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]); + reg &= ~CPU_RST; + writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]); + + /* avp_halt: */ +avp_halt: + reg = EVENT_MODE_STOP | EVENT_JTAG; + writel(reg, flow->halt_cop_events); + goto avp_halt; + +do_reset: + /* + * Execution comes here if something goes wrong. The chip is reset and + * a cold boot is performed. + */ + writel(SWR_TRIG_SYS_RST, &clkrst->crc_rst_dev[TEGRA_DEV_L]); + goto do_reset; +} + +/* + * wb_end() is a dummy function, and must be directly following wb_start(), + * and is used to calculate the size of wb_start(). + */ +void wb_end(void) +{ +} + diff --git a/arch/arm/cpu/armv7/tegra2/warmboot_avp.h b/arch/arm/cpu/armv7/tegra2/warmboot_avp.h index 56cdf7157f..3b568e9d02 100644 --- a/arch/arm/cpu/armv7/tegra2/warmboot_avp.h +++ b/arch/arm/cpu/armv7/tegra2/warmboot_avp.h @@ -24,138 +24,59 @@ #ifndef _WARMBOOT_AVP_H_ #define _WARMBOOT_AVP_H_ -/* Followings are used by warmboot_avp.S */ - -#define PMC_SCRATCH1_OFFSET 0x54 -#define PMC_SCRATCH3_OFFSET 0x5c -#define PMC_SCRATCH41_OFFSET 0x140 - -#define PG_UP_TAG_OFFSET 0 -#define TIMERUS_CNTR_1US_OFFSET 0 - -#define CSITE_CPUDBG0_LAR_OFFSET 0x10fb0 -#define CSITE_CPUDBG1_LAR_OFFSET 0x12fb0 - -#define APB_MISC_PP_CONFIG_CTL_OFFSET 0x24 -#define APB_MISC_PP_CONFIG_CTL_TBE_ENABLE (1 << 7) -#define APB_MISC_PP_CONFIG_CTL_JTAG_ENABLE (1 << 6) - -#define CLK_RST_CTLR_RST_DEV_U_SET_OFFSET 0x310 -#define CLK_RST_DEV_U_SET_SET_CSITE_RST (1 << 9) - -#define CLK_RST_CTLR_OSC_CTRL_OFFSET 0x50 -#define CLK_RST_CTLR_OSC_CTRL_XOFS_MASK (0x3f << 4) -#define CLK_RST_CTLR_OSC_CTRL_XOFS_VAL_4 (0x04 << 4) -#define CLK_RST_CTLR_OSC_CTRL_XOE_MASK (0x01 << 0) -#define CLK_RST_CTLR_OSC_CTRL_XOE_ENABLE (0x01 << 0) - -#define PMC_PWRGATE_STATUS_OFFSET 0x38 -#define PMC_PWRGATE_STATUS_CPU_MASK (0x01 << 0) - -#define PMC_PWRGATE_TOGGLE_OFFSET 0x30 -#define PMC_PWRGATE_TOGGLE_PARTID_CPU (0 << 0) -#define PMC_PWRGATE_TOGGLE_START_ENABLE (1 << 8) - -#define PMC_REMOVE_CLAMPING_CMD_OFFSET 0x34 -#define PMC_REMOVE_CLAMPING_CMD_CPU_ENABLE (1 << 0) - -#define FLOW_CTLR_HALT_COP_EVENTS_OFFSET 0x4 -#define FLOW_CTLR_HALT_COP_EVENTS_ZERO_VAL_20 (20 << 0) -#define FLOW_CTLR_HALT_COP_EVENTS_MSEC (1 << 24) -#define FLOW_CTLR_HALT_COP_EVENTS_JTAG (1 << 28) -#define FLOW_CTLR_HALT_COP_EVENTS_MODE_STOP (2 << 29) - -#define CLK_RST_CTLR_RST_DEV_L_SET_OFFSET 0x300 -#define CLK_RST_CTLR_RST_DEV_L_SET_CPU_RST (1 << 0) - -#define CLK_RST_CTLR_RST_CPU_CMPLX_SET_OFFSET 0x340 -#define CLK_RST_CTLR_RST_CPU_CMPLX_SET_CPURESET0 (1 << 0) -#define CLK_RST_CTLR_RST_CPU_CMPLX_SET_CPURESET1 (1 << 1) -#define CLK_RST_CTLR_RST_CPU_CMPLX_SET_DERESET0 (1 << 4) -#define CLK_RST_CTLR_RST_CPU_CMPLX_SET_DERESET1 (1 << 5) -#define CLK_RST_CTLR_RST_CPU_CMPLX_SET_DBGRESET0 (1 << 12) -#define CLK_RST_CTLR_RST_CPU_CMPLX_SET_DBGRESET1 (1 << 13) - -#define FLOW_CTLR_HALT_CPU1_EVENTS_OFFSET 0x14 -#define FLOW_CTLR_HALT_CPU1_EVENTS_MODE_FLOW_MODE_STOP (2 << 29) - -#define EVP_CPU_RESET_VECTOR_OFFSET 0x100 - -#define CLK_RST_CTLR_CCLK_BURST_POLICY_OFFSET 0x20 -#define CLK_RST_CTLR_CCLK_CWAKE_FIQ_SOURCE_SHIFT 12 -#define CLK_RST_CTLR_CCLK_CWAKE_IRQ_SOURCE_SHIFT 8 -#define CLK_RST_CTLR_CCLK_CWAKE_RUN_SOURCE_SHIFT 4 -#define CLK_RST_CTLR_CCLK_CWAKE_IDLE_SOURCE_SHIFT 0 -#define CLK_RST_CTLR_CCLK_CPU_STATE_RUN (2 << 28) - -#define CLK_RST_CTLR_CPU_CMPLX_OFFSET 0x4c -#define CLK_RST_CTLR_CPU_CMPLX_CPU_BRIDGE_CLKDIV_BY_4 (3 << 0) -#define CLK_RST_CTLR_CPU_CMPLX_CPU0_CLK_STP_STOP (1 << 8) -#define CLK_RST_CTLR_CPU_CMPLX_CPU0_CLK_STP_RUN (0 << 8) -#define CLK_RST_CTLR_CPU_CMPLX_CPU1_CLK_STP_STOP (1 << 9) -#define CLK_RST_CTLR_CPU_CMPLX_CPU1_CLK_STP_RUN (0 << 9) - -#define CLK_RST_CTLR_CLK_ENB_L_SET_OFFSET 0x320 -#define CLK_RST_CTLR_CLK_ENB_L_SET_CLK_ENB_CPU (1 << 0) - -#define CLK_RST_CTLR_RST_DEV_U_CLR_OFFSET 0x314 -#define CLK_RST_CTLR_RST_DEV_U_CLR_CSITE_RST_MASK (1 << 9) - -#define TIMERUS_USEC_CFG_OFFSET 0x4 -#define TIMERUS_USEC_CFG_USEC_DIVISOR_MASK 0xff - -#define CLK_RST_CTLR_PLLX_BASE_OFFSET 0xe0 -#define CLK_RST_CTLR_PLLX_MISC_OFFSET 0xe4 -#define CLK_RST_CTLR_PLLX_BASE_BYPASS_ENABLE (1 << 31) -#define CLK_RST_CTLR_PLLX_BASE_ENABLE_ENABLE (1 << 30) -#define CLK_RST_CTLR_PLLX_BASE_ENABLE_DISABLE (0 << 30) -#define CLK_RST_CTLR_PLLX_BASE_REF_DIS_REF_ENABLE (0 << 29) -#define CLK_RST_CTLR_PLLX_BASE_DIVP_SHIFT 20 -#define CLK_RST_CTLR_PLLX_BASE_DIVN_SHIFT 8 - -#define CLK_RST_CTLR_PLLX_MISC_DCCON_DEFAULT (1 << 20) -#define CLK_RST_CTLR_PLLX_MISC_CPCON_SHIFT 8 -#define CLK_RST_CTLR_PLLX_MISC_LFCON_SHIFT 4 - -#define PMC_SCRATCH3_PLLX_MISC_CPCON_SHIFT 22 -#define PMC_SCRATCH3_PLLX_MISC_CPCON_MASK 0xf -#define PMC_SCRATCH3_PLLX_MISC_LFCON_SHIFT 18 -#define PMC_SCRATCH3_PLLX_MISC_LFCON_MASK 0xf -#define PMC_SCRATCH3_PLLX_BASE_DIVP_SHIFT 15 -#define PMC_SCRATCH3_PLLX_BASE_DIVM_MASK 0x1f -#define PMC_SCRATCH3_PLLX_BASE_DIVN_SHIFT 5 -#define PMC_SCRATCH3_PLLX_BASE_DIVM_SHIFT 0 -#define PMC_SCRATCH3_PLLX_BASE_DIVN_MASK 0x3ff -#define PMC_SCRATCH3_PLLX_BASE_DIVN_SHIFT 5 -#define PMC_SCRATCH3_PLLX_BASE_DIVP_MASK 0x07 - -#define FLOW_CTLR_HALT_CPU_EVENTS_OFFSET 0x0 - -#define CLK_RST_CTLR_RST_CPU_CMPLX_CLR_OFFSET 0x344 -#define CLK_RST_CTLR_RST_CPU_CMPLX_CLR_CPURESET0 (1 << 0) -#define CLK_RST_CTLR_RST_CPU_CMPLX_CLR_CPURESET1 (1 << 1) -#define CLK_RST_CTLR_RST_CPU_CMPLX_CLR_DERESET0 (1 << 4) -#define CLK_RST_CTLR_RST_CPU_CMPLX_CLR_DERESET1 (1 << 5) -#define CLK_RST_CTLR_RST_CPU_CMPLX_CLR_DBGRESET0 (1 << 12) -#define CLK_RST_CTLR_RST_CPU_CMPLX_CLR_DBGRESET1 (1 << 13) - -#define CLK_RST_CTLR_PLLM_OUT_OFFSET 0x94 -#define CLK_RST_CTLR_PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0) -#define CLK_RST_CTLR_PLLM_OUT1_CLKEN_ENABLE (1 << 1) -#define CLK_RST_CTLR_PLLM_OUT1_RATIO_VAL_8 (8 << 8) - -#define CLK_RST_CTLR_SCLK_BURST_POLICY_OFFSET 0x28 -#define CLK_RST_CTLR_SCLK_SYS_STATE_IDLE (1 << 28) -#define CLK_RST_CTLR_SCLK_SWAKE_FIQ_SOURCE_PLLM_OUT1 (7 << 12) -#define CLK_RST_CTLR_SCLK_SWAKE_IRQ_SOURCE_PLLM_OUT1 (7 << 8) -#define CLK_RST_CTLR_SCLK_SWAKE_RUN_SOURCE_PLLM_OUT1 (7 << 4) -#define CLK_RST_CTLR_SCLK_SWAKE_IDLE_SOURCE_PLLM_OUT1 (7 << 0) - -#define CLK_RST_CTLR_RST_DEV_L_CLR_OFFSET 0x304 -#define CLK_RST_CTLR_RST_DEV_L_CLR_CPU_RST (1 << 0) - -#define CLK_RST_CTLR_RST_DEVICES_L_OFFSET 0x4 -#define CLK_RST_CTLR_RST_DEVICES_L_SWR_TRIG_SYS_RST (1 << 2) +#define TEGRA_DEV_L 0 +#define TEGRA_DEV_H 1 +#define TEGRA_DEV_U 2 + +#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) +#define SIMPLE_PLLE (CLOCK_ID_EPCI - CLOCK_ID_FIRST_SIMPLE) + +#define TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0) +#define TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4) + +#define USEC_CFG_DIVISOR_MASK 0xffff + +#define CONFIG_CTL_TBE (1 << 7) +#define CONFIG_CTL_JTAG (1 << 6) + +#define CPU_RST (1 << 0) +#define CLK_ENB_CPU (1 << 0) +#define SWR_TRIG_SYS_RST (1 << 2) +#define SWR_CSITE_RST (1 << 9) + +#define PWRGATE_STATUS_CPU (1 << 0) +#define PWRGATE_TOGGLE_PARTID_CPU (0 << 0) +#define PWRGATE_TOGGLE_START (1 << 8) + +#define CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 (3 << 0) +#define CPU_CMPLX_CPU0_CLK_STP_STOP (1 << 8) +#define CPU_CMPLX_CPU0_CLK_STP_RUN (0 << 8) +#define CPU_CMPLX_CPU1_CLK_STP_STOP (1 << 9) +#define CPU_CMPLX_CPU1_CLK_STP_RUN (0 << 9) + +#define CPU_CMPLX_CPURESET0 (1 << 0) +#define CPU_CMPLX_CPURESET1 (1 << 1) +#define CPU_CMPLX_DERESET0 (1 << 4) +#define CPU_CMPLX_DERESET1 (1 << 5) +#define CPU_CMPLX_DBGRESET0 (1 << 12) +#define CPU_CMPLX_DBGRESET1 (1 << 13) + +#define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0) +#define PLLM_OUT1_CLKEN_ENABLE (1 << 1) +#define PLLM_OUT1_RATIO_VAL_8 (8 << 8) + +#define SCLK_SYS_STATE_IDLE (1 << 28) +#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12) +#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8) +#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4) +#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0) + +#define EVENT_ZERO_VAL_20 (20 << 0) +#define EVENT_MSEC (1 << 24) +#define EVENT_JTAG (1 << 28) +#define EVENT_MODE_STOP (2 << 29) + +#define CCLK_PLLP_BURST_POLICY 0x20004444 #endif diff --git a/arch/arm/include/asm/arch-tegra2/flow.h b/arch/arm/include/asm/arch-tegra2/flow.h new file mode 100644 index 0000000000..cce6cbf7d0 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/flow.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2010, 2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FLOW_H_ +#define _FLOW_H_ + +struct flow_ctlr { + u32 halt_cpu_events; + u32 halt_cop_events; + u32 cpu_csr; + u32 cop_csr; + u32 halt_cpu1_events; + u32 cpu1_csr; +}; + +#endif |