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-rw-r--r--board/freescale/mx6q_hdmidongle/mx6q_hdmidongle.c16
1 files changed, 0 insertions, 16 deletions
diff --git a/board/freescale/mx6q_hdmidongle/mx6q_hdmidongle.c b/board/freescale/mx6q_hdmidongle/mx6q_hdmidongle.c
index 198ccc4bd6f..6677ad45e8e 100644
--- a/board/freescale/mx6q_hdmidongle/mx6q_hdmidongle.c
+++ b/board/freescale/mx6q_hdmidongle/mx6q_hdmidongle.c
@@ -219,8 +219,6 @@ void board_mmu_init(void)
#define ANATOP_PLL_PWDN_MASK 0x00001000
#define ANATOP_PLL_HOLD_RING_OFF_MASK 0x00000800
#define ANATOP_SATA_CLK_ENABLE_MASK 0x00100000
-#define PORT_PHY_CTL 0x178
-#define PORT_PHY_CTL_PDDQ_LOC 0x100000
/* Note: udelay() is not accurate for i2c timing */
static void __udelay(int time)
@@ -278,16 +276,6 @@ static int setup_sata(void)
* */
reg |= 0x59124c6;
writel(reg, IOMUXC_BASE_ADDR + 0x34);
- /* FIXME */
- /*
- * It needs to wait SATA PHY initialize completed, otherwise write the
- * PORT_PHY_CTL will fail, then can't enable PDDQ which let PHY entry LPM
- * Currently set it as 1ms.
- */
- __udelay(1000);
- /* Enable PDDQ mode in default */
- writel(readl(SATA_ARB_BASE_ADDR + PORT_PHY_CTL) | PORT_PHY_CTL_PDDQ_LOC,
- SATA_ARB_BASE_ADDR + PORT_PHY_CTL);
return 0;
}
@@ -1421,10 +1409,6 @@ int checkboard(void)
printf("UNKNOWN\n");
break;
}
- if (cpu_is_mx6q())
- printf("SATA PDDQ: %s\n", ((readl(SATA_ARB_BASE_ADDR
- + PORT_PHY_CTL)
- & PORT_PHY_CTL_PDDQ_LOC)>>20) ? "enabled" : "disabled");
return 0;
}