diff options
193 files changed, 8129 insertions, 2039 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 1f6008f747e..75f4133684a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -431,6 +431,7 @@ Rune Torgersen <runet@innovsys.com> Peter Tyser <ptyser@xes-inc.com> + XPEDITE5170 MPC8640 XPEDITE5200 MPC8548 XPEDITE5370 MPC8572 @@ -866,11 +867,38 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org> BF527-EZKIT BF527 BF533-EZKIT BF533 BF533-STAMP BF533 + BF537-PNAV BF537 BF537-STAMP BF537 BF538F-EZKIT BF538 BF548-EZKIT BF548 BF561-EZKIT BF561 +Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> +Blackfin Team <u-boot-devel@blackfin.uclinux.org> + + CM-BF527 BF527 + CM-BF533 BF533 + CM-BF537E BF537 + CM-BF548 BF548 + CM-BF561 BF561 + TCM-BF537 BF537 + +Martin Strubel <strubel@section5.ch> +Blackfin Team <u-boot-devel@blackfin.uclinux.org> + + BF537-minotaur BF537 + BF537-srv1 BF537 + +Wojtek Skulski <skulski@pas.rochester.edu> +Benjamin Matthews <mben12@gmail.com> + + BLACKSTAMP BF532 + +I-SYST Micromodule <support@i-syst.com> +Blackfin Team <u-boot-devel@blackfin.uclinux.org> + + IBF-DSP561 BF561 + ######################################################################### # End of MAINTAINERS list # ######################################################################### @@ -411,6 +411,7 @@ LIST_86xx=" \ MPC8610HPCD \ MPC8641HPCN \ sbc8641d \ + XPEDITE5170 \ " ######################################################################### @@ -802,10 +803,21 @@ LIST_blackfin=" \ bf527-ezkit \ bf533-ezkit \ bf533-stamp \ + bf537-minotaur \ + bf537-pnav \ + bf537-srv1 \ bf537-stamp \ bf538f-ezkit \ bf548-ezkit \ bf561-ezkit \ + blackstamp \ + cm-bf527 \ + cm-bf533 \ + cm-bf537e \ + cm-bf548 \ + cm-bf561 \ + ibf-dsp561 \ + tcm-bf537 \ " ######################################################################### @@ -137,6 +137,14 @@ ifeq ($(ARCH),powerpc) ARCH = ppc endif +# The "tools" are needed early, so put this first +# Don't include stuff already done in $(LIBS) +SUBDIRS = tools \ + examples \ + api_examples + +.PHONY : $(SUBDIRS) + ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk)) # load ARCH, BOARD, and CPU configuration @@ -282,14 +290,6 @@ LIBBOARD := $(addprefix $(obj),$(LIBBOARD)) # Add GCC lib PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc -# The "tools" are needed early, so put this first -# Don't include stuff already done in $(LIBS) -SUBDIRS = tools \ - examples \ - api_examples - -.PHONY : $(SUBDIRS) - ifeq ($(CONFIG_NAND_U_BOOT),y) NAND_SPL = nand_spl U_BOOT_NAND = $(obj)u-boot-nand.bin @@ -306,10 +306,8 @@ __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD)) ######################################################################### ######################################################################### +# Always append ALL so that arch config.mk's can add custom ones ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND) -ifeq ($(ARCH),blackfin) -ALL += $(obj)u-boot.ldr -endif all: $(ALL) @@ -323,6 +321,7 @@ $(obj)u-boot.bin: $(obj)u-boot $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ $(obj)u-boot.ldr: $(obj)u-boot + $(obj)tools/envcrc --binary > $(obj)env-ldr.o $(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS) $(obj)u-boot.ldr.hex: $(obj)u-boot.ldr @@ -2581,6 +2580,9 @@ MPC8641HPCN_config: unconfig sbc8641d_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc86xx sbc8641d +XPEDITE5170_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc86xx xpedite5170 xes + ######################################################################### ## 74xx/7xx Systems ######################################################################### @@ -3387,7 +3389,16 @@ suzaku_config: unconfig # Analog Devices boards BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \ - bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit + bf537-pnav bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit + +# Bluetechnix tinyboards +BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf548 cm-bf561 tcm-bf537 + +# Misc third party boards +BFIN_BOARDS += bf537-minotaur bf537-srv1 blackstamp + +# I-SYST Micromodule +BFIN_BOARDS += ibf-dsp561 $(BFIN_BOARDS:%=%_config) : unconfig @$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=) @@ -3561,8 +3572,7 @@ clean: $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \ $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \ $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \ - $(obj)board/bf5{18f,26,27,33,38f,48,61}-ez{brd,kit}/u-boot.lds \ - $(obj)board/bf5{33,37}-stamp/u-boot.lds \ + $(obj)lib_blackfin/u-boot.lds \ $(obj)cpu/blackfin/bootrom-asm-offsets.[chs] @rm -f $(obj)include/bmp_logo.h @rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map} diff --git a/blackfin_config.mk b/blackfin_config.mk index 05077c819b3..821f0827521 100644 --- a/blackfin_config.mk +++ b/blackfin_config.mk @@ -23,6 +23,8 @@ CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU))) CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE))) +CONFIG_ENV_OFFSET := $(strip $(subst ",,$(CONFIG_ENV_OFFSET))) +CONFIG_ENV_SIZE := $(strip $(subst ",,$(CONFIG_ENV_SIZE))) PLATFORM_RELFLAGS += -ffixed-P5 -fomit-frame-pointer -mno-fdpic PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN @@ -34,6 +36,10 @@ ifneq (,$(CONFIG_BFIN_CPU)) PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU) endif +ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) +ALL += $(obj)u-boot.ldr +endif + SYM_PREFIX = _ LDR_FLAGS-y := @@ -41,11 +47,18 @@ LDR_FLAGS-$(CONFIG_BFIN_BOOTROM_USES_EVT1) += -J LDR_FLAGS += --bmode $(subst BFIN_BOOT_,,$(CONFIG_BFIN_BOOT_MODE)) LDR_FLAGS += --use-vmas -ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) LDR_FLAGS += --initcode $(obj)cpu/$(CPU)/initcode.o +ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_UART) +ifneq ($(ENV_IS_EMBEDDED_CUSTOM),ENV_IS_EMBEDDED_CUSTOM) +LDR_FLAGS += --punchit $$(($(CONFIG_ENV_OFFSET))):$$(($(CONFIG_ENV_SIZE))):$(obj)env-ldr.o +endif endif ifneq (,$(findstring s,$(MAKEFLAGS))) LDR_FLAGS += --quiet endif LDR_FLAGS += $(LDR_FLAGS-y) + +ifeq ($(wildcard $(TOPDIR)/board/$(BOARD)/u-boot.lds*),) +LDSCRIPT = $(obj)lib_$(ARCH)/u-boot.lds +endif diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index a89cb8bf278..0817e601546 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -36,6 +36,7 @@ #include <atmel_lcdc.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) #include <net.h> +#include <netdev.h> #endif DECLARE_GLOBAL_DATA_PTR; @@ -227,6 +228,12 @@ int board_init(void) return 0; } +#ifdef CONFIG_DRIVER_DM9000 + int board_eth_init(bd_t *bis) + { + return dm9000_initialize(bis); + } + #endif int dram_init(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM; diff --git a/board/bf518f-ezbrd/.gitignore b/board/bf518f-ezbrd/.gitignore deleted file mode 100644 index 945f3245496..00000000000 --- a/board/bf518f-ezbrd/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/u-boot.lds diff --git a/board/bf518f-ezbrd/Makefile b/board/bf518f-ezbrd/Makefile index 1b217288b9f..f2bd2c247d4 100644 --- a/board/bf518f-ezbrd/Makefile +++ b/board/bf518f-ezbrd/Makefile @@ -35,12 +35,9 @@ SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS-y)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -$(obj)u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ - clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf518f-ezbrd/config.mk b/board/bf518f-ezbrd/config.mk index f4a5a80283e..f85bef5e2a7 100644 --- a/board/bf518f-ezbrd/config.mk +++ b/board/bf518f-ezbrd/config.mk @@ -26,7 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf518f-ezbrd/u-boot.lds.S b/board/bf518f-ezbrd/u-boot.lds.S deleted file mode 100644 index 3e8be358da6..00000000000 --- a/board/bf518f-ezbrd/u-boot.lds.S +++ /dev/null @@ -1,124 +0,0 @@ -/* - * U-boot - u-boot.lds.S - * - * Copyright (c) 2005-2008 Analog Device Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/blackfin.h> -#undef ALIGN -#undef ENTRY -#undef bfin - -/* If we don't actually load anything into L1 data, this will avoid - * a syntax error. If we do actually load something into L1 data, - * we'll get a linker memory load error (which is what we'd want). - * This is here in the first place so we can quickly test building - * for different CPU's which may lack non-cache L1 data. - */ -#ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE -# define L1_DATA_B_SRAM_SIZE 0 -#endif - -OUTPUT_ARCH(bfin) - -MEMORY -{ - ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN - l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE - l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE -} - -ENTRY(_start) -SECTIONS -{ - .text : - { - cpu/blackfin/start.o (.text .text.*) - __initcode_start = .; - cpu/blackfin/initcode.o (.text .text.*) - __initcode_end = .; - *(.text .text.*) - } >ram - - .rodata : - { - . = ALIGN(4); - *(.rodata .rodata.*) - *(.rodata1) - *(.eh_frame) - . = ALIGN(4); - } >ram - - .data : - { - . = ALIGN(256); - *(.data .data.*) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } >ram - - .u_boot_cmd : - { - ___u_boot_cmd_start = .; - *(.u_boot_cmd) - ___u_boot_cmd_end = .; - } >ram - - .text_l1 : - { - . = ALIGN(4); - __stext_l1 = .; - *(.l1.text) - . = ALIGN(4); - __etext_l1 = .; - } >l1_code AT>ram - __stext_l1_lma = LOADADDR(.text_l1); - - .data_l1 : - { - . = ALIGN(4); - __sdata_l1 = .; - *(.l1.data) - *(.l1.bss) - . = ALIGN(4); - __edata_l1 = .; - } >l1_data AT>ram - __sdata_l1_lma = LOADADDR(.data_l1); - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss .bss.*) - *(COMMON) - __bss_end = .; - } >ram -} diff --git a/board/bf526-ezbrd/.gitignore b/board/bf526-ezbrd/.gitignore deleted file mode 100644 index 945f3245496..00000000000 --- a/board/bf526-ezbrd/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/u-boot.lds diff --git a/board/bf526-ezbrd/Makefile b/board/bf526-ezbrd/Makefile index 88846baf518..a9ff760073b 100644 --- a/board/bf526-ezbrd/Makefile +++ b/board/bf526-ezbrd/Makefile @@ -36,12 +36,9 @@ SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS-y)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -$(obj)u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ - clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf526-ezbrd/config.mk b/board/bf526-ezbrd/config.mk index f4a5a80283e..f85bef5e2a7 100644 --- a/board/bf526-ezbrd/config.mk +++ b/board/bf526-ezbrd/config.mk @@ -26,7 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf526-ezbrd/u-boot.lds.S b/board/bf526-ezbrd/u-boot.lds.S deleted file mode 100644 index 3e8be358da6..00000000000 --- a/board/bf526-ezbrd/u-boot.lds.S +++ /dev/null @@ -1,124 +0,0 @@ -/* - * U-boot - u-boot.lds.S - * - * Copyright (c) 2005-2008 Analog Device Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/blackfin.h> -#undef ALIGN -#undef ENTRY -#undef bfin - -/* If we don't actually load anything into L1 data, this will avoid - * a syntax error. If we do actually load something into L1 data, - * we'll get a linker memory load error (which is what we'd want). - * This is here in the first place so we can quickly test building - * for different CPU's which may lack non-cache L1 data. - */ -#ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE -# define L1_DATA_B_SRAM_SIZE 0 -#endif - -OUTPUT_ARCH(bfin) - -MEMORY -{ - ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN - l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE - l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE -} - -ENTRY(_start) -SECTIONS -{ - .text : - { - cpu/blackfin/start.o (.text .text.*) - __initcode_start = .; - cpu/blackfin/initcode.o (.text .text.*) - __initcode_end = .; - *(.text .text.*) - } >ram - - .rodata : - { - . = ALIGN(4); - *(.rodata .rodata.*) - *(.rodata1) - *(.eh_frame) - . = ALIGN(4); - } >ram - - .data : - { - . = ALIGN(256); - *(.data .data.*) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } >ram - - .u_boot_cmd : - { - ___u_boot_cmd_start = .; - *(.u_boot_cmd) - ___u_boot_cmd_end = .; - } >ram - - .text_l1 : - { - . = ALIGN(4); - __stext_l1 = .; - *(.l1.text) - . = ALIGN(4); - __etext_l1 = .; - } >l1_code AT>ram - __stext_l1_lma = LOADADDR(.text_l1); - - .data_l1 : - { - . = ALIGN(4); - __sdata_l1 = .; - *(.l1.data) - *(.l1.bss) - . = ALIGN(4); - __edata_l1 = .; - } >l1_data AT>ram - __sdata_l1_lma = LOADADDR(.data_l1); - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss .bss.*) - *(COMMON) - __bss_end = .; - } >ram -} diff --git a/board/bf527-ezkit/.gitignore b/board/bf527-ezkit/.gitignore deleted file mode 100644 index 945f3245496..00000000000 --- a/board/bf527-ezkit/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/u-boot.lds diff --git a/board/bf527-ezkit/Makefile b/board/bf527-ezkit/Makefile index c2b98ec74ab..1a2f4b16bbc 100644 --- a/board/bf527-ezkit/Makefile +++ b/board/bf527-ezkit/Makefile @@ -36,12 +36,9 @@ SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS-y)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -$(obj)u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ - clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf527-ezkit/config.mk b/board/bf527-ezkit/config.mk index f4a5a80283e..f85bef5e2a7 100644 --- a/board/bf527-ezkit/config.mk +++ b/board/bf527-ezkit/config.mk @@ -26,7 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf533-ezkit/.gitignore b/board/bf533-ezkit/.gitignore deleted file mode 100644 index 945f3245496..00000000000 --- a/board/bf533-ezkit/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/u-boot.lds diff --git a/board/bf533-ezkit/Makefile b/board/bf533-ezkit/Makefile index 1260277a891..487b737ba85 100644 --- a/board/bf533-ezkit/Makefile +++ b/board/bf533-ezkit/Makefile @@ -35,12 +35,9 @@ SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS-y)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -$(obj)u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ - clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk index c8b9fb8c15e..3c0b46f7214 100644 --- a/board/bf533-ezkit/config.mk +++ b/board/bf533-ezkit/config.mk @@ -26,7 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf533-ezkit/u-boot.lds.S b/board/bf533-ezkit/u-boot.lds.S deleted file mode 100644 index f80f8944b1a..00000000000 --- a/board/bf533-ezkit/u-boot.lds.S +++ /dev/null @@ -1,145 +0,0 @@ -/* - * U-boot - u-boot.lds.S - * - * Copyright (c) 2005-2008 Analog Device Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/blackfin.h> -#undef ALIGN -#undef ENTRY -#undef bfin - -/* If we don't actually load anything into L1 data, this will avoid - * a syntax error. If we do actually load something into L1 data, - * we'll get a linker memory load error (which is what we'd want). - * This is here in the first place so we can quickly test building - * for different CPU's which may lack non-cache L1 data. - */ -#ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE -# define L1_DATA_B_SRAM_SIZE 0 -#endif - -OUTPUT_ARCH(bfin) - -MEMORY -{ - ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN - l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE - l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE -} - -ENTRY(_start) -SECTIONS -{ - .text : - { - cpu/blackfin/start.o (.text .text.*) - -#ifdef ENV_IS_EMBEDDED - /* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ - - cpu/blackfin/traps.o (.text .text.*) - cpu/blackfin/interrupt.o (.text .text.*) - cpu/blackfin/serial.o (.text .text.*) - common/dlmalloc.o (.text .text.*) - lib_generic/crc32.o (.text .text.*) - lib_generic/zlib.o (.text .text.*) - board/bf533-ezkit/bf533-ezkit.o (.text .text.*) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text .text.*) -#endif - - __initcode_start = .; - cpu/blackfin/initcode.o (.text .text.*) - __initcode_end = .; - - *(.text .text.*) - } >ram - - .rodata : - { - . = ALIGN(4); - *(.rodata .rodata.*) - *(.rodata1) - *(.eh_frame) - . = ALIGN(4); - } >ram - - .data : - { - . = ALIGN(256); - *(.data .data.*) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } >ram - - .u_boot_cmd : - { - ___u_boot_cmd_start = .; - *(.u_boot_cmd) - ___u_boot_cmd_end = .; - } >ram - - .text_l1 : - { - . = ALIGN(4); - __stext_l1 = .; - *(.l1.text) - . = ALIGN(4); - __etext_l1 = .; - } >l1_code AT>ram - __stext_l1_lma = LOADADDR(.text_l1); - - .data_l1 : - { - . = ALIGN(4); - __sdata_l1 = .; - *(.l1.data) - *(.l1.bss) - . = ALIGN(4); - __edata_l1 = .; - } >l1_data AT>ram - __sdata_l1_lma = LOADADDR(.data_l1); - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss .bss.*) - *(COMMON) - __bss_end = .; - } >ram -} diff --git a/board/bf533-stamp/.gitignore b/board/bf533-stamp/.gitignore deleted file mode 100644 index 945f3245496..00000000000 --- a/board/bf533-stamp/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/u-boot.lds diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile index 0f528375233..dbba12b848e 100644 --- a/board/bf533-stamp/Makefile +++ b/board/bf533-stamp/Makefile @@ -36,12 +36,9 @@ SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS-y)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -$(obj)u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ - clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk index c8b9fb8c15e..3c0b46f7214 100644 --- a/board/bf533-stamp/config.mk +++ b/board/bf533-stamp/config.mk @@ -26,7 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf533-stamp/u-boot.lds.S b/board/bf533-stamp/u-boot.lds.S deleted file mode 100644 index 8ddfa81dad0..00000000000 --- a/board/bf533-stamp/u-boot.lds.S +++ /dev/null @@ -1,143 +0,0 @@ -/* - * U-boot - u-boot.lds.S - * - * Copyright (c) 2005-2008 Analog Device Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/blackfin.h> -#undef ALIGN -#undef ENTRY -#undef bfin - -/* If we don't actually load anything into L1 data, this will avoid - * a syntax error. If we do actually load something into L1 data, - * we'll get a linker memory load error (which is what we'd want). - * This is here in the first place so we can quickly test building - * for different CPU's which may lack non-cache L1 data. - */ -#ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE -# define L1_DATA_B_SRAM_SIZE 0 -#endif - -OUTPUT_ARCH(bfin) - -MEMORY -{ - ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN - l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE - l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE -} - -ENTRY(_start) -SECTIONS -{ - .text : - { - cpu/blackfin/start.o (.text .text.*) - -#ifdef ENV_IS_EMBEDDED - /* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ - - cpu/blackfin/traps.o (.text .text.*) - cpu/blackfin/interrupt.o (.text .text.*) - cpu/blackfin/serial.o (.text .text.*) - common/dlmalloc.o (.text .text.*) - lib_generic/crc32.o (.text .text.*) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text .text.*) -#endif - - __initcode_start = .; - cpu/blackfin/initcode.o (.text .text.*) - __initcode_end = .; - - *(.text .text.*) - } >ram - - .rodata : - { - . = ALIGN(4); - *(.rodata .rodata.*) - *(.rodata1) - *(.eh_frame) - . = ALIGN(4); - } >ram - - .data : - { - . = ALIGN(256); - *(.data .data.*) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } >ram - - .u_boot_cmd : - { - ___u_boot_cmd_start = .; - *(.u_boot_cmd) - ___u_boot_cmd_end = .; - } >ram - - .text_l1 : - { - . = ALIGN(4); - __stext_l1 = .; - *(.l1.text) - . = ALIGN(4); - __etext_l1 = .; - } >l1_code AT>ram - __stext_l1_lma = LOADADDR(.text_l1); - - .data_l1 : - { - . = ALIGN(4); - __sdata_l1 = .; - *(.l1.data) - *(.l1.bss) - . = ALIGN(4); - __edata_l1 = .; - } >l1_data AT>ram - __sdata_l1_lma = LOADADDR(.data_l1); - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss .bss.*) - *(COMMON) - __bss_end = .; - } >ram -} diff --git a/board/bf537-minotaur/Makefile b/board/bf537-minotaur/Makefile new file mode 100644 index 00000000000..f2bd2c247d4 --- /dev/null +++ b/board/bf537-minotaur/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/bf537-minotaur/bf537-minotaur.c b/board/bf537-minotaur/bf537-minotaur.c new file mode 100644 index 00000000000..71b452a4f88 --- /dev/null +++ b/board/bf537-minotaur/bf537-minotaur.c @@ -0,0 +1,56 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2005-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <config.h> +#include <command.h> +#include <netdev.h> +#include <net.h> +#include <asm/blackfin.h> +#include <asm/net.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: CSP BF537 Minotaur board\n"); + printf(" Support: http://www.camsig.co.uk/\n"); + return 0; +} + +phys_size_t initdram(int board_type) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return gd->bd->bi_memsize; +} + +#ifdef CONFIG_BFIN_MAC +static void board_init_enetaddr(uchar *mac_addr) +{ + puts("Warning: Generating 'random' MAC address\n"); + bfin_gen_rand_mac(mac_addr); + eth_setenv_enetaddr("ethaddr", mac_addr); +} + +int board_eth_init(bd_t *bis) +{ + return bfin_EMAC_initialize(bis); +} +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_BFIN_MAC + uchar enetaddr[6]; + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + board_init_enetaddr(enetaddr); +#endif + + return 0; +} diff --git a/board/bf537-minotaur/config.mk b/board/bf537-minotaur/config.mk new file mode 100644 index 00000000000..d8308433b00 --- /dev/null +++ b/board/bf537-minotaur/config.mk @@ -0,0 +1,31 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf537-pnav/Makefile b/board/bf537-pnav/Makefile new file mode 100644 index 00000000000..f2bd2c247d4 --- /dev/null +++ b/board/bf537-pnav/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/bf537-pnav/bf537-pnav.c b/board/bf537-pnav/bf537-pnav.c new file mode 100644 index 00000000000..12cfefa8ffa --- /dev/null +++ b/board/bf537-pnav/bf537-pnav.c @@ -0,0 +1,56 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2005-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <config.h> +#include <command.h> +#include <netdev.h> +#include <net.h> +#include <asm/blackfin.h> +#include <asm/net.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: ADI BF537 PNAV board\n"); + printf(" Support: http://blackfin.uclinux.org/\n"); + return 0; +} + +phys_size_t initdram(int board_type) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return gd->bd->bi_memsize; +} + +#ifdef CONFIG_BFIN_MAC +static void board_init_enetaddr(uchar *mac_addr) +{ + puts("Warning: Generating 'random' MAC address\n"); + bfin_gen_rand_mac(mac_addr); + eth_setenv_enetaddr("ethaddr", mac_addr); +} + +int board_eth_init(bd_t *bis) +{ + return bfin_EMAC_initialize(bis); +} +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_BFIN_MAC + uchar enetaddr[6]; + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + board_init_enetaddr(enetaddr); +#endif + + return 0; +} diff --git a/board/bf537-pnav/config.mk b/board/bf537-pnav/config.mk new file mode 100644 index 00000000000..eaa09ff7958 --- /dev/null +++ b/board/bf537-pnav/config.mk @@ -0,0 +1,30 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +# Set some default LDR flags based on boot mode. +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf537-srv1/Makefile b/board/bf537-srv1/Makefile new file mode 100644 index 00000000000..f2bd2c247d4 --- /dev/null +++ b/board/bf537-srv1/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/bf537-srv1/bf537-srv1.c b/board/bf537-srv1/bf537-srv1.c new file mode 100644 index 00000000000..5ad39cc9357 --- /dev/null +++ b/board/bf537-srv1/bf537-srv1.c @@ -0,0 +1,56 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2005-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <config.h> +#include <command.h> +#include <netdev.h> +#include <net.h> +#include <asm/blackfin.h> +#include <asm/net.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: Surveyor SRV1 board\n"); + printf(" Support: http://www.surveyor.com/\n"); + return 0; +} + +phys_size_t initdram(int board_type) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return gd->bd->bi_memsize; +} + +#ifdef CONFIG_BFIN_MAC +static void board_init_enetaddr(uchar *mac_addr) +{ + puts("Warning: Generating 'random' MAC address\n"); + bfin_gen_rand_mac(mac_addr); + eth_setenv_enetaddr("ethaddr", mac_addr); +} + +int board_eth_init(bd_t *bis) +{ + return bfin_EMAC_initialize(bis); +} +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_BFIN_MAC + uchar enetaddr[6]; + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + board_init_enetaddr(enetaddr); +#endif + + return 0; +} diff --git a/board/bf537-srv1/config.mk b/board/bf537-srv1/config.mk new file mode 100644 index 00000000000..d8308433b00 --- /dev/null +++ b/board/bf537-srv1/config.mk @@ -0,0 +1,31 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf537-stamp/.gitignore b/board/bf537-stamp/.gitignore deleted file mode 100644 index 945f3245496..00000000000 --- a/board/bf537-stamp/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/u-boot.lds diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile index 1dbf406b29d..4c9e015a13e 100644 --- a/board/bf537-stamp/Makefile +++ b/board/bf537-stamp/Makefile @@ -39,12 +39,9 @@ SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS-y)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -$(obj)u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ - clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk index 719b97e2541..bc142574896 100644 --- a/board/bf537-stamp/config.mk +++ b/board/bf537-stamp/config.mk @@ -26,7 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf537-stamp/u-boot.lds.S b/board/bf537-stamp/u-boot.lds.S deleted file mode 100644 index 8ddfa81dad0..00000000000 --- a/board/bf537-stamp/u-boot.lds.S +++ /dev/null @@ -1,143 +0,0 @@ -/* - * U-boot - u-boot.lds.S - * - * Copyright (c) 2005-2008 Analog Device Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/blackfin.h> -#undef ALIGN -#undef ENTRY -#undef bfin - -/* If we don't actually load anything into L1 data, this will avoid - * a syntax error. If we do actually load something into L1 data, - * we'll get a linker memory load error (which is what we'd want). - * This is here in the first place so we can quickly test building - * for different CPU's which may lack non-cache L1 data. - */ -#ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE -# define L1_DATA_B_SRAM_SIZE 0 -#endif - -OUTPUT_ARCH(bfin) - -MEMORY -{ - ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN - l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE - l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE -} - -ENTRY(_start) -SECTIONS -{ - .text : - { - cpu/blackfin/start.o (.text .text.*) - -#ifdef ENV_IS_EMBEDDED - /* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ - - cpu/blackfin/traps.o (.text .text.*) - cpu/blackfin/interrupt.o (.text .text.*) - cpu/blackfin/serial.o (.text .text.*) - common/dlmalloc.o (.text .text.*) - lib_generic/crc32.o (.text .text.*) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text .text.*) -#endif - - __initcode_start = .; - cpu/blackfin/initcode.o (.text .text.*) - __initcode_end = .; - - *(.text .text.*) - } >ram - - .rodata : - { - . = ALIGN(4); - *(.rodata .rodata.*) - *(.rodata1) - *(.eh_frame) - . = ALIGN(4); - } >ram - - .data : - { - . = ALIGN(256); - *(.data .data.*) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } >ram - - .u_boot_cmd : - { - ___u_boot_cmd_start = .; - *(.u_boot_cmd) - ___u_boot_cmd_end = .; - } >ram - - .text_l1 : - { - . = ALIGN(4); - __stext_l1 = .; - *(.l1.text) - . = ALIGN(4); - __etext_l1 = .; - } >l1_code AT>ram - __stext_l1_lma = LOADADDR(.text_l1); - - .data_l1 : - { - . = ALIGN(4); - __sdata_l1 = .; - *(.l1.data) - *(.l1.bss) - . = ALIGN(4); - __edata_l1 = .; - } >l1_data AT>ram - __sdata_l1_lma = LOADADDR(.data_l1); - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss .bss.*) - *(COMMON) - __bss_end = .; - } >ram -} diff --git a/board/bf538f-ezkit/.gitignore b/board/bf538f-ezkit/.gitignore deleted file mode 100644 index 945f3245496..00000000000 --- a/board/bf538f-ezkit/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/u-boot.lds diff --git a/board/bf538f-ezkit/Makefile b/board/bf538f-ezkit/Makefile index 1b217288b9f..f2bd2c247d4 100644 --- a/board/bf538f-ezkit/Makefile +++ b/board/bf538f-ezkit/Makefile @@ -35,12 +35,9 @@ SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS-y)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -$(obj)u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ - clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf538f-ezkit/config.mk b/board/bf538f-ezkit/config.mk index c8b9fb8c15e..3c0b46f7214 100644 --- a/board/bf538f-ezkit/config.mk +++ b/board/bf538f-ezkit/config.mk @@ -26,7 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf538f-ezkit/u-boot.lds.S b/board/bf538f-ezkit/u-boot.lds.S deleted file mode 100644 index 8ddfa81dad0..00000000000 --- a/board/bf538f-ezkit/u-boot.lds.S +++ /dev/null @@ -1,143 +0,0 @@ -/* - * U-boot - u-boot.lds.S - * - * Copyright (c) 2005-2008 Analog Device Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/blackfin.h> -#undef ALIGN -#undef ENTRY -#undef bfin - -/* If we don't actually load anything into L1 data, this will avoid - * a syntax error. If we do actually load something into L1 data, - * we'll get a linker memory load error (which is what we'd want). - * This is here in the first place so we can quickly test building - * for different CPU's which may lack non-cache L1 data. - */ -#ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE -# define L1_DATA_B_SRAM_SIZE 0 -#endif - -OUTPUT_ARCH(bfin) - -MEMORY -{ - ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN - l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE - l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE -} - -ENTRY(_start) -SECTIONS -{ - .text : - { - cpu/blackfin/start.o (.text .text.*) - -#ifdef ENV_IS_EMBEDDED - /* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ - - cpu/blackfin/traps.o (.text .text.*) - cpu/blackfin/interrupt.o (.text .text.*) - cpu/blackfin/serial.o (.text .text.*) - common/dlmalloc.o (.text .text.*) - lib_generic/crc32.o (.text .text.*) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text .text.*) -#endif - - __initcode_start = .; - cpu/blackfin/initcode.o (.text .text.*) - __initcode_end = .; - - *(.text .text.*) - } >ram - - .rodata : - { - . = ALIGN(4); - *(.rodata .rodata.*) - *(.rodata1) - *(.eh_frame) - . = ALIGN(4); - } >ram - - .data : - { - . = ALIGN(256); - *(.data .data.*) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } >ram - - .u_boot_cmd : - { - ___u_boot_cmd_start = .; - *(.u_boot_cmd) - ___u_boot_cmd_end = .; - } >ram - - .text_l1 : - { - . = ALIGN(4); - __stext_l1 = .; - *(.l1.text) - . = ALIGN(4); - __etext_l1 = .; - } >l1_code AT>ram - __stext_l1_lma = LOADADDR(.text_l1); - - .data_l1 : - { - . = ALIGN(4); - __sdata_l1 = .; - *(.l1.data) - *(.l1.bss) - . = ALIGN(4); - __edata_l1 = .; - } >l1_data AT>ram - __sdata_l1_lma = LOADADDR(.data_l1); - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss .bss.*) - *(COMMON) - __bss_end = .; - } >ram -} diff --git a/board/bf548-ezkit/.gitignore b/board/bf548-ezkit/.gitignore deleted file mode 100644 index 945f3245496..00000000000 --- a/board/bf548-ezkit/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/u-boot.lds diff --git a/board/bf548-ezkit/Makefile b/board/bf548-ezkit/Makefile index c2b98ec74ab..1a2f4b16bbc 100644 --- a/board/bf548-ezkit/Makefile +++ b/board/bf548-ezkit/Makefile @@ -36,12 +36,9 @@ SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS-y)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -$(obj)u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ - clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf548-ezkit/config.mk b/board/bf548-ezkit/config.mk index 8b471f60deb..42ff9466730 100644 --- a/board/bf548-ezkit/config.mk +++ b/board/bf548-ezkit/config.mk @@ -26,7 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --dma 6 diff --git a/board/bf548-ezkit/u-boot.lds.S b/board/bf548-ezkit/u-boot.lds.S deleted file mode 100644 index 3e8be358da6..00000000000 --- a/board/bf548-ezkit/u-boot.lds.S +++ /dev/null @@ -1,124 +0,0 @@ -/* - * U-boot - u-boot.lds.S - * - * Copyright (c) 2005-2008 Analog Device Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/blackfin.h> -#undef ALIGN -#undef ENTRY -#undef bfin - -/* If we don't actually load anything into L1 data, this will avoid - * a syntax error. If we do actually load something into L1 data, - * we'll get a linker memory load error (which is what we'd want). - * This is here in the first place so we can quickly test building - * for different CPU's which may lack non-cache L1 data. - */ -#ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE -# define L1_DATA_B_SRAM_SIZE 0 -#endif - -OUTPUT_ARCH(bfin) - -MEMORY -{ - ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN - l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE - l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE -} - -ENTRY(_start) -SECTIONS -{ - .text : - { - cpu/blackfin/start.o (.text .text.*) - __initcode_start = .; - cpu/blackfin/initcode.o (.text .text.*) - __initcode_end = .; - *(.text .text.*) - } >ram - - .rodata : - { - . = ALIGN(4); - *(.rodata .rodata.*) - *(.rodata1) - *(.eh_frame) - . = ALIGN(4); - } >ram - - .data : - { - . = ALIGN(256); - *(.data .data.*) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } >ram - - .u_boot_cmd : - { - ___u_boot_cmd_start = .; - *(.u_boot_cmd) - ___u_boot_cmd_end = .; - } >ram - - .text_l1 : - { - . = ALIGN(4); - __stext_l1 = .; - *(.l1.text) - . = ALIGN(4); - __etext_l1 = .; - } >l1_code AT>ram - __stext_l1_lma = LOADADDR(.text_l1); - - .data_l1 : - { - . = ALIGN(4); - __sdata_l1 = .; - *(.l1.data) - *(.l1.bss) - . = ALIGN(4); - __edata_l1 = .; - } >l1_data AT>ram - __sdata_l1_lma = LOADADDR(.data_l1); - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss .bss.*) - *(COMMON) - __bss_end = .; - } >ram -} diff --git a/board/bf561-ezkit/.gitignore b/board/bf561-ezkit/.gitignore deleted file mode 100644 index 945f3245496..00000000000 --- a/board/bf561-ezkit/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/u-boot.lds diff --git a/board/bf561-ezkit/Makefile b/board/bf561-ezkit/Makefile index daebb74578b..bfeaf791e19 100644 --- a/board/bf561-ezkit/Makefile +++ b/board/bf561-ezkit/Makefile @@ -35,12 +35,9 @@ SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS-y)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -$(obj)u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ - clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk index 710809a9e39..cfad21a2a46 100644 --- a/board/bf561-ezkit/config.mk +++ b/board/bf561-ezkit/config.mk @@ -26,7 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/bf561-ezkit/u-boot.lds.S b/board/bf561-ezkit/u-boot.lds.S deleted file mode 100644 index e6d3ddca2f4..00000000000 --- a/board/bf561-ezkit/u-boot.lds.S +++ /dev/null @@ -1,152 +0,0 @@ -/* - * U-boot - u-boot.lds.S - * - * Copyright (c) 2005-2008 Analog Device Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/blackfin.h> -#undef ALIGN -#undef ENTRY -#undef bfin - -/* If we don't actually load anything into L1 data, this will avoid - * a syntax error. If we do actually load something into L1 data, - * we'll get a linker memory load error (which is what we'd want). - * This is here in the first place so we can quickly test building - * for different CPU's which may lack non-cache L1 data. - */ -#ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE -# define L1_DATA_B_SRAM_SIZE 0 -#endif - -/* The 0xC offset is so we don't clobber the tiny LDR jump block. */ -#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1 -# define L1_CODE_ORIGIN L1_INST_SRAM -#else -# define L1_CODE_ORIGIN L1_INST_SRAM + 0xC -#endif - -OUTPUT_ARCH(bfin) - -MEMORY -{ - ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN - l1_code : ORIGIN = L1_CODE_ORIGIN, LENGTH = L1_INST_SRAM_SIZE - l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE -} - -ENTRY(_start) -SECTIONS -{ - .text : - { - cpu/blackfin/start.o (.text .text.*) - -#ifdef ENV_IS_EMBEDDED - /* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ - - cpu/blackfin/traps.o (.text .text.*) - cpu/blackfin/interrupt.o (.text .text.*) - cpu/blackfin/serial.o (.text .text.*) - common/dlmalloc.o (.text .text.*) - lib_generic/crc32.o (.text .text.*) - lib_generic/zlib.o (.text .text.*) - board/bf561-ezkit/bf561-ezkit.o (.text .text.*) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text .text.*) -#endif - - __initcode_start = .; - cpu/blackfin/initcode.o (.text .text.*) - __initcode_end = .; - - *(.text .text.*) - } >ram - - .rodata : - { - . = ALIGN(4); - *(.rodata .rodata.*) - *(.rodata1) - *(.eh_frame) - . = ALIGN(4); - } >ram - - .data : - { - . = ALIGN(256); - *(.data .data.*) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } >ram - - .u_boot_cmd : - { - ___u_boot_cmd_start = .; - *(.u_boot_cmd) - ___u_boot_cmd_end = .; - } >ram - - .text_l1 : - { - . = ALIGN(4); - __stext_l1 = .; - *(.l1.text) - . = ALIGN(4); - __etext_l1 = .; - } >l1_code AT>ram - __stext_l1_lma = LOADADDR(.text_l1); - - .data_l1 : - { - . = ALIGN(4); - __sdata_l1 = .; - *(.l1.data) - *(.l1.bss) - . = ALIGN(4); - __edata_l1 = .; - } >l1_data AT>ram - __sdata_l1_lma = LOADADDR(.data_l1); - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss .bss.*) - *(COMMON) - __bss_end = .; - } >ram -} diff --git a/board/blackstamp/Makefile b/board/blackstamp/Makefile new file mode 100644 index 00000000000..f2bd2c247d4 --- /dev/null +++ b/board/blackstamp/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/blackstamp/blackstamp.c b/board/blackstamp/blackstamp.c new file mode 100644 index 00000000000..b671899e06c --- /dev/null +++ b/board/blackstamp/blackstamp.c @@ -0,0 +1,46 @@ +/* + * U-boot - blackstamp.c BlackStamp board specific routines + * Most code stolen from boards/bf533-stamp/bf533-stamp.c + * Edited to the BlackStamp by Ben Matthews for UR LLE + * + * Copyright (c) 2005-2009 Analog Devices Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: BlackStamp\n"); + printf("Support: http://blackfin.uclinux.org/gf/project/blackstamp/\n"); + return 0; +} + +phys_size_t initdram(int board_type) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return gd->bd->bi_memsize; +} + +#ifdef SHARED_RESOURCES +void swap_to(int device_id) +{ + bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0); + SSYNC(); + if (device_id == ETHERNET) + bfin_write_FIO_FLAG_S(PF0); + else if (device_id == FLASH) + bfin_write_FIO_FLAG_C(PF0); + else + printf("Unknown device to switch\n"); + SSYNC(); +} +#endif diff --git a/board/blackstamp/config.mk b/board/blackstamp/config.mk new file mode 100644 index 00000000000..eaa09ff7958 --- /dev/null +++ b/board/blackstamp/config.mk @@ -0,0 +1,30 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +# Set some default LDR flags based on boot mode. +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/cm-bf527/Makefile b/board/cm-bf527/Makefile new file mode 100644 index 00000000000..c2cd244cf29 --- /dev/null +++ b/board/cm-bf527/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o gpio.o gpio_cfi_flash.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/cm-bf527/cm-bf527.c b/board/cm-bf527/cm-bf527.c new file mode 100644 index 00000000000..db1cf9028cb --- /dev/null +++ b/board/cm-bf527/cm-bf527.c @@ -0,0 +1,79 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2005-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <config.h> +#include <net.h> +#include <netdev.h> +#include <asm/blackfin.h> +#include <asm/net.h> +#include <asm/mach-common/bits/otp.h> +#include "gpio_cfi_flash.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: Bluetechnix CM-BF527 board\n"); + printf(" Support: http://www.bluetechnix.at/\n"); + return 0; +} + +phys_size_t initdram(int board_type) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return gd->bd->bi_memsize; +} + +#ifdef CONFIG_BFIN_MAC +static void board_init_enetaddr(uchar *mac_addr) +{ + bool valid_mac = false; + + /* the MAC is stored in OTP memory page 0xDF */ + uint32_t ret; + uint64_t otp_mac; + + ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac); + if (!(ret & OTP_MASTER_ERROR)) { + uchar *otp_mac_p = (uchar *)&otp_mac; + + for (ret = 0; ret < 6; ++ret) + mac_addr[ret] = otp_mac_p[5 - ret]; + + if (is_valid_ether_addr(mac_addr)) + valid_mac = true; + } + + if (!valid_mac) { + puts("Warning: Generating 'random' MAC address\n"); + bfin_gen_rand_mac(mac_addr); + } + + eth_setenv_enetaddr("ethaddr", mac_addr); +} + +int board_eth_init(bd_t *bis) +{ + return bfin_EMAC_initialize(bis); +} +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_BFIN_MAC + uchar enetaddr[6]; + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + board_init_enetaddr(enetaddr); +#endif + + gpio_cfi_flash_init(); + + return 0; +} diff --git a/board/cm-bf527/config.mk b/board/cm-bf527/config.mk new file mode 100644 index 00000000000..f85bef5e2a7 --- /dev/null +++ b/board/cm-bf527/config.mk @@ -0,0 +1,33 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 + +# Set some default LDR flags based on boot mode. +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/cm-bf527/gpio.c b/board/cm-bf527/gpio.c new file mode 100644 index 00000000000..dcf641b6a9b --- /dev/null +++ b/board/cm-bf527/gpio.c @@ -0,0 +1,74 @@ +/* + * Control GPIO pins on the fly + * + * Copyright (c) 2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <command.h> + +#include <asm/blackfin.h> + +int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc != 3) { + show_usage: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* parse the behavior */ + ulong port_cmd = 0; + switch (argv[1][0]) { + case 'i': break; + case 's': port_cmd = (PORTFIO_SET - PORTFIO); break; + case 'c': port_cmd = (PORTFIO_CLEAR - PORTFIO); break; + case 't': port_cmd = (PORTFIO_TOGGLE - PORTFIO); break; + default: goto show_usage; + } + + /* parse the pin with format: [p]<fgh><#> */ + const char *str_pin = argv[2]; + + /* grab the [p]<fgh> portion */ + ulong port_base; + if (*str_pin == 'p') ++str_pin; + switch (*str_pin) { + case 'f': port_base = PORTFIO; break; + case 'g': port_base = PORTGIO; break; + case 'h': port_base = PORTHIO; break; + default: goto show_usage; + } + + /* grab the <#> portion */ + ulong pin = simple_strtoul(str_pin+1, NULL, 10); + ulong pin_mask = (1 << pin); + if (pin > 15) + goto show_usage; + + /* finally, let's do it: set direction and exec command */ + switch (*str_pin) { + case 'f': bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~pin_mask); break; + case 'g': bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~pin_mask); break; + case 'h': bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~pin_mask); break; + } + + ulong port_dir = port_base + (PORTFIO_DIR - PORTFIO); + if (argv[1][0] == 'i') + bfin_write16(port_dir, bfin_read16(port_dir) & ~pin_mask); + else { + bfin_write16(port_dir, bfin_read16(port_dir) | pin_mask); + bfin_write16(port_base + port_cmd, pin_mask); + } + + printf("gpio: pin %li on port %c has been %c\n", pin, *str_pin, argv[1][0]); + + return 0; +} + +U_BOOT_CMD(gpio, 3, 0, do_gpio, + "gpio - set/clear/toggle gpio output pins\n", + "<s|c|t> <port><pin>\n" + " - set/clear/toggle the specified pin\n"); diff --git a/board/cm-bf527/gpio_cfi_flash.c b/board/cm-bf527/gpio_cfi_flash.c new file mode 100644 index 00000000000..565d9003eff --- /dev/null +++ b/board/cm-bf527/gpio_cfi_flash.c @@ -0,0 +1,63 @@ +/* + * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support + * + * Copyright (c) 2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <asm/blackfin.h> +#include <asm/io.h> +#include "gpio_cfi_flash.h" + +#define GPIO_PIN_1 PH9 +#define GPIO_MASK_1 (1 << 21) +#define GPIO_PIN_2 PG11 +#define GPIO_MASK_2 (1 << 22) +#define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2) + +void *gpio_cfi_flash_swizzle(void *vaddr) +{ + unsigned long addr = (unsigned long)vaddr; + + if (addr & GPIO_MASK_1) + bfin_write_PORTHIO_SET(GPIO_PIN_1); + else + bfin_write_PORTHIO_CLEAR(GPIO_PIN_1); + +#ifdef GPIO_MASK_2 + if (addr & GPIO_MASK_2) + bfin_write_PORTGIO_SET(GPIO_PIN_2); + else + bfin_write_PORTGIO_CLEAR(GPIO_PIN_2); +#endif + + SSYNC(); + + return (void *)(addr & ~GPIO_MASK); +} + +#define __raw_writeq(value, addr) *(volatile u64 *)addr = value +#define __raw_readq(addr) *(volatile u64 *)addr + +#define MAKE_FLASH(size, sfx) \ +void flash_write##size(u##size value, void *addr) \ +{ \ + __raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \ +} \ +u##size flash_read##size(void *addr) \ +{ \ + return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \ +} +MAKE_FLASH(8, b) /* flash_write8() flash_read8() */ +MAKE_FLASH(16, w) /* flash_write16() flash_write16() */ +MAKE_FLASH(32, l) /* flash_write32() flash_write32() */ +MAKE_FLASH(64, q) /* flash_write64() flash_write64() */ + +void gpio_cfi_flash_init(void) +{ + bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() | GPIO_PIN_1); + bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | GPIO_PIN_2); + gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); +} diff --git a/board/cm-bf527/gpio_cfi_flash.h b/board/cm-bf527/gpio_cfi_flash.h new file mode 100644 index 00000000000..5211e972ad2 --- /dev/null +++ b/board/cm-bf527/gpio_cfi_flash.h @@ -0,0 +1,10 @@ +/* + * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support + * + * Copyright (c) 2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +void *gpio_cfi_flash_swizzle(void *vaddr); +void gpio_cfi_flash_init(void); diff --git a/board/cm-bf533/Makefile b/board/cm-bf533/Makefile new file mode 100644 index 00000000000..f2bd2c247d4 --- /dev/null +++ b/board/cm-bf533/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/cm-bf533/cm-bf533.c b/board/cm-bf533/cm-bf533.c new file mode 100644 index 00000000000..7eb761dcc88 --- /dev/null +++ b/board/cm-bf533/cm-bf533.c @@ -0,0 +1,25 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2005-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: Bluetechnix CM-BF533 board\n"); + printf(" Support: http://www.bluetechnix.at/\n"); + return 0; +} + +phys_size_t initdram(int board_type) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return gd->bd->bi_memsize; +} diff --git a/board/cm-bf533/config.mk b/board/cm-bf533/config.mk new file mode 100644 index 00000000000..3c0b46f7214 --- /dev/null +++ b/board/cm-bf533/config.mk @@ -0,0 +1,34 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/cm-bf537e/Makefile b/board/cm-bf537e/Makefile new file mode 100644 index 00000000000..3812ba1e721 --- /dev/null +++ b/board/cm-bf537e/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o flash.o gpio_cfi_flash.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/cm-bf537e/cm-bf537e.c b/board/cm-bf537e/cm-bf537e.c new file mode 100644 index 00000000000..d1ca0a420fd --- /dev/null +++ b/board/cm-bf537e/cm-bf537e.c @@ -0,0 +1,59 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2005-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <config.h> +#include <command.h> +#include <net.h> +#include <netdev.h> +#include <asm/blackfin.h> +#include <asm/net.h> +#include "gpio_cfi_flash.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: Bluetechnix CM-BF537E board\n"); + printf(" Support: http://www.bluetechnix.at/\n"); + return 0; +} + +phys_size_t initdram(int board_type) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return gd->bd->bi_memsize; +} + +#ifdef CONFIG_BFIN_MAC +static void board_init_enetaddr(uchar *mac_addr) +{ + puts("Warning: Generating 'random' MAC address\n"); + bfin_gen_rand_mac(mac_addr); + eth_setenv_enetaddr("ethaddr", mac_addr); +} + +int board_eth_init(bd_t *bis) +{ + return bfin_EMAC_initialize(bis); +} +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_BFIN_MAC + uchar enetaddr[6]; + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + board_init_enetaddr(enetaddr); +#endif + + gpio_cfi_flash_init(); + + return 0; +} diff --git a/board/cm-bf537e/config.mk b/board/cm-bf537e/config.mk new file mode 100644 index 00000000000..3c0b46f7214 --- /dev/null +++ b/board/cm-bf537e/config.mk @@ -0,0 +1,34 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/cm-bf537e/flash.c b/board/cm-bf537e/flash.c new file mode 100644 index 00000000000..25aeed264a0 --- /dev/null +++ b/board/cm-bf537e/flash.c @@ -0,0 +1,34 @@ +/* + * flash.c - helper commands for working with GPIO-assisted flash + * + * Copyright (c) 2005-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <command.h> +#include <asm/blackfin.h> +#include "gpio_cfi_flash.h" + +int do_pf(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong faddr = CONFIG_SYS_FLASH_BASE; + ushort data; + ulong dflg; + + if (argc > 1) { + dflg = simple_strtoul(argv[1], NULL, 16); + faddr |= (dflg << 21); + gpio_cfi_flash_swizzle((void *)faddr); + } else { + data = bfin_read_PORTFIO(); + printf("Port F data %04x (PF4:%i)\n", data, !!(data & PF4)); + } + + return 0; +} + +U_BOOT_CMD(pf, 3, 0, do_pf, + "set/clear PF4 GPIO flash bank switch\n", + "<pf4> - set PF4 GPIO pin state\n"); diff --git a/board/cm-bf537e/gpio_cfi_flash.c b/board/cm-bf537e/gpio_cfi_flash.c new file mode 100644 index 00000000000..bb35169c521 --- /dev/null +++ b/board/cm-bf537e/gpio_cfi_flash.c @@ -0,0 +1,60 @@ +/* + * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support + * + * Copyright (c) 2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <asm/blackfin.h> +#include <asm/io.h> +#include "gpio_cfi_flash.h" + +#define GPIO_PIN_1 PF4 +#define GPIO_MASK_1 (1 << 21) +#define GPIO_MASK (GPIO_MASK_1) + +void *gpio_cfi_flash_swizzle(void *vaddr) +{ + unsigned long addr = (unsigned long)vaddr; + + if (addr & GPIO_MASK_1) + bfin_write_PORTFIO_SET(GPIO_PIN_1); + else + bfin_write_PORTFIO_CLEAR(GPIO_PIN_1); + +#ifdef GPIO_MASK_2 + if (addr & GPIO_MASK_2) + bfin_write_PORTGIO_SET(GPIO_PIN_2); + else + bfin_write_PORTGIO_CLEAR(GPIO_PIN_2); +#endif + + SSYNC(); + + return (void *)(addr & ~GPIO_MASK); +} + +#define __raw_writeq(value, addr) *(volatile u64 *)addr = value +#define __raw_readq(addr) *(volatile u64 *)addr + +#define MAKE_FLASH(size, sfx) \ +void flash_write##size(u##size value, void *addr) \ +{ \ + __raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \ +} \ +u##size flash_read##size(void *addr) \ +{ \ + return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \ +} +MAKE_FLASH(8, b) /* flash_write8() flash_read8() */ +MAKE_FLASH(16, w) /* flash_write16() flash_write16() */ +MAKE_FLASH(32, l) /* flash_write32() flash_write32() */ +MAKE_FLASH(64, q) /* flash_write64() flash_write64() */ + +void gpio_cfi_flash_init(void) +{ + bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | GPIO_PIN_1); + gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); +} diff --git a/board/cm-bf537e/gpio_cfi_flash.h b/board/cm-bf537e/gpio_cfi_flash.h new file mode 100644 index 00000000000..5211e972ad2 --- /dev/null +++ b/board/cm-bf537e/gpio_cfi_flash.h @@ -0,0 +1,10 @@ +/* + * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support + * + * Copyright (c) 2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +void *gpio_cfi_flash_swizzle(void *vaddr); +void gpio_cfi_flash_init(void); diff --git a/board/cm-bf548/Makefile b/board/cm-bf548/Makefile new file mode 100644 index 00000000000..1a2f4b16bbc --- /dev/null +++ b/board/cm-bf548/Makefile @@ -0,0 +1,55 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +COBJS-$(CONFIG_VIDEO) += video.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/cm-bf548/cm-bf548.c b/board/cm-bf548/cm-bf548.c new file mode 100644 index 00000000000..1c2660046fb --- /dev/null +++ b/board/cm-bf548/cm-bf548.c @@ -0,0 +1,79 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2005-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <config.h> +#include <command.h> +#include <asm/blackfin.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: Bluetechnix CM-BF548 board\n"); + printf(" Support: http://www.bluetechnix.at/\n"); + return 0; +} + +phys_size_t initdram(int board_type) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return gd->bd->bi_memsize; +} + +int board_early_init_f(void) +{ + /* Port H: PH8 - PH13 == A4 - A9 + * address lines of the parallel asynchronous memory interface + */ + + /************************************************ + * configure GPIO * + * set port H function enable register * + * configure PH8-PH13 as peripheral (not GPIO) * + *************************************************/ + bfin_write_PORTH_FER(0x3F03); + + /************************************************ + * set port H MUX to configure PH8-PH13 * + * 1st Function (MUX = 00) (bits 16-27 == 0) * + * Set to address signals A4-A9 * + *************************************************/ + bfin_write_PORTH_MUX(0); + + /************************************************ + * set port H direction register * + * enable PH8-PH13 as outputs * + *************************************************/ + bfin_write_PORTH_DIR_SET(0x3F00); + + /* Port I: PI0 - PH14 == A10 - A24 + * address lines of the parallel asynchronous memory interface + */ + + /************************************************ + * set port I function enable register * + * configure PI0-PI14 as peripheral (not GPIO) * + *************************************************/ + bfin_write_PORTI_FER(0x7fff); + + /************************************************** + * set PORT I MUX to configure PI14-PI0 as * + * 1st Function (MUX=00) - address signals A10-A24 * + ***************************************************/ + bfin_write_PORTI_MUX(0); + + /**************************************** + * set PORT I direction register * + * enable PI0 - PI14 as outputs * + *****************************************/ + bfin_write_PORTI_DIR_SET(0x7fff); + + return 0; +} diff --git a/board/cm-bf548/config.mk b/board/cm-bf548/config.mk new file mode 100644 index 00000000000..0c95b396277 --- /dev/null +++ b/board/cm-bf548/config.mk @@ -0,0 +1,37 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --dma 6 +LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1 +LDR_FLAGS-BFIN_BOOT_SPI_MASTER := --dma 1 +LDR_FLAGS-BFIN_BOOT_UART := --dma 1 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c new file mode 100644 index 00000000000..49dbe77da5e --- /dev/null +++ b/board/cm-bf548/video.c @@ -0,0 +1,339 @@ +/* + * video.c - run splash screen on lcd + * + * Copyright (c) 2007-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <stdarg.h> +#include <common.h> +#include <config.h> +#include <malloc.h> +#include <asm/blackfin.h> +#include <asm/mach-common/bits/dma.h> +#include <i2c.h> +#include <linux/types.h> +#include <devices.h> + +int gunzip(void *, int, unsigned char *, unsigned long *); + +#ifdef CONFIG_VIDEO + +#define DMA_SIZE16 2 + +#include <asm/mach-common/bits/eppi.h> + +#include <asm/bfin_logo_230x230.h> + +#define LCD_X_RES 480 /*Horizontal Resolution */ +#define LCD_Y_RES 272 /* Vertical Resolution */ + +#define LCD_BPP 24 /* Bit Per Pixel */ +#define LCD_PIXEL_SIZE (LCD_BPP / 8) +#define DMA_BUS_SIZE 32 +#define ACTIVE_VIDEO_MEM_OFFSET 0 + +/* -- Horizontal synchronizing -- + * + * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet + * (LCY-W-06602A Page 9 of 22) + * + * Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz + * + * Period TH - 525 - Clock + * Pulse width THp - 41 - Clock + * Horizontal period THd - 480 - Clock + * Back porch THb - 2 - Clock + * Front porch THf - 2 - Clock + * + * -- Vertical synchronizing -- + * Period TV - 286 - Line + * Pulse width TVp - 10 - Line + * Vertical period TVd - 272 - Line + * Back porch TVb - 2 - Line + * Front porch TVf - 2 - Line + */ + +#define LCD_CLK (8*1000*1000) /* 8MHz */ + +/* # active data to transfer after Horizontal Delay clock */ +#define EPPI_HCOUNT LCD_X_RES + +/* # active lines to transfer after Vertical Delay clock */ +#define EPPI_VCOUNT LCD_Y_RES + +/* Samples per Line = 480 (active data) + 45 (padding) */ +#define EPPI_LINE 525 + +/* Lines per Frame = 272 (active data) + 14 (padding) */ +#define EPPI_FRAME 286 + +/* FS1 (Hsync) Width (Typical)*/ +#define EPPI_FS1W_HBL 41 + +/* FS1 (Hsync) Period (Typical) */ +#define EPPI_FS1P_AVPL EPPI_LINE + +/* Horizontal Delay clock after assertion of Hsync (Typical) */ +#define EPPI_HDELAY 43 + +/* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */ +#define EPPI_FS2W_LVB (EPPI_LINE * 10) + + /* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */ +#define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME) + +/* Vertical Delay after assertion of Vsync (2 Lines) */ +#define EPPI_VDELAY 12 + +#define EPPI_CLIP 0xFF00FF00 + +/* EPPI Control register configuration value for RGB out + * - EPPI as Output + * GP 2 frame sync mode, + * Internal Clock generation disabled, Internal FS generation enabled, + * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge, + * FS1 & FS2 are active high, + * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out) + * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled + * Swapping Enabled, + * One (DMA) Channel Mode, + * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output + * Regular watermark - when FIFO is 100% full, + * Urgent watermark - when FIFO is 75% full + */ + +#define EPPI_CONTROL (0x20136E2E) + +static inline u16 get_eppi_clkdiv(u32 target_ppi_clk) +{ + u32 sclk = get_sclk(); + + /* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */ + + return (((sclk / target_ppi_clk) / 2) - 1); +} + +void Init_PPI(void) +{ + u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK); + + bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL); + bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL); + bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB); + bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF); + bfin_write_EPPI0_CLIP(EPPI_CLIP); + + bfin_write_EPPI0_FRAME(EPPI_FRAME); + bfin_write_EPPI0_LINE(EPPI_LINE); + + bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT); + bfin_write_EPPI0_HDELAY(EPPI_HDELAY); + bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT); + bfin_write_EPPI0_VDELAY(EPPI_VDELAY); + + bfin_write_EPPI0_CLKDIV(eppi_clkdiv); + +/* + * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out) + * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output + */ +#if defined(CONFIG_VIDEO_RGB666) + bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 | + RGB_FMT_EN); +#else + bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) & + ~RGB_FMT_EN); +#endif + +} + +#define DEB2_URGENT 0x2000 /* DEB2 Urgent */ + +void Init_DMA(void *dst) +{ + +#if defined(CONFIG_DEB_DMA_URGENT) + *pEBIU_DDRQUE |= DEB2_URGENT; +#endif + + *pDMA12_START_ADDR = dst; + + /* X count */ + *pDMA12_X_COUNT = (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE; + *pDMA12_X_MODIFY = DMA_BUS_SIZE / 8; + + /* Y count */ + *pDMA12_Y_COUNT = LCD_Y_RES; + *pDMA12_Y_MODIFY = DMA_BUS_SIZE / 8; + + /* DMA Config */ + *pDMA12_CONFIG = WDSIZE_32 | /* 32 bit DMA */ + DMA2D | /* 2D DMA */ + FLOW_AUTO; /* autobuffer mode */ +} + +void Init_Ports(void) +{ + *pPORTF_MUX = 0x00000000; + *pPORTF_FER |= 0xFFFF; /* PPI0..15 */ + + *pPORTG_MUX &= + ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | + PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK); + *pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4; /* CLK, FS1, FS2, PPI16..17 */ + +#if !defined(CONFIG_VIDEO_RGB666) + *pPORTD_MUX &= + ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | + PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK); + *pPORTD_MUX |= + (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 | + PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4); + *pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5; /* PPI18..23 */ +#endif + + *pPORTE_FER &= ~PE3; /* DISP */ + *pPORTE_DIR_SET = PE3; + *pPORTE_SET = PE3; + +} + +void EnableDMA(void) +{ + *pDMA12_CONFIG |= DMAEN; +} + +void DisableDMA(void) +{ + *pDMA12_CONFIG &= ~DMAEN; +} + +/* enable and disable PPI functions */ +void EnablePPI(void) +{ + bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN); +} + +void DisablePPI(void) +{ + bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN); +} + +int video_init(void *dst) +{ + Init_Ports(); + Init_DMA(dst); + EnableDMA(); + Init_PPI(); + EnablePPI(); + + return 0; +} + +static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y) +{ + if (dcache_status()) + blackfin_dcache_flush_range(logo->data, + logo->data + logo->size); + + bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); + + /* Setup destination start address */ + bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE) + + (y * LCD_X_RES * LCD_PIXEL_SIZE)); + /* Setup destination xcount */ + bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16); + /* Setup destination xmodify */ + bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16); + + /* Setup destination ycount */ + bfin_write_MDMA_D0_Y_COUNT(logo->height); + /* Setup destination ymodify */ + bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + + DMA_SIZE16); + + /* Setup Source start address */ + bfin_write_MDMA_S0_START_ADDR(logo->data); + /* Setup Source xcount */ + bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16); + /* Setup Source xmodify */ + bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16); + + /* Setup Source ycount */ + bfin_write_MDMA_S0_Y_COUNT(logo->height); + /* Setup Source ymodify */ + bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16); + + /* Enable source DMA */ + bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D); + SSYNC(); + bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D); + + while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN) ; + + bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE + | DMA_ERR); + bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE + | DMA_ERR); + +} + +void video_putc(const char c) +{ +} + +void video_puts(const char *s) +{ +} + +int drv_video_init(void) +{ + int error, devices = 1; + device_t videodev; + + u8 *dst; + u32 fbmem_size = + LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET; + + dst = malloc(fbmem_size); + + if (dst == NULL) { + printf("Failed to alloc FB memory\n"); + return -1; + } +#ifdef EASYLOGO_ENABLE_GZIP + unsigned char *data = EASYLOGO_DECOMP_BUFFER; + unsigned long src_len = EASYLOGO_ENABLE_GZIP; + if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) { + puts("Failed to decompress logo\n"); + free(dst); + return -1; + } + bfin_logo.data = data; +#endif + + memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], + fbmem_size - ACTIVE_VIDEO_MEM_OFFSET); + + dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo, + (LCD_X_RES - bfin_logo.width) / 2, + (LCD_Y_RES - bfin_logo.height) / 2); + + video_init(dst); /* Video initialization */ + + memset(&videodev, 0, sizeof(videodev)); + + strcpy(videodev.name, "video"); + videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ + videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */ + videodev.putc = video_putc; /* 'putc' function */ + videodev.puts = video_puts; /* 'puts' function */ + + error = device_register(&videodev); + + return (error == 0) ? devices : error; +} + +#endif diff --git a/board/cm-bf561/Makefile b/board/cm-bf561/Makefile new file mode 100644 index 00000000000..f2bd2c247d4 --- /dev/null +++ b/board/cm-bf561/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/cm-bf561/cm-bf561.c b/board/cm-bf561/cm-bf561.c new file mode 100644 index 00000000000..5bce9eb59d0 --- /dev/null +++ b/board/cm-bf561/cm-bf561.c @@ -0,0 +1,25 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2005-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: Bluetechnix CM-BF561 core module\n"); + printf(" Support: http://www.bluetechnix.at/\n"); + return 0; +} + +phys_size_t initdram(int board_type) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return gd->bd->bi_memsize; +} diff --git a/board/cm-bf561/config.mk b/board/cm-bf561/config.mk new file mode 100644 index 00000000000..cfad21a2a46 --- /dev/null +++ b/board/cm-bf561/config.mk @@ -0,0 +1,34 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/davinci/common/misc.h b/board/davinci/common/misc.h index 316159a2f76..dc3cc413302 100644 --- a/board/davinci/common/misc.h +++ b/board/davinci/common/misc.h @@ -22,7 +22,6 @@ #ifndef __MISC_H #define __MISC_H -extern int eth_hw_init(void); int dvevm_read_mac_address(uint8_t *buf); void dv_configure_mac_address(uint8_t *rom_enetaddr); diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c index 8f386331e68..98937a9620c 100644 --- a/board/davinci/dvevm/dvevm.c +++ b/board/davinci/dvevm/dvevm.c @@ -73,9 +73,6 @@ int misc_init_r(void) if (dvevm_read_mac_address(eeprom_enetaddr)) dv_configure_mac_address(eeprom_enetaddr); - if (!eth_hw_init()) - printf("ethernet init failed!\n"); - i2c_read(0x39, 0x00, 1, &video_mode, 1); setenv("videostd", ((video_mode & 0x80) ? "pal" : "ntsc")); diff --git a/board/davinci/schmoogie/schmoogie.c b/board/davinci/schmoogie/schmoogie.c index 6e0f5913359..19c95809aa0 100644 --- a/board/davinci/schmoogie/schmoogie.c +++ b/board/davinci/schmoogie/schmoogie.c @@ -130,8 +130,5 @@ int misc_init_r(void) forceenv("serial#", (char *)&tmp[0]); } - if (!eth_hw_init()) - printf("ethernet init failed!\n"); - return(0); } diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c index 7f4ee361bb6..c24b9e188c9 100644 --- a/board/davinci/sffsdr/sffsdr.c +++ b/board/davinci/sffsdr/sffsdr.c @@ -143,8 +143,5 @@ int misc_init_r(void) if (sffsdr_read_mac_address(eeprom_enetaddr)) dv_configure_mac_address(eeprom_enetaddr); - if (!eth_hw_init()) - printf("Ethernet init failed\n"); - return(0); } diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c index a0bea05177c..7f9d9bba3dc 100644 --- a/board/davinci/sonata/sonata.c +++ b/board/davinci/sonata/sonata.c @@ -70,8 +70,5 @@ int misc_init_r(void) if (dvevm_read_mac_address(eeprom_enetaddr)) dv_configure_mac_address(eeprom_enetaddr); - if (!eth_hw_init()) - printf("ethernet init failed!\n"); - return(0); } diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index ae5304a9b45..3e1e3321695 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -78,12 +78,14 @@ static int has_been_read = 0; #ifdef CONFIG_SYS_I2C_EEPROM_NXID /* Is this a valid NXID EEPROM? */ -#define is_valid (*((u32 *)e.id) == (('N' << 24) | ('X' << 16) | ('I' << 8) | 'D')) +#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \ + (e.id[2] == 'I') || (e.id[3] == 'D')) #endif #ifdef CONFIG_SYS_I2C_EEPROM_CCID /* Is this a valid CCID EEPROM? */ -#define is_valid (*((u32 *)e.id) == (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D')) +#define is_valid ((e.id[0] == 'C') || (e.id[1] == 'C') || \ + (e.id[2] == 'I') || (e.id[3] == 'D')) #endif /** diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index b39cd4d7a51..4772074d81f 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -26,6 +26,7 @@ #include <common.h> #include <asm/immap.h> +#include <netdev.h> int checkboard(void) { @@ -138,3 +139,11 @@ void ide_set_reset(int idereset) } } #endif /* CONFIG_CMD_IDE */ + + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} +#endif diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 85c0120f271..dc4dbd3c3a5 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -116,7 +116,7 @@ int board_early_init_r(void) return 0; } -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif int fixed_sdram(void); @@ -138,7 +138,7 @@ phys_size_t initdram(int board_type) msize = fixed_sdram(); #endif -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize DDR ECC byte */ diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c index af3b8ceae4e..377187816a1 100644 --- a/board/freescale/mpc8360erdk/mpc8360erdk.c +++ b/board/freescale/mpc8360erdk/mpc8360erdk.c @@ -268,7 +268,7 @@ int fixed_sdram(void) phys_size_t initdram(int board_type) { -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; @@ -281,7 +281,7 @@ phys_size_t initdram(int board_type) im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; msize = fixed_sdram(); -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize DDR ECC byte */ diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index 062d762d2c3..85068923b7f 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -199,7 +199,7 @@ int board_early_init_r(void) return 0; } -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif int fixed_sdram(void); @@ -218,7 +218,7 @@ phys_size_t initdram(int board_type) msize = fixed_sdram(); #endif -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* Initialize DDR ECC byte */ ddr_enable_ecc(msize * 1024 * 1024); #endif diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 318a3dce710..a4a1927df84 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -59,7 +59,7 @@ testdram(void) } #endif -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) void ddr_enable_ecc(unsigned int dram_size); #endif int fixed_sdram(void); @@ -78,7 +78,7 @@ phys_size_t initdram(int board_type) msize = fixed_sdram(); #endif -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* Initialize DDR ECC byte */ ddr_enable_ecc(msize * 1024 * 1024); #endif diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 6b72d61426f..293e5a42dc0 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -36,6 +36,7 @@ #include <tsec.h> #include <asm/fsl_law.h> #include <asm/mp.h> +#include <netdev.h> #include "../common/pixis.h" #include "../common/sgmii_riser.h" @@ -594,7 +595,7 @@ int board_eth_init(bd_t *bis) tsec_eth_init(bis, tsec_info, num); - return 0; + return pci_eth_init(bis); } #endif diff --git a/board/ibf-dsp561/Makefile b/board/ibf-dsp561/Makefile new file mode 100644 index 00000000000..bfeaf791e19 --- /dev/null +++ b/board/ibf-dsp561/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2007 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ibf-dsp561/config.mk b/board/ibf-dsp561/config.mk new file mode 100644 index 00000000000..77c888b3bd3 --- /dev/null +++ b/board/ibf-dsp561/config.mk @@ -0,0 +1,31 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/ibf-dsp561/ibf-dsp561.c b/board/ibf-dsp561/ibf-dsp561.c new file mode 100644 index 00000000000..551fc291a05 --- /dev/null +++ b/board/ibf-dsp561/ibf-dsp561.c @@ -0,0 +1,25 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2008-2009 I-SYST. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: I-SYST IBF-DSP561 Micromodule\n"); + printf(" Support: http://www.i-syst.com/\n"); + return 0; +} + +phys_size_t initdram(int board_type) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return gd->bd->bi_memsize; +} diff --git a/board/keymile/kmeter1/kmeter1.c b/board/keymile/kmeter1/kmeter1.c index 660d87b53b4..3d1b9415489 100644 --- a/board/keymile/kmeter1/kmeter1.c +++ b/board/keymile/kmeter1/kmeter1.c @@ -153,7 +153,7 @@ int fixed_sdram(void) phys_size_t initdram (int board_type) { -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc (unsigned int dram_size); #endif volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; @@ -166,7 +166,7 @@ phys_size_t initdram (int board_type) im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; msize = fixed_sdram (); -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize DDR ECC byte */ diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index 72a1ad32f7a..7c272334aa5 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -137,40 +137,9 @@ phys_size_t initdram (int board_type) { /* Initialize all of memory for ECC, then * enable errors */ - uint *p = 0; - uint i = 0; volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - dma_init(); - for (*p = 0; p < (uint *)(8 * 1024); p++) { - if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } - *p = (unsigned int)0xdeadbeef; - if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); } - } - - /* 8K */ - dma_xfer((uint *)0x2000,0x2000,(uint *)0); - /* 16K */ - dma_xfer((uint *)0x4000,0x4000,(uint *)0); - /* 32K */ - dma_xfer((uint *)0x8000,0x8000,(uint *)0); - /* 64K */ - dma_xfer((uint *)0x10000,0x10000,(uint *)0); - /* 128k */ - dma_xfer((uint *)0x20000,0x20000,(uint *)0); - /* 256k */ - dma_xfer((uint *)0x40000,0x40000,(uint *)0); - /* 512k */ - dma_xfer((uint *)0x80000,0x80000,(uint *)0); - /* 1M */ - dma_xfer((uint *)0x100000,0x100000,(uint *)0); - /* 2M */ - dma_xfer((uint *)0x200000,0x200000,(uint *)0); - /* 4M */ - dma_xfer((uint *)0x400000,0x400000,(uint *)0); - for (i = 1; i < dram_size / 0x800000; i++) { - dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0); - } + dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); /* Enable errors for ECC */ ddr->err_disable = 0x00000000; diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index 7f032c8fad8..c40b5e38ddd 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -338,40 +338,9 @@ phys_size_t initdram (int board_type) { /* Initialize all of memory for ECC, then * enable errors */ - uint *p = 0; - uint i = 0; volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - dma_init(); - for (*p = 0; p < (uint *)(8 * 1024); p++) { - if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } - *p = (unsigned int)0xdeadbeef; - if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); } - } - /* 8K */ - dma_xfer((uint *)0x2000,0x2000,(uint *)0); - /* 16K */ - dma_xfer((uint *)0x4000,0x4000,(uint *)0); - /* 32K */ - dma_xfer((uint *)0x8000,0x8000,(uint *)0); - /* 64K */ - dma_xfer((uint *)0x10000,0x10000,(uint *)0); - /* 128k */ - dma_xfer((uint *)0x20000,0x20000,(uint *)0); - /* 256k */ - dma_xfer((uint *)0x40000,0x40000,(uint *)0); - /* 512k */ - dma_xfer((uint *)0x80000,0x80000,(uint *)0); - /* 1M */ - dma_xfer((uint *)0x100000,0x100000,(uint *)0); - /* 2M */ - dma_xfer((uint *)0x200000,0x200000,(uint *)0); - /* 4M */ - dma_xfer((uint *)0x400000,0x400000,(uint *)0); - - for (i = 1; i < dram_size / 0x800000; i++) { - dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0); - } + dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); /* Enable errors for ECC */ ddr->err_disable = 0x00000000; diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c index 3f6831be5e5..428e8c9e1c2 100644 --- a/board/scb9328/scb9328.c +++ b/board/scb9328/scb9328.c @@ -19,6 +19,7 @@ */ #include <common.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -70,3 +71,10 @@ void show_boot_progress (int status) { return; } + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} +#endif diff --git a/board/tcm-bf537/Makefile b/board/tcm-bf537/Makefile new file mode 100644 index 00000000000..3812ba1e721 --- /dev/null +++ b/board/tcm-bf537/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o flash.o gpio_cfi_flash.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/tcm-bf537/config.mk b/board/tcm-bf537/config.mk new file mode 100644 index 00000000000..3c0b46f7214 --- /dev/null +++ b/board/tcm-bf537/config.mk @@ -0,0 +1,34 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/tcm-bf537/flash.c b/board/tcm-bf537/flash.c new file mode 100644 index 00000000000..52c5bd83c9c --- /dev/null +++ b/board/tcm-bf537/flash.c @@ -0,0 +1,37 @@ +/* + * flash.c - helper commands for working with GPIO-assisted flash + * + * Copyright (c) 2005-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <command.h> +#include <asm/blackfin.h> +#include "gpio_cfi_flash.h" + +int do_pf(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong faddr = CONFIG_SYS_FLASH_BASE; + ushort data; + ulong dflg; + + if (argc == 3) { + dflg = simple_strtoul(argv[1], NULL, 16); + faddr |= (dflg << 21); + dflg = simple_strtoul(argv[2], NULL, 16); + faddr |= (dflg << 22); + gpio_cfi_flash_swizzle((void *)faddr); + } else { + data = bfin_read_PORTFIO(); + printf("Port F data %04x (PF4:%i PF5:%i)\n", data, + !!(data & PF4), !!(data & PF5)); + } + + return 0; +} + +U_BOOT_CMD(pf, 3, 0, do_pf, + "set/clear PF4/PF5 GPIO flash bank switch\n", + "<pf4> <pf5> - set PF4/PF5 GPIO pin state\n"); diff --git a/board/tcm-bf537/gpio_cfi_flash.c b/board/tcm-bf537/gpio_cfi_flash.c new file mode 100644 index 00000000000..7137d125580 --- /dev/null +++ b/board/tcm-bf537/gpio_cfi_flash.c @@ -0,0 +1,62 @@ +/* + * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support + * + * Copyright (c) 2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <asm/blackfin.h> +#include <asm/io.h> +#include "gpio_cfi_flash.h" + +#define GPIO_PIN_1 PF4 +#define GPIO_MASK_1 (1 << 21) +#define GPIO_PIN_2 PF5 +#define GPIO_MASK_2 (1 << 22) +#define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2) + +void *gpio_cfi_flash_swizzle(void *vaddr) +{ + unsigned long addr = (unsigned long)vaddr; + + if (addr & GPIO_MASK_1) + bfin_write_PORTFIO_SET(GPIO_PIN_1); + else + bfin_write_PORTFIO_CLEAR(GPIO_PIN_1); + +#ifdef GPIO_MASK_2 + if (addr & GPIO_MASK_2) + bfin_write_PORTFIO_SET(GPIO_PIN_2); + else + bfin_write_PORTFIO_CLEAR(GPIO_PIN_2); +#endif + + SSYNC(); + + return (void *)(addr & ~GPIO_MASK); +} + +#define __raw_writeq(value, addr) *(volatile u64 *)addr = value +#define __raw_readq(addr) *(volatile u64 *)addr + +#define MAKE_FLASH(size, sfx) \ +void flash_write##size(u##size value, void *addr) \ +{ \ + __raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \ +} \ +u##size flash_read##size(void *addr) \ +{ \ + return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \ +} +MAKE_FLASH(8, b) /* flash_write8() flash_read8() */ +MAKE_FLASH(16, w) /* flash_write16() flash_write16() */ +MAKE_FLASH(32, l) /* flash_write32() flash_write32() */ +MAKE_FLASH(64, q) /* flash_write64() flash_write64() */ + +void gpio_cfi_flash_init(void) +{ + bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | GPIO_PIN_1 | GPIO_PIN_2); + gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); +} diff --git a/board/tcm-bf537/gpio_cfi_flash.h b/board/tcm-bf537/gpio_cfi_flash.h new file mode 100644 index 00000000000..5211e972ad2 --- /dev/null +++ b/board/tcm-bf537/gpio_cfi_flash.h @@ -0,0 +1,10 @@ +/* + * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support + * + * Copyright (c) 2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +void *gpio_cfi_flash_swizzle(void *vaddr); +void gpio_cfi_flash_init(void); diff --git a/board/tcm-bf537/tcm-bf537.c b/board/tcm-bf537/tcm-bf537.c new file mode 100644 index 00000000000..573387d4f66 --- /dev/null +++ b/board/tcm-bf537/tcm-bf537.c @@ -0,0 +1,59 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2005-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <config.h> +#include <command.h> +#include <net.h> +#include <netdev.h> +#include <asm/blackfin.h> +#include <asm/net.h> +#include "gpio_cfi_flash.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: Bluetechnix TCM-BF537 board\n"); + printf(" Support: http://www.bluetechnix.at/\n"); + return 0; +} + +phys_size_t initdram(int board_type) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return gd->bd->bi_memsize; +} + +#ifdef CONFIG_BFIN_MAC +static void board_init_enetaddr(uchar *mac_addr) +{ + puts("Warning: Generating 'random' MAC address\n"); + bfin_gen_rand_mac(mac_addr); + eth_setenv_enetaddr("ethaddr", mac_addr); +} + +int board_eth_init(bd_t *bis) +{ + return bfin_EMAC_initialize(bis); +} +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_BFIN_MAC + uchar enetaddr[6]; + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + board_init_enetaddr(enetaddr); +#endif + + gpio_cfi_flash_init(); + + return 0; +} diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c index 7c6c8550074..5c0eb41d4b5 100644 --- a/board/trizepsiv/conxs.c +++ b/board/trizepsiv/conxs.c @@ -33,6 +33,7 @@ #include <common.h> #include <asm/arch/pxa-regs.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -144,3 +145,10 @@ int dram_init (void) return 0; } + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} +#endif diff --git a/board/xes/xpedite5170/Makefile b/board/xes/xpedite5170/Makefile new file mode 100644 index 00000000000..fea6686e699 --- /dev/null +++ b/board/xes/xpedite5170/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude ($obj).depend + +######################################################################### diff --git a/board/xes/xpedite5170/config.mk b/board/xes/xpedite5170/config.mk new file mode 100644 index 00000000000..c3df6d5ba18 --- /dev/null +++ b/board/xes/xpedite5170/config.mk @@ -0,0 +1,32 @@ +# +# Copyright 2009 Extreme Engineering Solutions, Inc. +# Copyright 2007-2008 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# XPedite5170 +# +TEXT_BASE = 0xfff00000 + +PLATFORM_RELFLAGS += -mrelocatable + +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float diff --git a/board/xes/xpedite5170/ddr.c b/board/xes/xpedite5170/ddr.c new file mode 100644 index 00000000000..1d57d0909a6 --- /dev/null +++ b/board/xes/xpedite5170/ddr.c @@ -0,0 +1,168 @@ +/* + * Copyright 2009 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, + sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_bus_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0) { + i2c_address = SPD_EEPROM_ADDRESS1; +#ifdef SPD_EEPROM_ADDRESS2 + } else if (ctrl_num == 1) { + i2c_address = SPD_EEPROM_ADDRESS2; +#endif + } else { + /* An inalid ctrl number was give, use default SPD */ + printf("ERROR: invalid DDR ctrl: %d\n", ctrl_num); + i2c_address = SPD_EEPROM_ADDRESS1; + } + + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +/* + * There are four board-specific SDRAM timing parameters which must be + * calculated based on the particular PCB artwork. These are: + * 1.) CPO (Read Capture Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths and + * chip-specific internal delays. + * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths. + * Unless clock and DQ lanes are very different + * lengths (>2"), this should be set to the nominal value + * of 1/2 clock delay. + * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control) + * - DDR_SDRAM_CLK_CNTL register + * Source: Signal Integrity Simulations + * 4.) 2T Timing on Addr/Ctl + * - TIMING_CFG_2 register + * Source: Signal Integrity Simulations + * Usually only needed with heavy load/very high speed (>DDR2-800) + * + * PCB routing on the XPedite5170 is nearly identical to the XPedite5370 + * so we use the XPedite5370 settings as a basis for the XPedite5170. + */ + +typedef struct board_memctl_options { + uint16_t datarate_mhz_low; + uint16_t datarate_mhz_high; + uint8_t clk_adjust; + uint8_t cpo_override; + uint8_t write_data_delay; +} board_memctl_options_t; + +static struct board_memctl_options bopts_ctrl[][2] = { + { + /* Controller 0 */ + { + /* DDR2 600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo_override = 8, + .write_data_delay = 2, + }, + { + /* DDR2 800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo_override = 9, + .write_data_delay = 2, + }, + }, + { + /* Controller 1 */ + { + /* DDR2 600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo_override = 7, + .write_data_delay = 2, + }, + { + /* DDR2 800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo_override = 8, + .write_data_delay = 2, + }, + }, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + struct board_memctl_options *bopts = bopts_ctrl[ctrl_num]; + sys_info_t sysinfo; + int i; + unsigned int datarate; + + get_sys_info(&sysinfo); + datarate = fsl_ddr_get_mem_data_rate() / 1000000; + + for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { + if ((bopts[i].datarate_mhz_low <= datarate) && + (bopts[i].datarate_mhz_high >= datarate)) { + debug("controller %d:\n", ctrl_num); + debug(" clk_adjust = %d\n", bopts[i].clk_adjust); + debug(" cpo = %d\n", bopts[i].cpo_override); + debug(" write_data_delay = %d\n", + bopts[i].write_data_delay); + popts->clk_adjust = bopts[i].clk_adjust; + popts->cpo_override = bopts[i].cpo_override; + popts->write_data_delay = bopts[i].write_data_delay; + } + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/xes/xpedite5170/law.c b/board/xes/xpedite5170/law.c new file mode 100644 index 00000000000..0b7d9ef8d18 --- /dev/null +++ b/board/xes/xpedite5170/law.c @@ -0,0 +1,52 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * Notes: + * CCSRBAR don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_NAND_BASE + /* NAND LAW covers 2 NAND flashes */ + SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC), +#endif +#ifdef CONFIG_SYS_PCIE1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), +#endif +#ifdef CONFIG_SYS_PCIE2_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite5170/u-boot.lds b/board/xes/xpedite5170/u-boot.lds new file mode 100644 index 00000000000..b71a7d6e580 --- /dev/null +++ b/board/xes/xpedite5170/u-boot.lds @@ -0,0 +1,132 @@ +/* + * Copyright 2006, 2007 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) + +SECTIONS +{ + + /* Read-only sections, merged into text segment: */ + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc86xx/start.o (.text) + cpu/mpc86xx/traps.o (.text) + cpu/mpc86xx/interrupts.o (.text) + cpu/mpc86xx/cpu_init.o (.text) + cpu/mpc86xx/cpu.o (.text) + cpu/mpc86xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xes/xpedite5170/xpedite5170.c b/board/xes/xpedite5170/xpedite5170.c new file mode 100644 index 00000000000..f4231a9a7a6 --- /dev/null +++ b/board/xes/xpedite5170/xpedite5170.c @@ -0,0 +1,111 @@ +/* + * Copyright 2009 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/io.h> +#include <fdt_support.h> +#include <pca953x.h> + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI) +extern void ft_board_pci_setup(void *blob, bd_t *bd); +#endif + +int checkboard(void) +{ + char *s; + + printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME); + printf(" "); + s = getenv("board_rev"); + if (s) + printf("Rev %s, ", s); + s = getenv("serial#"); + if (s) + printf("Serial# %s, ", s); + s = getenv("board_cfg"); + if (s) + printf("Cfg %s", s); + printf("\n"); + + return 0; +} +/* + * Print out which flash was booted from and if booting from the 2nd flash, + * swap flash chip selects to maintain consistent flash numbering/addresses. + */ +static void flash_cs_fixup(void) +{ + immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + ccsr_lbc_t *lbc = &immap->im_lbc; + int flash_sel; + + /* + * Print boot dev and swap flash flash chip selects if booted from 2nd + * flash. Swapping chip selects presents user with a common memory + * map regardless of which flash was booted from. + */ + flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS)); + printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); + + if (flash_sel) { + out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM); + out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM); + + out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM); + out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM); + } +} + +int board_early_init_r(void) +{ + /* Initialize PCA9557 devices */ + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0); + + flash_cs_fixup(); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCI + ft_board_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); +} +#endif + +#ifdef CONFIG_MP +extern void cpu_mp_lmb_reserve(struct lmb *lmb); + +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif diff --git a/common/Makefile b/common/Makefile index ee0cb33aca3..c8e5d261043 100644 --- a/common/Makefile +++ b/common/Makefile @@ -133,6 +133,7 @@ COBJS-$(CONFIG_CMD_SF) += cmd_sf.o COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o COBJS-$(CONFIG_CMD_SETEXPR) += cmd_setexpr.o COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o +COBJS-$(CONFIG_CMD_SPIBOOTLDR) += cmd_spibootldr.o COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o COBJS-$(CONFIG_CMD_UBI) += cmd_ubi.o diff --git a/common/cmd_spibootldr.c b/common/cmd_spibootldr.c new file mode 100644 index 00000000000..d29ed2bd85a --- /dev/null +++ b/common/cmd_spibootldr.c @@ -0,0 +1,36 @@ +/* + * U-boot - spibootldr.c + * + * Copyright (c) 2005-2008 Analog Devices Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <command.h> + +#include <asm/blackfin.h> +#include <asm/mach-common/bits/bootrom.h> + +int do_spibootldr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + s32 addr; + + /* Get the address */ + if (argc < 2) + addr = 0; + else + addr = simple_strtoul(argv[1], NULL, 16); + + printf("## Booting ldr image at SPI offset 0x%x ...\n", addr); + + return bfrom_SpiBoot(addr, BFLAG_PERIPHERAL | 4, 0, NULL); +} + +U_BOOT_CMD(spibootldr, 2, 0, do_spibootldr, + "boot ldr image from spi", + "[offset]\n" + " - boot ldr image stored at offset into spi\n"); diff --git a/common/serial.c b/common/serial.c index dd80e7c863e..5d0a73ce060 100644 --- a/common/serial.c +++ b/common/serial.c @@ -40,7 +40,8 @@ struct serial_device *__default_serial_console (void) return &serial_scc_device; #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \ - || defined(CONFIG_MPC5xxx) + || defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) \ + || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL) #if (CONFIG_CONS_INDEX==1) return &eserial1_device; diff --git a/config.mk b/config.mk index f5b9c28f1da..7fc045375a0 100644 --- a/config.mk +++ b/config.mk @@ -214,5 +214,9 @@ $(obj)%.o: %.S $(CC) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $< -c $(obj)%.o: %.c $(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c +$(obj)%.i: %.c + $(CPP) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c +$(obj)%.s: %.c + $(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c -S ######################################################################### diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile index 6eaa89c614a..e45ad25d99e 100644 --- a/cpu/arm926ejs/davinci/Makefile +++ b/cpu/arm926ejs/davinci/Makefile @@ -30,7 +30,7 @@ LIB = $(obj)lib$(SOC).a COBJS-y += cpu.o timer.o psc.o COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM644X) += dm644x.o -COBJS-$(CONFIG_DRIVER_TI_EMAC) += ether.o lxt972.o dp83848.o +COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o SOBJS = reset.o diff --git a/cpu/arm926ejs/davinci/cpu.c b/cpu/arm926ejs/davinci/cpu.c index 29aead6f4f5..390cab8a200 100644 --- a/cpu/arm926ejs/davinci/cpu.c +++ b/cpu/arm926ejs/davinci/cpu.c @@ -21,6 +21,7 @@ */ #include <common.h> +#include <netdev.h> #include <asm/arch/hardware.h> @@ -129,3 +130,14 @@ int print_cpuinfo(void) #endif +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int cpu_eth_init(bd_t *bis) +{ +#if defined(CONFIG_DRIVER_TI_EMAC) + davinci_emac_initialize(); +#endif + return 0; +} diff --git a/cpu/blackfin/jtag-console.c b/cpu/blackfin/jtag-console.c index d58582f6e01..c995d962dc0 100644 --- a/cpu/blackfin/jtag-console.c +++ b/cpu/blackfin/jtag-console.c @@ -11,7 +11,7 @@ #include <asm/blackfin.h> #ifndef CONFIG_JTAG_CONSOLE_TIMEOUT -# define CONFIG_JTAG_CONSOLE_TIMEOUT 100 +# define CONFIG_JTAG_CONSOLE_TIMEOUT 500 #endif /* The Blackfin tends to be much much faster than the JTAG hardware. */ diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index c4331ae97ee..e38a3722ca2 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -276,91 +276,6 @@ void watchdog_reset (void) } #endif -#if defined(CONFIG_DDR_ECC) -void dma_init(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile dma83xx_t *dma = &immap->dma; - volatile u32 status = swab32(dma->dmasr0); - volatile u32 dmamr0 = swab32(dma->dmamr0); - - debug("DMA-init\n"); - - /* initialize DMASARn, DMADAR and DMAABCRn */ - dma->dmadar0 = (u32)0; - dma->dmasar0 = (u32)0; - dma->dmabcr0 = 0; - - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - /* clear CS bit */ - dmamr0 &= ~DMA_CHANNEL_START; - dma->dmamr0 = swab32(dmamr0); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - /* while the channel is busy, spin */ - while(status & DMA_CHANNEL_BUSY) { - status = swab32(dma->dmasr0); - } - - debug("DMA-init end\n"); -} - -uint dma_check(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile dma83xx_t *dma = &immap->dma; - volatile u32 status = swab32(dma->dmasr0); - volatile u32 byte_count = swab32(dma->dmabcr0); - - /* while the channel is busy, spin */ - while (status & DMA_CHANNEL_BUSY) { - status = swab32(dma->dmasr0); - } - - if (status & DMA_CHANNEL_TRANSFER_ERROR) { - printf ("DMA Error: status = %x @ %d\n", status, byte_count); - } - - return status; -} - -int dma_xfer(void *dest, u32 count, void *src) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile dma83xx_t *dma = &immap->dma; - volatile u32 dmamr0; - - /* initialize DMASARn, DMADAR and DMAABCRn */ - dma->dmadar0 = swab32((u32)dest); - dma->dmasar0 = swab32((u32)src); - dma->dmabcr0 = swab32(count); - - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - /* init direct transfer, clear CS bit */ - dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT | - DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B | - DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN); - - dma->dmamr0 = swab32(dmamr0); - - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - /* set CS to start DMA transfer */ - dmamr0 |= DMA_CHANNEL_START; - dma->dmamr0 = swab32(dmamr0); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - return ((int)dma_check()); -} -#endif /*CONFIG_DDR_ECC*/ - /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 4704d2006f5..0f611804a07 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -64,13 +64,6 @@ void board_add_ram_info(int use_default) } #ifdef CONFIG_SPD_EEPROM - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) -extern void dma_init(void); -extern uint dma_check(void); -extern int dma_xfer(void *dest, uint count, void *src); -#endif - #ifndef CONFIG_SYS_READ_SPD #define CONFIG_SYS_READ_SPD i2c_read #endif @@ -830,7 +823,7 @@ long int spd_sdram() } #endif /* CONFIG_SPD_EEPROM */ -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Use timebase counter, get_timer() is not availabe * at this point of initialization yet. @@ -863,7 +856,6 @@ static __inline__ unsigned long get_tbms (void) /* * Initialize all of memory for ECC, then enable errors. */ -/* #define CONFIG_DDR_ECC_INIT_VIA_DMA */ void ddr_enable_ecc(unsigned int dram_size) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; @@ -872,46 +864,21 @@ void ddr_enable_ecc(unsigned int dram_size) register u64 *p; register uint size; unsigned int pattern[2]; -#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA) - uint i; -#endif + icache_enable(); t_start = get_tbms(); pattern[0] = 0xdeadbeef; pattern[1] = 0xdeadbeef; -#if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA) +#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA) + dma_meminit(pattern[0], dram_size); +#else debug("ddr init: CPU FP write method\n"); size = dram_size; for (p = 0; p < (u64*)(size); p++) { ppcDWstore((u32*)p, pattern); } __asm__ __volatile__ ("sync"); -#else - debug("ddr init: DMA method\n"); - size = 0x2000; - for (p = 0; p < (u64*)(size); p++) { - ppcDWstore((u32*)p, pattern); - } - __asm__ __volatile__ ("sync"); - - /* Initialise DMA for direct transfer */ - dma_init(); - /* Start DMA to transfer */ - dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */ - dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */ - dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */ - dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */ - dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */ - dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */ - dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */ - dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */ - dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */ - dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */ - - for (i = 1; i < dram_size / 0x800000; i++) { - dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); - } #endif t_end = get_tbms(); diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index d88c5646208..28c6119d3de 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -264,53 +264,6 @@ reset_85xx_watchdog(void) } #endif /* CONFIG_WATCHDOG */ -#if defined(CONFIG_DDR_ECC) -void dma_init(void) { - volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); - volatile fsl_dma_t *dma = &dma_base->dma[0]; - - dma->satr = 0x00040000; - dma->datr = 0x00040000; - dma->sr = 0xffffffff; /* clear any errors */ - asm("sync; isync; msync"); - return; -} - -uint dma_check(void) { - volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); - volatile fsl_dma_t *dma = &dma_base->dma[0]; - volatile uint status = dma->sr; - - /* While the channel is busy, spin */ - while((status & 4) == 4) { - status = dma->sr; - } - - /* clear MR[CS] channel start bit */ - dma->mr &= 0x00000001; - asm("sync;isync;msync"); - - if (status != 0) { - printf ("DMA Error: status = %x\n", status); - } - return status; -} - -int dma_xfer(void *dest, uint count, void *src) { - volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); - volatile fsl_dma_t *dma = &dma_base->dma[0]; - - dma->dar = (uint) dest; - dma->sar = (uint) src; - dma->bcr = count; - dma->mr = 0xf000004; - asm("sync;isync;msync"); - dma->mr = 0xf000005; - asm("sync;isync;msync"); - return dma_check(); -} -#endif - /* * Configures a UPM. The function requires the respective MxMR to be set * before calling this function. "size" is the number or entries, not a sizeof. diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index c98dd8da58f..41de6942a62 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -261,7 +261,9 @@ void cpu_init_f (void) #if defined(CONFIG_MPC8536) fsl_serdes_init(); #endif - +#if defined(CONFIG_FSL_DMA) + dma_init(); +#endif } diff --git a/cpu/mpc85xx/ddr-gen1.c b/cpu/mpc85xx/ddr-gen1.c index e24c9afaf59..54437dd0cbd 100644 --- a/cpu/mpc85xx/ddr-gen1.c +++ b/cpu/mpc85xx/ddr-gen1.c @@ -66,10 +66,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, } #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void dma_init(void); -extern uint dma_check(void); -extern int dma_xfer(void *dest, uint count, void *src); - /* * Initialize all of memory for ECC, then enable errors. */ @@ -77,36 +73,9 @@ extern int dma_xfer(void *dest, uint count, void *src); void ddr_enable_ecc(unsigned int dram_size) { - uint *p = 0; - uint i = 0; volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - dma_init(); - - for (*p = 0; p < (uint *)(8 * 1024); p++) { - if (((unsigned int)p & 0x1f) == 0) { - ppcDcbz((unsigned long) p); - } - *p = (unsigned int)CONFIG_MEM_INIT_VALUE; - if (((unsigned int)p & 0x1c) == 0x1c) { - ppcDcbf((unsigned long) p); - } - } - - dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */ - dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */ - dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */ - dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */ - dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */ - dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */ - dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */ - dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */ - dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */ - dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */ - - for (i = 1; i < dram_size / 0x800000; i++) { - dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); - } + dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); /* * Enable errors for ECC. diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index d47cc5ef3a9..bc6428680e5 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -31,6 +31,21 @@ #include <tsec.h> #include <asm/fsl_law.h> +struct cpu_type cpu_type_list [] = { + CPU_TYPE_ENTRY(8610, 8610), + CPU_TYPE_ENTRY(8641, 8641), + CPU_TYPE_ENTRY(8641D, 8641D), +}; + +struct cpu_type *identify_cpu(u32 ver) +{ + int i; + for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) + if (cpu_type_list[i].soc_ver == ver) + return &cpu_type_list[i]; + + return NULL; +} /* * Default board reset function @@ -53,6 +68,7 @@ checkcpu(void) char buf1[32], buf2[32]; volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; + struct cpu_type *cpu; uint msscr0 = mfspr(MSSCR0); svr = get_svr(); @@ -62,20 +78,13 @@ checkcpu(void) puts("CPU: "); - switch (ver) { - case SVR_8641: - puts("8641"); - break; - case SVR_8641D: - puts("8641D"); - break; - case SVR_8610: - puts("8610"); - break; - default: + cpu = identify_cpu(ver); + if (cpu) { + puts(cpu->name); + } else { puts("Unknown"); - break; } + printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); puts("Core: "); @@ -177,61 +186,6 @@ watchdog_reset(void) } #endif /* CONFIG_WATCHDOG */ - -#if defined(CONFIG_DDR_ECC) -void -dma_init(void) -{ - volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR); - volatile fsl_dma_t *dma = &dma_base->dma[0]; - - dma->satr = 0x00040000; - dma->datr = 0x00040000; - dma->sr = 0xffffffff; /* clear any errors */ - asm("sync; isync"); -} - -uint -dma_check(void) -{ - volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR); - volatile fsl_dma_t *dma = &dma_base->dma[0]; - volatile uint status = dma->sr; - - /* While the channel is busy, spin */ - while ((status & 4) == 4) { - status = dma->sr; - } - - /* clear MR[CS] channel start bit */ - dma->mr &= 0x00000001; - asm("sync;isync"); - - if (status != 0) { - printf("DMA Error: status = %x\n", status); - } - return status; -} - -int -dma_xfer(void *dest, uint count, void *src) -{ - volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR); - volatile fsl_dma_t *dma = &dma_base->dma[0]; - - dma->dar = (uint) dest; - dma->sar = (uint) src; - dma->bcr = count; - dma->mr = 0xf000004; - asm("sync;isync"); - dma->mr = 0xf000005; - asm("sync;isync"); - return dma_check(); -} - -#endif /* CONFIG_DDR_ECC */ - - /* * Print out the state of various machine registers. * Currently prints out LAWs, BR0/OR0, and BATs diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 49528aae713..341e815961c 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -113,6 +113,9 @@ void cpu_init_f(void) memctl->or7 = CONFIG_SYS_OR7_PRELIM; memctl->br7 = CONFIG_SYS_BR7_PRELIM; #endif +#if defined(CONFIG_FSL_DMA) + dma_init(); +#endif /* enable the timebase bit in HID0 */ set_hid0(get_hid0() | 0x4000000); diff --git a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index 8d686ac5d91..13d234e9331 100644 --- a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -68,7 +68,7 @@ compute_ranksize(const ddr3_spd_eeprom_t *spd) if ((spd->organization & 0x7) < 4) nbit_sdram_width = (spd->organization & 0x7) + 2; - bsize = 1 << (nbit_sdram_cap_bsize - 3 + bsize = 1ULL << (nbit_sdram_cap_bsize - 3 + nbit_primary_bus_width - nbit_sdram_width); debug("DDR: DDR III rank density = 0x%08x\n", bsize); diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index cf29efa0272..36d99f9b111 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libdma.a COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o +COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c new file mode 100644 index 00000000000..df33e7a3eec --- /dev/null +++ b/drivers/dma/fsl_dma.c @@ -0,0 +1,178 @@ +/* + * Copyright 2004,2007,2008 Freescale Semiconductor, Inc. + * (C) Copyright 2002, 2003 Motorola Inc. + * Xianghua Xiao (X.Xiao@motorola.com) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/fsl_dma.h> + +/* Controller can only transfer 2^26 - 1 bytes at a time */ +#define FSL_DMA_MAX_SIZE (0x3ffffff) + +#if defined(CONFIG_MPC83xx) +#define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_CTM_DIRECT | FSL_DMA_MR_DMSEN) +#else +#define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT) +#endif + + +#if defined(CONFIG_MPC83xx) +dma83xx_t *dma_base = (void *)(CONFIG_SYS_MPC83xx_DMA_ADDR); +#elif defined(CONFIG_MPC85xx) +ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); +#elif defined(CONFIG_MPC86xx) +ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR); +#else +#error "Freescale DMA engine not supported on your processor" +#endif + +static void dma_sync(void) +{ +#if defined(CONFIG_MPC85xx) + asm("sync; isync; msync"); +#elif defined(CONFIG_MPC86xx) + asm("sync; isync"); +#endif +} + +static void out_dma32(volatile unsigned *addr, int val) +{ +#if defined(CONFIG_MPC83xx) + out_le32(addr, val); +#else + out_be32(addr, val); +#endif +} + +static uint in_dma32(volatile unsigned *addr) +{ +#if defined(CONFIG_MPC83xx) + return in_le32(addr); +#else + return in_be32(addr); +#endif +} + +static uint dma_check(void) { + volatile fsl_dma_t *dma = &dma_base->dma[0]; + uint status; + + /* While the channel is busy, spin */ + do { + status = in_dma32(&dma->sr); + } while (status & FSL_DMA_SR_CB); + + /* clear MR[CS] channel start bit */ + out_dma32(&dma->mr, in_dma32(&dma->mr) & ~FSL_DMA_MR_CS); + dma_sync(); + + if (status != 0) + printf ("DMA Error: status = %x\n", status); + + return status; +} + +#if !defined(CONFIG_MPC83xx) +void dma_init(void) { + volatile fsl_dma_t *dma = &dma_base->dma[0]; + + out_dma32(&dma->satr, FSL_DMA_SATR_SREAD_SNOOP); + out_dma32(&dma->datr, FSL_DMA_DATR_DWRITE_SNOOP); + out_dma32(&dma->sr, 0xffffffff); /* clear any errors */ + dma_sync(); +} +#endif + +int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) { + volatile fsl_dma_t *dma = &dma_base->dma[0]; + uint xfer_size; + + while (count) { + xfer_size = MIN(FSL_DMA_MAX_SIZE, count); + + out_dma32(&dma->dar, (uint) dest); + out_dma32(&dma->sar, (uint) src); + out_dma32(&dma->bcr, xfer_size); + dma_sync(); + + /* Prepare mode register */ + out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT); + dma_sync(); + + /* Start the transfer */ + out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT | FSL_DMA_MR_CS); + + count -= xfer_size; + src += xfer_size; + dest += xfer_size; + + dma_sync(); + + if (dma_check()) + return -1; + } + + return 0; +} + +/* + * 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER + * while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA + */ +#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \ + !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \ + (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA))) +void dma_meminit(uint val, uint size) +{ + uint *p = 0; + uint i = 0; + + for (*p = 0; p < (uint *)(8 * 1024); p++) { + if (((uint)p & 0x1f) == 0) + ppcDcbz((ulong)p); + + *p = (uint)CONFIG_MEM_INIT_VALUE; + + if (((uint)p & 0x1c) == 0x1c) + ppcDcbf((ulong)p); + } + + dmacpy(0x002000, 0, 0x002000); /* 8K */ + dmacpy(0x004000, 0, 0x004000); /* 16K */ + dmacpy(0x008000, 0, 0x008000); /* 32K */ + dmacpy(0x010000, 0, 0x010000); /* 64K */ + dmacpy(0x020000, 0, 0x020000); /* 128K */ + dmacpy(0x040000, 0, 0x040000); /* 256K */ + dmacpy(0x080000, 0, 0x080000); /* 512K */ + dmacpy(0x100000, 0, 0x100000); /* 1M */ + dmacpy(0x200000, 0, 0x200000); /* 2M */ + dmacpy(0x400000, 0, 0x400000); /* 4M */ + + for (i = 1; i < size / 0x800000; i++) + dmacpy((0x800000 * i), 0, 0x800000); +} +#endif diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/bfin-twi_i2c.c index cfe55cd1d28..e7906340799 100644 --- a/drivers/i2c/bfin-twi_i2c.c +++ b/drivers/i2c/bfin-twi_i2c.c @@ -164,7 +164,7 @@ static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, /* prime the pump */ if (msg.alen) { - len = msg.alen; + len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len; debugi("first byte=0x%02x", *msg.abuf); bfin_write_TWI_XMT_DATA8(*(msg.abuf++)); --msg.alen; @@ -275,7 +275,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) * @chip: i2c chip addr * @addr: memory (register) address in the chip * @alen: byte size of address - * @buffer: buffer to store data read from chip + * @buffer: buffer holding data to write to chip * @len: how many bytes to write * @return: 0 on success, non-0 on failure */ diff --git a/drivers/mtd/spi/macronix.c b/drivers/mtd/spi/macronix.c index 9464c8440da..fe1310bf946 100644 --- a/drivers/mtd/spi/macronix.c +++ b/drivers/mtd/spi/macronix.c @@ -49,18 +49,10 @@ #define CMD_MX25XX_DP 0xb9 /* Deep Power-down */ #define CMD_MX25XX_RES 0xab /* Release from DP, and Read Signature */ -#define MXIC_ID_MX2516 0x15 -#define MXIC_ID_MX2520 0x12 -#define MXIC_ID_MX2532 0x16 -#define MXIC_ID_MX2540 0x13 -#define MXIC_ID_MX2564 0x17 -#define MXIC_ID_MX2580 0x14 -#define MXIC_ID_MX25128 0x18 - #define MACRONIX_SR_WIP (1 << 0) /* Write-in-Progress */ struct macronix_spi_flash_params { - u8 idcode1; + u16 idcode; u16 page_size; u16 pages_per_sector; u16 sectors_per_block; @@ -81,13 +73,45 @@ static inline struct macronix_spi_flash *to_macronix_spi_flash(struct spi_flash static const struct macronix_spi_flash_params macronix_spi_flash_table[] = { { - .idcode1 = MXIC_ID_MX25128, + .idcode = 0x2015, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "MX25L1605D", + }, + { + .idcode = 0x2016, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "MX25L3205D", + }, + { + .idcode = 0x2017, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "MX25L6405D", + }, + { + .idcode = 0x2018, .page_size = 256, .pages_per_sector = 16, .sectors_per_block = 16, .nr_blocks = 256, .name = "MX25L12805D", }, + { + .idcode = 0x2618, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 256, + .name = "MX25L12855E", + }, }; static int macronix_wait_ready(struct spi_flash *flash, unsigned long timeout) @@ -277,15 +301,16 @@ struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode) const struct macronix_spi_flash_params *params; struct macronix_spi_flash *mcx; unsigned int i; + u16 id = idcode[2] | idcode[1] << 8; for (i = 0; i < ARRAY_SIZE(macronix_spi_flash_table); i++) { params = ¯onix_spi_flash_table[i]; - if (params->idcode1 == idcode[2]) + if (params->idcode == id) break; } if (i == ARRAY_SIZE(macronix_spi_flash_table)) { - debug("SF: Unsupported Macronix ID %02x\n", idcode[1]); + debug("SF: Unsupported Macronix ID %04x\n", id); return NULL; } diff --git a/drivers/mtd/spi/sst.c b/drivers/mtd/spi/sst.c index 62236d495c0..50e929918a8 100644 --- a/drivers/mtd/spi/sst.c +++ b/drivers/mtd/spi/sst.c @@ -55,20 +55,36 @@ static inline struct sst_spi_flash *to_sst_spi_flash(struct spi_flash *flash) #define SST_SECTOR_SIZE (4 * 1024) static const struct sst_spi_flash_params sst_spi_flash_table[] = { { - .idcode1 = 0x01, + .idcode1 = 0x8d, .nr_sectors = 128, + .name = "SST25VF040B", + },{ + .idcode1 = 0x8e, + .nr_sectors = 256, + .name = "SST25VF080B", + },{ + .idcode1 = 0x41, + .nr_sectors = 512, + .name = "SST25VF016B", + },{ + .idcode1 = 0x4a, + .nr_sectors = 1024, + .name = "SST25VF032B", + },{ + .idcode1 = 0x01, + .nr_sectors = 16, .name = "SST25WF512", },{ .idcode1 = 0x02, - .nr_sectors = 256, + .nr_sectors = 32, .name = "SST25WF010", },{ .idcode1 = 0x03, - .nr_sectors = 512, + .nr_sectors = 64, .name = "SST25WF020", },{ .idcode1 = 0x04, - .nr_sectors = 1024, + .nr_sectors = 128, .name = "SST25WF040", }, }; diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 4f50b2db629..354e80b528e 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -536,7 +536,7 @@ static int io_init(struct ubi_device *ubi) */ ubi->peb_size = ubi->mtd->erasesize; - ubi->peb_count = ubi->mtd->size / ubi->mtd->erasesize; + ubi->peb_count = mtd_div_by_eb(ubi->mtd->size, ubi->mtd); ubi->flash_size = ubi->mtd->size; if (ubi->mtd->block_isbad && ubi->mtd->block_markbad) diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index 7bf3e0a96d1..587605dfd1f 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -259,9 +259,6 @@ static const struct fixed_phy_port fixed_phy_port[] = { /*-----------------------------------------------------------------------------+ * Global variables. TX and RX descriptors and buffers. *-----------------------------------------------------------------------------*/ -#if !defined(CONFIG_NET_MULTI) -struct eth_device *emac0_dev = NULL; -#endif /* * Get count of EMAC devices (doesn't have to be the max. possible number @@ -1643,11 +1640,7 @@ int enetInt (struct eth_device *dev) * Because the mal is generic, we need to get the current * eth device */ -#if defined(CONFIG_NET_MULTI) dev = eth_get_dev(); -#else - dev = emac0_dev; -#endif hw_p = dev->priv; @@ -2066,60 +2059,13 @@ int ppc_4xx_eth_initialize (bd_t * bis) virgin = 1; } -#if defined(CONFIG_NET_MULTI) eth_register (dev); -#else - emac0_dev = dev; -#endif -#if defined(CONFIG_NET_MULTI) #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register (dev->name, emac4xx_miiphy_read, emac4xx_miiphy_write); #endif -#endif } /* end for each supported device */ return 0; } - -#if !defined(CONFIG_NET_MULTI) -void eth_halt (void) { - if (emac0_dev) { - ppc_4xx_eth_halt(emac0_dev); - free(emac0_dev); - emac0_dev = NULL; - } -} - -int eth_init (bd_t *bis) -{ - ppc_4xx_eth_initialize(bis); - if (emac0_dev) { - return ppc_4xx_eth_init(emac0_dev, bis); - } else { - printf("ERROR: ethaddr not set!\n"); - return -1; - } -} - -int eth_send(volatile void *packet, int length) -{ - return (ppc_4xx_eth_send(emac0_dev, packet, length)); -} - -int eth_rx(void) -{ - return (ppc_4xx_eth_rx(emac0_dev)); -} - -int emac4xx_miiphy_initialize (bd_t * bis) -{ -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register ("ppc_4xx_eth0", - emac4xx_miiphy_read, emac4xx_miiphy_write); -#endif - - return 0; -} -#endif /* !defined(CONFIG_NET_MULTI) */ diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a360a50655b..c6097c3c5f5 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_ENC28J60) += enc28j60.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o COBJS-$(CONFIG_GRETH) += greth.o COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o +COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o COBJS-$(CONFIG_DRIVER_LAN91C96) += lan91c96.o COBJS-$(CONFIG_MACB) += macb.o @@ -64,6 +65,7 @@ COBJS-$(CONFIG_SH_ETHER) += sh_eth.o COBJS-$(CONFIG_DRIVER_SMC91111) += smc91111.o COBJS-$(CONFIG_DRIVER_SMC911X) += smc911x.o COBJS-$(CONFIG_TIGON3) += tigon3.o bcm570x_autoneg.o 5701rls.o +COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o COBJS-$(CONFIG_TSEC_ENET) += tsec.o COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o COBJS-$(CONFIG_ULI526X) += uli526x.o diff --git a/cpu/arm926ejs/davinci/ether.c b/drivers/net/davinci_emac.c index f6f81df6caf..fa8cee4d2ef 100644 --- a/cpu/arm926ejs/davinci/ether.c +++ b/drivers/net/davinci_emac.c @@ -40,21 +40,12 @@ #include <command.h> #include <net.h> #include <miiphy.h> +#include <malloc.h> #include <asm/arch/emac_defs.h> -#ifdef CONFIG_DRIVER_TI_EMAC - -#ifdef CONFIG_CMD_NET - unsigned int emac_dbg = 0; #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) -/* Internal static functions */ -static int davinci_eth_hw_init (void); -static int davinci_eth_open (void); -static int davinci_eth_close (void); -static int davinci_eth_send_packet (volatile void *packet, int length); -static int davinci_eth_rcv_packet (void); static void davinci_eth_mdio_enable(void); static int gen_init_phy(int phy_addr); @@ -62,38 +53,10 @@ static int gen_is_phy_connected(int phy_addr); static int gen_get_link_speed(int phy_addr); static int gen_auto_negotiate(int phy_addr); -/* Wrappers exported to the U-Boot proper */ -int eth_hw_init(void) -{ - return(davinci_eth_hw_init()); -} - -int eth_init(bd_t * bd) -{ - return(davinci_eth_open()); -} - -void eth_halt(void) -{ - davinci_eth_close(); -} - -int eth_send(volatile void *packet, int length) -{ - return(davinci_eth_send_packet(packet, length)); -} - -int eth_rx(void) -{ - return(davinci_eth_rcv_packet()); -} - void eth_mdio_enable(void) { davinci_eth_mdio_enable(); } -/* End of wrappers */ - static u_int8_t davinci_eth_mac_addr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; @@ -283,88 +246,11 @@ static int davinci_mii_phy_write(char *devname, unsigned char addr, unsigned cha return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1); } -int davinci_eth_miiphy_initialize(bd_t *bis) -{ - miiphy_register(phy.name, davinci_mii_phy_read, davinci_mii_phy_write); - - return(1); -} #endif -/* - * This function initializes the emac hardware. It does NOT initialize - * EMAC modules power or pin multiplexors, that is done by board_init() - * much earlier in bootup process. Returns 1 on success, 0 otherwise. - */ -static int davinci_eth_hw_init(void) -{ - u_int32_t phy_id; - u_int16_t tmp; - int i; - - davinci_eth_mdio_enable(); - - for (i = 0; i < 256; i++) { - if (adap_mdio->ALIVE) - break; - udelay(10); - } - - if (i >= 256) { - printf("No ETH PHY detected!!!\n"); - return(0); - } - - /* Find if a PHY is connected and get it's address */ - if (!davinci_eth_phy_detect()) - return(0); - - /* Get PHY ID and initialize phy_ops for a detected PHY */ - if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) { - active_phy_addr = 0xff; - return(0); - } - - phy_id = (tmp << 16) & 0xffff0000; - - if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) { - active_phy_addr = 0xff; - return(0); - } - - phy_id |= tmp & 0x0000ffff; - - switch (phy_id) { - case PHY_LXT972: - sprintf(phy.name, "LXT972 @ 0x%02x", active_phy_addr); - phy.init = lxt972_init_phy; - phy.is_phy_connected = lxt972_is_phy_connected; - phy.get_link_speed = lxt972_get_link_speed; - phy.auto_negotiate = lxt972_auto_negotiate; - break; - case PHY_DP83848: - sprintf(phy.name, "DP83848 @ 0x%02x", active_phy_addr); - phy.init = dp83848_init_phy; - phy.is_phy_connected = dp83848_is_phy_connected; - phy.get_link_speed = dp83848_get_link_speed; - phy.auto_negotiate = dp83848_auto_negotiate; - break; - default: - sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr); - phy.init = gen_init_phy; - phy.is_phy_connected = gen_is_phy_connected; - phy.get_link_speed = gen_get_link_speed; - phy.auto_negotiate = gen_auto_negotiate; - } - - printf("Ethernet PHY: %s\n", phy.name); - - return(1); -} - /* Eth device open */ -static int davinci_eth_open(void) +static int davinci_eth_open(struct eth_device *dev, bd_t *bis) { dv_reg_p addr; u_int32_t clkdiv, cnt; @@ -516,7 +402,7 @@ static void davinci_eth_ch_teardown(int ch) } /* Eth device close */ -static int davinci_eth_close(void) +static void davinci_eth_close(struct eth_device *dev) { debug_emac("+ emac_close\n"); @@ -528,7 +414,6 @@ static int davinci_eth_close(void) adap_ewrap->EWCTL = 0; debug_emac("- emac_close\n"); - return(1); } static int tx_send_loop = 0; @@ -537,7 +422,8 @@ static int tx_send_loop = 0; * This function sends a single packet on the network and returns * positive number (number of bytes transmitted) or negative for error */ -static int davinci_eth_send_packet (volatile void *packet, int length) +static int davinci_eth_send_packet (struct eth_device *dev, + volatile void *packet, int length) { int ret_status = -1; @@ -584,7 +470,7 @@ static int davinci_eth_send_packet (volatile void *packet, int length) /* * This function handles receipt of a packet from the network */ -static int davinci_eth_rcv_packet (void) +static int davinci_eth_rcv_packet (struct eth_device *dev) { volatile emac_desc *rx_curr_desc; volatile emac_desc *curr_desc; @@ -650,6 +536,90 @@ static int davinci_eth_rcv_packet (void) return (0); } -#endif /* CONFIG_CMD_NET */ +/* + * This function initializes the emac hardware. It does NOT initialize + * EMAC modules power or pin multiplexors, that is done by board_init() + * much earlier in bootup process. Returns 1 on success, 0 otherwise. + */ +int davinci_emac_initialize(void) +{ + u_int32_t phy_id; + u_int16_t tmp; + int i; + struct eth_device *dev; + + dev = malloc(sizeof *dev); + + if (dev == NULL) + return -1; + + memset(dev, 0, sizeof *dev); + + dev->iobase = 0; + dev->init = davinci_eth_open; + dev->halt = davinci_eth_close; + dev->send = davinci_eth_send_packet; + dev->recv = davinci_eth_rcv_packet; + + eth_register(dev); + + davinci_eth_mdio_enable(); + + for (i = 0; i < 256; i++) { + if (adap_mdio->ALIVE) + break; + udelay(10); + } + + if (i >= 256) { + printf("No ETH PHY detected!!!\n"); + return(0); + } + + /* Find if a PHY is connected and get it's address */ + if (!davinci_eth_phy_detect()) + return(0); + + /* Get PHY ID and initialize phy_ops for a detected PHY */ + if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) { + active_phy_addr = 0xff; + return(0); + } + + phy_id = (tmp << 16) & 0xffff0000; + + if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) { + active_phy_addr = 0xff; + return(0); + } + + phy_id |= tmp & 0x0000ffff; + + switch (phy_id) { + case PHY_LXT972: + sprintf(phy.name, "LXT972 @ 0x%02x", active_phy_addr); + phy.init = lxt972_init_phy; + phy.is_phy_connected = lxt972_is_phy_connected; + phy.get_link_speed = lxt972_get_link_speed; + phy.auto_negotiate = lxt972_auto_negotiate; + break; + case PHY_DP83848: + sprintf(phy.name, "DP83848 @ 0x%02x", active_phy_addr); + phy.init = dp83848_init_phy; + phy.is_phy_connected = dp83848_is_phy_connected; + phy.get_link_speed = dp83848_get_link_speed; + phy.auto_negotiate = dp83848_auto_negotiate; + break; + default: + sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr); + phy.init = gen_init_phy; + phy.is_phy_connected = gen_is_phy_connected; + phy.get_link_speed = gen_get_link_speed; + phy.auto_negotiate = gen_auto_negotiate; + } -#endif /* CONFIG_DRIVER_TI_EMAC */ + printf("Ethernet PHY: %s\n", phy.name); + + miiphy_register(phy.name, davinci_mii_phy_read, davinci_mii_phy_write); + return(1); +} diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index f1394354eb3..efe913589f2 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -103,14 +103,12 @@ typedef struct board_info { void (*outblk)(volatile void *data_ptr, int count); void (*inblk)(void *data_ptr, int count); void (*rx_status)(u16 *RxStatus, u16 *RxLen); + struct eth_device netdev; } board_info_t; static board_info_t dm9000_info; + /* function declaration ------------------------------------- */ -int eth_init(bd_t * bd); -int eth_send(volatile void *, int); -int eth_rx(void); -void eth_halt(void); static int dm9000_probe(void); static u16 phy_read(int); static void phy_write(int, u16); @@ -279,17 +277,16 @@ dm9000_reset(void) printf("ERROR: resetting DM9000 -> not responding\n"); } -/* Initilize dm9000 board +/* Initialize dm9000 board */ -int -eth_init(bd_t * bd) +static int dm9000_init(struct eth_device *dev, bd_t *bd) { int i, oft, lnk; u8 io_mode; struct board_info *db = &dm9000_info; uchar enetaddr[6]; - DM9000_DBG("eth_init()\n"); + DM9000_DBG("%s\n", __func__); /* RESET device */ dm9000_reset(); @@ -411,13 +408,13 @@ eth_init(bd_t * bd) Hardware start transmission. Send a packet to media from the upper layer. */ -int -eth_send(volatile void *packet, int length) +static int dm9000_send(struct eth_device *netdev, volatile void *packet, + int length) { int tmo; struct board_info *db = &dm9000_info; - DM9000_DMP_PACKET("eth_send", packet, length); + DM9000_DMP_PACKET(__func__ , packet, length); DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ @@ -453,10 +450,9 @@ eth_send(volatile void *packet, int length) Stop the interface. The interface is stopped when it is brought. */ -void -eth_halt(void) +static void dm9000_halt(struct eth_device *netdev) { - DM9000_DBG("eth_halt\n"); + DM9000_DBG("%s\n", __func__); /* RESET devie */ phy_write(0, 0x8000); /* PHY RESET */ @@ -468,8 +464,7 @@ eth_halt(void) /* Received a packet and pass to upper layer */ -int -eth_rx(void) +static int dm9000_rx(struct eth_device *netdev) { u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0]; u16 RxStatus, RxLen = 0; @@ -529,7 +524,7 @@ eth_rx(void) dm9000_reset(); } } else { - DM9000_DMP_PACKET("eth_rx", rdptr, RxLen); + DM9000_DMP_PACKET(__func__ , rdptr, RxLen); DM9000_DBG("passing packet to upper layer\n"); NetReceive(NetRxPackets[0], RxLen); @@ -621,3 +616,18 @@ phy_write(int reg, u16 value) DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value); } + +int dm9000_initialize(bd_t *bis) +{ + struct eth_device *dev = &(dm9000_info.netdev); + + dev->init = dm9000_init; + dev->halt = dm9000_halt; + dev->send = dm9000_send; + dev->recv = dm9000_rx; + sprintf(dev->name, "dm9000"); + + eth_register(dev); + + return 0; +} diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c new file mode 100644 index 00000000000..b43bbf2b3d2 --- /dev/null +++ b/drivers/net/kirkwood_egiga.c @@ -0,0 +1,664 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * (C) Copyright 2003 + * Ingo Assmus <ingo.assmus@keymile.com> + * + * based on - Driver for MV64360X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <net.h> +#include <malloc.h> +#include <miiphy.h> +#include <asm/errno.h> +#include <asm/types.h> +#include <asm/byteorder.h> +#include <asm/arch/kirkwood.h> +#include "kirkwood_egiga.h" + +/* + * smi_reg_read - miiphy_read callback function. + * + * Returns 16bit phy register value, or 0xffff on error + */ +static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct kwgbe_device *dkwgbe = to_dkwgbe(dev); + struct kwgbe_registers *regs = dkwgbe->regs; + u32 smi_reg; + volatile u32 timeout; + + /* Phyadr read request */ + if (phy_adr == 0xEE && reg_ofs == 0xEE) { + /* */ + *data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK); + return 0; + } + /* check parameters */ + if (phy_adr > PHYADR_MASK) { + printf("Err..(%s) Invalid PHY address %d\n", + __FUNCTION__, phy_adr); + return -EFAULT; + } + if (reg_ofs > PHYREG_MASK) { + printf("Err..(%s) Invalid register offset %d\n", + __FUNCTION__, reg_ofs); + return -EFAULT; + } + + timeout = KWGBE_PHY_SMI_TIMEOUT; + /* wait till the SMI is not busy */ + do { + /* read smi register */ + smi_reg = KWGBEREG_RD(regs->smi); + if (timeout-- == 0) { + printf("Err..(%s) SMI busy timeout\n", __FUNCTION__); + return -EFAULT; + } + } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK); + + /* fill the phy address and regiser offset and read opcode */ + smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS) + | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS) + | KWGBE_PHY_SMI_OPCODE_READ; + + /* write the smi register */ + KWGBEREG_WR(regs->smi, smi_reg); + + /*wait till read value is ready */ + timeout = KWGBE_PHY_SMI_TIMEOUT; + + do { + /* read smi register */ + smi_reg = KWGBEREG_RD(regs->smi); + if (timeout-- == 0) { + printf("Err..(%s) SMI read ready timeout\n", + __FUNCTION__); + return -EFAULT; + } + } while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK)); + + /* Wait for the data to update in the SMI register */ + for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ; + + *data = (u16) (KWGBEREG_RD(regs->smi) & KWGBE_PHY_SMI_DATA_MASK); + + debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr, + reg_ofs, *data); + + return 0; +} + +/* + * smi_reg_write - imiiphy_write callback function. + * + * Returns 0 if write succeed, -EINVAL on bad parameters + * -ETIME on timeout + */ +static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct kwgbe_device *dkwgbe = to_dkwgbe(dev); + struct kwgbe_registers *regs = dkwgbe->regs; + u32 smi_reg; + volatile u32 timeout; + + /* Phyadr write request*/ + if (phy_adr == 0xEE && reg_ofs == 0xEE) { + KWGBEREG_WR(regs->phyadr, data); + return 0; + } + + /* check parameters */ + if (phy_adr > PHYADR_MASK) { + printf("Err..(%s) Invalid phy address\n", __FUNCTION__); + return -EINVAL; + } + if (reg_ofs > PHYREG_MASK) { + printf("Err..(%s) Invalid register offset\n", __FUNCTION__); + return -EINVAL; + } + + /* wait till the SMI is not busy */ + timeout = KWGBE_PHY_SMI_TIMEOUT; + do { + /* read smi register */ + smi_reg = KWGBEREG_RD(regs->smi); + if (timeout-- == 0) { + printf("Err..(%s) SMI busy timeout\n", __FUNCTION__); + return -ETIME; + } + } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK); + + /* fill the phy addr and reg offset and write opcode and data */ + smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS); + smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS) + | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS); + smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ; + + /* write the smi register */ + KWGBEREG_WR(regs->smi, smi_reg); + + return 0; +} + +/* Stop and checks all queues */ +static void stop_queue(u32 * qreg) +{ + u32 reg_data; + + reg_data = readl(qreg); + + if (reg_data & 0xFF) { + /* Issue stop command for active channels only */ + writel((reg_data << 8), qreg); + + /* Wait for all queue activity to terminate. */ + do { + /* + * Check port cause register that all queues + * are stopped + */ + reg_data = readl(qreg); + } + while (reg_data & 0xFF); + } +} + +/* + * set_access_control - Config address decode parameters for Ethernet unit + * + * This function configures the address decode parameters for the Gigabit + * Ethernet Controller according the given parameters struct. + * + * @regs Register struct pointer. + * @param Address decode parameter struct. + */ +static void set_access_control(struct kwgbe_registers *regs, + struct kwgbe_winparam *param) +{ + u32 access_prot_reg; + + /* Set access control register */ + access_prot_reg = KWGBEREG_RD(regs->epap); + /* clear window permission */ + access_prot_reg &= (~(3 << (param->win * 2))); + access_prot_reg |= (param->access_ctrl << (param->win * 2)); + KWGBEREG_WR(regs->epap, access_prot_reg); + + /* Set window Size reg (SR) */ + KWGBEREG_WR(regs->barsz[param->win].size, + (((param->size / 0x10000) - 1) << 16)); + + /* Set window Base address reg (BA) */ + KWGBEREG_WR(regs->barsz[param->win].bar, + (param->target | param->attrib | param->base_addr)); + /* High address remap reg (HARR) */ + if (param->win < 4) + KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr); + + /* Base address enable reg (BARER) */ + if (param->enable == 1) + KWGBEREG_BITS_RESET(regs->bare, (1 << param->win)); + else + KWGBEREG_BITS_SET(regs->bare, (1 << param->win)); +} + +static void set_dram_access(struct kwgbe_registers *regs) +{ + struct kwgbe_winparam win_param; + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + /* Set access parameters for DRAM bank i */ + win_param.win = i; /* Use Ethernet window i */ + /* Window target - DDR */ + win_param.target = KWGBE_TARGET_DRAM; + /* Enable full access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; + win_param.high_addr = 0; + /* Get bank base */ + win_param.base_addr = kw_sdram_bar(i); + win_param.size = kw_sdram_bs(i); /* Get bank size */ + if (win_param.size == 0) + win_param.enable = 0; + else + win_param.enable = 1; /* Enable the access */ + + /* Enable DRAM bank */ + switch (i) { + case 0: + win_param.attrib = EBAR_DRAM_CS0; + break; + case 1: + win_param.attrib = EBAR_DRAM_CS1; + break; + case 2: + win_param.attrib = EBAR_DRAM_CS2; + break; + case 3: + win_param.attrib = EBAR_DRAM_CS3; + break; + default: + /* invalide bank, disable access */ + win_param.enable = 0; + win_param.attrib = 0; + break; + } + /* Set the access control for address window(EPAPR) RD/WR */ + set_access_control(regs, &win_param); + } +} + +/* + * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables + * + * Go through all the DA filter tables (Unicast, Special Multicast & Other + * Multicast) and set each entry to 0. + */ +static void port_init_mac_tables(struct kwgbe_registers *regs) +{ + int table_index; + + /* Clear DA filter unicast table (Ex_dFUT) */ + for (table_index = 0; table_index < 4; ++table_index) + KWGBEREG_WR(regs->dfut[table_index], 0); + + for (table_index = 0; table_index < 64; ++table_index) { + /* Clear DA filter special multicast table (Ex_dFSMT) */ + KWGBEREG_WR(regs->dfsmt[table_index], 0); + /* Clear DA filter other multicast table (Ex_dFOMT) */ + KWGBEREG_WR(regs->dfomt[table_index], 0); + } +} + +/* + * port_uc_addr - This function Set the port unicast address table + * + * This function locates the proper entry in the Unicast table for the + * specified MAC nibble and sets its properties according to function + * parameters. + * This function add/removes MAC addresses from the port unicast address + * table. + * + * @uc_nibble Unicast MAC Address last nibble. + * @option 0 = Add, 1 = remove address. + * + * RETURN: 1 if output succeeded. 0 if option parameter is invalid. + */ +static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble, + int option) +{ + u32 unicast_reg; + u32 tbl_offset; + u32 reg_offset; + + /* Locate the Unicast table entry */ + uc_nibble = (0xf & uc_nibble); + /* Register offset from unicast table base */ + tbl_offset = (uc_nibble / 4); + /* Entry offset within the above register */ + reg_offset = uc_nibble % 4; + + switch (option) { + case REJECT_MAC_ADDR: + /* + * Clear accepts frame bit at specified unicast + * DA table entry + */ + unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]); + unicast_reg &= (0xFF << (8 * reg_offset)); + KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg); + break; + case ACCEPT_MAC_ADDR: + /* Set accepts frame bit at unicast DA filter table entry */ + unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]); + unicast_reg &= (0xFF << (8 * reg_offset)); + unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset)); + KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg); + break; + default: + return 0; + } + return 1; +} + +/* + * port_uc_addr_set - This function Set the port Unicast address. + */ +static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr) +{ + u32 mac_h; + u32 mac_l; + + mac_l = (p_addr[4] << 8) | (p_addr[5]); + mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | + (p_addr[3] << 0); + + KWGBEREG_WR(regs->macal, mac_l); + KWGBEREG_WR(regs->macah, mac_h); + + /* Accept frames of this address */ + port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR); +} + +/* + * kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. + */ +static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe) +{ + volatile struct kwgbe_rxdesc *p_rx_desc; + int i; + + /* initialize the Rx descriptors ring */ + p_rx_desc = dkwgbe->p_rxdesc; + for (i = 0; i < RINGSZ; i++) { + p_rx_desc->cmd_sts = + KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT; + p_rx_desc->buf_size = PKTSIZE_ALIGN; + p_rx_desc->byte_cnt = 0; + p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN; + if (i == (RINGSZ - 1)) + p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc; + else { + p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *) + ((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE); + p_rx_desc = p_rx_desc->nxtdesc_p; + } + } + dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc; +} + +static int kwgbe_init(struct eth_device *dev) +{ + struct kwgbe_device *dkwgbe = to_dkwgbe(dev); + struct kwgbe_registers *regs = dkwgbe->regs; + + /* setup RX rings */ + kwgbe_init_rx_desc_ring(dkwgbe); + + /* Clear the ethernet port interrupts */ + KWGBEREG_WR(regs->ic, 0); + KWGBEREG_WR(regs->ice, 0); + /* Unmask RX buffer and TX end interrupt */ + KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL); + /* Unmask phy and link status changes interrupts */ + KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT); + + set_dram_access(regs); + port_init_mac_tables(regs); + port_uc_addr_set(regs, dkwgbe->dev.enetaddr); + + /* Assign port configuration and command. */ + KWGBEREG_WR(regs->pxc, PRT_CFG_VAL); + KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE); + KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE); + /* Disable port initially */ + KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN); + + /* Assign port SDMA configuration */ + KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE); + KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL); + KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL); + /* Turn off the port/RXUQ bandwidth limitation */ + KWGBEREG_WR(regs->pmtu, 0); + + /* Set maximum receive buffer to 9700 bytes */ + KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE + | (KWGBEREG_RD(regs->psc0) & MRU_MASK)); + + /* + * Set ethernet MTU for leaky bucket mechanism to 0 - this will + * disable the leaky bucket mechanism . + */ + KWGBEREG_WR(regs->pmtu, 0); + + /* Assignment of Rx CRDB of given RXUQ */ + KWGBEREG_WR(regs->rxcdp[RXUQ].rxcdp, (u32) dkwgbe->p_rxdesc_curr); + /* Enable port Rx. */ + KWGBEREG_WR(regs->rqc, (1 << RXUQ)); + +#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ + && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) + u16 phyadr; + miiphy_read(dev->name, 0xEE, 0xEE, &phyadr); + if (!miiphy_link(dev->name, phyadr)) { + printf("%s: No link on %s\n", __FUNCTION__, dev->name); + return -1; + } +#endif + return 0; +} + +static int kwgbe_halt(struct eth_device *dev) +{ + struct kwgbe_device *dkwgbe = to_dkwgbe(dev); + struct kwgbe_registers *regs = dkwgbe->regs; + + /* Disable all gigE address decoder */ + KWGBEREG_WR(regs->bare, 0x3f); + + stop_queue(®s->tqc); + stop_queue(®s->rqc); + + /* Enable port */ + KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN); + /* Set port is not reset */ + KWGBEREG_BITS_RESET(regs->psc1, 1 << 4); +#ifdef CONFIG_SYS_MII_MODE + /* Set MMI interface up */ + KWGBEREG_BITS_RESET(regs->psc1, 1 << 3); +#endif + /* Disable & mask ethernet port interrupts */ + KWGBEREG_WR(regs->ic, 0); + KWGBEREG_WR(regs->ice, 0); + KWGBEREG_WR(regs->pim, 0); + KWGBEREG_WR(regs->peim, 0); + + return 0; +} + +static int kwgbe_send(struct eth_device *dev, volatile void *dataptr, + int datasize) +{ + struct kwgbe_device *dkwgbe = to_dkwgbe(dev); + struct kwgbe_registers *regs = dkwgbe->regs; + struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc; + + if ((u32) dataptr & 0x07) { + printf("Err..(%s) xmit dataptr not 64bit aligned\n", + __FUNCTION__); + return -1; + } + p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC; + p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC; + p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA; + p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT; + p_txdesc->buf_ptr = (u8 *) dataptr; + p_txdesc->byte_cnt = datasize; + + /* Apply send command using zeroth RXUQ */ + KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc); + KWGBEREG_WR(regs->tqc, (1 << TXUQ)); + + /* + * wait for packet xmit completion + */ + while (p_txdesc->cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) { + /* return fail if error is detected */ + if (p_txdesc->cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) { + printf("Err..(%s) in xmit packet\n", __FUNCTION__); + return -1; + } + }; + return 0; +} + +static int kwgbe_recv(struct eth_device *dev) +{ + volatile struct kwgbe_device *dkwgbe = to_dkwgbe(dev); + volatile struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr; + volatile u32 timeout = 0; + + /* wait untill rx packet available or timeout */ + do { + if (timeout < KWGBE_PHY_SMI_TIMEOUT) + timeout++; + else { + debug("%s time out...\n", __FUNCTION__); + return -1; + } + } while (p_rxdesc_curr->cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA); + + if (p_rxdesc_curr->byte_cnt != 0) { + debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n", + __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt, + (u32) p_rxdesc_curr->buf_ptr, + (u32) p_rxdesc_curr->cmd_sts); + } + + /* + * In case received a packet without first/last bits on + * OR the error summary bit is on, + * the packets needs to be dropeed. + */ + if ((p_rxdesc_curr->cmd_sts & + (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) + != (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) { + + printf("Err..(%s) Dropping packet spread on" + " multiple descriptors\n", __FUNCTION__); + + } else if (p_rxdesc_curr->cmd_sts & KWGBE_ERROR_SUMMARY) { + + printf("Err..(%s) Dropping packet with errors\n", + __FUNCTION__); + + } else { + /* !!! call higher layer processing */ + debug("%s: Sending Received packet to" + " upper layer (NetReceive)\n", __FUNCTION__); + + /* let the upper layer handle the packet */ + NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET), + (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET)); + } + /* + * free these descriptors and point next in the ring + */ + p_rxdesc_curr->cmd_sts = + KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT; + p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; + p_rxdesc_curr->byte_cnt = 0; + + dkwgbe->p_rxdesc_curr = p_rxdesc_curr->nxtdesc_p; + return 0; +} + +int kirkwood_egiga_initialize(bd_t * bis) +{ + struct kwgbe_device *dkwgbe; + struct eth_device *dev; + int devnum; + char *s, buf[NAMESIZE * 2]; + u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS; + + for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) { + /*skip if port is configured not to use */ + if (used_ports[devnum] == 0) + continue; + + if (!(dkwgbe = malloc(sizeof(struct kwgbe_device)))) + goto error1; + + memset(dkwgbe, 0, sizeof(struct kwgbe_device)); + + if (!(dkwgbe->p_rxdesc = + (struct kwgbe_rxdesc *)memalign(PKTALIGN, + KW_RXQ_DESC_ALIGNED_SIZE + * RINGSZ + 1))) + goto error2; + + if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ + * PKTSIZE_ALIGN + 1))) + goto error3; + + if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *) + memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) { + free(dkwgbe->p_rxbuf); + error3: + free(dkwgbe->p_rxdesc); + error2: + free(dkwgbe); + error1: + printf("Err.. %s Failed to allocate memory\n", + __FUNCTION__); + return -1; + } + + dev = &dkwgbe->dev; + + /* must be less than NAMESIZE (16) */ + sprintf(dev->name, "egiga%d", devnum); + + /* Extract the MAC address from the environment */ + switch (devnum) { + case 0: + dkwgbe->regs = (void *)KW_EGIGA0_BASE; + s = "ethaddr"; + break; + case 1: + dkwgbe->regs = (void *)KW_EGIGA1_BASE; + s = "eth1addr"; + break; + default: /* this should never happen */ + printf("Err..(%s) Invalid device number %d\n", + __FUNCTION__, devnum); + return -1; + } + + while (!eth_getenv_enetaddr(s, dev->enetaddr)) { + /* Generate Ramdom MAC addresses if not set */ + sprintf(buf, "00:50:43:%02x:%02x:%02x", + get_random_hex(), get_random_hex(), + get_random_hex()); + setenv(s, buf); + } + + dev->init = (void *)kwgbe_init; + dev->halt = (void *)kwgbe_halt; + dev->send = (void *)kwgbe_send; + dev->recv = (void *)kwgbe_recv; + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, smi_reg_read, smi_reg_write); + /* Set phy address of the port */ + miiphy_write(dev->name, 0xEE, 0xEE, PHY_BASE_ADR + devnum); +#endif + } + return 0; diff --git a/drivers/net/kirkwood_egiga.h b/drivers/net/kirkwood_egiga.h new file mode 100644 index 00000000000..8b67c9c7907 --- /dev/null +++ b/drivers/net/kirkwood_egiga.h @@ -0,0 +1,503 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * based on - Driver for MV64360X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __EGIGA_H__ +#define __EGIGA_H__ + +#define MAX_KWGBE_DEVS 2 /*controller has two ports */ + +/* PHY_BASE_ADR is board specific and can be configured */ +#if defined (CONFIG_PHY_BASE_ADR) +#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR +#else +#define PHY_BASE_ADR 0x08 /* default phy base addr */ +#endif + +/* Constants */ +#define INT_CAUSE_UNMASK_ALL 0x0007ffff +#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff +#define MRU_MASK 0xfff1ffff +#define PHYADR_MASK 0x0000001f +#define PHYREG_MASK 0x0000001f +#define QTKNBKT_DEF_VAL 0x3fffffff +#define QMTBS_DEF_VAL 0x000003ff +#define QTKNRT_DEF_VAL 0x0000fcff +#define RXUQ 0 /* Used Rx queue */ +#define TXUQ 0 /* Used Rx queue */ + +#define to_dkwgbe(_kd) container_of(_kd, struct kwgbe_device, dev) +#define KWGBEREG_WR(adr, val) writel(val, &adr) +#define KWGBEREG_RD(adr) readl(&adr) +#define KWGBEREG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr) +#define KWGBEREG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr) + +/* Default port configuration value */ +#define PRT_CFG_VAL ( \ + KWGBE_UCAST_MOD_NRML | \ + KWGBE_DFLT_RXQ(RXUQ) | \ + KWGBE_DFLT_RX_ARPQ(RXUQ) | \ + KWGBE_RX_BC_IF_NOT_IP_OR_ARP | \ + KWGBE_RX_BC_IF_IP | \ + KWGBE_RX_BC_IF_ARP | \ + KWGBE_CPTR_TCP_FRMS_DIS | \ + KWGBE_CPTR_UDP_FRMS_DIS | \ + KWGBE_DFLT_RX_TCPQ(RXUQ) | \ + KWGBE_DFLT_RX_UDPQ(RXUQ) | \ + KWGBE_DFLT_RX_BPDUQ(RXUQ)) + +/* Default port extend configuration value */ +#define PORT_CFG_EXTEND_VALUE \ + KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \ + KWGBE_PARTITION_DIS | \ + KWGBE_TX_CRC_GENERATION_EN + +#define GT_KWGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8) + +/* Default sdma control value */ +#define PORT_SDMA_CFG_VALUE ( \ + KWGBE_RX_BURST_SIZE_16_64BIT | \ + KWGBE_BLM_RX_NO_SWAP | \ + KWGBE_BLM_TX_NO_SWAP | \ + GT_KWGBE_IPG_INT_RX(RXUQ) | \ + KWGBE_TX_BURST_SIZE_16_64BIT) + +/* Default port serial control value */ +#define PORT_SERIAL_CONTROL_VALUE ( \ + KWGBE_FORCE_LINK_PASS | \ + KWGBE_DIS_AUTO_NEG_FOR_DUPLX | \ + KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ + KWGBE_ADV_NO_FLOW_CTRL | \ + KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + KWGBE_FORCE_BP_MODE_NO_JAM | \ + (1 << 9) /* Reserved bit has to be 1 */ | \ + KWGBE_DO_NOT_FORCE_LINK_FAIL | \ + KWGBE_EN_AUTO_NEG_SPEED_GMII | \ + KWGBE_DTE_ADV_0 | \ + KWGBE_MIIPHY_MAC_MODE | \ + KWGBE_AUTO_NEG_NO_CHANGE | \ + KWGBE_MAX_RX_PACKET_1552BYTE | \ + KWGBE_CLR_EXT_LOOPBACK | \ + KWGBE_SET_FULL_DUPLEX_MODE | \ + KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX) + +/* Tx WRR confoguration macros */ +#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ +#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */ +#define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */ +/* MAC accepet/reject macros */ +#define ACCEPT_MAC_ADDR 0 +#define REJECT_MAC_ADDR 1 +/* Size of a Tx/Rx descriptor used in chain list data structure */ +#define KW_RXQ_DESC_ALIGNED_SIZE \ + (((sizeof(struct kwgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN) +/* Buffer offset from buffer pointer */ +#define RX_BUF_OFFSET 0x2 + +/* Port serial status reg (PSR) */ +#define KWGBE_INTERFACE_GMII_MII 0 +#define KWGBE_INTERFACE_PCM 1 +#define KWGBE_LINK_IS_DOWN 0 +#define KWGBE_LINK_IS_UP (1 << 1) +#define KWGBE_PORT_AT_HALF_DUPLEX 0 +#define KWGBE_PORT_AT_FULL_DUPLEX (1 << 2) +#define KWGBE_RX_FLOW_CTRL_DISD 0 +#define KWGBE_RX_FLOW_CTRL_ENBALED (1 << 3) +#define KWGBE_GMII_SPEED_100_10 0 +#define KWGBE_GMII_SPEED_1000 (1 << 4) +#define KWGBE_MII_SPEED_10 0 +#define KWGBE_MII_SPEED_100 (1 << 5) +#define KWGBE_NO_TX 0 +#define KWGBE_TX_IN_PROGRESS (1 << 7) +#define KWGBE_BYPASS_NO_ACTIVE 0 +#define KWGBE_BYPASS_ACTIVE (1 << 8) +#define KWGBE_PORT_NOT_AT_PARTN_STT 0 +#define KWGBE_PORT_AT_PARTN_STT (1 << 9) +#define KWGBE_PORT_TX_FIFO_NOT_EMPTY 0 +#define KWGBE_PORT_TX_FIFO_EMPTY (1 << 10) + +/* These macros describes the Port configuration reg (Px_cR) bits */ +#define KWGBE_UCAST_MOD_NRML 0 +#define KWGBE_UNICAST_PROMISCUOUS_MODE 1 +#define KWGBE_DFLT_RXQ(_x) (_x << 1) +#define KWGBE_DFLT_RX_ARPQ(_x) (_x << 4) +#define KWGBE_RX_BC_IF_NOT_IP_OR_ARP 0 +#define KWGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7) +#define KWGBE_RX_BC_IF_IP 0 +#define KWGBE_REJECT_BC_IF_IP (1 << 8) +#define KWGBE_RX_BC_IF_ARP 0 +#define KWGBE_REJECT_BC_IF_ARP (1 << 9) +#define KWGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12) +#define KWGBE_CPTR_TCP_FRMS_DIS 0 +#define KWGBE_CPTR_TCP_FRMS_EN (1 << 14) +#define KWGBE_CPTR_UDP_FRMS_DIS 0 +#define KWGBE_CPTR_UDP_FRMS_EN (1 << 15) +#define KWGBE_DFLT_RX_TCPQ(_x) (_x << 16) +#define KWGBE_DFLT_RX_UDPQ(_x) (_x << 19) +#define KWGBE_DFLT_RX_BPDUQ(_x) (_x << 22) +#define KWGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25) + +/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ +#define KWGBE_CLASSIFY_EN 1 +#define KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0 +#define KWGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1) +#define KWGBE_PARTITION_DIS 0 +#define KWGBE_PARTITION_EN (1 << 2) +#define KWGBE_TX_CRC_GENERATION_EN 0 +#define KWGBE_TX_CRC_GENERATION_DIS (1 << 3) + +/* These macros describes the Port Sdma configuration reg (SDCR) bits */ +#define KWGBE_RIFB 1 +#define KWGBE_RX_BURST_SIZE_1_64BIT 0 +#define KWGBE_RX_BURST_SIZE_2_64BIT (1 << 1) +#define KWGBE_RX_BURST_SIZE_4_64BIT (1 << 2) +#define KWGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1)) +#define KWGBE_RX_BURST_SIZE_16_64BIT (1 << 3) +#define KWGBE_BLM_RX_NO_SWAP (1 << 4) +#define KWGBE_BLM_RX_BYTE_SWAP 0 +#define KWGBE_BLM_TX_NO_SWAP (1 << 5) +#define KWGBE_BLM_TX_BYTE_SWAP 0 +#define KWGBE_DESCRIPTORS_BYTE_SWAP (1 << 6) +#define KWGBE_DESCRIPTORS_NO_SWAP 0 +#define KWGBE_TX_BURST_SIZE_1_64BIT 0 +#define KWGBE_TX_BURST_SIZE_2_64BIT (1 << 22) +#define KWGBE_TX_BURST_SIZE_4_64BIT (1 << 23) +#define KWGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22)) +#define KWGBE_TX_BURST_SIZE_16_64BIT (1 << 24) + +/* These macros describes the Port serial control reg (PSCR) bits */ +#define KWGBE_SERIAL_PORT_DIS 0 +#define KWGBE_SERIAL_PORT_EN 1 +#define KWGBE_FORCE_LINK_PASS (1 << 1) +#define KWGBE_DO_NOT_FORCE_LINK_PASS 0 +#define KWGBE_EN_AUTO_NEG_FOR_DUPLX 0 +#define KWGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2) +#define KWGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0 +#define KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) +#define KWGBE_ADV_NO_FLOW_CTRL 0 +#define KWGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4) +#define KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 +#define KWGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5) +#define KWGBE_FORCE_BP_MODE_NO_JAM 0 +#define KWGBE_FORCE_BP_MODE_JAM_TX (1 << 7) +#define KWGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8) +#define KWGBE_FORCE_LINK_FAIL 0 +#define KWGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10) +#define KWGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13) +#define KWGBE_EN_AUTO_NEG_SPEED_GMII 0 +#define KWGBE_DTE_ADV_0 0 +#define KWGBE_DTE_ADV_1 (1 << 14) +#define KWGBE_MIIPHY_MAC_MODE 0 +#define KWGBE_MIIPHY_PHY_MODE (1 << 15) +#define KWGBE_AUTO_NEG_NO_CHANGE 0 +#define KWGBE_RESTART_AUTO_NEG (1 << 16) +#define KWGBE_MAX_RX_PACKET_1518BYTE 0 +#define KWGBE_MAX_RX_PACKET_1522BYTE (1 << 17) +#define KWGBE_MAX_RX_PACKET_1552BYTE (1 << 18) +#define KWGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17)) +#define KWGBE_MAX_RX_PACKET_9192BYTE (1 << 19) +#define KWGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17)) +#define KWGBE_SET_EXT_LOOPBACK (1 << 20) +#define KWGBE_CLR_EXT_LOOPBACK 0 +#define KWGBE_SET_FULL_DUPLEX_MODE (1 << 21) +#define KWGBE_SET_HALF_DUPLEX_MODE 0 +#define KWGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22) +#define KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 +#define KWGBE_SET_GMII_SPEED_TO_10_100 0 +#define KWGBE_SET_GMII_SPEED_TO_1000 (1 << 23) +#define KWGBE_SET_MII_SPEED_TO_10 0 +#define KWGBE_SET_MII_SPEED_TO_100 (1 << 24) + +/* SMI register fields */ +#define KWGBE_PHY_SMI_TIMEOUT 10000 +#define KWGBE_PHY_SMI_DATA_OFFS 0 /* Data */ +#define KWGBE_PHY_SMI_DATA_MASK (0xffff << KWGBE_PHY_SMI_DATA_OFFS) +#define KWGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ +#define KWGBE_PHY_SMI_DEV_ADDR_MASK (PHYADR_MASK << KWGBE_PHY_SMI_DEV_ADDR_OFFS) +#define KWGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */ +#define KWGBE_SMI_REG_ADDR_MASK (PHYADR_MASK << KWGBE_SMI_REG_ADDR_OFFS) +#define KWGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ +#define KWGBE_PHY_SMI_OPCODE_MASK (3 << KWGBE_PHY_SMI_OPCODE_OFFS) +#define KWGBE_PHY_SMI_OPCODE_WRITE (0 << KWGBE_PHY_SMI_OPCODE_OFFS) +#define KWGBE_PHY_SMI_OPCODE_READ (1 << KWGBE_PHY_SMI_OPCODE_OFFS) +#define KWGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */ +#define KWGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */ + +/* SDMA command status fields macros */ +/* Tx & Rx descriptors status */ +#define KWGBE_ERROR_SUMMARY 1 +/* Tx & Rx descriptors command */ +#define KWGBE_BUFFER_OWNED_BY_DMA (1 << 31) +/* Tx descriptors status */ +#define KWGBE_LC_ERROR 0 +#define KWGBE_UR_ERROR (1 << 1) +#define KWGBE_RL_ERROR (1 << 2) +#define KWGBE_LLC_SNAP_FORMAT (1 << 9) + +/* Rx descriptors status */ +#define KWGBE_CRC_ERROR 0 +#define KWGBE_OVERRUN_ERROR (1 << 1) +#define KWGBE_MAX_FRAME_LENGTH_ERROR (1 << 2) +#define KWGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1)) +#define KWGBE_VLAN_TAGGED (1 << 19) +#define KWGBE_BPDU_FRAME (1 << 20) +#define KWGBE_TCP_FRAME_OVER_IP_V_4 0 +#define KWGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21) +#define KWGBE_OTHER_FRAME_TYPE (1 << 22) +#define KWGBE_LAYER_2_IS_KWGBE_V_2 (1 << 23) +#define KWGBE_FRAME_TYPE_IP_V_4 (1 << 24) +#define KWGBE_FRAME_HEADER_OK (1 << 25) +#define KWGBE_RX_LAST_DESC (1 << 26) +#define KWGBE_RX_FIRST_DESC (1 << 27) +#define KWGBE_UNKNOWN_DESTINATION_ADDR (1 << 28) +#define KWGBE_RX_EN_INTERRUPT (1 << 29) +#define KWGBE_LAYER_4_CHECKSUM_OK (1 << 30) + +/* Rx descriptors byte count */ +#define KWGBE_FRAME_FRAGMENTED (1 << 2) + +/* Tx descriptors command */ +#define KWGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10) +#define KWGBE_FRAME_SET_TO_VLAN (1 << 15) +#define KWGBE_TCP_FRAME 0 +#define KWGBE_UDP_FRAME (1 << 16) +#define KWGBE_GEN_TCP_UDP_CHECKSUM (1 << 17) +#define KWGBE_GEN_IP_V_4_CHECKSUM (1 << 18) +#define KWGBE_ZERO_PADDING (1 << 19) +#define KWGBE_TX_LAST_DESC (1 << 20) +#define KWGBE_TX_FIRST_DESC (1 << 21) +#define KWGBE_GEN_CRC (1 << 22) +#define KWGBE_TX_EN_INTERRUPT (1 << 23) +#define KWGBE_AUTO_MODE (1 << 30) + +/* Address decode parameters */ +/* Ethernet Base Address Register bits */ +#define EBAR_TARGET_DRAM 0x00000000 +#define EBAR_TARGET_DEVICE 0x00000001 +#define EBAR_TARGET_CBS 0x00000002 +#define EBAR_TARGET_PCI0 0x00000003 +#define EBAR_TARGET_PCI1 0x00000004 +#define EBAR_TARGET_CUNIT 0x00000005 +#define EBAR_TARGET_AUNIT 0x00000006 +#define EBAR_TARGET_GUNIT 0x00000007 + +/* Window attrib */ +#define EBAR_DRAM_CS0 0x00000E00 +#define EBAR_DRAM_CS1 0x00000D00 +#define EBAR_DRAM_CS2 0x00000B00 +#define EBAR_DRAM_CS3 0x00000700 + +/* DRAM Target interface */ +#define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000 +#define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000 +#define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000 + +/* Device Bus Target interface */ +#define EBAR_DEVICE_DEVCS0 0x00001E00 +#define EBAR_DEVICE_DEVCS1 0x00001D00 +#define EBAR_DEVICE_DEVCS2 0x00001B00 +#define EBAR_DEVICE_DEVCS3 0x00001700 +#define EBAR_DEVICE_BOOTCS3 0x00000F00 + +/* PCI Target interface */ +#define EBAR_PCI_BYTE_SWAP 0x00000000 +#define EBAR_PCI_NO_SWAP 0x00000100 +#define EBAR_PCI_BYTE_WORD_SWAP 0x00000200 +#define EBAR_PCI_WORD_SWAP 0x00000300 +#define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 +#define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400 +#define EBAR_PCI_IO_SPACE 0x00000000 +#define EBAR_PCI_MEMORY_SPACE 0x00000800 +#define EBAR_PCI_REQ64_FORCE 0x00000000 +#define EBAR_PCI_REQ64_SIZE 0x00001000 + +/* Window access control */ +#define EWIN_ACCESS_NOT_ALLOWED 0 +#define EWIN_ACCESS_READ_ONLY 1 +#define EWIN_ACCESS_FULL ((1 << 1) | 1) + +/* structures represents Controller registers */ +struct kwgbe_barsz { + u32 bar; + u32 size; +}; + +struct kwgbe_rxcdp { + struct kwgbe_rxdesc *rxcdp; + u32 rxcdp_pad[3]; +}; + +struct kwgbe_tqx { + u32 qxttbc; + u32 tqxtbc; + u32 tqxac; + u32 tqxpad; +}; + +struct kwgbe_registers { + u32 phyadr; + u32 smi; + u32 euda; + u32 eudid; + u8 pad1[0x080 - 0x00c - 4]; + u32 euic; + u32 euim; + u8 pad2[0x094 - 0x084 - 4]; + u32 euea; + u32 euiae; + u8 pad3[0x0b0 - 0x098 - 4]; + u32 euc; + u8 pad3a[0x200 - 0x0b0 - 4]; + struct kwgbe_barsz barsz[6]; + u8 pad4[0x280 - 0x22c - 4]; + u32 ha_remap[4]; + u32 bare; + u32 epap; + u8 pad5[0x400 - 0x294 - 4]; + u32 pxc; + u32 pxcx; + u32 mii_ser_params; + u8 pad6[0x410 - 0x408 - 4]; + u32 evlane; + u32 macal; + u32 macah; + u32 sdc; + u32 dscp[7]; + u32 psc0; + u32 vpt2p; + u32 ps0; + u32 tqc; + u32 psc1; + u32 ps1; + u32 mrvl_header; + u8 pad7[0x460 - 0x454 - 4]; + u32 ic; + u32 ice; + u32 pim; + u32 peim; + u8 pad8[0x474 - 0x46c - 4]; + u32 pxtfut; + u32 pad9; + u32 pxmfs; + u32 pad10; + u32 pxdfc; + u32 pxofc; + u8 pad11[0x494 - 0x488 - 4]; + u32 peuiae; + u8 pad12[0x4bc - 0x494 - 4]; + u32 eth_type_prio; + u8 pad13[0x4dc - 0x4bc - 4]; + u32 tqfpc; + u32 pttbrc; + u32 tqc1; + u32 pmtu; + u32 pmtbs; + u8 pad14[0x60c - 0x4ec - 4]; + struct kwgbe_rxcdp rxcdp[7]; + u32 rxcdp7; + u32 rqc; + struct kwgbe_txdesc *tcsdp; + u8 pad15[0x6c0 - 0x684 - 4]; + struct kwgbe_txdesc *tcqdp[8]; + u8 pad16[0x700 - 0x6dc - 4]; + struct kwgbe_tqx tqx[8]; + u32 pttbc; + u8 pad17[0x7a8 - 0x780 - 4]; + u32 tqxipg0; + u32 pad18[3]; + u32 tqxipg1; + u8 pad19[0x7c0 - 0x7b8 - 4]; + u32 hitkninlopkt; + u32 hitkninasyncpkt; + u32 lotkninasyncpkt; + u32 pad20; + u32 ts; + u8 pad21[0x3000 - 0x27d0 - 4]; + u32 pad20_1[32]; /* mib counter registes */ + u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32]; + u32 dfsmt[64]; + u32 dfomt[64]; + u32 dfut[4]; + u8 pad23[0xe20c0 - 0x7360c - 4]; + u32 pmbus_top_arbiter; +}; + +/* structures/enums needed by driver */ +enum kwgbe_adrwin { + KWGBE_WIN0, + KWGBE_WIN1, + KWGBE_WIN2, + KWGBE_WIN3, + KWGBE_WIN4, + KWGBE_WIN5 +}; + +enum kwgbe_target { + KWGBE_TARGET_DRAM, + KWGBE_TARGET_DEV, + KWGBE_TARGET_CBS, + KWGBE_TARGET_PCI0, + KWGBE_TARGET_PCI1 +}; + +struct kwgbe_winparam { + enum kwgbe_adrwin win; /* Window number */ + enum kwgbe_target target; /* System targets */ + u16 attrib; /* BAR attrib. See above macros */ + u32 base_addr; /* Window base address in u32 form */ + u32 high_addr; /* Window high address in u32 form */ + u32 size; /* Size in MBytes. Must be % 64Kbyte. */ + int enable; /* Enable/disable access to the window. */ + u16 access_ctrl; /*Access ctrl register. see above macros */ +}; + +struct kwgbe_rxdesc { + u32 cmd_sts; /* Descriptor command status */ + u16 buf_size; /* Buffer size */ + u16 byte_cnt; /* Descriptor buffer byte count */ + u8 *buf_ptr; /* Descriptor buffer pointer */ + struct kwgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */ +}; + +struct kwgbe_txdesc { + u32 cmd_sts; /* Descriptor command status */ + u16 l4i_chk; /* CPU provided TCP Checksum */ + u16 byte_cnt; /* Descriptor buffer byte count */ + u8 *buf_ptr; /* Descriptor buffer ptr */ + struct kwgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */ +}; + +/* port device data struct */ +struct kwgbe_device { + struct eth_device dev; + struct kwgbe_registers *regs; + struct kwgbe_txdesc *p_txdesc; + struct kwgbe_rxdesc *p_rxdesc; + struct kwgbe_rxdesc *p_rxdesc_curr; + u8 *p_rxbuf; +}; + +#endif /* __EGIGA_H__ */ diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index 4f1c0a0127b..4acc29e42cb 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -270,7 +270,7 @@ void __mii_init(void) if ((status & linkgood) == linkgood) break; - udelay(500); + udelay(1); } if (i >= MCFFEC_TOUT_LOOP) { printf("Link UP timeout\n"); diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 4fe3b052121..3b92614ac74 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libphy.a COBJS-$(CONFIG_BITBANGMII) += miiphybb.o +COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c new file mode 100644 index 00000000000..ec47286ddde --- /dev/null +++ b/drivers/net/phy/mv88e61xx.c @@ -0,0 +1,413 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <netdev.h> +#include "mv88e61xx.h" + +#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE +/* Chip Address mode + * The Switch support two modes of operation + * 1. single chip mode and + * 2. Multi-chip mode + * Refer section 9.2 &9.3 in chip datasheet-02 for more details + * + * By default single chip mode is configured + * multichip mode operation can be configured in board header + */ +static int mv88e61xx_busychk_multic(u32 devaddr) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + + /* Poll till SMIBusy bit is clear */ + do { + miiphy_read(name, devaddr, 0x0, ®); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & (1 << 15)); + return 0; +} + +static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + if (!miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { + printf("Error..could not read PHY dev address\n"); + return; + } + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write data to Switch indirect data register */ + miiphy_write(name, mii_dev_addr, 0x1, data); + /* Write command to Switch indirect command register (write) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 << + 15)); +} + +static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + if (!miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { + printf("Error..could not read PHY dev address\n"); + return; + } + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write command to Switch indirect command register (read) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 << + 15)); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Read data from Switch indirect data register */ + miiphy_read(name, mii_dev_addr, 0x1, (u16 *) & data); +} +#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ + +static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig, + u32 max_prtnum, u32 ports_ofs) +{ + u32 prt; + u16 reg; + char *name = swconfig->name; + u32 cpu_port = swconfig->cpuport; + u32 port_mask = swconfig->ports_enabled; + enum mv88e61xx_cfg_vlan vlancfg = swconfig->vlancfg; + + /* be sure all ports are disabled */ + for (prt = 0; prt < max_prtnum; prt++) { + RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, ®); + reg &= ~0x3; + WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, reg); + + if (!(cpu_port & (1 << prt))) + continue; + /* Set CPU port VID to 0x1 */ + RD_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, ®); + reg &= ~0xfff; + reg |= 0x1; + WR_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, reg); + } + + /* Setting Port default priority for all ports to zero */ + for (prt = 0; prt < max_prtnum; prt++) { + RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, ®); + reg &= ~0xc000; + WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, reg); + } + /* Setting VID and VID map for all ports except CPU port */ + for (prt = 0; prt < max_prtnum; prt++) { + /* only for enabled ports */ + if ((1 << prt) & port_mask) { + /* skip CPU port */ + if ((1 << prt) & cpu_port) { + /* + * Set Vlan map table for cpu_port to see + * all ports + */ + RD_PHY(name, (ports_ofs + prt), + MV88E61XX_PRT_VMAP_REG, ®); + reg &= ~((1 << max_prtnum) - 1); + reg |= port_mask & ~(1 << prt); + WR_PHY(name, (ports_ofs + prt), + MV88E61XX_PRT_VMAP_REG, reg); + } else { + + /* + * set Ports VLAN Mapping. + * port prt <--> cpu_port VLAN #prt+1. + */ + RD_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, ®); + reg &= ~0x0fff; + reg |= (prt + 1); + WR_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, reg); + + RD_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, ®); + if (vlancfg == MV88E61XX_VLANCFG_DEFAULT) { + /* + * all any port can send frames to all other ports + * ref: sec 3.2.1.1 of datasheet + */ + reg |= 0x03f; + reg &= ~(1 << prt); + } else if (vlancfg == MV88E61XX_VLANCFG_ROUTER) { + /* + * all other ports can send frames to CPU port only + * ref: sec 3.2.1.2 of datasheet + */ + reg &= ~((1 << max_prtnum) - 1); + reg |= cpu_port; + } + WR_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, reg); + } + } + } + + /* + * enable only appropriate ports to forwarding mode + * and disable the others + */ + for (prt = 0; prt < max_prtnum; prt++) { + if ((1 << prt) & port_mask) { + RD_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, ®); + reg |= 0x3; + WR_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } else { + /* Disable port */ + RD_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, ®); + reg &= ~0x3; + WR_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } + } +} + +/* + * Make sure SMIBusy bit cleared before another + * SMI operation can take place + */ +static int mv88e61xx_busychk(char *name) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + do { + RD_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (u16 *) & reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & 1 << 28); /* busy mask */ + return 0; +} + +/* + * Power up the specified port and reset PHY + */ +static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 prt) +{ + char *name = swconfig->name; + + /* Write Copper Specific control reg1 (0x14) for- + * Enable Phy power up + * Energy Detect on (sense&Xmit NLP Periodically + * reset other settings default + */ + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x3360); + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (0x9410 | (prt << 5))); + + if (mv88e61xx_busychk(name)) + return -1; + + /* Write PHY ctrl reg (0x0) to apply + * Phy reset (set bit 15 low) + * reset other default values + */ + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x1140); + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (0x9400 | (prt << 5))); + + if (mv88e61xx_busychk(name)) + return -1; + + return 0; +} + +/* + * Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3) + * is set to "On-1000Mb/s Link, Off Else" + * This function sets it to "On-Link, Blink-Activity, Off-NoLink" + * + * This is optional settings may be needed on some boards + * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s + * Link status + */ +static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 prt) +{ + char *name = swconfig->name; + u16 reg; + + if (swconfig->led_init != MV88E61XX_LED_INIT_EN) + return 0; + + /* set page address to 3 */ + reg = 3; + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg); + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST | + 1 << MV88E61XX_MODE_OFST | + 1 << MV88E61XX_OP_OFST | + prt << MV88E61XX_ADDR_OFST | 22)); + + if (mv88e61xx_busychk(name)) + return -1; + + /* set LED Func Ctrl reg */ + reg = 1; /* LED[0] On-Link, Blink-Activity, Off-NoLink */ + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg); + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST | + 1 << MV88E61XX_MODE_OFST | + 1 << MV88E61XX_OP_OFST | + prt << MV88E61XX_ADDR_OFST | 16)); + + if (mv88e61xx_busychk(name)) + return -1; + + /* set page address to 0 */ + reg = 0; + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg); + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST | + 1 << MV88E61XX_MODE_OFST | + 1 << MV88E61XX_OP_OFST | + prt << MV88E61XX_ADDR_OFST | 22)); + + if (mv88e61xx_busychk(name)) + return -1; + + return 0; +} + +/* + * Reverse Transmit polarity for Media Dependent Interface + * Pins (MDIP) bits in Copper Specific Control Register 3 + * (Page 0, Reg 20 for each phy (except cpu port) + * Reference: Section 1.1 Switch datasheet-3 + * + * This is optional settings may be needed on some boards + * for PHY<->magnetics h/w tuning + */ +static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 prt) +{ + char *name = swconfig->name; + u16 reg; + + if (swconfig->mdip != MV88E61XX_MDIP_REVERSE) + return 0; + + reg = 0x0f; /*Reverse MDIP/N[3:0] bits */ + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg); + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST | + 1 << MV88E61XX_MODE_OFST | + 1 << MV88E61XX_OP_OFST | + prt << MV88E61XX_ADDR_OFST | 20)); + + if (mv88e61xx_busychk(name)) + return -1; + + return 0; +} + +/* + * Marvell 88E61XX Switch initialization + */ +int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) +{ + u32 prt; + u16 reg; + char *idstr; + char *name = swconfig->name; + + if (miiphy_set_current_dev(name)) { + printf("%s failed\n", __FUNCTION__); + return -1; + } + + if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) { + swconfig->cpuport = (1 << 5); + printf("Invalid cpu port config, using default port5\n"); + } + + RD_PHY(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, ®); + reg &= 0xfff0; + if (reg == 0x1610) + idstr = "88E6161"; + if (reg == 0x1650) + idstr = "88E6165"; + if (reg == 0x1210) { + idstr = "88E6123"; + /* ports 2,3,4 not available */ + swconfig->ports_enabled &= 0x023; + } + + /* Port based VLANs configuration */ + if ((swconfig->vlancfg == MV88E61XX_VLANCFG_DEFAULT) + || (swconfig->vlancfg == MV88E61XX_VLANCFG_ROUTER)) + mv88e61xx_port_vlan_config(swconfig, MV88E61XX_MAX_PORTS_NUM, + MV88E61XX_PRT_OFST); + else { + printf("Unsupported mode %s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) { + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 9.5 of chip datasheet-02 + */ + WR_PHY(name, MV88E61XX_PRT_OFST + 5, + MV88E61XX_RGMII_TIMECTRL_REG, 0x18); + WR_PHY(name, MV88E61XX_PRT_OFST + 4, + MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); + } + + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + if (!((1 << prt) & swconfig->cpuport)) { + + if (mv88361xx_led_init(swconfig, prt)) + return -1; + if (mv88361xx_reverse_mdipn(swconfig, prt)) + return -1; + if (mv88361xx_powerup(swconfig, prt)) + return -1; + } + + /*Program port state */ + RD_PHY(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, ®); + WR_PHY(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, + reg | (swconfig->portstate & 0x03)); + } + + printf("%s Initialized on %s\n", idstr, name); + return 0; +} diff --git a/drivers/net/phy/mv88e61xx.h b/drivers/net/phy/mv88e61xx.h new file mode 100644 index 00000000000..42794644eca --- /dev/null +++ b/drivers/net/phy/mv88e61xx.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _MV88E61XX_H +#define _MV88E61XX_H + +#include <miiphy.h> + +#define MV88E61XX_CPU_PORT 0x5 +#define MV88E61XX_MAX_PORTS_NUM 0x6 + +#define MV88E61XX_PHY_TIMEOUT 100000 + +#define MV88E61XX_PRT_STS_REG 0x1 +#define MV88E61XX_PRT_CTRL_REG 0x4 +#define MV88E61XX_PRT_VMAP_REG 0x6 +#define MV88E61XX_PRT_VID_REG 0x7 + +#define MV88E61XX_PRT_OFST 0x10 +#define MV88E61XX_PHY_CMD 0x18 +#define MV88E61XX_PHY_DATA 0x19 +#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A +#define MV88E61XX_GLB2REG_DEVADR 0x1C + +#define MV88E61XX_BUSY_OFST 15 +#define MV88E61XX_MODE_OFST 12 +#define MV88E61XX_OP_OFST 10 +#define MV88E61XX_ADDR_OFST 5 + +#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE +static int mv88e61xx_busychk_multic(u32 devaddr); +static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data); +static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data); +#define WR_PHY mv88e61xx_wr_phy +#define RD_PHY mv88e61xx_rd_phy +#else +#define WR_PHY miiphy_write +#define RD_PHY miiphy_read +#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ + +#endif /* _MV88E61XX_H */ diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 399116f3a25..63fc02e44d1 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -468,6 +468,18 @@ uint mii_parse_link(uint mii_reg, struct tsec_private *priv) } /* + * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain + * circumstances. eg a gigabit TSEC connected to a gigabit switch with + * a 4-wire ethernet cable. Both ends advertise gigabit, but can't + * link. "Ethernet@Wirespeed" reduces advertised speed until link + * can be achieved. + */ +uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv) +{ + return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010; +} + +/* * Parse the BCM54xx status register for speed and duplex information. * The linux sungem_phy has this information, but in a table format. */ @@ -1070,6 +1082,34 @@ struct phy_info phy_info_BCM5464S = { }, }; +struct phy_info phy_info_BCM5482S = { + 0x0143bcb, + "Broadcom BCM5482S", + 4, + (struct phy_cmd[]) { /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + /* Setup read from auxilary control shadow register 7 */ + {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL}, + /* Read Misc Control register and or in Ethernet@Wirespeed */ + {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + struct phy_info phy_info_M88E1011S = { 0x01410c6, "Marvell 88E1011S", @@ -1611,6 +1651,7 @@ struct phy_info *phy_info[] = { &phy_info_cis8201, &phy_info_BCM5461S, &phy_info_BCM5464S, + &phy_info_BCM5482S, &phy_info_M88E1011S, &phy_info_M88E1111S, &phy_info_M88E1118, diff --git a/include/asm-arm/arch-davinci/emac_defs.h b/include/asm-arm/arch-davinci/emac_defs.h index c11161f5806..ae75f84042a 100644 --- a/include/asm-arm/arch-davinci/emac_defs.h +++ b/include/asm-arm/arch-davinci/emac_defs.h @@ -38,15 +38,38 @@ #include <asm/arch/hardware.h> +#ifdef CONFIG_SOC_DM365 +#define EMAC_BASE_ADDR (0x01d07000) +#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000) +#define EMAC_WRAPPER_RAM_ADDR (0x01d08000) +#define EMAC_MDIO_BASE_ADDR (0x01d0b000) +#else #define EMAC_BASE_ADDR (0x01c80000) #define EMAC_WRAPPER_BASE_ADDR (0x01c81000) #define EMAC_WRAPPER_RAM_ADDR (0x01c82000) #define EMAC_MDIO_BASE_ADDR (0x01c84000) +#endif +#ifdef CONFIG_SOC_DM646x +/* MDIO module input frequency */ +#define EMAC_MDIO_BUS_FREQ 76500000 +/* MDIO clock output frequency */ +#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ +#elif defined(CONFIG_SOC_DM365) +/* MDIO module input frequency */ +#define EMAC_MDIO_BUS_FREQ 121500000 +/* MDIO clock output frequency */ +#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */ +#else /* MDIO module input frequency */ #define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */ /* MDIO clock output frequency */ #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ +#endif + +/* PHY mask - set only those phy number bits where phy is/can be connected */ +#define EMAC_MDIO_PHY_NUM 1 +#define EMAC_MDIO_PHY_MASK (1 << EMAC_MDIO_PHY_NUM) /* Ethernet Min/Max packet size */ #define EMAC_MIN_ETHERNET_PKT_SIZE 60 @@ -103,6 +126,8 @@ typedef volatile struct _emac_desc #define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) +#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) +#define EMAC_MACCONTROL_GIGFORCE (1 << 17) #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) #define EMAC_RXMBPENABLE_RXBROADEN (0x2000) @@ -258,12 +283,17 @@ typedef struct { /* EMAC Wrapper Registers Structure */ typedef struct { +#if defined(CONFIG_SOC_DM646x) || defined(CONFIG_SOC_DM365) + dv_reg IDVER; + dv_reg SOFTRST; + dv_reg EMCTRL; +#else u_int8_t RSVD0[4100]; dv_reg EWCTL; dv_reg EWINTTCNT; +#endif } ewrap_regs; - /* EMAC MDIO Registers Structure */ typedef struct { dv_reg VERSION; diff --git a/include/asm-blackfin/blackfin-config-post.h b/include/asm-blackfin/blackfin-config-post.h deleted file mode 100644 index 623fdc74c69..00000000000 --- a/include/asm-blackfin/blackfin-config-post.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * blackfin-config-post.h - setup common defines for Blackfin boards based on config.h - * - * Copyright (c) 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BLACKFIN_CONFIG_POST_H__ -#define __ASM_BLACKFIN_CONFIG_POST_H__ - -/* Sanity check CONFIG_BFIN_CPU */ -#ifndef CONFIG_BFIN_CPU -# error CONFIG_BFIN_CPU: your board config needs to define this -#endif - -/* Make sure the structure is properly aligned */ -#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR) -# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned -#endif - -/* Set default CONFIG_VCO_HZ if need be */ -#if !defined(CONFIG_VCO_HZ) -# if (CONFIG_CLKIN_HALF == 0) -# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) -# else -# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2) -# endif -#endif - -/* Set default CONFIG_CCLK_HZ if need be */ -#if !defined(CONFIG_CCLK_HZ) -# if (CONFIG_PLL_BYPASS == 0) -# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV) -# else -# define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -# endif -#endif - -/* Set default CONFIG_SCLK_HZ if need be */ -#if !defined(CONFIG_SCLK_HZ) -# if (CONFIG_PLL_BYPASS == 0) -# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV) -# else -# define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ -# endif -#endif - -/* Since we use these to program PLL registers directly, - * make sure the values are sane and won't screw us up. - */ -#if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT -# error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63) -#endif -#if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF -# error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1 -#endif -#if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS -# error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1 -#endif - -/* Using L1 scratch pad makes sense for everyone by default. */ -#ifndef CONFIG_LINUX_CMDLINE_ADDR -# define CONFIG_LINUX_CMDLINE_ADDR L1_SRAM_SCRATCH -#endif -#ifndef CONFIG_LINUX_CMDLINE_SIZE -# define CONFIG_LINUX_CMDLINE_SIZE L1_SRAM_SCRATCH_SIZE -#endif - -/* Set default SPI flash CS to the one we boot from */ -#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_SPI_CS) -# define CONFIG_ENV_SPI_CS BFIN_BOOT_SPI_SSEL -#endif - -/* Default/common Blackfin memory layout */ -#ifndef CONFIG_SYS_SDRAM_BASE -# define CONFIG_SYS_SDRAM_BASE 0 -#endif -#ifndef CONFIG_SYS_MAX_RAM_SIZE -# define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024) -#endif -#ifndef CONFIG_SYS_MONITOR_BASE -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN) -#endif -#ifndef CONFIG_SYS_MALLOC_BASE -# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#endif -#ifndef CONFIG_SYS_GBL_DATA_SIZE -# define CONFIG_SYS_GBL_DATA_SIZE (128) -#endif -#ifndef CONFIG_SYS_GBL_DATA_ADDR -# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) -#endif -#ifndef CONFIG_STACKBASE -# define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4) -#endif -#ifndef CONFIG_SYS_MEMTEST_START -# define CONFIG_SYS_MEMTEST_START 0 -#endif -#ifndef CONFIG_SYS_MEMTEST_END -# define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4) -#endif - -/* Check to make sure everything fits in external RAM */ -#if ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE) -# error Memory Map does not fit into configuration -#endif - -/* Default/common Blackfin environment settings */ -#ifndef CONFIG_LOADADDR -# define CONFIG_LOADADDR 0x1000000 -#endif -#ifndef CONFIG_SYS_LOAD_ADDR -# define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#endif -#ifndef CONFIG_SYS_BOOTM_LEN -# define CONFIG_SYS_BOOTM_LEN 0x4000000 -#endif -#ifndef CONFIG_SYS_PROMPT -# define CONFIG_SYS_PROMPT "bfin> " -#endif -#ifndef CONFIG_SYS_CBSIZE -# ifdef CONFIG_CMD_KGDB -# define CONFIG_SYS_CBSIZE 1024 -# else -# define CONFIG_SYS_CBSIZE 256 -# endif -#endif -#ifndef CONFIG_SYS_BARGSIZE -# define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#endif -#ifndef CONFIG_SYS_PBSIZE -# define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#endif -#ifndef CONFIG_SYS_MAXARGS -# define CONFIG_SYS_MAXARGS 16 -#endif -#if defined(CONFIG_SYS_HZ) -# if (CONFIG_SYS_HZ != 1000) -# warning "CONFIG_SYS_HZ must always be 1000" -# endif -# undef CONFIG_SYS_HZ -#endif -#define CONFIG_SYS_HZ 1000 -#ifndef CONFIG_SYS_BAUDRATE_TABLE -# define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#endif - -#endif diff --git a/include/asm-blackfin/blackfin-config-pre.h b/include/asm-blackfin/config-pre.h index 44f9c2fe663..b1d3a946d3e 100644 --- a/include/asm-blackfin/blackfin-config-pre.h +++ b/include/asm-blackfin/config-pre.h @@ -1,7 +1,7 @@ /* - * blackfin-config-pre.h - common defines for Blackfin boards in config.h + * config-pre.h - common defines for Blackfin boards in config.h * - * Copyright (c) 2007 Analog Devices Inc. + * Copyright (c) 2007-2009 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ diff --git a/include/asm-blackfin/config.h b/include/asm-blackfin/config.h index 049c44eaf84..6623fb7ae10 100644 --- a/include/asm-blackfin/config.h +++ b/include/asm-blackfin/config.h @@ -1,24 +1,149 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * config.h - setup common defines for Blackfin boards based on config.h * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Copyright (c) 2007-2009 Analog Devices Inc. * + * Licensed under the GPL-2 or later. */ -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ +#ifndef __ASM_BLACKFIN_CONFIG_POST_H__ +#define __ASM_BLACKFIN_CONFIG_POST_H__ + +/* Sanity check CONFIG_BFIN_CPU */ +#ifndef CONFIG_BFIN_CPU +# error CONFIG_BFIN_CPU: your board config needs to define this +#endif + +/* Make sure the structure is properly aligned */ +#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR) +# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned +#endif + +/* Set default CONFIG_VCO_HZ if need be */ +#if !defined(CONFIG_VCO_HZ) +# if (CONFIG_CLKIN_HALF == 0) +# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) +# else +# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2) +# endif +#endif + +/* Set default CONFIG_CCLK_HZ if need be */ +#if !defined(CONFIG_CCLK_HZ) +# if (CONFIG_PLL_BYPASS == 0) +# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV) +# else +# define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +# endif +#endif + +/* Set default CONFIG_SCLK_HZ if need be */ +#if !defined(CONFIG_SCLK_HZ) +# if (CONFIG_PLL_BYPASS == 0) +# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV) +# else +# define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +# endif +#endif + +/* Since we use these to program PLL registers directly, + * make sure the values are sane and won't screw us up. + */ +#if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT +# error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63) +#endif +#if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF +# error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1 +#endif +#if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS +# error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1 +#endif + +/* Using L1 scratch pad makes sense for everyone by default. */ +#ifndef CONFIG_LINUX_CMDLINE_ADDR +# define CONFIG_LINUX_CMDLINE_ADDR L1_SRAM_SCRATCH +#endif +#ifndef CONFIG_LINUX_CMDLINE_SIZE +# define CONFIG_LINUX_CMDLINE_SIZE L1_SRAM_SCRATCH_SIZE +#endif + +/* Set default SPI flash CS to the one we boot from */ +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_SPI_CS) +# define CONFIG_ENV_SPI_CS BFIN_BOOT_SPI_SSEL +#endif + +/* Default/common Blackfin memory layout */ +#ifndef CONFIG_SYS_SDRAM_BASE +# define CONFIG_SYS_SDRAM_BASE 0 +#endif +#ifndef CONFIG_SYS_MAX_RAM_SIZE +# define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024) +#endif +#ifndef CONFIG_SYS_MONITOR_BASE +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN) +#endif +#ifndef CONFIG_SYS_MALLOC_BASE +# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) +#endif +#ifndef CONFIG_SYS_GBL_DATA_SIZE +# define CONFIG_SYS_GBL_DATA_SIZE (128) +#endif +#ifndef CONFIG_SYS_GBL_DATA_ADDR +# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) +#endif +#ifndef CONFIG_STACKBASE +# define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4) +#endif +#ifndef CONFIG_SYS_MEMTEST_START +# define CONFIG_SYS_MEMTEST_START 0 +#endif +#ifndef CONFIG_SYS_MEMTEST_END +# define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4) +#endif + +/* Check to make sure everything fits in external RAM */ +#if ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE) +# error Memory Map does not fit into configuration +#endif + +/* Default/common Blackfin environment settings */ +#ifndef CONFIG_LOADADDR +# define CONFIG_LOADADDR 0x1000000 +#endif +#ifndef CONFIG_SYS_LOAD_ADDR +# define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#endif +#ifndef CONFIG_SYS_BOOTM_LEN +# define CONFIG_SYS_BOOTM_LEN 0x4000000 +#endif +#ifndef CONFIG_SYS_PROMPT +# define CONFIG_SYS_PROMPT "bfin> " +#endif +#ifndef CONFIG_SYS_CBSIZE +# ifdef CONFIG_CMD_KGDB +# define CONFIG_SYS_CBSIZE 1024 +# else +# define CONFIG_SYS_CBSIZE 256 +# endif +#endif +#ifndef CONFIG_SYS_BARGSIZE +# define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#endif +#ifndef CONFIG_SYS_PBSIZE +# define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#endif +#ifndef CONFIG_SYS_MAXARGS +# define CONFIG_SYS_MAXARGS 16 +#endif +#if defined(CONFIG_SYS_HZ) +# if (CONFIG_SYS_HZ != 1000) +# warning "CONFIG_SYS_HZ must always be 1000" +# endif +# undef CONFIG_SYS_HZ +#endif +#define CONFIG_SYS_HZ 1000 +#ifndef CONFIG_SYS_BAUDRATE_TABLE +# define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#endif #endif diff --git a/include/asm-blackfin/mach-common/bits/bootrom.h b/include/asm-blackfin/mach-common/bits/bootrom.h index fb97ff81b3b..f537e93f701 100644 --- a/include/asm-blackfin/mach-common/bits/bootrom.h +++ b/include/asm-blackfin/mach-common/bits/bootrom.h @@ -200,6 +200,33 @@ typedef struct ADI_BOOT_DATA { int32_t dLogByteCount; } ADI_BOOT_DATA; +typedef void ADI_BOOT_HOOK_FUNC (ADI_BOOT_DATA *); + +#ifndef _BOOTROM_MEMBOOT +#define _BOOTROM_MEMBOOT 0 +#endif +static uint32_t (* const bfrom_MemBoot)(void *pBootStream, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_MEMBOOT; + +#ifndef _BOOTROM_TWIBOOT +#define _BOOTROM_TWIBOOT 0 +#endif +static uint32_t (* const bfrom_TwiBoot)(int32_t dTwiAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_TWIBOOT; + +#ifndef _BOOTROM_SPIBOOT +#define _BOOTROM_SPIBOOT 0 +#endif +static uint32_t (* const bfrom_SpiBoot)(int32_t dSpiAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_SPIBOOT; + +#ifndef _BOOTROM_OTPBOOT +#define _BOOTROM_OTPBOOT 0 +#endif +static uint32_t (* const bfrom_OtpBoot)(int32_t dOtpAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_OTPBOOT; + +#ifndef _BOOTROM_NANDBOOT +#define _BOOTROM_NANDBOOT 0 +#endif +static uint32_t (* const bfrom_NandBoot)(int32_t dNandAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_NANDBOOT; + #endif /* __ASSEMBLY__ */ /* Bit defines for ADI_BOOT_DATA->dFlags */ diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index 0900f65b96f..ca143c7fef7 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -29,4 +29,12 @@ #endif #endif +#ifndef CONFIG_FSL_DMA +#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \ + !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \ + (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA))) +#define CONFIG_FSL_DMA #endif +#endif + +#endif /* _ASM_CONFIG_H_ */ diff --git a/include/asm-ppc/fsl_dma.h b/include/asm-ppc/fsl_dma.h index aab8720977e..11641912a65 100644 --- a/include/asm-ppc/fsl_dma.h +++ b/include/asm-ppc/fsl_dma.h @@ -27,14 +27,95 @@ #include <asm/types.h> +#ifdef CONFIG_MPC83xx typedef struct fsl_dma { uint mr; /* DMA mode register */ +#define FSL_DMA_MR_CS 0x00000001 /* Channel start */ +#define FSL_DMA_MR_CC 0x00000002 /* Channel continue */ +#define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */ +#define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */ +#define FSL_DMA_MR_EOTIE 0x00000080 /* End-of-transfer interrupt en */ +#define FSL_DMA_MR_PRC_MASK 0x00000c00 /* PCI read command */ +#define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */ +#define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */ +#define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */ +#define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */ +#define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */ +#define FSL_DMA_MR_IRQS 0x00080000 /* Interrupt steer */ +#define FSL_DMA_MR_DMSEN 0x00100000 /* Direct mode snooping en */ +#define FSL_DMA_MR_BWC_MASK 0x00e00000 /* Bandwidth/pause ctl */ +#define FSL_DMA_MR_DRCNT 0x0f000000 /* DMA request count */ uint sr; /* DMA status register */ +#define FSL_DMA_SR_EOCDI 0x00000001 /* End-of-chain/direct interrupt */ +#define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */ +#define FSL_DMA_SR_CB 0x00000004 /* Channel busy */ +#define FSL_DMA_SR_TE 0x00000080 /* Transfer error */ + uint cdar; /* DMA current descriptor address register */ + char res0[4]; + uint sar; /* DMA source address register */ + char res1[4]; + uint dar; /* DMA destination address register */ + char res2[4]; + uint bcr; /* DMA byte count register */ + uint ndar; /* DMA next descriptor address register */ + uint gsr; /* DMA general status register (DMA3 ONLY!) */ + char res3[84]; +} fsl_dma_t; +#else +typedef struct fsl_dma { + uint mr; /* DMA mode register */ +#define FSL_DMA_MR_CS 0x00000001 /* Channel start */ +#define FSL_DMA_MR_CC 0x00000002 /* Channel continue */ +#define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */ +#define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */ +#define FSL_DMA_MR_CA 0x00000008 /* Channel abort */ +#define FSL_DMA_MR_CDSM 0x00000010 +#define FSL_DMA_MR_XFE 0x00000020 /* Extended features en */ +#define FSL_DMA_MR_EIE 0x00000040 /* Error interrupt en */ +#define FSL_DMA_MR_EOLSIE 0x00000080 /* End-of-lists interrupt en */ +#define FSL_DMA_MR_EOLNIE 0x00000100 /* End-of-links interrupt en */ +#define FSL_DMA_MR_EOSIE 0x00000200 /* End-of-seg interrupt en */ +#define FSL_DMA_MR_SRW 0x00000400 /* Single register write */ +#define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */ +#define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */ +#define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */ +#define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */ +#define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */ +#define FSL_DMA_MR_EMP_EN 0x00200000 /* Ext master pause en */ +#define FSL_DMA_MR_BWC_MASK 0x0f000000 /* Bandwidth/pause ctl */ +#define FSL_DMA_MR_BWC_DIS 0x0f000000 /* Bandwidth/pause ctl disable */ + uint sr; /* DMA status register */ +#define FSL_DMA_SR_EOLSI 0x00000001 /* End-of-list interrupt */ +#define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */ +#define FSL_DMA_SR_CB 0x00000004 /* Channel busy */ +#define FSL_DMA_SR_EOLNI 0x00000008 /* End-of-links interrupt */ +#define FSL_DMA_SR_PE 0x00000010 /* Programming error */ +#define FSL_DMA_SR_CH 0x00000020 /* Channel halted */ +#define FSL_DMA_SR_TE 0x00000080 /* Transfer error */ char res0[4]; uint clndar; /* DMA current link descriptor address register */ uint satr; /* DMA source attributes register */ +#define FSL_DMA_SATR_ESAD_MASK 0x000001ff /* Extended source addr */ +#define FSL_DMA_SATR_SREAD_NO_SNOOP 0x00040000 /* Read, don't snoop */ +#define FSL_DMA_SATR_SREAD_SNOOP 0x00050000 /* Read, snoop */ +#define FSL_DMA_SATR_SREAD_UNLOCK 0x00070000 /* Read, unlock l2 */ +#define FSL_DMA_SATR_STRAN_MASK 0x00f00000 /* Source interface */ +#define FSL_DMA_SATR_SSME 0x01000000 /* Source stride en */ +#define FSL_DMA_SATR_SPCIORDER 0x02000000 /* PCI transaction order */ +#define FSL_DMA_SATR_STFLOWLVL_MASK 0x0c000000 /* RIO flow level */ +#define FSL_DMA_SATR_SBPATRMU 0x20000000 /* Bypass ATMU */ uint sar; /* DMA source address register */ uint datr; /* DMA destination attributes register */ +#define FSL_DMA_DATR_EDAD_MASK 0x000001ff /* Extended dest addr */ +#define FSL_DMA_DATR_DWRITE_NO_SNOOP 0x00040000 /* Write, don't snoop */ +#define FSL_DMA_DATR_DWRITE_SNOOP 0x00050000 /* Write, snoop */ +#define FSL_DMA_DATR_DWRITE_ALLOC 0x00060000 /* Write, alloc l2 */ +#define FSL_DMA_DATR_DWRITE_LOCK 0x00070000 /* Write, lock l2 */ +#define FSL_DMA_DATR_DTRAN_MASK 0x00f00000 /* Dest interface */ +#define FSL_DMA_DATR_DSME 0x01000000 /* Dest stride en */ +#define FSL_DMA_DATR_DPCIORDER 0x02000000 /* PCI transaction order */ +#define FSL_DMA_DATR_DTFLOWLVL_MASK 0x0c000000 /* RIO flow level */ +#define FSL_DMA_DATR_DBPATRMU 0x20000000 /* Bypass ATMU */ uint dar; /* DMA destination address register */ uint bcr; /* DMA byte count register */ char res1[4]; @@ -47,5 +128,14 @@ typedef struct fsl_dma { uint dsr; /* DMA destination stride register */ char res4[56]; } fsl_dma_t; +#endif /* !CONFIG_MPC83xx */ + +#ifdef CONFIG_FSL_DMA +void dma_init(void); +int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n); +#if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) +void dma_meminit(uint val, uint size); +#endif +#endif #endif /* _ASM_DMA_H_ */ diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 8f945a15196..7c6a15185e1 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -32,6 +32,7 @@ #include <asm/fsl_i2c.h> #include <asm/mpc8xxx_spi.h> #include <asm/fsl_lbc.h> +#include <asm/fsl_dma.h> /* * Local Access Window @@ -367,51 +368,7 @@ typedef struct dma83xx { u32 imisr; /* 0x80 Inbound message interrupt status register */ u32 imimr; /* 0x84 Inbound message interrupt mask register */ u32 res4[0x1E]; /* 0x88-0x99 reserved */ - u32 dmamr0; /* 0x100 DMA 0 mode register */ - u32 dmasr0; /* 0x104 DMA 0 status register */ - u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */ - u32 res5; /* 0x10C reserved */ - u32 dmasar0; /* 0x110 DMA 0 source address register */ - u32 res6; /* 0x114 reserved */ - u32 dmadar0; /* 0x118 DMA 0 destination address register */ - u32 res7; /* 0x11C reserved */ - u32 dmabcr0; /* 0x120 DMA 0 byte count register */ - u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */ - u32 res8[0x16]; /* 0x128-0x179 reserved */ - u32 dmamr1; /* 0x180 DMA 1 mode register */ - u32 dmasr1; /* 0x184 DMA 1 status register */ - u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */ - u32 res9; /* 0x18C reserved */ - u32 dmasar1; /* 0x190 DMA 1 source address register */ - u32 res10; /* 0x194 reserved */ - u32 dmadar1; /* 0x198 DMA 1 destination address register */ - u32 res11; /* 0x19C reserved */ - u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */ - u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */ - u32 res12[0x16]; /* 0x1A8-0x199 reserved */ - u32 dmamr2; /* 0x200 DMA 2 mode register */ - u32 dmasr2; /* 0x204 DMA 2 status register */ - u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */ - u32 res13; /* 0x20C reserved */ - u32 dmasar2; /* 0x210 DMA 2 source address register */ - u32 res14; /* 0x214 reserved */ - u32 dmadar2; /* 0x218 DMA 2 destination address register */ - u32 res15; /* 0x21C reserved */ - u32 dmabcr2; /* 0x220 DMA 2 byte count register */ - u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */ - u32 res16[0x16]; /* 0x228-0x279 reserved */ - u32 dmamr3; /* 0x280 DMA 3 mode register */ - u32 dmasr3; /* 0x284 DMA 3 status register */ - u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */ - u32 res17; /* 0x28C reserved */ - u32 dmasar3; /* 0x290 DMA 3 source address register */ - u32 res18; /* 0x294 reserved */ - u32 dmadar3; /* 0x298 DMA 3 destination address register */ - u32 res19; /* 0x29C reserved */ - u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */ - u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */ - u32 dmagsr; /* 0x2A8 DMA general status register */ - u32 res20[0x15]; /* 0x2AC-0x2FF reserved */ + struct fsl_dma dma[4]; } dma83xx_t; /* @@ -895,6 +852,8 @@ typedef struct immap { } immap_t; #endif +#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000) +#define CONFIG_SYS_MPC83xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET) #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000) #define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) #define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index db2bdf0afa6..0efef052143 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -341,6 +341,15 @@ typedef struct ccsr_pcix { char res11[476]; } ccsr_pcix_t; +typedef struct ccsr_gpio { + uint gpdir; + uint gpodr; + uint gpdat; + uint gpier; + uint gpimr; + uint gpicr; +} ccsr_gpio_t; + #define PCIX_COMMAND 0x62 #define POWAR_EN 0x80000000 #define POWAR_IO_READ 0x00080000 @@ -1648,6 +1657,8 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) #define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000) +#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) #define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000) #define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) #define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index e7db1c6abf5..65546adbcad 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1021,7 +1021,7 @@ struct cpu_type { struct cpu_type *identify_cpu(u32 ver); -#if defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #define CPU_TYPE_ENTRY(n, v) \ { .name = #n, .soc_ver = SVR_##v, } #else diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 1fea6c36a67..50b3a03a012 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -88,6 +88,7 @@ # define _IO_BASE 0 #endif +#define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 #ifdef CONFIG_DRIVER_DM9000 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 2aba689664f..6f1b1a4c83c 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -404,7 +404,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* controller 3, direct to uli, tgtid 3, Base address 8000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull #else #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 @@ -423,7 +423,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* controller 2, Slot 2, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 @@ -442,7 +442,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull #else #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index d8042fb764a..035874b3129 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -335,7 +335,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL #else #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index a39ff26a7a2..fddcce5e4fa 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -46,6 +46,7 @@ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -437,7 +438,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); /* controller 3, Slot 1, tgtid 3, Base address b000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull #else #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 @@ -456,7 +457,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); /* controller 2, direct to uli, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 @@ -475,7 +476,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); /* controller 1, Slot 2, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull #else #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 3f943aa437b..4b9bcca79bc 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -96,6 +96,7 @@ #undef CONFIG_DDR_SPD #define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_FSL_DMA /* use DMA to init DDR ECC */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 43c2873e370..1db20bcceb5 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -98,6 +98,7 @@ #undef CONFIG_DDR_SPD #define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_FSL_DMA /* use DMA to init DDR ECC */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h new file mode 100644 index 00000000000..2553293306a --- /dev/null +++ b/include/configs/XPEDITE5170.h @@ -0,0 +1,756 @@ +/* + * Copyright 2009 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * xpedite5170 board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_MPC86xx 1 /* MPC86xx */ +#define CONFIG_MPC8641 1 /* MPC8641 specific */ +#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */ +#define CONFIG_SYS_BOARD_NAME "XPedite5170" +#define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ +#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ +#define CONFIG_ALTIVEC 1 + +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +/* + * DDR config + */ +#define CONFIG_FSL_DDR2 +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ +#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ +#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ + +/* + * virtual address to be used for temporary mappings. There + * should be 128k free at this VA. + */ +#define CONFIG_SYS_SCRATCH_VA 0xe0000000 + +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(unsigned long dummy); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */ + +/* + * L2CR setup + */ +#define CONFIG_SYS_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2CR_L2E) + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) + +/* + * Diagnostics + */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x20000000 + +/* + * Memory map + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable + * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable + * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable + * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable + * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable + * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable + * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable + * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable + * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable + */ + +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_2 | LCRR_EADC_3) + +/* + * NAND flash configuration + */ +#define CONFIG_SYS_NAND_BASE 0xef800000 +#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2} +#define CONFIG_SYS_MAX_NAND_DEVICE 2 +#define CONFIG_NAND_ACTL +#define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */ +#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */ +#define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */ +#define CONFIG_SYS_NAND_ACTL_DELAY 25 +#define CONFIG_SYS_NAND_QUIET_TEST +#define CONFIG_JFFS2_NAND + +/* + * NOR flash configuration + */ +#define CONFIG_SYS_FLASH_BASE 0xf8000000 +#define CONFIG_SYS_FLASH_BASE2 0xf0000000 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \ + {0xf7f00000, 0xc0000} } +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ + +/* + * Chip select configuration + */ +/* NOR Flash 0 on CS0 */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ + BR_PS_16 |\ + BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\ + OR_GPCM_CSNT |\ + OR_GPCM_XACS |\ + OR_GPCM_ACS_DIV2 |\ + OR_GPCM_SCY_8 |\ + OR_GPCM_TRLX |\ + OR_GPCM_EHTR |\ + OR_GPCM_EAD) + +/* NOR Flash 1 on CS1 */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\ + BR_PS_16 |\ + BR_V) +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM + +/* NAND flash on CS2 */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\ + BR_PS_8 |\ + BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\ + OR_GPCM_BCTLD |\ + OR_GPCM_CSNT |\ + OR_GPCM_ACS_DIV4 |\ + OR_GPCM_SCY_4 |\ + OR_GPCM_TRLX |\ + OR_GPCM_EHTR) + +/* Optional NAND flash on CS3 */ +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\ + BR_PS_8 |\ + BR_V) +#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM + +/* + * Use L1 as initial stack + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 +#define CONFIG_SYS_INIT_RAM_END 0x00004000 + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} +#define CONFIG_BAUDRATE 115200 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SYS_I2C_SPEED 100000 /* M41T00 only supports 100 KHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE + +/* PEX8518 slave I2C interface */ +#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 + +/* I2C DS1631 temperature sensor */ +#define CONFIG_SYS_I2C_DS1621_ADDR 0x48 +#define CONFIG_DTT_DS1621 +#define CONFIG_DTT_SENSORS { 0 } + +/* I2C EEPROM - AT24C128B */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 + +/* GPIO/EEPROM/SRAM */ +#define CONFIG_DS4510 +#define CONFIG_SYS_I2C_DS4510_ADDR 0x51 + +/* GPIO */ +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 +#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c +#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e +#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f +#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 + +/* + * PU = pulled high, PD = pulled low + * I = input, O = output, IO = input/output + */ +/* PCA9557 @ 0x18*/ +#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ +#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ +#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ +#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ +#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ +#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ + +/* PCA9557 @ 0x1c*/ +#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ +#define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */ +#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ +#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ +#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ +#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ +#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ +#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ + +/* PCA9557 @ 0x1e*/ +#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */ +#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */ + +/* PCA9557 @ 0x1f */ +#define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */ +#define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */ +#define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */ +#define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* PCIE1 - PEX8518 */ +#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ + +/* PCIE2 - VPX P1 */ +#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ + +/* + * Networking options + */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define CONFIG_HAS_ETH0 + +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_PHY_ADDR 2 +#define TSEC2_PHYIDX 0 +#define CONFIG_HAS_ETH1 + +/* + * BAT mappings + */ +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) +#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\ + BATU_BL_1M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU +#endif + +/* + * BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR + */ +#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U + +/* + * BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 1G PCI-Express 1 Memory + */ +#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\ + BATU_BL_1G |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U + +/* + * BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M PCI-Express 2 Memory + */ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\ + BATU_BL_512M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U + +/* + * BAT3 1M Cache-inhibited, guarded + * 0xe000_0000 1M CCSR + */ +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\ + BATU_BL_1M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U + +/* + * BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 + */ +#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\ + BATU_BL_32M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U + +/* + * BAT5 128K Cacheable, non-guarded + * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory) + */ +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\ + BATL_PP_RW |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\ + BATU_BL_128K |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L +#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U + +/* + * BAT6 256M Cache-inhibited, guarded + * 0xf000_0000 256M FLASH + */ +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\ + BATU_BL_256M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\ + BATL_PP_RW |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U + +/* Map the last 1M of flash where we're running from reset */ +#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE |\ + BATU_BL_1M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ + BATL_PP_RW |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY + +/* + * BAT7 64M Cache-inhibited, guarded + * 0xe800_0000 64K NAND FLASH + * 0xe804_0000 128K DUART Registers + */ +#define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\ + BATU_BL_512K |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U + +/* + * Command configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DS4510 +#define CONFIG_CMD_DS4510_INFO +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ +#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ +#define CONFIG_PANIC_HANG /* do not reset board on panic */ +#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ + +/* + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ +#define CONFIG_ENV_SIZE 0x8000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + +/* + * Flash memory map: + * fffc0000 - ffffffff Pri FDT (256KB) + * fff80000 - fffbffff Pri U-Boot Environment (256 KB) + * fff00000 - fff7ffff Pri U-Boot (512 KB) + * fef00000 - ffefffff Pri OS image (16MB) + * f8000000 - feefffff Pri OS Use/Filesystem (111MB) + * + * f7fc0000 - f7ffffff Sec FDT (256KB) + * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB) + * f7f00000 - f7f7ffff Sec U-Boot (512 KB) + * f6f00000 - f7efffff Sec OS image (16MB) + * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) + */ +#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff00000) +#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f00000) +#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfffc0000) +#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7fc0000) +#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000) +#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000) + +#define CONFIG_PROG_UBOOT1 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_UBOOT2 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_BOOT_OS_NET \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "if test -n $fdtaddr; then " \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "bootm $osaddr - $fdtaddr; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi; " \ + "else; " \ + "bootm $osaddr; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS1 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS2 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT1 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT2 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=yes\0" \ + "download_cmd=tftp\0" \ + "console_args=console=ttyS0,115200\0" \ + "root_args=root=/dev/nfs rw\0" \ + "misc_args=ip=on\0" \ + "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ + "bootfile=/home/user/file\0" \ + "osfile=/home/user/uImage-XPedite5170\0" \ + "fdtfile=/home/user/xpedite5170.dtb\0" \ + "ubootfile=/home/user/u-boot.bin\0" \ + "fdtaddr=c00000\0" \ + "osaddr=0x1000000\0" \ + "loadaddr=0x1000000\0" \ + "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ + "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ + "prog_os1="CONFIG_PROG_OS1"\0" \ + "prog_os2="CONFIG_PROG_OS2"\0" \ + "prog_fdt1="CONFIG_PROG_FDT1"\0" \ + "prog_fdt2="CONFIG_PROG_FDT2"\0" \ + "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ + "bootcmd_flash1=run set_bootargs; " \ + "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ + "bootcmd_flash2=run set_bootargs; " \ + "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ + "bootcmd=run bootcmd_flash1\0" +#endif /* __CONFIG_H */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 4f6b64011dc..83e05b343fe 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -131,6 +131,7 @@ #define CONFIG_SYS_NO_FLASH 1 /* Ethernet */ +#define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x30000000 #define DM9000_IO CONFIG_DM9000_BASE diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h index 06f2765a0d5..3db8171fb32 100644 --- a/include/configs/bf518f-ezbrd.h +++ b/include/configs/bf518f-ezbrd.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF518F_EZBRD_H__ #define __CONFIG_BF518F_EZBRD_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -88,8 +88,9 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SST #define CONFIG_SPI_FLASH_STMICRO @@ -143,6 +144,4 @@ */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - #endif diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h index afd9bb225a2..97853af2d05 100644 --- a/include/configs/bf526-ezbrd.h +++ b/include/configs/bf526-ezbrd.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF526_EZBRD_H__ #define __CONFIG_BF526_EZBRD_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -106,7 +106,7 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_SST @@ -185,6 +185,4 @@ void __led_toggle(led_id_t mask); */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - #endif diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index 0fe5fa53ff3..0d0235478b2 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF527_EZKIT_H__ #define __CONFIG_BF527_EZKIT_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -105,7 +105,7 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO @@ -167,6 +167,4 @@ */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - #endif diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index eb0889078b6..f896cb07a17 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF533_EZKIT_H__ #define __CONFIG_BF533_EZKIT_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -152,6 +152,4 @@ */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - #endif diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index d8e1ffc1d5f..c03561cef14 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF533_STAMP_H__ #define __CONFIG_BF533_STAMP_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -89,7 +89,7 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SPI_FLASH_SPANSION @@ -102,9 +102,9 @@ */ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_OFFSET 0x10000 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_OFFSET 0x4000 @@ -117,6 +117,21 @@ #else #define ENV_IS_EMBEDDED_CUSTOM #endif +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif /* @@ -241,6 +256,4 @@ void __led_toggle(led_id_t mask); */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - #endif diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h new file mode 100644 index 00000000000..23c2d33bc0b --- /dev/null +++ b/include/configs/bf537-minotaur.h @@ -0,0 +1,201 @@ +/* + * U-boot - Configuration file for CSP Minotaur board + * + * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch> + * Minotaur config, brushed up for official uClinux dist. + * Parallel flash support disabled, SPI flash boot command + * added ('run flashboot'). + * + * Flash image map: + * + * 0x00000000 u-boot bootstrap + * 0x00010000 environment + * 0x00020000 u-boot code + * 0x00030000 uImage.initramfs + * + */ + +#ifndef __CONFIG_BF537_MINOTAUR_H__ +#define __CONFIG_BF537_MINOTAUR_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf537-0.2 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 20 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_SIZE 32 +#define CONFIG_MEM_ADD_WDTH 9 + +#define CONFIG_EBIU_SDRRC_VAL 0x306 +#define CONFIG_EBIU_SDGCTL_VAL 0x91114d + +#define CONFIG_EBIU_AMGCTL_VAL 0xFF +#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_SYS_MALLOC_LEN (128 << 10) + + +/* + * Network Settings + */ +#ifndef __ADSPBF534__ +#define CONFIG_BFIN_MAC +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NET_MULTI 1 +#endif +#ifdef CONFIG_BFIN_MAC +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME bf537-minotaur +#endif + +#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_ROOTPATH /romfs +/* Use a fixed MAC address for booting up. Firstboot linux + * must fetch a valid MAC from the production server. */ +#define CONFIG_ETHADDR 02:80:ad:20:31:42 + + +/* + * Flash Settings + */ +/* We don't have a parallel flash chip there */ +#define CONFIG_SYS_NO_FLASH + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define ENV_IS_EMBEDDED_CUSTOM + + +/* + * I2C settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_MISC_INIT_R + +#define CONFIG_BAUDRATE 57600 +#define CONFIG_UART_CONSOLE 0 + +#define CONFIG_PANIC_HANG 1 +#define CONFIG_RTC_BFIN 1 +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_LOADS_ECHO 1 + +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) +# define CONFIG_BOOTDELAY -1 +#else +# define CONFIG_BOOTDELAY 5 +#endif + +#include <config_cmd_default.h> + +#ifdef CONFIG_BFIN_MAC +# define CONFIG_CMD_DHCP +# define CONFIG_CMD_PING +#else +# undef CONFIG_CMD_NET +#endif + +#define CONFIG_CMD_BOOTLDR +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#undef CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_SF + +#define CONFIG_BOOTCOMMAND "run ramboot" +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" +#define CONFIG_SYS_PROMPT "minotaur> " + +#define BOOT_ENV_SETTINGS \ + "update=tftpboot $(loadaddr) u-boot.ldr;" \ + "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \ + "sf erase 0 0x30000;" \ + "sf write $(loadaddr) 0 $(filesize)" \ + "flashboot=sf read 0x1000000 0x30000 0x320000;" \ + "bootm 0x1000000\0" +#ifdef CONFIG_BFIN_MAC +# define NETWORK_ENV_SETTINGS \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot $(loadaddr) linux;" \ + "run ramargs;run addip;bootelf\0" \ + "nfsboot=tftpboot $(loadaddr) linux;" \ + "run nfsargs;run addip;bootelf\0" +#else +# define NETWORK_ENV_SETTINGS +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \ + NETWORK_ENV_SETTINGS \ + "ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \ + BOOT_ENV_SETTINGS + +#endif diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h new file mode 100644 index 00000000000..0f908efff20 --- /dev/null +++ b/include/configs/bf537-pnav.h @@ -0,0 +1,185 @@ +/* + * U-boot - Configuration file for BF537 PNAV board + */ + +#ifndef __CONFIG_BF537_PNAV_H__ +#define __CONFIG_BF537_PNAV_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf537-0.2 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 24576000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 20 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 4 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 10 +#define CONFIG_MEM_SIZE 64 + +#define CONFIG_EBIU_SDRRC_VAL 0x3b7 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL 0xFF +#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Network Settings + */ +#ifndef __ADSPBF534__ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_BFIN_MAC +#define CONFIG_RMII +#define CONFIG_NET_MULTI 1 +#endif +#define CONFIG_HOSTNAME bf537-pnav +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:24:21:18 */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 71 + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + + +/* + * Env Storage Settings + */ +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) +#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x4000 +#else +#define ENV_IS_EMBEDDED +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR 0x20004000 +#define CONFIG_ENV_OFFSET 0x4000 +#endif +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_SECT_SIZE 0x2000 +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif + + +/* + * NAND Settings + */ +#define CONFIG_NAND_PLAT + +#define CONFIG_SYS_NAND_BASE 0x20100000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) +#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) +#define BFIN_NAND_READY PF12 +#define BFIN_NAND_WRITE(addr, cmd) \ + do { \ + bfin_write8(addr, cmd); \ + SSYNC(); \ + } while (0) + +#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) +#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) +#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTHIO() & BFIN_NAND_READY) +#define NAND_PLAT_INIT() \ + do { \ + bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \ + bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \ + bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \ + } while (0) + + +/* + * I2C settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R +#define CONFIG_RTC_BFIN +#define CONFIG_UART_CONSOLE 0 + +/* JFFS Partition offset set */ +#define CONFIG_SYS_JFFS2_FIRST_BANK 0 +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15 + +#define CONFIG_BOOTCOMMAND "run nandboot" +#define CONFIG_BOOTARGS_ROOT "/dev/mtdblock1 rw rootfstype=yaffs" + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h new file mode 100644 index 00000000000..727b7e70e64 --- /dev/null +++ b/include/configs/bf537-srv1.h @@ -0,0 +1,201 @@ +/* + * U-boot - Configuration file for CSP Minotaur board + * + * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch> + * Minotaur config, brushed up for official uClinux dist. + * Parallel flash support disabled, SPI flash boot command + * added ('run flashboot'). + * + * Flash image map: + * + * 0x00000000 u-boot bootstrap + * 0x00010000 environment + * 0x00020000 u-boot code + * 0x00030000 uImage.initramfs + * + */ + +#ifndef __CONFIG_BF537_SRV1_H__ +#define __CONFIG_BF537_SRV1_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf537-0.2 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 22118400 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 20 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_SIZE 32 +#define CONFIG_MEM_ADD_WDTH 9 + +#define CONFIG_EBIU_SDRRC_VAL 0x2ac +#define CONFIG_EBIU_SDGCTL_VAL 0x91110d + +#define CONFIG_EBIU_AMGCTL_VAL 0xFF +#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_SYS_MALLOC_LEN (384 << 10) + + +/* + * Network Settings + */ +#ifndef __ADSPBF534__ +#define CONFIG_BFIN_MAC +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NET_MULTI 1 +#endif +#ifdef CONFIG_BFIN_MAC +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME bf537-srv1 +#endif + +#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_ROOTPATH /romfs +/* Use a fixed MAC address for booting up. Firstboot linux + * must fetch a valid MAC from the production server. */ +#define CONFIG_ETHADDR 02:80:ad:20:31:42 + + +/* + * Flash Settings + */ +/* We don't have a parallel flash chip there */ +#define CONFIG_SYS_NO_FLASH + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define ENV_IS_EMBEDDED_CUSTOM + + +/* + * I2C settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_MISC_INIT_R + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_UART_CONSOLE 0 + +#define CONFIG_PANIC_HANG 1 +#define CONFIG_RTC_BFIN 1 +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_LOADS_ECHO 1 + +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) +# define CONFIG_BOOTDELAY -1 +#else +# define CONFIG_BOOTDELAY 5 +#endif + +#include <config_cmd_default.h> + +#ifdef CONFIG_BFIN_MAC +# define CONFIG_CMD_DHCP +# define CONFIG_CMD_PING +#else +# undef CONFIG_CMD_NET +#endif + +#define CONFIG_CMD_BOOTLDR +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#undef CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_SF + +#define CONFIG_BOOTCOMMAND "run flashboot" +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" +#define CONFIG_SYS_PROMPT "srv1> " + +#define BOOT_ENV_SETTINGS \ + "update=tftpboot $(loadaddr) u-boot.ldr;" \ + "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \ + "sf erase 0 0x30000;" \ + "sf write $(loadaddr) 0 $(filesize)" \ + "flashboot=sf read 0x1000000 0x30000 0x320000;" \ + "bootm 0x1000000\0" +#ifdef CONFIG_BFIN_MAC +# define NETWORK_ENV_SETTINGS \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot $(loadaddr) linux;" \ + "run ramargs;run addip;bootelf\0" \ + "nfsboot=tftpboot $(loadaddr) linux;" \ + "run nfsargs;run addip;bootelf\0" +#else +# define NETWORK_ENV_SETTINGS +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \ + NETWORK_ENV_SETTINGS \ + "ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \ + BOOT_ENV_SETTINGS + +#endif diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 3e5862d1381..0a86e83fbf4 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF537_STAMP_H__ #define __CONFIG_BF537_STAMP_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -87,7 +87,7 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SPI_FLASH_SPANSION @@ -100,9 +100,9 @@ */ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_OFFSET 0x10000 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_OFFSET 0x4000 @@ -115,6 +115,21 @@ #else #define ENV_IS_EMBEDDED_CUSTOM #endif +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif /* @@ -257,6 +272,4 @@ */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - #endif diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index a7fb92e62a9..535687fdbf0 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF538F_EZKIT_H__ #define __CONFIG_BF538F_EZKIT_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -83,7 +83,7 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SPI_FLASH_SPANSION @@ -111,6 +111,21 @@ #else #define ENV_IS_EMBEDDED_CUSTOM #endif +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif /* @@ -134,6 +149,4 @@ */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - #endif diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index ae9fb367457..dbcd2afb0d2 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF548_EZKIT_H__ #define __CONFIG_BF548_EZKIT_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -61,7 +61,7 @@ #define CONFIG_EBIU_FCTL_VAL (BCLK_4) #define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH) -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) #define CONFIG_SYS_MALLOC_LEN (768 * 1024) @@ -93,7 +93,7 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO @@ -206,6 +206,4 @@ */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - #endif diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index ef2019f39dd..4779a97a455 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF561_EZKIT_H__ #define __CONFIG_BF561_EZKIT_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -88,6 +88,23 @@ #else #define ENV_IS_EMBEDDED_CUSTOM #endif +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + lib_generic/zlib.o (.text .text.*); \ + board/bf561-ezkit/bf561-ezkit.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif /* @@ -149,6 +166,4 @@ */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - -#endif /* __CONFIG_EZKIT561_H__ */ +#endif diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index e0be07b477e..4149a294714 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -71,6 +71,7 @@ # define CONFIG_CMD_STRINGS # if defined(__ADSPBF51x__) || defined(__ADSPBF52x__) || defined(__ADSPBF54x__) # define CONFIG_CMD_OTP +# define CONFIG_CMD_SPIBOOTLDR # endif #endif @@ -102,14 +103,19 @@ #else # define CONFIG_BOOTDELAY 5 #endif -#define CONFIG_BOOTCOMMAND "run ramboot" +#ifndef CONFIG_BOOTCOMMAND +# define CONFIG_BOOTCOMMAND "run ramboot" +#endif #ifdef CONFIG_VIDEO # define CONFIG_BOOTARGS_VIDEO "console=tty0 " #else # define CONFIG_BOOTARGS_VIDEO "" #endif +#ifndef CONFIG_BOOTARGS_ROOT +# define CONFIG_BOOTARGS_ROOT "/dev/mtdblock0 rw" +#endif #define CONFIG_BOOTARGS \ - "root=/dev/mtdblock0 rw " \ + "root=" CONFIG_BOOTARGS_ROOT " " \ "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \ "earlyprintk=" \ "serial," \ @@ -117,7 +123,17 @@ MK_STR(CONFIG_BAUDRATE) " " \ CONFIG_BOOTARGS_VIDEO \ "console=ttyBF0," MK_STR(CONFIG_BAUDRATE) - +#if defined(CONFIG_CMD_NAND) +# define NAND_ENV_SETTINGS \ + "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \ + "nandboot=" \ + "nand read $(loadaddr) 0x20000 0x100000;" \ + "run nandargs;" \ + "bootm" \ + "\0" +#else +# define NAND_ENV_SETTINGS +#endif #if defined(CONFIG_CMD_NET) # if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) # define UBOOT_ENV_FILE "u-boot.bin" @@ -155,19 +171,23 @@ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \ "$(hostname):eth0:off" \ "\0" \ + \ + "ramfile=uImage\0" \ "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \ "ramboot=" \ - "tftp $(loadaddr) uImage;" \ + "tftp $(loadaddr) $(ramfile);" \ "run ramargs;" \ "run addip;" \ "bootm" \ "\0" \ + \ + "nfsfile=vmImage\0" \ "nfsargs=set bootargs " \ "root=/dev/nfs rw " \ "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \ "\0" \ "nfsboot=" \ - "tftp $(loadaddr) vmImage;" \ + "tftp $(loadaddr) $(nfsfile);" \ "run nfsargs;" \ "run addip;" \ "bootm" \ @@ -176,6 +196,7 @@ # define NETWORK_ENV_SETTINGS #endif #define CONFIG_EXTRA_ENV_SETTINGS \ + NAND_ENV_SETTINGS \ NETWORK_ENV_SETTINGS \ "flashboot=bootm 0x20100000\0" @@ -196,4 +217,9 @@ # define CONFIG_NET_RETRY_COUNT 20 #endif +/* + * Misc Settings + */ +#define CONFIG_LZMA + #endif diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h new file mode 100644 index 00000000000..1e4c716139a --- /dev/null +++ b/include/configs/blackstamp.h @@ -0,0 +1,273 @@ +/* + * U-boot - Configuration file for BlackStamp board + * Configuration by Ben Matthews for UR LLE using bf533-stamp.h + * as a template + * See http://blackfin.uclinux.org/gf/project/blackstamp/ + */ + +#ifndef __CONFIG_BLACKSTAMP_H__ +#define __CONFIG_BLACKSTAMP_H__ + +#include <asm/config-pre.h> + +/* + * Debugging: Set these options if you're having problems + */ +/* + * #define CONFIG_DEBUG_EARLY_SERIAL + * #define DEBUG + * #define CONFIG_DEBUG_DUMP + * #define CONFIG_DEBUG_DUMP_SYMS +*/ +#define CONFIG_PANIC_HANG 0 + +/* CPU Options + * Be sure to set the Silicon Revision Correctly + */ +#define CONFIG_BFIN_CPU bf532-0.5 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER + +/* + * Board settings + */ +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20300300 + +/* FLASH/ETHERNET uses the same address range + * Depending on what you have the CPLD doing + * this probably isn't needed + */ +#define SHARED_RESOURCES 1 + +/* Is I2C bit-banged? */ +#undef CONFIG_SOFT_I2 + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 16 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 3 + +/* + * Network settings + */ + +#ifdef CONFIG_DRIVER_SMC91111 +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME blackstamp +#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs +#define CONFIG_SYS_AUTOLOAD "no" + +/* To remove hardcoding and enable MAC storage in EEPROM */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ +#endif + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x40000 +#define ENV_IS_EMBEDDED_CUSTOM + +/* + * SDRAM settings & memory map + */ + +#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */ + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_SYS_MALLOC_LEN (384 << 10) + +/* + * Command settings + */ + +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE 1 +#define CONFIG_ENV_OVERWRITE 1 + +#include <config_cmd_default.h> + +#ifdef CONFIG_DRIVER_SMC91111 +# define CONFIG_CMD_DHCP +# define CONFIG_CMD_PING +#else +# undef CONFIG_CMD_NET +#endif + +#ifdef CONFIG_SOFT_I2C +# define CONFIG_CMD_I2C +#endif + +#define CONFIG_CMD_BOOTLDR +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_CPLBINFO +#define CONFIG_CMD_DATE +#define CONFIG_CMD_SF +#define CONFIG_CMD_ELF + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTCOMMAND "run ramboot" +#define CONFIG_BOOTARGS \ + "root=/dev/mtdblock0 rw " \ + "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \ + "earlyprintk=" \ + "serial," \ + "uart" MK_STR(CONFIG_UART_CONSOLE) "," \ + MK_STR(CONFIG_BAUDRATE) " " \ + "console=ttyBF0," MK_STR(CONFIG_BAUDRATE) + +#if defined(CONFIG_CMD_NET) +# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) +# define UBOOT_ENV_FILE "u-boot.bin" +# else +# define UBOOT_ENV_FILE "u-boot.ldr" +# endif +# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) +# ifdef CONFIG_SPI +# define UBOOT_ENV_UPDATE \ + "eeprom write $(loadaddr) 0x0 $(filesize)" +# else +# define UBOOT_ENV_UPDATE \ + "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \ + "sf erase 0 0x40000;" \ + "sf write $(loadaddr) 0 $(filesize)" +# endif +# else +# define UBOOT_ENV_UPDATE \ + "protect off 0x20000000 0x2003FFFF;" \ + "erase 0x20000000 0x2003FFFF;" \ + "cp.b $(loadaddr) 0x20000000 $(filesize)" +# endif +# define NETWORK_ENV_SETTINGS \ + "ubootfile=" UBOOT_ENV_FILE "\0" \ + "update=" \ + "tftp $(loadaddr) $(ubootfile);" \ + UBOOT_ENV_UPDATE \ + "\0" \ + "addip=set bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \ + "$(hostname):eth0:off" \ + "\0" \ + "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \ + "ramboot=" \ + "tftp $(loadaddr) uImage;" \ + "run ramargs;" \ + "run addip;" \ + "bootm" \ + "\0" \ + "nfsargs=set bootargs " \ + "root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \ + "\0" \ + "nfsboot=" \ + "tftp $(loadaddr) vmImage;" \ + "run nfsargs;" \ + "run addip;" \ + "bootm" \ + "\0" +#else +# define NETWORK_ENV_SETTINGS +#endif + +/* + * Console settings + */ +#define CONFIG_BAUDRATE 57600 +#define CONFIG_LOADS_ECHO 1 +#define CONFIG_UART_CONSOLE 0 + +/* + * I2C settings + * By default PF2 is used as SDA and PF3 as SCL on the Stamp board + * Located on the expansion connector on pins 86/85 + * Note these pins are arbitrarily chosen because we aren't using + * them yet. You can (and probably should) change these values! + */ +#ifdef CONFIG_SOFT_I2C + +#define PF_SCL PF9 +#define PF_SDA PF8 + +#define I2C_INIT do { *pFIO_DIR |= PF_SCL; SSYNC(); } while (0) +#define I2C_ACTIVE do { *pFIO_DIR |= PF_SDA; *pFIO_INEN &= ~PF_SDA; SSYNC(); } while (0) +#define I2C_TRISTATE do { *pFIO_DIR &= ~PF_SDA; *pFIO_INEN |= PF_SDA; SSYNC(); } while (0) +#define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0) +#define I2C_SDA(bit) \ + do { \ + if (bit) \ + *pFIO_FLAG_S = PF_SDA; \ + else \ + *pFIO_FLAG_C = PF_SDA; \ + SSYNC(); \ + } while (0) +#define I2C_SCL(bit) \ + do { \ + if (bit) \ + *pFIO_FLAG_S = PF_SCL; \ + else \ + *pFIO_FLAG_C = PF_SCL; \ + SSYNC(); \ + } while (0) +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0xFE +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_RTC_BFIN 1 + +/* + * Serial Flash Infomation + */ +#define CONFIG_BFIN_SPI +/* For the M25P64 SCK Should be Kept < 20Mhz */ +#define CONFIG_ENV_SPI_MAX_HZ 20000000 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + +/* + * FLASH organization and environment definitions + */ + +#define CONFIG_EBIU_AMGCTL_VAL 0xFF +#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3 +#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983 +#define CONFIG_EBIU_SDRRC_VAL 0x268 +#define CONFIG_EBIU_SDGCTL_VAL 0x911109 + +/* Even though Rev C boards have Parallel Flash + * We aren't supporting it. Newer versions of the + * hardware don't support Parallel Flash at all. + */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_FLASH + +#endif diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h new file mode 100644 index 00000000000..79d06fba524 --- /dev/null +++ b/include/configs/cm-bf527.h @@ -0,0 +1,135 @@ +/* + * U-boot - Configuration file for CM-BF527 board + */ + +#ifndef __CONFIG_CM_BF527_H__ +#define __CONFIG_CM_BF527_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf527-0.0 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 21 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 4 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +#define CONFIG_EBIU_SDRRC_VAL 0x3f8 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * NAND Settings + * (can't be used sametime as ethernet) + */ +/* #define CONFIG_BFIN_NFC */ +#ifdef CONFIG_BFIN_NFC +#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 +#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_CMD_NAND +#endif + + +/* + * Network Settings + */ +#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \ + !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC) +#define ADI_CMDS_NETWORK 1 +#define CONFIG_BFIN_MAC +#define CONFIG_RMII +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NET_MULTI 1 +#endif +#define CONFIG_HOSTNAME cm-bf527 +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 64 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR 0x20008000 +#define CONFIG_ENV_OFFSET 0x8000 +#define CONFIG_ENV_SIZE 0x8000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define ENV_IS_EMBEDDED_CUSTOM + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R +#define CONFIG_RTC_BFIN +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h new file mode 100644 index 00000000000..ea548e99927 --- /dev/null +++ b/include/configs/cm-bf533.h @@ -0,0 +1,102 @@ +/* + * U-boot - Configuration file for CM-BF533 board + */ + +#ifndef __CONFIG_CM_BF533_H__ +#define __CONFIG_CM_BF533_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf533-0.3 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 22 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +#define CONFIG_EBIU_SDRRC_VAL ((((CONFIG_SCLK_HZ / 1000) * 64) / 8192) - (7 + 2)) +#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3) + +#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Network Settings + */ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20200300 +#define CONFIG_HOSTNAME cm-bf533 +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 16 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x10000 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h new file mode 100644 index 00000000000..021b631a90b --- /dev/null +++ b/include/configs/cm-bf537e.h @@ -0,0 +1,137 @@ +/* + * U-boot - Configuration file for CM-BF537E board + */ + +#ifndef __CONFIG_CM_BF537E_H__ +#define __CONFIG_CM_BF537E_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf537-0.2 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 21 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 4 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +#define CONFIG_EBIU_SDRRC_VAL 0x3f8 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Network Settings + */ +#ifndef __ADSPBF534__ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_BFIN_MAC +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NET_MULTI 1 +#endif +#define CONFIG_HOSTNAME cm-bf537e +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 32 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) +#define ENV_IS_EMBEDDED +#else +#define ENV_IS_EMBEDDED_CUSTOM +#endif +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R +#define CONFIG_RTC_BFIN +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h new file mode 100644 index 00000000000..93c2239ea86 --- /dev/null +++ b/include/configs/cm-bf548.h @@ -0,0 +1,139 @@ +/* + * U-boot - Configuration file for cm-bf548 board + */ + +#ifndef __CONFIG_CM_BF548_H__ +#define __CONFIG_CM_BF548_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf548-0.0 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 21 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 4 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 10 +#define CONFIG_MEM_SIZE 64 + +#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE +#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222 +#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021 + +/* Default bank mapping: + * Async Bank 0 - 32MB Burst Flash + * Async Bank 1 - Ethernet + * Async Bank 2 - Nothing + * Async Bank 3 - Nothing + */ +#define CONFIG_EBIU_AMGCTL_VAL 0xFF +#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 +#define CONFIG_EBIU_FCTL_VAL (BCLK_4) +#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH) + +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) +#define CONFIG_SYS_MALLOC_LEN (640 * 1024) + + +/* + * Network Settings + */ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_DRIVER_SMC911X 1 +#define CONFIG_DRIVER_SMC911X_BASE 0x24000000 +#define CONFIG_DRIVER_SMC911X_16_BIT +#define CONFIG_HOSTNAME cm-bf548 +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:24:31:91 */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 259 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR 0x20008000 +#define CONFIG_ENV_OFFSET 0x8000 +#define CONFIG_ENV_SIZE 0x8000 +#define ENV_IS_EMBEDDED_CUSTOM + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_RTC_BFIN +#define CONFIG_UART_CONSOLE 1 + +#ifndef __ADSPBF542__ +/* Don't waste time transferring a logo over the UART */ +# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) +# define CONFIG_VIDEO +# endif +# define CONFIG_DEB_DMA_URGENT +#endif + +/* Define if want to do post memory test */ +#undef CONFIG_POST +#ifdef CONFIG_POST +#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */ +#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ +#endif + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h new file mode 100644 index 00000000000..53a25807aef --- /dev/null +++ b/include/configs/cm-bf561.h @@ -0,0 +1,102 @@ +/* + * U-boot - Configuration file for CM-BF561 board + */ + +#ifndef __CONFIG_CM_BF561_H__ +#define __CONFIG_CM_BF561_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf561-0.3 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 22 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 64 + +#define CONFIG_EBIU_SDRRC_VAL ((((CONFIG_SCLK_HZ / 1000) * 64) / 4096) - (7 + 2)) +#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3) + +#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | B3_PEN | B2_PEN | B1_PEN | B0_PEN | AMBEN_ALL | AMCKEN) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Network Settings + */ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x28000300 +#define CONFIG_HOSTNAME cm-bf561 +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:cf */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 67 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x10000 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 6c5d0650885..96b6afc3517 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -109,6 +109,7 @@ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI /*=====================*/ /* Flash & Environment */ /*=====================*/ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 6612cb3cbb1..9cb9838b5ad 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -77,6 +77,7 @@ #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_NET_MULTI /*=====================*/ /* Flash & Environment */ /*=====================*/ diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 6c1dc117dea..a47620fca8d 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -74,6 +74,7 @@ #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_NET_MULTI /* Flash & Environment */ #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 893729c6f24..82901b39332 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -109,6 +109,7 @@ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI /*=====================*/ /* Flash & Environment */ /*=====================*/ diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h new file mode 100644 index 00000000000..066859f8ee8 --- /dev/null +++ b/include/configs/ibf-dsp561.h @@ -0,0 +1,145 @@ +/* + * U-boot - Configuration file for IBF-DSP561 board + */ + +#ifndef __CONFIG_IBF_DSP561__H__ +#define __CONFIG_IBF_DSP561__H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf561-0.5 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 24 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 64 + +#define CONFIG_EBIU_SDRRC_VAL 0x377 +#define CONFIG_EBIU_SDGCTL_VAL 0x91998d +#define CONFIG_EBIU_SDBCTL_VAL 0x15 + +#define CONFIG_EBIU_AMGCTL_VAL 0x3F +#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Flash Settings + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */ +/* The BF561-EZKIT uses a top boot flash */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR 0x20004000 +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) +#define ENV_IS_EMBEDDED +#else +#define ENV_IS_EMBEDDED_CUSTOM +#endif +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + lib_generic/zlib.o (.text .text.*); \ + board/ibf-dsp561/ibf-dsp561.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif + + +/* + * I2C Settings + */ +#define CONFIG_SOFT_I2C 1 +#define PF_SCL 0x1/*PF0*/ +#define PF_SDA 0x2/*PF1*/ + +#ifdef CONFIG_SOFT_I2C +#define I2C_INIT do { *pFIO0_DIR |= PF_SCL; SSYNC(); } while (0) +#define I2C_ACTIVE do { *pFIO0_DIR |= PF_SDA; *pFIO0_INEN &= ~PF_SDA; SSYNC(); } while (0) +#define I2C_TRISTATE do { *pFIO0_DIR &= ~PF_SDA; *pFIO0_INEN |= PF_SDA; SSYNC(); } while (0) +#define I2C_READ ((*pFIO0_FLAG_D & PF_SDA) != 0) +#define I2C_SDA(bit) \ + do { \ + if (bit) \ + *pFIO0_FLAG_S = PF_SDA; \ + else \ + *pFIO0_FLAG_C = PF_SDA; \ + SSYNC(); \ + } while (0) +#define I2C_SCL(bit) \ + do { \ + if (bit) \ + *pFIO0_FLAG_S = PF_SCL; \ + else \ + *pFIO0_FLAG_C = PF_SCL; \ + SSYNC(); \ + } while (0) +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 +#endif + + +/* + * Misc Settings + */ +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index 893c3d3c2f7..555671464bb 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -255,6 +255,7 @@ #define CONFIG_SYS_CS5U_VAL 0x00008400 #define CONFIG_SYS_CS5L_VAL 0x00000D03 +#define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x16000000 #define DM9000_IO CONFIG_DM9000_BASE diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h new file mode 100644 index 00000000000..9794e1b9042 --- /dev/null +++ b/include/configs/tcm-bf537.h @@ -0,0 +1,139 @@ +/* + * U-boot - Configuration file for TCM-BF537 board + */ + +#ifndef __CONFIG_TCM_BF537_H__ +#define __CONFIG_TCM_BF537_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf537-0.2 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 21 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 4 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +#define CONFIG_EBIU_SDRRC_VAL 0x3f8 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Network Settings + */ +/* TCM-BF537E has no PHY on it, but EXT-BF5xx-USB/Ethernet board has */ +#ifndef __ADSPBF534__ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_BFIN_MAC +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NET_MULTI 1 +#endif +#define CONFIG_HOSTNAME tcm-bf537 +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 67 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) +#define ENV_IS_EMBEDDED +#else +#define ENV_IS_EMBEDDED_CUSTOM +#endif +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R +#define CONFIG_RTC_BFIN +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + + +#endif diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index 49045fd069d..bfa7157214f 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -278,6 +278,7 @@ #define CONFIG_SYS_MCIO0_VAL 0x00008407 #define CONFIG_SYS_MCIO1_VAL 0x0000c108 +#define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x08000000 #define DM9000_IO CONFIG_DM9000_BASE diff --git a/include/mpc83xx.h b/include/mpc83xx.h index c5bd6cb16ab..fd742c7809d 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -1041,22 +1041,6 @@ #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ #define ECC_ERROR_MAN_SBEC_SHIFT 0 -/* DMAMR - DMA Mode Register - */ -#define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ -#define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ -#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ -#define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ - -/* DMASR - DMA Status Register - */ -#define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ -#define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ - /* CONFIG_ADDRESS - PCI Config Address Register */ #define PCI_CONFIG_ADDRESS_EN 0x80000000 diff --git a/include/netdev.h b/include/netdev.h index 63cf730a303..aed5c4cce31 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -44,6 +44,7 @@ int cpu_eth_init(bd_t *bis); int au1x00_enet_initialize(bd_t*); int bfin_EMAC_initialize(bd_t *bis); int dc21x4x_initialize(bd_t *bis); +int davinci_emac_initialize(void); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); int eepro100_initialize(bd_t *bis); @@ -52,6 +53,7 @@ int fec_initialize (bd_t *bis); int greth_initialize(bd_t *bis); void gt6426x_eth_initialize(bd_t *bis); int inca_switch_initialize(bd_t *bis); +int kirkwood_egiga_initialize(bd_t *bis); int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); int mcdmafec_initialize(bd_t *bis); int mcffec_initialize(bd_t *bis); @@ -73,6 +75,7 @@ int tsi108_eth_initialize(bd_t *bis); int uec_initialize(int index); int uli526x_initialize(bd_t *bis); int sh_eth_initialize(bd_t *bis); +int dm9000_initialize(bd_t *bis); /* Boards with PCI network controllers can call this from their board_eth_init() * function to initialize whatever's on board. @@ -116,4 +119,51 @@ static inline int pci_eth_init(bd_t *bis) return num; } +/* + * Boards with mv88e61xx switch can use this by defining + * CONFIG_MV88E61XX_SWITCH in respective board configheader file + * the stuct and enums here are used to specify switch configuration params + */ +#if defined(CONFIG_MV88E61XX_SWITCH) +enum mv88e61xx_cfg_vlan { + MV88E61XX_VLANCFG_DEFAULT, + MV88E61XX_VLANCFG_ROUTER +}; + +enum mv88e61xx_cfg_mdip { + MV88E61XX_MDIP_NOCHANGE, + MV88E61XX_MDIP_REVERSE +}; + +enum mv88e61xx_cfg_ledinit { + MV88E61XX_LED_INIT_DIS, + MV88E61XX_LED_INIT_EN +}; + +enum mv88e61xx_cfg_rgmiid { + MV88E61XX_RGMII_DELAY_DIS, + MV88E61XX_RGMII_DELAY_EN +}; + +enum mv88e61xx_cfg_prtstt { + MV88E61XX_PORTSTT_DISABLED, + MV88E61XX_PORTSTT_BLOCKING, + MV88E61XX_PORTSTT_LEARNING, + MV88E61XX_PORTSTT_FORWARDING +}; + +struct mv88e61xx_config { + char *name; + enum mv88e61xx_cfg_vlan vlancfg; + enum mv88e61xx_cfg_rgmiid rgmii_delay; + enum mv88e61xx_cfg_prtstt portstate; + enum mv88e61xx_cfg_ledinit led_init; + enum mv88e61xx_cfg_mdip mdip; + u32 ports_enabled; + u8 cpuport; +}; + +int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); +#endif /* CONFIG_MV88E61XX_SWITCH */ + #endif /* _NETDEV_H_ */ diff --git a/include/serial.h b/include/serial.h index aca5221044f..5722337269b 100644 --- a/include/serial.h +++ b/include/serial.h @@ -24,7 +24,8 @@ extern struct serial_device * default_serial_console (void); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ - defined(CONFIG_MPC5xxx) + defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) || \ + defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CONFIG_SYS_NS16550_SERIAL) diff --git a/include/tsec.h b/include/tsec.h index 9184256b577..0ac30340606 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -152,6 +152,8 @@ #define MIIM_EXT_PAGE_ACCESS 0x1f /* Broadcom BCM54xx -- taken from linux sungem_phy */ +#define MIIM_BCM54xx_AUXCNTL 0x18 +#define MIIM_BCM54xx_AUXCNTL_ENCODE(val) ((val & 0x7) << 12)|(val & 0x7) #define MIIM_BCM54xx_AUXSTATUS 0x19 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8 diff --git a/lib_blackfin/.gitignore b/lib_blackfin/.gitignore new file mode 100644 index 00000000000..09f1be04eb5 --- /dev/null +++ b/lib_blackfin/.gitignore @@ -0,0 +1 @@ +u-boot.lds diff --git a/lib_blackfin/Makefile b/lib_blackfin/Makefile index 46ef7f33169..e32ecc92d35 100644 --- a/lib_blackfin/Makefile +++ b/lib_blackfin/Makefile @@ -47,9 +47,12 @@ COBJS-y += string.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) -$(LIB): $(obj).depend $(OBJS) +$(LIB): $(obj).depend $(OBJS) $(obj)u-boot.lds $(AR) $(ARFLAGS) $@ $(OBJS) +$(obj)u-boot.lds: u-boot.lds.S + $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ + ######################################################################### # defines $(obj).depend target diff --git a/board/bf527-ezkit/u-boot.lds.S b/lib_blackfin/u-boot.lds.S index 3e8be358da6..4755153fcf9 100644 --- a/board/bf527-ezkit/u-boot.lds.S +++ b/lib_blackfin/u-boot.lds.S @@ -31,6 +31,10 @@ #undef ENTRY #undef bfin +#ifndef LDS_BOARD_TEXT +# define LDS_BOARD_TEXT +#endif + /* If we don't actually load anything into L1 data, this will avoid * a syntax error. If we do actually load something into L1 data, * we'll get a linker memory load error (which is what we'd want). @@ -57,9 +61,13 @@ SECTIONS .text : { cpu/blackfin/start.o (.text .text.*) + + LDS_BOARD_TEXT + __initcode_start = .; cpu/blackfin/initcode.o (.text .text.*) __initcode_end = .; + *(.text .text.*) } >ram diff --git a/net/bootp.c b/net/bootp.c index 3dea70aab0b..77057c6c0a7 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -687,7 +687,7 @@ BootpRequest (void) * Calculate proper packet lengths taking into account the * variable size of the options field */ - pktlen = BOOTP_SIZE - sizeof(bp->bp_vend) + ext_len; + pktlen = ((int)(pkt-NetTxPacket)) + BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + ext_len; iplen = BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + ext_len; NetSetIP(iphdr, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC, iplen); NetSetTimeout(SELECT_TIMEOUT, BootpTimeout); @@ -860,7 +860,7 @@ static void DhcpSendRequestPkt(Bootp_t *bp_offer) NetCopyIP(&OfferedIP, &bp_offer->bp_yiaddr); extlen = DhcpExtended((u8 *)bp->bp_vend, DHCP_REQUEST, NetDHCPServerIP, OfferedIP); - pktlen = BOOTP_SIZE - sizeof(bp->bp_vend) + extlen; + pktlen = ((int)(pkt-NetTxPacket)) + BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + extlen; iplen = BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + extlen; NetSetIP(iphdr, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC, iplen); diff --git a/net/eth.c b/net/eth.c index 8940ebf1179..3d93966918e 100644 --- a/net/eth.c +++ b/net/eth.c @@ -501,10 +501,8 @@ char *eth_get_name (void) #elif defined(CONFIG_CMD_NET) && !defined(CONFIG_NET_MULTI) extern int at91rm9200_miiphy_initialize(bd_t *bis); -extern int emac4xx_miiphy_initialize(bd_t *bis); extern int mcf52x2_miiphy_initialize(bd_t *bis); extern int ns7520_miiphy_initialize(bd_t *bis); -extern int davinci_eth_miiphy_initialize(bd_t *bis); int eth_initialize(bd_t *bis) @@ -516,18 +514,12 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_AT91RM9200) at91rm9200_miiphy_initialize(bis); #endif -#if defined(CONFIG_PPC4xx_EMAC) - emac4xx_miiphy_initialize(bis); -#endif #if defined(CONFIG_MCF52x2) mcf52x2_miiphy_initialize(bis); #endif #if defined(CONFIG_DRIVER_NS7520_ETHERNET) ns7520_miiphy_initialize(bis); #endif -#if defined(CONFIG_DRIVER_TI_EMAC) - davinci_eth_miiphy_initialize(bis); -#endif return 0; } #endif diff --git a/tools/jtagconsole b/tools/jtagconsole new file mode 100755 index 00000000000..24198c83cac --- /dev/null +++ b/tools/jtagconsole @@ -0,0 +1,39 @@ +#!/bin/sh + +usage() { + ( + echo "Usage: $0 [board IP] [board port]" + echo "" + echo "If IP is not specified, 'localhost' will be used" + echo "If port is not specified, '2001' will be used" + [ -z "$*" ] && exit 0 + echo "" + echo "ERROR: $*" + exit 1 + ) 1>&2 + exit $? +} + +while [ -n "$1" ] ; do + case $1 in + -h|--help) usage;; + --) break;; + -*) usage "Invalid option $1";; + *) break;; + esac + shift +done + +ip=${1:-localhost} +port=${2:-2001} + +if [ -z "${ip}" ] || [ -n "$3" ] ; then + usage "Invalid number of arguments" +fi + +trap "stty icanon echo intr ^C" 0 2 3 5 10 13 15 +echo "NOTE: the interrupt signal (normally ^C) has been remapped to ^T" + +stty -icanon -echo intr ^T +nc ${ip} ${port} +exit 0 |