diff options
| -rw-r--r-- | arch/arm/cpu/armv7/tegra2/ap20.c | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra2/clock.c | 6 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra2/clock.h | 43 | ||||
| -rw-r--r-- | board/nvidia/common/board.c | 2 |
4 files changed, 26 insertions, 27 deletions
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index dc5f984d6f..64d4c69d24 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -36,7 +36,7 @@ u32 s_first_boot = 1; void init_pllx(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_XCPU]; + struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU]; u32 reg; /* If PLLX is already enabled, just return */ diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c index 0aaed7d948..5aa64821e4 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -42,7 +42,7 @@ enum clock_osc_freq clock_get_osc_freq(void) return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; } -unsigned long clock_start_pll(enum clock_pll_id clkid, u32 divm, u32 divn, +unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, u32 divp, u32 cpcon, u32 lfcon) { struct clk_rst_ctlr *clkrst = @@ -50,7 +50,7 @@ unsigned long clock_start_pll(enum clock_pll_id clkid, u32 divm, u32 divn, u32 data; struct clk_pll *pll; - assert(clock_pll_id_isvalid(clkid)); + assert(clock_id_isvalid(clkid)); pll = &clkrst->crc_pll[clkid]; /* @@ -66,7 +66,7 @@ unsigned long clock_start_pll(enum clock_pll_id clkid, u32 divm, u32 divn, data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) | (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT); - if (clkid == CLOCK_PLL_ID_USB) + if (clkid == CLOCK_ID_USB) data |= divp << PLLU_VCO_FREQ_SHIFT; else data |= divp << PLL_DIVP_SHIFT; diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h index d01aec825d..8adb23c8ac 100644 --- a/arch/arm/include/asm/arch-tegra2/clock.h +++ b/arch/arm/include/asm/arch-tegra2/clock.h @@ -22,7 +22,7 @@ /* Tegra2 clock control functions */ #ifndef _CLOCK_H - +#define _CLOCK_H /* Set of oscillator frequencies supported in the internal API. */ enum clock_osc_freq { @@ -36,22 +36,22 @@ enum clock_osc_freq { }; /* The PLLs supported by the hardware */ -enum clock_pll_id { - CLOCK_PLL_ID_FIRST, - CLOCK_PLL_ID_CGENERAL = CLOCK_PLL_ID_FIRST, - CLOCK_PLL_ID_MEMORY, - CLOCK_PLL_ID_PERIPH, - CLOCK_PLL_ID_AUDIO, - CLOCK_PLL_ID_USB, - CLOCK_PLL_ID_DISPLAY, +enum clock_id { + CLOCK_ID_FIRST, + CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, + CLOCK_ID_MEMORY, + CLOCK_ID_PERIPH, + CLOCK_ID_AUDIO, + CLOCK_ID_USB, + CLOCK_ID_DISPLAY, /* now the simple ones */ - CLOCK_PLL_ID_FIRST_SIMPLE, - CLOCK_PLL_ID_XCPU = CLOCK_PLL_ID_FIRST_SIMPLE, - CLOCK_PLL_ID_EPCI, - CLOCK_PLL_ID_SFROM32KHZ, + CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_EPCI, + CLOCK_ID_SFROM32KHZ, - CLOCK_PLL_ID_COUNT, + CLOCK_ID_COUNT, }; /* The clocks supported by the hardware */ @@ -80,7 +80,7 @@ enum periph_id { /* 16 */ PERIPH_ID_TWC, - PERIPH_ID_PWC, + PERIPH_ID_PWM, PERIPH_ID_I2S2, PERIPH_ID_EPP, PERIPH_ID_VI, @@ -181,8 +181,7 @@ enum periph_id { #define PERIPH_MASK(id) (1 << ((id) & 0x1f)) /* return 1 if a PLL ID is in range */ -#define clock_pll_id_isvalid(id) ((id) >= CLOCK_PLL_ID_FIRST && \ - (id) < CLOCK_PLL_ID_COUNT) +#define clock_id_isvalid(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) /* return 1 if a peripheral ID is in range */ #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ @@ -194,7 +193,7 @@ enum periph_id { /* return the current oscillator clock frequency */ enum clock_osc_freq clock_get_osc_freq(void); -/* +/** * Start PLL using the provided configuration parameters. * * @param id clock id @@ -206,7 +205,7 @@ enum clock_osc_freq clock_get_osc_freq(void); * * @returns monotonic time in us that the PLL will be stable */ -unsigned long clock_start_pll(enum clock_pll_id id, u32 divm, u32 divn, +unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, u32 divp, u32 cpcon, u32 lfcon); /* @@ -224,7 +223,7 @@ void clock_enable(enum periph_id clkid); */ void clock_set_enable(enum periph_id clkid, int enable); -/* +/** * Reset a peripheral. This puts it in reset, waits for a delay, then takes * it out of reset and waits for th delay again. * @@ -233,7 +232,7 @@ void clock_set_enable(enum periph_id clkid, int enable); */ void reset_periph(enum periph_id periph_id, int us_delay); -/* +/** * Put a peripheral into or out of reset. * * @param periph_id peripheral to reset @@ -251,7 +250,7 @@ enum crc_reset_id { crc_rst_debug = 1 << 4, }; -/* +/** * Put parts of the CPU complex into or out of reset.\ * * @param cpu cpu number (0 or 1 on Tegra2) diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 160dac8e1c..32d3cfb14e 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -77,7 +77,7 @@ int timer_init(void) static void clock_init_uart(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_PERIPH]; + struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH]; u32 reg; reg = readl(&pll->pll_base); |