diff options
| -rw-r--r-- | arch/arm/cpu/armv7/tegra-common/ap20.c | 5 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra-common/clock.c | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/ap20.h | 5 |
3 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/tegra-common/ap20.c b/arch/arm/cpu/armv7/tegra-common/ap20.c index 774567374a..529ce84860 100644 --- a/arch/arm/cpu/armv7/tegra-common/ap20.c +++ b/arch/arm/cpu/armv7/tegra-common/ap20.c @@ -605,3 +605,8 @@ void tegra_start(void) is_tegra_processor_reset = check_is_tegra_processor_reset(); } +void tegra_update_clocks(void) +{ + /* Enable CoreSight with new clock speed */ + clock_enable_coresight(1); +} diff --git a/arch/arm/cpu/armv7/tegra-common/clock.c b/arch/arm/cpu/armv7/tegra-common/clock.c index 8964c66208..01caab6b9f 100644 --- a/arch/arm/cpu/armv7/tegra-common/clock.c +++ b/arch/arm/cpu/armv7/tegra-common/clock.c @@ -1384,6 +1384,7 @@ int clock_early_init(ulong pllp_base) clock_set_rate(CLOCK_ID_PERIPH, 432, osc_freq_mhz, 1, 8); clock_set_rate(CLOCK_ID_CGENERAL, 600, osc_freq_mhz, 0, 8); } + tegra_update_clocks(); return 0; } diff --git a/arch/arm/include/asm/arch-tegra/ap20.h b/arch/arm/include/asm/arch-tegra/ap20.h index 6c1e57eea3..3d834e678d 100644 --- a/arch/arm/include/asm/arch-tegra/ap20.h +++ b/arch/arm/include/asm/arch-tegra/ap20.h @@ -129,3 +129,8 @@ int ap20_get_num_cpus(void); * @return SOC type - see TEGRA_SOC... */ int tegra_get_chip_type(void); + +/** + * Update any clocks that need to be adjusted after the fdt is available + */ +void tegra_update_clocks(void); |