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-rwxr-xr-xMAKEALL1
-rw-r--r--Makefile8
-rw-r--r--board/freescale/mpc8536ds/ddr.c6
-rw-r--r--board/freescale/mpc8536ds/law.c4
-rw-r--r--board/freescale/mpc8536ds/mpc8536ds.c30
-rw-r--r--board/freescale/mpc8536ds/tlb.c8
-rw-r--r--board/freescale/mpc8540ads/ddr.c3
-rw-r--r--board/freescale/mpc8540ads/law.c2
-rw-r--r--board/freescale/mpc8540ads/tlb.c8
-rw-r--r--board/freescale/mpc8541cds/tlb.c8
-rw-r--r--board/freescale/mpc8544ds/ddr.c3
-rw-r--r--board/freescale/mpc8544ds/mpc8544ds.c34
-rw-r--r--board/freescale/mpc8544ds/tlb.c6
-rw-r--r--board/freescale/mpc8548cds/mpc8548cds.c8
-rw-r--r--board/freescale/mpc8548cds/tlb.c6
-rw-r--r--board/freescale/mpc8555cds/tlb.c8
-rw-r--r--board/freescale/mpc8560ads/ddr.c3
-rw-r--r--board/freescale/mpc8560ads/law.c2
-rw-r--r--board/freescale/mpc8560ads/tlb.c8
-rw-r--r--board/freescale/mpc8568mds/law.c2
-rw-r--r--board/freescale/mpc8568mds/mpc8568mds.c8
-rw-r--r--board/freescale/mpc8568mds/tlb.c2
-rw-r--r--board/freescale/mpc8572ds/law.c4
-rw-r--r--board/freescale/mpc8572ds/mpc8572ds.c16
-rw-r--r--board/freescale/mpc8572ds/tlb.c12
-rw-r--r--board/freescale/mpc8610hpcd/ddr.c3
-rw-r--r--board/freescale/mpc8641hpcn/ddr.c2
-rw-r--r--board/stxgp3/ddr.c3
-rw-r--r--board/stxssa/ddr.c3
-rw-r--r--cpu/mpc85xx/cpu.c7
-rw-r--r--cpu/mpc85xx/fdt.c15
-rw-r--r--cpu/mpc85xx/pci.c32
-rw-r--r--cpu/mpc85xx/speed.c10
-rw-r--r--cpu/mpc8xxx/ddr/ctrl_regs.c48
-rw-r--r--cpu/mpc8xxx/ddr/options.c2
-rw-r--r--doc/README.mpc8572ds167
-rw-r--r--include/asm-ppc/fsl_ddr_sdram.h7
-rw-r--r--include/asm-ppc/fsl_lbc.h8
-rw-r--r--include/configs/MPC8536DS.h63
-rw-r--r--include/configs/MPC8540ADS.h13
-rw-r--r--include/configs/MPC8541CDS.h16
-rw-r--r--include/configs/MPC8544DS.h47
-rw-r--r--include/configs/MPC8548CDS.h28
-rw-r--r--include/configs/MPC8555CDS.h16
-rw-r--r--include/configs/MPC8560ADS.h13
-rw-r--r--include/configs/MPC8568MDS.h20
-rw-r--r--include/configs/MPC8572DS.h98
-rw-r--r--include/e500.h6
48 files changed, 595 insertions, 232 deletions
diff --git a/MAKEALL b/MAKEALL
index 29faaa5b597..530fe822948 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -374,6 +374,7 @@ LIST_85xx=" \
MPC8560ADS \
MPC8568MDS \
MPC8572DS \
+ MPC8572DS_36BIT \
PM854 \
PM856 \
sbc8540 \
diff --git a/Makefile b/Makefile
index 4aeae074a51..8c735866c15 100644
--- a/Makefile
+++ b/Makefile
@@ -2416,8 +2416,14 @@ MPC8555CDS_config: unconfig
MPC8568MDS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
+MPC8572DS_36BIT_config \
MPC8572DS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8572ds freescale
+ @mkdir -p $(obj)include
+ @if [ "$(findstring _36BIT_,$@)" ] ; then \
+ echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
+ $(XECHO) "... enabling 36-bit physical addressing." ; \
+ fi
+ @$(MKCONFIG) -a MPC8572DS ppc mpc85xx mpc8572ds freescale
PM854_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c
index 3135d6dfe4b..2bad787d606 100644
--- a/board/freescale/mpc8536ds/ddr.c
+++ b/board/freescale/mpc8536ds/ddr.c
@@ -79,4 +79,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
+
+ /*
+ * For wake up arp feature, we need enable auto self refresh
+ */
+ popts->auto_self_refresh_en = 1;
+ popts->sr_it = 0x6;
}
diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c
index 0861fa70800..31614d23887 100644
--- a/board/freescale/mpc8536ds/law.c
+++ b/board/freescale/mpc8536ds/law.c
@@ -30,14 +30,14 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
- SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
- SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+ SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
};
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 2b17612b336..1e2e2dc13af 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -192,14 +192,14 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE3_MEM_BASE,
+ CONFIG_SYS_PCIE3_MEM_BUS,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE3_IO_BASE,
+ CONFIG_SYS_PCIE3_IO_BUS,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
@@ -247,22 +247,22 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BASE,
+ CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
-#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE2,
+ CONFIG_SYS_PCIE1_MEM_BUS2,
CONFIG_SYS_PCIE1_MEM_PHYS2,
CONFIG_SYS_PCIE1_MEM_SIZE2,
PCI_REGION_MEM);
@@ -310,22 +310,22 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BASE,
+ CONFIG_SYS_PCIE2_MEM_BUS,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BASE,
+ CONFIG_SYS_PCIE2_IO_BUS,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
-#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BASE2,
+ CONFIG_SYS_PCIE2_MEM_BUS2,
CONFIG_SYS_PCIE2_MEM_PHYS2,
CONFIG_SYS_PCIE2_MEM_SIZE2,
PCI_REGION_MEM);
@@ -378,22 +378,22 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
-#ifdef CONFIG_SYS_PCI1_MEM_BASE2
+#ifdef CONFIG_SYS_PCI1_MEM_BUS2
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE2,
+ CONFIG_SYS_PCI1_MEM_BUS2,
CONFIG_SYS_PCI1_MEM_PHYS2,
CONFIG_SYS_PCI1_MEM_SIZE2,
PCI_REGION_MEM);
@@ -433,7 +433,7 @@ int board_early_init_r(void)
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
- set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c
index c81a9592208..35a13d44996 100644
--- a/board/freescale/mpc8536ds/tlb.c
+++ b/board/freescale/mpc8536ds/tlb.c
@@ -41,7 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE,
+ SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 0),
@@ -53,17 +53,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256K, 1),
diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c
index 7850794d64f..93d1100717f 100644
--- a/board/freescale/mpc8540ads/ddr.c
+++ b/board/freescale/mpc8540ads/ddr.c
@@ -65,6 +65,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
*/
popts->write_data_delay = 3;
+ /* 2T timing enable */
+ popts->twoT_en = 1;
+
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c
index 7dd8f29588a..f5644e15495 100644
--- a/board/freescale/mpc8540ads/law.c
+++ b/board/freescale/mpc8540ads/law.c
@@ -52,7 +52,7 @@ struct law_entry law_table[] = {
/* This is not so much the SDRAM map as it is the whole localbus map. */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
- SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+ SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c
index 2ec3ccce97d..a9925d54277 100644
--- a/board/freescale/mpc8540ads/tlb.c
+++ b/board/freescale/mpc8540ads/tlb.c
@@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
@@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
@@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 3: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
@@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 4: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c
index bf957c08cee..ae6812fc931 100644
--- a/board/freescale/mpc8541cds/tlb.c
+++ b/board/freescale/mpc8541cds/tlb.c
@@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
@@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
@@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 3: 256M Non-cacheable, guarded
* 0xa0000000 256M PCI2 MEM First half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
@@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 4: 256M Non-cacheable, guarded
* 0xb0000000 256M PCI2 MEM Second half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c
index 34f84a26562..b8330eb961d 100644
--- a/board/freescale/mpc8544ds/ddr.c
+++ b/board/freescale/mpc8544ds/ddr.c
@@ -75,6 +75,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
*/
popts->write_data_delay = 3;
+ /* 2T timing enable */
+ popts->twoT_en = 1;
+
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 977731289b1..7ff5a9bb832 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -139,22 +139,22 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE3_MEM_BASE,
+ CONFIG_SYS_PCIE3_MEM_BUS,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE3_IO_BASE,
+ CONFIG_SYS_PCIE3_IO_BUS,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
-#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE3_MEM_BASE2,
+ CONFIG_SYS_PCIE3_MEM_BUS2,
CONFIG_SYS_PCIE3_MEM_PHYS2,
CONFIG_SYS_PCIE3_MEM_SIZE2,
PCI_REGION_MEM);
@@ -173,7 +173,7 @@ pci_init_board(void)
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
*/
- in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BASE);
+ in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
} else {
printf (" PCIE3: disabled\n");
}
@@ -206,22 +206,22 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BASE,
+ CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
-#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE2,
+ CONFIG_SYS_PCIE1_MEM_BUS2,
CONFIG_SYS_PCIE1_MEM_PHYS2,
CONFIG_SYS_PCIE1_MEM_SIZE2,
PCI_REGION_MEM);
@@ -269,22 +269,22 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BASE,
+ CONFIG_SYS_PCIE2_MEM_BUS,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BASE,
+ CONFIG_SYS_PCIE2_IO_BUS,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
-#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BASE2,
+ CONFIG_SYS_PCIE2_MEM_BUS2,
CONFIG_SYS_PCIE2_MEM_PHYS2,
CONFIG_SYS_PCIE2_MEM_SIZE2,
PCI_REGION_MEM);
@@ -337,22 +337,22 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
-#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE3_MEM_BASE2,
+ CONFIG_SYS_PCIE3_MEM_BUS2,
CONFIG_SYS_PCIE3_MEM_PHYS2,
CONFIG_SYS_PCIE3_MEM_SIZE2,
PCI_REGION_MEM);
diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c
index c7442b26ffc..d99441b2cb8 100644
--- a/board/freescale/mpc8544ds/tlb.c
+++ b/board/freescale/mpc8544ds/tlb.c
@@ -52,21 +52,21 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 1: 1G Non-cacheable, guarded
* 0x80000000 1G PCIE 8,9,a,b
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_PHYS, CONFIG_SYS_PCIE_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1G, 1),
/*
* TLB 2: 256M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 90e89bc7192..70320ea1a74 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -306,14 +306,14 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
@@ -390,14 +390,14 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BASE,
+ CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index eab212a4c5c..2267ad7478c 100644
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 1: 1G Non-cacheable, guarded
* 0x80000000 1G PCI1/PCIE 8,9,a,b
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1G, 1),
@@ -62,14 +62,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
/*
* TLB 2: 256M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
#endif
diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c
index bf957c08cee..ae6812fc931 100644
--- a/board/freescale/mpc8555cds/tlb.c
+++ b/board/freescale/mpc8555cds/tlb.c
@@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
@@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
@@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 3: 256M Non-cacheable, guarded
* 0xa0000000 256M PCI2 MEM First half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
@@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 4: 256M Non-cacheable, guarded
* 0xb0000000 256M PCI2 MEM Second half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c
index 7850794d64f..93d1100717f 100644
--- a/board/freescale/mpc8560ads/ddr.c
+++ b/board/freescale/mpc8560ads/ddr.c
@@ -65,6 +65,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
*/
popts->write_data_delay = 3;
+ /* 2T timing enable */
+ popts->twoT_en = 1;
+
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c
index 7dd8f29588a..f5644e15495 100644
--- a/board/freescale/mpc8560ads/law.c
+++ b/board/freescale/mpc8560ads/law.c
@@ -52,7 +52,7 @@ struct law_entry law_table[] = {
/* This is not so much the SDRAM map as it is the whole localbus map. */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
- SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+ SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c
index 2ec3ccce97d..a9925d54277 100644
--- a/board/freescale/mpc8560ads/tlb.c
+++ b/board/freescale/mpc8560ads/tlb.c
@@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
@@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
@@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 3: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
@@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 4: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c
index da7b6dcb722..3114e8a173e 100644
--- a/board/freescale/mpc8568mds/law.c
+++ b/board/freescale/mpc8568mds/law.c
@@ -54,7 +54,7 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CONFIG_SYS_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+ SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 7a23b338a59..915fae7fa40 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -397,14 +397,14 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
@@ -450,14 +450,14 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BASE,
+ CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c
index 107755273ec..8470c878e19 100644
--- a/board/freescale/mpc8568mds/tlb.c
+++ b/board/freescale/mpc8568mds/tlb.c
@@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* 0x80000000 512M PCI1 MEM
* 0xa0000000 512M PCIe MEM
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1G, 1),
diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c
index 83eb6811c05..02ea0ec59ed 100644
--- a/board/freescale/mpc8572ds/law.c
+++ b/board/freescale/mpc8572ds/law.c
@@ -28,14 +28,14 @@
#include <asm/mmu.h>
struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
- SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+ SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
};
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index c2487e5b844..e57f9fff2b6 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -185,14 +185,14 @@ void pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE3_MEM_BASE,
+ CONFIG_SYS_PCIE3_MEM_BUS,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE3_IO_BASE,
+ CONFIG_SYS_PCIE3_IO_BUS,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
@@ -215,7 +215,7 @@ void pci_init_board(void)
pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
PCI_BASE_ADDRESS_1, &temp32);
- if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) {
+ if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
debug(" uli1572 read to %x\n", temp32);
in_be32((unsigned *)temp32);
}
@@ -252,14 +252,14 @@ void pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BASE,
+ CONFIG_SYS_PCIE2_MEM_BUS,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BASE,
+ CONFIG_SYS_PCIE2_IO_BUS,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
@@ -307,14 +307,14 @@ void pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BASE,
+ CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
@@ -358,7 +358,7 @@ int board_early_init_r(void)
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
- set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c
index 829896ac060..d832f89742f 100644
--- a/board/freescale/mpc8572ds/tlb.c
+++ b/board/freescale/mpc8572ds/tlb.c
@@ -54,26 +54,26 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_PHYS, CONFIG_SYS_PCIE3_IO_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
@@ -82,7 +82,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
- SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE,
+ SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_4K, 1),
};
diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c
index 414ac243a5b..0117d136bbb 100644
--- a/board/freescale/mpc8610hpcd/ddr.c
+++ b/board/freescale/mpc8610hpcd/ddr.c
@@ -74,6 +74,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
*/
popts->write_data_delay = 3;
+ /* 2T timing enable */
+ popts->twoT_en = 1;
+
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c
index 3789b5442ec..8dc249b99dc 100644
--- a/board/freescale/mpc8641hpcn/ddr.c
+++ b/board/freescale/mpc8641hpcn/ddr.c
@@ -162,4 +162,6 @@ void fsl_ddr_board_options(memctl_options_t *popts,
}
}
+ /* 2T timing enable */
+ popts->twoT_en = 1;
}
diff --git a/board/stxgp3/ddr.c b/board/stxgp3/ddr.c
index 7850794d64f..93d1100717f 100644
--- a/board/stxgp3/ddr.c
+++ b/board/stxgp3/ddr.c
@@ -65,6 +65,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
*/
popts->write_data_delay = 3;
+ /* 2T timing enable */
+ popts->twoT_en = 1;
+
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
diff --git a/board/stxssa/ddr.c b/board/stxssa/ddr.c
index 7850794d64f..93d1100717f 100644
--- a/board/stxssa/ddr.c
+++ b/board/stxssa/ddr.c
@@ -65,6 +65,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
*/
popts->write_data_delay = 3;
+ /* 2T timing enable */
+ popts->twoT_en = 1;
+
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 15ba7f1c5ed..a34e2515e80 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -90,6 +90,7 @@ int checkcpu (void)
#else
u32 ddr_ratio = 0;
#endif
+ int i;
svr = get_svr();
ver = SVR_SOC_VER(svr);
@@ -141,8 +142,10 @@ int checkcpu (void)
get_sys_info(&sysinfo);
- puts("Clock Configuration:\n");
- printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
+ puts("Clock Configuration:\n ");
+ for (i = 0; i < CONFIG_NUM_CPUS; i++)
+ printf("CPU%d:%-4s MHz, ",
+ i,strmhz(buf1, sysinfo.freqProcessor[i]));
printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
switch (ddr_ratio) {
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index 69fab995270..1fae47c2dcd 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -213,6 +213,10 @@ void fdt_add_enet_stashing(void *fdt)
void ft_cpu_setup(void *blob, bd_t *bd)
{
+ int off;
+ int val;
+ sys_info_t sysinfo;
+
/* delete crypto node if not on an E-processor */
if (!IS_E_PROCESSOR(get_svr()))
fdt_fixup_crypto_node(blob, 0);
@@ -228,8 +232,15 @@ void ft_cpu_setup(void *blob, bd_t *bd)
"timebase-frequency", bd->bi_busfreq / 8, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
- do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "clock-frequency", bd->bi_intfreq, 1);
+ get_sys_info(&sysinfo);
+ off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
+ while (off != -FDT_ERR_NOTFOUND) {
+ u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
+ val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]);
+ fdt_setprop(blob, off, "clock-frequency", &val, 4);
+ off = fdt_node_offset_by_prop_value(blob, off, "device_type",
+ "cpu", 4);
+ }
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c
index 787c6eb74c4..fedf1a54df6 100644
--- a/cpu/mpc85xx/pci.c
+++ b/cpu/mpc85xx/pci.c
@@ -31,6 +31,22 @@
#if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT)
+#ifndef CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
+#endif
+
+#ifndef CONFIG_SYS_PCI1_IO_BUS
+#define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE
+#endif
+
+#ifndef CONFIG_SYS_PCI2_MEM_BUS
+#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
+#endif
+
+#ifndef CONFIG_SYS_PCI2_IO_BUS
+#define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE
+#endif
+
static struct pci_controller *pci_hose;
void
@@ -80,14 +96,14 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
}
- pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & 0x000fffff;
+ pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff;
pcix->potear1 = 0x00000000;
pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
pcix->powbear1 = 0x00000000;
pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
- pcix->potar2 = (CONFIG_SYS_PCI1_IO_BASE >> 12) & 0x000fffff;
+ pcix->potar2 = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff;
pcix->potear2 = 0x00000000;
pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
pcix->powbear2 = 0x00000000;
@@ -105,13 +121,13 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pcix->piwar3 = 0;
pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
@@ -165,14 +181,14 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
*/
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & 0x000fffff;
+ pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff;
pcix2->potear1 = 0x00000000;
pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
pcix2->powbear1 = 0x00000000;
pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
- pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BASE >> 12) & 0x000fffff;
+ pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff;
pcix2->potear2 = 0x00000000;
pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
pcix2->powbear2 = 0x00000000;
@@ -190,13 +206,13 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pcix2->piwar3 = 0;
pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI2_MEM_BASE,
+ CONFIG_SYS_PCI2_MEM_BUS,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI2_IO_BASE,
+ CONFIG_SYS_PCI2_IO_BUS,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 0d55228b641..b0f47e042e9 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -39,17 +39,19 @@ void get_sys_info (sys_info_t * sysInfo)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint plat_ratio,e500_ratio,half_freqSystemBus;
uint lcrr_div;
+ int i;
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
- e500_ratio = (gur->porpllsr) & 0x003f0000;
- e500_ratio >>= 16;
/* Divide before multiply to avoid integer
* overflow for processor speeds above 2GHz */
half_freqSystemBus = sysInfo->freqSystemBus/2;
- sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
+ for (i = 0; i < CONFIG_NUM_CPUS; i++) {
+ e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
+ sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
+ }
/* Note: freqDDRBus is the MCLK frequency, not the data rate. */
sysInfo->freqDDRBus = sysInfo->freqSystemBus;
@@ -105,7 +107,7 @@ int get_clocks (void)
dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
get_sys_info (&sys_info);
- gd->cpu_clk = sys_info.freqProcessor;
+ gd->cpu_clk = sys_info.freqProcessor[0];
gd->bus_clk = sys_info.freqSystemBus;
gd->mem_clk = sys_info.freqDDRBus;
gd->lbc_clk = sys_info.freqLocalBus;
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 1783e927a54..292980d0b07 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -167,7 +167,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
| ((trrt_mclk & 0x3) << 26) /* RRT */
| ((twwt_mclk & 0x3) << 24) /* WWT */
| ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
- | ((pre_pd_exit_mclk & 0x7) << 16) /* PRE_PD_EXIT */
+ | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
| ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
| ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
);
@@ -185,10 +185,14 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
unsigned int cntl_adj = 0; /* Control Adjust */
+ /* If the tRAS > 19 MCLK, we use the ext mode */
+ if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
+ ext_acttopre = 1;
+
ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
ddr->timing_cfg_3 = (0
| ((ext_acttopre & 0x1) << 24)
- | ((ext_refrec & 0x7) << 16)
+ | ((ext_refrec & 0xF) << 16)
| ((ext_caslat & 0x1) << 12)
| ((cntl_adj & 0x7) << 0)
);
@@ -251,12 +255,12 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
ddr->timing_cfg_1 = (0
- | ((pretoact_mclk & 0x07) << 28)
+ | ((pretoact_mclk & 0x0F) << 28)
| ((acttopre_mclk & 0x0F) << 24)
- | ((acttorw_mclk & 0x7) << 20)
+ | ((acttorw_mclk & 0xF) << 20)
| ((caslat_ctrl & 0xF) << 16)
| ((refrec_ctrl & 0xF) << 12)
- | ((wrrec_mclk & 0x07) << 8)
+ | ((wrrec_mclk & 0x0F) << 8)
| ((acttoact_mclk & 0x07) << 4)
| ((wrtord_mclk & 0x07) << 0)
);
@@ -309,13 +313,13 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
ddr->timing_cfg_2 = (0
- | ((add_lat_mclk & 0x7) << 28)
+ | ((add_lat_mclk & 0xf) << 28)
| ((cpo & 0x1f) << 23)
- | ((wr_lat & 0x7) << 19)
+ | ((wr_lat & 0xf) << 19)
| ((rd_to_pre & 0x7) << 13)
| ((wr_data_delay & 0x7) << 10)
| ((cke_pls & 0x7) << 6)
- | ((four_act & 0x1f) << 0)
+ | ((four_act & 0x3f) << 0)
);
debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
}
@@ -332,7 +336,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
unsigned int sdram_type; /* Type of SDRAM */
unsigned int dyn_pwr; /* Dynamic power management mode */
unsigned int dbw; /* DRAM dta bus width */
- unsigned int eight_be; /* 8-beat burst enable */
+ unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
unsigned int ncap = 0; /* Non-concurrent auto-precharge */
unsigned int threeT_en; /* Enable 3T timing */
unsigned int twoT_en; /* Enable 2T timing */
@@ -359,7 +363,9 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
dyn_pwr = popts->dynamic_power;
dbw = popts->data_bus_width;
- eight_be = 0; /* always 0 for DDR2 */
+ /* DDR3 must use 8-beat bursts when using 32-bit bus mode */
+ if ((sdram_type == SDRAM_TYPE_DDR3) && (dbw == 0x1))
+ eight_be = 1;
threeT_en = popts->threeT_en;
twoT_en = popts->twoT_en;
ba_intlv_ctl = popts->ba_intlv_ctl;
@@ -691,10 +697,10 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
unsigned int wodt_off = 0; /* Write to ODT off */
ddr->timing_cfg_5 = (0
- | ((rodt_on & 0xf) << 24)
- | ((rodt_off & 0xf) << 20)
- | ((wodt_on & 0xf) << 12)
- | ((wodt_off & 0xf) << 8)
+ | ((rodt_on & 0x1f) << 24)
+ | ((rodt_off & 0x7) << 20)
+ | ((wodt_on & 0x1f) << 12)
+ | ((wodt_off & 0x7) << 8)
);
debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
}
@@ -744,15 +750,14 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr)
| ((wrlvl_dqsen & 0x7) << 16)
| ((wrlvl_smpl & 0xf) << 12)
| ((wrlvl_wlr & 0x7) << 8)
- | ((wrlvl_start & 0xF) << 0)
+ | ((wrlvl_start & 0x1F) << 0)
);
}
/* DDR Self Refresh Counter (DDR_SR_CNTR) */
-static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr)
+static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
{
- unsigned int sr_it = 0; /* Self Refresh Idle Threshold */
-
+ /* Self Refresh Idle Threshold */
ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
}
@@ -855,6 +860,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
unsigned int i;
unsigned int cas_latency;
unsigned int additive_latency;
+ unsigned int sr_it;
memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
@@ -876,6 +882,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
? popts->additive_latency_override_value
: common_dimm->additive_latency;
+ sr_it = (popts->auto_self_refresh_en)
+ ? popts->sr_it
+ : 0;
+
/* Chip Select Memory Bounds (CSn_BNDS) */
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
phys_size_t sa = 0;
@@ -1036,7 +1046,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_ddr_wrlvl_cntl(ddr);
set_ddr_pd_cntl(ddr);
- set_ddr_sr_cntr(ddr);
+ set_ddr_sr_cntr(ddr, sr_it);
set_ddr_sdram_rcw_1(ddr);
set_ddr_sdram_rcw_2(ddr);
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index af7f73a835a..d4702d73bc9 100644
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -142,7 +142,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
* - number of components, number of active ranks
* - how much time you want to spend playing around
*/
- popts->twoT_en = 1;
+ popts->twoT_en = 0;
popts->threeT_en = 0;
/*
diff --git a/doc/README.mpc8572ds b/doc/README.mpc8572ds
new file mode 100644
index 00000000000..f9ffde4457f
--- /dev/null
+++ b/doc/README.mpc8572ds
@@ -0,0 +1,167 @@
+Overview
+--------
+MPC8572DS is a high-performance computing, evaluation and development platform
+supporting the mpc8572 PowerTM processor.
+
+Building U-boot
+-----------
+ make MPC8572DS_config
+ make
+
+Flash Banks
+-----------
+MPC8572DS board has two flash banks. They are both present on boot, but their
+locations can be swapped using the dip-switch SW9[1:2].
+
+Booting is always from the boot bank at 0xec00_0000.
+
+
+Memory Map
+----------
+
+0xe800_0000 - 0xebff_ffff Alernate bank 64MB
+0xec00_0000 - 0xefff_ffff Boot bank 64MB
+
+0xebf8_0000 - 0xebff_ffff Alternate u-boot address 512KB
+0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB
+
+
+Flashing Images
+---------------
+
+To place a new u-boot image in the alternate flash bank and then reset with that
+ new image temporarily, use this:
+
+ tftp 1000000 u-boot.bin
+ erase ebf80000 ebffffff
+ cp.b 1000000 ebf80000 80000
+ pixis_reset altbank
+
+
+To program the image in the boot flash bank:
+
+ tftp 1000000 u-boot.bin
+ protect off all
+ erase eff80000 ffffffff
+ cp.b 1000000 eff80000 80000
+
+
+The pixis_reset command
+-----------------------
+The command - "pixis_reset", is introduced to reset mpc8572ds board
+using the FPGA sequencer. When the board restarts, it has the option
+of using either the current or alternate flash bank as the boot
+image, with or without the watchdog timer enabled, and finally with
+or without frequency changes.
+
+Usage is;
+
+ pixis_reset
+ pixis_reset altbank
+ pixis_reset altbank wd
+ pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+ pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+
+Examples:
+
+ /* reset to current bank, like "reset" command */
+ pixis_reset
+
+ /* reset board but use the to alternate flash bank */
+ pixis_reset altbank
+
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+ dtc -b 0 -f -I dts -O dtb mpc8572ds.dts > mpc8572ds.dtb
+
+Likely, that .dts file will come from here;
+
+ linux-2.6/arch/powerpc/boot/dts/mpc8572ds.dts
+
+
+Booting Linux
+-------------
+
+Place a linux uImage in the TFTP disk area.
+
+ tftp 1000000 uImage.8572
+ tftp c00000 mpc8572ds.dtb
+ bootm 1000000 - c00000
+
+
+Implementing AMP(Asymmetric MultiProcessing)
+-------------
+1. Build kernel image for core0:
+
+ a. $ make 85xx/mpc8572_ds_defconfig
+
+ b. $ make menuconfig
+ - un-select "Processor support"->"Symetric multi-processing support"
+
+ c. $ make uImage
+
+ d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
+
+2. Build kernel image for core1:
+
+ a. $ make 85xx/mpc8572_ds_defconfig
+
+ b. $ make menuconfig
+ - Un-select "Processor support"->"Symetric multi-processing support"
+ - Select "Advanced setup" -> " Prompt for advanced kernel
+ configuration options"
+ - Select "Set physical address where the kernel is loaded" and
+ set it to 0x20000000, asssuming core1 will start from 512MB.
+ - Select "Set custom page offset address"
+ - Select "Set custom kernel base address"
+ - Select "Set maximum low memory"
+ - "Exit" and save the selection.
+
+ c. $ make uImage
+
+ d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
+
+3. Create dtb for core0:
+
+ $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb
+
+4. Create dtb for core1:
+
+ $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb
+
+5. Bring up two cores separately:
+
+ a. Power on the board, under u-boot prompt:
+ => setenv <serverip>
+ => setenv <ipaddr>
+ => setenv bootargs root=/dev/ram rw console=ttyS0,115200
+ b. Bring up core1's kernel first:
+ => setenv bootm_low 0x20000000
+ => setenv bootm_size 0x10000000
+ => tftp 21000000 8572/uImage.core1
+ => tftp 22000000 8572/ramdiskfile
+ => tftp 20c00000 8572/mpc8572ds_core1.dtb
+ => interrupts off
+ => bootm start 21000000 22000000 20c00000
+ => bootm loados
+ => bootm ramdisk
+ => bootm fdt
+ => fdt boardsetup
+ => fdt chosen $initrd_start $initrd_end
+ => bootm prep
+ => cpu 1 release $bootm_low - $fdtaddr -
+ c. Bring up core0's kernel(on the same u-boot console):
+ => setenv bootm_low 0
+ => setenv bootm_size 0x20000000
+ => tftp 1000000 8572/uImage.core0
+ => tftp 2000000 8572/ramdiskfile
+ => tftp c00000 8572/mpc8572ds_core0.dtb
+ => bootm 1000000 2000000 c00000
+
+Please note only core0 will run u-boot, core1 starts kernel directly after
+"cpu release" command is issued.
+
diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h
index c1ea7cd6bb1..b213af35ef3 100644
--- a/include/asm-ppc/fsl_ddr_sdram.h
+++ b/include/asm-ppc/fsl_ddr_sdram.h
@@ -34,7 +34,10 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
#elif defined(CONFIG_FSL_DDR3)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
#endif
+#endif /* #if defined(CONFIG_FSL_DDR1) */
/* define bank(chip select) interleaving mode */
#define FSL_DDR_CS0_CS1 0x40
@@ -143,6 +146,10 @@ typedef struct memctl_options_s {
unsigned int bstopre;
unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */
+
+ /* Automatic self refresh */
+ unsigned int auto_self_refresh_en;
+ unsigned int sr_it;
} memctl_options_t;
extern phys_size_t fsl_ddr_sdram(void);
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index e492c62a8bc..9fa0b659499 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -28,6 +28,8 @@
#define BR_BA 0xFFFF8000
#define BR_BA_SHIFT 15
+#define BR_XBA 0x00006000
+#define BR_XBA_SHIFT 13
#define BR_PS 0x00001800
#define BR_PS_SHIFT 11
#define BR_PS_8 0x00000800 /* Port Size 8 bit */
@@ -70,7 +72,7 @@
#endif
/* Convert an address into the right format for the BR registers */
-#ifdef CONFIG_PHYS_64BIT
+#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
((x & 0x300000000ULL) >> 19)))
#else
@@ -90,6 +92,8 @@
#define OR_GPCM_AM 0xFFFF8000
#define OR_GPCM_AM_SHIFT 15
+#define OR_GPCM_XAM 0x00006000
+#define OR_GPCM_XAM_SHIFT 13
#define OR_GPCM_BCTLD 0x00001000
#define OR_GPCM_BCTLD_SHIFT 12
#define OR_GPCM_CSNT 0x00000800
@@ -132,6 +136,8 @@
#define OR_FCM_AM 0xFFFF8000
#define OR_FCM_AM_SHIFT 15
+#define OR_FCM_XAM 0x00006000
+#define OR_FCM_XAM_SHIFT 13
#define OR_FCM_BCTLD 0x00001000
#define OR_FCM_BCTLD_SHIFT 12
#define OR_FCM_PGS 0x00000400
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 505c48be2ba..e379d5327d9 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -34,6 +34,7 @@
#define CONFIG_MPC8536 1
#define CONFIG_MPC8536DS 1
+#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
@@ -166,12 +167,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
* Local Bus Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BR0_PRELIM 0xe8001001
-#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
+#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
-#define CONFIG_SYS_BR1_PRELIM 0xe0001001
-#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
+#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
#define CONFIG_SYS_FLASH_QUIET_TEST
@@ -194,8 +196,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
+#define PIXIS_BASE_PHYS PIXIS_BASE
-#define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */
+#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
@@ -254,7 +257,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* NAND flash config */
-#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
+#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
@@ -271,20 +274,20 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\
+#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
+#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\
+#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
@@ -355,34 +358,42 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_BASE 0x90000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_BASE 0x98000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
-#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 3, direct to uli, tgtid 3, Base address 8000 */
-#define CONFIG_SYS_PCIE3_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
@@ -392,10 +403,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_PHYS
+#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/
+/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
/* video */
#define CONFIG_VIDEO
@@ -408,7 +419,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
/*#define CONFIG_CONSOLE_CURSOR*/
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_PHYS
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
#endif
#undef CONFIG_EEPRO100
@@ -422,8 +433,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#endif
#ifndef CONFIG_PCI_PNP
- #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
- #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BASE
+ #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
+ #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
#endif
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index f22b7529dda..0d03b0b85f8 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -308,18 +308,21 @@
#define CONFIG_SYS_I2C_OFFSET 0x3000
/* RapidIO MMU */
-#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
-#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
+#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
+#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
+#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 399189c598e..fa82fbc6fde 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -341,17 +341,21 @@ extern unsigned long get_clock_freq(void);
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
-#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
+#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
#define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 9b1b34cc8bc..59cfde6284b 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -263,50 +263,61 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
+#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
#define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
+#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
#define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
-#define CONFIG_SYS_PCI1_MEM_BASE 0xc0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 1, tgtid 1, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 2,tgtid 2, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 3, direct to uli, tgtid 3, Base address b000 */
-#define CONFIG_SYS_PCIE3_MEM_BASE 0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
-#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
-#define CONFIG_SYS_PCIE3_MEM_BASE2 0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_PHYS2 CONFIG_SYS_PCIE3_MEM_BASE2
+#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
#if defined(CONFIG_PCI)
/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_PHYS
+#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/
+/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
/* video */
#define CONFIG_VIDEO
@@ -336,8 +347,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
#ifndef CONFIG_PCI_PNP
- #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
- #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BASE
+ #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
+ #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
#endif
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index e1bd45ef1b0..95bce951479 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -365,29 +365,36 @@ extern unsigned long get_clock_freq(void);
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
+#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#ifdef CONFIG_PCI2
-#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000
+#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
#endif
#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
#endif
@@ -396,7 +403,8 @@ extern unsigned long get_clock_freq(void);
/*
* RapidIO MMU
*/
-#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
+#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000
+#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000
#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
#endif
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index c92f82d48c9..6bf09613b09 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -339,17 +339,21 @@ extern unsigned long get_clock_freq(void);
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
+#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index bf4bd2c1a00..3f78a6e120a 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -300,18 +300,21 @@
#define CONFIG_SYS_I2C_OFFSET 0x3000
/* RapidIO MMU */
-#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
-#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
+#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
+#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
+#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index da1f4542281..58ff52b33fd 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -322,21 +322,27 @@ extern unsigned long get_clock_freq(void);
* General PCI
* Memory Addresses are mapped 1-1. I/O is mapped from 0
*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
-#define CONFIG_SYS_SRIO_MEM_BASE 0xc0000000
+#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000
+#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000
#ifdef CONFIG_QE
/*
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index f84cc7e9c13..ac0a4641e9e 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -36,6 +36,7 @@
#define CONFIG_MP 1 /* support multiple processors */
#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
+#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
@@ -74,6 +75,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_ENABLE_36BIT_PHYS 1
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+#endif
+
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x7fffffff
#define CONFIG_PANIC_HANG /* do not reset board on panic */
@@ -84,7 +90,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
*/
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
+#else
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
+#endif
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
@@ -169,14 +179,19 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
* Local Bus Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#endif
-#define CONFIG_SYS_BR0_PRELIM 0xe8001001
-#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
+#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
-#define CONFIG_SYS_BR1_PRELIM 0xe0001001
-#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
+#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
@@ -197,8 +212,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
+#ifdef CONFIG_PHYS_64BIT
+#define PIXIS_BASE_PHYS 0xfffdf0000ull
+#else
+#define PIXIS_BASE_PHYS PIXIS_BASE
+#endif
-#define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */
+#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
@@ -261,7 +281,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
#define CONFIG_SYS_NAND_BASE 0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
+#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
CONFIG_SYS_NAND_BASE + 0x40000, \
CONFIG_SYS_NAND_BASE + 0x80000,\
@@ -273,7 +297,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* NAND flash config */
-#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
+#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
@@ -290,20 +314,20 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\
+#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
+#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\
+#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
@@ -378,33 +402,63 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
*/
/* controller 3, direct to uli, tgtid 3, Base address 8000 */
-#define CONFIG_SYS_PCIE3_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
+#endif
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
+#else
#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
+#endif
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
+#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
+#else
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
+#endif
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
+#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
+#else
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
+#endif
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
#if defined(CONFIG_PCI)
/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_PHYS
+#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
/* video */
#define CONFIG_VIDEO
@@ -434,8 +488,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#endif
#ifndef CONFIG_PCI_PNP
- #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BASE
- #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BASE
+ #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
+ #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
#endif
diff --git a/include/e500.h b/include/e500.h
index 9d3c8417c01..4c5eeb74e14 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -8,9 +8,13 @@
#ifndef __ASSEMBLY__
+#ifndef CONFIG_NUM_CPUS
+#define CONFIG_NUM_CPUS 1
+#endif
+
typedef struct
{
- unsigned long freqProcessor;
+ unsigned long freqProcessor[CONFIG_NUM_CPUS];
unsigned long freqSystemBus;
unsigned long freqDDRBus;
unsigned long freqLocalBus;