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-rw-r--r--arch/x86/cpu/ivybridge/early_me.c3
-rw-r--r--arch/x86/cpu/ivybridge/sdram.c6
-rw-r--r--arch/x86/include/asm/cpu.h9
-rw-r--r--configs/chromebox_panther_defconfig2
4 files changed, 16 insertions, 4 deletions
diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c
index 612c9103e3..f0d6899006 100644
--- a/arch/x86/cpu/ivybridge/early_me.c
+++ b/arch/x86/cpu/ivybridge/early_me.c
@@ -10,6 +10,7 @@
#include <dm.h>
#include <errno.h>
#include <asm/pci.h>
+#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/arch/me.h>
#include <asm/arch/pch.h>
@@ -189,7 +190,7 @@ int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
}
static const struct udevice_id ivybridge_syscon_ids[] = {
- { .compatible = "intel,me", },
+ { .compatible = "intel,me", .data = X86_SYSCON_ME },
{ }
};
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 3e5be4e0a0..e23c422cd0 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -18,6 +18,8 @@
#include <rtc.h>
#include <spi.h>
#include <spi_flash.h>
+#include <syscon.h>
+#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/gpio.h>
#include <asm/global_data.h>
@@ -739,11 +741,9 @@ int dram_init(void)
return ret;
if (!dev)
return -ENODEV;
- ret = uclass_first_device(UCLASS_SYSCON, &me_dev);
+ ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
if (ret)
return ret;
- if (!me_dev)
- return -ENODEV;
debug("Boot mode %d\n", gd->arch.pei_boot_mode);
debug("mrc_input %p\n", pei_data.mrc_input);
pei_data.boot_mode = gd->arch.pei_boot_mode;
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index c70183ccef..76cdf47509 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -45,6 +45,15 @@ enum {
GDT_BASE_HIGH_MASK = 0xf,
};
+/*
+ * System controllers in an x86 system. We mostly need to just find these and
+ * use them on PCI. At some point these might have their own uclass.
+ */
+enum {
+ X86_NONE,
+ X86_SYSCON_ME, /* Intel Management Engine */
+};
+
struct cpuid_result {
uint32_t eax;
uint32_t ebx;
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index 17a94f8f1e..e4a3821047 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -16,6 +16,8 @@ CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y