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-rw-r--r--arch/arm/dts/zynqmp-clk-ccf.dtsi290
-rw-r--r--arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts2
-rw-r--r--arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts2
-rw-r--r--arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts2
-rw-r--r--arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts2
-rw-r--r--arch/arm/dts/zynqmp-zcu102-revA.dts2
-rw-r--r--configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zcu102_rev1_0_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zcu102_revA_defconfig1
-rw-r--r--configs/xilinx_zynqmp_zcu102_revB_defconfig1
13 files changed, 302 insertions, 5 deletions
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
new file mode 100644
index 0000000000..4449d5b93d
--- /dev/null
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -0,0 +1,290 @@
+/*
+ * Clock specification for Xilinx ZynqMP
+ *
+ * (C) Copyright 2017, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ fclk0: fclk0 {
+ status = "disabled";
+ compatible = "xlnx,fclk";
+ clocks = <&clkc 71>;
+ };
+
+ fclk1: fclk1 {
+ status = "disabled";
+ compatible = "xlnx,fclk";
+ clocks = <&clkc 72>;
+ };
+
+ fclk2: fclk2 {
+ status = "disabled";
+ compatible = "xlnx,fclk";
+ clocks = <&clkc 73>;
+ };
+
+ fclk3: fclk3 {
+ status = "disabled";
+ compatible = "xlnx,fclk";
+ clocks = <&clkc 74>;
+ };
+
+ pss_ref_clk: pss_ref_clk {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33333333>;
+ };
+
+ video_clk: video_clk {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+
+ pss_alt_ref_clk: pss_alt_ref_clk {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ gt_crx_ref_clk: gt_crx_ref_clk {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <108000000>;
+ };
+
+ aux_ref_clk: aux_ref_clk {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+
+ clkc: clkc {
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ compatible = "xlnx,zynqmp-clkc";
+ clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
+ clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
+ clock-output-names = "iopll", "rpll", "apll", "dpll",
+ "vpll", "iopll_to_fpd", "rpll_to_fpd",
+ "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
+ "acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
+ "dbg_trace", "dbg_tstmp", "dp_video_ref",
+ "dp_audio_ref", "dp_stc_ref", "gdma_ref",
+ "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
+ "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
+ "topsw_main", "topsw_lsbus", "gtgref0_ref",
+ "lpd_switch", "lpd_lsbus", "usb0_bus_ref",
+ "usb1_bus_ref", "usb3_dual_ref", "usb0",
+ "usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
+ "csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
+ "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
+ "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
+ "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
+ "uart0_ref", "uart1_ref", "spi0_ref",
+ "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
+ "can0_ref", "can1_ref", "can0", "can1",
+ "dll_ref", "adma_ref", "timestamp_ref",
+ "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt";
+ };
+
+ dp_aclk: dp_aclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-accuracy = <100>;
+ };
+};
+
+&can0 {
+ clocks = <&clkc 63>, <&clkc 31>;
+};
+
+&can1 {
+ clocks = <&clkc 64>, <&clkc 31>;
+};
+
+&cpu0 {
+ clocks = <&clkc 10>;
+};
+
+&fpd_dma_chan1 {
+ clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan2 {
+ clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan3 {
+ clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan4 {
+ clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan5 {
+ clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan6 {
+ clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan7 {
+ clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan8 {
+ clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&gpu {
+ clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>;
+};
+
+&lpd_dma_chan1 {
+ clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan2 {
+ clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan3 {
+ clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan4 {
+ clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan5 {
+ clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan6 {
+ clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan7 {
+ clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan8 {
+ clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&nand0 {
+ clocks = <&clkc 60>, <&clkc 31>;
+};
+
+&gem0 {
+ clocks = <&clkc 31>, <&clkc 49>, <&clkc 45>, <&clkc 49>, <&clkc 44>;
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem1 {
+ clocks = <&clkc 31>, <&clkc 50>, <&clkc 46>, <&clkc 50>, <&clkc 44>;
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem2 {
+ clocks = <&clkc 31>, <&clkc 51>, <&clkc 47>, <&clkc 51>, <&clkc 44>;
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem3 {
+ clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>, <&clkc 44>;
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gpio {
+ clocks = <&clkc 31>;
+};
+
+&i2c0 {
+ clocks = <&clkc 61>;
+};
+
+&i2c1 {
+ clocks = <&clkc 62>;
+};
+
+&pcie {
+ clocks = <&clkc 23>;
+};
+
+&qspi {
+ clocks = <&clkc 53>, <&clkc 31>;
+};
+
+&sata {
+ clocks = <&clkc 22>;
+};
+
+&sdhci0 {
+ clocks = <&clkc 54>, <&clkc 31>;
+};
+
+&sdhci1 {
+ clocks = <&clkc 55>, <&clkc 31>;
+};
+
+&spi0 {
+ clocks = <&clkc 58>, <&clkc 31>;
+};
+
+&spi1 {
+ clocks = <&clkc 59>, <&clkc 31>;
+};
+
+&uart0 {
+ clocks = <&clkc 56>, <&clkc 31>;
+};
+
+&uart1 {
+ clocks = <&clkc 57>, <&clkc 31>;
+};
+
+&usb0 {
+ clocks = <&clkc 32>, <&clkc 34>;
+};
+
+&usb1 {
+ clocks = <&clkc 33>, <&clkc 34>;
+};
+
+&watchdog0 {
+ clocks = <&clkc 75>;
+};
+
+&xilinx_ams {
+ clocks = <&clkc 70>;
+};
+
+&xilinx_drm {
+ clocks = <&clkc 16>;
+};
+
+&xlnx_dp {
+ clocks = <&dp_aclk>, <&clkc 17>;
+};
+
+&xlnx_dpdma {
+ clocks = <&clkc 20>;
+};
+
+&xlnx_dp_snd_codec0 {
+ clocks = <&clkc 17>;
+};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 04d82c4d2e..9062ffe919 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm015-dc1 RevA";
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 7dfe960135..bf43bf8748 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm016-dc2 RevA";
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index 648e3ba799..39c82c592f 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm018-dc4";
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index f3020a5760..c774b866fb 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -12,7 +12,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm019-dc5 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 64a883b96e..2be6eb0eb5 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 7da0ca8789..9addd427e7 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -45,6 +45,7 @@ CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 3e531661eb..4f4d670477 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -44,6 +44,7 @@ CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index 9bc0b77c2c..409ec35b6d 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -34,6 +34,7 @@ CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index ac565ecf8f..34d74cbdfe 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -34,6 +34,7 @@ CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index 1df5b0b5c6..867d8337f6 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -48,6 +48,7 @@ CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index c8a8362148..db46d013ed 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -48,6 +48,7 @@ CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 8f85b5f675..e551e44f2e 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -48,6 +48,7 @@ CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-01 06:58:38 +0000