diff options
| -rw-r--r-- | board/nvidia/common/emc.c | 242 |
1 files changed, 17 insertions, 225 deletions
diff --git a/board/nvidia/common/emc.c b/board/nvidia/common/emc.c index db579c4890..07fda2b5a1 100644 --- a/board/nvidia/common/emc.c +++ b/board/nvidia/common/emc.c @@ -381,110 +381,6 @@ void seaboard_emc_init(void) } } -static const struct tegra_emc_table kaen_emc_tables_Nanya_333Mhz[] = { - { - .rate = 166500, /* SDRAM frequency */ - .regs = { - 0x0000000a, /* RC */ - 0x00000016, /* RFC */ - 0x00000008, /* RAS */ - 0x00000003, /* RP */ - 0x00000004, /* R2W */ - 0x00000004, /* W2R */ - 0x00000002, /* R2P */ - 0x0000000a, /* W2P */ - 0x00000003, /* RD_RCD */ - 0x00000003, /* WR_RCD */ - 0x00000002, /* RRD */ - 0x00000001, /* REXT */ - 0x00000003, /* WDV */ - 0x00000004, /* QUSE */ - 0x00000003, /* QRST */ - 0x00000009, /* QSAFE */ - 0x0000000c, /* RDV */ - 0x000004df, /* REFRESH */ - 0x00000000, /* BURST_REFRESH_NUM */ - 0x00000003, /* PDEX2WR */ - 0x00000003, /* PDEX2RD */ - 0x00000003, /* PCHG2PDEN */ - 0x00000003, /* ACT2PDEN */ - 0x00000001, /* AR2PDEN */ - 0x00000009, /* RW2PDEN */ - 0x000000c8, /* TXSR */ - 0x00000003, /* TCKE */ - 0x00000007, /* TFAW */ - 0x00000004, /* TRPAB */ - 0x00000006, /* TCLKSTABLE */ - 0x00000002, /* TCLKSTOP */ - 0x00000000, /* TREFBW */ - 0x00000000, /* QUSE_EXTRA */ - 0x00000003, /* FBIO_CFG6 */ - 0x00000000, /* ODT_WRITE */ - 0x00000000, /* ODT_READ */ - 0x00000083, /* FBIO_CFG5 */ - 0xa06e04ae, /* CFG_DIG_DLL */ - 0x007e2010, /* DLL_XFORM_DQS */ - 0x00000000, /* DLL_XFORM_QUSE */ - 0x00000000, /* ZCAL_REF_CNT */ - 0x00000000, /* ZCAL_WAIT_CNT */ - 0x00000000, /* AUTO_CAL_INTERVAL */ - 0x00000000, /* CFG_CLKTRIM_0 */ - 0x00000000, /* CFG_CLKTRIM_1 */ - 0x00000000, /* CFG_CLKTRIM_2 */ - } - }, { - .rate = 333000, /* SDRAM frequency */ - .regs = { - 0x00000014, /* RC */ - 0x0000002b, /* RFC */ - 0x0000000f, /* RAS */ - 0x00000005, /* RP */ - 0x00000004, /* R2W */ - 0x00000005, /* W2R */ - 0x00000003, /* R2P */ - 0x0000000a, /* W2P */ - 0x00000005, /* RD_RCD */ - 0x00000005, /* WR_RCD */ - 0x00000003, /* RRD */ - 0x00000001, /* REXT */ - 0x00000003, /* WDV */ - 0x00000004, /* QUSE */ - 0x00000003, /* QRST */ - 0x00000009, /* QSAFE */ - 0x0000000c, /* RDV */ - 0x000009ff, /* REFRESH */ - 0x00000000, /* BURST_REFRESH_NUM */ - 0x00000003, /* PDEX2WR */ - 0x00000003, /* PDEX2RD */ - 0x00000005, /* PCHG2PDEN */ - 0x00000005, /* ACT2PDEN */ - 0x00000001, /* AR2PDEN */ - 0x0000000e, /* RW2PDEN */ - 0x000000c8, /* TXSR */ - 0x00000003, /* TCKE */ - 0x0000000d, /* TFAW */ - 0x00000006, /* TRPAB */ - 0x00000006, /* TCLKSTABLE */ - 0x00000002, /* TCLKSTOP */ - 0x00000000, /* TREFBW */ - 0x00000000, /* QUSE_EXTRA */ - 0x00000003, /* FBIO_CFG6 */ - 0x00000000, /* ODT_WRITE */ - 0x00000000, /* ODT_READ */ - 0x00000083, /* FBIO_CFG5 */ - 0xe04e048b, /* CFG_DIG_DLL */ - 0x007e2010, /* DLL_XFORM_DQS */ - 0x007f8417, /* DLL_XFORM_QUSE */ - 0x00000000, /* ZCAL_REF_CNT */ - 0x00000000, /* ZCAL_WAIT_CNT */ - 0x00000000, /* AUTO_CAL_INTERVAL */ - 0x00000000, /* CFG_CLKTRIM_0 */ - 0x00000000, /* CFG_CLKTRIM_1 */ - 0x00000000, /* CFG_CLKTRIM_2 */ - } - } -}; - static const struct tegra_emc_table kaen_emc_tables_Nanya_380Mhz[] = { { .rate = 190000, /* SDRAM frequency */ @@ -527,7 +423,7 @@ static const struct tegra_emc_table kaen_emc_tables_Nanya_380Mhz[] = { 0x00000000, /* ODT_READ */ 0x00000083, /* FBIO_CFG5 */ 0xa06204ae, /* CFG_DIG_DLL */ - 0x007fd010, /* DLL_XFORM_DQS */ + 0x007da010, /* DLL_XFORM_DQS */ 0x00000000, /* DLL_XFORM_QUSE */ 0x00000000, /* ZCAL_REF_CNT */ 0x00000000, /* ZCAL_WAIT_CNT */ @@ -542,7 +438,7 @@ static const struct tegra_emc_table kaen_emc_tables_Nanya_380Mhz[] = { 0x00000016, /* RC */ 0x00000031, /* RFC */ 0x00000012, /* RAS */ - 0x00000006, /* RP */ + 0x00000005, /* RP */ 0x00000004, /* R2W */ 0x00000005, /* W2R */ 0x00000003, /* R2P */ @@ -560,129 +456,25 @@ static const struct tegra_emc_table kaen_emc_tables_Nanya_380Mhz[] = { 0x00000000, /* BURST_REFRESH_NUM */ 0x00000003, /* PDEX2WR */ 0x00000003, /* PDEX2RD */ - 0x00000006, /* PCHG2PDEN */ - 0x00000005, /* ACT2PDEN */ - 0x00000001, /* AR2PDEN */ - 0x00000010, /* RW2PDEN */ - 0x000000c8, /* TXSR */ - 0x00000003, /* TCKE */ - 0x0000000e, /* TFAW */ - 0x00000007, /* TRPAB */ - 0x00000008, /* TCLKSTABLE */ - 0x00000002, /* TCLKSTOP */ - 0x00000000, /* TREFBW */ - 0x00000004, /* QUSE_EXTRA */ - 0x00000002, /* FBIO_CFG6 */ - 0x00000000, /* ODT_WRITE */ - 0x00000000, /* ODT_READ */ - 0x00000083, /* FBIO_CFG5 */ - 0xe044048b, /* CFG_DIG_DLL */ - 0x007e4010, /* DLL_XFORM_DQS */ - 0x00016617, /* DLL_XFORM_QUSE */ - 0x00000000, /* ZCAL_REF_CNT */ - 0x00000000, /* ZCAL_WAIT_CNT */ - 0x00000000, /* AUTO_CAL_INTERVAL */ - 0x00000000, /* CFG_CLKTRIM_0 */ - 0x00000000, /* CFG_CLKTRIM_1 */ - 0x00000000, /* CFG_CLKTRIM_2 */ - } - } -}; - -static const struct tegra_emc_table kaen_emc_tables_Samsung_333Mhz[] = { - { - .rate = 166500, /* SDRAM frequency */ - .regs = { - 0x0000000a, /* RC */ - 0x00000016, /* RFC */ - 0x00000008, /* RAS */ - 0x00000003, /* RP */ - 0x00000004, /* R2W */ - 0x00000004, /* W2R */ - 0x00000002, /* R2P */ - 0x0000000c, /* W2P */ - 0x00000003, /* RD_RCD */ - 0x00000003, /* WR_RCD */ - 0x00000002, /* RRD */ - 0x00000001, /* REXT */ - 0x00000004, /* WDV */ - 0x00000005, /* QUSE */ - 0x00000004, /* QRST */ - 0x00000009, /* QSAFE */ - 0x0000000d, /* RDV */ - 0x000004df, /* REFRESH */ - 0x00000000, /* BURST_REFRESH_NUM */ - 0x00000003, /* PDEX2WR */ - 0x00000003, /* PDEX2RD */ - 0x00000003, /* PCHG2PDEN */ - 0x00000003, /* ACT2PDEN */ - 0x00000001, /* AR2PDEN */ - 0x0000000a, /* RW2PDEN */ - 0x000000c8, /* TXSR */ - 0x00000003, /* TCKE */ - 0x00000006, /* TFAW */ - 0x00000004, /* TRPAB */ - 0x00000008, /* TCLKSTABLE */ - 0x00000002, /* TCLKSTOP */ - 0x00000000, /* TREFBW */ - 0x00000000, /* QUSE_EXTRA */ - 0x00000003, /* FBIO_CFG6 */ - 0x00000000, /* ODT_WRITE */ - 0x00000000, /* ODT_READ */ - 0x00000083, /* FBIO_CFG5 */ - 0xa06e04ae, /* CFG_DIG_DLL */ - 0x007e2010, /* DLL_XFORM_DQS */ - 0x00000000, /* DLL_XFORM_QUSE */ - 0x00000000, /* ZCAL_REF_CNT */ - 0x00000000, /* ZCAL_WAIT_CNT */ - 0x00000000, /* AUTO_CAL_INTERVAL */ - 0x00000000, /* CFG_CLKTRIM_0 */ - 0x00000000, /* CFG_CLKTRIM_1 */ - 0x00000000, /* CFG_CLKTRIM_2 */ - } - }, { - .rate = 333000, /* SDRAM frequency */ - .regs = { - 0x00000014, /* RC */ - 0x0000002b, /* RFC */ - 0x0000000f, /* RAS */ - 0x00000005, /* RP */ - 0x00000004, /* R2W */ - 0x00000005, /* W2R */ - 0x00000003, /* R2P */ - 0x0000000c, /* W2P */ - 0x00000005, /* RD_RCD */ - 0x00000005, /* WR_RCD */ - 0x00000003, /* RRD */ - 0x00000001, /* REXT */ - 0x00000004, /* WDV */ - 0x00000005, /* QUSE */ - 0x00000004, /* QRST */ - 0x00000009, /* QSAFE */ - 0x0000000d, /* RDV */ - 0x000009ff, /* REFRESH */ - 0x00000000, /* BURST_REFRESH_NUM */ - 0x00000003, /* PDEX2WR */ - 0x00000003, /* PDEX2RD */ 0x00000005, /* PCHG2PDEN */ 0x00000005, /* ACT2PDEN */ 0x00000001, /* AR2PDEN */ 0x0000000f, /* RW2PDEN */ 0x000000c8, /* TXSR */ 0x00000003, /* TCKE */ - 0x0000000c, /* TFAW */ + 0x0000000e, /* TFAW */ 0x00000006, /* TRPAB */ 0x00000008, /* TCLKSTABLE */ 0x00000002, /* TCLKSTOP */ 0x00000000, /* TREFBW */ 0x00000000, /* QUSE_EXTRA */ - 0x00000002, /* FBIO_CFG6 */ + 0x00000003, /* FBIO_CFG6 */ 0x00000000, /* ODT_WRITE */ 0x00000000, /* ODT_READ */ 0x00000083, /* FBIO_CFG5 */ - 0xe04e048b, /* CFG_DIG_DLL */ - 0x007de010, /* DLL_XFORM_DQS */ - 0x00022015, /* DLL_XFORM_QUSE */ + 0xe044048b, /* CFG_DIG_DLL */ + 0x007da010, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ 0x00000000, /* ZCAL_REF_CNT */ 0x00000000, /* ZCAL_WAIT_CNT */ 0x00000000, /* AUTO_CAL_INTERVAL */ @@ -735,7 +527,7 @@ static const struct tegra_emc_table kaen_emc_tables_Samsung_380Mhz[] = { 0x00000000, /* ODT_READ */ 0x00000083, /* FBIO_CFG5 */ 0xa06204ae, /* CFG_DIG_DLL */ - 0x007e0010, /* DLL_XFORM_DQS */ + 0x007e2010, /* DLL_XFORM_DQS */ 0x00000000, /* DLL_XFORM_QUSE */ 0x00000000, /* ZCAL_REF_CNT */ 0x00000000, /* ZCAL_WAIT_CNT */ @@ -780,13 +572,13 @@ static const struct tegra_emc_table kaen_emc_tables_Samsung_380Mhz[] = { 0x00000002, /* TCLKSTOP */ 0x00000000, /* TREFBW */ 0x00000000, /* QUSE_EXTRA */ - 0x00000002, /* FBIO_CFG6 */ + 0x00000003, /* FBIO_CFG6 */ 0x00000000, /* ODT_WRITE */ 0x00000000, /* ODT_READ */ 0x00000083, /* FBIO_CFG5 */ 0xe044048b, /* CFG_DIG_DLL */ - 0x007e0010, /* DLL_XFORM_DQS */ - 0x00023215, /* DLL_XFORM_QUSE */ + 0x007de010, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ 0x00000000, /* ZCAL_REF_CNT */ 0x00000000, /* ZCAL_WAIT_CNT */ 0x00000000, /* AUTO_CAL_INTERVAL */ @@ -799,14 +591,14 @@ static const struct tegra_emc_table kaen_emc_tables_Samsung_380Mhz[] = { struct tegra_board_emc_table kaen_emc[] = { { - .table = kaen_emc_tables_Samsung_333Mhz, - .table_size = ARRAY_SIZE(kaen_emc_tables_Samsung_333Mhz), - .name = "Samsung 333MHz", + .table = kaen_emc_tables_Samsung_380Mhz, + .table_size = ARRAY_SIZE(kaen_emc_tables_Samsung_380Mhz), + .name = "Samsung 380MHz", }, { - .table = kaen_emc_tables_Nanya_333Mhz, - .table_size = ARRAY_SIZE(kaen_emc_tables_Nanya_333Mhz), - .name = "Nanya 333MHz", + .table = kaen_emc_tables_Nanya_380Mhz, + .table_size = ARRAY_SIZE(kaen_emc_tables_Nanya_380Mhz), + .name = "Nanya 380MHz", }, { .table = kaen_emc_tables_Samsung_380Mhz, |