diff options
71 files changed, 3340 insertions, 66 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 397981a40c..4a62d4b108 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -840,15 +840,12 @@ config STM32 config ARCH_ROCKCHIP bool "Support Rockchip SoCs" - select SUPPORT_SPL - select SPL select OF_CONTROL - select CPU_V7 select BLK select DM - select SPL_DM + select SPL_DM if SPL select SYS_MALLOC_F - select SPL_SYS_MALLOC_SIMPLE + select SPL_SYS_MALLOC_SIMPLE if SPL select DM_GPIO select DM_I2C select DM_MMC diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ca8712a7a7..c97e3f6bc7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -31,7 +31,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-firefly.dtb \ rk3288-jerry.dtb \ rk3288-rock2-square.dtb \ - rk3036-sdk.dtb + rk3288-evb.dtb \ + rk3036-sdk.dtb \ + rk3399-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-odroidc2.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ diff --git a/arch/arm/dts/rk3288-evb.dts b/arch/arm/dts/rk3288-evb.dts new file mode 100644 index 0000000000..caf24ee8ad --- /dev/null +++ b/arch/arm/dts/rk3288-evb.dts @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +#include "rk3288-evb.dtsi" + +/ { + model = "Evb-RK3288"; + compatible = "evb-rk3288,evb-rk3288", "rockchip,rk3288"; + + chosen { + stdout-path = &uart2; + }; +}; + +&dmc { + rockchip,num-channels = <2>; + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x2>; + rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x2 0x0 0xe 0xe>; + rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&pwm1 { + status = "okay"; +}; + +&uart2 { + u-boot,dm-pre-reloc; + reg-shift = <2>; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio8 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-evb.dtsi b/arch/arm/dts/rk3288-evb.dtsi new file mode 100644 index 0000000000..cb7d03e558 --- /dev/null +++ b/arch/arm/dts/rk3288-evb.dtsi @@ -0,0 +1,379 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +#include "rk3288.dtsi" + +/ { + memory { + reg = <0 0x80000000>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@0 { + gpio-key,wakeup = <1>; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = <116>; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + }; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_flash: flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_5v: usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_host_5v: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_5v>; + }; + + vcc_otg_5v: usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_5v>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_flash>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + fcs,suspend-voltage-selector = <1>; + reg = <0x40>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + fcs,suspend-voltage-selector = <1>; + reg = <0x41>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + interrupt-parent = <&gpio7>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + }; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_hold>; + system-power-controller; + + regulators { + vcc_ddr: REG1 { + regulator-name = "vcc_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_io: REG2 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "vcc_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd10_lcd: REG6 { + regulator-name = "vdd10_lcd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcca_codec: REG7 { + regulator-name = "vcca_codec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_tp: REG8 { + regulator-name = "vcca_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccio_pmu: REG9 { + regulator-name = "vccio_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_10: REG10 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc18_lcd: REG12 { + regulator-name = "vcc18_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + act8846 { + pwr_hold: pwr-hold { + rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&sdio0 { + broken-cd; + bus-width = <4>; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>; + vmmc-supply = <&vcc_18>; + status = "disabled"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + vmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 3dab0fc83e..bcf051a9d9 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -454,6 +454,7 @@ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_OTG0>; clock-names = "otg"; + dr_mode = "otg"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts new file mode 100644 index 0000000000..bbcfcd0da9 --- /dev/null +++ b/arch/arm/dts/rk3399-evb.dts @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include <dt-bindings/pwm/pwm.h> +#include "rk3399.dtsi" + +/ { + model = "Rockchip RK3399 Evaluation Board"; + compatible = "rockchip,rk3399-evb", "rockchip,rk3399", + "google,rk3399evb-rev2"; + + chosen { + stdout-path = &uart2; + }; + + vdd_center: vdd-center { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 25000 0>; + regulator-name = "vdd_center"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + status = "okay"; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&emmc_phy { + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 21 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pmic_dvs2: pmic-dvs2 { + rockchip,pins = + <1 18 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi new file mode 100644 index 0000000000..fb5af54799 --- /dev/null +++ b/arch/arm/dts/rk3399.dtsi @@ -0,0 +1,1028 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/clock/rk3399-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/rockchip.h> + +/ { + compatible = "rockchip,rk3399"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_l0>; + }; + core1 { + cpu = <&cpu_l1>; + }; + core2 { + cpu = <&cpu_l2>; + }; + core3 { + cpu = <&cpu_l3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_b0>; + }; + core1 { + cpu = <&cpu_b1>; + }; + }; + }; + + cpu_l0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ + clocks = <&cru ARMCLKL>; + }; + + cpu_l1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + clocks = <&cru ARMCLKL>; + }; + + cpu_l2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + clocks = <&cru ARMCLKL>; + }; + + cpu_l3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + clocks = <&cru ARMCLKL>; + }; + + cpu_b0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ + clocks = <&cru ARMCLKB>; + }; + + cpu_b1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + clocks = <&cru ARMCLKB>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dmac_bus: dma-controller@ff6d0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff6d0000 0x0 0x4000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC0_PERILP>; + clock-names = "apb_pclk"; + }; + + dmac_peri: dma-controller@ff6e0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff6e0000 0x0 0x4000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC1_PERILP>; + clock-names = "apb_pclk"; + }; + }; + + sdio0: dwmmc@fe310000 { + compatible = "rockchip,rk3399-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe310000 0x0 0x4000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + status = "disabled"; + }; + + sdmmc: dwmmc@fe320000 { + compatible = "rockchip,rk3399-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe320000 0x0 0x4000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + status = "disabled"; + }; + + sdhci: sdhci@fe330000 { + compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; + reg = <0x0 0xfe330000 0x0 0x10000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru SCLK_EMMC>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; + clock-names = "clk_xin", "clk_ahb"; + phys = <&emmc_phy>; + phy-names = "phy_arasan"; + status = "disabled"; + }; + + usb_host0_ehci: usb@fe380000 { + compatible = "generic-ehci"; + reg = <0x0 0xfe380000 0x0 0x20000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; + clock-names = "hclk_host0", "hclk_host0_arb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@fe3a0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfe3a0000 0x0 0x20000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; + clock-names = "hclk_host0", "hclk_host0_arb"; + status = "disabled"; + }; + + usb_host1_ehci: usb@fe3c0000 { + compatible = "generic-ehci"; + reg = <0x0 0xfe3c0000 0x0 0x20000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; + clock-names = "hclk_host1", "hclk_host1_arb"; + status = "disabled"; + }; + + usb_host1_ohci: usb@fe3e0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfe3e0000 0x0 0x20000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; + clock-names = "hclk_host1", "hclk_host1_arb"; + status = "disabled"; + }; + + gic: interrupt-controller@fee00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + + reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ + <0x0 0xfef00000 0 0xc0000>, /* GICR */ + <0x0 0xfff00000 0 0x10000>, /* GICC */ + <0x0 0xfff10000 0 0x10000>, /* GICH */ + <0x0 0xfff20000 0 0x10000>; /* GICV */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + its: interrupt-controller@fee20000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xfee20000 0x0 0x20000>; + }; + }; + + uart0: serial@ff180000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff180000 0x0 0x100>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "disabled"; + }; + + uart1: serial@ff190000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff190000 0x0 0x100>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "disabled"; + }; + + uart2: serial@ff1a0000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1a0000 0x0 0x100>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; + status = "disabled"; + }; + + uart3: serial@ff1b0000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1b0000 0x0 0x100>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; + status = "disabled"; + }; + + spi0: spi@ff1c0000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff1c0000 0x0 0x1000>; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@ff1d0000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff1d0000 0x0 0x1000>; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@ff1e0000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff1e0000 0x0 0x1000>; + clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@ff1f0000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff1f0000 0x0 0x1000>; + clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@ff200000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff200000 0x0 0x1000>; + clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pmugrf: syscon@ff320000 { + compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xff320000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rk3399-pmu-io-voltage-domain"; + status = "disabled"; + }; + }; + + spi3: spi@ff350000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff350000 0x0 0x1000>; + clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart4: serial@ff370000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff370000 0x0 0x100>; + clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + status = "disabled"; + }; + + pwm0: pwm@ff420000 { + compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff420000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&pmucru PCLK_RKPWM_PMU>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm1: pwm@ff420010 { + compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff420010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&pmucru PCLK_RKPWM_PMU>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm2: pwm@ff420020 { + compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff420020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&pmucru PCLK_RKPWM_PMU>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm3: pwm@ff420030 { + compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff420030 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3a_pin>; + clocks = <&pmucru PCLK_RKPWM_PMU>; + clock-names = "pwm"; + status = "disabled"; + }; + + pmucru: pmu-clock-controller@ff750000 { + compatible = "rockchip,rk3399-pmucru"; + reg = <0x0 0xff750000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&pmucru PLL_PPLL>; + assigned-clock-rates = <676000000>; + }; + + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3399-cru"; + reg = <0x0 0xff760000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, + <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, + <&cru PCLK_PERIHP>, + <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, + <&cru PCLK_PERILP0>, + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; + assigned-clock-rates = + <594000000>, <800000000>, + <1000000000>, + <150000000>, <75000000>, + <37500000>, + <100000000>, <100000000>, + <50000000>, + <100000000>, <50000000>; + }; + + grf: syscon@ff770000 { + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff770000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + io_domains: io-domains { + compatible = "rockchip,rk3399-io-voltage-domain"; + status = "disabled"; + }; + + emmc_phy: phy@f780 { + compatible = "rockchip,rk3399-emmc-phy"; + reg = <0xf780 0x24>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + watchdog@ff840000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xff840000 0x0 0x100>; + clocks = <&cru PCLK_WDT>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + }; + + spdif: spdif@ff870000 { + compatible = "rockchip,rk3399-spdif"; + reg = <0x0 0xff870000 0x0 0x1000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac_bus 7>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_bus>; + status = "disabled"; + }; + + i2s0: i2s@ff880000 { + compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff880000 0x0 0x1000>; + rockchip,grf = <&grf>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac_bus 0>, <&dmac_bus 1>; + dma-names = "tx", "rx"; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_8ch_bus>; + status = "disabled"; + }; + + i2s1: i2s@ff890000 { + compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff890000 0x0 0x1000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac_bus 2>, <&dmac_bus 3>; + dma-names = "tx", "rx"; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_bus>; + status = "disabled"; + }; + + i2s2: i2s@ff8a0000 { + compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff8a0000 0x0 0x1000>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac_bus 4>, <&dmac_bus 5>; + dma-names = "tx", "rx"; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3399-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio0@ff720000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff720000 0x0 0x100>; + clocks = <&pmucru PCLK_GPIO0_PMU>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio1: gpio1@ff730000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff730000 0x0 0x100>; + clocks = <&pmucru PCLK_GPIO1_PMU>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio2: gpio2@ff780000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff780000 0x0 0x100>; + clocks = <&cru PCLK_GPIO2>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio3: gpio3@ff788000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff788000 0x0 0x100>; + clocks = <&cru PCLK_GPIO3>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio4: gpio4@ff790000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff790000 0x0 0x100>; + clocks = <&cru PCLK_GPIO4>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_12ma: pcfg-pull-none-12ma { + bias-disable; + drive-strength = <12>; + }; + + pcfg_pull_up_8ma: pcfg-pull-up-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_down_4ma: pcfg-pull-down-4ma { + bias-pull-down; + drive-strength = <4>; + }; + + pcfg_pull_up_2ma: pcfg-pull-up-2ma { + bias-pull-up; + drive-strength = <2>; + }; + + pcfg_pull_down_12ma: pcfg-pull-down-12ma { + bias-pull-down; + drive-strength = <12>; + }; + + pcfg_pull_none_13ma: pcfg-pull-none-13ma { + bias-disable; + drive-strength = <13>; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = + <1 15 RK_FUNC_2 &pcfg_pull_none>, + <1 16 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = + <4 2 RK_FUNC_1 &pcfg_pull_none>, + <4 1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = + <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, + <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = + <4 17 RK_FUNC_1 &pcfg_pull_none>, + <4 16 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = + <1 12 RK_FUNC_1 &pcfg_pull_none>, + <1 11 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c5 { + i2c5_xfer: i2c5-xfer { + rockchip,pins = + <3 11 RK_FUNC_2 &pcfg_pull_none>, + <3 10 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c6 { + i2c6_xfer: i2c6-xfer { + rockchip,pins = + <2 10 RK_FUNC_2 &pcfg_pull_none>, + <2 9 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c7 { + i2c7_xfer: i2c7-xfer { + rockchip,pins = + <2 8 RK_FUNC_2 &pcfg_pull_none>, + <2 7 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c8 { + i2c8_xfer: i2c8-xfer { + rockchip,pins = + <1 21 RK_FUNC_1 &pcfg_pull_none>, + <1 20 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2s0 { + i2s0_8ch_bus: i2s0-8ch-bus { + rockchip,pins = + <3 24 RK_FUNC_1 &pcfg_pull_none>, + <3 25 RK_FUNC_1 &pcfg_pull_none>, + <3 26 RK_FUNC_1 &pcfg_pull_none>, + <3 27 RK_FUNC_1 &pcfg_pull_none>, + <3 28 RK_FUNC_1 &pcfg_pull_none>, + <3 29 RK_FUNC_1 &pcfg_pull_none>, + <3 30 RK_FUNC_1 &pcfg_pull_none>, + <3 31 RK_FUNC_1 &pcfg_pull_none>, + <4 0 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2s1 { + i2s1_2ch_bus: i2s1-2ch-bus { + rockchip,pins = + <4 3 RK_FUNC_1 &pcfg_pull_none>, + <4 4 RK_FUNC_1 &pcfg_pull_none>, + <4 5 RK_FUNC_1 &pcfg_pull_none>, + <4 6 RK_FUNC_1 &pcfg_pull_none>, + <4 7 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + spdif { + spdif_bus: spdif-bus { + rockchip,pins = + <4 21 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = + <3 6 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = + <3 7 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = + <3 8 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = + <3 5 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = + <3 4 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = + <1 9 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = + <1 10 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = + <1 7 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = + <1 8 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spi2 { + spi2_clk: spi2-clk { + rockchip,pins = + <2 11 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_cs0: spi2-cs0 { + rockchip,pins = + <2 12 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_rx: spi2-rx { + rockchip,pins = + <2 9 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_tx: spi2-tx { + rockchip,pins = + <2 10 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + spi3 { + spi3_clk: spi3-clk { + rockchip,pins = + <1 17 RK_FUNC_1 &pcfg_pull_up>; + }; + spi3_cs0: spi3-cs0 { + rockchip,pins = + <1 18 RK_FUNC_1 &pcfg_pull_up>; + }; + spi3_rx: spi3-rx { + rockchip,pins = + <1 15 RK_FUNC_1 &pcfg_pull_up>; + }; + spi3_tx: spi3-tx { + rockchip,pins = + <1 16 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + spi4 { + spi4_clk: spi4-clk { + rockchip,pins = + <3 2 RK_FUNC_2 &pcfg_pull_up>; + }; + spi4_cs0: spi4-cs0 { + rockchip,pins = + <3 3 RK_FUNC_2 &pcfg_pull_up>; + }; + spi4_rx: spi4-rx { + rockchip,pins = + <3 0 RK_FUNC_2 &pcfg_pull_up>; + }; + spi4_tx: spi4-tx { + rockchip,pins = + <3 1 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spi5 { + spi5_clk: spi5-clk { + rockchip,pins = + <2 22 RK_FUNC_2 &pcfg_pull_up>; + }; + spi5_cs0: spi5-cs0 { + rockchip,pins = + <2 23 RK_FUNC_2 &pcfg_pull_up>; + }; + spi5_rx: spi5-rx { + rockchip,pins = + <2 20 RK_FUNC_2 &pcfg_pull_up>; + }; + spi5_tx: spi5-tx { + rockchip,pins = + <2 21 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = + <2 16 RK_FUNC_1 &pcfg_pull_up>, + <2 17 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = + <2 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = + <2 19 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = + <3 12 RK_FUNC_2 &pcfg_pull_up>, + <3 13 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart2a { + uart2a_xfer: uart2a-xfer { + rockchip,pins = + <4 8 RK_FUNC_2 &pcfg_pull_up>, + <4 9 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart2b { + uart2b_xfer: uart2b-xfer { + rockchip,pins = + <4 16 RK_FUNC_2 &pcfg_pull_up>, + <4 17 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart2c { + uart2c_xfer: uart2c-xfer { + rockchip,pins = + <4 19 RK_FUNC_1 &pcfg_pull_up>, + <4 20 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = + <3 14 RK_FUNC_2 &pcfg_pull_up>, + <3 15 RK_FUNC_2 &pcfg_pull_none>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = + <3 18 RK_FUNC_2 &pcfg_pull_none>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = + <3 19 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart4 { + uart4_xfer: uart4-xfer { + rockchip,pins = + <1 7 RK_FUNC_1 &pcfg_pull_up>, + <1 8 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uarthdcp { + uarthdcp_xfer: uarthdcp-xfer { + rockchip,pins = + <4 21 RK_FUNC_2 &pcfg_pull_up>, + <4 22 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = + <4 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + vop0_pwm_pin: vop0-pwm-pin { + rockchip,pins = + <4 18 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = + <4 22 RK_FUNC_1 &pcfg_pull_none>; + }; + + vop1_pwm_pin: vop1-pwm-pin { + rockchip,pins = + <4 18 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = + <1 19 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm3a { + pwm3a_pin: pwm3a-pin { + rockchip,pins = + <0 6 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm3b { + pwm3b_pin: pwm3b-pin { + rockchip,pins = + <1 14 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; +}; diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 317e5128ed..21edbc2f89 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -65,6 +65,8 @@ void *rockchip_get_cru(void); struct rk3288_cru; struct rk3288_grf; -void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); +void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); + +int rockchip_get_clk(struct udevice **devp); #endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c49cc19be3..1aac3c85ba 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -1,7 +1,21 @@ if ARCH_ROCKCHIP +config ROCKCHIP_RK3036 + bool "Support Rockchip RK3036" + select CPU_V7 + select SUPPORT_SPL + select SPL + help + The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 + including NEON and GPU, Mali-400 graphics, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. + config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" + select CPU_V7 + select SUPPORT_SPL + select SPL help The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two @@ -9,14 +23,26 @@ config ROCKCHIP_RK3288 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs. -config ROCKCHIP_RK3036 - bool "Support Rockchip RK3036" +config ROCKCHIP_RK3399 + bool "Support Rockchip RK3399" + select ARM64 help - The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 - including NEON and GPU, Mali-400 graphics, several DDR3 options + The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 + and quad-core Cortex-A53. + including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two + video interfaces supporting HDMI and eDP, several DDR3 options and video codec support. Peripherals include Gigabit Ethernet, - USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. + USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. + +config ROCKCHIP_SPL_BACK_TO_BROM + bool "SPL returns to bootrom" + default y if ROCKCHIP_RK3036 + help + Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, + SPL will return to the boot rom, which will then load the U-Boot + binary to keep going on. -source "arch/arm/mach-rockchip/rk3288/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" +source "arch/arm/mach-rockchip/rk3288/Kconfig" +source "arch/arm/mach-rockchip/rk3399/Kconfig" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 55567cb131..157d42fe96 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -5,11 +5,15 @@ # ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o +obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-$(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) += save_boot_param.o else obj-$(CONFIG_ROCKCHIP_RK3288) += board.o endif +ifndef CONFIG_ARM64 obj-y += rk_timer.o -obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ +endif obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ +obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 816540e582..bec756d7ac 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -10,12 +10,45 @@ #include <ram.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/periph.h> +#include <asm/gpio.h> +#include <dm/pinctrl.h> DECLARE_GLOBAL_DATA_PTR; int board_init(void) { +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM + struct udevice *pinctrl; + int ret; + + /* + * We need to implement sdcard iomux here for the further + * initlization, otherwise, it'll hit sdcard command sending + * timeout exception. + */ + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + goto err; + } + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); + if (ret) { + debug("%s: Failed to set up SD card\n", __func__); + goto err; + } + + return 0; +err: + printf("board_init: Error %d\n", ret); + + /* No way to report error here */ + hang(); + + return -1; +#else return 0; +#endif } int dram_init(void) @@ -52,6 +85,78 @@ void lowlevel_init(void) { } +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#include <usb.h> +#include <usb/dwc2_udc.h> + +static struct dwc2_plat_otg_data rk3288_otg_data = { + .rx_fifo_sz = 512, + .np_tx_fifo_sz = 16, + .tx_fifo_sz = 128, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + int node, phy_node; + const char *mode; + bool matched = false; + const void *blob = gd->fdt_blob; + u32 grf_phy_offset; + + /* find the usb_otg node */ + node = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3288-usb"); + + while (node > 0) { + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode && strcmp(mode, "otg") == 0) { + matched = true; + break; + } + + node = fdt_node_offset_by_compatible(blob, node, + "rockchip,rk3288-usb"); + } + if (!matched) { + debug("Not found usb_otg device\n"); + return -ENODEV; + } + rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); + + node = fdtdec_lookup_phandle(blob, node, "phys"); + if (node <= 0) { + debug("Not found usb phy device\n"); + return -ENODEV; + } + + phy_node = fdt_parent_offset(blob, node); + if (phy_node <= 0) { + debug("Not found usb phy device\n"); + return -ENODEV; + } + + rk3288_otg_data.phy_of_node = phy_node; + grf_phy_offset = fdtdec_get_addr(blob, node, "reg"); + + /* find the grf node */ + node = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3288-grf"); + if (node <= 0) { + debug("Not found grf device\n"); + return -ENODEV; + } + rk3288_otg_data.regs_phy = grf_phy_offset + + fdtdec_get_addr(blob, node, "reg"); + + return dwc2_udc_probe(&rk3288_otg_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + return 0; +} +#endif + static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -73,7 +178,7 @@ static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, int ret, i; struct udevice *dev; - ret = uclass_get_device(UCLASS_CLK, 0, &dev); + ret = rockchip_get_clk(&dev); if (ret) { printf("clk-uclass not found\n"); return 0; diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index cc03808847..f7562bd610 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -15,7 +15,7 @@ config SYS_MALLOC_F_LEN config ROCKCHIP_COMMON bool "Support rk common fuction" -source "board/evb_rk3036/evb_rk3036/Kconfig" -source "board/kylin/kylin_rk3036/Kconfig" +source "board/rockchip/evb_rk3036/Kconfig" +source "board/rockchip/kylin_rk3036/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile index 97d299d6cc..6095777b8f 100644 --- a/arch/arm/mach-rockchip/rk3036/Makefile +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -10,4 +10,3 @@ obj-y += syscon_rk3036.o endif obj-y += sdram_rk3036.o -obj-y += save_boot_param.o diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 123f58b27f..ed14023021 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -149,7 +149,7 @@ static int configure_emmc(struct udevice *pinctrl) return 0; } #endif - +extern void back_to_bootrom(void); void board_init_f(ulong dummy) { struct udevice *pinctrl; @@ -187,7 +187,7 @@ void board_init_f(ulong dummy) rockchip_timer_init(); configure_l2ctlr(); - ret = uclass_get_device(UCLASS_CLK, 0, &dev); + ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return; @@ -204,6 +204,9 @@ void board_init_f(ulong dummy) debug("DRAM init failed: %d\n", ret); return; } +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM + back_to_bootrom(); +#endif } static int setup_led(void) @@ -248,7 +251,8 @@ void spl_board_init(void) } #ifdef CONFIG_SPL_MMC_SUPPORT if (!IS_ENABLED(CONFIG_TARGET_ROCK2) && - !IS_ENABLED(CONFIG_TARGET_FIREFLY_RK3288)) { + !IS_ENABLED(CONFIG_TARGET_FIREFLY_RK3288) && + !IS_ENABLED(CONFIG_TARGET_EVB_RK3288)) { ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); if (ret) { debug("%s: Failed to set up SD card\n", __func__); diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 72156245bd..031dbfc061 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -8,6 +8,14 @@ config TARGET_FIREFLY_RK3288 also includes on-board eMMC and 1GB of SDRAM. Expansion connectors provide access to display pins, I2C, SPI, UART and GPIOs. +config TARGET_EVB_RK3288 + bool "Evb-RK3288" + help + EVB-RK3288 is a RK3288-based development board with 2 USB ports, + HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It + also includes on-board eMMC and 2GB of SDRAM. Expansion connectors + provide access to display pins, I2C, SPI, UART and GPIOs. + config TARGET_CHROMEBOOK_JERRY bool "Google/Rockchip Veyron-Jerry Chromebook" help @@ -45,4 +53,6 @@ source "board/firefly/firefly-rk3288/Kconfig" source "board/radxa/rock2/Kconfig" +source "board/evb-rk3288/evb-rk3288/Kconfig" + endif diff --git a/arch/arm/mach-rockchip/rk3288/Makefile b/arch/arm/mach-rockchip/rk3288/Makefile index 6f62375f46..82b00a1b01 100644 --- a/arch/arm/mach-rockchip/rk3288/Makefile +++ b/arch/arm/mach-rockchip/rk3288/Makefile @@ -4,6 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-y += clk_rk3288.o obj-y += reset_rk3288.o obj-y += sdram_rk3288.o obj-y += syscon_rk3288.o diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c new file mode 100644 index 0000000000..2099e349c1 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk3288_cru), devp); +} diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c index b36b6afcd9..cf9ef2e845 100644 --- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c @@ -575,14 +575,14 @@ static void dram_all_config(const struct dram_info *dram, &sdram_params->ch[chan]; sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); - sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan); + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); - sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0; + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); - sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan); - sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan); + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); } @@ -734,13 +734,13 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu) rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & SYS_REG_RANK_MASK); col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); - bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0; + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK); cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK); - bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) & - SYS_REG_BW_MASK; + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & + SYS_REG_BW_MASK)); row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & SYS_REG_ROW_3_4_MASK; @@ -784,7 +784,7 @@ static int veyron_init(struct dram_info *priv) return ret; udelay(100);/* Must wait for voltage to stabilize, 2mV/us */ - rkclk_configure_cpu(priv->cru, priv->grf); + rk3288_clk_configure_cpu(priv->cru, priv->grf); return 0; } @@ -923,7 +923,7 @@ static int rk3288_dmc_probe(struct udevice *dev) priv->chan[1].pctl = regmap_get_range(plat->map, 2); priv->chan[1].publ = regmap_get_range(plat->map, 3); #endif - ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk); + ret = rockchip_get_clk(&dev_clk); if (ret) return ret; priv->ddr_clk.id = CLK_DDR; diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig new file mode 100644 index 0000000000..83bd04add2 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -0,0 +1,23 @@ +if ROCKCHIP_RK3399 + +choice + prompt "RK3399 board select" + +config TARGET_EVB_RK3399 + bool "RK3399 evaluation board" + help + RK3399evb is a evaluation board for Rockchp rk3399, + with full function and phisical connectors support like type-C ports, + usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial... + +endchoice + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x0800 + +source "board/rockchip/evb_rk3399/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/rk3399/Makefile b/arch/arm/mach-rockchip/rk3399/Makefile new file mode 100644 index 0000000000..3f219ac6f8 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3399/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += rk3399.o diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c new file mode 100644 index 0000000000..b9d7629407 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/armv8/mmu.h> + +static struct mm_region rk3399_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rk3399_mem_map; diff --git a/arch/arm/mach-rockchip/rk3036/save_boot_param.S b/arch/arm/mach-rockchip/save_boot_param.S index 778ec83c2c..85b407b4d3 100644 --- a/arch/arm/mach-rockchip/rk3036/save_boot_param.S +++ b/arch/arm/mach-rockchip/save_boot_param.S @@ -1,5 +1,5 @@ /* - * (C) Copyright 2015 Google, Inc + * (C) Copyright 2016 Rockchip Electronics Co., Ltd * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/board/evb-rk3288/evb-rk3288/Kconfig b/board/evb-rk3288/evb-rk3288/Kconfig new file mode 100644 index 0000000000..b201acb983 --- /dev/null +++ b/board/evb-rk3288/evb-rk3288/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3288 + +config SYS_BOARD + default "evb-rk3288" + +config SYS_VENDOR + default "evb-rk3288" + +config SYS_CONFIG_NAME + default "evb-rk3288" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/evb-rk3288/evb-rk3288/MAINTAINERS b/board/evb-rk3288/evb-rk3288/MAINTAINERS new file mode 100644 index 0000000000..222c254c61 --- /dev/null +++ b/board/evb-rk3288/evb-rk3288/MAINTAINERS @@ -0,0 +1,6 @@ +EVB-RK3288 +M: Lin Huang <hl@rock-chips.com> +S: Maintained +F: board/evb-rk3288/evb-rk3288 +F: include/configs/evb-rk3288.h +F: configs/evb-rk3288_defconfig diff --git a/board/evb-rk3288/evb-rk3288/Makefile b/board/evb-rk3288/evb-rk3288/Makefile new file mode 100644 index 0000000000..c11b657601 --- /dev/null +++ b/board/evb-rk3288/evb-rk3288/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb-rk3288.o diff --git a/board/evb-rk3288/evb-rk3288/evb-rk3288.c b/board/evb-rk3288/evb-rk3288/evb-rk3288.c new file mode 100644 index 0000000000..a82f0ae283 --- /dev/null +++ b/board/evb-rk3288/evb-rk3288/evb-rk3288.c @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> + +void board_boot_order(u32 *spl_boot_list) +{ + /* eMMC prior to sdcard. */ + spl_boot_list[0] = BOOT_DEVICE_MMC2; + spl_boot_list[1] = BOOT_DEVICE_MMC1; +} diff --git a/board/evb_rk3036/evb_rk3036/Kconfig b/board/rockchip/evb_rk3036/Kconfig index ae2a9ebe47..ef45f62925 100644 --- a/board/evb_rk3036/evb_rk3036/Kconfig +++ b/board/rockchip/evb_rk3036/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "evb_rk3036" config SYS_VENDOR - default "evb_rk3036" + default "rockchip" config SYS_CONFIG_NAME default "evb_rk3036" diff --git a/board/evb_rk3036/evb_rk3036/MAINTAINERS b/board/rockchip/evb_rk3036/MAINTAINERS index 152d31ce50..152d31ce50 100644 --- a/board/evb_rk3036/evb_rk3036/MAINTAINERS +++ b/board/rockchip/evb_rk3036/MAINTAINERS diff --git a/board/evb_rk3036/evb_rk3036/Makefile b/board/rockchip/evb_rk3036/Makefile index 0403836e13..0403836e13 100644 --- a/board/evb_rk3036/evb_rk3036/Makefile +++ b/board/rockchip/evb_rk3036/Makefile diff --git a/board/evb_rk3036/evb_rk3036/evb_rk3036.c b/board/rockchip/evb_rk3036/evb_rk3036.c index f5758b1e9a..f5758b1e9a 100644 --- a/board/evb_rk3036/evb_rk3036/evb_rk3036.c +++ b/board/rockchip/evb_rk3036/evb_rk3036.c diff --git a/board/rockchip/evb_rk3399/Kconfig b/board/rockchip/evb_rk3399/Kconfig new file mode 100644 index 0000000000..412b81cbee --- /dev/null +++ b/board/rockchip/evb_rk3399/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3399 + +config SYS_BOARD + default "evb_rk3399" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_rk3399" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/board/rockchip/evb_rk3399/MAINTAINERS diff --git a/board/rockchip/evb_rk3399/Makefile b/board/rockchip/evb_rk3399/Makefile new file mode 100644 index 0000000000..aaa51c212e --- /dev/null +++ b/board/rockchip/evb_rk3399/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb-rk3399.o diff --git a/board/rockchip/evb_rk3399/README b/board/rockchip/evb_rk3399/README new file mode 100644 index 0000000000..fb8bb19763 --- /dev/null +++ b/board/rockchip/evb_rk3399/README @@ -0,0 +1,73 @@ +Introduction +============ + +RK3399 key features we might use in U-Boot: +* CPU: ARMv8 64bit Big-Little architecture, +* Big: dual-core Cortex-A72 +* Little: quad-core Cortex-A53 +* IRAM: 200KB +* DRAM: 4GB-128MB dual-channel +* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50 +* SD/MMC: support SD 3.0, MMC 4.51 +* USB: USB3.0 typc-C port *2 with dwc3 controller +* USB2.0 EHCI host port *2 +* Display: RGB/HDMI/DP/MIPI/EDP + +evb key features: +* regulator: pwm regulator for CPU B/L +* PMIC: rk808 +* debug console: UART2 + +In order to support Arm Trust Firmware(ATF), we need to use the +miniloader from rockchip which: +* do DRAM init +* load and verify ATF image +* load and verify U-Boot image + +Here is the step-by-step to boot to U-Boot on rk3399. + +Get the Source and prebuild binary +================================== + + > mkdir ~/evb_rk3399 + > cd ~/evb_rk3399 + > git clone https://github.com/ARM-software/arm-trusted-firmware.git + > git clone https://github.com/rockchip-linux/rkbin + > git clone https://github.com/rockchip-linux/rkflashtool + +Compile the ATF +=============== + + > cd arm-trusted-firmware + > make realclean + > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 + +Compile the U-Boot +================== + + > cd ../u-boot + > make CROSS_COMPILE=aarch64-linux-gnu- evb-rk3399_defconfig all + +Compile the rkflashtool +======================= + + > cd ../rkflashtool + > make + +Package the image for miniloader +================================ + > cd .. + > cp arm-trusted-firmware/build/rk3399/release/bl31.bin rkbin/rk33 + > ./rkbin/tools/trust_merger rkbin/tools/RK3399TRUST.ini + > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img + > mkdir image + > mv trust.img ./image/ + > mv uboot.img ./image/rk3399evb-uboot.bin + +Flash the image +=============== +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: + + > ./rkflashtool/rkflashloader rk3399evb + +You should be able to get U-Boot log message in console/UART2 now. diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c new file mode 100644 index 0000000000..dffacd0a84 --- /dev/null +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/armv8/mmu.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x80000000; + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = 0x80000000; +} diff --git a/board/kylin/kylin_rk3036/Kconfig b/board/rockchip/kylin_rk3036/Kconfig index 5d75c1fc0f..8d35b4e62b 100644 --- a/board/kylin/kylin_rk3036/Kconfig +++ b/board/rockchip/kylin_rk3036/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "kylin_rk3036" config SYS_VENDOR - default "kylin" + default "rockchip" config SYS_CONFIG_NAME default "kylin_rk3036" diff --git a/board/kylin/kylin_rk3036/MAINTAINERS b/board/rockchip/kylin_rk3036/MAINTAINERS index f8ee834377..f8ee834377 100644 --- a/board/kylin/kylin_rk3036/MAINTAINERS +++ b/board/rockchip/kylin_rk3036/MAINTAINERS diff --git a/board/kylin/kylin_rk3036/Makefile b/board/rockchip/kylin_rk3036/Makefile index 0663270506..0663270506 100644 --- a/board/kylin/kylin_rk3036/Makefile +++ b/board/rockchip/kylin_rk3036/Makefile diff --git a/board/kylin/kylin_rk3036/kylin_rk3036.c b/board/rockchip/kylin_rk3036/kylin_rk3036.c index 2a258710ac..2a258710ac 100644 --- a/board/kylin/kylin_rk3036/kylin_rk3036.c +++ b/board/rockchip/kylin_rk3036/kylin_rk3036.c diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index d5bc5153b1..fd5314aae1 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -53,7 +53,7 @@ CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_ROCKCHIP_PINCTRL=y +CONFIG_ROCKCHIP_RK3288_PINCTRL=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK808=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 9894fffcca..2d5e5e053f 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -32,7 +32,7 @@ CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y -CONFIG_ROCKCHIP_3036_PINCTRL=y +CONFIG_ROCKCHIP_RK3036_PINCTRL=y CONFIG_RAM=y # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_DEBUG_UART=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig new file mode 100644 index 0000000000..41cfedd879 --- /dev/null +++ b/configs/evb-rk3288_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3288=y +CONFIG_TARGET_EVB_RK3288=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb" +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SYSRESET=y +CONFIG_DM_MMC=y +CONFIG_ROCKCHIP_DWMMC=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_FULL is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_ROCKCHIP_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_ACT8846=y +CONFIG_DM_REGULATOR=y +CONFIG_REGULATOR_ACT8846=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig new file mode 100644 index 0000000000..3f9b47e679 --- /dev/null +++ b/configs/evb-rk3399_defconfig @@ -0,0 +1,33 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_GPT=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_FIT=y +CONFIG_SYSRESET=y +CONFIG_DM_MMC=y +CONFIG_ROCKCHIP_SDHCI=y +CONFIG_PINCTRL=y +CONFIG_RAM=y +CONFIG_SYS_NS16550=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index bdafc716aa..4122000489 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -46,7 +46,7 @@ CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_ROCKCHIP_PINCTRL=y +CONFIG_ROCKCHIP_RK3288_PINCTRL=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_ACT8846=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 0ff6c6b9a4..51196aa089 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -32,7 +32,7 @@ CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y -CONFIG_ROCKCHIP_3036_PINCTRL=y +CONFIG_ROCKCHIP_RK3036_PINCTRL=y CONFIG_RAM=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 3e16b805ca..3b6d7d95e6 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -44,7 +44,7 @@ CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_ROCKCHIP_PINCTRL=y +CONFIG_ROCKCHIP_RK3288_PINCTRL=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_ACT8846=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 89ebe92ce1..29e6d85bd4 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -120,8 +120,8 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCI_SANDBOX=y CONFIG_PINCTRL=y CONFIG_PINCONF=y -CONFIG_ROCKCHIP_PINCTRL=y -CONFIG_ROCKCHIP_3036_PINCTRL=y +CONFIG_ROCKCHIP_RK3288_PINCTRL=y +CONFIG_ROCKCHIP_RK3036_PINCTRL=y CONFIG_PINCTRL_SANDBOX=y CONFIG_DM_PMIC=y CONFIG_PMIC_ACT8846=y diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig index 60c73398db..503845bb00 100644 --- a/configs/sandbox_noblk_defconfig +++ b/configs/sandbox_noblk_defconfig @@ -112,8 +112,8 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCI_SANDBOX=y CONFIG_PINCTRL=y CONFIG_PINCONF=y -CONFIG_ROCKCHIP_PINCTRL=y -CONFIG_ROCKCHIP_3036_PINCTRL=y +CONFIG_ROCKCHIP_RK3288_PINCTRL=y +CONFIG_ROCKCHIP_RK3036_PINCTRL=y CONFIG_PINCTRL_SANDBOX=y CONFIG_DM_PMIC=y CONFIG_PMIC_ACT8846=y diff --git a/doc/README.rockchip b/doc/README.rockchip index e0572c80b9..c218a8b547 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -36,11 +36,12 @@ You will need: Building ======== -At present three RK3288 boards are supported: +At present four RK3288 boards are supported: - Firefly RK3288 - use firefly-rk3288 configuration - Radxa Rock 2 - use rock2 configuration - Hisense Chromebook - use chromebook_jerry configuration + - EVB RK3288 - use evb-rk3288 configuration Two RK3036 board are supported: @@ -119,6 +120,20 @@ something like: Hit any key to stop autoboot: 0 => +The rockchip bootrom can load and boot an initial spl, then continue to +load a second-level bootloader(ie. U-BOOT) as soon as it returns to bootrom. +Therefore RK3288 has another loading sequence like RK3036. The option of +U-Boot is controlled with this setting in U-Boot: + + #define CONFIG_ROCKCHIP_SPL_BACK_TO_BROM + +You can create the image via the following operations: + + ./firefly-rk3288/tools/mkimage -n rk3288 -T rksd -d \ + firefly-rk3288/spl/u-boot-spl-dtb.bin out && \ + cat firefly-rk3288/u-boot-dtb.bin >> out && \ + sudo dd if=out of=/dev/sdc seek=64 + If you have an HDMI cable attached you should see a video console. For evb_rk3036 board: @@ -129,6 +144,32 @@ For evb_rk3036 board: Note: rk3036 SDMMC and debug uart use the same iomux, so if you boot from SD, the debug uart must be disabled +Using fastboot on rk3288 +======================== +- Define GPT partition layout like kylin_rk3036(see include/configs/kylin_rk3036.h) +- Write GPT partition layout to mmc device which fastboot want to use it to +store the image + + => gpt write mmc 1 $partitions + +- Invoke fastboot command to prepare + + => fastboot 1 + +- Start fastboot request on PC + + fastboot -i 0x2207 flash loader evb-rk3288/spl/u-boot-spl-dtb.bin + +You should see something like: + + => fastboot 1 + WARNING: unknown variable: partition-type:loader + Starting download of 357796 bytes + .. + downloading of 357796 bytes finished + Flashing Raw Image + ........ wrote 357888 bytes to 'loader' + Booting from SPI ================ diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c index 679f010bb7..e00feb0809 100644 --- a/drivers/clk/clk_rk3288.c +++ b/drivers/clk/clk_rk3288.c @@ -47,7 +47,7 @@ enum { OUTPUT_MAX_HZ = 2200U * 1000000, OUTPUT_MIN_HZ = 27500000, FREF_MAX_HZ = 2200U * 1000000, - FREF_MIN_HZ = 269 * 1000000, + FREF_MIN_HZ = 269 * 1000, }; enum { @@ -145,7 +145,7 @@ void *rockchip_get_cru(void) struct udevice *dev; int ret; - ret = uclass_get_device(UCLASS_CLK, 0, &dev); + ret = rockchip_get_clk(&dev); if (ret) return ERR_PTR(ret); @@ -447,7 +447,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) } #endif -void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) +void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) { /* pll enter slow-mode */ rk_clrsetreg(&cru->cru_mode_con, diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 1141ce1ba3..de602ae52d 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -311,6 +311,26 @@ static int uclass_find_device_by_phandle(enum uclass_id id, } #endif +int uclass_get_device_by_driver(enum uclass_id id, + const struct driver *find_drv, + struct udevice **devp) +{ + struct udevice *dev; + struct uclass *uc; + int ret; + + ret = uclass_get(id, &uc); + if (ret) + return ret; + + list_for_each_entry(dev, &uc->dev_head, uclass_node) { + if (dev->driver == find_drv) + return uclass_get_device_tail(dev, 0, devp); + } + + return -ENODEV; +} + int uclass_get_device_tail(struct udevice *dev, int ret, struct udevice **devp) { diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index e0adb9b1a3..dc8f2b6852 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -61,6 +61,12 @@ config ZYNQ_SDHCI help Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform +config ROCKCHIP_SDHCI + bool "Arasan SDHCI controller for Rockchip support" + depends on DM_MMC && BLK && DM_MMC_OPS + help + Support for Arasan SDHCI host controller on Rockchip ARM SoCs platform + config MMC_UNIPHIER bool "UniPhier SD/MMC Host Controller support" depends on ARCH_UNIPHIER diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index b44a12e606..18351fb48a 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o +obj-$(CONFIG_ROCKCHIP_SDHCI) += rockchip_sdhci.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c new file mode 100644 index 0000000000..023c29be0a --- /dev/null +++ b/drivers/mmc/rockchip_sdhci.c @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * Rockchip SD Host Controller Interface + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <malloc.h> +#include <sdhci.h> + +/* 400KHz is max freq for card ID etc. Use that as min */ +#define EMMC_MIN_FREQ 400000 + +struct rockchip_sdhc_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +struct rockchip_sdhc { + struct sdhci_host host; + void *base; +}; + +static int arasan_sdhci_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); + struct rockchip_sdhc *prv = dev_get_priv(dev); + struct sdhci_host *host = &prv->host; + int ret; + u32 caps; + + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; + + caps = sdhci_readl(host, SDHCI_CAPABILITIES); + ret = sdhci_setup_cfg(&plat->cfg, dev->name, host->bus_width, + caps, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ, EMMC_MIN_FREQ, + host->version, host->quirks, 0); + + host->mmc = &plat->mmc; + if (ret) + return ret; + host->mmc->priv = &prv->host; + host->mmc->dev = dev; + upriv->mmc = host->mmc; + + return sdhci_probe(dev); +} + +static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) +{ + struct sdhci_host *host = dev_get_priv(dev); + + host->name = dev->name; + host->ioaddr = dev_get_addr_ptr(dev); + + return 0; +} + +static int rockchip_sdhci_bind(struct udevice *dev) +{ + struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); + int ret; + + ret = sdhci_bind(dev, &plat->mmc, &plat->cfg); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id arasan_sdhci_ids[] = { + { .compatible = "arasan,sdhci-5.1" }, + { } +}; + +U_BOOT_DRIVER(arasan_sdhci_drv) = { + .name = "arasan_sdhci", + .id = UCLASS_MMC, + .of_match = arasan_sdhci_ids, + .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata, + .ops = &sdhci_ops, + .bind = rockchip_sdhci_bind, + .probe = arasan_sdhci_probe, + .priv_auto_alloc_size = sizeof(struct rockchip_sdhc), + .platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat), +}; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 1785e3b28c..2972dba1f9 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -123,21 +123,21 @@ config QCA953X_PINCTRL both the GPIO definitions and pin control functions for each available multiplex function. -config ROCKCHIP_PINCTRL - bool "Rockchip pin control driver" +config ROCKCHIP_RK3036_PINCTRL + bool "Rockchip rk3036 pin control driver" depends on DM help - Support pin multiplexing control on Rockchip SoCs. The driver is + Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is controlled by a device tree node which contains both the GPIO definitions and pin control functions for each available multiplex function. -config ROCKCHIP_3036_PINCTRL - bool "Rockchip rk3036 pin control driver" +config ROCKCHIP_RK3288_PINCTRL + bool "Rockchip pin control driver" depends on DM help - Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is - controlled by a device tree node which contains both the GPIO + Support pin multiplexing control on Rockchip rk3288 SoCs. The driver + is controlled by a device tree node which contains both the GPIO definitions and pin control functions for each available multiplex function. diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 6fa7d00d0d..64e9587cce 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -5,5 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_ROCKCHIP_PINCTRL) += pinctrl_rk3288.o -obj-$(CONFIG_ROCKCHIP_3036_PINCTRL) += pinctrl_rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3036_PINCTRL) += pinctrl_rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c index a23278d957..029927f8ac 100644 --- a/drivers/usb/gadget/dwc2_udc_otg.c +++ b/drivers/usb/gadget/dwc2_udc_otg.c @@ -403,6 +403,7 @@ static void reconfig_usbd(struct dwc2_udc *dev) int i; unsigned int uTemp = writel(CORE_SOFT_RESET, ®->grstctl); uint32_t dflt_gusbcfg; + uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz; debug("Reseting OTG controller\n"); @@ -467,18 +468,27 @@ static void reconfig_usbd(struct dwc2_udc *dev) /* 10. Unmask device IN EP common interrupts*/ writel(DIEPMSK_INIT, ®->diepmsk); + rx_fifo_sz = RX_FIFO_SIZE; + np_tx_fifo_sz = NPTX_FIFO_SIZE; + tx_fifo_sz = PTX_FIFO_SIZE; + + if (dev->pdata->rx_fifo_sz) + rx_fifo_sz = dev->pdata->rx_fifo_sz; + if (dev->pdata->np_tx_fifo_sz) + np_tx_fifo_sz = dev->pdata->np_tx_fifo_sz; + if (dev->pdata->tx_fifo_sz) + tx_fifo_sz = dev->pdata->tx_fifo_sz; + /* 11. Set Rx FIFO Size (in 32-bit words) */ - writel(RX_FIFO_SIZE >> 2, ®->grxfsiz); + writel(rx_fifo_sz, ®->grxfsiz); /* 12. Set Non Periodic Tx FIFO Size */ - writel((NPTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE >> 2)) << 0, + writel((np_tx_fifo_sz << 16) | rx_fifo_sz, ®->gnptxfsiz); for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++) - writel((PTX_FIFO_SIZE >> 2) << 16 | - ((RX_FIFO_SIZE + NPTX_FIFO_SIZE + - PTX_FIFO_SIZE*(i-1)) >> 2) << 0, - ®->dieptxf[i-1]); + writel((rx_fifo_sz + np_tx_fifo_sz + tx_fifo_sz*(i-1)) | + tx_fifo_sz << 16, ®->dieptxf[i-1]); /* Flush the RX FIFO */ writel(RX_FIFO_FLUSH, ®->grstctl); diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h b/drivers/usb/gadget/dwc2_udc_otg_regs.h index 78ec90ea9f..c94396afc0 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_regs.h +++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h @@ -130,9 +130,9 @@ struct dwc2_usbotg_reg { #define HIGH_SPEED_CONTROL_PKT_SIZE 64 #define HIGH_SPEED_BULK_PKT_SIZE 512 -#define RX_FIFO_SIZE (1024*4) -#define NPTX_FIFO_SIZE (1024*4) -#define PTX_FIFO_SIZE (1536*1) +#define RX_FIFO_SIZE (1024) +#define NPTX_FIFO_SIZE (1024) +#define PTX_FIFO_SIZE (384) #define DEPCTL_TXFNUM_0 (0x0<<22) #define DEPCTL_TXFNUM_1 (0x1<<22) diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c index 12f5c85c31..0d6d2fba8a 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c @@ -110,6 +110,9 @@ static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req) ctrl = readl(®->out_endp[ep_num].doepctl); + invalidate_dcache_range((unsigned long) ep->dma_buf, + (unsigned long) ep->dma_buf + ep->len); + writel((unsigned int) ep->dma_buf, ®->out_endp[ep_num].doepdma); writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length), ®->out_endp[ep_num].doeptsiz); diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile index 93d147e26f..4e548c24ec 100644 --- a/drivers/usb/phy/Makefile +++ b/drivers/usb/phy/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_TWL4030_USB) += twl4030.o obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o +obj-$(CONFIG_ROCKCHIP_USB2_PHY) += rockchip_usb2_phy.o diff --git a/drivers/usb/phy/rockchip_usb2_phy.c b/drivers/usb/phy/rockchip_usb2_phy.c new file mode 100644 index 0000000000..1958478d62 --- /dev/null +++ b/drivers/usb/phy/rockchip_usb2_phy.c @@ -0,0 +1,107 @@ +/* + * Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <libfdt.h> + +#include "../gadget/dwc2_udc_otg_priv.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define BIT_WRITEABLE_SHIFT 16 + +struct usb2phy_reg { + unsigned int offset; + unsigned int bitend; + unsigned int bitstart; + unsigned int disable; + unsigned int enable; +}; + +/** + * struct rockchip_usb2_phy_cfg: usb-phy port configuration + * @port_reset: usb otg per-port reset register + * @soft_con: software control usb otg register + * @suspend: phy suspend register + */ +struct rockchip_usb2_phy_cfg { + struct usb2phy_reg port_reset; + struct usb2phy_reg soft_con; + struct usb2phy_reg suspend; +}; + +struct rockchip_usb2_phy_dt_id { + char compatible[128]; + const void *data; +}; + +static const struct rockchip_usb2_phy_cfg rk3288_pdata = { + .port_reset = {0x00, 12, 12, 0, 1}, + .soft_con = {0x08, 2, 2, 0, 1}, + .suspend = {0x0c, 5, 0, 0x01, 0x2A}, +}; + +static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = { + { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata }, + {} +}; + +static void property_enable(struct dwc2_plat_otg_data *pdata, + const struct usb2phy_reg *reg, bool en) +{ + unsigned int val, mask, tmp; + + tmp = en ? reg->enable : reg->disable; + mask = GENMASK(reg->bitend, reg->bitstart); + val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); + + writel(val, pdata->regs_phy + reg->offset); +} + + +void otg_phy_init(struct dwc2_udc *dev) +{ + struct dwc2_plat_otg_data *pdata = dev->pdata; + struct rockchip_usb2_phy_cfg *phy_cfg = NULL; + struct rockchip_usb2_phy_dt_id *of_id; + int i; + + for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) { + of_id = &rockchip_usb2_phy_dt_ids[i]; + if (fdt_node_check_compatible(gd->fdt_blob, pdata->phy_of_node, + of_id->compatible) == 0) { + phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data; + break; + } + } + if (!phy_cfg) { + debug("Can't find device platform data\n"); + + hang(); + return; + } + pdata->priv = phy_cfg; + /* disable software control */ + property_enable(pdata, &phy_cfg->soft_con, false); + + /* reset otg port */ + property_enable(pdata, &phy_cfg->port_reset, true); + mdelay(1); + property_enable(pdata, &phy_cfg->port_reset, false); + udelay(1); +} + +void otg_phy_off(struct dwc2_udc *dev) +{ + struct dwc2_plat_otg_data *pdata = dev->pdata; + struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv; + + /* enable software control */ + property_enable(pdata, &phy_cfg->soft_con, true); + /* enter suspend */ + property_enable(pdata, &phy_cfg->suspend, true); +} diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index cc26f1956d..c6d88d9225 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -238,7 +238,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase, return ret; } - ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk); + ret = rockchip_get_clk(&dev_clk); if (!ret) { clk.id = DCLK_VOP0 + remote_vop_id; ret = clk_request(dev_clk, &clk); diff --git a/include/configs/evb-rk3288.h b/include/configs/evb-rk3288.h new file mode 100644 index 0000000000..342557fff3 --- /dev/null +++ b/include/configs/evb-rk3288.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include <configs/rk3288_common.h> + +#define CONFIG_SPL_MMC_SUPPORT + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +/* SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) + +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h new file mode 100644 index 0000000000..047850a8f9 --- /dev/null +++ b/include/configs/evb_rk3399.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EVB_RK3399_H +#define __EVB_RK3399_H + +#include <configs/rk3399_common.h> + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +/* + * SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) + +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 8adc26fc8b..2a36c1706b 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -33,7 +33,12 @@ #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SPL_BOARD_INIT +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +/* Bootrom will load u-boot binary to 0x0 once return from SPL */ +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#else #define CONFIG_SYS_TEXT_BASE 0x00100000 +#endif #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0xff718000 @@ -79,6 +84,32 @@ #define CONFIG_SPI #define CONFIG_SF_DEFAULT_SPEED 20000000 +/* usb otg */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_DWC2_OTG +#define CONFIG_ROCKCHIP_USB2_PHY +#define CONFIG_USB_GADGET_VBUS_DRAW 0 + +/* fastboot */ +#define CONFIG_CMD_FASTBOOT +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_FASTBOOT_FLASH +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 /* eMMC */ +/* stroe safely fastboot buffer data to the middle of bank */ +#define CONFIG_FASTBOOT_BUF_ADDR (CONFIG_SYS_SDRAM_BASE \ + + SDRAM_BANK_SIZE / 2) +#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000 + +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_G_DNL_MANUFACTURER "Rockchip" +#define CONFIG_G_DNL_VENDOR_NUM 0x2207 +#define CONFIG_G_DNL_PRODUCT_NUM 0x320a + +/* Enable gpt partition table */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION + #ifndef CONFIG_SPL_BUILD #include <config_distro_defaults.h> diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h new file mode 100644 index 0000000000..6ce1aa76a6 --- /dev/null +++ b/include/configs/rk3399_common.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3399_COMMON_H +#define __CONFIG_RK3399_COMMON_H + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 1500000 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_TEXT_BASE 0x00200000 +#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +#define CONFIG_SYS_LOAD_ADDR 0x00800800 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +/* MMC/SD IP block */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SDHCI +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000 + +#define CONFIG_FAT_WRITE + +/* RAW SD card / eMMC locations. */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 +#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) + +/* FAT sd card locations. */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_SF_DEFAULT_SPEED 20000000 + +#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00000000\0" \ + "pxefile_addr_r=0x00100000\0" \ + "fdt_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x04000000\0" + +/* First try to boot from SD (index 0), then eMMC (index 1) */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#include <config_distro_bootcmd.h> +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV + +#endif + +#endif diff --git a/include/dm/device.h b/include/dm/device.h index c825d47236..705849b228 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -207,6 +207,10 @@ struct driver { #define U_BOOT_DRIVER(__name) \ ll_entry_declare(struct driver, __name, driver) +/* Get a pointer to a given driver */ +#define DM_GET_DRIVER(__name) \ + ll_entry_get(struct driver, __name, driver) + /** * dev_get_platdata() - Get the platform data for a device * diff --git a/include/dm/uclass.h b/include/dm/uclass.h index fd368b6bd0..84f05bcfce 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -38,6 +38,7 @@ struct uclass { struct list_head sibling_node; }; +struct driver; struct udevice; /* Members of this uclass sequence themselves with aliases */ @@ -194,6 +195,23 @@ int uclass_get_device_by_phandle(enum uclass_id id, struct udevice *parent, const char *name, struct udevice **devp); /** + * uclass_get_device_by_driver() - Get a uclass device for a driver + * + * This searches the devices in the uclass for one that uses the given + * driver. Use DM_GET_DRIVER(name) for the @drv argument, where 'name' is + * the driver name - as used in U_BOOT_DRIVER(name). + * + * The device is probed to activate it ready for use. + * + * @id: ID to look up + * @drv: Driver to look for + * @devp: Returns pointer to the first device with that driver + * @return 0 if OK, -ve on error + */ +int uclass_get_device_by_driver(enum uclass_id id, const struct driver *drv, + struct udevice **devp); + +/** * uclass_first_device() - Get the first device in a uclass * * The device returned is probed if necessary, and ready for use diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h new file mode 100644 index 0000000000..0a86aec50a --- /dev/null +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -0,0 +1,746 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H + +/* core clocks */ +#define PLL_APLLL 1 +#define PLL_APLLB 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define PLL_VPLL 7 +#define ARMCLKL 8 +#define ARMCLKB 9 + +/* sclk gates (special clocks) */ +#define SCLK_I2C1 65 +#define SCLK_I2C2 66 +#define SCLK_I2C3 67 +#define SCLK_I2C5 68 +#define SCLK_I2C6 69 +#define SCLK_I2C7 70 +#define SCLK_SPI0 71 +#define SCLK_SPI1 72 +#define SCLK_SPI2 73 +#define SCLK_SPI4 74 +#define SCLK_SPI5 75 +#define SCLK_SDMMC 76 +#define SCLK_SDIO 77 +#define SCLK_EMMC 78 +#define SCLK_TSADC 79 +#define SCLK_SARADC 80 +#define SCLK_UART0 81 +#define SCLK_UART1 82 +#define SCLK_UART2 83 +#define SCLK_UART3 84 +#define SCLK_SPDIF_8CH 85 +#define SCLK_I2S0_8CH 86 +#define SCLK_I2S1_8CH 87 +#define SCLK_I2S2_8CH 88 +#define SCLK_I2S_8CH_OUT 89 +#define SCLK_TIMER00 90 +#define SCLK_TIMER01 91 +#define SCLK_TIMER02 92 +#define SCLK_TIMER03 93 +#define SCLK_TIMER04 94 +#define SCLK_TIMER05 95 +#define SCLK_TIMER06 96 +#define SCLK_TIMER07 97 +#define SCLK_TIMER08 98 +#define SCLK_TIMER09 99 +#define SCLK_TIMER10 100 +#define SCLK_TIMER11 101 +#define SCLK_MACREF 102 +#define SCLK_MAC_RX 103 +#define SCLK_MAC_TX 104 +#define SCLK_MAC 105 +#define SCLK_MACREF_OUT 106 +#define SCLK_VOP0_PWM 107 +#define SCLK_VOP1_PWM 108 +#define SCLK_RGA_CORE 109 +#define SCLK_ISP0 110 +#define SCLK_ISP1 111 +#define SCLK_HDMI_CEC 112 +#define SCLK_HDMI_SFR 113 +#define SCLK_DP_CORE 114 +#define SCLK_PVTM_CORE_L 115 +#define SCLK_PVTM_CORE_B 116 +#define SCLK_PVTM_GPU 117 +#define SCLK_PVTM_DDR 118 +#define SCLK_MIPIDPHY_REF 119 +#define SCLK_MIPIDPHY_CFG 120 +#define SCLK_HSICPHY 121 +#define SCLK_USBPHY480M 122 +#define SCLK_USB2PHY0_REF 123 +#define SCLK_USB2PHY1_REF 124 +#define SCLK_UPHY0_TCPDPHY_REF 125 +#define SCLK_UPHY0_TCPDCORE 126 +#define SCLK_UPHY1_TCPDPHY_REF 127 +#define SCLK_UPHY1_TCPDCORE 128 +#define SCLK_USB3OTG0_REF 129 +#define SCLK_USB3OTG1_REF 130 +#define SCLK_USB3OTG0_SUSPEND 131 +#define SCLK_USB3OTG1_SUSPEND 132 +#define SCLK_CRYPTO0 133 +#define SCLK_CRYPTO1 134 +#define SCLK_CCI_TRACE 135 +#define SCLK_CS 136 +#define SCLK_CIF_OUT 137 +#define SCLK_PCIEPHY_REF 138 +#define SCLK_PCIE_CORE 139 +#define SCLK_M0_PERILP 140 +#define SCLK_M0_PERILP_DEC 141 +#define SCLK_CM0S 142 +#define SCLK_DBG_NOC 143 +#define SCLK_DBG_PD_CORE_B 144 +#define SCLK_DBG_PD_CORE_L 145 +#define SCLK_DFIMON0_TIMER 146 +#define SCLK_DFIMON1_TIMER 147 +#define SCLK_INTMEM0 148 +#define SCLK_INTMEM1 149 +#define SCLK_INTMEM2 150 +#define SCLK_INTMEM3 151 +#define SCLK_INTMEM4 152 +#define SCLK_INTMEM5 153 +#define SCLK_SDMMC_DRV 154 +#define SCLK_SDMMC_SAMPLE 155 +#define SCLK_SDIO_DRV 156 +#define SCLK_SDIO_SAMPLE 157 +#define SCLK_VDU_CORE 158 +#define SCLK_VDU_CA 159 +#define SCLK_PCIE_PM 160 +#define SCLK_SPDIF_REC_DPTX 161 +#define SCLK_DPHY_PLL 162 +#define SCLK_DPHY_TX0_CFG 163 +#define SCLK_DPHY_TX1RX1_CFG 164 +#define SCLK_DPHY_RX0_CFG 165 +#define SCLK_RMII_SRC 166 +#define SCLK_PCIEPHY_REF100M 167 + +#define DCLK_VOP0 180 +#define DCLK_VOP1 181 +#define DCLK_VOP0_DIV 182 +#define DCLK_VOP1_DIV 183 +#define DCLK_M0_PERILP 184 + +#define FCLK_CM0S 190 + +/* aclk gates */ +#define ACLK_PERIHP 192 +#define ACLK_PERIHP_NOC 193 +#define ACLK_PERILP0 194 +#define ACLK_PERILP0_NOC 195 +#define ACLK_PERF_PCIE 196 +#define ACLK_PCIE 197 +#define ACLK_INTMEM 198 +#define ACLK_TZMA 199 +#define ACLK_DCF 200 +#define ACLK_CCI 201 +#define ACLK_CCI_NOC0 202 +#define ACLK_CCI_NOC1 203 +#define ACLK_CCI_GRF 204 +#define ACLK_CENTER 205 +#define ACLK_CENTER_MAIN_NOC 206 +#define ACLK_CENTER_PERI_NOC 207 +#define ACLK_GPU 208 +#define ACLK_PERF_GPU 209 +#define ACLK_GPU_GRF 210 +#define ACLK_DMAC0_PERILP 211 +#define ACLK_DMAC1_PERILP 212 +#define ACLK_GMAC 213 +#define ACLK_GMAC_NOC 214 +#define ACLK_PERF_GMAC 215 +#define ACLK_VOP0_NOC 216 +#define ACLK_VOP0 217 +#define ACLK_VOP1_NOC 218 +#define ACLK_VOP1 219 +#define ACLK_RGA 220 +#define ACLK_RGA_NOC 221 +#define ACLK_HDCP 222 +#define ACLK_HDCP_NOC 223 +#define ACLK_HDCP22 224 +#define ACLK_IEP 225 +#define ACLK_IEP_NOC 226 +#define ACLK_VIO 227 +#define ACLK_VIO_NOC 228 +#define ACLK_ISP0 229 +#define ACLK_ISP1 230 +#define ACLK_ISP0_NOC 231 +#define ACLK_ISP1_NOC 232 +#define ACLK_ISP0_WRAPPER 233 +#define ACLK_ISP1_WRAPPER 234 +#define ACLK_VCODEC 235 +#define ACLK_VCODEC_NOC 236 +#define ACLK_VDU 237 +#define ACLK_VDU_NOC 238 +#define ACLK_PERI 239 +#define ACLK_EMMC 240 +#define ACLK_EMMC_CORE 241 +#define ACLK_EMMC_NOC 242 +#define ACLK_EMMC_GRF 243 +#define ACLK_USB3 244 +#define ACLK_USB3_NOC 245 +#define ACLK_USB3OTG0 246 +#define ACLK_USB3OTG1 247 +#define ACLK_USB3_RKSOC_AXI_PERF 248 +#define ACLK_USB3_GRF 249 +#define ACLK_GIC 250 +#define ACLK_GIC_NOC 251 +#define ACLK_GIC_ADB400_CORE_L_2_GIC 252 +#define ACLK_GIC_ADB400_CORE_B_2_GIC 253 +#define ACLK_GIC_ADB400_GIC_2_CORE_L 254 +#define ACLK_GIC_ADB400_GIC_2_CORE_B 255 +#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 +#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 +#define ACLK_ADB400M_PD_CORE_L 258 +#define ACLK_ADB400M_PD_CORE_B 259 +#define ACLK_PERF_CORE_L 260 +#define ACLK_PERF_CORE_B 261 +#define ACLK_GIC_PRE 262 +#define ACLK_VOP0_PRE 263 +#define ACLK_VOP1_PRE 264 + +/* pclk gates */ +#define PCLK_PERIHP 320 +#define PCLK_PERIHP_NOC 321 +#define PCLK_PERILP0 322 +#define PCLK_PERILP1 323 +#define PCLK_PERILP1_NOC 324 +#define PCLK_PERILP_SGRF 325 +#define PCLK_PERIHP_GRF 326 +#define PCLK_PCIE 327 +#define PCLK_SGRF 328 +#define PCLK_INTR_ARB 329 +#define PCLK_CENTER_MAIN_NOC 330 +#define PCLK_CIC 331 +#define PCLK_COREDBG_B 332 +#define PCLK_COREDBG_L 333 +#define PCLK_DBG_CXCS_PD_CORE_B 334 +#define PCLK_DCF 335 +#define PCLK_GPIO2 336 +#define PCLK_GPIO3 337 +#define PCLK_GPIO4 338 +#define PCLK_GRF 339 +#define PCLK_HSICPHY 340 +#define PCLK_I2C1 341 +#define PCLK_I2C2 342 +#define PCLK_I2C3 343 +#define PCLK_I2C5 344 +#define PCLK_I2C6 345 +#define PCLK_I2C7 346 +#define PCLK_SPI0 347 +#define PCLK_SPI1 348 +#define PCLK_SPI2 349 +#define PCLK_SPI4 350 +#define PCLK_SPI5 351 +#define PCLK_UART0 352 +#define PCLK_UART1 353 +#define PCLK_UART2 354 +#define PCLK_UART3 355 +#define PCLK_TSADC 356 +#define PCLK_SARADC 357 +#define PCLK_GMAC 358 +#define PCLK_GMAC_NOC 359 +#define PCLK_TIMER0 360 +#define PCLK_TIMER1 361 +#define PCLK_EDP 362 +#define PCLK_EDP_NOC 363 +#define PCLK_EDP_CTRL 364 +#define PCLK_VIO 365 +#define PCLK_VIO_NOC 366 +#define PCLK_VIO_GRF 367 +#define PCLK_MIPI_DSI0 368 +#define PCLK_MIPI_DSI1 369 +#define PCLK_HDCP 370 +#define PCLK_HDCP_NOC 371 +#define PCLK_HDMI_CTRL 372 +#define PCLK_DP_CTRL 373 +#define PCLK_HDCP22 374 +#define PCLK_GASKET 375 +#define PCLK_DDR 376 +#define PCLK_DDR_MON 377 +#define PCLK_DDR_SGRF 378 +#define PCLK_ISP1_WRAPPER 379 +#define PCLK_WDT 380 +#define PCLK_EFUSE1024NS 381 +#define PCLK_EFUSE1024S 382 +#define PCLK_PMU_INTR_ARB 383 +#define PCLK_MAILBOX0 384 +#define PCLK_USBPHY_MUX_G 385 +#define PCLK_UPHY0_TCPHY_G 386 +#define PCLK_UPHY0_TCPD_G 387 +#define PCLK_UPHY1_TCPHY_G 388 +#define PCLK_UPHY1_TCPD_G 389 +#define PCLK_ALIVE 390 + +/* hclk gates */ +#define HCLK_PERIHP 448 +#define HCLK_PERILP0 449 +#define HCLK_PERILP1 450 +#define HCLK_PERILP0_NOC 451 +#define HCLK_PERILP1_NOC 452 +#define HCLK_M0_PERILP 453 +#define HCLK_M0_PERILP_NOC 454 +#define HCLK_AHB1TOM 455 +#define HCLK_HOST0 456 +#define HCLK_HOST0_ARB 457 +#define HCLK_HOST1 458 +#define HCLK_HOST1_ARB 459 +#define HCLK_HSIC 460 +#define HCLK_SD 461 +#define HCLK_SDMMC 462 +#define HCLK_SDMMC_NOC 463 +#define HCLK_M_CRYPTO0 464 +#define HCLK_M_CRYPTO1 465 +#define HCLK_S_CRYPTO0 466 +#define HCLK_S_CRYPTO1 467 +#define HCLK_I2S0_8CH 468 +#define HCLK_I2S1_8CH 469 +#define HCLK_I2S2_8CH 470 +#define HCLK_SPDIF 471 +#define HCLK_VOP0_NOC 472 +#define HCLK_VOP0 473 +#define HCLK_VOP1_NOC 474 +#define HCLK_VOP1 475 +#define HCLK_ROM 476 +#define HCLK_IEP 477 +#define HCLK_IEP_NOC 478 +#define HCLK_ISP0 479 +#define HCLK_ISP1 480 +#define HCLK_ISP0_NOC 481 +#define HCLK_ISP1_NOC 482 +#define HCLK_ISP0_WRAPPER 483 +#define HCLK_ISP1_WRAPPER 484 +#define HCLK_RGA 485 +#define HCLK_RGA_NOC 486 +#define HCLK_HDCP 487 +#define HCLK_HDCP_NOC 488 +#define HCLK_HDCP22 489 +#define HCLK_VCODEC 490 +#define HCLK_VCODEC_NOC 491 +#define HCLK_VDU 492 +#define HCLK_VDU_NOC 493 +#define HCLK_SDIO 494 +#define HCLK_SDIO_NOC 495 +#define HCLK_SDIOAUDIO_NOC 496 + +#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) + +/* pmu-clocks indices */ + +#define PLL_PPLL 1 + +#define SCLK_32K_SUSPEND_PMU 2 +#define SCLK_SPI3_PMU 3 +#define SCLK_TIMER12_PMU 4 +#define SCLK_TIMER13_PMU 5 +#define SCLK_UART4_PMU 6 +#define SCLK_PVTM_PMU 7 +#define SCLK_WIFI_PMU 8 +#define SCLK_I2C0_PMU 9 +#define SCLK_I2C4_PMU 10 +#define SCLK_I2C8_PMU 11 + +#define PCLK_SRC_PMU 19 +#define PCLK_PMU 20 +#define PCLK_PMUGRF_PMU 21 +#define PCLK_INTMEM1_PMU 22 +#define PCLK_GPIO0_PMU 23 +#define PCLK_GPIO1_PMU 24 +#define PCLK_SGRF_PMU 25 +#define PCLK_NOC_PMU 26 +#define PCLK_I2C0_PMU 27 +#define PCLK_I2C4_PMU 28 +#define PCLK_I2C8_PMU 29 +#define PCLK_RKPWM_PMU 30 +#define PCLK_SPI3_PMU 31 +#define PCLK_TIMER_PMU 32 +#define PCLK_MAILBOX_PMU 33 +#define PCLK_UART4_PMU 34 +#define PCLK_WDT_M0_PMU 35 + +#define FCLK_CM0S_SRC_PMU 44 +#define FCLK_CM0S_PMU 45 +#define SCLK_CM0S_PMU 46 +#define HCLK_CM0S_PMU 47 +#define DCLK_CM0S_PMU 48 +#define PCLK_INTR_ARB_PMU 49 +#define HCLK_NOC_PMU 50 + +#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE_L0 0 +#define SRST_CORE_B0 1 +#define SRST_CORE_PO_L0 2 +#define SRST_CORE_PO_B0 3 +#define SRST_L2_L 4 +#define SRST_L2_B 5 +#define SRST_ADB_L 6 +#define SRST_ADB_B 7 +#define SRST_A_CCI 8 +#define SRST_A_CCIM0_NOC 9 +#define SRST_A_CCIM1_NOC 10 +#define SRST_DBG_NOC 11 + +/* cru_softrst_con1 */ +#define SRST_CORE_L0_T 16 +#define SRST_CORE_L1 17 +#define SRST_CORE_L2 18 +#define SRST_CORE_L3 19 +#define SRST_CORE_PO_L0_T 20 +#define SRST_CORE_PO_L1 21 +#define SRST_CORE_PO_L2 22 +#define SRST_CORE_PO_L3 23 +#define SRST_A_ADB400_GIC2COREL 24 +#define SRST_A_ADB400_COREL2GIC 25 +#define SRST_P_DBG_L 26 +#define SRST_L2_L_T 28 +#define SRST_ADB_L_T 29 +#define SRST_A_RKPERF_L 30 +#define SRST_PVTM_CORE_L 31 + +/* cru_softrst_con2 */ +#define SRST_CORE_B0_T 32 +#define SRST_CORE_B1 33 +#define SRST_CORE_PO_B0_T 36 +#define SRST_CORE_PO_B1 37 +#define SRST_A_ADB400_GIC2COREB 40 +#define SRST_A_ADB400_COREB2GIC 41 +#define SRST_P_DBG_B 42 +#define SRST_L2_B_T 43 +#define SRST_ADB_B_T 45 +#define SRST_A_RKPERF_B 46 +#define SRST_PVTM_CORE_B 47 + +/* cru_softrst_con3 */ +#define SRST_A_CCI_T 50 +#define SRST_A_CCIM0_NOC_T 51 +#define SRST_A_CCIM1_NOC_T 52 +#define SRST_A_ADB400M_PD_CORE_B_T 53 +#define SRST_A_ADB400M_PD_CORE_L_T 54 +#define SRST_DBG_NOC_T 55 +#define SRST_DBG_CXCS 56 +#define SRST_CCI_TRACE 57 +#define SRST_P_CCI_GRF 58 + +/* cru_softrst_con4 */ +#define SRST_A_CENTER_MAIN_NOC 64 +#define SRST_A_CENTER_PERI_NOC 65 +#define SRST_P_CENTER_MAIN 66 +#define SRST_P_DDRMON 67 +#define SRST_P_CIC 68 +#define SRST_P_CENTER_SGRF 69 +#define SRST_DDR0_MSCH 70 +#define SRST_DDRCFG0_MSCH 71 +#define SRST_DDR0 72 +#define SRST_DDRPHY0 73 +#define SRST_DDR1_MSCH 74 +#define SRST_DDRCFG1_MSCH 75 +#define SRST_DDR1 76 +#define SRST_DDRPHY1 77 +#define SRST_DDR_CIC 78 +#define SRST_PVTM_DDR 79 + +/* cru_softrst_con5 */ +#define SRST_A_VCODEC_NOC 80 +#define SRST_A_VCODEC 81 +#define SRST_H_VCODEC_NOC 82 +#define SRST_H_VCODEC 83 +#define SRST_A_VDU_NOC 88 +#define SRST_A_VDU 89 +#define SRST_H_VDU_NOC 90 +#define SRST_H_VDU 91 +#define SRST_VDU_CORE 92 +#define SRST_VDU_CA 93 + +/* cru_softrst_con6 */ +#define SRST_A_IEP_NOC 96 +#define SRST_A_VOP_IEP 97 +#define SRST_A_IEP 98 +#define SRST_H_IEP_NOC 99 +#define SRST_H_IEP 100 +#define SRST_A_RGA_NOC 102 +#define SRST_A_RGA 103 +#define SRST_H_RGA_NOC 104 +#define SRST_H_RGA 105 +#define SRST_RGA_CORE 106 +#define SRST_EMMC_NOC 108 +#define SRST_EMMC 109 +#define SRST_EMMC_GRF 110 + +/* cru_softrst_con7 */ +#define SRST_A_PERIHP_NOC 112 +#define SRST_P_PERIHP_GRF 113 +#define SRST_H_PERIHP_NOC 114 +#define SRST_USBHOST0 115 +#define SRST_HOSTC0_AUX 116 +#define SRST_HOST0_ARB 117 +#define SRST_USBHOST1 118 +#define SRST_HOSTC1_AUX 119 +#define SRST_HOST1_ARB 120 +#define SRST_SDIO0 121 +#define SRST_SDMMC 122 +#define SRST_HSIC 123 +#define SRST_HSIC_AUX 124 +#define SRST_AHB1TOM 125 +#define SRST_P_PERIHP_NOC 126 +#define SRST_HSICPHY 127 + +/* cru_softrst_con8 */ +#define SRST_A_PCIE 128 +#define SRST_P_PCIE 129 +#define SRST_PCIE_CORE 130 +#define SRST_PCIE_MGMT 131 +#define SRST_PCIE_MGMT_STICKY 132 +#define SRST_PCIE_PIPE 133 +#define SRST_PCIE_PM 134 +#define SRST_PCIEPHY 135 +#define SRST_A_GMAC_NOC 136 +#define SRST_A_GMAC 137 +#define SRST_P_GMAC_NOC 138 +#define SRST_P_GMAC_GRF 140 +#define SRST_HSICPHY_POR 142 +#define SRST_HSICPHY_UTMI 143 + +/* cru_softrst_con9 */ +#define SRST_USB2PHY0_POR 144 +#define SRST_USB2PHY0_UTMI_PORT0 145 +#define SRST_USB2PHY0_UTMI_PORT1 146 +#define SRST_USB2PHY0_EHCIPHY 147 +#define SRST_UPHY0_PIPE_L00 148 +#define SRST_UPHY0 149 +#define SRST_UPHY0_TCPDPWRUP 150 +#define SRST_USB2PHY1_POR 152 +#define SRST_USB2PHY1_UTMI_PORT0 153 +#define SRST_USB2PHY1_UTMI_PORT1 154 +#define SRST_USB2PHY1_EHCIPHY 155 +#define SRST_UPHY1_PIPE_L00 156 +#define SRST_UPHY1 157 +#define SRST_UPHY1_TCPDPWRUP 158 + +/* cru_softrst_con10 */ +#define SRST_A_PERILP0_NOC 160 +#define SRST_A_DCF 161 +#define SRST_GIC500 162 +#define SRST_DMAC0_PERILP0 163 +#define SRST_DMAC1_PERILP0 164 +#define SRST_TZMA 165 +#define SRST_INTMEM 166 +#define SRST_ADB400_MST0 167 +#define SRST_ADB400_MST1 168 +#define SRST_ADB400_SLV0 169 +#define SRST_ADB400_SLV1 170 +#define SRST_H_PERILP0 171 +#define SRST_H_PERILP0_NOC 172 +#define SRST_ROM 173 +#define SRST_CRYPTO_S 174 +#define SRST_CRYPTO_M 175 + +/* cru_softrst_con11 */ +#define SRST_P_DCF 176 +#define SRST_CM0S_NOC 177 +#define SRST_CM0S 178 +#define SRST_CM0S_DBG 179 +#define SRST_CM0S_PO 180 +#define SRST_CRYPTO 181 +#define SRST_P_PERILP1_SGRF 182 +#define SRST_P_PERILP1_GRF 183 +#define SRST_CRYPTO1_S 184 +#define SRST_CRYPTO1_M 185 +#define SRST_CRYPTO1 186 +#define SRST_GIC_NOC 188 +#define SRST_SD_NOC 189 +#define SRST_SDIOAUDIO_BRG 190 + +/* cru_softrst_con12 */ +#define SRST_H_PERILP1 192 +#define SRST_H_PERILP1_NOC 193 +#define SRST_H_I2S0_8CH 194 +#define SRST_H_I2S1_8CH 195 +#define SRST_H_I2S2_8CH 196 +#define SRST_H_SPDIF_8CH 197 +#define SRST_P_PERILP1_NOC 198 +#define SRST_P_EFUSE_1024 199 +#define SRST_P_EFUSE_1024S 200 +#define SRST_P_I2C0 201 +#define SRST_P_I2C1 202 +#define SRST_P_I2C2 203 +#define SRST_P_I2C3 204 +#define SRST_P_I2C4 205 +#define SRST_P_I2C5 206 +#define SRST_P_MAILBOX0 207 + +/* cru_softrst_con13 */ +#define SRST_P_UART0 208 +#define SRST_P_UART1 209 +#define SRST_P_UART2 210 +#define SRST_P_UART3 211 +#define SRST_P_SARADC 212 +#define SRST_P_TSADC 213 +#define SRST_P_SPI0 214 +#define SRST_P_SPI1 215 +#define SRST_P_SPI2 216 +#define SRST_P_SPI3 217 +#define SRST_P_SPI4 218 +#define SRST_SPI0 219 +#define SRST_SPI1 220 +#define SRST_SPI2 221 +#define SRST_SPI3 222 +#define SRST_SPI4 223 + +/* cru_softrst_con14 */ +#define SRST_I2S0_8CH 224 +#define SRST_I2S1_8CH 225 +#define SRST_I2S2_8CH 226 +#define SRST_SPDIF_8CH 227 +#define SRST_UART0 228 +#define SRST_UART1 229 +#define SRST_UART2 230 +#define SRST_UART3 231 +#define SRST_TSADC 232 +#define SRST_I2C0 233 +#define SRST_I2C1 234 +#define SRST_I2C2 235 +#define SRST_I2C3 236 +#define SRST_I2C4 237 +#define SRST_I2C5 238 +#define SRST_SDIOAUDIO_NOC 239 + +/* cru_softrst_con15 */ +#define SRST_A_VIO_NOC 240 +#define SRST_A_HDCP_NOC 241 +#define SRST_A_HDCP 242 +#define SRST_H_HDCP_NOC 243 +#define SRST_H_HDCP 244 +#define SRST_P_HDCP_NOC 245 +#define SRST_P_HDCP 246 +#define SRST_P_HDMI_CTRL 247 +#define SRST_P_DP_CTRL 248 +#define SRST_S_DP_CTRL 249 +#define SRST_C_DP_CTRL 250 +#define SRST_P_MIPI_DSI0 251 +#define SRST_P_MIPI_DSI1 252 +#define SRST_DP_CORE 253 +#define SRST_DP_I2S 254 + +/* cru_softrst_con16 */ +#define SRST_GASKET 256 +#define SRST_VIO_GRF 258 +#define SRST_DPTX_SPDIF_REC 259 +#define SRST_HDMI_CTRL 260 +#define SRST_HDCP_CTRL 261 +#define SRST_A_ISP0_NOC 262 +#define SRST_A_ISP1_NOC 263 +#define SRST_H_ISP0_NOC 266 +#define SRST_H_ISP1_NOC 267 +#define SRST_H_ISP0 268 +#define SRST_H_ISP1 269 +#define SRST_ISP0 270 +#define SRST_ISP1 271 + +/* cru_softrst_con17 */ +#define SRST_A_VOP0_NOC 272 +#define SRST_A_VOP1_NOC 273 +#define SRST_A_VOP0 274 +#define SRST_A_VOP1 275 +#define SRST_H_VOP0_NOC 276 +#define SRST_H_VOP1_NOC 277 +#define SRST_H_VOP0 278 +#define SRST_H_VOP1 279 +#define SRST_D_VOP0 280 +#define SRST_D_VOP1 281 +#define SRST_VOP0_PWM 282 +#define SRST_VOP1_PWM 283 +#define SRST_P_EDP_NOC 284 +#define SRST_P_EDP_CTRL 285 + +/* cru_softrst_con18 */ +#define SRST_A_GPU 288 +#define SRST_A_GPU_NOC 289 +#define SRST_A_GPU_GRF 290 +#define SRST_PVTM_GPU 291 +#define SRST_A_USB3_NOC 292 +#define SRST_A_USB3_OTG0 293 +#define SRST_A_USB3_OTG1 294 +#define SRST_A_USB3_GRF 295 +#define SRST_PMU 296 + +/* cru_softrst_con19 */ +#define SRST_P_TIMER0_5 304 +#define SRST_TIMER0 305 +#define SRST_TIMER1 306 +#define SRST_TIMER2 307 +#define SRST_TIMER3 308 +#define SRST_TIMER4 309 +#define SRST_TIMER5 310 +#define SRST_P_TIMER6_11 311 +#define SRST_TIMER6 312 +#define SRST_TIMER7 313 +#define SRST_TIMER8 314 +#define SRST_TIMER9 315 +#define SRST_TIMER10 316 +#define SRST_TIMER11 317 +#define SRST_P_INTR_ARB_PMU 318 +#define SRST_P_ALIVE_SGRF 319 + +/* cru_softrst_con20 */ +#define SRST_P_GPIO2 320 +#define SRST_P_GPIO3 321 +#define SRST_P_GPIO4 322 +#define SRST_P_GRF 323 +#define SRST_P_ALIVE_NOC 324 +#define SRST_P_WDT0 325 +#define SRST_P_WDT1 326 +#define SRST_P_INTR_ARB 327 +#define SRST_P_UPHY0_DPTX 328 +#define SRST_P_UPHY0_APB 330 +#define SRST_P_UPHY0_TCPHY 332 +#define SRST_P_UPHY1_TCPHY 333 +#define SRST_P_UPHY0_TCPDCTRL 334 +#define SRST_P_UPHY1_TCPDCTRL 335 + +/* pmu soft-reset indices */ + +/* pmu_cru_softrst_con0 */ +#define SRST_P_NOC 0 +#define SRST_P_INTMEM 1 +#define SRST_H_CM0S 2 +#define SRST_H_CM0S_NOC 3 +#define SRST_DBG_CM0S 4 +#define SRST_PO_CM0S 5 +#define SRST_P_SPI6 6 +#define SRST_SPI6 7 +#define SRST_P_TIMER_0_1 8 +#define SRST_P_TIMER_0 9 +#define SRST_P_TIMER_1 10 +#define SRST_P_UART4 11 +#define SRST_UART4 12 +#define SRST_P_WDT 13 + +/* pmu_cru_softrst_con1 */ +#define SRST_P_I2C6 16 +#define SRST_P_I2C7 17 +#define SRST_P_I2C8 18 +#define SRST_P_MAILBOX 19 +#define SRST_P_RKPWM 20 +#define SRST_P_PMUGRF 21 +#define SRST_P_SGRF 22 +#define SRST_P_GPIO0 23 +#define SRST_P_GPIO1 24 +#define SRST_P_CRU 25 +#define SRST_P_INTR 26 +#define SRST_PVTM 27 +#define SRST_I2C6 28 +#define SRST_I2C7 29 +#define SRST_I2C8 30 + +#endif diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h index 302e9a35a2..7324d8a62d 100644 --- a/include/usb/dwc2_udc.h +++ b/include/usb/dwc2_udc.h @@ -12,12 +12,17 @@ #define PHY0_SLEEP (1 << 5) struct dwc2_plat_otg_data { + void *priv; + int phy_of_node; int (*phy_control)(int on); unsigned int regs_phy; unsigned int regs_otg; unsigned int usb_phy_ctrl; unsigned int usb_flags; unsigned int usb_gusbcfg; + unsigned int rx_fifo_sz; + unsigned int np_tx_fifo_sz; + unsigned int tx_fifo_sz; }; int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata); diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 72621fd095..0a072aa83c 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -56,6 +56,7 @@ struct spl_info { static struct spl_info spl_infos[] = { { "rk3036", "RK30", 0x1000 }, { "rk3288", "RK32", 0x8000 }, + { "rk3399", "RK33", 0x20000 }, }; static unsigned char rc4_key[16] = { |