diff options
| -rw-r--r-- | arch/arm/dts/Makefile | 3 | ||||
| -rw-r--r-- | arch/arm/dts/r8a77995-draak.dts | 124 | ||||
| -rw-r--r-- | arch/arm/mach-rmobile/Kconfig.64 | 6 | ||||
| -rw-r--r-- | board/renesas/draak/Kconfig | 15 | ||||
| -rw-r--r-- | board/renesas/draak/MAINTAINERS | 6 | ||||
| -rw-r--r-- | board/renesas/draak/Makefile | 9 | ||||
| -rw-r--r-- | board/renesas/draak/draak.c | 133 | ||||
| -rw-r--r-- | configs/r8a77995_draak_defconfig | 61 | ||||
| -rw-r--r-- | include/configs/draak.h | 47 |
9 files changed, 403 insertions, 1 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b3f62c44986..1c9ac1468b2 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -394,7 +394,8 @@ dtb-$(CONFIG_RCAR_GEN3) += \ r8a7795-salvator-x.dtb \ r8a7796-m3ulcb.dtb \ r8a7796-salvator-x.dtb \ - r8a77970-eagle.dtb + r8a77970-eagle.dtb \ + r8a77995-draak.dtb dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2l-evm.dtb \ diff --git a/arch/arm/dts/r8a77995-draak.dts b/arch/arm/dts/r8a77995-draak.dts new file mode 100644 index 00000000000..09de73b11db --- /dev/null +++ b/arch/arm/dts/r8a77995-draak.dts @@ -0,0 +1,124 @@ +/* + * Device Tree Source for the Draak board + * + * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2017 Glider bvba + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a77995.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Renesas Draak board based on r8a77995"; + compatible = "renesas,draak", "renesas,r8a77995"; + + aliases { + serial0 = &scif2; + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x18000000>; + }; +}; + +&extal_clk { + clock-frequency = <48000000>; +}; + +&pfc { + avb0_pins: avb { + mux { + groups = "avb0_link", "avb0_mdc", "avb0_mii"; + function = "avb0"; + }; + }; + + pwm0_pins: pwm0 { + groups = "pwm0_c"; + function = "pwm0"; + }; + + pwm1_pins: pwm1 { + groups = "pwm1_c"; + function = "pwm1"; + }; + + scif2_pins: scif2 { + groups = "scif2_data"; + function = "scif2"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&avb { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + phy-handle = <&phy0>; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio5>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pwm0 { + pinctrl-0 = <&pwm0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index f22cd5269ac..6112d79f0d7 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -21,6 +21,11 @@ choice prompt "Renesus ARM64 SoCs board select" optional +config TARGET_DRAAK + bool "Draak board" + help + Support for Renesas R-Car Gen3 Draak platform + config TARGET_EAGLE bool "Eagle board" help @@ -41,6 +46,7 @@ endchoice config SYS_SOC default "rmobile" +source "board/renesas/draak/Kconfig" source "board/renesas/eagle/Kconfig" source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig" diff --git a/board/renesas/draak/Kconfig b/board/renesas/draak/Kconfig new file mode 100644 index 00000000000..9106387bb99 --- /dev/null +++ b/board/renesas/draak/Kconfig @@ -0,0 +1,15 @@ +if TARGET_DRAAK + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "draak" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "draak" + +endif diff --git a/board/renesas/draak/MAINTAINERS b/board/renesas/draak/MAINTAINERS new file mode 100644 index 00000000000..1dbcc2811c5 --- /dev/null +++ b/board/renesas/draak/MAINTAINERS @@ -0,0 +1,6 @@ +DRAAK BOARD +M: Marek Vasut <marek.vasut+renesas@gmail.com> +S: Maintained +F: board/renesas/draak/ +F: include/configs/draak.h +F: configs/r8a77995_draak_defconfig diff --git a/board/renesas/draak/Makefile b/board/renesas/draak/Makefile new file mode 100644 index 00000000000..604522ebb16 --- /dev/null +++ b/board/renesas/draak/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/draak/Makefile +# +# Copyright (C) 2015 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := draak.o diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c new file mode 100644 index 00000000000..acdaaff72ae --- /dev/null +++ b/board/renesas/draak/draak.c @@ -0,0 +1,133 @@ +/* + * board/renesas/draak/draak.c + * This file is Draak board support. + * + * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <netdev.h> +#include <dm.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> +#include <asm/arch/sh_sdhi.h> +#include <i2c.h> +#include <mmc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define CPGWPCR 0xE6150904 +#define CPGWPR 0xE615090C + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + writel(0xA5A50000, CPGWPCR); + writel(0xFFFFFFFF, CPGWPR); +} + +#define GSX_MSTP112 BIT(12) /* 3DG */ +#define TMU0_MSTP125 BIT(25) /* secure */ +#define TMU1_MSTP124 BIT(24) /* non-secure */ +#define SCIF2_MSTP310 BIT(10) /* SCIF2 */ +#define DVFS_MSTP926 BIT(26) +#define HSUSB_MSTP704 BIT(4) /* HSUSB */ + +int board_early_init_f(void) +{ + /* TMU0,1 */ /* which use ? */ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); + +#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) + /* DVFS for reset */ + mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); +#endif + return 0; +} + +/* SYSC */ +/* R/- 32 Power status register 2(3DG) */ +#define SYSC_PWRSR2 0xE6180100 +/* -/W 32 Power resume control register 2 (3DG) */ +#define SYSC_PWRONCR2 0xE618010C + +/* HSUSB block registers */ +#define HSUSB_REG_LPSTS 0xE6590102 +#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) +#define HSUSB_REG_UGCTRL2 0xE6590184 +#define HSUSB_REG_UGCTRL2_USB0SEL 0x30 +#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10 + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; + + /* USB1 pull-up */ + setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); + + /* Configure the HSUSB block */ + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704); + /* Choice USB0SEL */ + clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, + HSUSB_REG_UGCTRL2_USB0SEL_EHCI); + /* low power status */ + setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); + + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +#define RST_BASE 0xE6160000 +#define RST_CA57RESCNT (RST_BASE + 0x40) +#define RST_CA53RESCNT (RST_BASE + 0x44) +#define RST_RSTOUTCR (RST_BASE + 0x58) +#define RST_CA57_CODE 0xA5A5000F +#define RST_CA53_CODE 0x5A5A000F + +void reset_cpu(ulong addr) +{ + unsigned long midr, cputype; + + asm volatile("mrs %0, midr_el1" : "=r" (midr)); + cputype = (midr >> 4) & 0xfff; + + if (cputype == 0xd03) + writel(RST_CA53_CODE, RST_CA53RESCNT); + else if (cputype == 0xd07) + writel(RST_CA57_CODE, RST_CA57RESCNT); + else + hang(); +} diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig new file mode 100644 index 00000000000..6998ce553df --- /dev/null +++ b/configs/r8a77995_draak_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARM=y +CONFIG_ARCH_RMOBILE=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_RCAR_GEN3=y +CONFIG_R8A77995=y +CONFIG_TARGET_DRAAK=y +CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak" +CONFIG_SMBIOS_PRODUCT_NAME="" +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" +CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb" +CONFIG_VERSION_VARIABLE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_DM_GPIO=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y +CONFIG_DM_MMC=y +CONFIG_MMC_UNIPHIER=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_RENESAS_RPC_HF=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_RENESAS_RAVB=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_PFC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SCIF_CONSOLE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_SMBIOS_MANUFACTURER="" diff --git a/include/configs/draak.h b/include/configs/draak.h new file mode 100644 index 00000000000..392ba4a6ba3 --- /dev/null +++ b/include/configs/draak.h @@ -0,0 +1,47 @@ +/* + * include/configs/draak.h + * This file is Draak board configuration. + * + * Copyright (C) 2015 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DRAAK_H +#define __DRAAK_H + +#undef DEBUG + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_NET_MULTI +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +/* XTAL_CLK : 33.33MHz */ +#define CONFIG_SYS_CLK_FREQ 33333333u + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 2 + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_MTD_DEVICE +#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CONFIG_CMD_CACHE + +#endif /* __DRAAK_H */ |