diff options
| -rw-r--r-- | board/freescale/mx51_bbg/mx51_bbg.c | 8 | ||||
| -rwxr-xr-x | board/freescale/mx53_ard/mx53_ard.c | 8 | ||||
| -rw-r--r-- | board/freescale/mx53_smd/mx53_smd.c | 8 | ||||
| -rw-r--r-- | board/freescale/mx6q_sabreauto/lowlevel_init.S | 28 | ||||
| -rw-r--r-- | board/freescale/mx6q_sabreauto/mx6q_sabreauto.c | 225 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/mx6/generic.c | 7 | ||||
| -rw-r--r-- | drivers/video/ipu_common.c | 9 | ||||
| -rw-r--r-- | drivers/video/ipu_regs.h | 89 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx6/mx6.h | 7 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx6/mx6_pins.h | 72 | ||||
| -rw-r--r-- | include/configs/mx6q_sabreauto.h | 32 | ||||
| -rw-r--r-- | include/ipu.h | 11 |
12 files changed, 441 insertions, 63 deletions
diff --git a/board/freescale/mx51_bbg/mx51_bbg.c b/board/freescale/mx51_bbg/mx51_bbg.c index 8508d3b1a7..ea0c447d9e 100644 --- a/board/freescale/mx51_bbg/mx51_bbg.c +++ b/board/freescale/mx51_bbg/mx51_bbg.c @@ -77,6 +77,7 @@ u32 mx51_io_base_addr; #ifdef CONFIG_VIDEO_MX5 extern unsigned char fsl_bmp_600x400[]; extern int fsl_bmp_600x400_size; +extern int g_ipu_hw_rev; #if defined(CONFIG_BMP_8BPP) short colormap[256]; @@ -889,6 +890,13 @@ void lcd_enable(void) int ret; unsigned int reg; + /* + * hw_rev 2: IPUV3DEX + * hw_rev 3: IPUV3M + * hw_rev 4: IPUV3H + */ + g_ipu_hw_rev = IPUV3_HW_REV_IPUV3DEX; + mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT4); mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, PAD_CTL_HYS_NONE | diff --git a/board/freescale/mx53_ard/mx53_ard.c b/board/freescale/mx53_ard/mx53_ard.c index 29fd1c6f55..2360d7c096 100755 --- a/board/freescale/mx53_ard/mx53_ard.c +++ b/board/freescale/mx53_ard/mx53_ard.c @@ -79,6 +79,7 @@ static enum boot_device boot_dev; #ifdef CONFIG_VIDEO_MX5 extern unsigned char fsl_bmp_600x400[]; extern int fsl_bmp_600x400_size; +extern int g_ipu_hw_rev; #if defined(CONFIG_BMP_8BPP) unsigned short colormap[256]; @@ -837,6 +838,13 @@ void lcd_enable(void) s = getenv("lvds_num"); di = simple_strtol(s, NULL, 10); + /* + * hw_rev 2: IPUV3DEX + * hw_rev 3: IPUV3M + * hw_rev 4: IPUV3H + */ + g_ipu_hw_rev = IPUV3_HW_REV_IPUV3M; + /* 200Hz PWM wave, 50% duty */ if (di == 1) { pwm1.enable_pwm_pad = enable_pwm1_pad; diff --git a/board/freescale/mx53_smd/mx53_smd.c b/board/freescale/mx53_smd/mx53_smd.c index b471a7b4db..aa8568beac 100644 --- a/board/freescale/mx53_smd/mx53_smd.c +++ b/board/freescale/mx53_smd/mx53_smd.c @@ -80,6 +80,7 @@ static enum boot_device boot_dev; #ifdef CONFIG_VIDEO_MX5 extern unsigned char fsl_bmp_600x400[]; extern int fsl_bmp_600x400_size; +extern int g_ipu_hw_rev; #if defined(CONFIG_BMP_8BPP) unsigned short colormap[256]; @@ -744,6 +745,13 @@ void lcd_enable(void) s = getenv("lvds_num"); di = simple_strtol(s, NULL, 10); + /* + * hw_rev 2: IPUV3DEX + * hw_rev 3: IPUV3M + * hw_rev 4: IPUV3H + */ + g_ipu_hw_rev = IPUV3_HW_REV_IPUV3M; + /* 20KHz PWM wave, 50% duty */ if (di == 1) { imx_pwm_config(pwm1, 25000, 50000); diff --git a/board/freescale/mx6q_sabreauto/lowlevel_init.S b/board/freescale/mx6q_sabreauto/lowlevel_init.S index fed880a81e..5da8199b68 100644 --- a/board/freescale/mx6q_sabreauto/lowlevel_init.S +++ b/board/freescale/mx6q_sabreauto/lowlevel_init.S @@ -34,6 +34,31 @@ /* AIPS setup - Only setup MPROTx registers. * The PACR default values are good.*/ .macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_ON_BASE_ADDR + ldr r1, =0x77777777 + str r1, [r0, #0x0] + str r1, [r0, #0x4] + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + str r1, [r0, #0x50] + + ldr r0, =AIPS2_ON_BASE_ADDR + ldr r1, =0x77777777 + str r1, [r0, #0x0] + str r1, [r0, #0x4] + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + str r1, [r0, #0x50] .endm /* init_aips */ .macro setup_pll pll, freq @@ -79,13 +104,12 @@ str r1, [r0, #CLKCTL_CCGR2] ldr r1, =0x3FF00000 str r1, [r0, #CLKCTL_CCGR3] - ldr r1, =0xF300 + ldr r1, =0xFFF300 str r1, [r0, #CLKCTL_CCGR4] ldr r1, =0xF0000C3 str r1, [r0, #CLKCTL_CCGR5] ldr r1, =0x3C0 str r1, [r0, #CLKCTL_CCGR6] - .endm .section ".text.init", "x" diff --git a/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c b/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c index e799b3d94d..c63ec4b288 100644 --- a/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c +++ b/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c @@ -27,6 +27,18 @@ #include <asm/arch/iomux-v3.h> #include <asm/errno.h> +#if defined(CONFIG_VIDEO_MX5) +#include <linux/list.h> +#include <linux/fb.h> +#include <linux/mxcfb.h> +#include <ipu.h> +#include <lcd.h> +#endif + +#if CONFIG_I2C_MXC +#include <i2c.h> +#endif + #ifdef CONFIG_CMD_MMC #include <mmc.h> #include <fsl_esdhc.h> @@ -50,6 +62,37 @@ DECLARE_GLOBAL_DATA_PTR; static u32 system_rev; static enum boot_device boot_dev; +#ifdef CONFIG_VIDEO_MX5 +extern unsigned char fsl_bmp_600x400[]; +extern int fsl_bmp_600x400_size; +extern int g_ipu_hw_rev; + +#if defined(CONFIG_BMP_8BPP) +unsigned short colormap[256]; +#elif defined(CONFIG_BMP_16BPP) +unsigned short colormap[65536]; +#else +unsigned short colormap[16777216]; +#endif + +static int di = 1; + + +extern int ipuv3_fb_init(struct fb_videomode *mode, int di, + int interface_pix_fmt, + ipu_di_clk_parent_t di_clk_parent, + int di_clk_val); + +static struct fb_videomode lvds_xga = { + "XGA", 60, 1024, 768, 15385, 220, 40, 21, 7, 60, 10, + FB_SYNC_EXT, + FB_VMODE_NONINTERLACED, + 0, +}; + +vidinfo_t panel_info; +#endif + static inline void setup_boot_device(void) { uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); @@ -228,6 +271,73 @@ static void setup_uart(void) mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_ROW0__UART4_RXD); } +#ifdef CONFIG_I2C_MXC +static void setup_i2c(unsigned int module_base) +{ + unsigned int reg; + + switch (module_base) { + case I2C1_BASE_ADDR: + /* i2c1 SDA */ + mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT8__I2C1_SDA); + + /* i2c1 SCL */ + mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT9__I2C1_SCL); + + /* Enable i2c clock */ + reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2); + reg |= 0xC0; + writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2); + + break; + case I2C2_BASE_ADDR: + /* i2c2 SDA */ + mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_ROW3__I2C2_SDA); + + /* i2c2 SCL */ + mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_COL3__I2C2_SCL); + + /* Enable i2c clock */ + reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2); + reg |= 0x300; + writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2); + + break; + case I2C3_BASE_ADDR: + /* GPIO_5 for I2C3_SCL */ + mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_5__I2C3_SCL); + + /* GPIO_16 for I2C3_SDA */ + mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_16__I2C3_SDA); + + /* Enable i2c clock */ + reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2); + reg |= 0xC00; + writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2); + + break; + default: + printf("Invalid I2C base: 0x%x\n", module_base); + break; + } +} + +void setup_lvds_poweron(void) +{ + uchar value; + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + i2c_read(0x1f, 3, 1, &value, 1); + value &= ~0x2; + i2c_write(0x1f, 3, 1, &value, 1); + + i2c_read(0x1f, 1, 1, &value, 1); + value |= 0x2; + i2c_write(0x1f, 1, 1, &value, 1); +} + +#endif + #define HW_OCOTP_MACn(n) (0x00000620 + (n) * 0x10) #ifdef CONFIG_MXC_FEC @@ -376,6 +486,104 @@ u32 get_ddr_delay(struct fsl_esdhc *cfg) #endif +#ifdef CONFIG_LCD +void lcd_enable(void) +{ + char *s; + int ret; + unsigned int reg; + + s = getenv("lvds_num"); + di = simple_strtol(s, NULL, 10); + + /* + * hw_rev 2: IPUV3DEX + * hw_rev 3: IPUV3M + * hw_rev 4: IPUV3H + */ + g_ipu_hw_rev = IPUV3_HW_REV_IPUV3H; + + /* set GPIO_9 to high so that backlight control could be high */ + mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_9__GPIO_1_9); + reg = readl(GPIO1_BASE_ADDR + GPIO_GDIR); + reg |= (1 << 9); + writel(reg, GPIO1_BASE_ADDR + GPIO_GDIR); + + reg = readl(GPIO1_BASE_ADDR + GPIO_DR); + reg |= (1 << 9); + writel(reg, GPIO1_BASE_ADDR + GPIO_DR); + + /* Enable IPU clock */ + if (di == 1) { + reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3); + reg |= 0xC033; + writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3); + } else { + reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3); + reg |= 0x300F; + writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3); + } + + ret = ipuv3_fb_init(&lvds_xga, di, IPU_PIX_FMT_RGB666, + DI_PCLK_LDB, 65000000); + if (ret) + puts("LCD cannot be configured\n"); + + reg = readl(ANATOP_BASE_ADDR + 0xF0); + reg &= ~0x00003F00; + reg |= 0x00001300; + writel(reg, ANATOP_BASE_ADDR + 0xF4); + + reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR); + reg &= ~0x00007E00; + reg |= 0x00003600; + writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR); + + reg = readl(CCM_BASE_ADDR + CLKCTL_CSCMR2); + reg |= 0x00000C00; + writel(reg, CCM_BASE_ADDR + CLKCTL_CSCMR2); + + reg = 0x0002A953; + writel(reg, CCM_BASE_ADDR + CLKCTL_CHSCCDR); + + if (di == 1) + writel(0x40C, IOMUXC_BASE_ADDR + 0x8); + else + writel(0x201, IOMUXC_BASE_ADDR + 0x8); +} +#endif + +#ifdef CONFIG_VIDEO_MX5 +void panel_info_init(void) +{ + panel_info.vl_bpix = LCD_BPP; + panel_info.vl_col = lvds_xga.xres; + panel_info.vl_row = lvds_xga.yres; + panel_info.cmap = colormap; +} +#endif + +#ifdef CONFIG_SPLASH_SCREEN +void setup_splash_image(void) +{ + char *s; + ulong addr; + + s = getenv("splashimage"); + + if (s != NULL) { + addr = simple_strtoul(s, NULL, 16); + +#if defined(CONFIG_ARCH_MMU) + addr = ioremap_nocache(iomem_to_phys(addr), + fsl_bmp_600x400_size); +#endif + memcpy((char *)addr, (char *)fsl_bmp_600x400, + fsl_bmp_600x400_size); + } +} +#endif + int board_init(void) { #ifdef CONFIG_MFG @@ -400,6 +608,23 @@ int board_init(void) setup_sata(); #endif + +#ifdef CONFIG_VIDEO_MX5 + +#ifdef CONFIG_I2C_MXC + setup_i2c(CONFIG_SYS_I2C_PORT); + /* Enable lvds power */ + setup_lvds_poweron(); +#endif + + panel_info_init(); + + gd->fb_base = CONFIG_FB_BASE; +#ifdef CONFIG_ARCH_MMU + gd->fb_base = ioremap_nocache(iomem_to_phys(gd->fb_base), 0); +#endif +#endif + return 0; } diff --git a/cpu/arm_cortexa8/mx6/generic.c b/cpu/arm_cortexa8/mx6/generic.c index fb0ef94135..f959b9598a 100644 --- a/cpu/arm_cortexa8/mx6/generic.c +++ b/cpu/arm_cortexa8/mx6/generic.c @@ -763,3 +763,10 @@ int arch_cpu_init(void) } #endif +void ipu_clk_enable(void) +{ +} + +void ipu_clk_disable(void) +{ +} diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c index 798f7d057a..79d87e3d69 100644 --- a/drivers/video/ipu_common.c +++ b/drivers/video/ipu_common.c @@ -36,6 +36,8 @@ #include <asm/errno.h> #include "ipu_regs.h" +int g_ipu_hw_rev; + extern struct mxc_ccm_reg *mxc_ccm; extern u32 *ipu_cpmem_base; @@ -392,6 +394,13 @@ int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val) #endif ipu_base = IPU_CTRL_BASE_ADDR; + /* base fixup */ + if (g_ipu_hw_rev == IPUV3_HW_REV_IPUV3H) /* IPUv3H */ + ipu_base += IPUV3H_REG_BASE; + else if (g_ipu_hw_rev == IPUV3_HW_REV_IPUV3M) /* IPUv3M */ + ipu_base += IPUV3M_REG_BASE; + else /* IPUv3D, v3E, v3EX */ + ipu_base += IPUV3DEX_REG_BASE; ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE); ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE); diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h index bfa10f5415..a60c2b8717 100644 --- a/drivers/video/ipu_regs.h +++ b/drivers/video/ipu_regs.h @@ -30,31 +30,60 @@ #ifndef __IPU_REGS_INCLUDED__ #define __IPU_REGS_INCLUDED__ +/* + * hw_rev 2: IPUV3DEX + * hw_rev 3: IPUV3M + * hw_rev 4: IPUV3H + */ +extern int g_ipu_hw_rev; + #define IPU_DISP0_BASE 0x00000000 #define IPU_MCU_T_DEFAULT 8 -#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25) -#define IPU_CM_REG_BASE 0x1E000000 -#define IPU_STAT_REG_BASE 0x1E000200 -#define IPU_IDMAC_REG_BASE 0x1E008000 -#define IPU_ISP_REG_BASE 0x1E010000 -#define IPU_DP_REG_BASE 0x1E018000 -#define IPU_IC_REG_BASE 0x1E020000 -#define IPU_IRT_REG_BASE 0x1E028000 -#define IPU_CSI0_REG_BASE 0x1E030000 -#define IPU_CSI1_REG_BASE 0x1E038000 -#define IPU_DI0_REG_BASE 0x1E040000 -#define IPU_DI1_REG_BASE 0x1E048000 -#define IPU_SMFC_REG_BASE 0x1E050000 -#define IPU_DC_REG_BASE 0x1E058000 -#define IPU_DMFC_REG_BASE 0x1E060000 -#define IPU_CPMEM_REG_BASE 0x1F000000 -#define IPU_LUT_REG_BASE 0x1F020000 -#define IPU_SRM_REG_BASE 0x1F040000 -#define IPU_TPM_REG_BASE 0x1F060000 -#define IPU_DC_TMPL_REG_BASE 0x1F080000 -#define IPU_ISP_TBPR_REG_BASE 0x1F0C0000 -#define IPU_VDI_REG_BASE 0x1E068000 - +#define IPU_DISP1_BASE ({g_ipu_hw_rev < 4 ? \ + (IPU_MCU_T_DEFAULT << 25) : \ + (0x00000000); }) +#define IPUV3DEX_REG_BASE 0x1E000000 +#define IPUV3M_REG_BASE 0x1E000000 +#define IPUV3H_REG_BASE 0x00200000 + +#define IPU_CM_REG_BASE 0x00000000 +#define IPU_STAT_REG_BASE 0x00000200 +#define IPU_IDMAC_REG_BASE 0x00008000 +#define IPU_ISP_REG_BASE 0x00010000 +#define IPU_DP_REG_BASE 0x00018000 +#define IPU_IC_REG_BASE 0x00020000 +#define IPU_IRT_REG_BASE 0x00028000 +#define IPU_CSI0_REG_BASE 0x00030000 +#define IPU_CSI1_REG_BASE 0x00038000 +#define IPU_DI0_REG_BASE 0x00040000 +#define IPU_DI1_REG_BASE 0x00048000 +#define IPU_SMFC_REG_BASE 0x00050000 +#define IPU_DC_REG_BASE 0x00058000 +#define IPU_DMFC_REG_BASE 0x00060000 +#define IPU_VDI_REG_BASE 0x00068000 +#define IPU_CPMEM_REG_BASE ({g_ipu_hw_rev >= 4 ? \ + (0x00100000) : \ + (0x01000000); }) +#define IPU_LUT_REG_BASE ({g_ipu_hw_rev >= 4 ? \ + (0x00120000) : \ + (0x01020000); }) + +#define IPU_SRM_REG_BASE ({g_ipu_hw_rev >= 4 ? \ + (0x00140000) : \ + (0x01040000); }) +#define IPU_TPM_REG_BASE ({g_ipu_hw_rev >= 4 ? \ + (0x00160000) : \ + (0x01060000); }) +#define IPU_DC_TMPL_REG_BASE ({g_ipu_hw_rev >= 4 ? \ + (0x00180000) : \ + (0x01080000); }) +#define IPU_ISP_TBPR_REG_BASE ({g_ipu_hw_rev >= 4 ? \ + (0x001C0000) : \ + (0x010C0000); }) + +#define IPU_DISP_REG_BASE_ADDR ({g_ipu_hw_rev >= 4 ? \ + (IPU_CTRL_BASE_ADDR + IPUV3H_REG_BASE) : \ + (IPU_CTRL_BASE_ADDR + IPUV3M_REG_BASE); }) extern u32 *ipu_dc_tmpl_reg; @@ -303,7 +332,7 @@ struct ipu_dmfc { u32 stat; }; -#define IPU_CM_REG ((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \ +#define IPU_CM_REG ((struct ipu_cm *)(IPU_DISP_REG_BASE_ADDR + \ IPU_CM_REG_BASE)) #define IPU_CONF (&IPU_CM_REG->conf) #define IPU_SRM_PRI1 (&IPU_CM_REG->srm_pri1) @@ -318,7 +347,7 @@ struct ipu_dmfc { #define IPU_GPR (&IPU_CM_REG->gpr) #define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32]) -#define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \ +#define IPU_STAT ((struct ipu_stat *)(IPU_DISP_REG_BASE_ADDR + \ IPU_STAT_REG_BASE)) #define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32]) #define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32]) @@ -326,14 +355,14 @@ struct ipu_dmfc { #define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1]) -#define IDMAC_REG ((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \ +#define IDMAC_REG ((struct ipu_idmac *)(IPU_DISP_REG_BASE_ADDR + \ IPU_IDMAC_REG_BASE)) #define IDMAC_CONF (&IDMAC_REG->conf) #define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[ch / 32]) #define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[ch / 32]) #define IDMAC_WM_EN(ch) (&IDMAC_REG->wm_en[ch / 32]) -#define DI_REG(di) ((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \ +#define DI_REG(di) ((struct ipu_di *)(IPU_DISP_REG_BASE_ADDR + \ ((di == 1) ? IPU_DI1_REG_BASE : \ IPU_DI0_REG_BASE))) #define DI_GENERAL(di) (&DI_REG(di)->general) @@ -349,7 +378,7 @@ struct ipu_dmfc { #define DI_POL(di) (&DI_REG(di)->pol) #define DI_SCR_CONF(di) (&DI_REG(di)->scr_conf) -#define DMFC_REG ((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \ +#define DMFC_REG ((struct ipu_dmfc *)(IPU_DISP_REG_BASE_ADDR + \ IPU_DMFC_REG_BASE)) #define DMFC_WR_CHAN (&DMFC_REG->wr_chan) #define DMFC_WR_CHAN_DEF (&DMFC_REG->wr_chan_def) @@ -359,7 +388,7 @@ struct ipu_dmfc { #define DMFC_IC_CTRL (&DMFC_REG->ic_ctrl) -#define DC_REG ((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \ +#define DC_REG ((struct ipu_dc *)(IPU_DISP_REG_BASE_ADDR + \ IPU_DC_REG_BASE)) #define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[n / 2]) #define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[n / 2]) @@ -402,7 +431,7 @@ static inline struct ipu_dc_ch *dc_ch_offset(int ch) #define DP_ASYNC0 0x60 #define DP_ASYNC1 0xBC -#define DP_REG ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \ +#define DP_REG ((struct ipu_dp *)(IPU_DISP_REG_BASE_ADDR + \ IPU_DP_REG_BASE)) #define DP_COM_CONF(flow) (&DP_REG->com_conf_sync) #define DP_GRAPH_WIND_CTRL(flow) (&DP_REG->graph_wind_ctrl_sync) diff --git a/include/asm-arm/arch-mx6/mx6.h b/include/asm-arm/arch-mx6/mx6.h index 772290a876..1a984de8e8 100644 --- a/include/asm-arm/arch-mx6/mx6.h +++ b/include/asm-arm/arch-mx6/mx6.h @@ -65,6 +65,11 @@ * @ingroup MSL_MX6 */ +/* + * IPU + */ +#define IPU_CTRL_BASE_ADDR 0x02400000 + /*! * Register an interrupt handler for the SMN as well as the SCC. In some * implementations, the SMN is not connected at all, and in others, it is @@ -575,7 +580,7 @@ #define CLKCTL_CS1CDR 0x28 #define CLKCTL_CS2CDR 0x2C #define CLKCTL_CDCDR 0x30 -#define CLKCTL_CHSCDR 0x34 +#define CLKCTL_CHSCCDR 0x34 #define CLKCTL_CSCDR2 0x38 #define CLKCTL_CSCDR3 0x3C #define CLKCTL_CSCDR4 0x40 diff --git a/include/asm-arm/arch-mx6/mx6_pins.h b/include/asm-arm/arch-mx6/mx6_pins.h index f64473a3f4..539231b509 100644 --- a/include/asm-arm/arch-mx6/mx6_pins.h +++ b/include/asm-arm/arch-mx6/mx6_pins.h @@ -55,6 +55,18 @@ typedef enum iomux_config { PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define MX6Q_I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define MX6Q_PWM_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED| \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define MX6Q_HIGH_DRV (PAD_CTL_DSE_120ohm) + #define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \ IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0) #define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \ @@ -254,7 +266,7 @@ typedef enum iomux_config { #define _MX6Q_PAD_EIM_EB2__GPIO_2_30 \ IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0) #define _MX6Q_PAD_EIM_EB2__I2C2_SCL \ - IOMUX_PAD(0x03A0, 0x008C, 6, 0x08A0, 0, 0) + IOMUX_PAD(0x03A0, 0x008C, 6 | IOMUX_CONFIG_SION, 0x08A0, 0, 0) #define _MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \ IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0) @@ -271,7 +283,7 @@ typedef enum iomux_config { #define _MX6Q_PAD_EIM_D16__GPIO_3_16 \ IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0) #define _MX6Q_PAD_EIM_D16__I2C2_SDA \ - IOMUX_PAD(0x03A4, 0x0090, 6, 0x08A4, 0, 0) + IOMUX_PAD(0x03A4, 0x0090, 6 | IOMUX_CONFIG_SION, 0x08A4, 0, 0) #define _MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \ IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0) @@ -286,7 +298,7 @@ typedef enum iomux_config { #define _MX6Q_PAD_EIM_D17__GPIO_3_17 \ IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0) #define _MX6Q_PAD_EIM_D17__I2C3_SCL \ - IOMUX_PAD(0x03A8, 0x0094, 6, 0x08A8, 0, 0) + IOMUX_PAD(0x03A8, 0x0094, 6 | IOMUX_CONFIG_SION, 0x08A8, 0, 0) #define _MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \ IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0) @@ -303,7 +315,7 @@ typedef enum iomux_config { #define _MX6Q_PAD_EIM_D18__GPIO_3_18 \ IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0) #define _MX6Q_PAD_EIM_D18__I2C3_SDA \ - IOMUX_PAD(0x03AC, 0x0098, 6, 0x08AC, 0, 0) + IOMUX_PAD(0x03AC, 0x0098, 6 | IOMUX_CONFIG_SION, 0x08AC, 0, 0) #define _MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \ IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0) @@ -354,7 +366,7 @@ typedef enum iomux_config { #define _MX6Q_PAD_EIM_D21__GPIO_3_21 \ IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0) #define _MX6Q_PAD_EIM_D21__I2C1_SCL \ - IOMUX_PAD(0x03B8, 0x00A4, 6, 0x0898, 0, 0) + IOMUX_PAD(0x03B8, 0x00A4, 6 | IOMUX_CONFIG_SION, 0x0898, 0, 0) #define _MX6Q_PAD_EIM_D21__SPDIF_IN1 \ IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0) @@ -490,7 +502,7 @@ typedef enum iomux_config { #define _MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \ IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0) #define _MX6Q_PAD_EIM_D28__I2C1_SDA \ - IOMUX_PAD(0x03D8, 0x00C4, 1, 0x089C, 0, 0) + IOMUX_PAD(0x03D8, 0x00C4, 1 | IOMUX_CONFIG_SION, 0x089C, 0, 0) #define _MX6Q_PAD_EIM_D28__ECSPI4_MOSI \ IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0) #define _MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \ @@ -2154,7 +2166,7 @@ typedef enum iomux_config { #define _MX6Q_PAD_KEY_COL3__KPP_COL_3 \ IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0) #define _MX6Q_PAD_KEY_COL3__I2C2_SCL \ - IOMUX_PAD(0x05E0, 0x0210, 4, 0x08A0, 1, 0) + IOMUX_PAD(0x05E0, 0x0210, 4 | IOMUX_CONFIG_SION, 0x08A0, 1, 0) #define _MX6Q_PAD_KEY_COL3__GPIO_4_12 \ IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0) #define _MX6Q_PAD_KEY_COL3__SPDIF_IN1 \ @@ -2171,7 +2183,7 @@ typedef enum iomux_config { #define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \ IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0) #define _MX6Q_PAD_KEY_ROW3__I2C2_SDA \ - IOMUX_PAD(0x05E4, 0x0214, 4, 0x08A4, 1, 0) + IOMUX_PAD(0x05E4, 0x0214, 4 | IOMUX_CONFIG_SION, 0x08A4, 1, 0) #define _MX6Q_PAD_KEY_ROW3__GPIO_4_13 \ IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0) #define _MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \ @@ -2267,7 +2279,7 @@ typedef enum iomux_config { #define _MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \ IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0) #define _MX6Q_PAD_GPIO_3__I2C3_SCL \ - IOMUX_PAD(0x05FC, 0x022C, 2, 0x08A8, 1, 0) + IOMUX_PAD(0x05FC, 0x022C, 2 | IOMUX_CONFIG_SION, 0x08A8, 1, 0) #define _MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \ IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0) #define _MX6Q_PAD_GPIO_3__CCM_CLKO2 \ @@ -2284,7 +2296,7 @@ typedef enum iomux_config { #define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \ IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0) #define _MX6Q_PAD_GPIO_6__I2C3_SDA \ - IOMUX_PAD(0x0600, 0x0230, 2, 0x08AC, 1, 0) + IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0) #define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \ IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0) #define _MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \ @@ -2343,7 +2355,7 @@ typedef enum iomux_config { #define _MX6Q_PAD_GPIO_5__GPIO_1_5 \ IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0) #define _MX6Q_PAD_GPIO_5__I2C3_SCL \ - IOMUX_PAD(0x060C, 0x023C, 6, 0x08A8, 2, 0) + IOMUX_PAD(0x060C, 0x023C, 6 | IOMUX_CONFIG_SION, 0x08A8, 2, 0) #define _MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \ IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0) @@ -2398,7 +2410,7 @@ typedef enum iomux_config { #define _MX6Q_PAD_GPIO_16__GPIO_7_11 \ IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0) #define _MX6Q_PAD_GPIO_16__I2C3_SDA \ - IOMUX_PAD(0x0618, 0x0248, 6, 0x08AC, 2, 0) + IOMUX_PAD(0x0618, 0x0248, 6 | IOMUX_CONFIG_SION, 0x08AC, 2, 0) #define _MX6Q_PAD_GPIO_16__SJC_DE_B \ IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0) @@ -2586,7 +2598,7 @@ typedef enum iomux_config { #define _MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \ IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0) #define _MX6Q_PAD_CSI0_DAT8__I2C1_SDA \ - IOMUX_PAD(0x0648, 0x0278, 4, 0x089C, 1, 0) + IOMUX_PAD(0x0648, 0x0278, 4 | IOMUX_CONFIG_SION, 0x089C, 1, 0) #define _MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \ IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0) #define _MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \ @@ -2603,7 +2615,7 @@ typedef enum iomux_config { #define _MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \ IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0) #define _MX6Q_PAD_CSI0_DAT9__I2C1_SCL \ - IOMUX_PAD(0x064C, 0x027C, 4, 0x0898, 1, 0) + IOMUX_PAD(0x064C, 0x027C, 4 | IOMUX_CONFIG_SION, 0x0898, 1, 0) #define _MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \ IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0) #define _MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \ @@ -3755,7 +3767,7 @@ typedef enum iomux_config { #define MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 (_MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL (_MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_EB2__GPIO_2_30 (_MX6Q_PAD_EIM_EB2__GPIO_2_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_EB2__I2C2_SCL (_MX6Q_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB2__I2C2_SCL (_MX6Q_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 (_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -3764,7 +3776,7 @@ typedef enum iomux_config { #define MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 (_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA (_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D16__GPIO_3_16 (_MX6Q_PAD_EIM_D16__GPIO_3_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D16__I2C2_SDA (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D16__I2C2_SDA (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D17__ECSPI1_MISO (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -3772,7 +3784,7 @@ typedef enum iomux_config { #define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK (_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT (_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D17__GPIO_3_17 (_MX6Q_PAD_EIM_D17__GPIO_3_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D17__I2C3_SCL (_MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D17__I2C3_SCL (_MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 (_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -3781,7 +3793,7 @@ typedef enum iomux_config { #define MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 (_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS (_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D18__GPIO_3_18 (_MX6Q_PAD_EIM_D18__GPIO_3_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D18__I2C3_SDA (_MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D18__I2C3_SDA (_MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 (_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -3808,7 +3820,7 @@ typedef enum iomux_config { #define MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 (_MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC (_MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D21__GPIO_3_21 (_MX6Q_PAD_EIM_D21__GPIO_3_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D21__I2C1_SCL (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D21__I2C1_SCL (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_EIM_D21__SPDIF_IN1 (_MX6Q_PAD_EIM_D21__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 (_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -3880,7 +3892,7 @@ typedef enum iomux_config { #define MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 (_MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D28__I2C1_SDA (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D28__I2C1_SDA (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_EIM_D28__ECSPI4_MOSI (_MX6Q_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 (_MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D28__UART2_CTS (_MX6Q_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) @@ -4809,7 +4821,7 @@ typedef enum iomux_config { #define MX6Q_PAD_KEY_COL3__ENET_CRS (_MX6Q_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL (_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_KEY_COL3__KPP_COL_3 (_MX6Q_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_COL3__I2C2_SCL (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL3__I2C2_SCL (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_KEY_COL3__GPIO_4_12 (_MX6Q_PAD_KEY_COL3__GPIO_4_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_KEY_COL3__SPDIF_IN1 (_MX6Q_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 (_MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -4818,7 +4830,7 @@ typedef enum iomux_config { #define MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK (_MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA (_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_KEY_ROW3__KPP_ROW_3 (_MX6Q_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_KEY_ROW3__I2C2_SDA (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW3__I2C2_SDA (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_KEY_ROW3__GPIO_4_13 (_MX6Q_PAD_KEY_ROW3__GPIO_4_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT (_MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) #define MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 (_MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -4862,14 +4874,14 @@ typedef enum iomux_config { #define MX6Q_PAD_GPIO_9__WDOG1_WDOG_B (_MX6Q_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_GPIO_9__KPP_COL_6 (_MX6Q_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_GPIO_9__CCM_REF_EN_B (_MX6Q_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_9__PWM1_PWMO (_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_9__GPIO_1_9 (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_9__PWM1_PWMO (_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(MX6Q_PWM_PAD_CTRL)) +#define MX6Q_PAD_GPIO_9__GPIO_1_9 (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(MX6Q_HIGH_DRV)) #define MX6Q_PAD_GPIO_9__USDHC1_WP (_MX6Q_PAD_GPIO_9__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) #define MX6Q_PAD_GPIO_9__SRC_EARLY_RST (_MX6Q_PAD_GPIO_9__SRC_EARLY_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_GPIO_3__ESAI1_HCKR (_MX6Q_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 (_MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_3__I2C3_SCL (_MX6Q_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_3__I2C3_SCL (_MX6Q_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT (_MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_GPIO_3__CCM_CLKO2 (_MX6Q_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_GPIO_3__GPIO_1_3 (_MX6Q_PAD_GPIO_3__GPIO_1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -4878,7 +4890,7 @@ typedef enum iomux_config { #define MX6Q_PAD_GPIO_6__ESAI1_SCKT (_MX6Q_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_6__I2C3_SDA (_MX6Q_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_6__I2C3_SDA (_MX6Q_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 (_MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB (_MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_GPIO_6__GPIO_1_6 (_MX6Q_PAD_GPIO_6__GPIO_1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -4909,7 +4921,7 @@ typedef enum iomux_config { #define MX6Q_PAD_GPIO_5__CCM_CLKO (_MX6Q_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 (_MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_GPIO_5__GPIO_1_5 (_MX6Q_PAD_GPIO_5__GPIO_1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_5__I2C3_SCL (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_5__I2C3_SCL (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_GPIO_5__CHEETAH_EVENTI (_MX6Q_PAD_GPIO_5__CHEETAH_EVENTI | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 (_MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -4938,7 +4950,7 @@ typedef enum iomux_config { #define MX6Q_PAD_GPIO_16__USDHC1_LCTL (_MX6Q_PAD_GPIO_16__USDHC1_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) #define MX6Q_PAD_GPIO_16__SPDIF_IN1 (_MX6Q_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_GPIO_16__GPIO_7_11 (_MX6Q_PAD_GPIO_16__GPIO_7_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_GPIO_16__I2C3_SDA (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_16__I2C3_SDA (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_GPIO_16__SJC_DE_B (_MX6Q_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_GPIO_17__ESAI1_TX0 (_MX6Q_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -5038,7 +5050,7 @@ typedef enum iomux_config { #define MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 (_MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK (_MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_CSI0_DAT8__KPP_COL_7 (_MX6Q_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA (_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA (_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_CSI0_DAT8__GPIO_5_26 (_MX6Q_PAD_CSI0_DAT8__GPIO_5_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 (_MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 (_MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -5047,7 +5059,7 @@ typedef enum iomux_config { #define MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 (_MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI (_MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 (_MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL (_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL (_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_CSI0_DAT9__GPIO_5_27 (_MX6Q_PAD_CSI0_DAT9__GPIO_5_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 (_MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 (_MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) diff --git a/include/configs/mx6q_sabreauto.h b/include/configs/mx6q_sabreauto.h index c310155aea..ed943a37b1 100644 --- a/include/configs/mx6q_sabreauto.h +++ b/include/configs/mx6q_sabreauto.h @@ -88,6 +88,8 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_DNS +#define CONFIG_CMD_I2C + /* Enable below configure when supporting nand */ #define CONFIG_CMD_MMC @@ -166,6 +168,17 @@ #define CONFIG_NETMASK 255.255.255.0 /* + * I2C Configs + */ +#ifdef CONFIG_CMD_I2C + #define CONFIG_HARD_I2C 1 + #define CONFIG_I2C_MXC 1 + #define CONFIG_SYS_I2C_PORT I2C3_BASE_ADDR + #define CONFIG_SYS_I2C_SPEED 100000 + #define CONFIG_SYS_I2C_SLAVE 0x1f +#endif + +/* * MMC Configs */ #ifdef CONFIG_CMD_MMC @@ -245,4 +258,23 @@ #else #define CONFIG_ENV_IS_NOWHERE 1 #endif + +#ifdef CONFIG_SPLASH_SCREEN + /* + * Framebuffer and LCD + */ + #define CONFIG_LCD + #define CONFIG_IPU_V3H + #define CONFIG_VIDEO_MX5 + #define CONFIG_IPU_CLKRATE 260000000 + #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE + #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE + #define CONFIG_SYS_CONSOLE_IS_IN_ENV + #define LCD_BPP LCD_COLOR16 + #define CONFIG_CMD_BMP + #define CONFIG_BMP_8BPP + #define CONFIG_FB_BASE (TEXT_BASE + 0x300000) + #define CONFIG_SPLASH_SCREEN_ALIGN + #define CONFIG_SYS_WHITE_ON_BLACK +#endif #endif /* __CONFIG_H */ diff --git a/include/ipu.h b/include/ipu.h index 94e551fa19..864b330acb 100644 --- a/include/ipu.h +++ b/include/ipu.h @@ -187,6 +187,17 @@ typedef enum { IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER, } ipu_buffer_t; + +/* + * Enumeration of version of IPU V3 . + */ +typedef enum { + IPUV3_HW_REV_IPUV3DEX = 2, /*IPUv3D, IPUv3E IPUv3EX */ + IPUV3_HW_REV_IPUV3M = 3, /*IPUv3M */ + IPUV3_HW_REV_IPUV3H = 4, /*IPUv3H */ +} ipu3_hw_rev_t; + + #define IPU_PANEL_SERIAL 1 #define IPU_PANEL_PARALLEL 2 |