diff options
34 files changed, 803 insertions, 2758 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 62b013f744..b57140036e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -78,10 +78,6 @@ Holger Brunck <holger.brunck@keymile.com> tuge1 MPC8321 tuxx1 MPC8321 -Cyril Chemparathy <cyril@ti.com> - - tnetv107x_evm tnetv107x - Conn Clark <clark@esteem.com> ESTEEM192E MPC8xx @@ -367,6 +363,10 @@ Frank Panno <fpanno@delphintech.com> ep8260 MPC8260 +Chan-Taek Park <c-park@ti.com> + + tnetv107x_evm tnetv107x + Denis Peter <d.peter@mpl.ch> MIP405 PPC4xx @@ -401,8 +401,6 @@ Stefan Roese <sr@denx.de> uc100 MPC857 - TQM85xx MPC8540/8541/8555/8560 - acadia PPC405EZ alpr PPC440GX bamboo PPC440EP @@ -731,7 +729,7 @@ Chander Kashyap <k.chander@samsung.com> SMDKV310 ARM ARMV7 (EXYNOS4210 SoC) SMDK5250 ARM ARMV7 (EXYNOS5250 SoC) -Heungjun Kim <riverful.kim@samsung.com> +Lukasz Majewski <l.majewski@samsung.com> trats ARM ARMV7 (EXYNOS4210 SoC) @@ -24,7 +24,7 @@ VERSION = 2012 PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc2 ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else @@ -704,6 +704,8 @@ The following options need to be configured: - Boot Delay: CONFIG_BOOTDELAY - in seconds Delay before automatically booting the default image; set to -1 to disable autoboot. + set to -2 to autoboot with no delay and not check for abort + (even when CONFIG_ZERO_BOOTDELAY_CHECK is defined). See doc/README.autoboot for these options that work with CONFIG_BOOTDELAY. None are required. @@ -814,6 +816,7 @@ The following options need to be configured: CONFIG_CMD_IMLS List all found images CONFIG_CMD_IMMAP * IMMR dump support CONFIG_CMD_IMPORTENV * import an environment + CONFIG_CMD_INI * import data from an ini file into the env CONFIG_CMD_IRQ * irqinfo CONFIG_CMD_ITEST Integer/string test of 2 values CONFIG_CMD_JFFS2 * JFFS2 Support @@ -855,7 +858,8 @@ The following options need to be configured: CONFIG_CMD_SPI * SPI serial bus support CONFIG_CMD_TFTPSRV * TFTP transfer in server mode CONFIG_CMD_TFTPPUT * TFTP put command (upload) - CONFIG_CMD_TIME * run command and report execution time + CONFIG_CMD_TIME * run command and report execution time (ARM specific) + CONFIG_CMD_TIMER * access to the system tick timer CONFIG_CMD_USB * USB support CONFIG_CMD_CDP * Cisco Discover Protocol support CONFIG_CMD_MFSL * Microblaze FSL support @@ -4688,7 +4692,10 @@ Over time, many people have reported problems when trying to use the consider minicom to be broken, and recommend not to use it. Under Unix, I recommend to use C-Kermit for general purpose use (and especially for kermit binary protocol download ("loadb" command), and -use "cu" for S-Record download ("loads" command). +use "cu" for S-Record download ("loads" command). See +http://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.3. +for help with kermit. + Nevertheless, if you absolutely want to use it try adding this configuration to your "File transfer protocols" section: diff --git a/arch/openrisc/include/asm/bitops.h b/arch/openrisc/include/asm/bitops.h index c001a5d1f6..c76a40901f 100644 --- a/arch/openrisc/include/asm/bitops.h +++ b/arch/openrisc/include/asm/bitops.h @@ -25,4 +25,8 @@ #define PLATFORM_FFS #include <asm/bitops/ffs.h> +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + #endif /* __ASM_GENERIC_BITOPS_H */ diff --git a/arch/openrisc/lib/timer.c b/arch/openrisc/lib/timer.c index 4e92a31159..89e644bc47 100644 --- a/arch/openrisc/lib/timer.c +++ b/arch/openrisc/lib/timer.c @@ -86,6 +86,16 @@ void set_timer(ulong t) timestamp = t; } +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} + void __udelay(ulong usec) { ulong elapsed = 0; diff --git a/board/alphaproject/ap_sh4a_4a/lowlevel_init.S b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S index f04b36bafd..cf9c225e6d 100644 --- a/board/alphaproject/ap_sh4a_4a/lowlevel_init.S +++ b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S @@ -330,7 +330,7 @@ init_dbsc3_ctrl_533: DBKIND_A: .long 0xFE800020 DBKIND_D: .long 0x00000005 DBCONF_A: .long 0xFE800024 -DBCONF_D: .long 0x0D020901 +DBCONF_D: .long 0x0D020A01 DBTR0_A: .long 0xFE800040 DBTR0_D_533:.long 0x00000004 diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c index 64de04ca29..dbcb34b8f0 100644 --- a/board/amirix/ap1000/ap1000.c +++ b/board/amirix/ap1000/ap1000.c @@ -43,11 +43,13 @@ int checkboard (void) /* After a loadace command, the SystemAce control register is left in a wonky state. */ /* this code did not work in board_pre_init */ unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE; + unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR; + unsigned int device = (*revision_reg_ptr & AP1xx_TARGET_MASK); p[SYSACE_CTRLREG0] = 0x0; /* add platform and device to banner */ - switch (get_device ()) { + switch (device) { case AP1xx_AP107_TARGET: puts (AP1xx_AP107_TARGET_STR); break; @@ -160,13 +162,6 @@ unsigned int get_platform (void) return (*revision_reg_ptr & AP1xx_PLATFORM_MASK); } -unsigned int get_device (void) -{ - unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR; - - return (*revision_reg_ptr & AP1xx_TARGET_MASK); -} - #if 0 /* loadace is not working; it appears to be a hardware issue with the system ace. */ /* This function loads FPGA configurations from the SystemACE CompactFlash diff --git a/board/amirix/ap1000/ap1000.h b/board/amirix/ap1000/ap1000.h index 118c4d1b9a..d294816d26 100644 --- a/board/amirix/ap1000/ap1000.h +++ b/board/amirix/ap1000/ap1000.h @@ -164,7 +164,6 @@ void set_eat_machine_checks(int a_flag); int get_eat_machine_checks(void); unsigned int get_platform(void); -unsigned int get_device(void); void* memcpyb(void * dest,const void *src,size_t count); int process_bootflag(ulong bootflag); void user_led_on(void); diff --git a/board/tqc/tqm85xx/Makefile b/board/tqc/tqm85xx/Makefile deleted file mode 100644 index 0a5501fda0..0000000000 --- a/board/tqc/tqm85xx/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += sdram.o -COBJS-y += law.o -COBJS-y += tlb.o - -COBJS-$(CONFIG_NAND) += nand.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c deleted file mode 100644 index c596303c5d..0000000000 --- a/board/tqc/tqm85xx/law.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * Standard mapping: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO or PCI express 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff CAN and NAND Flash 16M - * 0xef00_0000 0xefff_ffff PCI express IO 16M - * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 128M - * - * Big FLASH mapping: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xa000_ffff CCSR 1M - * 0xa200_0000 0xa2ff_ffff PCI1 IO 16M - * 0xa300_0000 0xa3ff_ffff CAN and NAND Flash 16M - * 0xaf00_0000 0xafff_ffff PCI express IO 16M - * 0xb000_0000 0xbfff_ffff RapidIO or PCI express 256M - * 0xc000_0000 0xffff_ffff FLASH (boot bank) 1G - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#ifdef CONFIG_TQM_BIGFLASH -#define LAW_3_SIZE LAW_SIZE_1G -#define LAW_5_SIZE LAW_SIZE_256M -#else -#define LAW_3_SIZE LAW_SIZE_128M -#define LAW_5_SIZE LAW_SIZE_512M -#endif - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_2G, LAW_TRGT_IF_DDR), - SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC), -#ifndef CONFIG_PCIE1 - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO), -#endif /* CONFIG_PCIE1 */ -#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND) - SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), -#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */ -}; - -int num_law_entries = ARRAY_SIZE (law_table); diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c deleted file mode 100644 index 4b16c31de2..0000000000 --- a/board/tqc/tqm85xx/nand.c +++ /dev/null @@ -1,472 +0,0 @@ -/* - * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de> - * - * (C) Copyright 2006 - * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/io.h> -#include <asm/errno.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/fsl_upm.h> -#include <ioports.h> - -#include <nand.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern uint get_lbc_clock (void); - -/* index of UPM RAM array run pattern for NAND command cycle */ -#define CONFIG_SYS_NAN_UPM_WRITE_CMD_OFS 0x08 - -/* index of UPM RAM array run pattern for NAND address cycle */ -#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x10 - -/* Structure for table with supported UPM timings */ -struct upm_freq { - ulong freq; - const u32 *upm_patt; - uchar gpl4_disable; - uchar ehtr; - uchar ead; -}; - -/* NAND-FLASH UPM tables for TQM85XX according to TQM8548.pq.timing.101.doc */ - -/* UPM pattern for bus clock = 25 MHz */ -static const u32 upm_patt_25[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff32000, 0x0fa32000, 0x3fb32005, 0xfffffc00, - /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 33.3 MHz */ -static const u32 upm_patt_33[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00, - /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 41.7 MHz */ -static const u32 upm_patt_42[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00, - /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 50 MHz */ -static const u32 upm_patt_50[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff33000, 0x0fa33100, 0x0fa33005, 0xfffffc00, - /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c35, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc35, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c05, 0xfffffc00, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 66.7 MHz */ -static const u32 upm_patt_67[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000, - /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 83.3 MHz */ -static const u32 upm_patt_83[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000, - /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff3e30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3fe30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f33e00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 100 MHz */ -static const u32 upm_patt_100[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33200, 0x0fa33000, - /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff3f30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3ff30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f33f00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 133.3 MHz */ -static const u32 upm_patt_133[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33300, 0x0fa33000, - /* 0x04 */ 0x0fa33000, 0x0fa33005, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff3f30, 0x00ff3d30, 0x0fff3d30, 0x0fff3c35, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3ff30, 0x00f3fd30, 0x0ff3fd30, 0x0ff3fc35, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f33f00, 0x00f33d00, 0x0ff33d00, 0x0ff33c05, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 166.7 MHz */ -static const u32 upm_patt_167[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff33200, 0x0fe33000, 0x0fa33300, 0x0fa33300, - /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff3f30, 0x00ff3f30, 0x0fff3e30, 0xffff3c35, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3ff30, 0x00f3ff30, 0x0ff3fe30, 0x0ff3fc35, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f33f00, 0x00f33f00, 0x0ff33e00, 0x0ff33c05, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* Supported UPM timings */ -struct upm_freq upm_freq_table[] = { - /* nominal freq. | ptr to table | GPL4 dis. | EHTR | EAD */ - {25000000, upm_patt_25, 1, 0, 0}, - {33333333, upm_patt_33, 1, 0, 0}, - {41666666, upm_patt_42, 1, 0, 0}, - {50000000, upm_patt_50, 0, 0, 0}, - {66666666, upm_patt_67, 0, 0, 0}, - {83333333, upm_patt_83, 0, 0, 0}, - {100000000, upm_patt_100, 0, 1, 1}, - {133333333, upm_patt_133, 0, 1, 1}, - {166666666, upm_patt_167, 0, 1, 1}, -}; - -#define UPM_FREQS (sizeof(upm_freq_table) / sizeof(struct upm_freq)) - -volatile const u32 *nand_upm_patt; - -/* - * write into UPMB ram - */ -static void upmb_write (u_char addr, ulong val) -{ - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - out_be32 (&lbc->mdr, val); - - clrsetbits_be32(&lbc->mbmr, MxMR_MAD_MSK, - MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); - - /* dummy access to perform write */ - out_8 ((void __iomem *)CONFIG_SYS_NAND_BASE, 0); - - clrbits_be32(&lbc->mbmr, MxMR_OP_WARR); -} - -/* - * Initialize UPM for NAND flash access. - */ -static void nand_upm_setup (volatile fsl_lbc_t *lbc) -{ - uint i, j; - uint or3 = CONFIG_SYS_OR3_PRELIM; - uint clock = get_lbc_clock (); - - set_lbc_br(3, 0); /* disable bank and reset all bits */ - set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); - - /* - * Search appropriate UPM table for bus clock. - * If the bus clock exceeds a tolerated value, take the UPM timing for - * the next higher supported frequency to ensure that access works - * (even the access may be slower then). - */ - for (i = 0; (i < UPM_FREQS) && (clock > upm_freq_table[i].freq); i++) - ; - - if (i >= UPM_FREQS) - /* no valid entry found */ - /* take last entry with configuration for max. bus clock */ - i--; - - if (upm_freq_table[i].ehtr) { - /* EHTR must be set due to TQM8548 timing specification */ - or3 |= OR_UPM_EHTR; - } - if (upm_freq_table[i].ead) - /* EAD must be set due to TQM8548 timing specification */ - or3 |= OR_UPM_EAD; - - set_lbc_or(3, or3); - - /* Assign address of table */ - nand_upm_patt = upm_freq_table[i].upm_patt; - - for (j = 0; j < 64; j++) { - upmb_write (j, *nand_upm_patt); - nand_upm_patt++; - } - - /* Put UPM back to normal operation mode */ - if (upm_freq_table[i].gpl4_disable) - /* GPL4 must be disabled according to timing specification */ - out_be32 (&lbc->mbmr, MxMR_OP_NORM | MxMR_GPL_x4DIS); - - return; -} - -static struct fsl_upm_nand fun = { - .width = 8, - .upm_cmd_offset = 0x08, - .upm_addr_offset = 0x10, - .upm_mar_chip_offset = CONFIG_SYS_NAND_CS_DIST, - .chip_offset = CONFIG_SYS_NAND_CS_DIST, - .chip_delay = NAND_BIG_DELAY_US, - .wait_flags = FSL_UPM_WAIT_RUN_PATTERN | FSL_UPM_WAIT_WRITE_BUFFER, -}; - -void board_nand_select_device (struct nand_chip *nand, int chip) -{ -} - -int board_nand_init (struct nand_chip *nand) -{ - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - if (!nand_upm_patt) - nand_upm_setup (lbc); - - fun.upm.io_addr = nand->IO_ADDR_R; - fun.upm.mxmr = (void __iomem *)&lbc->mbmr; - fun.upm.mdr = (void __iomem *)&lbc->mdr; - fun.upm.mar = (void __iomem *)&lbc->mar; - - return fsl_upm_nand_init (nand, &fun); -} diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c deleted file mode 100644 index baf073e548..0000000000 --- a/board/tqc/tqm85xx/sdram.c +++ /dev/null @@ -1,436 +0,0 @@ - -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <asm/processor.h> -#include <asm/mmu.h> - -struct sdram_conf_s { - unsigned long size; - unsigned long reg; -#ifdef CONFIG_TQM8548 - unsigned long refresh; -#endif /* CONFIG_TQM8548 */ -}; - -typedef struct sdram_conf_s sdram_conf_t; - -#ifdef CONFIG_TQM8548 -#ifdef CONFIG_TQM8548_AG -sdram_conf_t ddr_cs_conf[] = { - {(1024 << 20), 0x80044202, 0x0002D000}, /* 1024MB, 14x10(4) */ - { (512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */ - { (256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */ - { (128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */ -}; -#else /* !CONFIG_TQM8548_AG */ -sdram_conf_t ddr_cs_conf[] = { - {(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */ - {(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */ - {(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */ -}; -#endif /* CONFIG_TQM8548_AG */ -#else /* !CONFIG_TQM8548 */ -sdram_conf_t ddr_cs_conf[] = { - {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */ - {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */ - {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */ - {( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */ -}; -#endif /* CONFIG_TQM8548 */ - -#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0])) - -int cas_latency (void); -static phys_size_t sdram_setup(int); - -/* - * Autodetect onboard DDR SDRAM on 85xx platforms - * - * NOTE: Some of the hardcoded values are hardware dependant, - * so this should be extended for other future boards - * using this routine! - */ -phys_size_t fixed_sdram(void) -{ - int casl = 0; - phys_size_t dram_size = 0; - - casl = cas_latency(); - dram_size = sdram_setup(casl); - if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { - /* - * Try again with default CAS latency - */ - printf("Problem with CAS lantency, using default CL %d/10!\n", - CONFIG_DDR_DEFAULT_CL); - dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL); - puts(" "); - } - return dram_size; -} - -static phys_size_t sdram_setup(int casl) -{ - int i; - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); -#ifdef CONFIG_TQM8548 - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE) - volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); -#endif -#else /* !CONFIG_TQM8548 */ - unsigned long cfg_ddr_timing1; - unsigned long cfg_ddr_mode; -#endif /* CONFIG_TQM8548 */ - - /* - * Disable memory controller. - */ - ddr->cs0_config = 0; - ddr->sdram_cfg = 0; - -#ifdef CONFIG_TQM8548 - /* Timing and refresh settings for DDR2-533 and below */ - - ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; - ddr->cs0_config = ddr_cs_conf[0].reg; - ddr->timing_cfg_3 = 0x00020000; - - /* TIMING CFG 1, 533MHz - * PRETOACT: 4 Clocks - * ACTTOPRE: 12 Clocks - * ACTTORW: 4 Clocks - * CASLAT: 4 Clocks - * REFREC: EXT_REFREC:REFREC 53 Clocks - * WRREC: 4 Clocks - * ACTTOACT: 3 Clocks - * WRTORD: 2 Clocks - */ - ddr->timing_cfg_1 = 0x4C47D432; - - /* TIMING CFG 2, 533MHz - * ADD_LAT: 3 Clocks - * CPO: READLAT + 1 - * WR_LAT: 3 Clocks - * RD_TO_PRE: 2 Clocks - * WR_DATA_DELAY: 1/2 Clock - * CKE_PLS: 3 Clock - * FOUR_ACT: 14 Clocks - */ - ddr->timing_cfg_2 = 0x331848CE; - - /* DDR SDRAM Mode, 533MHz - * MRS: Extended Mode Register - * OUT: Outputs enabled - * RDQS: no - * DQS: enabled - * OCD: default state - * RTT: 75 Ohms - * Posted CAS: 3 Clocks - * ODS: reduced strength - * DLL: enabled - * MR: Mode Register - * PD: fast exit - * WR: 4 Clocks - * DLL: no DLL reset - * TM: normal - * CAS latency: 4 Clocks - * BT: sequential - * Burst length: 4 - */ - ddr->sdram_mode = 0x439E0642; - - /* DDR SDRAM Interval, 533MHz - * REFINT: 1040 Clocks - * BSTOPRE: 256 - */ - ddr->sdram_interval = (1040 << 16) | 0x100; - - /* - * Workaround for erratum DDR19 according to MPC8548 Device Errata - * document, Rev. 1: DDR IO receiver must be set to an acceptable - * bias point by modifying a hidden register. - */ - if (SVR_REV (get_svr ()) < 0x21) - gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */ - - /* DDR SDRAM CFG 2 - * FRC_SR: normal mode - * SR_IE: no self-refresh interrupt - * DLL_RST_DIS: don't care, leave at reset value - * DQS_CFG: differential DQS signals - * ODT_CFG: assert ODT to internal IOs only during reads to DRAM - * LVWx_CFG: don't care, leave at reset value - * NUM_PR: 1 refresh will be issued at a time - * DM_CFG: don't care, leave at reset value - * D_INIT: no data initialization - */ - ddr->sdram_cfg_2 = 0x04401000; - - /* DDR SDRAM MODE 2 - * MRS: Extended Mode Register 2 - */ - ddr->sdram_mode_2 = 0x8000C000; - - /* DDR SDRAM CLK CNTL - * CLK_ADJUST: 1/2 Clock 0x02000000 - * CLK_ADJUST: 5/8 Clock 0x02800000 - */ - ddr->sdram_clk_cntl = 0x02800000; - - /* wait for clock stabilization */ - asm ("sync;isync;msync"); - udelay (1000); - -#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE) - /* - * Workaround for erratum DDR20 according to MPC8548 Device Errata - * document, Rev. 1: "CKE signal may not function correctly after - * assertion of HRESET" - */ - - /* 1. Configure DDR register as is done in normal DDR configuration. - * Do not set DDR_SDRAM_CFG[MEM_EN]. - * - * 2. Set reserved bit EEBACR[3] at offset 0x1000 - */ - ecm->eebacr |= 0x10000000; - - /* - * 3. Before DDR_SDRAM_CFG[MEM_EN] is set, write DDR_SDRAM_CFG_2[D_INIT] - * - * DDR_SDRAM_CFG_2: - * FRC_SR: normal mode - * SR_IE: no self-refresh interrupt - * DLL_RST_DIS: don't care, leave at reset value - * DQS_CFG: differential DQS signals - * ODT_CFG: assert ODT to internal IOs only during reads to DRAM - * LVWx_CFG: don't care, leave at reset value - * NUM_PR: 1 refresh will be issued at a time - * DM_CFG: don't care, leave at reset value - * D_INIT: enable data initialization - */ - ddr->sdram_cfg_2 |= 0x00000010; - - /* - * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data - * training - */ - ddr->debug[2] |= 0x00000400; - - /* - * 5. Wait 200 micro-seconds - */ - udelay (200); - - /* - * 6. Set DDR_SDRAM_CFG[MEM_EN] - * - * BTW, initialize DDR_SDRAM_CFG: - * MEM_EN: enabled - * SREN: don't care, leave at reset value - * ECC_EN: no error report - * RD_EN: no registered DIMMs - * SDRAM_TYPE: DDR2 - * DYN_PWR: no power management - * 32_BE: don't care, leave at reset value - * 8_BE: 4 beat burst - * NCAP: don't care, leave at reset value - * 2T_EN: 1T Timing - * BA_INTLV_CTL: no interleaving - * x32_EN: x16 organization - * PCHB8: MA[10] for auto-precharge - * HSE: half strength for single and 2-layer stacks - * (full strength for 3- and 4-layer stacks not - * yet considered) - * MEM_HALT: no halt - * BI: automatic initialization - */ - ddr->sdram_cfg = 0x83000008; - - /* - * 7. Poll DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware - */ - asm ("sync;isync;msync"); - while (ddr->sdram_cfg_2 & 0x00000010) - asm ("eieio"); - - /* - * 8. Clear D3[21] to re-enable data training - */ - ddr->debug[2] &= ~0x00000400; - - /* - * 9. Set D2(21) to force data training to run - */ - ddr->debug[1] |= 0x00000400; - - /* - * 10. Poll on D2[21] until it is cleared by hardware - */ - asm ("sync;isync;msync"); - while (ddr->debug[1] & 0x00000400) - asm ("eieio"); - - /* - * 11. Clear reserved bit EEBACR[3] at offset 0x1000 - */ - ecm->eebacr &= ~0x10000000; - -#else /* !(CONFIG_TQM8548_AG || CONFIG_TQM8548_BE) */ - - /* DDR SDRAM CLK CNTL - * MEM_EN: enabled - * SREN: don't care, leave at reset value - * ECC_EN: no error report - * RD_EN: no register DIMMs - * SDRAM_TYPE: DDR2 - * DYN_PWR: no power management - * 32_BE: don't care, leave at reset value - * 8_BE: 4 beat burst - * NCAP: don't care, leave at reset value - * 2T_EN: 1T Timing - * BA_INTLV_CTL: no interleaving - * x32_EN: x16 organization - * PCHB8: MA[10] for auto-precharge - * HSE: half strength for single and 2-layer stacks - * (full strength for 3- and 4-layer stacks no yet considered) - * MEM_HALT: no halt - * BI: automatic initialization - */ - ddr->sdram_cfg = 0x83000008; - -#endif /* CONFIG_TQM8548_AG || CONFIG_TQM8548_BE */ - - asm ("sync; isync; msync"); - udelay (1000); -#else /* !CONFIG_TQM8548 */ - switch (casl) { - case 20: - cfg_ddr_timing1 = 0x47405331 | (3 << 16); - cfg_ddr_mode = 0x40020002 | (2 << 4); - break; - - case 25: - cfg_ddr_timing1 = 0x47405331 | (4 << 16); - cfg_ddr_mode = 0x40020002 | (6 << 4); - break; - - case 30: - default: - cfg_ddr_timing1 = 0x47405331 | (5 << 16); - cfg_ddr_mode = 0x40020002 | (3 << 4); - break; - } - - ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; - ddr->cs0_config = ddr_cs_conf[0].reg; - ddr->timing_cfg_1 = cfg_ddr_timing1; - ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */ - ddr->sdram_mode = cfg_ddr_mode; - ddr->sdram_interval = 0x05160100; /* autocharge,no open page */ - ddr->err_disable = 0x0000000D; - - asm ("sync; isync; msync"); - udelay (1000); - - ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */ - asm ("sync; isync; msync"); - udelay (1000); -#endif /* CONFIG_TQM8548 */ - - /* - * get_ram_size() depends on having tlbs for the DDR, but they are - * not yet setup because we don't know the size. Set up a temp - * mapping and delete it when done. - */ - setup_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB); - for (i = 0; i < N_DDR_CS_CONF; i++) { - ddr->cs0_config = ddr_cs_conf[i].reg; - - if (get_ram_size (0, ddr_cs_conf[i].size) == - ddr_cs_conf[i].size) { - /* - * size detected -> set Chip Select Bounds Register - */ - ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24; - - break; - } - } - clear_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB); - -#ifdef CONFIG_TQM8548 - if (i < N_DDR_CS_CONF) { - /* Adjust refresh rate for DDR2 */ - - ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000; - - ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) | - (ddr_cs_conf[i].refresh & 0x0000F000); - - return ddr_cs_conf[i].size; - } -#endif /* CONFIG_TQM8548 */ - - /* return size if detected, else return 0 */ - return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0; -} - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf ("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf ("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf ("SDRAM test passed.\n"); - return 0; -} -#endif diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c deleted file mode 100644 index f9f8cc9a01..0000000000 --- a/board/tqc/tqm85xx/tlb.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - -#ifndef CONFIG_TQM_BIGFLASH - /* - * TLB 0, 1: 128M Non-cacheable, guarded - * 0xf8000000 128M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 1, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x4000000, - CONFIG_SYS_FLASH_BASE + 0x4000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - -#ifdef CONFIG_PCIE1 - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xc0000000 256M PCI express MEM First half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 256M Non-cacheable, guarded - * 0xd0000000 256M PCI express MEM Second half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000, - CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), -#else /* !CONFIG_PCIE */ - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, - CONFIG_SYS_RIO_MEM_BASE + 0x10000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), -#endif /* CONFIG_PCIE */ - - /* - * TLB 6: 64M Non-cacheable, guarded - * 0xe0000000 1M CCSRBAR - * 0xe2000000 16M PCI1 IO - * 0xe3000000 16M CAN and NAND Flash - */ - SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 6, BOOKE_PAGESZ_64M, 1), -#ifdef CONFIG_PCIE1 - /* - * TLB 9: 16M Non-cacheable, guarded - * 0xef000000 16M PCI express IO - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_BUS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 9, BOOKE_PAGESZ_16M, 1), -#endif /* CONFIG_PCIE */ - -#else /* CONFIG_TQM_BIGFLASH */ - - /* - * TLB 0,1,2,3: 1G Non-cacheable, guarded - * 0xc0000000 1G FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x10000000, - CONFIG_SYS_FLASH_BASE + 0x10000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x20000000, - CONFIG_SYS_FLASH_BASE + 0x20000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x30000000, - CONFIG_SYS_FLASH_BASE + 0x30000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 0, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - -#ifdef CONFIG_PCIE1 - /* - * TLB 6: 256M Non-cacheable, guarded - * 0xc0000000 256M PCI express MEM First half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 6, BOOKE_PAGESZ_256M, 1), -#else /* !CONFIG_PCIE */ - /* - * TLB 6: 256M Non-cacheable, guarded - * 0xb0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 6, BOOKE_PAGESZ_256M, 1), - -#endif /* CONFIG_PCIE */ - - /* - * TLB 7: 64M Non-cacheable, guarded - * 0xa0000000 1M CCSRBAR - * 0xa2000000 16M PCI1 IO - * 0xa3000000 16M CAN and NAND Flash - */ - SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 7, BOOKE_PAGESZ_64M, 1), -#ifdef CONFIG_PCIE1 - /* - * TLB 10: 16M Non-cacheable, guarded - * 0xaf000000 16M PCI express IO - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 10, BOOKE_PAGESZ_16M, 1), -#endif /* CONFIG_PCIE */ - -#endif /* CONFIG_TQM_BIGFLASH */ -}; - -int num_tlb_entries = ARRAY_SIZE (tlb_table); diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c deleted file mode 100644 index 8fb73abde7..0000000000 --- a/board/tqc/tqm85xx/tqm85xx.c +++ /dev/null @@ -1,626 +0,0 @@ -/* - * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de> - * - * (C) Copyright 2006 - * Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de. - * - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003, Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <asm/io.h> -#include <asm/fsl_serdes.h> -#include <linux/compiler.h> -#include <ioports.h> -#include <flash.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[]; /* FLASH chips info */ - -void local_bus_init (void); -ulong flash_get_size (ulong base, int banknum); - -#ifdef CONFIG_PS2MULT -void ps2mult_early_init (void); -#endif - -#ifdef CONFIG_CPM2 -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A: conf, ppar, psor, pdir, podr, pdat */ - { - {1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */ - {1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */ - {1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */ - {1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */ - {1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */ - {1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */ - {0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */ - {0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */ - {0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */ - {0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */ - {1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */ - {1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */ - {1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */ - {1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */ - {1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */ - {1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */ - {1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */ - {1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */ - {0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */ - {0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */ - {0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */ - {0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */ - {0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */ - {0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */ - {0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */ - {0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */ - {0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */ - {0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */ - {0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */ - {0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */ - {0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */ - {0, 0, 0, 1, 0, 0} /* PA0 : PA0 */ - }, - - /* Port B: conf, ppar, psor, pdir, podr, pdat */ - { - {1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */ - {1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */ - {1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */ - {1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */ - {1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */ - {1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */ - {1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */ - {1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */ - {1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */ - {1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */ - {1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */ - {1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */ - {1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */ - {1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */ - {1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */ - {1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */ - {1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */ - {1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */ - {1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */ - {1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */ - {1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */ - {1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */ - {1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */ - {1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */ - {1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */ - {1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */ - {1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */ - {1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */ - {0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */ - {0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */ - {0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */ - {0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */ - }, - - /* Port C: conf, ppar, psor, pdir, podr, pdat */ - { - {0, 0, 0, 1, 0, 0}, /* PC31: PC31 */ - {0, 0, 0, 1, 0, 0}, /* PC30: PC30 */ - {0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */ - {0, 0, 0, 1, 0, 0}, /* PC28: PC28 */ - {0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */ - {0, 0, 0, 1, 0, 0}, /* PC26: PC26 */ - {0, 0, 0, 1, 0, 0}, /* PC25: PC25 */ - {0, 0, 0, 1, 0, 0}, /* PC24: PC24 */ - {0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */ - {0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */ - {1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */ - {1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */ - {1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */ - {1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */ - {1, 1, 0, 0, 0, 0}, /* PC17: PC17 */ - {1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */ - {0, 1, 0, 0, 0, 0}, /* PC15: PC15 */ - {0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */ - {0, 1, 0, 0, 0, 0}, /* PC13: PC13 */ - {0, 1, 0, 1, 0, 0}, /* PC12: PC12 */ - {0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */ - {0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */ - {0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */ - {0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */ - {0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */ - {0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */ - {0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */ - {0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */ - {0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */ - {0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */ - {0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */ - {0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */ - }, - - /* Port D: conf, ppar, psor, pdir, podr, pdat */ - { -#ifdef CONFIG_TQM8560 - {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */ - {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */ - {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */ -#else /* !CONFIG_TQM8560 */ - {0, 0, 0, 0, 0, 0}, /* PD31: PD31 */ - {0, 0, 0, 0, 0, 0}, /* PD30: PD30 */ - {0, 0, 0, 0, 0, 0}, /* PD29: PD29 */ -#endif /* CONFIG_TQM8560 */ - {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */ - {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */ - {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */ - {0, 0, 0, 1, 0, 0}, /* PD25: PD25 */ - {0, 0, 0, 1, 0, 0}, /* PD24: PD24 */ - {0, 0, 0, 1, 0, 0}, /* PD23: PD23 */ - {0, 0, 0, 1, 0, 0}, /* PD22: PD22 */ - {0, 0, 0, 1, 0, 0}, /* PD21: PD21 */ - {0, 0, 0, 1, 0, 0}, /* PD20: PD20 */ - {0, 0, 0, 1, 0, 0}, /* PD19: PD19 */ - {0, 0, 0, 1, 0, 0}, /* PD18: PD18 */ - {0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */ - {0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */ - {0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */ - {0, 0, 0, 1, 0, 0}, /* PD14: LED */ - {0, 0, 0, 0, 0, 0}, /* PD13: PD13 */ - {0, 0, 0, 0, 0, 0}, /* PD12: PD12 */ - {0, 0, 0, 0, 0, 0}, /* PD11: PD11 */ - {0, 0, 0, 0, 0, 0}, /* PD10: PD10 */ - {0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */ - {0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */ - {0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */ - {0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */ - {0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */ - {0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */ - {0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */ - {0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */ - {0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */ - {0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */ - } -}; -#endif /* CONFIG_CPM2 */ - -#define CASL_STRING1 "casl=xx" -#define CASL_STRING2 "casl=" - -static const int casl_table[] = { 20, 25, 30 }; -#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0])) - -int cas_latency (void) -{ - char buf[128]; - int casl; - int val; - int i; - - casl = CONFIG_DDR_DEFAULT_CL; - - i = getenv_f("serial#", buf, sizeof(buf)); - - if (i >0) { - if (strncmp(buf + strlen (buf) - strlen (CASL_STRING1), - CASL_STRING2, strlen (CASL_STRING2)) == 0) { - val = simple_strtoul (buf + strlen (buf) - 2, NULL, 10); - - for (i = 0; i < N_CASL; ++i) { - if (val == casl_table[i]) { - return val; - } - } - } - } - - return casl; -} - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf ("Board: %s", CONFIG_BOARDNAME); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc ('\n'); - - /* - * Initialize local bus. - */ - local_bus_init (); - - return 0; -} - -int misc_init_r (void) -{ - /* - * Adjust flash start and offset to detected values - */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Recalculate CS configuration if second FLASH bank is available - */ - if (flash_info[0].size > 0) { - set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) | - (CONFIG_SYS_OR1_PRELIM & 0x00007fff)); - set_lbc_br(1, gd->bd->bi_flashstart | - (CONFIG_SYS_BR1_PRELIM & 0x00007fff)); - /* - * Re-check to get correct base address for bank 1 - */ - flash_get_size (gd->bd->bi_flashstart, 0); - } else { - set_lbc_or(1, 0); - set_lbc_br(1, 0); - } - - /* - * If bank 1 is equipped, bank 0 is mapped after bank 1 - */ - set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) | - (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); - set_lbc_br(0, (gd->bd->bi_flashstart + flash_info[0].size) | - (CONFIG_SYS_BR0_PRELIM & 0x00007fff)); - - /* - * Re-check to get correct base address for bank 0 - */ - flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1); - - /* - * Re-do flash protection upon new addresses - */ - flash_protect (FLAG_PROTECT_CLEAR, - gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, 0xffffffff, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - -#ifdef CONFIG_ENV_ADDR_REDUND - /* Redundant environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); -#endif - - return 0; -} - -#ifdef CONFIG_CAN_DRIVER -/* - * Initialize UPMC RAM - */ -static void upmc_write (u_char addr, uint val) -{ - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - out_be32 (&lbc->mdr, val); - - clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK, - MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); - - /* dummy access to perform write */ - out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0); - - /* normal operation */ - clrbits_be32(&lbc->mcmr, MxMR_OP_WARR); -} -#endif /* CONFIG_CAN_DRIVER */ - -uint get_lbc_clock (void) -{ - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - sys_info_t sys_info; - ulong clkdiv = lbc->lcrr & LCRR_CLKDIV; - - get_sys_info (&sys_info); - - if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { -#ifdef CONFIG_MPC8548 - /* - * Yes, the entire PQ38 family use the same - * bit-representation for twice the clock divider value. - */ - clkdiv *= 2; -#endif - return sys_info.freqSystemBus / clkdiv; - } - - puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n"); - - return 0; -} - -/* - * Initialize Local Bus - */ -void local_bus_init (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint lbc_mhz = get_lbc_clock () / 1000000; - -#ifdef CONFIG_MPC8548 - uint svr = get_svr (); - uint lcrr; - - /* - * MPC revision < 2.0 - * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1: - * Modify engineering use only register at address 0xE_0F20. - * "1. Read register at offset 0xE_0F20 - * 2. And value with 0x0000_FFFF - * 3. OR result with 0x0000_0004 - * 4. Write result back to offset 0xE_0F20." - * - * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2: - * Modify engineering use only register at address 0xE_0F20. - * "1. Read register at offset 0xE_0F20 - * 2. And value with 0xFFFF_FFDF - * 3. Write result back to offset 0xE_0F20." - * - * Since it is the same register, we do the modification in one step. - */ - if (SVR_MAJ (svr) < 2) { - uint dummy = gur->lbiuiplldcr1; - dummy &= 0x0000FFDF; - dummy |= 0x00000004; - gur->lbiuiplldcr1 = dummy; - } - - lcrr = CONFIG_SYS_LBC_LCRR; - - /* - * Local Bus Clock > 83.3 MHz. According to timing - * specifications set LCRR[EADC] to 2 delay cycles. - */ - if (lbc_mhz > 83) { - lcrr &= ~LCRR_EADC; - lcrr |= LCRR_EADC_2; - } - - /* - * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30 - * disable PLL bypass for Local Bus Clock > 83 MHz. - */ - if (lbc_mhz >= 66) - lcrr &= (~LCRR_DBYP); /* DLL Enabled */ - - else - lcrr |= LCRR_DBYP; /* DLL Bypass */ - - lbc->lcrr = lcrr; - asm ("sync;isync;msync"); - - /* - * According to MPC8548ERMAD Rev.1.3 read back LCRR - * and terminate with isync - */ - lcrr = lbc->lcrr; - asm ("isync;"); - - /* let DLL stabilize */ - udelay (500); - -#else /* !CONFIG_MPC8548 */ - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66MHz, DLL bypass mode must be used. - * If localbus freq is > 133MHz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - if (lbc_mhz < 66) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ - lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA | - LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */ - - } else if (lbc_mhz >= 133) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ - - } else { - /* - * On REV1 boards, need to change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 temporarily. - */ - uint pvr = get_pvr (); - uint temp_lbcdll = 0; - - if (pvr == PVR_85xx_REV1) { - /* FIXME: Justify the high bit here. */ - lbc->lcrr = 0x10000004; - } - - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ - udelay (200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm ("sync;isync;msync"); - } -#endif /* !CONFIG_MPC8548 */ - -#ifdef CONFIG_CAN_DRIVER - /* - * According to timing specifications EAD must be - * set if Local Bus Clock is > 83 MHz. - */ - if (lbc_mhz > 83) - set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD); - else - set_lbc_or(2, CONFIG_SYS_OR2_CAN); - set_lbc_br(2, CONFIG_SYS_BR2_CAN); - - /* LGPL4 is UPWAIT */ - out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X); - - /* Initialize UPMC for CAN: single read */ - upmc_write (0x00, 0xFFFFED00); - upmc_write (0x01, 0xCCFFCC00); - upmc_write (0x02, 0x00FFCF00); - upmc_write (0x03, 0x00FFCF00); - upmc_write (0x04, 0x00FFDC00); - upmc_write (0x05, 0x00FFCF00); - upmc_write (0x06, 0x00FFED00); - upmc_write (0x07, 0x3FFFCC07); - - /* Initialize UPMC for CAN: single write */ - upmc_write (0x18, 0xFFFFED00); - upmc_write (0x19, 0xCCFFEC00); - upmc_write (0x1A, 0x00FFED80); - upmc_write (0x1B, 0x00FFED80); - upmc_write (0x1C, 0x00FFFC00); - upmc_write (0x1D, 0x0FFFEC00); - upmc_write (0x1E, 0x0FFFEF00); - upmc_write (0x1F, 0x3FFFEC05); -#endif /* CONFIG_CAN_DRIVER */ -} - -/* - * Initialize PCI Devices, report devices found. - */ - -#ifdef CONFIG_PCI1 -static struct pci_controller pci1_hose; -#endif /* CONFIG_PCI1 */ - -void pci_init_board (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int first_free_busno = 0; -#ifdef CONFIG_PCI1 - struct fsl_pci_info pci_info; - int pcie_ep; - - u32 devdisr = in_be32(&gur->devdisr); - - uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32; - uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB; - uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */ - uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD; - - if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info, 1); - set_next_law(pci_info.mem_phys, - law_size_bits(pci_info.mem_size), pci_info.law); - set_next_law(pci_info.io_phys, - law_size_bits(pci_info.io_size), pci_info.law); - - pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs); - printf("PCI1: %d bit, %s MHz, %s, %s, %s\n", - (pci_32) ? 32 : 64, - (pci_speed == 33333333) ? "33" : - (pci_speed == 66666666) ? "66" : "unknown", - pci_clk_sel ? "sync" : "async", - pcie_ep ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter"); - first_free_busno = fsl_pci_init_port(&pci_info, - &pci1_hose, first_free_busno); -#ifdef CONFIG_PCIX_CHECK - if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) { - ushort reg16 = - PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | - PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; - uint dev = PCI_BDF(0, 0, 0); - - /* PCI-X init */ - if (CONFIG_SYS_CLK_FREQ < 66000000) - puts ("PCI-X will only work at 66 MHz\n"); - - pci_write_config_word(dev, PCIX_COMMAND, reg16); - } -#endif - } else { - printf("PCI1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); -#endif - - fsl_pcie_init_board(first_free_busno); -} - -#ifdef CONFIG_OF_BOARD_SETUP -void ft_board_setup (void *blob, bd_t *bd) -{ - ft_cpu_setup (blob, bd); - - FT_FSL_PCI_SETUP; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -#ifdef CONFIG_BOARD_EARLY_INIT_R -int board_early_init_r (void) -{ -#ifdef CONFIG_PS2MULT - ps2mult_early_init (); -#endif /* CONFIG_PS2MULT */ - return (0); -} -#endif /* CONFIG_BOARD_EARLY_INIT_R */ - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Intialize TSECs first */ - return pci_eth_init(bis); -} diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index 4f08be61f1..e905c26c6f 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -43,8 +43,6 @@ SECTIONS drivers/pcmcia/libpcmcia.o (.text.pcmcia_hardware_enable) drivers/rtc/librtc.o (.text*) drivers/misc/libmisc.o (.text*) - *(.text.print_buffer) - *(.text.print_size) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.ppcenv*) diff --git a/boards.cfg b/boards.cfg index fe201c2669..7c1fc7427a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -841,13 +841,6 @@ BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freesca stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M -TQM8540 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8540,TQM8540=y,HOSTNAME=tqm8540,BOARDNAME="TQM8540" -TQM8541 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8541,TQM8541=y,HOSTNAME=tqm8541,BOARDNAME="TQM8541" -TQM8548 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8548,TQM8548=y,HOSTNAME=tqm8548,BOARDNAME="TQM8548" -TQM8548_AG powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8548,TQM8548_AG=y,HOSTNAME=tqm8485,BOARDNAME="TQM8548_AG" -TQM8548_BE powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8548,TQM8548_BE=y,HOSTNAME=tqm8548,BOARDNAME="TQM8548_BE" -TQM8555 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8555,TQM8555=y,HOSTNAME=tqm8555,BOARDNAME="TQM8555" -TQM8560 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8560,TQM8560=y,HOSTNAME=tqm8560,BOARDNAME="TQM8560" xpedite520x powerpc mpc85xx - xes xpedite537x powerpc mpc85xx - xes xpedite550x powerpc mpc85xx - xes diff --git a/common/Makefile b/common/Makefile index 5442fbbc99..973f05a99f 100644 --- a/common/Makefile +++ b/common/Makefile @@ -107,6 +107,7 @@ COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o +COBJS-$(CONFIG_CMD_INI) += cmd_ini.o COBJS-$(CONFIG_CMD_IRQ) += cmd_irq.o COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o diff --git a/common/cmd_cache.c b/common/cmd_cache.c index 9c228e219d..5512f924b1 100644 --- a/common/cmd_cache.c +++ b/common/cmd_cache.c @@ -36,21 +36,24 @@ void __weak invalidate_icache_all(void) puts("No arch specific invalidate_icache_all available!\n"); } -int do_icache ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_icache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { switch (argc) { case 2: /* on / off */ switch (parse_argv(argv[1])) { - case 0: icache_disable(); + case 0: + icache_disable(); break; - case 1: icache_enable (); + case 1: + icache_enable(); break; - case 2: invalidate_icache_all(); + case 2: + invalidate_icache_all(); break; } - /* FALL TROUGH */ + break; case 1: /* get status */ - printf ("Instruction Cache is %s\n", + printf("Instruction Cache is %s\n", icache_status() ? "ON" : "OFF"); return 0; default: @@ -65,40 +68,42 @@ void __weak flush_dcache_all(void) /* please define arch specific flush_dcache_all */ } -int do_dcache ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { switch (argc) { - case 2: /* on / off */ + case 2: /* on / off */ switch (parse_argv(argv[1])) { - case 0: dcache_disable(); + case 0: + dcache_disable(); break; - case 1: dcache_enable (); + case 1: + dcache_enable(); break; - case 2: flush_dcache_all(); + case 2: + flush_dcache_all(); break; } - /* FALL TROUGH */ + break; case 1: /* get status */ - printf ("Data (writethrough) Cache is %s\n", + printf("Data (writethrough) Cache is %s\n", dcache_status() ? "ON" : "OFF"); return 0; default: return CMD_RET_USAGE; } return 0; - } static int parse_argv(const char *s) { - if (strcmp(s, "flush") == 0) { - return (2); - } else if (strcmp(s, "on") == 0) { - return (1); - } else if (strcmp(s, "off") == 0) { - return (0); - } - return (-1); + if (strcmp(s, "flush") == 0) + return 2; + else if (strcmp(s, "on") == 0) + return 1; + else if (strcmp(s, "off") == 0) + return 0; + + return -1; } diff --git a/common/cmd_echo.c b/common/cmd_echo.c index 43a6da5722..1e499fb0db 100644 --- a/common/cmd_echo.c +++ b/common/cmd_echo.c @@ -30,17 +30,31 @@ int do_echo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int putnl = 1; for (i = 1; i < argc; i++) { - char *p = argv[i], c; + char *p = argv[i]; + char *nls; /* new-line suppression */ if (i > 1) putc(' '); - while ((c = *p++) != '\0') { - if (c == '\\' && *p == 'c') { - putnl = 0; - p++; - } else { - putc(c); + + nls = strstr(p, "\\c"); + if (nls) { + char *prenls = p; + + putnl = 0; + /* + * be paranoid and guess that someone might + * say \c more than once + */ + while (nls) { + *nls = '\0'; + puts(prenls); + *nls = '\\'; + prenls = nls + 2; + nls = strstr(prenls, "\\c"); } + puts(prenls); + } else { + puts(p); } } diff --git a/common/cmd_ini.c b/common/cmd_ini.c new file mode 100644 index 0000000000..74481cbf6f --- /dev/null +++ b/common/cmd_ini.c @@ -0,0 +1,275 @@ +/* + * inih -- simple .INI file parser + * + * Copyright (c) 2009, Brush Technology + * Copyright (c) 2012: + * Joe Hershberger, National Instruments, joe.hershberger@ni.com + * All rights reserved. + * + * The "inih" library is distributed under the following license, which is + * derived from and very similar to the 3-clause BSD license: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Brush Technology nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRUSH TECHNOLOGY ''AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL BRUSH TECHNOLOGY BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Go to the project home page for more info: + * http://code.google.com/p/inih/ + */ + +#include <common.h> +#include <command.h> +#include <environment.h> +#include <linux/ctype.h> +#include <linux/string.h> + +#ifdef CONFIG_INI_MAX_LINE +#define MAX_LINE CONFIG_INI_MAX_LINE +#else +#define MAX_LINE 200 +#endif + +#ifdef CONFIG_INI_MAX_SECTION +#define MAX_SECTION CONFIG_INI_MAX_SECTION +#else +#define MAX_SECTION 50 +#endif + +#ifdef CONFIG_INI_MAX_NAME +#define MAX_NAME CONFIG_INI_MAX_NAME +#else +#define MAX_NAME 50 +#endif + +/* Strip whitespace chars off end of given string, in place. Return s. */ +static char *rstrip(char *s) +{ + char *p = s + strlen(s); + + while (p > s && isspace(*--p)) + *p = '\0'; + return s; +} + +/* Return pointer to first non-whitespace char in given string. */ +static char *lskip(const char *s) +{ + while (*s && isspace(*s)) + s++; + return (char *)s; +} + +/* Return pointer to first char c or ';' comment in given string, or pointer to + null at end of string if neither found. ';' must be prefixed by a whitespace + character to register as a comment. */ +static char *find_char_or_comment(const char *s, char c) +{ + int was_whitespace = 0; + + while (*s && *s != c && !(was_whitespace && *s == ';')) { + was_whitespace = isspace(*s); + s++; + } + return (char *)s; +} + +/* Version of strncpy that ensures dest (size bytes) is null-terminated. */ +static char *strncpy0(char *dest, const char *src, size_t size) +{ + strncpy(dest, src, size); + dest[size - 1] = '\0'; + return dest; +} + +/* Emulate the behavior of fgets but on memory */ +static char *memgets(char *str, int num, char **mem, size_t *memsize) +{ + char *end; + int len; + int newline = 1; + + end = memchr(*mem, '\n', *memsize); + if (end == NULL) { + if (*memsize == 0) + return NULL; + end = *mem + *memsize; + newline = 0; + } + len = min((end - *mem) + newline, num); + memcpy(str, *mem, len); + if (len < num) + str[len] = '\0'; + + /* prepare the mem vars for the next call */ + *memsize -= (end - *mem) + newline; + *mem += (end - *mem) + newline; + + return str; +} + +/* Parse given INI-style file. May have [section]s, name=value pairs + (whitespace stripped), and comments starting with ';' (semicolon). Section + is "" if name=value pair parsed before any section heading. name:value + pairs are also supported as a concession to Python's ConfigParser. + + For each name=value pair parsed, call handler function with given user + pointer as well as section, name, and value (data only valid for duration + of handler call). Handler should return nonzero on success, zero on error. + + Returns 0 on success, line number of first error on parse error (doesn't + stop on first error). +*/ +static int ini_parse(char *filestart, size_t filelen, + int (*handler)(void *, char *, char *, char *), void *user) +{ + /* Uses a fair bit of stack (use heap instead if you need to) */ + char line[MAX_LINE]; + char section[MAX_SECTION] = ""; + char prev_name[MAX_NAME] = ""; + + char *curmem = filestart; + char *start; + char *end; + char *name; + char *value; + size_t memleft = filelen; + int lineno = 0; + int error = 0; + + /* Scan through file line by line */ + while (memgets(line, sizeof(line), &curmem, &memleft) != NULL) { + lineno++; + start = lskip(rstrip(line)); + + if (*start == ';' || *start == '#') { + /* + * Per Python ConfigParser, allow '#' comments at start + * of line + */ + } +#if CONFIG_INI_ALLOW_MULTILINE + else if (*prev_name && *start && start > line) { + /* + * Non-blank line with leading whitespace, treat as + * continuation of previous name's value (as per Python + * ConfigParser). + */ + if (!handler(user, section, prev_name, start) && !error) + error = lineno; + } +#endif + else if (*start == '[') { + /* A "[section]" line */ + end = find_char_or_comment(start + 1, ']'); + if (*end == ']') { + *end = '\0'; + strncpy0(section, start + 1, sizeof(section)); + *prev_name = '\0'; + } else if (!error) { + /* No ']' found on section line */ + error = lineno; + } + } else if (*start && *start != ';') { + /* Not a comment, must be a name[=:]value pair */ + end = find_char_or_comment(start, '='); + if (*end != '=') + end = find_char_or_comment(start, ':'); + if (*end == '=' || *end == ':') { + *end = '\0'; + name = rstrip(start); + value = lskip(end + 1); + end = find_char_or_comment(value, '\0'); + if (*end == ';') + *end = '\0'; + rstrip(value); + /* Strip double-quotes */ + if (value[0] == '"' && + value[strlen(value)-1] == '"') { + value[strlen(value)-1] = '\0'; + value += 1; + } + + /* + * Valid name[=:]value pair found, call handler + */ + strncpy0(prev_name, name, sizeof(prev_name)); + if (!handler(user, section, name, value) && + !error) + error = lineno; + } else if (!error) + /* No '=' or ':' found on name[=:]value line */ + error = lineno; + } + } + + return error; +} + +static int ini_handler(void *user, char *section, char *name, char *value) +{ + char *requested_section = (char *)user; +#ifdef CONFIG_INI_CASE_INSENSITIVE + int i; + + for (i = 0; i < strlen(requested_section); i++) + requested_section[i] = tolower(requested_section[i]); + for (i = 0; i < strlen(section); i++) + section[i] = tolower(section[i]); +#endif + + if (!strcmp(section, requested_section)) { +#ifdef CONFIG_INI_CASE_INSENSITIVE + for (i = 0; i < strlen(name); i++) + name[i] = tolower(name[i]); + for (i = 0; i < strlen(value); i++) + value[i] = tolower(value[i]); +#endif + setenv(name, value); + printf("ini: Imported %s as %s\n", name, value); + } + + /* success */ + return 1; +} + +static int do_ini(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const char *section; + char *file_address; + size_t file_size; + + if (argc == 1) + return CMD_RET_USAGE; + + section = argv[1]; + file_address = (char *)simple_strtoul( + argc < 3 ? getenv("loadaddr") : argv[2], NULL, 16); + file_size = (size_t)simple_strtoul( + argc < 4 ? getenv("filesize") : argv[3], NULL, 16); + + return ini_parse(file_address, file_size, ini_handler, (void *)section); +} + +U_BOOT_CMD( + ini, 4, 0, do_ini, + "parse an ini file in memory and merge the specified section into the env", + "section [[file-address] file-size]" +); diff --git a/common/cmd_md5sum.c b/common/cmd_md5sum.c index b93dd9b440..3f81fdf6ef 100644 --- a/common/cmd_md5sum.c +++ b/common/cmd_md5sum.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2011 + * Joe Hershberger, National Instruments, joe.hershberger@ni.com + * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * @@ -25,6 +28,125 @@ #include <command.h> #include <u-boot/md5.h> +/* + * Store the resulting sum to an address or variable + */ +static void store_result(const u8 *sum, const char *dest) +{ + unsigned int i; + + if (*dest == '*') { + u8 *ptr; + + ptr = (u8 *)simple_strtoul(dest + 1, NULL, 16); + for (i = 0; i < 16; i++) + *ptr++ = sum[i]; + } else { + char str_output[33]; + char *str_ptr = str_output; + + for (i = 0; i < 16; i++) { + sprintf(str_ptr, "%02x", sum[i]); + str_ptr += 2; + } + str_ptr = '\0'; + setenv(dest, str_output); + } +} + +#ifdef CONFIG_MD5SUM_VERIFY +static int parse_verify_sum(char *verify_str, u8 *vsum) +{ + if (*verify_str == '*') { + u8 *ptr; + + ptr = (u8 *)simple_strtoul(verify_str + 1, NULL, 16); + memcpy(vsum, ptr, 16); + } else { + unsigned int i; + char *vsum_str; + + if (strlen(verify_str) == 32) + vsum_str = verify_str; + else { + vsum_str = getenv(verify_str); + if (vsum_str == NULL || strlen(vsum_str) != 32) + return 1; + } + + for (i = 0; i < 16; i++) { + char *nullp = vsum_str + (i + 1) * 2; + char end = *nullp; + + *nullp = '\0'; + *(u8 *)(vsum + i) = + simple_strtoul(vsum_str + (i * 2), NULL, 16); + *nullp = end; + } + } + return 0; +} + +int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ulong addr, len; + unsigned int i; + u8 output[16]; + u8 vsum[16]; + int verify = 0; + int ac; + char * const *av; + + if (argc < 3) + return CMD_RET_USAGE; + + av = argv + 1; + ac = argc - 1; + if (strcmp(*av, "-v") == 0) { + verify = 1; + av++; + ac--; + if (ac < 3) + return CMD_RET_USAGE; + } + + addr = simple_strtoul(*av++, NULL, 16); + len = simple_strtoul(*av++, NULL, 16); + + md5_wd((unsigned char *) addr, len, output, CHUNKSZ_MD5); + + if (!verify) { + printf("md5 for %08lx ... %08lx ==> ", addr, addr + len - 1); + for (i = 0; i < 16; i++) + printf("%02x", output[i]); + printf("\n"); + + if (ac > 2) + store_result(output, *av); + } else { + char *verify_str = *av++; + + if (parse_verify_sum(verify_str, vsum)) { + printf("ERROR: %s does not contain a valid md5 sum\n", + verify_str); + return 1; + } + if (memcmp(output, vsum, 16) != 0) { + printf("md5 for %08lx ... %08lx ==> ", addr, + addr + len - 1); + for (i = 0; i < 16; i++) + printf("%02x", output[i]); + printf(" != "); + for (i = 0; i < 16; i++) + printf("%02x", vsum[i]); + printf(" ** ERROR **\n"); + return 1; + } + } + + return 0; +} +#else static int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned long addr, len; @@ -43,11 +165,27 @@ static int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("%02x", output[i]); printf("\n"); + if (argc > 3) + store_result(output, argv[3]); + return 0; } +#endif +#ifdef CONFIG_MD5SUM_VERIFY +U_BOOT_CMD( + md5sum, 5, 1, do_md5sum, + "compute MD5 message digest", + "address count [[*]sum]\n" + " - compute MD5 message digest [save to sum]\n" + "md5sum -v address count [*]sum\n" + " - verify md5sum of memory area" +); +#else U_BOOT_CMD( - md5sum, 3, 1, do_md5sum, + md5sum, 4, 1, do_md5sum, "compute MD5 message digest", - "address count" + "address count [[*]sum]\n" + " - compute MD5 message digest [save to sum]" ); +#endif diff --git a/common/cmd_misc.c b/common/cmd_misc.c index 973b1c2082..3b47a0c095 100644 --- a/common/cmd_misc.c +++ b/common/cmd_misc.c @@ -53,3 +53,30 @@ U_BOOT_CMD( "N\n" " - delay execution for N seconds (N is _decimal_ !!!)" ); + +#ifdef CONFIG_CMD_TIMER +static int do_timer(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + static ulong start; + + if (argc != 2) + return CMD_RET_USAGE; + + if (!strcmp(argv[1], "start")) + start = get_timer(0); + + if (!strcmp(argv[1], "get")) { + ulong msecs = get_timer(start) * 1000 / CONFIG_SYS_HZ; + printf("%ld.%03d\n", msecs / 1000, (int)(msecs % 1000)); + } + + return 0; +} + +U_BOOT_CMD( + timer, 2, 1, do_timer, + "access the system timer", + "start - Reset the timer reference.\n" + "timer get - Print the time since 'start'." +); +#endif diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 8ecc498230..bb1d4ec3e5 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -215,6 +215,9 @@ int env_check_apply(const char *name, const char *oldval, { int console = -1; + /* Default value for NULL to protect string-manipulating functions */ + newval = newval ? : ""; + /* Check for console redirection */ if (strcmp(name, "stdin") == 0) console = stdin; diff --git a/common/cmd_sha1sum.c b/common/cmd_sha1sum.c index 2713a14f1f..8db5456c95 100644 --- a/common/cmd_sha1sum.c +++ b/common/cmd_sha1sum.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2011 + * Joe Hershberger, National Instruments, joe.hershberger@ni.com + * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * @@ -25,6 +28,125 @@ #include <command.h> #include <sha1.h> +/* + * Store the resulting sum to an address or variable + */ +static void store_result(const u8 *sum, const char *dest) +{ + unsigned int i; + + if (*dest == '*') { + u8 *ptr; + + ptr = (u8 *)simple_strtoul(dest + 1, NULL, 16); + for (i = 0; i < 20; i++) + *ptr++ = sum[i]; + } else { + char str_output[41]; + char *str_ptr = str_output; + + for (i = 0; i < 20; i++) { + sprintf(str_ptr, "%02x", sum[i]); + str_ptr += 2; + } + str_ptr = '\0'; + setenv(dest, str_output); + } +} + +#ifdef CONFIG_SHA1SUM_VERIFY +static int parse_verify_sum(char *verify_str, u8 *vsum) +{ + if (*verify_str == '*') { + u8 *ptr; + + ptr = (u8 *)simple_strtoul(verify_str + 1, NULL, 16); + memcpy(vsum, ptr, 20); + } else { + unsigned int i; + char *vsum_str; + + if (strlen(verify_str) == 40) + vsum_str = verify_str; + else { + vsum_str = getenv(verify_str); + if (vsum_str == NULL || strlen(vsum_str) != 40) + return 1; + } + + for (i = 0; i < 20; i++) { + char *nullp = vsum_str + (i + 1) * 2; + char end = *nullp; + + *nullp = '\0'; + *(u8 *)(vsum + i) = + simple_strtoul(vsum_str + (i * 2), NULL, 16); + *nullp = end; + } + } + return 0; +} + +int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ulong addr, len; + unsigned int i; + u8 output[20]; + u8 vsum[20]; + int verify = 0; + int ac; + char * const *av; + + if (argc < 3) + return CMD_RET_USAGE; + + av = argv + 1; + ac = argc - 1; + if (strcmp(*av, "-v") == 0) { + verify = 1; + av++; + ac--; + if (ac < 3) + return CMD_RET_USAGE; + } + + addr = simple_strtoul(*av++, NULL, 16); + len = simple_strtoul(*av++, NULL, 16); + + sha1_csum_wd((unsigned char *) addr, len, output, CHUNKSZ_SHA1); + + if (!verify) { + printf("SHA1 for %08lx ... %08lx ==> ", addr, addr + len - 1); + for (i = 0; i < 20; i++) + printf("%02x", output[i]); + printf("\n"); + + if (ac > 2) + store_result(output, *av); + } else { + char *verify_str = *av++; + + if (parse_verify_sum(verify_str, vsum)) { + printf("ERROR: %s does not contain a valid SHA1 sum\n", + verify_str); + return 1; + } + if (memcmp(output, vsum, 20) != 0) { + printf("SHA1 for %08lx ... %08lx ==> ", addr, + addr + len - 1); + for (i = 0; i < 20; i++) + printf("%02x", output[i]); + printf(" != "); + for (i = 0; i < 20; i++) + printf("%02x", vsum[i]); + printf(" ** ERROR **\n"); + return 1; + } + } + + return 0; +} +#else static int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned long addr, len; @@ -43,11 +165,27 @@ static int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("%02x", output[i]); printf("\n"); + if (argc > 3) + store_result(output, argv[3]); + return 0; } +#endif +#ifdef CONFIG_SHA1SUM_VERIFY +U_BOOT_CMD( + sha1sum, 5, 1, do_sha1sum, + "compute SHA1 message digest", + "address count [[*]sum]\n" + " - compute SHA1 message digest [save to sum]\n" + "sha1sum -v address count [*]sum\n" + " - verify sha1sum of memory area" +); +#else U_BOOT_CMD( - sha1sum, 3, 1, do_sha1sum, + sha1sum, 4, 1, do_sha1sum, "compute SHA1 message digest", - "address count" + "address count [[*]sum]\n" + " - compute SHA1 message digest [save to sum]" ); +#endif diff --git a/common/cmd_test.c b/common/cmd_test.c index fcb5ef2f71..6da06b9f78 100644 --- a/common/cmd_test.c +++ b/common/cmd_test.c @@ -33,12 +33,12 @@ int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc < 3) return 1; -#if 0 +#ifdef DEBUG { - printf("test:"); + debug("test(%d):", argc); left = 1; while (argv[left]) - printf(" %s", argv[left++]); + debug(" '%s'", argv[left++]); } #endif diff --git a/common/main.c b/common/main.c index 81984acb00..9507cec88b 100644 --- a/common/main.c +++ b/common/main.c @@ -222,7 +222,8 @@ int abortboot(int bootdelay) #ifdef CONFIG_MENUPROMPT printf(CONFIG_MENUPROMPT); #else - printf("Hit any key to stop autoboot: %2d ", bootdelay); + if (bootdelay >= 0) + printf("Hit any key to stop autoboot: %2d ", bootdelay); #endif #if defined CONFIG_ZERO_BOOTDELAY_CHECK @@ -382,7 +383,7 @@ void main_loop (void) debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>"); - if (bootdelay >= 0 && s && !abortboot (bootdelay)) { + if (bootdelay != -1 && s && !abortboot(bootdelay)) { # ifdef CONFIG_AUTOBOOT_KEYED int prev = disable_ctrlc(1); /* disable Control C checking */ # endif diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 5929a8e0a0..d0f47164d7 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,8 +11,9 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= -apollon arm omap24xx - 2012-09-06 Kyungmin Park <kyungmin.park@samsung.com> -tb0229 mips mips32 - 2011-12-12 +TQM85xx powerpc MPC85xx - - Stefan Roese <sr@denx.de> +apollon arm omap24xx 535c74f 2012-09-18 Kyungmin Park <kyungmin.park@samsung.com> +tb0229 mips mips32 3f3110d 2011-12-12 rmu powerpc MPC850 fb82fd7 2011-12-07 Wolfgang Denk <wd@denx.de> OXC powerpc MPC8240 309a292 2011-12-07 BAB7xx powerpc MPC740/MPC750 c53043b 2011-12-07 Frank Gottschling <fgottschling@eltec.de> diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c index 31c174bd3b..11eb167e37 100644 --- a/drivers/mtd/nand/fsl_upm.c +++ b/drivers/mtd/nand/fsl_upm.c @@ -57,7 +57,7 @@ static void fun_wait(struct fsl_upm_nand *fun) debug("unexpected busy state\n"); } else { /* - * If the R/B pin is not connected, like on the TQM8548, + * If the R/B pin is not connected, * a short delay is necessary. */ udelay(1); @@ -115,10 +115,10 @@ static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar); /* - * Some boards/chips needs this. At least the MPC8360E-RDK and - * TQM8548 need it. Probably weird chip, because I don't see - * any need for this on MPC8555E + Samsung K9F1G08U0A. Usually - * here are 0-2 unexpected busy states per block read. + * Some boards/chips needs this. At least the MPC8360E-RDK + * needs it. Probably weird chip, because I don't see any + * need for this on MPC8555E + Samsung K9F1G08U0A. Usually + * here are 0-2 unexpected busy states per block read. */ if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN) fun_wait(fun); diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index 3deffd523e..d6d55b9fff 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -314,7 +314,7 @@ int ext4fs_checksum_update(unsigned int i) struct ext_filesystem *fs = get_fs(); __u16 crc = 0; - desc = (struct ext2_block_group *)&fs->gd[i]; + desc = (struct ext2_block_group *)&fs->bgd[i]; if (fs->sb->feature_ro_compat & EXT4_FEATURE_RO_COMPAT_GDT_CSUM) { int offset = offsetof(struct ext2_block_group, bg_checksum); @@ -874,17 +874,17 @@ long int ext4fs_get_new_blk_no(void) char *zero_buffer = zalloc(fs->blksz); if (!journal_buffer || !zero_buffer) goto fail; - struct ext2_block_group *gd = (struct ext2_block_group *)fs->gdtable; + struct ext2_block_group *bgd = (struct ext2_block_group *)fs->gdtable; if (fs->first_pass_bbmap == 0) { for (i = 0; i < fs->no_blkgrp; i++) { - if (gd[i].free_blocks) { - if (gd[i].bg_flags & EXT4_BG_BLOCK_UNINIT) { - put_ext4(((uint64_t) (gd[i].block_id * + if (bgd[i].free_blocks) { + if (bgd[i].bg_flags & EXT4_BG_BLOCK_UNINIT) { + put_ext4(((uint64_t) (bgd[i].block_id * fs->blksz)), zero_buffer, fs->blksz); - gd[i].bg_flags = - gd[i]. + bgd[i].bg_flags = + bgd[i]. bg_flags & ~EXT4_BG_BLOCK_UNINIT; memcpy(fs->blk_bmaps[i], zero_buffer, fs->blksz); @@ -897,16 +897,16 @@ long int ext4fs_get_new_blk_no(void) fs->curr_blkno = fs->curr_blkno + (i * fs->blksz * 8); fs->first_pass_bbmap++; - gd[i].free_blocks--; + bgd[i].free_blocks--; fs->sb->free_blocks--; - status = ext4fs_devread(gd[i].block_id * + status = ext4fs_devread(bgd[i].block_id * fs->sect_perblk, 0, fs->blksz, journal_buffer); if (status == 0) goto fail; if (ext4fs_log_journal(journal_buffer, - gd[i].block_id)) + bgd[i].block_id)) goto fail; goto success; } else { @@ -935,19 +935,19 @@ restart: if (bg_idx >= fs->no_blkgrp) goto fail; - if (gd[bg_idx].free_blocks == 0) { + if (bgd[bg_idx].free_blocks == 0) { debug("block group %u is full. Skipping\n", bg_idx); fs->curr_blkno = fs->curr_blkno + blk_per_grp; fs->curr_blkno--; goto restart; } - if (gd[bg_idx].bg_flags & EXT4_BG_BLOCK_UNINIT) { + if (bgd[bg_idx].bg_flags & EXT4_BG_BLOCK_UNINIT) { memset(zero_buffer, '\0', fs->blksz); - put_ext4(((uint64_t) (gd[bg_idx].block_id * fs->blksz)), - zero_buffer, fs->blksz); + put_ext4(((uint64_t) (bgd[bg_idx].block_id * + fs->blksz)), zero_buffer, fs->blksz); memcpy(fs->blk_bmaps[bg_idx], zero_buffer, fs->blksz); - gd[bg_idx].bg_flags = gd[bg_idx].bg_flags & + bgd[bg_idx].bg_flags = bgd[bg_idx].bg_flags & ~EXT4_BG_BLOCK_UNINIT; } @@ -961,18 +961,18 @@ restart: /* journal backup */ if (prev_bg_bitmap_index != bg_idx) { memset(journal_buffer, '\0', fs->blksz); - status = ext4fs_devread(gd[bg_idx].block_id + status = ext4fs_devread(bgd[bg_idx].block_id * fs->sect_perblk, 0, fs->blksz, journal_buffer); if (status == 0) goto fail; if (ext4fs_log_journal(journal_buffer, - gd[bg_idx].block_id)) + bgd[bg_idx].block_id)) goto fail; prev_bg_bitmap_index = bg_idx; } - gd[bg_idx].free_blocks--; + bgd[bg_idx].free_blocks--; fs->sb->free_blocks--; goto success; } @@ -1000,19 +1000,21 @@ int ext4fs_get_new_inode_no(void) char *zero_buffer = zalloc(fs->blksz); if (!journal_buffer || !zero_buffer) goto fail; - struct ext2_block_group *gd = (struct ext2_block_group *)fs->gdtable; + struct ext2_block_group *bgd = (struct ext2_block_group *)fs->gdtable; if (fs->first_pass_ibmap == 0) { for (i = 0; i < fs->no_blkgrp; i++) { - if (gd[i].free_inodes) { - if (gd[i].bg_itable_unused != gd[i].free_inodes) - gd[i].bg_itable_unused = - gd[i].free_inodes; - if (gd[i].bg_flags & EXT4_BG_INODE_UNINIT) { + if (bgd[i].free_inodes) { + if (bgd[i].bg_itable_unused != + bgd[i].free_inodes) + bgd[i].bg_itable_unused = + bgd[i].free_inodes; + if (bgd[i].bg_flags & EXT4_BG_INODE_UNINIT) { put_ext4(((uint64_t) - (gd[i].inode_id * fs->blksz)), + (bgd[i].inode_id * + fs->blksz)), zero_buffer, fs->blksz); - gd[i].bg_flags = gd[i].bg_flags & + bgd[i].bg_flags = bgd[i].bg_flags & ~EXT4_BG_INODE_UNINIT; memcpy(fs->inode_bmaps[i], zero_buffer, fs->blksz); @@ -1025,17 +1027,17 @@ int ext4fs_get_new_inode_no(void) fs->curr_inode_no = fs->curr_inode_no + (i * inodes_per_grp); fs->first_pass_ibmap++; - gd[i].free_inodes--; - gd[i].bg_itable_unused--; + bgd[i].free_inodes--; + bgd[i].bg_itable_unused--; fs->sb->free_inodes--; - status = ext4fs_devread(gd[i].inode_id * + status = ext4fs_devread(bgd[i].inode_id * fs->sect_perblk, 0, fs->blksz, journal_buffer); if (status == 0) goto fail; if (ext4fs_log_journal(journal_buffer, - gd[i].inode_id)) + bgd[i].inode_id)) goto fail; goto success; } else @@ -1047,13 +1049,13 @@ restart: fs->curr_inode_no++; /* get the blockbitmap index respective to blockno */ ibmap_idx = fs->curr_inode_no / inodes_per_grp; - if (gd[ibmap_idx].bg_flags & EXT4_BG_INODE_UNINIT) { + if (bgd[ibmap_idx].bg_flags & EXT4_BG_INODE_UNINIT) { memset(zero_buffer, '\0', fs->blksz); - put_ext4(((uint64_t) (gd[ibmap_idx].inode_id * + put_ext4(((uint64_t) (bgd[ibmap_idx].inode_id * fs->blksz)), zero_buffer, fs->blksz); - gd[ibmap_idx].bg_flags = - gd[ibmap_idx].bg_flags & ~EXT4_BG_INODE_UNINIT; + bgd[ibmap_idx].bg_flags = + bgd[ibmap_idx].bg_flags & ~EXT4_BG_INODE_UNINIT; memcpy(fs->inode_bmaps[ibmap_idx], zero_buffer, fs->blksz); } @@ -1069,21 +1071,22 @@ restart: /* journal backup */ if (prev_inode_bitmap_index != ibmap_idx) { memset(journal_buffer, '\0', fs->blksz); - status = ext4fs_devread(gd[ibmap_idx].inode_id + status = ext4fs_devread(bgd[ibmap_idx].inode_id * fs->sect_perblk, 0, fs->blksz, journal_buffer); if (status == 0) goto fail; if (ext4fs_log_journal(journal_buffer, - gd[ibmap_idx].inode_id)) + bgd[ibmap_idx].inode_id)) goto fail; prev_inode_bitmap_index = ibmap_idx; } - if (gd[ibmap_idx].bg_itable_unused != gd[ibmap_idx].free_inodes) - gd[ibmap_idx].bg_itable_unused = - gd[ibmap_idx].free_inodes; - gd[ibmap_idx].free_inodes--; - gd[ibmap_idx].bg_itable_unused--; + if (bgd[ibmap_idx].bg_itable_unused != + bgd[ibmap_idx].free_inodes) + bgd[ibmap_idx].bg_itable_unused = + bgd[ibmap_idx].free_inodes; + bgd[ibmap_idx].free_inodes--; + bgd[ibmap_idx].bg_itable_unused--; fs->sb->free_inodes--; goto success; } diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index 93dcb7e8fa..3a5ef20a4b 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -209,14 +209,14 @@ static void ext4fs_update(void) /* update block groups */ for (i = 0; i < fs->no_blkgrp; i++) { - fs->gd[i].bg_checksum = ext4fs_checksum_update(i); - put_ext4((uint64_t)(fs->gd[i].block_id * fs->blksz), + fs->bgd[i].bg_checksum = ext4fs_checksum_update(i); + put_ext4((uint64_t)(fs->bgd[i].block_id * fs->blksz), fs->blk_bmaps[i], fs->blksz); } /* update inode table groups */ for (i = 0; i < fs->no_blkgrp; i++) { - put_ext4((uint64_t) (fs->gd[i].inode_id * fs->blksz), + put_ext4((uint64_t) (fs->bgd[i].inode_id * fs->blksz), fs->inode_bmaps[i], fs->blksz); } @@ -266,7 +266,7 @@ fail: static void delete_single_indirect_block(struct ext2_inode *inode) { - struct ext2_block_group *gd = NULL; + struct ext2_block_group *bgd = NULL; static int prev_bg_bmap_idx = -1; long int blknr; int remainder; @@ -280,7 +280,7 @@ static void delete_single_indirect_block(struct ext2_inode *inode) return; } /* get block group descriptor table */ - gd = (struct ext2_block_group *)fs->gdtable; + bgd = (struct ext2_block_group *)fs->gdtable; /* deleting the single indirect block associated with inode */ if (inode->b.blocks.indir_block != 0) { @@ -295,18 +295,18 @@ static void delete_single_indirect_block(struct ext2_inode *inode) bg_idx--; } ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx); - gd[bg_idx].free_blocks++; + bgd[bg_idx].free_blocks++; fs->sb->free_blocks++; /* journal backup */ if (prev_bg_bmap_idx != bg_idx) { status = - ext4fs_devread(gd[bg_idx].block_id * + ext4fs_devread(bgd[bg_idx].block_id * fs->sect_perblk, 0, fs->blksz, journal_buffer); if (status == 0) goto fail; if (ext4fs_log_journal - (journal_buffer, gd[bg_idx].block_id)) + (journal_buffer, bgd[bg_idx].block_id)) goto fail; prev_bg_bmap_idx = bg_idx; } @@ -326,7 +326,7 @@ static void delete_double_indirect_block(struct ext2_inode *inode) unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group; unsigned int *di_buffer = NULL; unsigned int *DIB_start_addr = NULL; - struct ext2_block_group *gd = NULL; + struct ext2_block_group *bgd = NULL; struct ext_filesystem *fs = get_fs(); char *journal_buffer = zalloc(fs->blksz); if (!journal_buffer) { @@ -334,7 +334,7 @@ static void delete_double_indirect_block(struct ext2_inode *inode) return; } /* get the block group descriptor table */ - gd = (struct ext2_block_group *)fs->gdtable; + bgd = (struct ext2_block_group *)fs->gdtable; if (inode->b.blocks.double_indir_block != 0) { di_buffer = zalloc(fs->blksz); @@ -362,11 +362,11 @@ static void delete_double_indirect_block(struct ext2_inode *inode) ext4fs_reset_block_bmap(*di_buffer, fs->blk_bmaps[bg_idx], bg_idx); di_buffer++; - gd[bg_idx].free_blocks++; + bgd[bg_idx].free_blocks++; fs->sb->free_blocks++; /* journal backup */ if (prev_bg_bmap_idx != bg_idx) { - status = ext4fs_devread(gd[bg_idx].block_id + status = ext4fs_devread(bgd[bg_idx].block_id * fs->sect_perblk, 0, fs->blksz, journal_buffer); @@ -374,7 +374,7 @@ static void delete_double_indirect_block(struct ext2_inode *inode) goto fail; if (ext4fs_log_journal(journal_buffer, - gd[bg_idx].block_id)) + bgd[bg_idx].block_id)) goto fail; prev_bg_bmap_idx = bg_idx; } @@ -391,19 +391,19 @@ static void delete_double_indirect_block(struct ext2_inode *inode) bg_idx--; } ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx); - gd[bg_idx].free_blocks++; + bgd[bg_idx].free_blocks++; fs->sb->free_blocks++; /* journal backup */ if (prev_bg_bmap_idx != bg_idx) { memset(journal_buffer, '\0', fs->blksz); - status = ext4fs_devread(gd[bg_idx].block_id * + status = ext4fs_devread(bgd[bg_idx].block_id * fs->sect_perblk, 0, fs->blksz, journal_buffer); if (status == 0) goto fail; if (ext4fs_log_journal(journal_buffer, - gd[bg_idx].block_id)) + bgd[bg_idx].block_id)) goto fail; prev_bg_bmap_idx = bg_idx; } @@ -427,7 +427,7 @@ static void delete_triple_indirect_block(struct ext2_inode *inode) unsigned int *tib_start_addr = NULL; unsigned int *tip_buffer = NULL; unsigned int *tipb_start_addr = NULL; - struct ext2_block_group *gd = NULL; + struct ext2_block_group *bgd = NULL; struct ext_filesystem *fs = get_fs(); char *journal_buffer = zalloc(fs->blksz); if (!journal_buffer) { @@ -435,7 +435,7 @@ static void delete_triple_indirect_block(struct ext2_inode *inode) return; } /* get block group descriptor table */ - gd = (struct ext2_block_group *)fs->gdtable; + bgd = (struct ext2_block_group *)fs->gdtable; if (inode->b.blocks.triple_indir_block != 0) { tigp_buffer = zalloc(fs->blksz); @@ -477,20 +477,21 @@ static void delete_triple_indirect_block(struct ext2_inode *inode) bg_idx); tip_buffer++; - gd[bg_idx].free_blocks++; + bgd[bg_idx].free_blocks++; fs->sb->free_blocks++; /* journal backup */ if (prev_bg_bmap_idx != bg_idx) { status = - ext4fs_devread(gd[bg_idx].block_id * - fs->sect_perblk, 0, - fs->blksz, - journal_buffer); + ext4fs_devread( + bgd[bg_idx].block_id * + fs->sect_perblk, 0, + fs->blksz, + journal_buffer); if (status == 0) goto fail; if (ext4fs_log_journal(journal_buffer, - gd[bg_idx]. + bgd[bg_idx]. block_id)) goto fail; prev_bg_bmap_idx = bg_idx; @@ -516,20 +517,20 @@ static void delete_triple_indirect_block(struct ext2_inode *inode) fs->blk_bmaps[bg_idx], bg_idx); tigp_buffer++; - gd[bg_idx].free_blocks++; + bgd[bg_idx].free_blocks++; fs->sb->free_blocks++; /* journal backup */ if (prev_bg_bmap_idx != bg_idx) { memset(journal_buffer, '\0', fs->blksz); status = - ext4fs_devread(gd[bg_idx].block_id * + ext4fs_devread(bgd[bg_idx].block_id * fs->sect_perblk, 0, fs->blksz, journal_buffer); if (status == 0) goto fail; if (ext4fs_log_journal(journal_buffer, - gd[bg_idx].block_id)) + bgd[bg_idx].block_id)) goto fail; prev_bg_bmap_idx = bg_idx; } @@ -546,19 +547,19 @@ static void delete_triple_indirect_block(struct ext2_inode *inode) bg_idx--; } ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx); - gd[bg_idx].free_blocks++; + bgd[bg_idx].free_blocks++; fs->sb->free_blocks++; /* journal backup */ if (prev_bg_bmap_idx != bg_idx) { memset(journal_buffer, '\0', fs->blksz); - status = ext4fs_devread(gd[bg_idx].block_id * + status = ext4fs_devread(bgd[bg_idx].block_id * fs->sect_perblk, 0, fs->blksz, journal_buffer); if (status == 0) goto fail; if (ext4fs_log_journal(journal_buffer, - gd[bg_idx].block_id)) + bgd[bg_idx].block_id)) goto fail; prev_bg_bmap_idx = bg_idx; } @@ -590,13 +591,13 @@ static int ext4fs_delete_file(int inodeno) unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group; unsigned int inode_per_grp = ext4fs_root->sblock.inodes_per_group; struct ext2_inode *inode_buffer = NULL; - struct ext2_block_group *gd = NULL; + struct ext2_block_group *bgd = NULL; struct ext_filesystem *fs = get_fs(); char *journal_buffer = zalloc(fs->blksz); if (!journal_buffer) return -ENOMEM; /* get the block group descriptor table */ - gd = (struct ext2_block_group *)fs->gdtable; + bgd = (struct ext2_block_group *)fs->gdtable; status = ext4fs_read_inode(ext4fs_root, inodeno, &inode); if (status == 0) goto fail; @@ -631,19 +632,19 @@ static int ext4fs_delete_file(int inodeno) debug("EXT4_EXTENTS Block releasing %ld: %d\n", blknr, bg_idx); - gd[bg_idx].free_blocks++; + bgd[bg_idx].free_blocks++; fs->sb->free_blocks++; /* journal backup */ if (prev_bg_bmap_idx != bg_idx) { status = - ext4fs_devread(gd[bg_idx].block_id * + ext4fs_devread(bgd[bg_idx].block_id * fs->sect_perblk, 0, fs->blksz, journal_buffer); if (status == 0) goto fail; if (ext4fs_log_journal(journal_buffer, - gd[bg_idx].block_id)) + bgd[bg_idx].block_id)) goto fail; prev_bg_bmap_idx = bg_idx; } @@ -676,19 +677,19 @@ static int ext4fs_delete_file(int inodeno) bg_idx); debug("ActualB releasing %ld: %d\n", blknr, bg_idx); - gd[bg_idx].free_blocks++; + bgd[bg_idx].free_blocks++; fs->sb->free_blocks++; /* journal backup */ if (prev_bg_bmap_idx != bg_idx) { memset(journal_buffer, '\0', fs->blksz); - status = ext4fs_devread(gd[bg_idx].block_id + status = ext4fs_devread(bgd[bg_idx].block_id * fs->sect_perblk, 0, fs->blksz, journal_buffer); if (status == 0) goto fail; if (ext4fs_log_journal(journal_buffer, - gd[bg_idx].block_id)) + bgd[bg_idx].block_id)) goto fail; prev_bg_bmap_idx = bg_idx; } @@ -701,7 +702,7 @@ static int ext4fs_delete_file(int inodeno) /* get the block no */ inodeno--; - blkno = __le32_to_cpu(gd[ibmap_idx].inode_table_id) + + blkno = __le32_to_cpu(bgd[ibmap_idx].inode_table_id) + (inodeno % __le32_to_cpu(inode_per_grp)) / inodes_per_block; /* get the offset of the inode */ @@ -731,15 +732,15 @@ static int ext4fs_delete_file(int inodeno) /* update the respective inode bitmaps */ inodeno++; ext4fs_reset_inode_bmap(inodeno, fs->inode_bmaps[ibmap_idx], ibmap_idx); - gd[ibmap_idx].free_inodes++; + bgd[ibmap_idx].free_inodes++; fs->sb->free_inodes++; /* journal backup */ memset(journal_buffer, '\0', fs->blksz); - status = ext4fs_devread(gd[ibmap_idx].inode_id * + status = ext4fs_devread(bgd[ibmap_idx].inode_id * fs->sect_perblk, 0, fs->blksz, journal_buffer); if (status == 0) goto fail; - if (ext4fs_log_journal(journal_buffer, gd[ibmap_idx].inode_id)) + if (ext4fs_log_journal(journal_buffer, bgd[ibmap_idx].inode_id)) goto fail; ext4fs_update(); @@ -797,7 +798,7 @@ int ext4fs_init(void) printf("Error in getting the block group descriptor table\n"); goto fail; } - fs->gd = (struct ext2_block_group *)fs->gdtable; + fs->bgd = (struct ext2_block_group *)fs->gdtable; /* load all the available bitmap block of the partition */ fs->blk_bmaps = zalloc(fs->no_blkgrp * sizeof(char *)); @@ -811,7 +812,7 @@ int ext4fs_init(void) for (i = 0; i < fs->no_blkgrp; i++) { status = - ext4fs_devread(fs->gd[i].block_id * fs->sect_perblk, 0, + ext4fs_devread(fs->bgd[i].block_id * fs->sect_perblk, 0, fs->blksz, (char *)fs->blk_bmaps[i]); if (status == 0) goto fail; @@ -828,7 +829,7 @@ int ext4fs_init(void) } for (i = 0; i < fs->no_blkgrp; i++) { - status = ext4fs_devread(fs->gd[i].inode_id * fs->sect_perblk, + status = ext4fs_devread(fs->bgd[i].inode_id * fs->sect_perblk, 0, fs->blksz, (char *)fs->inode_bmaps[i]); if (status == 0) @@ -842,7 +843,7 @@ int ext4fs_init(void) * reboot of a linux kernel */ for (i = 0; i < fs->no_blkgrp; i++) - real_free_blocks = real_free_blocks + fs->gd[i].free_blocks; + real_free_blocks = real_free_blocks + fs->bgd[i].free_blocks; if (real_free_blocks != fs->sb->free_blocks) fs->sb->free_blocks = real_free_blocks; @@ -907,7 +908,7 @@ void ext4fs_deinit(void) free(fs->gdtable); fs->gdtable = NULL; - fs->gd = NULL; + fs->bgd = NULL; /* * reinitiliazed the global inode and * block bitmap first execution check variables @@ -1087,7 +1088,7 @@ int ext4fs_write(const char *fname, unsigned char *buffer, goto fail; ibmap_idx = inodeno / ext4fs_root->sblock.inodes_per_group; inodeno--; - itable_blkno = __le32_to_cpu(fs->gd[ibmap_idx].inode_table_id) + + itable_blkno = __le32_to_cpu(fs->bgd[ibmap_idx].inode_table_id) + (inodeno % __le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block; blkoff = (inodeno % inodes_per_block) * fs->inodesz; @@ -1105,7 +1106,7 @@ int ext4fs_write(const char *fname, unsigned char *buffer, } ibmap_idx = parent_inodeno / ext4fs_root->sblock.inodes_per_group; parent_inodeno--; - parent_itable_blkno = __le32_to_cpu(fs->gd[ibmap_idx].inode_table_id) + + parent_itable_blkno = __le32_to_cpu(fs->bgd[ibmap_idx].inode_table_id) + (parent_inodeno % __le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block; blkoff = (parent_inodeno % inodes_per_block) * fs->inodesz; diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h deleted file mode 100644 index 95455c49c3..0000000000 --- a/include/configs/TQM85xx.h +++ /dev/null @@ -1,697 +0,0 @@ -/* - * (C) Copyright 2007 - * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de. - * - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Wolfgang Denk <wd@denx.de> - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao <X.Xiao@motorola.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * TQM85xx (8560/40/55/41/48) board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ - -#if defined(CONFIG_TQM8548_BE) -#define CONFIG_SYS_TEXT_BASE 0xfff80000 -#else -#define CONFIG_SYS_TEXT_BASE 0xfffc0000 -#endif - -#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE) -#define CONFIG_TQM8548 -#endif - -#define CONFIG_PCI -#ifndef CONFIG_TQM8548_AG -#define CONFIG_PCI1 /* PCI/PCI-X controller */ -#endif -#ifdef CONFIG_TQM8548 -#define CONFIG_PCIE1 /* PCI Express interface */ -#endif - -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ - -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - - /* - * Configuration for big NOR Flashes - * - * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash. - * Please be aware, that this changes the whole memory map (new CCSRBAR - * address, etc). You have to use an adapted Linux kernel or FDT blob - * if this option is set. - */ -#undef CONFIG_TQM_BIGFLASH - -/* - * NAND flash support (disabled by default) - * - * Warning: NAND support will likely increase the U-Boot image size - * to more than 256 KB. Please adjust CONFIG_SYS_TEXT_BASE if necessary. - */ -#ifdef CONFIG_TQM8548_BE -#define CONFIG_NAND -#endif - -/* - * MPC8540 and MPC8548 don't have CPM module - */ -#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548) -#define CONFIG_CPM2 1 /* has CPM2 */ -#endif - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE) -#define CONFIG_CAN_DRIVER /* CAN Driver support */ -#endif - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33333333 - * 66666666 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33333333 -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END 0x10000000 - -#ifdef CONFIG_TQM_BIGFLASH -#define CONFIG_SYS_CCSRBAR 0xA0000000 -#else -#define CONFIG_SYS_CCSRBAR 0xE0000000 -#endif -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* - * DDR Setup - */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ - -#if defined(CONFIG_TQM_BIGFLASH) || \ - (!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE)) -#define CONFIG_SYS_PPC_DDR_WIMGE (MAS2_I | MAS2_G) -#define CONFIG_SYS_DDR_EARLY_SIZE_MB (512) -#else -#define CONFIG_SYS_PPC_DDR_WIMGE (0) -#define CONFIG_SYS_DDR_EARLY_SIZE_MB (2 * 1024) -#endif - -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#ifdef CONFIG_TQM8548_AG -#define CONFIG_VERY_BIG_RAM -#endif - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) -/* TQM8540 & 8560 need DLL-override */ -#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ -#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */ -#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */ - -#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \ - defined(CONFIG_TQM8548) -#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ -#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */ - -/* - * Flash on the Local Bus - */ -#ifdef CONFIG_TQM_BIGFLASH -#define CONFIG_SYS_FLASH0 0xE0000000 -#define CONFIG_SYS_FLASH1 0xC0000000 -#else /* !CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_FLASH0 0xFC000000 -#define CONFIG_SYS_FLASH1 0xF8000000 -#endif /* CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } - -#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ - -/* Default ORx timings are for <= 41.7 MHz Local Bus Clock. - * - * Note: According to timing specifications external addr latch delay - * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz. - * - * For other Local Bus Clocks see following table: - * - * Clock/MHz CONFIG_SYS_ORx_PRELIM - * 166 0x.....CA5 - * 133 0x.....C85 - * 100 0x.....C65 - * 83 0x.....FA2 - * 66 0x.....C82 - * 50 0x.....C60 - * 42 0x.....040 - * 33 0x.....030 - * 25 0x.....020 - * - */ -#ifdef CONFIG_TQM_BIGFLASH -#define CONFIG_SYS_BR0_PRELIM 0xE0001801 /* port size 32bit */ -#define CONFIG_SYS_OR0_PRELIM 0xE0000040 /* 512MB Flash */ -#define CONFIG_SYS_BR1_PRELIM 0xC0001801 /* port size 32bit */ -#define CONFIG_SYS_OR1_PRELIM 0xE0000040 /* 512MB Flash */ -#else /* !CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_BR0_PRELIM 0xfc001801 /* port size 32bit */ -#define CONFIG_SYS_OR0_PRELIM 0xfc000040 /* 64MB Flash */ -#define CONFIG_SYS_BR1_PRELIM 0xf8001801 /* port size 32bit */ -#define CONFIG_SYS_OR1_PRELIM 0xfc000040 /* 64MB Flash */ -#endif /* CONFIG_TQM_BIGFLASH */ - -#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* speed up output to Flash */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -/* - * Note: when changing the Local Bus clock divider you have to - * change the timing values in CONFIG_SYS_ORx_PRELIM. - * - * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8. - * LCRR[16:17] EADC : External address delay cycles. It should be set to 2 - * for Local Bus Clock > 83.3 MHz. - */ -#define CONFIG_SYS_LBC_LCRR 0x00030008 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_CCSRBAR \ - + 0x04010000) /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)/* Reserved for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#if defined(CONFIG_TQM8560) - -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -#else /* !CONFIG_TQM8560 */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* PS/2 Keyboard */ -#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ -#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ -#define CONFIG_PS2SERIAL 2 /* .. on DUART2 */ -#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */ -#define CONFIG_BOARD_EARLY_INIT_R 1 - -#endif /* CONFIG_TQM8560 */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* CAN */ -#define CONFIG_SYS_CAN_BASE (CONFIG_SYS_CCSRBAR \ - + 0x03000000) /* CAN base address */ -#ifdef CONFIG_CAN_DRIVER -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */ -#define CONFIG_SYS_OR2_CAN (CONFIG_SYS_CAN_OR_AM | OR_UPM_BI) -#define CONFIG_SYS_BR2_CAN ((CONFIG_SYS_CAN_BASE & BR_BA) | \ - BR_PS_8 | BR_MS_UPMC | BR_V) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x48} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 - -/* I2C RTC */ -#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* I2C EEPROM */ -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also). - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - -#ifndef CONFIG_PCIE1 -/* RapidIO MMU */ -#ifdef CONFIG_TQM_BIGFLASH -#define CONFIG_SYS_RIO_MEM_BASE 0xb0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_SIZE 0x10000000 /* 256M */ -#else /* !CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ -#endif /* CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE -#endif /* CONFIG_PCIE1 */ - -/* NAND FLASH */ -#ifdef CONFIG_NAND - -#define CONFIG_NAND_FSL_UPM 1 - -#define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */ - -/* address distance between chip selects */ -#define CONFIG_SYS_NAND_SELECT_DEVICE 1 -#define CONFIG_SYS_NAND_CS_DIST 0x200 - -#define CONFIG_SYS_NAND_SIZE 0x8000 -#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_CCSRBAR + 0x03010000) - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define CONFIG_SYS_NAND_MAX_CHIPS 2 /* Number of chips per device */ - -/* CS3 for NAND Flash */ -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_NAND_BASE & BR_BA) | \ - BR_PS_8 | BR_MS_UPMB | BR_V) -#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI) - -#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */ - -#endif /* CONFIG_NAND */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BUS (CONFIG_SYS_CCSRBAR + 0x02000000) -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS -#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#ifdef CONFIG_PCIE1 -/* - * General PCI express - * Addresses are mapped 1-1. - */ -#ifdef CONFIG_TQM_BIGFLASH -#define CONFIG_SYS_PCIE1_MEM_BUS 0xb0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BUS 0xaf000000 -#else /* !CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BUS 0xef000000 -#endif /* CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS -#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS -#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ -#endif /* CONFIG_PCIE1 */ - -#if defined(CONFIG_PCI) - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#define CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT -#define FEC_PHY_ADDR 3 -#define FEC_PHYIDX 0 -#define FEC_FLAGS 0 -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 - -#ifdef CONFIG_TQM8548 -/* - * TQM8548 has 4 ethernet ports. 4 ETSEC's. - * - * On the STK85xx Starterkit the ETSEC3/4 ports are on an - * additional adapter (AIO) between module and Starterkit. - */ -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "TSEC2" -#define CONFIG_TSEC4 1 -#define CONFIG_TSEC4_NAME "TSEC3" -#define TSEC3_PHY_ADDR 4 -#define TSEC4_PHY_ADDR 5 -#define TSEC3_PHYIDX 0 -#define TSEC4_PHYIDX 0 -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define CONFIG_HAS_ETH3 -#define CONFIG_HAS_ETH4 -#endif /* CONFIG_TQM8548 */ - -/* Options are TSEC[0-1], FEC */ -#define CONFIG_ETHPRIME "TSEC0" - -#if defined(CONFIG_TQM8540) -/* - * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC. - * The FEC port is connected on the same signals as the FCC3 port - * of the TQM8560 to the baseboard (STK85xx Starterkit). - * - * On the STK85xx Starterkit the X47/X50 jumper has to be set to - * a - d (X50.2 - 3) to enable the FEC port. - */ -#define CONFIG_MPC85XX_FEC 1 -#define CONFIG_MPC85XX_FEC_NAME "FEC" -#endif - -#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) -/* - * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port - * can be used at once, since only one FCC port is available on the STK85xx - * Starterkit. - * - * To use this port you have to configure U-Boot to use the FCC port 1...2 - * and set the X47/X50 jumper to: - * FCC1: a - b (X47.2 - X50.2) - * FCC2: a - c (X50.2 - 1) - */ -#define CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */ -#endif - -#if defined(CONFIG_TQM8560) -/* - * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port - * can be used at once, since only one FCC port is available on the STK85xx - * Starterkit. - * - * To use this port you have to configure U-Boot to use the FCC port 1...3 - * and set the X47/X50 jumper to: - * FCC1: a - b (X47.2 - X50.2) - * FCC2: a - c (X50.2 - 1) - * FCC3: a - d (X50.2 - 3) - */ -#define CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */ -#endif - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) -#define CONFIG_ETHER_ON_FCC1 -#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \ - CMXFCR_TF1CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) -#endif - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) -#define CONFIG_ETHER_ON_FCC2 -#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \ - CMXFCR_TF2CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13) -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) -#endif - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) -#define CONFIG_ETHER_ON_FCC3 -#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \ - CMXFCR_TF3CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) -#endif - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 - -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_TIMESTAMP /* Print image info with ts */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -#ifdef CONFIG_NAND -/* - * Use NAND-FLash as JFFS2 device - */ -#define CONFIG_CMD_NAND -#define CONFIG_CMD_JFFS2 - -#define CONFIG_JFFS2_NAND 1 - -#ifdef CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nand0=TQM85xx-nand" -#define MTDPARTS_DEFAULT "mtdparts=TQM85xx-nand:-" -#else -#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ -#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_SIZE 0x200000 /* size of jffs2 partition */ -#endif /* CONFIG_CMD_MTDPARTS */ - -#endif /* CONFIG_NAND */ - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP -#ifndef CONFIG_TQM8548_AG -#define CONFIG_CMD_DATE -#endif -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_DTT -#define CONFIG_CMD_MII -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buf Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ - -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - - -/* - * Setup some board specific values for the default environment variables - */ -#ifdef CONFIG_CPM2 -#define CONFIG_ENV_CONSDEV "consdev=ttyCPM0\0" -#else -#define CONFIG_ENV_CONSDEV "consdev=ttyS0\0" -#endif -#define CONFIG_ENV_FDT_FILE "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \ - MK_STR(CONFIG_HOSTNAME)".dtb\0" -#define CONFIG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0" -#define CONFIG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \ - "uboot_addr="MK_STR(CONFIG_SYS_TEXT_BASE)"\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_ENV_BOOTFILE \ - CONFIG_ENV_FDT_FILE \ - CONFIG_ENV_CONSDEV \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ - ":$hostname:$netdev:off panic=1\0" \ - "addcons=setenv bootargs $bootargs " \ - "console=$consdev,$baudrate\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm $kernel_addr - $fdt_addr\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \ - "net_nfs=tftp $kernel_addr_r $bootfile;" \ - "tftp $fdt_addr_r $fdt_file;" \ - "run nfsargs addip addcons;" \ - "bootm $kernel_addr_r - $fdt_addr_r\0" \ - "rootpath=/opt/eldk/ppc_85xx\0" \ - "fdt_addr_r=900000\0" \ - "kernel_addr_r=1000000\0" \ - "fdt_addr=ffec0000\0" \ - "kernel_addr=ffd00000\0" \ - "ramdisk_addr=ff800000\0" \ - CONFIG_ENV_UBOOT \ - "load=tftp 100000 $uboot\0" \ - "update=protect off $uboot_addr +$filesize;" \ - "erase $uboot_addr +$filesize;" \ - "cp.b 100000 $uboot_addr $filesize" \ - "upd=run load update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#endif /* __CONFIG_H */ diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index f6a44976fb..1e19ffae0e 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -2,7 +2,7 @@ * (C) Copyright 2003-2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Based on PRO Motion board config file by Andy Joseph, andy@promessdev.com + * Based on Motion-PRO board config file by Robert McCullough, rob@promessinc.com * * See file CREDITS for list of people who contributed to this * project. @@ -100,6 +100,7 @@ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_ETHADDR 00:50:C2:40:10:00 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 @@ -111,21 +112,21 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "hostname=motionpro\0" \ - "netmask=255.255.0.0\0" \ - "ipaddr=192.168.160.22\0" \ - "serverip=192.168.1.1\0" \ - "gatewayip=192.168.1.1\0" \ + "netmask=255.255.255.0\0" \ + "ipaddr=192.168.1.106\0" \ + "serverip=192.168.1.100\0" \ + "gatewayip=192.168.1.100\0" \ "console=ttyPSC0,115200\0" \ "u-boot_addr=400000\0" \ "kernel_addr=400000\0" \ "fdt_addr=700000\0" \ "ramdisk_addr=800000\0" \ "multi_image_addr=800000\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "u-boot=motionpro/u-boot.bin\0" \ - "bootfile=motionpro/uImage\0" \ - "fdt_file=motionpro/motionpro.dtb\0" \ - "ramdisk_file=motionpro/uRamdisk\0" \ + "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ + "u-boot=/tftpboot/motionpro/u-boot.bin\0" \ + "bootfile=/tftpboot/motionpro/uImage\0" \ + "fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \ + "ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \ "multi_image_file=kernel+initrd+dtb.img\0" \ "load=tftp ${u-boot_addr} ${u-boot}\0" \ "update=prot off fff00000 +${filesize};" \ @@ -135,25 +136,32 @@ "ramargs=setenv bootargs root=/dev/ram rw\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ - "fat_args=setenv bootargs rw\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "fat_args=setenv bootargs root=/dev/sda rw\0" \ + "mtdids=nor0=ff000000.flash\0" \ + "mtdparts=ff000000.flash:13m(fs),2m(kernel),384k(uboot)," \ + "128k(env),128k(redund_env)," \ + "128k(dtb),128k(user_data)\0" \ + "addcons=setenv bootargs ${bootargs} console=${console}\0" \ + "addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:" \ "${netmask}:${hostname}:${netdev}:off panic=1 " \ "console=${console}\0" \ "net_nfs=tftp ${kernel_addr} ${bootfile}; " \ - "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip; " \ + "tftp ${fdt_addr} ${fdt_file}; " \ + "run nfsargs addip addmtd; " \ "bootm ${kernel_addr} - ${fdt_addr}\0" \ "net_self=tftp ${kernel_addr} ${bootfile}; " \ "tftp ${fdt_addr} ${fdt_file}; " \ "tftp ${ramdisk_addr} ${ramdisk_file}; " \ - "run ramargs addip; " \ + "nfs ${ramdisk_addr} ${serverip}:${rootpath}/images/uRamdisk; " \ + "run ramargs addip addcons addmtd; " \ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "fat_multi=run fat_args addip; fatload ide 0:1 " \ + "fat_multi=run fat_args addip addmtd; fatload ide 0:1 " \ "${multi_image_addr} ${multi_image_file}; " \ "bootm ${multi_image_addr}\0" \ "" -#define CONFIG_BOOTCOMMAND "run net_nfs" +#define CONFIG_BOOTCOMMAND "run fat_multi" /* * do board-specific init @@ -209,7 +217,7 @@ #define CONFIG_SYS_RAMBOOT 1 #endif -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ #define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* 1 MiB for malloc() */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ @@ -274,7 +282,7 @@ #define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=motionpro-0" #define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \ - "13m(fs),2m(kernel),256k(uboot)," \ + "13m(fs),2m(kernel),384k(uboot)," \ "128k(env),128k(redund_env)," \ "128k(dtb),-(user_data)" diff --git a/include/ext4fs.h b/include/ext4fs.h index b6eedde318..23298fcd7d 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -94,7 +94,7 @@ struct ext_filesystem { /* Superblock */ struct ext2_sblock *sb; /* Block group descritpor table */ - struct ext2_block_group *gd; + struct ext2_block_group *bgd; char *gdtable; /* Block Bitmap Related */ @@ -1161,7 +1161,7 @@ NetReceive(uchar *inpkt, int len) #ifdef CONFIG_NETCONSOLE nc_input_packet((uchar *)ip + IP_UDP_HDR_SIZE, - ntohl(ip->ip_src), + src_ip, ntohs(ip->udp_dst), ntohs(ip->udp_src), ntohs(ip->udp_len) - UDP_HDR_SIZE); |