diff options
| -rw-r--r-- | arch/arm/cpu/armv7/tegra-common/ap20.c | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra-common/clock.c | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/clock.h | 2 | ||||
| -rw-r--r-- | board/nvidia/chromeos/power_management.c | 8 |
4 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/cpu/armv7/tegra-common/ap20.c b/arch/arm/cpu/armv7/tegra-common/ap20.c index 7eae670522..58405d49af 100644 --- a/arch/arm/cpu/armv7/tegra-common/ap20.c +++ b/arch/arm/cpu/armv7/tegra-common/ap20.c @@ -42,7 +42,7 @@ struct clk_pll_table { }; /* ~0=uninitialized/unknown, 0=false, 1=true */ -uint32_t is_tegra2_processor_reset = 0xffffffff; +uint32_t is_tegra_processor_reset = 0xffffffff; /* * Timing tables for each SOC for all four oscillator options. @@ -386,7 +386,7 @@ void tegra_start(void) /* FIXME: should have ap20's L2 disabled too? */ - /* Init is_tegra2_processor_reset */ - is_tegra2_processor_reset = check_is_tegra2_processor_reset(); + /* Init is_tegra_processor_reset */ + is_tegra_processor_reset = check_is_tegra_processor_reset(); } diff --git a/arch/arm/cpu/armv7/tegra-common/clock.c b/arch/arm/cpu/armv7/tegra-common/clock.c index fd5393086f..d14fb5e002 100644 --- a/arch/arm/cpu/armv7/tegra-common/clock.c +++ b/arch/arm/cpu/armv7/tegra-common/clock.c @@ -900,7 +900,7 @@ int clock_verify(void) return 0; } -uint32_t check_is_tegra2_processor_reset(void) +uint32_t check_is_tegra_processor_reset(void) { u32 base_reg; struct clk_pll *pll; diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 832248ed98..72050e77a4 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -349,7 +349,7 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, unsigned clock_get_rate(enum clock_id clkid); /* Return 1=processor reset; 0=not */ -uint32_t check_is_tegra2_processor_reset(void); +uint32_t check_is_tegra_processor_reset(void); /* * Checks that clocks are valid and prints a warning if not diff --git a/board/nvidia/chromeos/power_management.c b/board/nvidia/chromeos/power_management.c index 66edf786d9..63842e2ca0 100644 --- a/board/nvidia/chromeos/power_management.c +++ b/board/nvidia/chromeos/power_management.c @@ -26,15 +26,15 @@ #define TPS6586X_SUPPLYEND 0x13 #define TPS6586X_SUPPLYENE 0x14 -extern uint32_t is_tegra2_processor_reset; +extern uint32_t is_tegra_processor_reset; int is_processor_reset(void) { - if (is_tegra2_processor_reset == ~0U) { - VBDEBUG(PREFIX "error: is_tegra2_processor_reset " + if (is_tegra_processor_reset == ~0U) { + VBDEBUG(PREFIX "error: is_tegra_processor_reset " "uninitialized\n"); } - return is_tegra2_processor_reset ? 1 : 0; + return is_tegra_processor_reset ? 1 : 0; } static int pmic_set_bit(int reg, int bit, int value) |