1167 files changed, 29535 insertions, 73119 deletions

diff --git a/CREDITS b/CREDITS
deleted file mode 100644
index 43d476423dd..00000000000
--- a/CREDITS
+++ /dev/null
@@ -1,536 +0,0 @@
-#
-#   Parts of the development effort for this project have been
-#   sponsored by SIEMENS AG, Austria. Thanks to SIEMENS for
-#   supporting an Open Source project!
-#
-#
-#   This is at least a partial credits-file of individual people that
-#   have contributed to the U-Boot project. It is sorted by name and
-#   formatted to allow easy grepping and beautification by scripts.
-#   The fields are: name (N), email (E), web-address (W), PGP key ID
-#   and fingerprint (P), description (D), and snail-mail address (S).
-#   Thanks,
-#
-#                       Wolfgang Denk
-#----------
-
-N: Dr. Bruno Achauer
-E: bruno@exet-ag.de
-D: Support for NetBSD (both as host and target system)
-
-N: Guillaume Alexandre
-E: guillaume.alexandre@gespac.ch
-D: Add PCIPPC6 configuration
-
-N: Pantelis Antoniou
-E: panto@intracom.gr
-D: NETVIA & NETPHONE board support, ARTOS support.
-D: Support for Silicon Turnkey eXpress XTc
-
-N: Pierre Aubert
-E: <p.aubert@staubli.com>
-D: Support for RPXClassic board
-
-N: Yuli Barcohen
-E: yuli@arabellasw.com
-D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards.
-D: Support for Zephyr Engineering ZPC.1900 board.
-D: Support for Interphase iSPAN boards.
-D: Support for Analogue&Micro Adder boards.
-D: Support for Analogue&Micro Rattler boards.
-W: http://www.arabellasw.com
-
-N: Jerry van Baren
-E: <vanbaren@cideas.com>
-D: BedBug port to 603e core (MPC82xx). Code for enhanced memory test.
-
-N: Pavel Bartusek
-E: <pba@sysgo.com>
-D: Reiserfs support
-W: http://www.elinos.com
-
-N: Andre Beaudin
-E: <andre.beaudin@colubris.com>
-D: PCMCIA, Ethernet, TFTP
-
-N: Jon Benediktsson
-E: jonb@marel.is
-D: Support for Marel V37 board
-
-N: Raphael Bossek
-E: raphael.bossek@solutions4linux.de
-D: 8xxrom-0.3.0
-
-N: Cliff Brake
-E: cliff.brake@gmail.com
-D: Port to Vibren PXA255 IDP platform
-W: http://www.vibren.com
-W: http://bec-systems.com
-
-N: Rick Bronson
-E: rick@efn.org
-D: Atmel AT91RM9200DK and NAND support
-
-N: David Brown
-E: DBrown03@harris.com
-D: Extensions to 8xxrom-0.3.0
-
-N: Oliver Brown
-E: obrown@adventnetworks.com
-D: Port to the gw8260 board
-
-N: Jonathan De Bruyne
-E: jonathan.debruyne@siemens.atea.be
-D: Port to Siemens IAD210 board
-
-N: Ken Chou
-E: kchou@ieee.org
-D: Support for A3000 SBC board
-
-N: Conn Clark
-E: clark@esteem.com
-D: ESTEEM192E support
-
-N: Magnus Damm
-E: damm@opensource.se
-D: 8xxrom
-
-N: Richard Danter
-E: richard.danter@windriver.com
-D: Support for Wind River PPMC 7xx/74xx boards
-
-N: George G. Davis
-E: gdavis@mvista.com
-D: Board ports for ADS GraphicsClient+ and Intel Assabet
-
-N: Arun Dharankar
-E: ADharankar@ATTBI.Com
-D: threads / scheduler example code
-
-N: K?ri Dav??sson
-E: kd@flaga.is
-D: FLAGA DM Support
-
-N: Wolfgang Denk
-E: wd@denx.de
-D: U-Boot initial version, continuing maintenance, ARMBoot merge
-W: http://www.denx.de
-
-N: Dan A. Dickey
-E: ddickey@charter.net
-D: FADS Support
-
-N: Mike Dunn
-E: mikedunn@newsguy.com
-D: Palmtreo680 board, docg4 nand flash driver
-
-N: Dave Ellis
-E: DGE@sixnetio.com
-D: EEPROM Speedup
-
-N: Daniel Engstr?m
-E: daniel@omicron.se
-D: x86 port, Support for sc520_cdp board
-
-N: Hayden Fraser
-E: Hayden.Fraser@freescale.com
-D: Support for ColdFire MCF5253
-W: www.freescale.com
-
-N: Dr. Wolfgang Grandegger
-E: wg@denx.de
-D: Support for Interphase 4539 T1/E1/J1 PMC, CCM, SCM boards
-W: www.denx.de
-
-N: Peter Figuli
-E: peposh@etc.sk
-D: Support for WEP EP250 (PXA) board
-
-N: Thomas Frieden
-E: ThomasF@hyperion-entertainment.com
-D: Support for AmigaOne
-
-N: Paul Gortmaker
-E: paul.gortmaker@windriver.com
-D: Support for WRS SBC8347/8349 boards
-
-N: Frank Gottschling
-E: fgottschling@eltec.de
-D: Support for ELTEC MHPC/ELPPC boards, cfb-console, i8042, SMI LynxEM
-W: www.eltec.de
-
-N: Marius Groeger
-E: mgroeger@sysgo.de
-D: MBX Support, board specific function interface, EST SBC8260 support; initial support for StrongARM (LART), ARM720TDMI (implementa A7)
-W: www.elinos.com
-
-N: Kirk Haderlie
-E: khaderlie@vividimage.com
-D: Added TFTP to 8xxrom (-> 0.3.1)
-
-N: Chris Hallinan
-E: clh@net1plus.com
-D: DHCP Support
-
-N: Anne-Sophie Harnois
-E: Anne-Sophie.Harnois@nextream.fr
-D: Port to Walnut405 board
-
-N: Andreas Heppel
-E: aheppel@sysgo.de
-D: CPU Support for MPC 75x
-
-N: Josh Huber
-E: huber@alum.wpi.edu
-D: Port to the Galileo Evaluation Board, and the MPC74xx cpu series.
-W: http://www.mclx.com/
-
-H: Stuart Hughes
-E: stuarth@lineo.com
-D: Port to MPC8260ADS board
-
-H: Rich Ireland
-E: r.ireland@computer.org
-D: FPGA device configuration driver
-
-H: Mark Jackson
-E: mpfj@mimc.co.uk
-D: Port to MIMC200 board
-
-N: Gary Jennejohn
-E: garyj@jennejohn.org
-D: Support for Samsung ARM920T S3C2400X, ARM920T "TRAB"
-W: www.denx.de
-
-N: Murray Jensen
-E: Murray.Jensen@csiro.au
-D: Initial 8260 support; GDB support
-D: Port to Cogent+Hymod boards; Hymod Board Database
-
-N: Yoo. Jonghoon
-E: yooth@ipone.co.kr
-D: Added port to the RPXlite board
-
-N: Mark Jonas
-E: mark.jonas@freescale.com
-D: Support for Freescale Total5200 platform
-W: http://www.mobilegt.com/
-
-N: Mark Jonas
-E: mark.jonas@de.bosch.com
-D: Support for MPR2 board
-
-N: Sam Song
-E: samsongshu@yahoo.com.cn
-D: Port to the RPXlite_DW board
-
-N: Brad Kemp
-E: Brad.Kemp@seranoa.com
-D: Port to Windriver ppmc8260 board
-
-N: Sangmoon Kim
-E: dogoil@etinsys.com
-D: Support for debris board
-D: Support for KVME080 board
-
-N: Frederick W. Klatt
-E: fred.klatt@windriver.com
-D: Support for Wind River SBC8540/SBC8560 boards
-
-N: Thomas Koeller
-E: tkoeller@gmx.net
-D: Port to Motorola Sandpoint 3 (MPC8240)
-
-N: Raghu Krishnaprasad
-E: Raghu.Krishnaprasad@fci.com
-D: Support for Adder-II MPC852T evaluation board
-W: http://www.forcecomputers.com
-
-N: Sergey Kubushyn
-E: ksi@koi8.net
-D: Support for various TI DaVinci based boards.
-
-N: Bernhard Kuhn
-E: bkuhn@metrowerks.com
-D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards
-
-N: Prakash Kumar
-E: prakash@embedx.com
-D  Support for Intrinsyc CERF PXA250 board.
-
-N: Thomas Lange
-E: thomas@corelatus.se
-D: Support for GTH, GTH2 and dbau1x00 boards; lots of PCMCIA fixes
-
-N: The LEOX team
-E: team@leox.org
-D: Support for LEOX boards, DS164x RTC
-W: http://www.leox.org
-
-N: TsiChung Liew
-E: Tsi-Chung.Liew@freescale.com
-D: Support for ColdFire MCF523x, MCF532x, MCF5445x, MCF547x_8x
-W: www.freescale.com
-
-N: Leif Lindholm
-E: leif.lindholm@i3micro.com
-D: Support for AMD dbau1550 board.
-
-N: Stephan Linz
-E: linz@li-pro.net
-D: Support for Nios Stratix Development Kit (DK-1S10)
-D: Support for SSV ADNP/ESC1 (Nios Cyclone)
-W: http://www.li-pro.net
-
-N: Dave Liu
-E: daveliu@freescale.com
-D: Support for MPC8315, MPC832x, MPC8360, MPC837x
-W: www.freescale.com
-
-N: Raymond Lo
-E: lo@routefree.com
-D: Support for DOS partitions
-
-N: James MacAulay
-E: james.macaulay@amirix.com
-D: Suppport for Amirix AP1000
-W: www.amirix.com
-
-N: Dan Malek
-E: dan@embeddedalley.com
-D: FADSROM, the grandfather of all of this
-D: Support for Silicon Turnkey eXpress XTc
-
-N: Andrea "llandre" Marson
-E: andrea.marson@dave-tech.it
-D: Port to PPChameleonEVB board
-W: www.dave-tech.it
-
-N: Reinhard Meyer
-E: r.meyer@emk-elektronik.de
-D: Port to EMK TOP860 Module
-
-N: Jay Monkman
-E: jtm@smoothsmoothie.com
-D: EST SBC8260 support
-
-N: Frank Morauf
-E: frank.morauf@salzbrenner.com
-D: Support for Embedded Planet RPX Super Board
-
-N: David M?ller
-E: d.mueller@elsoft.ch
-D: Support for Samsung ARM920T SMDK2410 eval board
-
-N: Scott McNutt
-E: smcnutt@psyent.com
-D: Support for Altera Nios-32 CPU
-D: Support for Altera Nios-II CPU
-D: Support for Nios Cyclone Development Kit (DK-1C20)
-W: http://www.psyent.com
-
-N: Rolf Offermanns
-E: rof@sysgo.de
-D: Initial support for SSV-DNP1110, SMC91111 driver
-W: www.elinos.com
-
-N: John Otken
-E: jotken@softadvances.com
-D: Support for AMCC Luan 440SP board
-
-N: Tolunay Orkun
-E: torkun@nextio.com
-D: Support for Cogent CSB272 & CSB472 boards
-
-N: Keith Outwater
-E: keith_outwater@mvis.com
-D: Support for generic/custom MPC860T boards (GEN860T, GEN860T_SC)
-
-N: Frank Panno
-E: fpanno@delphintech.com
-D: Support for Embedded Planet EP8260 Board
-
-N: Denis Peter
-E: d.peter@mpl.ch
-D: Support for 4xx SCSI, floppy, CDROM, CT69000 video, ...
-D: Support for PIP405 board
-D: Support for MIP405 board
-
-N: Dave Peverley
-E: dpeverley@mpc-data.co.uk
-W: http://www.mpc-data.co.uk
-D: OMAP730 P2 board support
-
-N: Bill Pitts
-E: wlp@mindspring.com
-D: BedBug embedded debugger code
-
-N: Daniel Poirot
-E: dan.poirot@windriver.com
-D: Support for the Wind River sbc405, sbc8240 board
-W: http://www.windriver.com
-
-N: Stelian Pop
-E: stelian@popies.net
-D: Atmel AT91CAP9ADK support
-
-N: Ricardo Ribalda Delgado
-E: ricardo.ribalda@uam.es
-D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460, v5fx30teval
-D: Virtex ppc440 generic architecture
-D: Virtex ppc405 generic architecture
-W: http://www.ii.uam.es/~rribalda
-
-N: Stefan Roese
-E: sr@denx.de
-D: AMCC PPC4xx Support
-W: http://www.denx.de
-
-N: Erwin Rol
-E: erwin@muffin.org
-D: boot support for RTEMS
-
-N: Paul Ruhland
-E: pruhland@rochester.rr.com
-D: Port to Logic Zoom LH7A40x SDK board(s)
-
-N: Neil Russell
-E: caret@c-side.com
-D: Author of LiMon-1.4.2, which contributed some ideas
-
-N: Travis B. Sawyer
-E: travis.sawyer@sandburst.com
-D: Support for AMCC PPC440GX, XES XPedite1000 440GX PrPMC board.  AMCC 440gx Ref Platform (Ocotea)
-
-N: Paolo Scaffardi
-E: arsenio@tin.it
-D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more
-
-N: Andre Schwarz
-E: andre.schwarz@matrix-vision.de
-D: Support for Matrix Vision boards (MVBLM7/MVBC_P/MVSMR)
-
-N: Robert Schwebel
-E: r.schwebel@pengutronix.de
-D: Support for csb226 and innokom boards (PXA2xx)
-
-N: Aaron Sells
-E: sellsa@embeddedplanet.com
-D: Support for EP82xxM
-
-N: Art Shipkowski
-E: art@videon-central.com
-D: Support for NetSilicon NS7520
-D: Support for ColdFire MCF5275
-
-N: Jeremy C. Andrus
-E: jeremy@jeremya.com
-D: ColdFire MCF5249 initialization code
-W: jeremya.com
-
-N: Michal Simek
-E: monstr@monstr.eu
-D: Support for Microblaze, ML401, XUPV2P board
-W: www.monstr.eu
-
-N: Yasushi Shoji
-E: yashi@atmark-techno.com
-D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board
-
-N: Kurt Stremerch
-E: kurt@exys.be
-D: Support for Exys XSEngine board
-
-N: Andrea Scian
-E: andrea.scian@dave-tech.it
-D: Port to B2 board
-W: www.dave-tech.it
-
-N: Timur Tabi
-E: timur@freescale.com
-D: Support for MPC8349E-mITX
-W: www.freescale.com
-
-N: Rob Taylor
-E: robt@flyingpig.com
-D: Port to MBX860T and Sandpoint8240
-
-N: Erik Theisen
-E: etheisen@mindspring.com
-D: MBX8xx and many other patches
-
-N: Jim Thompson
-E: jim@musenki.com
-D: Support for MUSENKI board
-
-N: Rune Torgersen
-E: <runet@innovsys.com>
-D: Support for Motorola MPC8266ADS board
-
-N: Greg Ungerer
-E: greg.ungerer@opengear.com
-D: Support for ks8695 CPU, and OpenGear cmXXXX boards
-
-N: David Updegraff
-E: dave@cray.com
-D: Port to Cray L1 board; DHCP vendor extensions
-
-N: Christian Vejlbo
-E: christian.vejlbo@tellabs.com
-D: FADS860T ethernet support
-
-N: Robert Whaley
-E: rwhaley@applieddata.net
-D: Port to ARM PXA27x adsvix SBC
-
-N: Martin Winistoerfer
-E: martinwinistoerfer@gmx.ch
-D: Port to MPC555/556 microcontrollers and support for cmi board
-
-N: David Wu
-E: support@arcturusnetworks.com
-D: Mercury Security EP2500
-W: http://www.arcturusnetworks.com
-
-N: Ming-Len Wu
-E: minglen_wu@techware.com.tw
-D: Motorola MX1ADS board support
-W: http://www.techware.com.tw/
-
-N: Xianghua Xiao
-E: x.xiao@motorola.com
-D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.
-
-N: John Zhan
-E: zhanz@sinovee.com
-D: Support for SinoVee Microsystems SC8xx SBC
-
-N: Alex Zuepke
-E: azu@sysgo.de
-D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
-W: www.elinos.com
-
-N: Nobuhiro Iwamatsu
-E: iwamatsu@nigauri.org
-D: Support for SuperH, MS7750SE01 and  MS7722SE01 boards.
-W: http://www.nigauri.org/~iwamatsu/
-
-N: Alan Lu
-E: alnalu001@gmail.com
-D: Support for Artila M-501 starter kit
-W: http://www.artila.com/
-
-N: Kimmo Leppala
-E: kimmo.leppala@sysart.fi
-D: Support for Artila M-501 starter kit
-W: http://www.sysart.fi/
-
-N: Timo Tuunainen
-E: timo.tuunainen@sysart.fi
-D: Support for Artila M-501 starter kit
-W: http://www.sysart.fi/
-
-N: Philip Balister
-E: philip@opensdr.com
-D: Port to Lyrtech SFFSDR development board.
-W: www.opensdr.com
diff --git a/Kconfig b/Kconfig
index e0c899210e1..f34f341dd72 100644
--- a/Kconfig
+++ b/Kconfig
@@ -70,8 +70,15 @@ config TPL_BUILD
 	depends on $KCONFIG_OBJDIR="tpl"
 	default y
 
+config SUPPORT_SPL
+	bool
+
+config SUPPORT_TPL
+	bool
+
 config SPL
 	bool
+	depends on SUPPORT_SPL
 	prompt "Enable SPL" if !SPL_BUILD
 	default y if SPL_BUILD
 	help
@@ -79,7 +86,7 @@ config SPL
 
 config TPL
 	bool
-	depends on SPL
+	depends on SPL && SUPPORT_TPL
 	prompt "Enable TPL" if !SPL_BUILD
 	default y if TPL_BUILD
 	default n
@@ -100,6 +107,12 @@ config SYS_EXTRA_OPTIONS
 	  configuration to Kconfig. Since this option will be removed sometime,
 	  new boards should not use this option.
 
+config SYS_TEXT_BASE
+	depends on SPARC
+	hex "Text Base"
+	help
+	  TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
+
 endmenu		# Boot images
 
 source "arch/Kconfig"
diff --git a/MAINTAINERS b/MAINTAINERS
index fd346c9fca6..4e2f8a9abb4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -253,7 +253,7 @@ T:	git git://git.denx.de/u-boot-mips.git
 F:	arch/mips/
 
 MMC
-M:	Pantelis Antoniou <panto.antoniou-consulting.com>
+M:	Pantelis Antoniou <panto@antoniou-consulting.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mmc.git
 F:	drivers/mmc/
diff --git a/Makefile b/Makefile
index 99097e1e572..9c8a5801314 100644
--- a/Makefile
+++ b/Makefile
@@ -652,6 +652,10 @@ ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
 libs-y += arch/$(ARCH)/imx-common/
 endif
 
+ifneq (,$(filter $(SOC), armada-xp kirkwood))
+libs-y += arch/$(ARCH)/mvebu-common/
+endif
+
 libs-$(CONFIG_ARM) += arch/arm/cpu/
 libs-$(CONFIG_PPC) += arch/powerpc/cpu/
 
@@ -670,13 +674,9 @@ u-boot-main := $(libs-y)
 
 
 # Add GCC lib
-ifdef CONFIG_USE_PRIVATE_LIBGCC
 ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y)
 PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a
 else
-PLATFORM_LIBGCC = -L $(CONFIG_USE_PRIVATE_LIBGCC) -lgcc
-endif
-else
 PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`) -lgcc
 endif
 PLATFORM_LIBS += $(PLATFORM_LIBGCC)
@@ -754,6 +754,11 @@ endif
 endif
 endif
 
+# Add optional build target if defined in board/cpu/soc headers
+ifneq ($(CONFIG_BUILD_TARGET),)
+ALL-y += $(CONFIG_BUILD_TARGET:"%"=%)
+endif
+
 LDFLAGS_u-boot += $(LDFLAGS_FINAL)
 ifneq ($(CONFIG_SYS_TEXT_BASE),)
 LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
@@ -941,7 +946,8 @@ u-boot-nand.gph: u-boot.bin FORCE
 ifneq ($(CONFIG_SUNXI),)
 OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
 				   --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
-u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin \
+			u-boot$(if $(CONFIG_OF_CONTROL),-dtb,).img FORCE
 	$(call if_changed,pad_cat)
 endif
 
diff --git a/README b/README
index 46def0086b8..7b5538ed3e9 100644
--- a/README
+++ b/README
@@ -544,6 +544,12 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
 		Number of controllers used for other than main memory.
 
+		CONFIG_SYS_FSL_SEC_BE
+		Defines the SEC controller register space as Big Endian
+
+		CONFIG_SYS_FSL_SEC_LE
+		Defines the SEC controller register space as Little Endian
+
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
@@ -617,13 +623,6 @@ The following options need to be configured:
 		exists, unlike the similar options in the Linux kernel. Do not
 		set these options unless they apply!
 
-- CPU timer options:
-		CONFIG_SYS_HZ
-
-		The frequency of the timer returned by get_timer().
-		get_timer() must operate in milliseconds and this CONFIG
-		option must be set to 1000.
-
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
 
@@ -1459,6 +1458,9 @@ The following options need to be configured:
 		CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
 		txfilltuning field in the EHCI controller on reset.
 
+		CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2
+		HW module registers.
+
 - USB Device:
 		Define the below if you wish to use the USB console.
 		Once firmware is rebuilt from a serial console issue the
@@ -2716,6 +2718,14 @@ CBFS (Coreboot Filesystem) support
 		200 ms.
 
 - Configuration Management:
+		CONFIG_BUILD_TARGET
+
+		Some SoCs need special image types (e.g. U-Boot binary
+		with a special header) as build targets. By defining
+		CONFIG_BUILD_TARGET in the SoC / board header, this
+		special image will be automatically built upon calling
+		make / MAKEALL.
+
 		CONFIG_IDENT_STRING
 
 		If defined, this string will be added to the U-Boot
@@ -2824,10 +2834,6 @@ CBFS (Coreboot Filesystem) support
 
 		Enable auto completion of commands using TAB.
 
-		Note that this feature has NOT been implemented yet
-		for the "hush" shell.
-
-
 		CONFIG_SYS_HUSH_PARSER
 
 		Define this variable to enable the "hush" shell (from
@@ -3541,7 +3547,7 @@ FIT uImage format:
 
 		CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
 		CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
-		CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION
+		CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION
 		Address, size and partition on the MMC to load U-Boot from
 		when the MMC is being used in raw mode.
 
@@ -3558,16 +3564,19 @@ FIT uImage format:
 		CONFIG_SPL_FAT_SUPPORT
 		Support for fs/fat/libfat.o in SPL binary
 
-		CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME
-		Filename to read to load U-Boot when reading from FAT
+		CONFIG_SPL_EXT_SUPPORT
+		Support for EXT filesystem in SPL binary
 
-		CONFIG_SPL_FAT_LOAD_KERNEL_NAME
+		CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
+		Filename to read to load U-Boot when reading from filesystem
+
+		CONFIG_SPL_FS_LOAD_KERNEL_NAME
 		Filename to read to load kernel uImage when reading
-		from FAT (for Falcon mode)
+		from filesystem (for Falcon mode)
 
-		CONFIG_SPL_FAT_LOAD_ARGS_NAME
+		CONFIG_SPL_FS_LOAD_ARGS_NAME
 		Filename to read to load kernel argument parameters
-		when reading from FAT (for Falcon mode)
+		when reading from filesystem (for Falcon mode)
 
 		CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
 		Set this for NAND SPL on PPC mpc83xx targets, so that
@@ -4048,6 +4057,11 @@ Configuration Settings:
 	be asserted. See doc/README.omap-reset-time for details on how
 	the value can be calulated on a given board.
 
+- CONFIG_USE_STDINT
+	If stdint.h is available with your toolchain you can define this
+	option to enable it. You can provide option 'USE_STDINT=1' when
+	building U-Boot to enable this.
+
 The following definitions that deal with the placement and management
 of environment data (variable area); in general, we support the
 following configurations:
diff --git a/arch/Kconfig b/arch/Kconfig
index bf2676469c7..f63cc5a7e94 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -7,6 +7,7 @@ config ARC
 
 config ARM
 	bool "ARM architecture"
+	select HAVE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
 
 config AVR32
@@ -24,6 +25,7 @@ config MICROBLAZE
 
 config MIPS
 	bool "MIPS architecture"
+	select HAVE_PRIVATE_LIBGCC
 
 config NDS32
 	bool "NDS32 architecture"
@@ -36,6 +38,7 @@ config OPENRISC
 
 config PPC
 	bool "PowerPC architecture"
+	select HAVE_PRIVATE_LIBGCC
 
 config SANDBOX
 	bool "Sandbox"
@@ -43,12 +46,14 @@ config SANDBOX
 
 config SH
 	bool "SuperH architecture"
+	select HAVE_PRIVATE_LIBGCC
 
 config SPARC
 	bool "SPARC architecture"
 
 config X86
 	bool "x86 architecture"
+	select HAVE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
 
 endchoice
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bef298f1bcb..22eb2d58545 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -7,465 +7,692 @@ config SYS_ARCH
 config ARM64
 	bool
 
+config HAS_VBAR
+        bool
+
+config CPU_ARM720T
+        bool
+
+config CPU_ARM920T
+        bool
+
+config CPU_ARM926EJS
+        bool
+
+config CPU_ARM946ES
+        bool
+
+config CPU_ARM1136
+        bool
+
+config CPU_ARM1176
+        bool
+        select HAS_VBAR
+
+config CPU_V7
+        bool
+        select HAS_VBAR
+
+config CPU_PXA
+        bool
+
+config CPU_SA1100
+        bool
+
+config SYS_CPU
+        default "arm720t" if CPU_ARM720T
+        default "arm920t" if CPU_ARM920T
+        default "arm926ejs" if CPU_ARM926EJS
+        default "arm946es" if CPU_ARM946ES
+        default "arm1136" if CPU_ARM1136
+        default "arm1176" if CPU_ARM1176
+        default "armv7" if CPU_V7
+        default "pxa" if CPU_PXA
+        default "sa1100" if CPU_SA1100
+
 choice
 	prompt "Target select"
 
 config TARGET_INTEGRATORAP_CM720T
 	bool "Support integratorap_cm720t"
+	select CPU_ARM720T
 
 config TARGET_INTEGRATORAP_CM920T
 	bool "Support integratorap_cm920t"
+	select CPU_ARM920T
 
 config TARGET_INTEGRATORCP_CM920T
 	bool "Support integratorcp_cm920t"
+	select CPU_ARM920T
 
 config TARGET_A320EVB
 	bool "Support a320evb"
+	select CPU_ARM920T
 
 config TARGET_AT91RM9200EK
 	bool "Support at91rm9200ek"
+	select CPU_ARM920T
 
 config TARGET_EB_CPUX9K2
 	bool "Support eb_cpux9k2"
+	select CPU_ARM920T
 
 config TARGET_CPUAT91
 	bool "Support cpuat91"
+	select CPU_ARM920T
 
 config TARGET_EDB93XX
 	bool "Support edb93xx"
+	select CPU_ARM920T
 
 config TARGET_SCB9328
 	bool "Support scb9328"
+	select CPU_ARM920T
 
 config TARGET_CM4008
 	bool "Support cm4008"
+	select CPU_ARM920T
 
 config TARGET_CM41XX
 	bool "Support cm41xx"
+	select CPU_ARM920T
 
 config TARGET_VCMA9
 	bool "Support VCMA9"
+	select CPU_ARM920T
 
 config TARGET_SMDK2410
 	bool "Support smdk2410"
+	select CPU_ARM920T
 
 config TARGET_INTEGRATORAP_CM926EJS
 	bool "Support integratorap_cm926ejs"
+	select CPU_ARM926EJS
 
 config TARGET_INTEGRATORCP_CM926EJS
 	bool "Support integratorcp_cm926ejs"
+	select CPU_ARM926EJS
 
 config TARGET_ASPENITE
 	bool "Support aspenite"
+	select CPU_ARM926EJS
 
 config TARGET_GPLUGD
 	bool "Support gplugd"
+	select CPU_ARM926EJS
 
 config TARGET_AFEB9260
 	bool "Support afeb9260"
+	select CPU_ARM926EJS
 
 config TARGET_AT91SAM9260EK
 	bool "Support at91sam9260ek"
+	select CPU_ARM926EJS
 
 config TARGET_AT91SAM9261EK
 	bool "Support at91sam9261ek"
+	select CPU_ARM926EJS
 
 config TARGET_AT91SAM9263EK
 	bool "Support at91sam9263ek"
+	select CPU_ARM926EJS
 
 config TARGET_AT91SAM9M10G45EK
 	bool "Support at91sam9m10g45ek"
+	select CPU_ARM926EJS
 
 config TARGET_AT91SAM9N12EK
 	bool "Support at91sam9n12ek"
+	select CPU_ARM926EJS
 
 config TARGET_AT91SAM9RLEK
 	bool "Support at91sam9rlek"
+	select CPU_ARM926EJS
 
 config TARGET_AT91SAM9X5EK
 	bool "Support at91sam9x5ek"
+	select CPU_ARM926EJS
 
 config TARGET_SNAPPER9260
 	bool "Support snapper9260"
+	select CPU_ARM926EJS
 
 config TARGET_VL_MA2SC
 	bool "Support vl_ma2sc"
+	select CPU_ARM926EJS
 
 config TARGET_SBC35_A9G20
 	bool "Support sbc35_a9g20"
+	select CPU_ARM926EJS
 
 config TARGET_TNY_A9260
 	bool "Support tny_a9260"
+	select CPU_ARM926EJS
 
 config TARGET_USB_A9263
 	bool "Support usb_a9263"
+	select CPU_ARM926EJS
 
 config TARGET_ETHERNUT5
 	bool "Support ethernut5"
-
-config TARGET_TOP9000
-	bool "Support top9000"
+	select CPU_ARM926EJS
 
 config TARGET_MEESC
 	bool "Support meesc"
+	select CPU_ARM926EJS
 
 config TARGET_OTC570
 	bool "Support otc570"
+	select CPU_ARM926EJS
 
 config TARGET_CPU9260
 	bool "Support cpu9260"
+	select CPU_ARM926EJS
 
 config TARGET_PM9261
 	bool "Support pm9261"
+	select CPU_ARM926EJS
 
 config TARGET_PM9263
 	bool "Support pm9263"
+	select CPU_ARM926EJS
 
 config TARGET_PM9G45
 	bool "Support pm9g45"
+	select CPU_ARM926EJS
 
 config TARGET_CORVUS
 	bool "Support corvus"
+	select CPU_ARM926EJS
 
 config TARGET_TAURUS
 	bool "Support taurus"
+	select CPU_ARM926EJS
 
 config TARGET_STAMP9G20
 	bool "Support stamp9g20"
+	select CPU_ARM926EJS
 
 config ARCH_DAVINCI
 	bool "TI DaVinci"
+	select CPU_ARM926EJS
 	help
 	  Support for TI's DaVinci platform.
 
 config KIRKWOOD
 	bool "Marvell Kirkwood"
+	select CPU_ARM926EJS
+
+config TARGET_DB_MV784MP_GP
+	bool "Support db-mv784mp-gp"
+
+config TARGET_MAXBCM
+	bool "Support maxbcm"
 
 config TARGET_DEVKIT3250
 	bool "Support devkit3250"
+	select CPU_ARM926EJS
 
 config TARGET_JADECPU
 	bool "Support jadecpu"
+	select CPU_ARM926EJS
 
 config TARGET_MX25PDK
 	bool "Support mx25pdk"
+	select CPU_ARM926EJS
 
 config TARGET_TX25
 	bool "Support tx25"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config TARGET_ZMX25
 	bool "Support zmx25"
+	select CPU_ARM926EJS
 
 config TARGET_APF27
 	bool "Support apf27"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config TARGET_IMX27LITE
 	bool "Support imx27lite"
+	select CPU_ARM926EJS
 
 config TARGET_MAGNESIUM
 	bool "Support magnesium"
+	select CPU_ARM926EJS
 
 config TARGET_APX4DEVKIT
 	bool "Support apx4devkit"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config TARGET_XFI3
 	bool "Support xfi3"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config TARGET_M28EVK
 	bool "Support m28evk"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config TARGET_MX23EVK
 	bool "Support mx23evk"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config TARGET_MX28EVK
 	bool "Support mx28evk"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config TARGET_MX23_OLINUXINO
 	bool "Support mx23_olinuxino"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config TARGET_BG0900
 	bool "Support bg0900"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config TARGET_SANSA_FUZE_PLUS
 	bool "Support sansa_fuze_plus"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config TARGET_SC_SPS_1
 	bool "Support sc_sps_1"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config ARCH_NOMADIK
 	bool "ST-Ericsson Nomadik"
+	select CPU_ARM926EJS
 
 config ORION5X
 	bool "Marvell Orion"
+	select CPU_ARM926EJS
 
 config TARGET_DKB
 	bool "Support dkb"
+	select CPU_ARM926EJS
 
 config TARGET_SPEAR300
 	bool "Support spear300"
+	select CPU_ARM926EJS
 
 config TARGET_SPEAR310
 	bool "Support spear310"
+	select CPU_ARM926EJS
 
 config TARGET_SPEAR320
 	bool "Support spear320"
+	select CPU_ARM926EJS
 
 config TARGET_SPEAR600
 	bool "Support spear600"
+	select CPU_ARM926EJS
 
 config TARGET_X600
 	bool "Support x600"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config ARCH_VERSATILE
 	bool "ARM Ltd. Versatile family"
+	select CPU_ARM926EJS
 
 config TARGET_INTEGRATORCP_CM1136
 	bool "Support integratorcp_cm1136"
+	select CPU_ARM1136
 
 config TARGET_IMX31_PHYCORE
 	bool "Support imx31_phycore"
+	select CPU_ARM1136
 
 config TARGET_QONG
 	bool "Support qong"
+	select CPU_ARM1136
 
 config TARGET_MX31ADS
 	bool "Support mx31ads"
+	select CPU_ARM1136
 
 config TARGET_MX31PDK
 	bool "Support mx31pdk"
+	select CPU_ARM1136
+	select SUPPORT_SPL
 
 config TARGET_TT01
 	bool "Support tt01"
+	select CPU_ARM1136
 
 config TARGET_IMX31_LITEKIT
 	bool "Support imx31_litekit"
+	select CPU_ARM1136
 
 config TARGET_WOODBURN
 	bool "Support woodburn"
+	select CPU_ARM1136
 
 config TARGET_WOODBURN_SD
 	bool "Support woodburn_sd"
+	select CPU_ARM1136
+	select SUPPORT_SPL
 
 config TARGET_FLEA3
 	bool "Support flea3"
+	select CPU_ARM1136
 
 config TARGET_MX35PDK
 	bool "Support mx35pdk"
+	select CPU_ARM1136
 
 config TARGET_RPI_B
 	bool "Support rpi_b"
+	select CPU_ARM1176
 
 config TARGET_TNETV107X_EVM
 	bool "Support tnetv107x_evm"
+	select CPU_ARM1176
 
 config TARGET_INTEGRATORAP_CM946ES
 	bool "Support integratorap_cm946es"
+	select CPU_ARM946ES
 
 config TARGET_INTEGRATORCP_CM946ES
 	bool "Support integratorcp_cm946es"
+	select CPU_ARM946ES
 
 config TARGET_VEXPRESS_CA15_TC2
 	bool "Support vexpress_ca15_tc2"
+	select CPU_V7
 
 config TARGET_VEXPRESS_CA5X2
 	bool "Support vexpress_ca5x2"
+	select CPU_V7
 
 config TARGET_VEXPRESS_CA9X4
 	bool "Support vexpress_ca9x4"
+	select CPU_V7
 
 config TARGET_KWB
 	bool "Support kwb"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_TSERIES
 	bool "Support tseries"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_CM_T335
 	bool "Support cm_t335"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_PEPPER
 	bool "Support pepper"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_AM335X_IGEP0033
 	bool "Support am335x_igep0033"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_PCM051
 	bool "Support pcm051"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_DRACO
 	bool "Support draco"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_DXR2
 	bool "Support dxr2"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_PXM2
 	bool "Support pxm2"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_RUT
 	bool "Support rut"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_PENGWYN
 	bool "Support pengwyn"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_AM335X_EVM
 	bool "Support am335x_evm"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_AM43XX_EVM
 	bool "Support am43xx_evm"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_TI814X_EVM
 	bool "Support ti814x_evm"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_TI816X_EVM
 	bool "Support ti816x_evm"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_SAMA5D3_XPLAINED
 	bool "Support sama5d3_xplained"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_SAMA5D3XEK
 	bool "Support sama5d3xek"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_BCM28155_AP
 	bool "Support bcm28155_ap"
+	select CPU_V7
 
 config TARGET_BCM958300K
 	bool "Support bcm958300k"
+	select CPU_V7
 
 config TARGET_BCM958622HR
 	bool "Support bcm958622hr"
+	select CPU_V7
 
 config ARCH_EXYNOS
 	bool "Samsung EXYNOS"
+	select CPU_V7
 
 config ARCH_S5PC1XX
 	bool "Samsung S5PC1XX"
+	select CPU_V7
 
 config ARCH_HIGHBANK
 	bool "Calxeda Highbank"
+	select CPU_V7
 
 config ARCH_KEYSTONE
 	bool "TI Keystone"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_M53EVK
 	bool "Support m53evk"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_IMA3_MX53
 	bool "Support ima3-mx53"
+	select CPU_V7
 
 config TARGET_MX51EVK
 	bool "Support mx51evk"
+	select CPU_V7
 
 config TARGET_MX53ARD
 	bool "Support mx53ard"
+	select CPU_V7
 
 config TARGET_MX53EVK
 	bool "Support mx53evk"
+	select CPU_V7
 
 config TARGET_MX53LOCO
 	bool "Support mx53loco"
+	select CPU_V7
 
 config TARGET_MX53SMD
 	bool "Support mx53smd"
+	select CPU_V7
 
 config TARGET_MX51_EFIKAMX
 	bool "Support mx51_efikamx"
+	select CPU_V7
 
 config TARGET_VISION2
 	bool "Support vision2"
+	select CPU_V7
 
 config TARGET_UDOO
 	bool "Support udoo"
+	select CPU_V7
 
 config TARGET_WANDBOARD
 	bool "Support wandboard"
+	select CPU_V7
 
 config TARGET_TITANIUM
 	bool "Support titanium"
+	select CPU_V7
 
 config TARGET_NITROGEN6X
 	bool "Support nitrogen6x"
+	select CPU_V7
 
 config TARGET_CGTQMX6EVAL
 	bool "Support cgtqmx6eval"
+	select CPU_V7
 
 config TARGET_EMBESTMX6BOARDS
 	bool "Support embestmx6boards"
+	select CPU_V7
 
 config TARGET_ARISTAINETOS
 	bool "Support aristainetos"
+	select CPU_V7
 
 config TARGET_MX6QARM2
 	bool "Support mx6qarm2"
+	select CPU_V7
 
 config TARGET_MX6QSABREAUTO
 	bool "Support mx6qsabreauto"
+	select CPU_V7
 
 config TARGET_MX6SABRESD
 	bool "Support mx6sabresd"
+	select CPU_V7
 
 config TARGET_MX6SLEVK
 	bool "Support mx6slevk"
+	select CPU_V7
 
 config TARGET_MX6SXSABRESD
 	bool "Support mx6sxsabresd"
+	select CPU_V7
 
 config TARGET_GW_VENTANA
 	bool "Support gw_ventana"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_HUMMINGBOARD
 	bool "Support hummingboard"
+	select CPU_V7
 
 config TARGET_KOSAGI_NOVENA
 	bool "Support Kosagi Novena"
 
 config TARGET_TQMA6
 	bool "TQ Systems TQMa6 board"
+	select CPU_V7
 
 config TARGET_OT1200
 	bool "Bachmann OT1200"
+	select CPU_V7
 
 config OMAP34XX
 	bool "OMAP34XX SoC"
+	select CPU_V7
 
 config OMAP44XX
 	bool "OMAP44XX SoC"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config OMAP54XX
 	bool "OMAP54XX SoC"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config RMOBILE
 	bool "Renesas ARM SoCs"
+	select CPU_V7
 
 config TARGET_CM_FX6
 	bool "Support cm_fx6"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_SOCFPGA_CYCLONE5
 	bool "Support socfpga_cyclone5"
+	select CPU_V7
+	select SUPPORT_SPL
 
-config TARGET_SUN4I
-	bool "Support sun4i"
-
-config TARGET_SUN5I
-	bool "Support sun5i"
-
-config TARGET_SUN7I
-	bool "Support sun7i"
+config ARCH_SUNXI
+	bool "Support sunxi (Allwinner) SoCs"
 
 config TARGET_SNOWBALL
 	bool "Support snowball"
+	select CPU_V7
 
 config TARGET_U8500_HREF
 	bool "Support u8500_href"
+	select CPU_V7
 
 config TARGET_VF610TWR
 	bool "Support vf610twr"
+	select CPU_V7
 
 config ZYNQ
 	bool "Xilinx Zynq Platform"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TEGRA
 	bool "NVIDIA Tegra"
+	select SUPPORT_SPL
 	select SPL
 	select OF_CONTROL if !SPL_BUILD
+	select CPU_ARM720T if SPL_BUILD
+	select CPU_V7 if !SPL_BUILD
 
 config TARGET_VEXPRESS_AEMV8A
 	bool "Support vexpress_aemv8a"
@@ -481,51 +708,70 @@ config TARGET_LS2085A_SIMU
 
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds_nor"
+	select CPU_V7
 
 config TARGET_LS1021ATWR
 	bool "Support ls1021atwr_nor"
+	select CPU_V7
 
 config TARGET_BALLOON3
 	bool "Support balloon3"
+	select CPU_PXA
 
 config TARGET_H2200
 	bool "Support h2200"
+	select CPU_PXA
 
 config TARGET_PALMLD
 	bool "Support palmld"
+	select CPU_PXA
 
 config TARGET_PALMTC
 	bool "Support palmtc"
+	select CPU_PXA
 
 config TARGET_PALMTREO680
 	bool "Support palmtreo680"
+	select CPU_PXA
+	select SUPPORT_SPL
 
 config TARGET_PXA255_IDP
 	bool "Support pxa255_idp"
+	select CPU_PXA
 
 config TARGET_TRIZEPSIV
 	bool "Support trizepsiv"
+	select CPU_PXA
 
 config TARGET_VPAC270
 	bool "Support vpac270"
+	select CPU_PXA
+	select SUPPORT_SPL
 
 config TARGET_XAENIAX
 	bool "Support xaeniax"
+	select CPU_PXA
 
 config TARGET_ZIPITZ2
 	bool "Support zipitz2"
+	select CPU_PXA
 
 config TARGET_LP8X4X
 	bool "Support lp8x4x"
+	select CPU_PXA
 
 config TARGET_COLIBRI_PXA270
 	bool "Support colibri_pxa270"
+	select CPU_PXA
 
 config TARGET_JORNADA
 	bool "Support jornada"
+	select CPU_SA1100
 
 config ARCH_UNIPHIER
 	bool "Panasonic UniPhier platform"
+	select CPU_V7
+	select SUPPORT_SPL
 
 endchoice
 
@@ -570,6 +816,7 @@ source "board/BuS/eb_cpux9k2/Kconfig"
 source "board/BuS/vl_ma2sc/Kconfig"
 source "board/CarMediaLab/flea3/Kconfig"
 source "board/Marvell/aspenite/Kconfig"
+source "board/Marvell/db-mv784mp-gp/Kconfig"
 source "board/Marvell/dkb/Kconfig"
 source "board/Marvell/gplugd/Kconfig"
 source "board/afeb9260/Kconfig"
@@ -612,7 +859,6 @@ source "board/denx/m28evk/Kconfig"
 source "board/denx/m53evk/Kconfig"
 source "board/egnite/ethernut5/Kconfig"
 source "board/embest/mx6boards/Kconfig"
-source "board/emk/top9000/Kconfig"
 source "board/esd/meesc/Kconfig"
 source "board/esd/otc570/Kconfig"
 source "board/esg/ima3-mx53/Kconfig"
@@ -652,6 +898,7 @@ source "board/karo/tx25/Kconfig"
 source "board/kosagi/novena/Kconfig"
 source "board/logicpd/imx27lite/Kconfig"
 source "board/logicpd/imx31_litekit/Kconfig"
+source "board/maxbcm/Kconfig"
 source "board/mpl/vcma9/Kconfig"
 source "board/olimex/mx23_olinuxino/Kconfig"
 source "board/palmld/Kconfig"
diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
index 8d3f92cae9d..bc98edda7a2 100644
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -531,7 +531,7 @@ u32 spl_boot_mode(void)
 	switch (spl_boot_device()) {
 	case BOOT_DEVICE_MMC1:
 #ifdef CONFIG_SPL_FAT_SUPPORT
-		return MMCSD_MODE_FAT;
+		return MMCSD_MODE_FS;
 #else
 		return MMCSD_MODE_RAW;
 #endif
diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/cpu/arm926ejs/at91/led.c
index 46ed0550239..b8d5c785df4 100644
--- a/arch/arm/cpu/arm926ejs/at91/led.c
+++ b/arch/arm/cpu/arm926ejs/at91/led.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <asm/gpio.h>
 #include <asm/arch/gpio.h>
+#include <status_led.h>
 
 #ifdef CONFIG_RED_LED
 void red_led_on(void)
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index e86c2edd3bb..8d7873c9af3 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -99,7 +99,4 @@ void flush_cache(unsigned long start, unsigned long size)
 /*
  * Stub implementations for l2 cache operations
  */
-void __l2_cache_disable(void) {}
-
-void l2_cache_disable(void)
-	__attribute__((weak, alias("__l2_cache_disable")));
+__weak void l2_cache_disable(void) {}
diff --git a/arch/arm/cpu/arm926ejs/davinci/Kconfig b/arch/arm/cpu/arm926ejs/davinci/Kconfig
index 4c18ab631ef..613f04d8b03 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Kconfig
+++ b/arch/arm/cpu/arm926ejs/davinci/Kconfig
@@ -8,18 +8,22 @@ config TARGET_ENBW_CMC
 
 config TARGET_IPAM390
 	bool "IPAM390 board"
+	select SUPPORT_SPL
 
 config TARGET_DA830EVM
 	bool "DA830 EVM board"
 
 config TARGET_DA850EVM
 	bool "DA850 EVM board"
+	select SUPPORT_SPL
 
 config TARGET_CAM_ENC_4XX
 	bool "CAM ENC 4xx board"
+	select SUPPORT_SPL
 
 config TARGET_HAWKBOARD
 	bool "Hawkboard"
+	select SUPPORT_SPL
 
 config TARGET_DAVINCI_DM355EVM
 	bool "DM355 EVM board"
@@ -53,9 +57,6 @@ config TARGET_CALIMAIN
 
 endchoice
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_SOC
 	default "davinci"
 
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
index 91ffedf732b..6c037a16c90 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
+++ b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
@@ -59,9 +59,6 @@ config TARGET_GOFLEXHOME
 
 endchoice
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_SOC
 	default "kirkwood"
 
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
index c230ce8994e..df4756e4bdb 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile
+++ b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
@@ -7,7 +7,5 @@
 #
 
 obj-y	= cpu.o
-obj-y	+= dram.o
-obj-y	+= mpp.o
-obj-y	+= timer.o
 obj-y	+= cache.o
+obj-y	+= mpp.o
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index 881e2de81b3..9e412bbb04d 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -9,14 +9,11 @@
 #include <common.h>
 #include <netdev.h>
 #include <asm/cache.h>
-#include <u-boot/md5.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <mvebu_mmc.h>
 
-#define BUFLEN	16
-
 void reset_cpu(unsigned long ignored)
 {
 	struct kwcpu_registers *cpureg =
@@ -30,31 +27,6 @@ void reset_cpu(unsigned long ignored)
 }
 
 /*
- * Generates Ramdom hex number reading some time varient system registers
- * and using md5 algorithm
- */
-unsigned char get_random_hex(void)
-{
-	int i;
-	u32 inbuf[BUFLEN];
-	u8 outbuf[BUFLEN];
-
-	/*
-	 * in case of 88F6281/88F6282/88F6192 A0,
-	 * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
-	 * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
-	 * reserved regs and does not have names at this moment
-	 * (no errata available)
-	 */
-	writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
-	for (i = 0; i < BUFLEN; i++) {
-		inbuf[i] = readl(KW_REG_UNDOC_0x1470);
-	}
-	md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
-	return outbuf[outbuf[7] % 0x0f];
-}
-
-/*
  * Window Size
  * Used with the Base register to set the address window size and location.
  * Must be programmed from LSB to MSB as sequence of ones followed by
@@ -140,50 +112,6 @@ int kw_config_adr_windows(void)
 }
 
 /*
- * kw_config_gpio - GPIO configuration
- */
-void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
-{
-	struct kwgpio_registers *gpio0reg =
-		(struct kwgpio_registers *)KW_GPIO0_BASE;
-	struct kwgpio_registers *gpio1reg =
-		(struct kwgpio_registers *)KW_GPIO1_BASE;
-
-	/* Init GPIOS to default values as per board requirement */
-	writel(gpp0_oe_val, &gpio0reg->dout);
-	writel(gpp1_oe_val, &gpio1reg->dout);
-	writel(gpp0_oe, &gpio0reg->oe);
-	writel(gpp1_oe, &gpio1reg->oe);
-}
-
-/*
- * kw_config_mpp - Multi-Purpose Pins Functionality configuration
- *
- * Each MPP can be configured to different functionality through
- * MPP control register, ref (sec 6.1 of kirkwood h/w specification)
- *
- * There are maximum 64 Multi-Pourpose Pins on Kirkwood
- * Each MPP functionality can be configuration by a 4bit value
- * of MPP control reg, the value and associated functionality depends
- * upon used SoC varient
- */
-int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
-		u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
-{
-	u32 *mppreg = (u32 *) KW_MPP_BASE;
-
-	/* program mpp registers */
-	writel(mpp0_7, &mppreg[0]);
-	writel(mpp8_15, &mppreg[1]);
-	writel(mpp16_23, &mppreg[2]);
-	writel(mpp24_31, &mppreg[3]);
-	writel(mpp32_39, &mppreg[4]);
-	writel(mpp40_47, &mppreg[5]);
-	writel(mpp48_55, &mppreg[6]);
-	return 0;
-}
-
-/*
  * SYSRSTn Duration Counter Support
  *
  * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
index 0ba6f098cb6..7222504ed3a 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
@@ -12,7 +12,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 
 static u32 kirkwood_variant(void)
diff --git a/arch/arm/cpu/arm926ejs/nomadik/Kconfig b/arch/arm/cpu/arm926ejs/nomadik/Kconfig
index eda51fdc378..265f3364691 100644
--- a/arch/arm/cpu/arm926ejs/nomadik/Kconfig
+++ b/arch/arm/cpu/arm926ejs/nomadik/Kconfig
@@ -8,9 +8,6 @@ config NOMADIK_NHK8815
 
 endchoice
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_SOC
 	default "nomadik"
 
diff --git a/arch/arm/cpu/arm926ejs/orion5x/Kconfig b/arch/arm/cpu/arm926ejs/orion5x/Kconfig
index 2d0ab2be173..5a542629c75 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/Kconfig
+++ b/arch/arm/cpu/arm926ejs/orion5x/Kconfig
@@ -8,9 +8,6 @@ config TARGET_EDMINIV2
 
 endchoice
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_SOC
 	default "orion5x"
 
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
index 3757ffb2c2f..697e0945d79 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -38,7 +38,7 @@ int arch_cpu_init(void)
 #if defined(CONFIG_DW_UDC)
 	periph1_clken |= MISC_USBDENB;
 #endif
-#if defined(CONFIG_DW_I2C)
+#if defined(CONFIG_SYS_I2C_DW)
 	periph1_clken |= MISC_I2CENB;
 #endif
 #if defined(CONFIG_ST_SMI)
diff --git a/arch/arm/cpu/arm926ejs/versatile/Kconfig b/arch/arm/cpu/arm926ejs/versatile/Kconfig
index 35c16d876ce..d2e76f4afc6 100644
--- a/arch/arm/cpu/arm926ejs/versatile/Kconfig
+++ b/arch/arm/cpu/arm926ejs/versatile/Kconfig
@@ -1,8 +1,5 @@
 if ARCH_VERSATILE
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "versatile"
 
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 828d10bb5a4..29b1d734382 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -9,7 +9,9 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
+#include <ns16550.h>
 #include <spl.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
@@ -36,6 +38,63 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_DM_GPIO
+static const struct omap_gpio_platdata am33xx_gpio[] = {
+	{ 0, AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
+	{ 1, AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ 2, AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ 3, AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
+#ifdef CONFIG_AM43XX
+	{ 4, AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ 5, AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
+#endif
+};
+
+U_BOOT_DEVICES(am33xx_gpios) = {
+	{ "gpio_omap", &am33xx_gpio[0] },
+	{ "gpio_omap", &am33xx_gpio[1] },
+	{ "gpio_omap", &am33xx_gpio[2] },
+	{ "gpio_omap", &am33xx_gpio[3] },
+#ifdef CONFIG_AM43XX
+	{ "gpio_omap", &am33xx_gpio[4] },
+	{ "gpio_omap", &am33xx_gpio[5] },
+#endif
+};
+
+# ifndef CONFIG_OF_CONTROL
+/*
+ * TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove
+ * the CONFIGs. At the same time, we should move this to the board files.
+ */
+static const struct ns16550_platdata am33xx_serial[] = {
+	{ CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK },
+#  ifdef CONFIG_SYS_NS16550_COM2
+	{ CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK },
+#   ifdef CONFIG_SYS_NS16550_COM3
+	{ CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK },
+	{ CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK },
+	{ CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK },
+	{ CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK },
+#   endif
+#  endif
+};
+
+U_BOOT_DEVICES(am33xx_uarts) = {
+	{ "serial_omap", &am33xx_serial[0] },
+#  ifdef CONFIG_SYS_NS16550_COM2
+	{ "serial_omap", &am33xx_serial[1] },
+#   ifdef CONFIG_SYS_NS16550_COM3
+	{ "serial_omap", &am33xx_serial[2] },
+	{ "serial_omap", &am33xx_serial[3] },
+	{ "serial_omap", &am33xx_serial[4] },
+	{ "serial_omap", &am33xx_serial[5] },
+#   endif
+#  endif
+};
+# endif
+
+#else
+
 static const struct gpio_bank gpio_bank_am33xx[] = {
 	{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
 	{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -49,6 +108,8 @@ static const struct gpio_bank gpio_bank_am33xx[] = {
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
 
+#endif
+
 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 int cpu_mmc_init(bd_t *bis)
 {
diff --git a/arch/arm/cpu/armv7/armada-xp/Makefile b/arch/arm/cpu/armv7/armada-xp/Makefile
new file mode 100644
index 00000000000..885dcee2e19
--- /dev/null
+++ b/arch/arm/cpu/armv7/armada-xp/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= cpu.o
diff --git a/arch/arm/cpu/armv7/armada-xp/cpu.c b/arch/arm/cpu/armv7/armada-xp/cpu.c
new file mode 100644
index 00000000000..1cf70a9f5d5
--- /dev/null
+++ b/arch/arm/cpu/armv7/armada-xp/cpu.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#define DDR_BASE_CS_OFF(n)	(0x0000 + ((n) << 3))
+#define DDR_SIZE_CS_OFF(n)	(0x0004 + ((n) << 3))
+
+static struct mbus_win windows[] = {
+	/* PCIE MEM address space */
+	{ DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
+
+	/* PCIE IO address space */
+	{ DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
+
+	/* SPI */
+	{ DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
+	  CPU_ATTR_SPIFLASH },
+
+	/* NOR */
+	{ DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
+	  CPU_ATTR_BOOTROM },
+};
+
+void reset_cpu(unsigned long ignored)
+{
+	struct mvebu_system_registers *reg =
+		(struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
+
+	writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask);
+	writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst);
+	while (1)
+		;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
+	u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
+
+	puts("SoC:   ");
+
+	switch (devid) {
+	case SOC_MV78460_ID:
+		puts("MV78460-");
+		break;
+	default:
+		puts("Unknown-");
+		break;
+	}
+
+	switch (revid) {
+	case 1:
+		puts("A0\n");
+		break;
+	case 2:
+		puts("B0\n");
+		break;
+	default:
+		puts("??\n");
+		break;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+/*
+ * This function initialize Controller DRAM Fastpath windows.
+ * It takes the CS size information from the 0x1500 scratch registers
+ * and sets the correct windows sizes and base addresses accordingly.
+ *
+ * These values are set in the scratch registers by the Marvell
+ * DDR3 training code, which is executed by the BootROM before the
+ * main payload (U-Boot) is executed. This training code is currently
+ * only available in the Marvell U-Boot version. It needs to be
+ * ported to mainline U-Boot SPL at some point.
+ */
+static void update_sdram_window_sizes(void)
+{
+	u64 base = 0;
+	u32 size, temp;
+	int i;
+
+	for (i = 0; i < SDRAM_MAX_CS; i++) {
+		size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
+		if (size != 0) {
+			size |= ~(SDRAM_ADDR_MASK);
+
+			/* Set Base Address */
+			temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
+			writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
+
+			/*
+			 * Check if out of max window size and resize
+			 * the window
+			 */
+			temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
+				~(SDRAM_ADDR_MASK)) | 1;
+			temp |= (size & SDRAM_ADDR_MASK);
+			writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
+
+			base += ((u64)size + 1);
+		} else {
+			/*
+			 * Disable window if not used, otherwise this
+			 * leads to overlapping enabled windows with
+			 * pretty strange results
+			 */
+			clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
+		}
+	}
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+	/* Linux expects the internal registers to be at 0xf1000000 */
+	writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
+
+	/*
+	 * We need to call mvebu_mbus_probe() before calling
+	 * update_sdram_window_sizes() as it disables all previously
+	 * configured mbus windows and then configures them as
+	 * required for U-Boot. Calling update_sdram_window_sizes()
+	 * without this configuration will not work, as the internal
+	 * registers can't be accessed reliably because of potenial
+	 * double mapping.
+	 * After updating the SDRAM access windows we need to call
+	 * mvebu_mbus_probe() again, as this now correctly configures
+	 * the SDRAM areas that are later used by the MVEBU drivers
+	 * (e.g. USB, NETA).
+	 */
+
+	/*
+	 * First disable all windows
+	 */
+	mvebu_mbus_probe(NULL, 0);
+
+	/*
+	 * Now the SDRAM access windows can be reconfigured using
+	 * the information in the SDRAM scratch pad registers
+	 */
+	update_sdram_window_sizes();
+
+	/*
+	 * Finally the mbus windows can be configured with the
+	 * updated SDRAM sizes
+	 */
+	mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
+
+	return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+/*
+ * SOC specific misc init
+ */
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+	/* Nothing yet, perhaps we need something here later */
+	return 0;
+}
+#endif /* CONFIG_ARCH_MISC_INIT */
+
+#ifdef CONFIG_MVNETA
+int cpu_eth_init(bd_t *bis)
+{
+	mvneta_initialize(bis, MVEBU_EGIGA0_BASE, 0, CONFIG_PHY_BASE_ADDR + 0);
+	mvneta_initialize(bis, MVEBU_EGIGA1_BASE, 1, CONFIG_PHY_BASE_ADDR + 1);
+	mvneta_initialize(bis, MVEBU_EGIGA2_BASE, 2, CONFIG_PHY_BASE_ADDR + 2);
+	mvneta_initialize(bis, MVEBU_EGIGA3_BASE, 3, CONFIG_PHY_BASE_ADDR + 3);
+
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig
index 7a0d182e5fb..090be9383fc 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -4,6 +4,7 @@ choice
 	prompt "EXYNOS board select"
 
 config TARGET_SMDKV310
+	select SUPPORT_SPL
 	bool "Exynos4210 SMDKV310 board"
 	select OF_CONTROL if !SPL_BUILD
 
@@ -15,6 +16,7 @@ config TARGET_S5PC210_UNIVERSAL
 
 config TARGET_ORIGEN
 	bool "Exynos4412 Origen board"
+	select SUPPORT_SPL
 
 config TARGET_TRATS2
 	bool "Exynos4412 Trat2 board"
@@ -24,29 +26,31 @@ config TARGET_ODROID
 
 config TARGET_ARNDALE
 	bool "Exynos5250 Arndale board"
+	select SUPPORT_SPL
 	select OF_CONTROL if !SPL_BUILD
 
 config TARGET_SMDK5250
 	bool "SMDK5250 board"
+	select SUPPORT_SPL
 	select OF_CONTROL if !SPL_BUILD
 
 config TARGET_SNOW
 	bool "Snow board"
+	select SUPPORT_SPL
 	select OF_CONTROL if !SPL_BUILD
 
 config TARGET_SMDK5420
 	bool "SMDK5420 board"
+	select SUPPORT_SPL
 	select OF_CONTROL if !SPL_BUILD
 
 config TARGET_PEACH_PIT
 	bool "Peach Pi board"
+	select SUPPORT_SPL
 	select OF_CONTROL if !SPL_BUILD
 
 endchoice
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_SOC
 	default "exynos"
 
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index b929486da9c..3d95dc3339e 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -7,7 +7,7 @@
 
 #include <common.h>
 #include <fdtdec.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/sromc.h>
 
@@ -172,6 +172,9 @@ static int exynos5420_mmc_config(int peripheral, int flags)
 		 * this same assumption.
 		 */
 		if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) {
+#ifndef CONFIG_SPL_BUILD
+			gpio_request(i, "sdmmc0_vdden");
+#endif
 			gpio_set_value(i, 1);
 			gpio_cfg_pin(i, S5P_GPIO_OUTPUT);
 		} else {
diff --git a/arch/arm/cpu/armv7/highbank/Kconfig b/arch/arm/cpu/armv7/highbank/Kconfig
index 29ff99511cd..0e73c041429 100644
--- a/arch/arm/cpu/armv7/highbank/Kconfig
+++ b/arch/arm/cpu/armv7/highbank/Kconfig
@@ -1,8 +1,5 @@
 if ARCH_HIGHBANK
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "highbank"
 
diff --git a/arch/arm/cpu/armv7/keystone/Kconfig b/arch/arm/cpu/armv7/keystone/Kconfig
index 8249b5e2703..134ae87fe1e 100644
--- a/arch/arm/cpu/armv7/keystone/Kconfig
+++ b/arch/arm/cpu/armv7/keystone/Kconfig
@@ -9,10 +9,10 @@ config TARGET_K2HK_EVM
 config TARGET_K2E_EVM
 	bool "TI Keystone 2 Edison EVM"
 
-endchoice
+config TARGET_K2L_EVM
+	bool "TI Keystone 2 Lamar EVM"
 
-config SYS_CPU
-	default "armv7"
+endchoice
 
 config SYS_SOC
 	default "keystone"
diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile
index f8519c04035..ed030db2c88 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -10,10 +10,9 @@ obj-y	+= psc.o
 obj-y	+= clock.o
 obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
 obj-$(CONFIG_SOC_K2E) += clock-k2e.o
+obj-$(CONFIG_SOC_K2L) += clock-k2l.o
 obj-y	+= cmd_clock.o
 obj-y	+= cmd_mon.o
-obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
 obj-y	+= msmc.o
-obj-$(CONFIG_SPL_BUILD)	+= spl.o
-obj-y	+= ddr3.o
+obj-y	+= ddr3.o cmd_ddr3.o
 obj-y	+= keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2l.c b/arch/arm/cpu/armv7/keystone/clock-k2l.c
new file mode 100644
index 00000000000..1c5e4d54d89
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2l.c
@@ -0,0 +1,138 @@
+/*
+ * Keystone2: get clk rate for K2L
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+	[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+	[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+	[TETRIS_PLL] = {KS2_ARMPLLCTL0,  KS2_ARMPLLCTL1},
+	[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+int dev_speeds[] = {
+	SPD800,
+	SPD1000,
+	SPD1200,
+	SPD800,
+	SPD800,
+	SPD800,
+	SPD800,
+	SPD800,
+	SPD1200,
+	SPD1000,
+	SPD800,
+	SPD800,
+	SPD800,
+};
+
+int arm_speeds[] = {
+	SPD800,
+	SPD1000,
+	SPD1200,
+	SPD1350,
+	SPD1400,
+	SPD800,
+	SPD1400,
+	SPD1350,
+	SPD1200,
+	SPD1000,
+	SPD800,
+	SPD800,
+	SPD800,
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll:	pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+	unsigned long mult = 1, prediv = 1, output_div = 2;
+	unsigned long ret;
+	u32 tmp, reg;
+
+	if (pll == CORE_PLL) {
+		ret = external_clk[sys_clk];
+		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+			/* PLL mode */
+			tmp = __raw_readl(KS2_MAINPLLCTL0);
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+				(pllctl_reg_read(pll, mult) &
+				PLLM_MULT_LO_MASK)) + 1;
+			output_div = ((pllctl_reg_read(pll, secctl) >>
+					PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+			ret = ret / prediv / output_div * mult;
+		}
+	} else {
+		switch (pll) {
+		case PASS_PLL:
+			ret = external_clk[pa_clk];
+			reg = KS2_PASSPLLCTL0;
+			break;
+		case TETRIS_PLL:
+			ret = external_clk[tetris_clk];
+			reg = KS2_ARMPLLCTL0;
+			break;
+		case DDR3_PLL:
+			ret = external_clk[ddr3_clk];
+			reg = KS2_DDR3APLLCTL0;
+			break;
+		default:
+			return 0;
+		}
+
+		tmp = __raw_readl(reg);
+		if (!(tmp & PLLCTL_BYPASS)) {
+			/* Bypass disabled */
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+				      PLL_CLKOD_MASK) + 1;
+			ret = ((ret / prediv) * mult) / output_div;
+		}
+	}
+
+	return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+	switch (clk) {
+	case core_pll_clk:      return pll_freq_get(CORE_PLL);
+	case pass_pll_clk:      return pll_freq_get(PASS_PLL);
+	case tetris_pll_clk:    return pll_freq_get(TETRIS_PLL);
+	case ddr3_pll_clk:      return pll_freq_get(DDR3_PLL);
+	case sys_clk0_1_clk:
+	case sys_clk0_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(1);
+	case sys_clk1_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(2);
+	case sys_clk2_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(3);
+	case sys_clk3_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(4);
+	case sys_clk0_2_clk:    return clk_get_rate(sys_clk0_clk) / 2;
+	case sys_clk0_3_clk:    return clk_get_rate(sys_clk0_clk) / 3;
+	case sys_clk0_4_clk:    return clk_get_rate(sys_clk0_clk) / 4;
+	case sys_clk0_6_clk:    return clk_get_rate(sys_clk0_clk) / 6;
+	case sys_clk0_8_clk:    return clk_get_rate(sys_clk0_clk) / 8;
+	case sys_clk0_12_clk:   return clk_get_rate(sys_clk0_clk) / 12;
+	case sys_clk0_24_clk:   return clk_get_rate(sys_clk0_clk) / 24;
+	case sys_clk1_3_clk:    return clk_get_rate(sys_clk1_clk) / 3;
+	case sys_clk1_4_clk:    return clk_get_rate(sys_clk1_clk) / 4;
+	case sys_clk1_6_clk:    return clk_get_rate(sys_clk1_clk) / 6;
+	case sys_clk1_12_clk:   return clk_get_rate(sys_clk1_clk) / 12;
+	default:
+		break;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c
index 47fc89398d4..d13fbc1a4bb 100644
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ b/arch/arm/cpu/armv7/keystone/clock.c
@@ -185,10 +185,6 @@ void init_pll(const struct pll_init_data *data)
 		tmp &= ~(PLL_BWADJ_HI_MASK);
 		tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
 
-		/* set PLL Select (bit 13) for PASS PLL */
-		if (data->pll == PASS_PLL)
-			tmp |= PLLCTL_PAPLL;
-
 		__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
 
 		/* Reset bit: bit 14 for both DDR3 & PASS PLL */
@@ -261,3 +257,16 @@ inline int get_max_arm_speed(void)
 	return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
 }
 #endif
+
+void pass_pll_pa_clk_enable(void)
+{
+	u32 reg;
+
+	reg = readl(keystone_pll_regs[PASS_PLL].reg1);
+
+	reg |= PLLCTL_PAPLL;
+	writel(reg, keystone_pll_regs[PASS_PLL].reg1);
+
+	/* wait till clock is enabled */
+	sdelay(15000);
+}
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c
index d97c95be11d..af1b701e826 100644
--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
@@ -58,20 +58,11 @@ pll_cmd_usage:
 	return cmd_usage(cmdtp);
 }
 
-#ifdef CONFIG_SOC_K2HK
-U_BOOT_CMD(
-	pllset,	5,	0,	do_pll_cmd,
-	"set pll multiplier and pre divider",
-	"<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
-);
-#endif
-#ifdef CONFIG_SOC_K2E
 U_BOOT_CMD(
 	pllset, 5,      0,      do_pll_cmd,
 	"set pll multiplier and pre divider",
-	"<pa|ddr3> <mult> <div> <OD>\n"
+	PLLSET_CMD_LIST " <mult> <div> <OD>\n"
 );
-#endif
 
 int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
@@ -95,12 +86,8 @@ U_BOOT_CMD(
 	getclk,	2,	0,	do_getclk_cmd,
 	"get clock rate",
 	"<clk index>\n"
-#ifdef CONFIG_SOC_K2HK
-	"See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n"
-#endif
-#ifdef CONFIG_SOC_K2E
-	"See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
-#endif
+	"The indexes for clocks:\n"
+	CLOCK_INDEXES_LIST
 );
 
 int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -141,5 +128,8 @@ U_BOOT_CMD(
 	psc,	3,	0,	do_psc_cmd,
 	"<enable/disable psc module os disable domain>",
 	"<mod/domain index> <en|di|domain>\n"
-	"See the hardware.h for Power and Sleep Controller (PSC) Domains\n"
+	"Intended to control Power and Sleep Controller (PSC) domains and\n"
+	"modules. The module or domain index exectly corresponds to ones\n"
+	"listed in official TRM. For instance, to enable MSMC RAM clock\n"
+	"domain use command: psc 14 en.\n"
 );
diff --git a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c b/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
new file mode 100644
index 00000000000..ea78ad8fd53
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
@@ -0,0 +1,248 @@
+/*
+ * Keystone2: DDR3 test commands
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/ddr3.h>
+#include <common.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_MIN_ADDR		CONFIG_SYS_SDRAM_BASE
+
+#define DDR_REMAP_ADDR		0x80000000
+#define ECC_START_ADDR1		((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17)
+
+#define ECC_END_ADDR1		(((gd->start_addr_sp - DDR_REMAP_ADDR - \
+				 CONFIG_STACKSIZE) >> 17) - 2)
+
+#define DDR_TEST_BURST_SIZE	1024
+
+static int ddr_memory_test(u32 start_address, u32 end_address, int quick)
+{
+	u32 index_start, value, index;
+
+	index_start = start_address;
+
+	while (1) {
+		/* Write a pattern */
+		for (index = index_start;
+				index < index_start + DDR_TEST_BURST_SIZE;
+				index += 4)
+			__raw_writel(index, index);
+
+		/* Read and check the pattern */
+		for (index = index_start;
+				index < index_start + DDR_TEST_BURST_SIZE;
+				index += 4) {
+			value = __raw_readl(index);
+			if (value != index) {
+				printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+				       index, value, __raw_readl(index));
+
+				return -1;
+			}
+		}
+
+		index_start += DDR_TEST_BURST_SIZE;
+		if (index_start >= end_address)
+			break;
+
+		if (quick)
+			continue;
+
+		/* Write a pattern for complementary values */
+		for (index = index_start;
+		     index < index_start + DDR_TEST_BURST_SIZE;
+		     index += 4)
+			__raw_writel((u32)~index, index);
+
+		/* Read and check the pattern */
+		for (index = index_start;
+		     index < index_start + DDR_TEST_BURST_SIZE;
+		     index += 4) {
+			value = __raw_readl(index);
+			if (value != ~index) {
+				printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+				       index, value, __raw_readl(index));
+
+				return -1;
+			}
+		}
+
+		index_start += DDR_TEST_BURST_SIZE;
+		if (index_start >= end_address)
+			break;
+
+		/* Write a pattern */
+		for (index = index_start;
+		     index < index_start + DDR_TEST_BURST_SIZE;
+		     index += 2)
+			__raw_writew((u16)index, index);
+
+		/* Read and check the pattern */
+		for (index = index_start;
+		     index < index_start + DDR_TEST_BURST_SIZE;
+		     index += 2) {
+			value = __raw_readw(index);
+			if (value != (u16)index) {
+				printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+				       index, value, __raw_readw(index));
+
+				return -1;
+			}
+		}
+
+		index_start += DDR_TEST_BURST_SIZE;
+		if (index_start >= end_address)
+			break;
+
+		/* Write a pattern */
+		for (index = index_start;
+		     index < index_start + DDR_TEST_BURST_SIZE;
+		     index += 1)
+			__raw_writeb((u8)index, index);
+
+		/* Read and check the pattern */
+		for (index = index_start;
+		     index < index_start + DDR_TEST_BURST_SIZE;
+		     index += 1) {
+			value = __raw_readb(index);
+			if (value != (u8)index) {
+				printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+				       index, value, __raw_readb(index));
+
+				return -1;
+			}
+		}
+
+		index_start += DDR_TEST_BURST_SIZE;
+		if (index_start >= end_address)
+			break;
+	}
+
+	puts("ddr memory test PASSED!\n");
+	return 0;
+}
+
+static int ddr_memory_compare(u32 address1, u32 address2, u32 size)
+{
+	u32 index, value, index2, value2;
+
+	for (index = address1, index2 = address2;
+	     index < address1 + size;
+	     index += 4, index2 += 4) {
+		value = __raw_readl(index);
+		value2 = __raw_readl(index2);
+
+		if (value != value2) {
+			printf("ddr_memory_test: Compare failed at address = 0x%x value = 0x%x, address2 = 0x%x value2 = 0x%x\n",
+			       index, value, index2, value2);
+
+			return -1;
+		}
+	}
+
+	puts("ddr memory compare PASSED!\n");
+	return 0;
+}
+
+static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err)
+{
+	u32 value1, value2, value3;
+
+	puts("Disabling DDR ECC ...\n");
+	ddr3_disable_ecc(base);
+
+	value1 = __raw_readl(address);
+	value2 = value1 ^ ecc_err;
+	__raw_writel(value2, address);
+
+	value3 = __raw_readl(address);
+	printf("ECC err test, addr 0x%x, read data 0x%x, wrote data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
+	       address, value1, value2, ecc_err, value3);
+
+	__raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16),
+		     base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
+
+	puts("Enabling DDR ECC ...\n");
+	ddr3_enable_ecc(base, 1);
+
+	value1 = __raw_readl(address);
+	printf("ECC err test, addr 0x%x, read data 0x%x\n", address, value1);
+
+	ddr3_check_ecc_int(base);
+	return 0;
+}
+
+static int do_ddr_test(cmd_tbl_t *cmdtp,
+		       int flag, int argc, char * const argv[])
+{
+	u32 start_addr, end_addr, size, ecc_err;
+
+	if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) {
+		if (!ddr3_ecc_support_rmw(KS2_DDR3A_EMIF_CTRL_BASE)) {
+			puts("ECC RMW isn't supported for this SOC\n");
+			return 1;
+		}
+
+		start_addr = simple_strtoul(argv[2], NULL, 16);
+		ecc_err = simple_strtoul(argv[3], NULL, 16);
+
+		if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
+		    (start_addr > (CONFIG_SYS_SDRAM_BASE +
+		     CONFIG_MAX_RAM_BANK_SIZE - 1))) {
+			puts("Invalid address!\n");
+			return cmd_usage(cmdtp);
+		}
+
+		ddr_memory_ecc_err(KS2_DDR3A_EMIF_CTRL_BASE,
+				   start_addr, ecc_err);
+		return 0;
+	}
+
+	if (!(((argc == 4) && (strncmp(argv[1], "test", 5) == 0)) ||
+	      ((argc == 5) && (strncmp(argv[1], "compare", 8) == 0))))
+		return cmd_usage(cmdtp);
+
+	start_addr = simple_strtoul(argv[2], NULL, 16);
+	end_addr = simple_strtoul(argv[3], NULL, 16);
+
+	if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
+	    (start_addr > (CONFIG_SYS_SDRAM_BASE +
+	     CONFIG_MAX_RAM_BANK_SIZE - 1)) ||
+	    (end_addr < CONFIG_SYS_SDRAM_BASE) ||
+	    (end_addr > (CONFIG_SYS_SDRAM_BASE +
+	     CONFIG_MAX_RAM_BANK_SIZE - 1)) || (start_addr >= end_addr)) {
+		puts("Invalid start or end address!\n");
+		return cmd_usage(cmdtp);
+	}
+
+	puts("Please wait ...\n");
+	if (argc == 5) {
+		size = simple_strtoul(argv[4], NULL, 16);
+		ddr_memory_compare(start_addr, end_addr, size);
+	} else {
+		ddr_memory_test(start_addr, end_addr, 0);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(ddr,	5, 1, do_ddr_test,
+	   "DDR3 test",
+	   "test <start_addr in hex> <end_addr in hex> - test DDR from start\n"
+	   "	address to end address\n"
+	   "ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n"
+	   "	compare DDR data of (size) bytes from start address to end\n"
+	   "	address\n"
+	   "ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n"
+	   "	in DDR data at <addr>, the command will read a 32-bit data\n"
+	   "	from <addr>, and write (data ^ bit_err) back to <addr>\n"
+);
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c
index 2eabec10f95..923906afb5b 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -9,9 +9,19 @@
 
 #include <asm/io.h>
 #include <common.h>
+#include <asm/arch/msmc.h>
 #include <asm/arch/ddr3.h>
 #include <asm/arch/psc_defs.h>
 
+#include <asm/ti-common/ti-edma3.h>
+
+#define DDR3_EDMA_BLK_SIZE_SHIFT	10
+#define DDR3_EDMA_BLK_SIZE		(1 << DDR3_EDMA_BLK_SIZE_SHIFT)
+#define DDR3_EDMA_BCNT			0x8000
+#define DDR3_EDMA_CCNT			1
+#define DDR3_EDMA_XF_SIZE		(DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT)
+#define DDR3_EDMA_SLOT_NUM		1
+
 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 {
 	unsigned int tmp;
@@ -70,6 +80,240 @@ void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
 	__raw_writel(emif_cfg->sdrfc,  base + KS2_DDR3_SDRFC_OFFSET);
 }
 
+int ddr3_ecc_support_rmw(u32 base)
+{
+	u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET);
+
+	/* Check the DDR3 controller ID reg if the controllers
+	   supports ECC RMW or not */
+	if (value == 0x40461C02)
+		return 1;
+
+	return 0;
+}
+
+static void ddr3_ecc_config(u32 base, u32 value)
+{
+	u32 data;
+
+	__raw_writel(value,  base + KS2_DDR3_ECC_CTRL_OFFSET);
+	udelay(100000); /* delay required to synchronize across clock domains */
+
+	if (value & KS2_DDR3_ECC_EN) {
+		/* Clear the 1-bit error count */
+		data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
+		__raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
+
+		/* enable the ECC interrupt */
+		__raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
+			     KS2_DDR3_WR_ECC_ERR_SYS,
+			     base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET);
+
+		/* Clear the ECC error interrupt status */
+		__raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
+			     KS2_DDR3_WR_ECC_ERR_SYS,
+			     base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
+	}
+}
+
+static void ddr3_reset_data(u32 base, u32 ddr3_size)
+{
+	u32 mpax[2];
+	u32 seg_num;
+	u32 seg, blks, dst, edma_blks;
+	struct edma3_slot_config slot;
+	struct edma3_channel_config edma_channel;
+	u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, };
+
+	/* Setup an edma to copy the 1k block to the entire DDR */
+	puts("\nClear entire DDR3 memory to enable ECC\n");
+
+	/* save the SES MPAX regs */
+	msmc_get_ses_mpax(8, 0, mpax);
+
+	/* setup edma slot 1 configuration */
+	slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
+		   EDMA3_SLOPT_COMP_CODE(0) |
+		   EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
+	slot.bcnt = DDR3_EDMA_BCNT;
+	slot.acnt = DDR3_EDMA_BLK_SIZE;
+	slot.ccnt = DDR3_EDMA_CCNT;
+	slot.src_bidx = 0;
+	slot.dst_bidx = DDR3_EDMA_BLK_SIZE;
+	slot.src_cidx = 0;
+	slot.dst_cidx = 0;
+	slot.link = EDMA3_PARSET_NULL_LINK;
+	slot.bcntrld = 0;
+	edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot);
+
+	/* configure quik edma channel */
+	edma_channel.slot = DDR3_EDMA_SLOT_NUM;
+	edma_channel.chnum = 0;
+	edma_channel.complete_code = 0;
+	/* event trigger after dst update */
+	edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
+	qedma3_start(KS2_EDMA0_BASE, &edma_channel);
+
+	/* DDR3 size in segments (4KB seg size) */
+	seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT);
+
+	for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
+		/* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
+		   access slave interface so that edma driver can access */
+		msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT,
+				     KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G);
+
+		if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
+			edma_blks = KS2_MSMC_MAP_SEG_NUM <<
+					(KS2_MSMC_SEG_SIZE_SHIFT
+					- DDR3_EDMA_BLK_SIZE_SHIFT);
+		else
+			edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT
+					- DDR3_EDMA_BLK_SIZE_SHIFT);
+
+		/* Use edma driver to scrub 2GB DDR memory */
+		for (dst = base, blks = 0; blks < edma_blks;
+		     blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) {
+			edma3_set_src_addr(KS2_EDMA0_BASE,
+					   edma_channel.slot, (u32)edma_src);
+			edma3_set_dest_addr(KS2_EDMA0_BASE,
+					    edma_channel.slot, (u32)dst);
+
+			while (edma3_check_for_transfer(KS2_EDMA0_BASE,
+							&edma_channel))
+				udelay(10);
+		}
+	}
+
+	qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
+
+	/* restore the SES MPAX regs */
+	msmc_set_ses_mpax(8, 0, mpax);
+}
+
+static void ddr3_ecc_init_range(u32 base)
+{
+	u32 ecc_val = KS2_DDR3_ECC_EN;
+	u32 rmw = ddr3_ecc_support_rmw(base);
+
+	if (rmw)
+		ecc_val |= KS2_DDR3_ECC_RMW_EN;
+
+	__raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
+
+	ddr3_ecc_config(base, ecc_val);
+}
+
+void ddr3_enable_ecc(u32 base, int test)
+{
+	u32 ecc_val = KS2_DDR3_ECC_ENABLE;
+	u32 rmw = ddr3_ecc_support_rmw(base);
+
+	if (test)
+		ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN;
+
+	if (!rmw) {
+		if (!test)
+			/* by default, disable ecc when rmw = 0 and no
+			   ecc test */
+			ecc_val = 0;
+	} else {
+		ecc_val |= KS2_DDR3_ECC_RMW_EN;
+	}
+
+	ddr3_ecc_config(base, ecc_val);
+}
+
+void ddr3_disable_ecc(u32 base)
+{
+	ddr3_ecc_config(base, 0);
+}
+
+#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
+static void cic_init(u32 base)
+{
+	/* Disable CIC global interrupts */
+	__raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE);
+
+	/* Set to normal mode, no nesting, no priority hold */
+	__raw_writel(0, base + KS2_CIC_CTRL);
+	__raw_writel(0, base + KS2_CIC_HOST_CTRL);
+
+	/* Enable CIC global interrupts */
+	__raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE);
+}
+
+static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num)
+{
+	/* Map the system interrupt to a CIC channel */
+	__raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num);
+
+	/* Enable CIC system interrupt */
+	__raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET);
+
+	/* Enable CIC Host interrupt */
+	__raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET);
+}
+
+static void ddr3_map_ecc_cic2_irq(u32 base)
+{
+	cic_init(base);
+	cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM,
+			   KS2_CIC2_DDR3_ECC_IRQ_NUM);
+}
+#endif
+
+void ddr3_init_ecc(u32 base)
+{
+	u32 ddr3_size;
+
+	if (!ddr3_ecc_support_rmw(base)) {
+		ddr3_disable_ecc(base);
+		return;
+	}
+
+	ddr3_ecc_init_range(base);
+	ddr3_size = ddr3_get_size();
+	ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
+
+	/* mapping DDR3 ECC system interrupt from CIC2 to GIC */
+#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
+	ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE);
+#endif
+	ddr3_enable_ecc(base, 0);
+}
+
+void ddr3_check_ecc_int(u32 base)
+{
+	char *env;
+	int ecc_test = 0;
+	u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
+
+	env = getenv("ecc_test");
+	if (env)
+		ecc_test = simple_strtol(env, NULL, 0);
+
+	if (value & KS2_DDR3_WR_ECC_ERR_SYS)
+		puts("DDR3 ECC write error interrupted\n");
+
+	if (value & KS2_DDR3_2B_ECC_ERR_SYS) {
+		puts("DDR3 ECC 2-bit error interrupted\n");
+
+		if (!ecc_test) {
+			puts("Reseting the device ...\n");
+			reset_cpu(0);
+		}
+	}
+
+	value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
+	if (value) {
+		printf("1-bit ECC err count: 0x%x\n", value);
+		value = __raw_readl(base +
+				    KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET);
+		printf("1-bit ECC err address log: 0x%x\n", value);
+	}
+}
+
 void ddr3_reset_ddrphy(void)
 {
 	u32 tmp;
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index a8f8aee8ab4..c2b947839d2 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -13,6 +13,7 @@
 #include <asm/arch/msmc.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/psc_defs.h>
 
 void chip_configuration_unlock(void)
 {
@@ -20,17 +21,67 @@ void chip_configuration_unlock(void)
 	__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
 }
 
+#ifdef CONFIG_SOC_K2L
+void osr_init(void)
+{
+	u32 i;
+	u32 j;
+	u32 val;
+	u32 base = KS2_OSR_CFG_BASE;
+	u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
+
+	/* Enable the OSR clock domain */
+	psc_enable_module(KS2_LPSC_OSR);
+
+	/* Disable OSR ECC check for all the ram banks */
+	for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
+		val = i | KS2_OSR_ECC_VEC_TRIG_RD |
+			(KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
+
+		writel(val , base + KS2_OSR_ECC_VEC);
+
+		/**
+		 * wait till read is done.
+		 * Print should be added after earlyprintk support is added.
+		 */
+		for (j = 0; j < 10000; j++) {
+			val = readl(base + KS2_OSR_ECC_VEC);
+			if (val & KS2_OSR_ECC_VEC_RD_DONE)
+				break;
+		}
+
+		ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
+						KS2_OSR_ECC_CTRL_CHK;
+
+		writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
+		writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
+	}
+
+	/* Reset OSR memory to all zeros */
+	for (i = 0; i < KS2_OSR_SIZE; i += 4)
+		writel(0, KS2_OSR_DATA_BASE + i);
+
+	/* Enable OSR ECC check for all the ram banks */
+	for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
+		writel(ecc_ctrl[i] |
+		       KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
+}
+#endif
+
 int arch_cpu_init(void)
 {
 	chip_configuration_unlock();
 	icache_enable();
 
-	msmc_share_all_segments(8);  /* TETRIS */
-	msmc_share_all_segments(9);  /* NETCP */
-	msmc_share_all_segments(10); /* QM PDSP */
-	msmc_share_all_segments(11); /* PCIE 0 */
-#ifdef CONFIG_SOC_K2E
-	msmc_share_all_segments(13); /* PCIE 1 */
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
+#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
+#endif
+#ifdef CONFIG_SOC_K2L
+	osr_init();
 #endif
 
 	/*
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c
index 7d8e5978dfa..7899141d543 100644
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ b/arch/arm/cpu/armv7/keystone/msmc.c
@@ -66,3 +66,29 @@ void msmc_share_all_segments(int priv_id)
 		msmc->ses[priv_id][j].mpaxh &= 0xffffff7ful;
 	}
 }
+
+void msmc_map_ses_segment(int priv_id, int ses_pair,
+			  u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size)
+{
+	struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+	msmc->ses[priv_id][ses_pair].mpaxh = src_pfn << 12 |
+					     (size & 0x1f) | 0x80;
+	msmc->ses[priv_id][ses_pair].mpaxl = dst_pfn << 8 | 0x3f;
+}
+
+void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
+{
+	struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+	*mpax++ = msmc->ses[priv_id][ses_pair].mpaxl;
+	*mpax = msmc->ses[priv_id][ses_pair].mpaxh;
+}
+
+void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
+{
+	struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+	msmc->ses[priv_id][ses_pair].mpaxl = *mpax++;
+	msmc->ses[priv_id][ses_pair].mpaxh = *mpax;
+}
diff --git a/arch/arm/cpu/armv7/keystone/spl.c b/arch/arm/cpu/armv7/keystone/spl.c
deleted file mode 100644
index d4b0e9b163e..00000000000
--- a/arch/arm/cpu/armv7/keystone/spl.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * common spl init code
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-#include <common.h>
-#include <config.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <spl.h>
-#include <spi_flash.h>
-
-#include <asm/u-boot.h>
-#include <asm/utils.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_K2HK_EVM
-static struct pll_init_data spl_pll_config[] = {
-	CORE_PLL_799,
-	TETRIS_PLL_500,
-};
-#endif
-
-#ifdef CONFIG_K2E_EVM
-static struct pll_init_data spl_pll_config[] = {
-	CORE_PLL_800,
-};
-#endif
-
-void spl_init_keystone_plls(void)
-{
-	init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
-}
-
-void spl_board_init(void)
-{
-	spl_init_keystone_plls();
-	preloader_console_init();
-}
-
-u32 spl_boot_device(void)
-{
-#if defined(CONFIG_SPL_SPI_LOAD)
-	return BOOT_DEVICE_SPI;
-#else
-	puts("Unknown boot device\n");
-	hang();
-#endif
-}
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index c0bb431412f..affbf7f702a 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -9,6 +9,7 @@
 
 #include <common.h>
 #include <asm/armv7.h>
+#include <asm/bootm.h>
 #include <asm/pl310.h>
 #include <asm/errno.h>
 #include <asm/io.h>
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 30335647605..fb535eb9ecc 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -81,8 +81,8 @@ u32 spl_boot_mode(void)
 
 	if (val == MMCSD_MODE_RAW)
 		return MMCSD_MODE_RAW;
-	else if (val == MMCSD_MODE_FAT)
-		return MMCSD_MODE_FAT;
+	else if (val == MMCSD_MODE_FS)
+		return MMCSD_MODE_FS;
 	else
 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 		return MMCSD_MODE_EMMCBOOT;
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index 6fae1e5f36e..c215404469f 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -5,57 +5,71 @@ choice
 
 config TARGET_AM3517_EVM
 	bool "AM3517 EVM"
+	select SUPPORT_SPL
 
 config TARGET_MT_VENTOUX
 	bool "TeeJet Mt.Ventoux"
+	select SUPPORT_SPL
 
 config TARGET_OMAP3_SDP3430
 	bool "TI OMAP3430 SDP"
 
 config TARGET_OMAP3_BEAGLE
 	bool "TI OMAP3 BeagleBoard"
+	select SUPPORT_SPL
 
 config TARGET_CM_T35
-	bool "CompuLab CM-T35"
+	bool "CompuLab CM-T3530 and CM-T3730 boards"
+	select SUPPORT_SPL
 
 config TARGET_DEVKIT8000
 	bool "TimLL OMAP3 Devkit8000"
+	select SUPPORT_SPL
 
 config TARGET_OMAP3_EVM
 	bool "TI OMAP3 EVM"
+	select SUPPORT_SPL
 
 config TARGET_OMAP3_EVM_QUICK_MMC
 	bool "TI OMAP3 EVM Quick MMC"
+	select SUPPORT_SPL
 
 config TARGET_OMAP3_EVM_QUICK_NAND
 	bool "TI OMAP3 EVM Quick NAND"
+	select SUPPORT_SPL
 
 config TARGET_OMAP3_IGEP00X0
 	bool "IGEP"
+	select SUPPORT_SPL
 
 config TARGET_OMAP3_OVERO
 	bool "OMAP35xx Gumstix Overo"
+	select SUPPORT_SPL
 
 config TARGET_OMAP3_ZOOM1
 	bool "TI Zoom1"
 
 config TARGET_AM3517_CRANE
 	bool "am3517_crane"
+	select SUPPORT_SPL
 
 config TARGET_OMAP3_PANDORA
 	bool "OMAP3 Pandora"
 
 config TARGET_ECO5PK
 	bool "ECO5PK"
+	select SUPPORT_SPL
 
 config TARGET_DIG297
 	bool "DIG297"
 
 config TARGET_TRICORDER
 	bool "Tricorder"
+	select SUPPORT_SPL
 
 config TARGET_MCX
 	bool "MCX"
+	select SUPPORT_SPL
 
 config TARGET_OMAP3_LOGIC
 	bool "OMAP3 Logic"
@@ -68,15 +82,14 @@ config TARGET_NOKIA_RX51
 
 config TARGET_TAO3530
 	bool "TAO3530"
+	select SUPPORT_SPL
 
 config TARGET_TWISTER
 	bool "Twister"
+	select SUPPORT_SPL
 
 endchoice
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_SOC
 	default "omap3"
 
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 667e77ff05b..53a9e5d77df 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -17,13 +17,15 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <dm.h>
+#include <mmc.h>
 #include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
 #include <asm/cache.h>
 #include <asm/armv7.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 #include <asm/omap_common.h>
 #include <asm/arch/mmc_host_def.h>
 #include <i2c.h>
@@ -38,6 +40,27 @@ static void omap3_setup_aux_cr(void);
 static void omap3_invalidate_l2_cache_secure(void);
 #endif
 
+#ifdef CONFIG_DM_GPIO
+static const struct omap_gpio_platdata omap34xx_gpio[] = {
+	{ 0, OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ 1, OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ 2, OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
+	{ 3, OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ 4, OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
+	{ 5, OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+U_BOOT_DEVICES(am33xx_gpios) = {
+	{ "gpio_omap", &omap34xx_gpio[0] },
+	{ "gpio_omap", &omap34xx_gpio[1] },
+	{ "gpio_omap", &omap34xx_gpio[2] },
+	{ "gpio_omap", &omap34xx_gpio[3] },
+	{ "gpio_omap", &omap34xx_gpio[4] },
+	{ "gpio_omap", &omap34xx_gpio[5] },
+};
+
+#else
+
 static const struct gpio_bank gpio_bank_34xx[6] = {
 	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
 	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
@@ -49,6 +72,8 @@ static const struct gpio_bank gpio_bank_34xx[6] = {
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
 
+#endif
+
 #ifdef CONFIG_SPL_BUILD
 /*
 * We use static variables because global data is not ready yet.
@@ -65,7 +90,7 @@ u32 spl_boot_mode(void)
 	case BOOT_DEVICE_MMC2:
 		return MMCSD_MODE_RAW;
 	case BOOT_DEVICE_MMC1:
-		return MMCSD_MODE_FAT;
+		return MMCSD_MODE_FS;
 		break;
 	default:
 		puts("spl: ERROR:  unknown device - can't select boot mode\n");
@@ -266,7 +291,7 @@ int __weak misc_init_r(void)
  * Routine: wait_for_command_complete
  * Description: Wait for posting to finish on watchdog
  *****************************************************************************/
-void wait_for_command_complete(struct watchdog *wd_base)
+static void wait_for_command_complete(struct watchdog *wd_base)
 {
 	int pending = 1;
 	do {
diff --git a/arch/arm/cpu/armv7/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c
index 6c7330a0cab..a2aadc98169 100644
--- a/arch/arm/cpu/armv7/omap3/emif4.c
+++ b/arch/arm/cpu/armv7/omap3/emif4.c
@@ -61,7 +61,7 @@ u32 get_sdr_cs_offset(u32 cs)
  *  - Init the emif4 module for DDR access
  *  - Early init routines, called from flash or SRAM.
  */
-void do_emif4_init(void)
+static void do_emif4_init(void)
 {
 	unsigned int regval;
 	/* Set the DDR PHY parameters in PHY ctrl registers */
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
index bef5f05eaa7..bbb65bbe726 100644
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ b/arch/arm/cpu/armv7/omap3/sys_info.c
@@ -16,6 +16,8 @@
 #include <asm/io.h>
 #include <asm/arch/mem.h>	/* get mem tables */
 #include <asm/arch/sys_proto.h>
+#include <asm/bootm.h>
+
 #include <i2c.h>
 #include <linux/compiler.h>
 
@@ -202,7 +204,7 @@ u32 __weak get_board_rev(void)
 /********************************************************
  *  get_base(); get upper addr of current execution
  *******************************************************/
-u32 get_base(void)
+static u32 get_base(void)
 {
 	u32 val;
 
diff --git a/arch/arm/cpu/armv7/omap4/Kconfig b/arch/arm/cpu/armv7/omap4/Kconfig
index e2708951357..eccf897258d 100644
--- a/arch/arm/cpu/armv7/omap4/Kconfig
+++ b/arch/arm/cpu/armv7/omap4/Kconfig
@@ -14,9 +14,6 @@ config TARGET_OMAP4_SDP4430
 
 endchoice
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_SOC
 	default "omap4"
 
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig
index 2ccf5b919da..129982cacac 100644
--- a/arch/arm/cpu/armv7/omap5/Kconfig
+++ b/arch/arm/cpu/armv7/omap5/Kconfig
@@ -14,9 +14,6 @@ config TARGET_DRA7XX_EVM
 
 endchoice
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_SOC
 	default "omap5"
 
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig
index 6c2bb22a853..c46a0cc9b8d 100644
--- a/arch/arm/cpu/armv7/rmobile/Kconfig
+++ b/arch/arm/cpu/armv7/rmobile/Kconfig
@@ -20,9 +20,6 @@ config TARGET_ALT
 
 endchoice
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_SOC
 	default "rmobile"
 
diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig
index 2fbbc182039..628813423fe 100644
--- a/arch/arm/cpu/armv7/s5pc1xx/Kconfig
+++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig
@@ -13,9 +13,6 @@ config TARGET_SMDKC100
 
 endchoice
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_SOC
 	default "s5pc1xx"
 
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
index 0eab264668c..8c3e5f7cd42 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -176,7 +176,7 @@ static void socfpga_nic301_slave_ns(void)
 
 static uint32_t iswgrp_handoff[8];
 
-int misc_init_r(void)
+int arch_early_init_r(void)
 {
 	int i;
 	for (i = 0; i < 8; i++)	/* Cache initial SW setting regs */
diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
index db9bdad7d6c..569fa418f46 100644
--- a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
@@ -42,13 +42,4 @@ SECTIONS
 		. = ALIGN(4);
 		__bss_end = .;
 	} >.sdram
-
-	. = ALIGN(8);
-	__malloc_start = .;
-	. = . + CONFIG_SPL_MALLOC_SIZE;
-	__malloc_end = .;
-
-	. = . + CONFIG_SPL_STACK_SIZE;
-	. = ALIGN(8);
-	__stack_start = .;
 }
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index fedd7c8f7e0..fdc05b942f1 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -81,12 +81,6 @@ ENTRY(c_runtime_cpu_setup)
 	mcr     p15, 0, r0, c7, c10, 4	@ DSB
 	mcr     p15, 0, r0, c7, c5, 4	@ ISB
 #endif
-/*
- * Move vector table
- */
-	/* Set vector address in CP15 VBAR register */
-	ldr     r0, =_start
-	mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
 
 	bx	lr
 
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index e9721b27b64..82dbf764e43 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -11,9 +11,13 @@ obj-y	+= timer.o
 obj-y	+= board.o
 obj-y	+= clock.o
 obj-y	+= pinmux.o
-obj-$(CONFIG_SUN4I)	+= clock_sun4i.o
-obj-$(CONFIG_SUN5I)	+= clock_sun4i.o
-obj-$(CONFIG_SUN7I)	+= clock_sun4i.o
+obj-$(CONFIG_MACH_SUN6I)	+= prcm.o
+obj-$(CONFIG_MACH_SUN8I)	+= prcm.o
+obj-$(CONFIG_MACH_SUN4I)	+= clock_sun4i.o
+obj-$(CONFIG_MACH_SUN5I)	+= clock_sun4i.o
+obj-$(CONFIG_MACH_SUN6I)	+= clock_sun6i.o
+obj-$(CONFIG_MACH_SUN7I)	+= clock_sun4i.o
+obj-$(CONFIG_MACH_SUN8I)	+= clock_sun6i.o
 
 ifndef CONFIG_SPL_BUILD
 obj-y	+= cpu_info.o
@@ -23,9 +27,9 @@ endif
 endif
 
 ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_SUN4I)	+= dram.o
-obj-$(CONFIG_SUN5I)	+= dram.o
-obj-$(CONFIG_SUN7I)	+= dram.o
+obj-$(CONFIG_MACH_SUN4I)	+= dram.o
+obj-$(CONFIG_MACH_SUN5I)	+= dram.o
+obj-$(CONFIG_MACH_SUN7I)	+= dram.o
 ifdef CONFIG_SPL_FEL
 obj-y	+= start.o
 endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index f2cedbb1568..6c812fc6e9c 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -50,18 +50,35 @@ u32 spl_boot_mode(void)
 
 int gpio_init(void)
 {
-#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
+#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
+#endif
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
+	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
+#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
-	sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
+	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
-	sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
-#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
+	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
+	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
-	sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
+	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
+	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
 #else
 #error Unsupported console port number. Please fix pin mux settings in board.c
 #endif
@@ -71,6 +88,7 @@ int gpio_init(void)
 
 void reset_cpu(ulong addr)
 {
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
 	static const struct sunxi_wdog *wdog =
 		 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 
@@ -82,12 +100,22 @@ void reset_cpu(ulong addr)
 		/* sun5i sometimes gets stuck without this */
 		writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
 	}
+#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */
+	static const struct sunxi_wdog *wdog =
+		 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
+
+	/* Set the watchdog for its shortest interval (.5s) and wait */
+	writel(WDT_CFG_RESET, &wdog->cfg);
+	writel(WDT_MODE_EN, &wdog->mode);
+	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
+#endif
 }
 
 /* do some early init */
 void s_init(void)
 {
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
+#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
+		defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
 	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
 	asm volatile(
 		"mrc p15, 0, r0, c1, c0, 1\n"
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index ecbdb0162b2..a0e49d179fe 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -35,7 +35,7 @@ void clock_init_safe(void)
 	       APB0_DIV_1 << APB0_DIV_SHIFT |
 	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 	       &ccm->cpu_ahb_apb0_cfg);
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
 #endif
 	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
@@ -180,6 +180,17 @@ void clock_set_pll1(unsigned int hz)
 }
 #endif
 
+unsigned int clock_get_pll5p(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	uint32_t rval = readl(&ccm->pll5_cfg);
+	int n = ((rval & CCM_PLL5_CTRL_N_MASK) >> CCM_PLL5_CTRL_N_SHIFT);
+	int k = ((rval & CCM_PLL5_CTRL_K_MASK) >> CCM_PLL5_CTRL_K_SHIFT) + 1;
+	int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT);
+	return (24000000 * n * k) >> p;
+}
+
 unsigned int clock_get_pll6(void)
 {
 	struct sunxi_ccm_reg *const ccm =
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
new file mode 100644
index 00000000000..1eae9767d0d
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -0,0 +1,76 @@
+/*
+ * sun6i specific clock code
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+void clock_init_uart(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+#if CONFIG_CONS_INDEX < 5
+	/* uart clock source is apb2 */
+	writel(APB2_CLK_SRC_OSC24M|
+	       APB2_CLK_RATE_N_1|
+	       APB2_CLK_RATE_M(1),
+	       &ccm->apb2_div);
+
+	/* open the clock for uart */
+	setbits_le32(&ccm->apb2_gate,
+		     CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
+				       CONFIG_CONS_INDEX - 1));
+
+	/* deassert uart reset */
+	setbits_le32(&ccm->apb2_reset_cfg,
+		     1 << (APB2_RESET_UART_SHIFT +
+			   CONFIG_CONS_INDEX - 1));
+#else
+	/* enable R_PIO and R_UART clocks, and de-assert resets */
+	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
+#endif
+
+	/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
+	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+}
+
+int clock_twi_onoff(int port, int state)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	if (port > 3)
+		return -1;
+
+	/* set the apb clock gate for twi */
+	if (state)
+		setbits_le32(&ccm->apb2_gate,
+			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
+	else
+		clrbits_le32(&ccm->apb2_gate,
+			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
+
+	return 0;
+}
+
+unsigned int clock_get_pll6(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	uint32_t rval = readl(&ccm->pll6_cfg);
+	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
+	int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
+	return 24000000 * n * k / 2;
+}
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index 5cf35acc1e6..41b9add297a 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -13,9 +13,9 @@
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
 {
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
 	puts("CPU:   Allwinner A10 (SUN4I)\n");
-#elif defined CONFIG_SUN5I
+#elif defined CONFIG_MACH_SUN5I
 	u32 val = readl(SUNXI_SID_BASE + 0x08);
 	switch ((val >> 12) & 0xf) {
 	case 0: puts("CPU:   Allwinner A12 (SUN5I)\n"); break;
@@ -23,8 +23,12 @@ int print_cpuinfo(void)
 	case 7: puts("CPU:   Allwinner A10s (SUN5I)\n"); break;
 	default: puts("CPU:   Allwinner A1X (SUN5I)\n");
 	}
-#elif defined CONFIG_SUN7I
+#elif defined CONFIG_MACH_SUN6I
+	puts("CPU:   Allwinner A31 (SUN6I)\n");
+#elif defined CONFIG_MACH_SUN7I
 	puts("CPU:   Allwinner A20 (SUN7I)\n");
+#elif defined CONFIG_MACH_SUN8I
+	puts("CPU:   Allwinner A23 (SUN8I)\n");
 #else
 #warning Please update cpu_info.c with correct CPU information
 	puts("CPU:   SUNXI Family\n");
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 584f7420d7d..dc9fdb930b6 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -74,7 +74,7 @@ static void mctl_ddr3_reset(void)
 	struct sunxi_dram_reg *dram =
 			(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
 	struct sunxi_timer_reg *timer =
 			(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
 	u32 reg_val;
@@ -113,7 +113,7 @@ static void mctl_set_drive(void)
 {
 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
 	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
 #else
 	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
@@ -202,7 +202,7 @@ static void mctl_enable_dllx(u32 phase)
 }
 
 static u32 hpcr_value[32] = {
-#ifdef CONFIG_SUN5I
+#ifdef CONFIG_MACH_SUN5I
 	0, 0, 0, 0,
 	0, 0, 0, 0,
 	0, 0, 0, 0,
@@ -212,7 +212,7 @@ static u32 hpcr_value[32] = {
 	0x0301, 0x0301, 0x0301, 0x0301,
 	0x0301, 0x0301, 0x0301, 0
 #endif
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
 	0x0301, 0x0301, 0x0301, 0x0301,
 	0x0301, 0x0301, 0, 0,
 	0, 0, 0, 0,
@@ -222,7 +222,7 @@ static u32 hpcr_value[32] = {
 	0x1035, 0x1031, 0x0731, 0x1035,
 	0x1031, 0x0301, 0x0301, 0x0731
 #endif
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
 	0x0301, 0x0301, 0x0301, 0x0301,
 	0x0301, 0x0301, 0x0301, 0x0301,
 	0, 0, 0, 0,
@@ -252,15 +252,9 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
 {
 	u32 reg_val;
 	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
-	/* PLL5P and PLL6 are the potential clock sources for MBUS */
-	u32 pll6x_div, pll5p_div;
-	u32 pll6x_clk = clock_get_pll6() / 1000000;
-	u32 pll5p_clk = clk / 24 * 48;
+	u32 pll5p_clk, pll6x_clk;
+	u32 pll5p_div, pll6x_div;
 	u32 pll5p_rate, pll6x_rate;
-#ifdef CONFIG_SUN7I
-	pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
-#endif
 
 	/* setup DRAM PLL */
 	reg_val = readl(&ccm->pll5_cfg);
@@ -268,33 +262,32 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
 	reg_val &= ~CCM_PLL5_CTRL_K_MASK;		/* set K to 0 (x1) */
 	reg_val &= ~CCM_PLL5_CTRL_N_MASK;		/* set N to 0 (x0) */
 	reg_val &= ~CCM_PLL5_CTRL_P_MASK;		/* set P to 0 (x1) */
+#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
+	/* Old kernels are hardcoded to P=1 (divide by 2) */
+	reg_val |= CCM_PLL5_CTRL_P(1);
+#endif
 	if (clk >= 540 && clk < 552) {
-		/* dram = 540MHz, pll5p = 1080MHz */
-		pll5p_clk = 1080;
+		/* dram = 540MHz */
 		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
 		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
 		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
 	} else if (clk >= 512 && clk < 528) {
-		/* dram = 512MHz, pll5p = 1536MHz */
-		pll5p_clk = 1536;
+		/* dram = 512MHz */
 		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
 		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
 		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
 	} else if (clk >= 496 && clk < 504) {
-		/* dram = 496MHz, pll5p = 1488MHz */
-		pll5p_clk = 1488;
+		/* dram = 496MHz */
 		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
 		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
 		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
 	} else if (clk >= 468 && clk < 480) {
-		/* dram = 468MHz, pll5p = 936MHz */
-		pll5p_clk = 936;
+		/* dram = 468MHz */
 		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
 		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
 		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
 	} else if (clk >= 396 && clk < 408) {
-		/* dram = 396MHz, pll5p = 792MHz */
-		pll5p_clk = 792;
+		/* dram = 396MHz */
 		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
 		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
 		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
@@ -311,7 +304,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
 
 	setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
 
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
 	/* reset GPS */
 	clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
 	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
@@ -322,6 +315,13 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
 	/* setup MBUS clock */
 	if (!mbus_clk)
 		mbus_clk = 300;
+
+	/* PLL5P and PLL6 are the potential clock sources for MBUS */
+	pll6x_clk = clock_get_pll6() / 1000000;
+#ifdef CONFIG_MACH_SUN7I
+	pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
+#endif
+	pll5p_clk = clock_get_pll5p() / 1000000;
 	pll6x_div = DIV_ROUND_UP(pll6x_clk, mbus_clk);
 	pll5p_div = DIV_ROUND_UP(pll5p_clk, mbus_clk);
 	pll6x_rate = pll6x_clk / pll6x_div;
@@ -348,7 +348,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
 	 * open DRAMC AHB & DLL register clock
 	 * close it first
 	 */
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
 	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
 #else
 	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
@@ -356,7 +356,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
 	udelay(22);
 
 	/* then open it */
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
 	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
 #else
 	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
@@ -417,7 +417,7 @@ static int dramc_scan_readpipe(void)
 
 static void dramc_clock_output_en(u32 on)
 {
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 
 	if (on)
@@ -425,7 +425,7 @@ static void dramc_clock_output_en(u32 on)
 	else
 		clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
 #endif
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
 	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	if (on)
 		setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
@@ -527,7 +527,7 @@ static void mctl_set_impedance(u32 zq, u32 odt_en)
 	u32 reg_val;
 	u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF;
 
-#ifndef CONFIG_SUN7I
+#ifndef CONFIG_MACH_SUN7I
 	/* Appears that some kind of automatically initiated default
 	 * ZQ calibration is already in progress at this point on sun4i/sun5i
 	 * hardware, but not on sun7i. So it is reasonable to wait for its
@@ -539,7 +539,7 @@ static void mctl_set_impedance(u32 zq, u32 odt_en)
 	if (!odt_en)
 		return;
 
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
 	/* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock
 	 * unless bit 24 is set in SDR_ZQCR1. Not much is known about the
 	 * SDR_ZQCR1 register, but there are hints indicating that it might
@@ -597,7 +597,7 @@ static unsigned long dramc_init_helper(struct dram_para *para)
 	/* dram clock off */
 	dramc_clock_output_en(0);
 
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
 	/* select dram controller 1 */
 	writel(DRAM_CSEL_MAGIC, &dram->csel);
 #endif
@@ -654,7 +654,7 @@ static unsigned long dramc_init_helper(struct dram_para *para)
 	writel(para->tpr2, &dram->tpr2);
 
 	reg_val = DRAM_MR_BURST_LENGTH(0x0);
-#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
+#if (defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I))
 	reg_val |= DRAM_MR_POWER_DOWN;
 #endif
 	reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
@@ -668,7 +668,7 @@ static unsigned long dramc_init_helper(struct dram_para *para)
 	/* disable drift compensation and set passive DQS window mode */
 	clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
 
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
 	/* Command rate timing mode 2T & 1T */
 	if (para->tpr4 & 0x1)
 		setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
@@ -718,7 +718,7 @@ unsigned long dramc_init(struct dram_para *para)
 	/* try to autodetect the DRAM bus width and density */
 	para->io_width  = 16;
 	para->bus_width = 32;
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I)
 	/* only A0-A14 address lines on A10/A13, limiting max density to 4096 */
 	para->density = 4096;
 #else
diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c b/arch/arm/cpu/armv7/sunxi/pinmux.c
index 1f2843fcac4..b026f78ca50 100644
--- a/arch/arm/cpu/armv7/sunxi/pinmux.c
+++ b/arch/arm/cpu/armv7/sunxi/pinmux.c
@@ -10,32 +10,42 @@
 #include <asm/io.h>
 #include <asm/arch/gpio.h>
 
-int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
+void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
 {
-	u32 bank = GPIO_BANK(pin);
-	u32 index = GPIO_CFG_INDEX(pin);
-	u32 offset = GPIO_CFG_OFFSET(pin);
-	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+	u32 index = GPIO_CFG_INDEX(bank_offset);
+	u32 offset = GPIO_CFG_OFFSET(bank_offset);
 
 	clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
-
-	return 0;
 }
 
-int sunxi_gpio_get_cfgpin(u32 pin)
+void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
 {
-	u32 cfg;
 	u32 bank = GPIO_BANK(pin);
-	u32 index = GPIO_CFG_INDEX(pin);
-	u32 offset = GPIO_CFG_OFFSET(pin);
 	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
 
+	sunxi_gpio_set_cfgbank(pio, pin, val);
+}
+
+int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
+{
+	u32 index = GPIO_CFG_INDEX(bank_offset);
+	u32 offset = GPIO_CFG_OFFSET(bank_offset);
+	u32 cfg;
+
 	cfg = readl(&pio->cfg[0] + index);
 	cfg >>= offset;
 
 	return cfg & 0xf;
 }
 
+int sunxi_gpio_get_cfgpin(u32 pin)
+{
+	u32 bank = GPIO_BANK(pin);
+	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+	return sunxi_gpio_get_cfgbank(pio, pin);
+}
+
 int sunxi_gpio_set_drv(u32 pin, u32 val)
 {
 	u32 bank = GPIO_BANK(pin);
diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c
new file mode 100644
index 00000000000..19b4938dc97
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/prcm.c
@@ -0,0 +1,35 @@
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+/* APB0 clock gate and reset bit offsets are the same. */
+void prcm_apb0_enable(u32 flags)
+{
+	struct sunxi_prcm_reg *prcm =
+		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+	/* open the clock for module */
+	setbits_le32(&prcm->apb0_gate, flags);
+
+	/* deassert reset for module */
+	setbits_le32(&prcm->apb0_reset, flags);
+}
diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig
index bcae2d60334..3ea6d7651cb 100644
--- a/arch/arm/cpu/armv7/tegra-common/Kconfig
+++ b/arch/arm/cpu/armv7/tegra-common/Kconfig
@@ -17,6 +17,9 @@ config TEGRA124
 
 endchoice
 
+config USE_PRIVATE_LIBGCC
+	default y if SPL_BUILD
+
 config SYS_CPU
 	default "arm720t" if SPL_BUILD
 	default "armv7" if !SPL_BUILD
diff --git a/arch/arm/cpu/armv7/tegra20/display.c b/arch/arm/cpu/armv7/tegra20/display.c
index fd77f3f0eff..d98cec90180 100644
--- a/arch/arm/cpu/armv7/tegra20/display.c
+++ b/arch/arm/cpu/armv7/tegra20/display.c
@@ -194,7 +194,8 @@ static void rgb_enable(struct dc_com_reg *com)
 		writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
 }
 
-int setup_window(struct disp_ctl_win *win, struct fdt_disp_config *config)
+static int setup_window(struct disp_ctl_win *win,
+			struct fdt_disp_config *config)
 {
 	win->x = 0;
 	win->y = 0;
diff --git a/arch/arm/cpu/armv7/tegra30/Kconfig b/arch/arm/cpu/armv7/tegra30/Kconfig
index 54aec4ed509..3abdc7ba173 100644
--- a/arch/arm/cpu/armv7/tegra30/Kconfig
+++ b/arch/arm/cpu/armv7/tegra30/Kconfig
@@ -3,6 +3,9 @@ if TEGRA30
 choice
 	prompt "Tegra30 board select"
 
+config TARGET_APALIS_T30
+	bool "Toradex Apalis T30 board"
+
 config TARGET_BEAVER
 	bool "NVIDIA Tegra30 Beaver evaluation board"
 
@@ -20,6 +23,7 @@ endchoice
 config SYS_SOC
 	default "tegra30"
 
+source "board/toradex/apalis_t30/Kconfig"
 source "board/nvidia/beaver/Kconfig"
 source "board/nvidia/cardhu/Kconfig"
 source "board/toradex/colibri_t30/Kconfig"
diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig
index 34f5496c8c6..f013dc3cadd 100644
--- a/arch/arm/cpu/armv7/uniphier/Kconfig
+++ b/arch/arm/cpu/armv7/uniphier/Kconfig
@@ -1,16 +1,10 @@
 menu "Panasonic UniPhier platform"
 	depends on ARCH_UNIPHIER
 
-config SYS_CPU
-	string
-	default "armv7"
-
 config SYS_SOC
-	string
 	default "uniphier"
 
 config SYS_CONFIG_NAME
-	string
 	default "ph1_pro4" if MACH_PH1_PRO4
 	default "ph1_ld4" if MACH_PH1_LD4
 	default "ph1_sld8" if MACH_PH1_SLD8
@@ -29,4 +23,13 @@ config MACH_PH1_SLD8
 
 endchoice
 
+config CMD_PINMON
+	bool "Enable boot mode pins monitor command"
+	depends on !SPL_BUILD
+	default y
+	help
+	  The command "pinmon" shows the state of the boot mode pins.
+	  The boot mode pins are latched when the system reset is deasserted
+	  and determine which device the system should load a boot image from.
+
 endmenu
diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile
index 7cedddaadc7..dd57469d9c5 100644
--- a/arch/arm/cpu/armv7/uniphier/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/Makefile
@@ -12,7 +12,7 @@ obj-y += dram_init.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
 obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
 obj-$(CONFIG_UNIPHIER_SMP) += smp.o
-obj-$(if $(CONFIG_SPL_BUILD),,y) += cmd_pinmon.o
+obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
 
 obj-y += board_common.o
 obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
index b385e195447..781b511a97b 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+obj-y += platdevice.o
 obj-y += boot-mode.o
 obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
 		sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
new file mode 100644
index 00000000000..0047223181a
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/platdevice.h>
+
+#define UART_MASTER_CLK		36864000
+
+SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
+SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
+SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
+SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
index 712afd1beeb..e11f4f6d8b3 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+obj-y += platdevice.o
 obj-y += boot-mode.o
 obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \
 				sg_init.o pll_init.o clkrst_init.o pinctrl.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
new file mode 100644
index 00000000000..6da921e9204
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/platdevice.h>
+
+#define UART_MASTER_CLK		73728000
+
+SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
+SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
+SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
+SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
index b385e195447..781b511a97b 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+obj-y += platdevice.o
 obj-y += boot-mode.o
 obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
 		sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
new file mode 100644
index 00000000000..59d054a3102
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/platdevice.h>
+
+#define UART_MASTER_CLK		80000000
+
+SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
+SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
+SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
+SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
diff --git a/arch/arm/cpu/armv7/zynq/Kconfig b/arch/arm/cpu/armv7/zynq/Kconfig
index d6655a972bb..f418cd6d99e 100644
--- a/arch/arm/cpu/armv7/zynq/Kconfig
+++ b/arch/arm/cpu/armv7/zynq/Kconfig
@@ -17,9 +17,6 @@ config TARGET_ZYNQ_ZC770
 
 endchoice
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "zynq"
 
diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c
index 9ff2ef2ae36..31627f970ef 100644
--- a/arch/arm/cpu/armv7/zynq/spl.c
+++ b/arch/arm/cpu/armv7/zynq/spl.c
@@ -63,7 +63,7 @@ u32 spl_boot_device(void)
 #ifdef CONFIG_SPL_MMC_SUPPORT
 u32 spl_boot_mode(void)
 {
-	return MMCSD_MODE_FAT;
+	return MMCSD_MODE_FS;
 }
 #endif
 
diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c
index cbb5a529da2..674a47061e7 100644
--- a/arch/arm/cpu/at91-common/spl.c
+++ b/arch/arm/cpu/at91-common/spl.c
@@ -102,7 +102,7 @@ u32 spl_boot_mode(void)
 	switch (spl_boot_device()) {
 #ifdef CONFIG_SYS_USE_MMC
 	case BOOT_DEVICE_MMC1:
-		return MMCSD_MODE_FAT;
+		return MMCSD_MODE_FS;
 		break;
 #endif
 	case BOOT_DEVICE_NONE:
diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c
index 433da09d10c..b6a84a57747 100644
--- a/arch/arm/cpu/tegra-common/board.c
+++ b/arch/arm/cpu/tegra-common/board.c
@@ -9,6 +9,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
+#include <asm/arch/mc.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch-tegra/pmc.h>
@@ -27,55 +28,6 @@ enum {
 	UART_COUNT = 5,
 };
 
-#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
-	defined(CONFIG_TEGRA114)
-/*
- * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
- * so we are using this value to identify memory size.
- */
-unsigned int query_sdram_size(void)
-{
-	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 reg;
-
-	reg = readl(&pmc->pmc_scratch20);
-	debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
-
-#if defined(CONFIG_TEGRA20)
-	/* bits 30:28 in OdmData are used for RAM size on T20  */
-	reg &= 0x70000000;
-
-	switch ((reg) >> 28) {
-	case 1:
-		return 0x10000000;	/* 256 MB */
-	case 0:
-	case 2:
-	default:
-		return 0x20000000;	/* 512 MB */
-	case 3:
-		return 0x40000000;	/* 1GB */
-	}
-#else	/* Tegra30/Tegra114 */
-	/* bits 31:28 in OdmData are used for RAM size on T30  */
-	switch ((reg) >> 28) {
-	case 0:
-	case 1:
-	default:
-		return 0x10000000;	/* 256 MB */
-	case 2:
-		return 0x20000000;	/* 512 MB */
-	case 3:
-		return 0x30000000;	/* 768 MB */
-	case 4:
-		return 0x40000000;	/* 1GB */
-	case 8:
-		return 0x7ff00000;	/* 2GB - 1MB */
-	}
-#endif
-}
-#else
-#include <asm/arch/mc.h>
-
 /* Read the RAM size directly from the memory controller */
 unsigned int query_sdram_size(void)
 {
@@ -83,12 +35,22 @@ unsigned int query_sdram_size(void)
 	u32 size_mb;
 
 	size_mb = readl(&mc->mc_emem_cfg);
+#if defined(CONFIG_TEGRA20)
+	debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", size_mb);
+	size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024);
+#else
 	debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb);
+	size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024 * 1024);
+#endif
 
-	return size_mb * 1024 * 1024;
-}
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
+	/* External memory limited to 2047 MB due to IROM/HI-VEC */
+	if (size_mb == SZ_2G) size_mb -= SZ_1M;
 #endif
 
+	return size_mb;
+}
+
 int dram_init(void)
 {
 	/* We do not initialise DRAM here. We just query the size */
diff --git a/arch/arm/cpu/tegra-common/sys_info.c b/arch/arm/cpu/tegra-common/sys_info.c
index de20325ecf3..5933c35ddd4 100644
--- a/arch/arm/cpu/tegra-common/sys_info.c
+++ b/arch/arm/cpu/tegra-common/sys_info.c
@@ -8,7 +8,7 @@
 #include <common.h>
 #include <linux/ctype.h>
 
-void upstring(char *s)
+static void upstring(char *s)
 {
 	while (*s) {
 		*s = toupper(*s);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c37580ed842..52f89268940 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_MACH_SUN7I) +=  sun7i-a20-pcduino3.dtb
 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
@@ -22,6 +23,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra20-ventana.dtb \
 	tegra20-whistler.dtb \
 	tegra20-colibri_t20_iris.dtb \
+	tegra30-apalis.dtb \
 	tegra30-beaver.dtb \
 	tegra30-cardhu.dtb \
 	tegra30-colibri.dtb \
diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi
index 2f66deda9f5..e70b4d1f1fa 100644
--- a/arch/arm/dts/am335x-bone-common.dtsi
+++ b/arch/arm/dts/am335x-bone-common.dtsi
@@ -10,6 +10,10 @@
 	model = "TI AM335x BeagleBone";
 	compatible = "ti,am335x-bone", "ti,am33xx";
 
+	chosen {
+		stdout-path = &uart0;
+	};
+
 	cpus {
 		cpu@0 {
 			cpu0-supply = <&dcdc2_reg>;
diff --git a/arch/arm/dts/dt-bindings/gpio/gpio.h b/arch/arm/dts/dt-bindings/gpio/gpio.h
deleted file mode 100644
index e6b1e0a808a..00000000000
--- a/arch/arm/dts/dt-bindings/gpio/gpio.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This header provides constants for most GPIO bindings.
- *
- * Most GPIO bindings include a flags cell as part of the GPIO specifier.
- * In most cases, the format of the flags cell uses the standard values
- * defined in this header.
- */
-
-#ifndef _DT_BINDINGS_GPIO_GPIO_H
-#define _DT_BINDINGS_GPIO_GPIO_H
-
-#define GPIO_ACTIVE_HIGH 0
-#define GPIO_ACTIVE_LOW 1
-
-#endif
diff --git a/arch/arm/dts/exynos4.dtsi b/arch/arm/dts/exynos4.dtsi
index 110eb43a2f8..77fad48fb4b 100644
--- a/arch/arm/dts/exynos4.dtsi
+++ b/arch/arm/dts/exynos4.dtsi
@@ -7,9 +7,16 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
+	combiner: interrupt-controller@10440000 {
+		compatible = "samsung,exynos4210-combiner";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		reg = <0x10440000 0x1000>;
+	};
+
 	serial@13800000 {
 		compatible = "samsung,exynos4210-uart";
 		reg = <0x13800000 0x3c>;
diff --git a/arch/arm/dts/exynos4210-origen.dts b/arch/arm/dts/exynos4210-origen.dts
index 15059d22022..dd2476c1a39 100644
--- a/arch/arm/dts/exynos4210-origen.dts
+++ b/arch/arm/dts/exynos4210-origen.dts
@@ -8,8 +8,8 @@
  */
 
 /dts-v1/;
-/include/ "skeleton.dtsi"
-/include/ "exynos4.dtsi"
+#include "skeleton.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Insignal Origen evaluation board based on Exynos4210";
diff --git a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
new file mode 100644
index 00000000000..f9b61ba8e8f
--- /dev/null
+++ b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
@@ -0,0 +1,27 @@
+/*
+ * U-Boot additions to enable a generic Exynos GPIO driver
+ *
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/{
+	pinctrl_0: pinctrl@11400000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos4210-pinctrl";
+	};
+
+	pinctrl_1: pinctrl@11000000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpx0: gpx0 {
+			reg = <0xc00>;
+		};
+	};
+
+	pinctrl_2: pinctrl@03860000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+};
diff --git a/arch/arm/dts/exynos4210-pinctrl.dtsi b/arch/arm/dts/exynos4210-pinctrl.dtsi
new file mode 100644
index 00000000000..bda17f79f47
--- /dev/null
+++ b/arch/arm/dts/exynos4210-pinctrl.dtsi
@@ -0,0 +1,304 @@
+/*
+ * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2011-2012 Linaro Ltd.
+ *		www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+	pinctrl@11400000 {
+		gpa0: gpa0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpa1: gpa1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb: gpb {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc0: gpc0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc1: gpc1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpd0: gpd0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpd1: gpd1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpe0: gpe0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpe1: gpe1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpe2: gpe2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpe3: gpe3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpe4: gpe4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpf0: gpf0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpf1: gpf1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpf2: gpf2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpf3: gpf3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+	};
+
+	pinctrl@11000000 {
+		gpj0: gpj0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpj1: gpj1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpk0: gpk0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpk1: gpk1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpk2: gpk2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpk3: gpk3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpl0: gpl0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpl1: gpl1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpl2: gpl2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpy0: gpy0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy1: gpy1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy2: gpy2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy3: gpy3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy4: gpy4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy5: gpy5 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy6: gpy6 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpx0: gpx0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			interrupt-parent = <&gic>;
+			interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+				     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
+			#interrupt-cells = <2>;
+		};
+
+		gpx1: gpx1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			interrupt-parent = <&gic>;
+			interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+				     <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+			#interrupt-cells = <2>;
+		};
+
+		gpx2: gpx2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpx3: gpx3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+	};
+
+	pinctrl@03860000 {
+		gpz: gpz {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+	};
+};
diff --git a/arch/arm/dts/exynos4210-smdkv310.dts b/arch/arm/dts/exynos4210-smdkv310.dts
index c390c8f0c8a..00cad0447d8 100644
--- a/arch/arm/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/dts/exynos4210-smdkv310.dts
@@ -7,7 +7,7 @@
  */
 
 /dts-v1/;
-/include/ "exynos4.dtsi"
+#include "exynos4.dtsi"
 
 / {
 	model = "Samsung SMDKV310 on Exynos4210";
diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts
index 0ff69393b75..8c7a2c3a787 100644
--- a/arch/arm/dts/exynos4210-trats.dts
+++ b/arch/arm/dts/exynos4210-trats.dts
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "exynos4.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Samsung Trats based on Exynos4210";
@@ -101,7 +101,7 @@
 	sdhci@12510000 {
 		samsung,bus-width = <8>;
 		samsung,timing = <1 3 3>;
-		pwr-gpios = <&gpio 0xA2 0>;
+		pwr-gpios = <&gpio 146 0>;
 	};
 
 	sdhci@12520000 {
@@ -111,7 +111,7 @@
 	sdhci@12530000 {
 		samsung,bus-width = <4>;
 		samsung,timing = <1 2 3>;
-		cd-gpios = <&gpio 0x39C 0>;
+		cd-gpios = <&gpio 284 0>;
 	};
 
 	sdhci@12540000 {
diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts
index 6941906aaa3..808c3f7cc3a 100644
--- a/arch/arm/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/dts/exynos4210-universal_c210.dts
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "exynos4.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Samsung Universal C210 based on Exynos4210 rev0";
@@ -24,7 +24,7 @@
 	sdhci@12510000 {
 		samsung,bus-width = <8>;
 		samsung,timing = <1 3 3>;
-		pwr-gpios = <&gpio 0xA2 0>;
+		pwr-gpios = <&gpio 146 0>;
 	};
 
 	sdhci@12520000 {
@@ -34,13 +34,26 @@
 	sdhci@12530000 {
 		samsung,bus-width = <4>;
 		samsung,timing = <1 2 3>;
-		cd-gpios = <&gpio 0x39C 0>;
+		cd-gpios = <&gpio 284 0>;
 	};
 
 	sdhci@12540000 {
 		status = "disabled";
 	};
 
+	soft-spi {
+		compatible = "u-boot,soft-spi";
+		cs-gpio = <&gpio 235 0>;	/* Y43 */
+		sclk-gpio = <&gpio 225 0>;	/* Y31 */
+		mosi-gpio = <&gpio 227 0>;	/* Y33 */
+		miso-gpio = <&gpio 224 0>;	/* Y30 */
+		spi-delay-us = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cs@0 {
+		};
+	};
+
 	fimd@11c00000 {
 		compatible = "samsung,exynos-fimd";
 		reg = <0x11c00000 0xa4>;
diff --git a/arch/arm/dts/exynos4210.dtsi b/arch/arm/dts/exynos4210.dtsi
new file mode 100644
index 00000000000..634a5c1dd27
--- /dev/null
+++ b/arch/arm/dts/exynos4210.dtsi
@@ -0,0 +1,156 @@
+/*
+ * Samsung's Exynos4210 SoC device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *		www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include "exynos4.dtsi"
+#include "exynos4210-pinctrl.dtsi"
+#include "exynos4210-pinctrl-uboot.dtsi"
+
+/ {
+	compatible = "samsung,exynos4210";
+
+	aliases {
+		pinctrl0 = &pinctrl_0;
+		pinctrl1 = &pinctrl_1;
+		pinctrl2 = &pinctrl_2;
+	};
+
+	pd_lcd1: lcd1-power-domain@10023CA0 {
+		compatible = "samsung,exynos4210-pd";
+		reg = <0x10023CA0 0x20>;
+	};
+
+	gic: interrupt-controller@10490000 {
+		cpu-offset = <0x8000>;
+	};
+
+	combiner: interrupt-controller@10440000 {
+		samsung,combiner-nr = <16>;
+		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+	};
+
+	mct@10050000 {
+		compatible = "samsung,exynos4210-mct";
+		reg = <0x10050000 0x800>;
+		interrupt-parent = <&mct_map>;
+		interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
+		clocks = <&clock 3>, <&clock 344>;
+		clock-names = "fin_pll", "mct";
+
+		mct_map: mct-map {
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			#size-cells = <0>;
+			interrupt-map = <0 &gic 0 57 0>,
+					<1 &gic 0 69 0>,
+					<2 &combiner 12 6>,
+					<3 &combiner 12 7>,
+					<4 &gic 0 42 0>,
+					<5 &gic 0 48 0>;
+		};
+	};
+
+	clock: clock-controller@10030000 {
+		compatible = "samsung,exynos4210-clock";
+		reg = <0x10030000 0x20000>;
+		#clock-cells = <1>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupt-parent = <&combiner>;
+		interrupts = <2 2>, <3 2>;
+	};
+
+	pinctrl_0: pinctrl@11400000 {
+		compatible = "samsung,exynos4210-pinctrl";
+		reg = <0x11400000 0x1000>;
+		interrupts = <0 47 0>;
+	};
+
+	pinctrl_1: pinctrl@11000000 {
+		compatible = "samsung,exynos4210-pinctrl";
+		reg = <0x11000000 0x1000>;
+		interrupts = <0 46 0>;
+
+		wakup_eint: wakeup-interrupt-controller {
+			compatible = "samsung,exynos4210-wakeup-eint";
+			interrupt-parent = <&gic>;
+			interrupts = <0 32 0>;
+		};
+	};
+
+	pinctrl_2: pinctrl@03860000 {
+		compatible = "samsung,exynos4210-pinctrl";
+		reg = <0x03860000 0x1000>;
+	};
+
+	tmu@100C0000 {
+		compatible = "samsung,exynos4210-tmu";
+		interrupt-parent = <&combiner>;
+		reg = <0x100C0000 0x100>;
+		interrupts = <2 4>;
+		clocks = <&clock 383>;
+		clock-names = "tmu_apbif";
+		status = "disabled";
+	};
+
+	g2d@12800000 {
+		compatible = "samsung,s5pv210-g2d";
+		reg = <0x12800000 0x1000>;
+		interrupts = <0 89 0>;
+		clocks = <&clock 177>, <&clock 277>;
+		clock-names = "sclk_fimg2d", "fimg2d";
+		status = "disabled";
+	};
+
+	camera {
+		clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>;
+		clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
+
+		fimc_0: fimc@11800000 {
+			samsung,pix-limits = <4224 8192 1920 4224>;
+			samsung,mainscaler-ext;
+			samsung,cam-if;
+		};
+
+		fimc_1: fimc@11810000 {
+			samsung,pix-limits = <4224 8192 1920 4224>;
+			samsung,mainscaler-ext;
+			samsung,cam-if;
+		};
+
+		fimc_2: fimc@11820000 {
+			samsung,pix-limits = <4224 8192 1920 4224>;
+			samsung,mainscaler-ext;
+			samsung,lcd-wb;
+		};
+
+		fimc_3: fimc@11830000 {
+			samsung,pix-limits = <1920 8192 1366 1920>;
+			samsung,rotators = <0>;
+			samsung,mainscaler-ext;
+			samsung,lcd-wb;
+		};
+	};
+};
diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts
index 24d0bf18e3e..2a1f1dda4e2 100644
--- a/arch/arm/dts/exynos4412-odroid.dts
+++ b/arch/arm/dts/exynos4412-odroid.dts
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "exynos4.dtsi"
+#include "exynos4412.dtsi"
 
 / {
 	model = "Odroid based on Exynos4412";
@@ -51,7 +51,7 @@
 	sdhci@12530000 {
 		samsung,bus-width = <4>;
 		samsung,timing = <1 2 3>;
-		cd-gpios = <&gpio 0xC2 0>;
+		cd-gpios = <&gpio 122 0>;
 	};
 
 	sdhci@12540000 {
diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts
index cc58c878b82..60e4515a7e7 100644
--- a/arch/arm/dts/exynos4412-trats2.dts
+++ b/arch/arm/dts/exynos4412-trats2.dts
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "exynos4.dtsi"
+#include "exynos4412.dtsi"
 
 / {
 	model = "Samsung Trats2 based on Exynos4412";
@@ -416,7 +416,7 @@
 	sdhci@12510000 {
 		samsung,bus-width = <8>;
 		samsung,timing = <1 3 3>;
-		pwr-gpios = <&gpio 0xB2 0>;
+		pwr-gpios = <&gpio 0x6a 0>;
 		status = "disabled";
 	};
 
@@ -427,7 +427,7 @@
 	sdhci@12530000 {
 		samsung,bus-width = <4>;
 		samsung,timing = <1 2 3>;
-		cd-gpios = <&gpio 0x3BC 0>;
+		cd-gpios = <&gpio 0x7a 0>;
 	};
 
 	sdhci@12540000 {
@@ -437,7 +437,7 @@
 	dwmmc@12550000 {
 		samsung,bus-width = <8>;
 		samsung,timing = <2 1 0>;
-		pwr-gpios = <&gpio 0xB2 0>;
+		pwr-gpios = <&gpio 0x6a 0>;
 		fifoth_val = <0x203f0040>;
 		bus_hz = <400000000>;
 		div = <0x3>;
diff --git a/arch/arm/dts/exynos4412.dtsi b/arch/arm/dts/exynos4412.dtsi
new file mode 100644
index 00000000000..87b339c739d
--- /dev/null
+++ b/arch/arm/dts/exynos4412.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Samsung's Exynos4412 SoC device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include "exynos4x12.dtsi"
+
+/ {
+	compatible = "samsung,exynos4412";
+
+	gic: interrupt-controller@10490000 {
+		cpu-offset = <0x4000>;
+	};
+
+	interrupt-controller@10440000 {
+		samsung,combiner-nr = <20>;
+		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+			     <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
+	};
+
+};
diff --git a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
new file mode 100644
index 00000000000..c41d07b65fc
--- /dev/null
+++ b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
@@ -0,0 +1,43 @@
+/*
+ * U-Boot additions to enable a generic Exynos GPIO driver
+ *
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/{
+	pinctrl_0: pinctrl@11400000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpf0: gpf0 {
+			reg = <0x180>;
+		};
+		gpj0: gpj0 {
+			reg = <0x240>;
+		};
+	};
+
+	pinctrl_1: pinctrl@11000000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpk0: gpk0 {
+			reg = <0x40>;
+		};
+		gpm0: gpm0 {
+			reg = <0x260>;
+		};
+		gpx0: gpx0 {
+			reg = <0xc00>;
+		};
+	};
+
+	pinctrl_2: pinctrl@03860000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	pinctrl_3: pinctrl@106E0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+};
diff --git a/arch/arm/dts/exynos4x12-pinctrl.dtsi b/arch/arm/dts/exynos4x12-pinctrl.dtsi
new file mode 100644
index 00000000000..23061351ffb
--- /dev/null
+++ b/arch/arm/dts/exynos4x12-pinctrl.dtsi
@@ -0,0 +1,344 @@
+/*
+ * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+	pinctrl@11400000 {
+		gpa0: gpa0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpa1: gpa1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb: gpb {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc0: gpc0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc1: gpc1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpd0: gpd0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpd1: gpd1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpf0: gpf0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpf1: gpf1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpf2: gpf2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpf3: gpf3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpj0: gpj0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpj1: gpj1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pinctrl@11000000 {
+		gpk0: gpk0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpk1: gpk1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpk2: gpk2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpk3: gpk3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpl0: gpl0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpl1: gpl1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpl2: gpl2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpy0: gpy0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy1: gpy1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy2: gpy2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy3: gpy3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy4: gpy4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy5: gpy5 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy6: gpy6 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpm0: gpm0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpm1: gpm1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpm2: gpm2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpm3: gpm3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpm4: gpm4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpx0: gpx0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			interrupt-parent = <&gic>;
+			interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+				     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
+			#interrupt-cells = <2>;
+		};
+
+		gpx1: gpx1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			interrupt-parent = <&gic>;
+			interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+				     <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+			#interrupt-cells = <2>;
+		};
+
+		gpx2: gpx2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpx3: gpx3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pinctrl@03860000 {
+		gpz: gpz {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pinctrl@106E0000 {
+		gpv0: gpv0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpv1: gpv1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpv2: gpv2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpv3: gpv3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpv4: gpv4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
diff --git a/arch/arm/dts/exynos4x12.dtsi b/arch/arm/dts/exynos4x12.dtsi
new file mode 100644
index 00000000000..5d58c6eedcf
--- /dev/null
+++ b/arch/arm/dts/exynos4x12.dtsi
@@ -0,0 +1,115 @@
+/*
+ * Samsung's Exynos4x12 SoCs device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+` * published by the Free Software Foundation.
+*/
+
+#include "exynos4.dtsi"
+#include "exynos4x12-pinctrl.dtsi"
+#include "exynos4x12-pinctrl-uboot.dtsi"
+
+/ {
+	aliases {
+		pinctrl0 = &pinctrl_0;
+		pinctrl1 = &pinctrl_1;
+		pinctrl2 = &pinctrl_2;
+		pinctrl3 = &pinctrl_3;
+		mshc0 = &mshc_0;
+	};
+
+	pd_isp: isp-power-domain@10023CA0 {
+		compatible = "samsung,exynos4210-pd";
+		reg = <0x10023CA0 0x20>;
+	};
+
+	clock: clock-controller@10030000 {
+		compatible = "samsung,exynos4412-clock";
+		reg = <0x10030000 0x20000>;
+		#clock-cells = <1>;
+	};
+
+	mct@10050000 {
+		compatible = "samsung,exynos4412-mct";
+		reg = <0x10050000 0x800>;
+		interrupt-parent = <&mct_map>;
+		interrupts = <0>, <1>, <2>, <3>, <4>;
+		clocks = <&clock 3>, <&clock 344>;
+		clock-names = "fin_pll", "mct";
+
+		mct_map: mct-map {
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			#size-cells = <0>;
+			interrupt-map = <0 &gic 0 57 0>,
+					<1 &combiner 12 5>,
+					<2 &combiner 12 6>,
+					<3 &combiner 12 7>,
+					<4 &gic 1 12 0>;
+		};
+	};
+
+	pinctrl_0: pinctrl@11400000 {
+		compatible = "samsung,exynos4x12-pinctrl";
+		reg = <0x11400000 0x1000>;
+		interrupts = <0 47 0>;
+	};
+
+	pinctrl_1: pinctrl@11000000 {
+		compatible = "samsung,exynos4x12-pinctrl";
+		reg = <0x11000000 0x1000>;
+		interrupts = <0 46 0>;
+
+		wakup_eint: wakeup-interrupt-controller {
+			compatible = "samsung,exynos4210-wakeup-eint";
+			interrupt-parent = <&gic>;
+			interrupts = <0 32 0>;
+		};
+	};
+
+	pinctrl_2: pinctrl@03860000 {
+		compatible = "samsung,exynos4x12-pinctrl";
+		reg = <0x03860000 0x1000>;
+		interrupt-parent = <&combiner>;
+		interrupts = <10 0>;
+	};
+
+	pinctrl_3: pinctrl@106E0000 {
+		compatible = "samsung,exynos4x12-pinctrl";
+		reg = <0x106E0000 0x1000>;
+		interrupts = <0 72 0>;
+	};
+
+	g2d@10800000 {
+		compatible = "samsung,exynos4212-g2d";
+		reg = <0x10800000 0x1000>;
+		interrupts = <0 89 0>;
+		clocks = <&clock 177>, <&clock 277>;
+		clock-names = "sclk_fimg2d", "fimg2d";
+		status = "disabled";
+	};
+
+	mshc_0: mmc@12550000 {
+		compatible = "samsung,exynos4412-dw-mshc";
+		reg = <0x12550000 0x1000>;
+		interrupts = <0 77 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		fifo-depth = <0x80>;
+		clocks = <&clock 301>, <&clock 149>;
+		clock-names = "biu", "ciu";
+		status = "disabled";
+	};
+};
diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
index a2b533a1368..e53906892c8 100644
--- a/arch/arm/dts/exynos5.dtsi
+++ b/arch/arm/dts/exynos5.dtsi
@@ -5,11 +5,38 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "samsung,exynos5";
 
+	combiner: interrupt-controller@10440000 {
+		compatible = "samsung,exynos4210-combiner";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		samsung,combiner-nr = <32>;
+		reg = <0x10440000 0x1000>;
+		interrupts =	<0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+				<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+				<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+				<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+				<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+				<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+				<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+				<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+	};
+
+	gic: interrupt-controller@10481000 {
+		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg =	<0x10481000 0x1000>,
+			<0x10482000 0x1000>,
+			<0x10484000 0x2000>,
+			<0x10486000 0x2000>;
+		interrupts = <1 9 0xf04>;
+	};
+
 	sromc@12250000 {
 		compatible = "samsung,exynos-sromc";
 		reg = <0x12250000 0x20>;
@@ -17,6 +44,33 @@
 		#size-cells = <0>;
 	};
 
+	combiner: interrupt-controller@10440000 {
+		compatible = "samsung,exynos4210-combiner";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		samsung,combiner-nr = <32>;
+		reg = <0x10440000 0x1000>;
+		interrupts =	<0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+				<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+				<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+				<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+				<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+				<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+				<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+				<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+	};
+
+	gic: interrupt-controller@10481000 {
+		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg =	<0x10481000 0x1000>,
+			<0x10482000 0x1000>,
+			<0x10484000 0x2000>,
+			<0x10486000 0x2000>;
+		interrupts = <1 9 0xf04>;
+	};
+
 	i2c@12c60000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -190,6 +244,7 @@
 		compatible = "samsung,exynos4210-uart";
 		reg = <0x12C30000 0x100>;
 		interrupts = <0 54 0>;
+		u-boot,dm-pre-reloc;
 		id = <3>;
 	};
 
diff --git a/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
new file mode 100644
index 00000000000..7edb0ca2900
--- /dev/null
+++ b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
@@ -0,0 +1,40 @@
+/*
+ * U-Boot additions to enable a generic Exynos GPIO driver
+ *
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/{
+	pinctrl_0: pinctrl@11400000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpc4: gpc4 {
+			reg = <0x2e0>;
+		};
+		gpx0: gpx0 {
+			reg = <0xc00>;
+		};
+	};
+
+	pinctrl_1: pinctrl@13400000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	pinctrl_2: pinctrl@10d10000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpv2: gpv2 {
+			reg = <0x060>;
+		};
+		gpv4: gpv4 {
+			reg = <0xc0>;
+		};
+	};
+
+	pinctrl_3: pinctrl@03860000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+};
diff --git a/arch/arm/dts/exynos5250-pinctrl.dtsi b/arch/arm/dts/exynos5250-pinctrl.dtsi
new file mode 100644
index 00000000000..67755a1e08f
--- /dev/null
+++ b/arch/arm/dts/exynos5250-pinctrl.dtsi
@@ -0,0 +1,331 @@
+/*
+ * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+	pinctrl@11400000 {
+		gpa0: gpa0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpa1: gpa1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpa2: gpa2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb0: gpb0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb1: gpb1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb2: gpb2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb3: gpb3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc0: gpc0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc1: gpc1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc2: gpc2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc3: gpc3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpd0: gpd0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpd1: gpd1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpy0: gpy0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy1: gpy1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy2: gpy2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy3: gpy3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy4: gpy4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy5: gpy5 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy6: gpy6 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpc4: gpc4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpx0: gpx0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			interrupt-parent = <&combiner>;
+			#interrupt-cells = <2>;
+			interrupts = <23 0>, <24 0>, <25 0>, <25 1>,
+				     <26 0>, <26 1>, <27 0>, <27 1>;
+		};
+
+		gpx1: gpx1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			interrupt-parent = <&combiner>;
+			#interrupt-cells = <2>;
+			interrupts = <28 0>, <28 1>, <29 0>, <29 1>,
+				     <30 0>, <30 1>, <31 0>, <31 1>;
+		};
+
+		gpx2: gpx2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpx3: gpx3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pinctrl@13400000 {
+		gpe0: gpe0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpe1: gpe1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpf0: gpf0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpf1: gpf1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpg0: gpg0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpg1: gpg1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpg2: gpg2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gph0: gph0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gph1: gph1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+	};
+
+	pinctrl@10d10000 {
+		gpv0: gpv0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpv1: gpv1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpv2: gpv2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpv3: gpv3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpv4: gpv4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+	};
+
+	pinctrl@03860000 {
+		gpz: gpz {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+	};
+};
diff --git a/arch/arm/dts/exynos5250-smdk5250.dts b/arch/arm/dts/exynos5250-smdk5250.dts
index 9020382d97c..885040920c0 100644
--- a/arch/arm/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/dts/exynos5250-smdk5250.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
 
 / {
 	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts
index ab4f2f85815..6fd9275c4ef 100644
--- a/arch/arm/dts/exynos5250-snow.dts
+++ b/arch/arm/dts/exynos5250-snow.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
 
 / {
 	model = "Google Snow";
@@ -53,6 +53,14 @@
 		};
 	};
 
+	spi@12d30000 {
+		spi-max-frequency = <50000000>;
+		firmware_storage_spi: flash@0 {
+			compatible = "spi-flash";
+			reg = <0>;
+		};
+	};
+
 	spi@131b0000 {
 		spi-max-frequency = <1000000>;
 		spi-deactivate-delay = <100>;
diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi
index 0c644e7cac8..ccbafe9b07d 100644
--- a/arch/arm/dts/exynos5250.dtsi
+++ b/arch/arm/dts/exynos5250.dtsi
@@ -5,9 +5,48 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-/include/ "exynos5.dtsi"
+#include "exynos5.dtsi"
+#include "exynos5250-pinctrl.dtsi"
+#include "exynos5250-pinctrl-uboot.dtsi"
 
 / {
+	aliases {
+		pinctrl0 = &pinctrl_0;
+		pinctrl1 = &pinctrl_1;
+		pinctrl2 = &pinctrl_2;
+		pinctrl3 = &pinctrl_3;
+	};
+
+	pinctrl_0: pinctrl@11400000 {
+		compatible = "samsung,exynos5250-pinctrl";
+		reg = <0x11400000 0x1000>;
+		interrupts = <0 46 0>;
+
+		wakup_eint: wakeup-interrupt-controller {
+			compatible = "samsung,exynos4210-wakeup-eint";
+			interrupt-parent = <&gic>;
+			interrupts = <0 32 0>;
+		};
+	};
+
+	pinctrl_1: pinctrl@13400000 {
+		compatible = "samsung,exynos5250-pinctrl";
+		reg = <0x13400000 0x1000>;
+		interrupts = <0 45 0>;
+	};
+
+	pinctrl_2: pinctrl@10d10000 {
+		compatible = "samsung,exynos5250-pinctrl";
+		reg = <0x10d10000 0x1000>;
+		interrupts = <0 50 0>;
+	};
+
+	pinctrl_3: pinctrl@03860000 {
+		compatible = "samsung,exynos5250-pinctrl";
+		reg = <0x03860000 0x1000>;
+		interrupts = <0 47 0>;
+	};
+
 	i2c@12ca0000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts
index 995e62b3372..fde863de3cf 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "exynos54xx.dtsi"
+#include "exynos54xx.dtsi"
 
 / {
 	model = "Samsung/Google Peach Pit board based on Exynos5420";
@@ -140,6 +140,7 @@
 	spi@12d30000 { /* spi1 */
 		spi-max-frequency = <50000000>;
 		firmware_storage_spi: flash@0 {
+			compatible = "spi-flash";
 			reg = <0>;
 
 			/*
diff --git a/arch/arm/dts/exynos5420-smdk5420.dts b/arch/arm/dts/exynos5420-smdk5420.dts
index 1bc62562835..6855027389d 100644
--- a/arch/arm/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/dts/exynos5420-smdk5420.dts
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "exynos54xx.dtsi"
+#include "exynos54xx.dtsi"
 
 / {
 	model = "SAMSUNG SMDK5420 board based on EXYNOS5420";
diff --git a/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
new file mode 100644
index 00000000000..5a86211d4a0
--- /dev/null
+++ b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
@@ -0,0 +1,40 @@
+/*
+ * U-Boot additions to enable a generic Exynos GPIO driver
+ *
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/{
+	/*
+	 * Replicate the ordering of arch/arm/include/asm/arch-exynos/gpio.h
+	 * TODO(sjg@chromium.org): This ordering ceases to matter once GPIO
+	 * numbers are not needed in U-Boot for exynos.
+	 */
+	pinctrl@14010000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+	pinctrl@13400000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpy7 {
+		};
+
+		gpx0 {
+			reg = <0xc00>;
+		};
+	};
+	pinctrl@13410000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+	pinctrl@14000000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+	pinctrl@03860000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+};
diff --git a/arch/arm/dts/exynos54xx-pinctrl.dtsi b/arch/arm/dts/exynos54xx-pinctrl.dtsi
new file mode 100644
index 00000000000..775d956a5f3
--- /dev/null
+++ b/arch/arm/dts/exynos54xx-pinctrl.dtsi
@@ -0,0 +1,305 @@
+/*
+ * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include "exynos54xx-pinctrl-uboot.dtsi"
+
+/ {
+	pinctrl@13400000 {
+		gpy7: gpy7 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpx0: gpx0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			interrupt-parent = <&combiner>;
+			#interrupt-cells = <2>;
+			interrupts = <23 0>, <24 0>, <25 0>, <25 1>,
+				     <26 0>, <26 1>, <27 0>, <27 1>;
+		};
+
+		gpx1: gpx1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			interrupt-parent = <&combiner>;
+			#interrupt-cells = <2>;
+			interrupts = <28 0>, <28 1>, <29 0>, <29 1>,
+				     <30 0>, <30 1>, <31 0>, <31 1>;
+		};
+
+		gpx2: gpx2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpx3: gpx3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+	};
+
+	pinctrl@13410000 {
+		gpc0: gpc0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc1: gpc1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc2: gpc2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc3: gpc3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc4: gpc4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpd1: gpd1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpy0: gpy0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy1: gpy1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy2: gpy2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy3: gpy3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy4: gpy4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy5: gpy5 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpy6: gpy6 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+	};
+
+	pinctrl@14000000 {
+		gpe0: gpe0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpe1: gpe1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpf0: gpf0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpf1: gpf1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpg0: gpg0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpg1: gpg1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpg2: gpg2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpj4: gpj4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+	};
+
+	pinctrl@14010000 {
+		gpa0: gpa0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpa1: gpa1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpa2: gpa2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb0: gpb0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb1: gpb1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb2: gpb2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb3: gpb3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb4: gpb4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gph0: gph0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+	};
+
+	pinctrl@03860000 {
+		gpz: gpz {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+	};
+};
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index c21d798a23d..916cf3a5b66 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -5,7 +5,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-/include/ "exynos5.dtsi"
+#include "exynos5.dtsi"
+#include "exynos54xx-pinctrl.dtsi"
 
 / {
 	config {
@@ -24,6 +25,11 @@
 		i2c8 = "/i2c@12e00000";
 		i2c9 = "/i2c@12e10000";
 		i2c10 = "/i2c@12e20000";
+		pinctrl0 = &pinctrl_0;
+		pinctrl1 = &pinctrl_1;
+		pinctrl2 = &pinctrl_2;
+		pinctrl3 = &pinctrl_3;
+		pinctrl4 = &pinctrl_4;
 		spi0 = "/spi@12d20000";
 		spi1 = "/spi@12d30000";
 		spi2 = "/spi@12d40000";
@@ -123,6 +129,42 @@
 		reg = <0x14680000 0x100>;
 	};
 
+	pinctrl_0: pinctrl@13400000 {
+		compatible = "samsung,exynos5420-pinctrl";
+		reg = <0x13400000 0x1000>;
+		interrupts = <0 45 0>;
+
+		wakeup-interrupt-controller {
+			compatible = "samsung,exynos4210-wakeup-eint";
+			interrupt-parent = <&gic>;
+			interrupts = <0 32 0>;
+		};
+	};
+
+	pinctrl_1: pinctrl@13410000 {
+		compatible = "samsung,exynos5420-pinctrl";
+		reg = <0x13410000 0x1000>;
+		interrupts = <0 78 0>;
+	};
+
+	pinctrl_2: pinctrl@14000000 {
+		compatible = "samsung,exynos5420-pinctrl";
+		reg = <0x14000000 0x1000>;
+		interrupts = <0 46 0>;
+	};
+
+	pinctrl_3: pinctrl@14010000 {
+		compatible = "samsung,exynos5420-pinctrl";
+		reg = <0x14010000 0x1000>;
+		interrupts = <0 50 0>;
+	};
+
+	pinctrl_4: pinctrl@03860000 {
+		compatible = "samsung,exynos5420-pinctrl";
+		reg = <0x03860000 0x1000>;
+		interrupts = <0 47 0>;
+	};
+
 	fimd@14400000 {
 		/* sysmmu is not used in U-Boot */
 		samsung,disable-sysmmu;
diff --git a/arch/arm/dts/s5pc100-pinctrl.dtsi b/arch/arm/dts/s5pc100-pinctrl.dtsi
new file mode 100644
index 00000000000..bd9f97c97ba
--- /dev/null
+++ b/arch/arm/dts/s5pc100-pinctrl.dtsi
@@ -0,0 +1,180 @@
+/*
+ * U-Boot additions to enable a generic Exynos GPIO driver
+ *
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/ {
+	pinctrl@e0300000 {
+		gpa0: gpa0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpa1: gpa1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpb: gpb {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpc: gpc {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpd: gpd {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpe0: gpe0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpe1: gpe1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpf0: gpf0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpf1: gpf1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpf2: gpf2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpf3: gpf3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpg0: gpg0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpg1: gpg1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpg2: gpg2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpg3: gpg3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpi: gpi {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpj0: gpj0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpj1: gpj1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpj2: gpj2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpj3: gpj3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpj4: gpj4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpk0: gpk0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpk1: gpk1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpk2: gpk2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpk3: gpk3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpl0: gpl0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpl1: gpl1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpl2: gpl2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpl3: gpl3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpl4: gpl4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gph0: gph0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gph1: gph1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gph2: gph2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gph3: gph3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+	};
+};
diff --git a/arch/arm/dts/s5pc110-pinctrl.dtsi b/arch/arm/dts/s5pc110-pinctrl.dtsi
new file mode 100644
index 00000000000..d21b6ab756a
--- /dev/null
+++ b/arch/arm/dts/s5pc110-pinctrl.dtsi
@@ -0,0 +1,273 @@
+/*
+ * U-Boot additions to enable a generic Exynos GPIO driver
+ *
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/ {
+	pinctrl@e0200000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpa0: gpa0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpa1: gpa1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpb: gpb {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpc0: gpc0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpc1: gpc1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpd0: gpd0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpd1: gpd1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpe0: gpe0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpe1: gpe1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpf0: gpf0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpf1: gpf1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpf2: gpf2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpf3: gpf3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpg0: gpg0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpg1: gpg1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpg2: gpg2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpg3: gpg3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpi: gpi {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpj0: gpj0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpj1: gpj1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpj2: gpj2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpj3: gpj3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpj4: gpj4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp01: gpmp01 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp02: gpmp02 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp03: gpmp03 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp04: gpmp04 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp05: gpmp05 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp06: gpmp06 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp07: gpmp07 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp10: gpmp10 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp11: gpmp11 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp12: gpmp12 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp13: gpmp13 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp14: gpmp14 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp15: gpmp15 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp16: gpmp16 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp17: gpmp17 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp18: gpmp18 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp20: gpmp20 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp21: gpmp21 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp22: gpmp22 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp23: gpmp23 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp24: gpmp24 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp25: gpmp25 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp26: gpmp26 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp27: gpmp27 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpmp28: gpmp28 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gph0: gph0 {
+			reg = <0xc00>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gph1: gph1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gph2: gph2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gph3: gph3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+	};
+};
diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts
index 2e671bbf7e9..7bbfe591cd8 100644
--- a/arch/arm/dts/s5pc1xx-goni.dts
+++ b/arch/arm/dts/s5pc1xx-goni.dts
@@ -9,6 +9,7 @@
 /dts-v1/;
 
 #include "skeleton.dtsi"
+#include "s5pc110-pinctrl.dtsi"
 
 / {
 	model = "Samsung Goni based on S5PC110";
@@ -17,6 +18,12 @@
 	aliases {
 		serial2 = "/serial@e2900800";
 		console = "/serial@e2900800";
+		pinctrl0 = &pinctrl0;
+	};
+
+	pinctrl0: pinctrl@e0200000 {
+		compatible = "samsung,s5pc110-pinctrl";
+		reg = <0xe0200000 0x1000>;
 	};
 
 	serial@e2900800 {
diff --git a/arch/arm/dts/s5pc1xx-smdkc100.dts b/arch/arm/dts/s5pc1xx-smdkc100.dts
index 42754ce811c..95f15ed48d3 100644
--- a/arch/arm/dts/s5pc1xx-smdkc100.dts
+++ b/arch/arm/dts/s5pc1xx-smdkc100.dts
@@ -9,6 +9,7 @@
 /dts-v1/;
 
 #include "skeleton.dtsi"
+#include "s5pc100-pinctrl.dtsi"
 
 / {
 	model = "Samsung SMDKC100 based on S5PC100";
@@ -17,6 +18,12 @@
 	aliases {
 		serial0 = "/serial@ec000000";
 		console = "/serial@ec000000";
+		pinctrl0 = &pinctrl0;
+	};
+
+	pinctrl0: pinctrl@e0300000 {
+		compatible = "samsung,s5pc100-pinctrl";
+		reg = <0xe0200000 0x1000>;
 	};
 
 	serial@ec000000 {
diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts
new file mode 100644
index 00000000000..f7cc8e7a09c
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-pcduino3.dts
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2014 Zoltan HERPAI
+ * Zoltan HERPAI <wigyori@uid0.hu>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "LinkSprite pcDuino3";
+	compatible = "linksprite,pcduino3", "allwinner,sun7i-a20";
+
+	chosen {
+		stdout-path = &uart0;
+	};
+
+	soc@01c00000 {
+		mmc0: mmc@01c0f000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+			vmmc-supply = <&reg_vcc3v3>;
+			bus-width = <4>;
+			cd-gpios = <&pio 7 1 0>; /* PH1 */
+			cd-inverted;
+			status = "okay";
+		};
+
+		usbphy: phy@01c13400 {
+			usb1_vbus-supply = <&reg_usb1_vbus>;
+			usb2_vbus-supply = <&reg_usb2_vbus>;
+			status = "okay";
+		};
+
+		ehci0: usb@01c14000 {
+			status = "okay";
+		};
+
+		ohci0: usb@01c14400 {
+			status = "okay";
+		};
+
+		ahci: sata@01c18000 {
+			target-supply = <&reg_ahci_5v>;
+			status = "okay";
+		};
+
+		ehci1: usb@01c1c000 {
+			status = "okay";
+		};
+
+		ohci1: usb@01c1c400 {
+			status = "okay";
+		};
+
+		pinctrl@01c20800 {
+			ahci_pwr_pin_a: ahci_pwr_pin@0 {
+				allwinner,pins = "PH2";
+			};
+
+			led_pins_pcduino3: led_pins@0 {
+				allwinner,pins = "PH15", "PH16";
+				allwinner,function = "gpio_out";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			key_pins_pcduino3: key_pins@0 {
+				allwinner,pins = "PH17", "PH18", "PH19";
+				allwinner,function = "gpio_in";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+		};
+
+		ir0: ir@01c21800 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&ir0_pins_a>;
+			status = "okay";
+		};
+
+		uart0: serial@01c28000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_pins_a>;
+			status = "okay";
+		};
+
+		i2c0: i2c@01c2ac00 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins_a>;
+			status = "okay";
+
+			axp209: pmic@34 {
+				compatible = "x-powers,axp209";
+				reg = <0x34>;
+				interrupt-parent = <&nmi_intc>;
+				interrupts = <0 8>;
+
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		gmac: ethernet@01c50000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&gmac_pins_mii_a>;
+			phy = <&phy1>;
+			phy-mode = "mii";
+			status = "okay";
+
+			phy1: ethernet-phy@1 {
+				reg = <1>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_pins_pcduino3>;
+
+		tx {
+			label = "pcduino3:green:tx";
+			gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
+		};
+
+		rx {
+			label = "pcduino3:green:rx";
+			gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_pins_pcduino3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		button@0 {
+			label = "Key Back";
+			linux,code = <KEY_BACK>;
+			gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
+		};
+		button@1 {
+			label = "Key Home";
+			linux,code = <KEY_HOME>;
+			gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
+		};
+		button@2 {
+			label = "Key Menu";
+			linux,code = <KEY_MENU>;
+			gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	reg_usb1_vbus: usb1-vbus {
+		status = "okay";
+	};
+
+	reg_usb2_vbus: usb2-vbus {
+		status = "okay";
+	};
+
+	reg_ahci_5v: ahci-5v {
+		gpio = <&pio 7 2 0>;
+		status = "okay";
+	};
+};
diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi
new file mode 100644
index 00000000000..4011628c738
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20.dtsi
@@ -0,0 +1,988 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&gic>;
+
+	aliases {
+		ethernet0 = &gmac;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+		serial6 = &uart6;
+		serial7 = &uart7;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <1>;
+		};
+	};
+
+	memory {
+		reg = <0x40000000 0x80000000>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <1 13 0xf08>,
+			     <1 14 0xf08>,
+			     <1 11 0xf08>,
+			     <1 10 0xf08>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+		interrupts = <0 120 4>,
+			     <0 121 4>;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc24M: clk@01c20050 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-osc-clk";
+			reg = <0x01c20050 0x4>;
+			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
+		};
+
+		osc32k: clk@0 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			clock-output-names = "osc32k";
+		};
+
+		pll1: clk@01c20000 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-pll1-clk";
+			reg = <0x01c20000 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll1";
+		};
+
+		pll4: clk@01c20018 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-pll4-clk";
+			reg = <0x01c20018 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll4";
+		};
+
+		pll5: clk@01c20020 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-pll5-clk";
+			reg = <0x01c20020 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll5_ddr", "pll5_other";
+		};
+
+		pll6: clk@01c20028 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-pll6-clk";
+			reg = <0x01c20028 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll6_sata", "pll6_other", "pll6";
+		};
+
+		pll8: clk@01c20040 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-pll4-clk";
+			reg = <0x01c20040 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll8";
+		};
+
+		cpu: cpu@01c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-cpu-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
+			clock-output-names = "cpu";
+		};
+
+		axi: axi@01c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-axi-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&cpu>;
+			clock-output-names = "axi";
+		};
+
+		ahb: ahb@01c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-ahb-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&axi>;
+			clock-output-names = "ahb";
+		};
+
+		ahb_gates: clk@01c20060 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun7i-a20-ahb-gates-clk";
+			reg = <0x01c20060 0x8>;
+			clocks = <&ahb>;
+			clock-output-names = "ahb_usb0", "ahb_ehci0",
+				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
+				"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+				"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
+				"ahb_nand", "ahb_sdram", "ahb_ace",
+				"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
+				"ahb_spi2", "ahb_spi3", "ahb_sata",
+				"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
+				"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
+				"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
+				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+				"ahb_de_fe1", "ahb_gmac", "ahb_mp",
+				"ahb_mali";
+		};
+
+		apb0: apb0@01c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-apb0-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&ahb>;
+			clock-output-names = "apb0";
+		};
+
+		apb0_gates: clk@01c20068 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun7i-a20-apb0-gates-clk";
+			reg = <0x01c20068 0x4>;
+			clocks = <&apb0>;
+			clock-output-names = "apb0_codec", "apb0_spdif",
+				"apb0_ac97", "apb0_iis0", "apb0_iis1",
+				"apb0_pio", "apb0_ir0", "apb0_ir1",
+				"apb0_iis2", "apb0_keypad";
+		};
+
+		apb1_mux: apb1_mux@01c20058 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-apb1-mux-clk";
+			reg = <0x01c20058 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+			clock-output-names = "apb1_mux";
+		};
+
+		apb1: apb1@01c20058 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-apb1-clk";
+			reg = <0x01c20058 0x4>;
+			clocks = <&apb1_mux>;
+			clock-output-names = "apb1";
+		};
+
+		apb1_gates: clk@01c2006c {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun7i-a20-apb1-gates-clk";
+			reg = <0x01c2006c 0x4>;
+			clocks = <&apb1>;
+			clock-output-names = "apb1_i2c0", "apb1_i2c1",
+				"apb1_i2c2", "apb1_i2c3", "apb1_can",
+				"apb1_scr", "apb1_ps20", "apb1_ps21",
+				"apb1_i2c4", "apb1_uart0", "apb1_uart1",
+				"apb1_uart2", "apb1_uart3", "apb1_uart4",
+				"apb1_uart5", "apb1_uart6", "apb1_uart7";
+		};
+
+		nand_clk: clk@01c20080 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20080 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "nand";
+		};
+
+		ms_clk: clk@01c20084 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20084 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "ms";
+		};
+
+		mmc0_clk: clk@01c20088 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20088 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "mmc0";
+		};
+
+		mmc1_clk: clk@01c2008c {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c2008c 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "mmc1";
+		};
+
+		mmc2_clk: clk@01c20090 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20090 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "mmc2";
+		};
+
+		mmc3_clk: clk@01c20094 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20094 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "mmc3";
+		};
+
+		ts_clk: clk@01c20098 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20098 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "ts";
+		};
+
+		ss_clk: clk@01c2009c {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c2009c 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "ss";
+		};
+
+		spi0_clk: clk@01c200a0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200a0 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "spi0";
+		};
+
+		spi1_clk: clk@01c200a4 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200a4 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "spi1";
+		};
+
+		spi2_clk: clk@01c200a8 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200a8 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "spi2";
+		};
+
+		pata_clk: clk@01c200ac {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200ac 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "pata";
+		};
+
+		ir0_clk: clk@01c200b0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200b0 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "ir0";
+		};
+
+		ir1_clk: clk@01c200b4 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200b4 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "ir1";
+		};
+
+		usb_clk: clk@01c200cc {
+			#clock-cells = <1>;
+		        #reset-cells = <1>;
+			compatible = "allwinner,sun4i-a10-usb-clk";
+			reg = <0x01c200cc 0x4>;
+			clocks = <&pll6 1>;
+			clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
+		};
+
+		spi3_clk: clk@01c200d4 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c200d4 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+			clock-output-names = "spi3";
+		};
+
+		mbus_clk: clk@01c2015c {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c2015c 0x4>;
+			clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
+			clock-output-names = "mbus";
+		};
+
+		/*
+		 * The following two are dummy clocks, placeholders used in the gmac_tx
+		 * clock. The gmac driver will choose one parent depending on the PHY
+		 * interface mode, using clk_set_rate auto-reparenting.
+		 * The actual TX clock rate is not controlled by the gmac_tx clock.
+		 */
+		mii_phy_tx_clk: clk@2 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <25000000>;
+			clock-output-names = "mii_phy_tx";
+		};
+
+		gmac_int_tx_clk: clk@3 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <125000000>;
+			clock-output-names = "gmac_int_tx";
+		};
+
+		gmac_tx_clk: clk@01c20164 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-gmac-clk";
+			reg = <0x01c20164 0x4>;
+			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+			clock-output-names = "gmac_tx";
+		};
+
+		/*
+		 * Dummy clock used by output clocks
+		 */
+		osc24M_32k: clk@1 {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <750>;
+			clock-mult = <1>;
+			clocks = <&osc24M>;
+			clock-output-names = "osc24M_32k";
+		};
+
+		clk_out_a: clk@01c201f0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-out-clk";
+			reg = <0x01c201f0 0x4>;
+			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+			clock-output-names = "clk_out_a";
+		};
+
+		clk_out_b: clk@01c201f4 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-out-clk";
+			reg = <0x01c201f4 0x4>;
+			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+			clock-output-names = "clk_out_b";
+		};
+	};
+
+	soc@01c00000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		nmi_intc: interrupt-controller@01c00030 {
+			compatible = "allwinner,sun7i-a20-sc-nmi";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x01c00030 0x0c>;
+			interrupts = <0 0 4>;
+		};
+
+		spi0: spi@01c05000 {
+			compatible = "allwinner,sun4i-a10-spi";
+			reg = <0x01c05000 0x1000>;
+			interrupts = <0 10 4>;
+			clocks = <&ahb_gates 20>, <&spi0_clk>;
+			clock-names = "ahb", "mod";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@01c06000 {
+			compatible = "allwinner,sun4i-a10-spi";
+			reg = <0x01c06000 0x1000>;
+			interrupts = <0 11 4>;
+			clocks = <&ahb_gates 21>, <&spi1_clk>;
+			clock-names = "ahb", "mod";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		emac: ethernet@01c0b000 {
+			compatible = "allwinner,sun4i-a10-emac";
+			reg = <0x01c0b000 0x1000>;
+			interrupts = <0 55 4>;
+			clocks = <&ahb_gates 17>;
+			status = "disabled";
+		};
+
+		mdio@01c0b080 {
+			compatible = "allwinner,sun4i-a10-mdio";
+			reg = <0x01c0b080 0x14>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc0: mmc@01c0f000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c0f000 0x1000>;
+			clocks = <&ahb_gates 8>, <&mmc0_clk>;
+			clock-names = "ahb", "mmc";
+			interrupts = <0 32 4>;
+			status = "disabled";
+		};
+
+		mmc1: mmc@01c10000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c10000 0x1000>;
+			clocks = <&ahb_gates 9>, <&mmc1_clk>;
+			clock-names = "ahb", "mmc";
+			interrupts = <0 33 4>;
+			status = "disabled";
+		};
+
+		mmc2: mmc@01c11000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c11000 0x1000>;
+			clocks = <&ahb_gates 10>, <&mmc2_clk>;
+			clock-names = "ahb", "mmc";
+			interrupts = <0 34 4>;
+			status = "disabled";
+		};
+
+		mmc3: mmc@01c12000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c12000 0x1000>;
+			clocks = <&ahb_gates 11>, <&mmc3_clk>;
+			clock-names = "ahb", "mmc";
+			interrupts = <0 35 4>;
+			status = "disabled";
+		};
+
+		usbphy: phy@01c13400 {
+			#phy-cells = <1>;
+			compatible = "allwinner,sun7i-a20-usb-phy";
+			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+			reg-names = "phy_ctrl", "pmu1", "pmu2";
+			clocks = <&usb_clk 8>;
+			clock-names = "usb_phy";
+			resets = <&usb_clk 1>, <&usb_clk 2>;
+			reset-names = "usb1_reset", "usb2_reset";
+			status = "disabled";
+		};
+
+		ehci0: usb@01c14000 {
+			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
+			reg = <0x01c14000 0x100>;
+			interrupts = <0 39 4>;
+			clocks = <&ahb_gates 1>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci0: usb@01c14400 {
+			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
+			reg = <0x01c14400 0x100>;
+			interrupts = <0 64 4>;
+			clocks = <&usb_clk 6>, <&ahb_gates 2>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		spi2: spi@01c17000 {
+			compatible = "allwinner,sun4i-a10-spi";
+			reg = <0x01c17000 0x1000>;
+			interrupts = <0 12 4>;
+			clocks = <&ahb_gates 22>, <&spi2_clk>;
+			clock-names = "ahb", "mod";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		ahci: sata@01c18000 {
+			compatible = "allwinner,sun4i-a10-ahci";
+			reg = <0x01c18000 0x1000>;
+			interrupts = <0 56 4>;
+			clocks = <&pll6 0>, <&ahb_gates 25>;
+			status = "disabled";
+		};
+
+		ehci1: usb@01c1c000 {
+			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
+			reg = <0x01c1c000 0x100>;
+			interrupts = <0 40 4>;
+			clocks = <&ahb_gates 3>;
+			phys = <&usbphy 2>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci1: usb@01c1c400 {
+			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
+			reg = <0x01c1c400 0x100>;
+			interrupts = <0 65 4>;
+			clocks = <&usb_clk 7>, <&ahb_gates 4>;
+			phys = <&usbphy 2>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		spi3: spi@01c1f000 {
+			compatible = "allwinner,sun4i-a10-spi";
+			reg = <0x01c1f000 0x1000>;
+			interrupts = <0 50 4>;
+			clocks = <&ahb_gates 23>, <&spi3_clk>;
+			clock-names = "ahb", "mod";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		pio: pinctrl@01c20800 {
+			compatible = "allwinner,sun7i-a20-pinctrl";
+			reg = <0x01c20800 0x400>;
+			interrupts = <0 28 4>;
+			clocks = <&apb0_gates 5>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			#size-cells = <0>;
+			#gpio-cells = <3>;
+
+			pwm0_pins_a: pwm0@0 {
+				allwinner,pins = "PB2";
+				allwinner,function = "pwm";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			pwm1_pins_a: pwm1@0 {
+				allwinner,pins = "PI3";
+				allwinner,function = "pwm";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			uart0_pins_a: uart0@0 {
+				allwinner,pins = "PB22", "PB23";
+				allwinner,function = "uart0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			uart2_pins_a: uart2@0 {
+				allwinner,pins = "PI16", "PI17", "PI18", "PI19";
+				allwinner,function = "uart2";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			uart6_pins_a: uart6@0 {
+				allwinner,pins = "PI12", "PI13";
+				allwinner,function = "uart6";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			uart7_pins_a: uart7@0 {
+				allwinner,pins = "PI20", "PI21";
+				allwinner,function = "uart7";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			i2c0_pins_a: i2c0@0 {
+				allwinner,pins = "PB0", "PB1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			i2c1_pins_a: i2c1@0 {
+				allwinner,pins = "PB18", "PB19";
+				allwinner,function = "i2c1";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			i2c2_pins_a: i2c2@0 {
+				allwinner,pins = "PB20", "PB21";
+				allwinner,function = "i2c2";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			emac_pins_a: emac0@0 {
+				allwinner,pins = "PA0", "PA1", "PA2",
+						"PA3", "PA4", "PA5", "PA6",
+						"PA7", "PA8", "PA9", "PA10",
+						"PA11", "PA12", "PA13", "PA14",
+						"PA15", "PA16";
+				allwinner,function = "emac";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			clk_out_a_pins_a: clk_out_a@0 {
+				allwinner,pins = "PI12";
+				allwinner,function = "clk_out_a";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			clk_out_b_pins_a: clk_out_b@0 {
+				allwinner,pins = "PI13";
+				allwinner,function = "clk_out_b";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			gmac_pins_mii_a: gmac_mii@0 {
+				allwinner,pins = "PA0", "PA1", "PA2",
+						"PA3", "PA4", "PA5", "PA6",
+						"PA7", "PA8", "PA9", "PA10",
+						"PA11", "PA12", "PA13", "PA14",
+						"PA15", "PA16";
+				allwinner,function = "gmac";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			gmac_pins_rgmii_a: gmac_rgmii@0 {
+				allwinner,pins = "PA0", "PA1", "PA2",
+						"PA3", "PA4", "PA5", "PA6",
+						"PA7", "PA8", "PA10",
+						"PA11", "PA12", "PA13",
+						"PA15", "PA16";
+				allwinner,function = "gmac";
+				/*
+				 * data lines in RGMII mode use DDR mode
+				 * and need a higher signal drive strength
+				 */
+				allwinner,drive = <3>;
+				allwinner,pull = <0>;
+			};
+
+			spi1_pins_a: spi1@0 {
+				allwinner,pins = "PI16", "PI17", "PI18", "PI19";
+				allwinner,function = "spi1";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			spi2_pins_a: spi2@0 {
+				allwinner,pins = "PC19", "PC20", "PC21", "PC22";
+				allwinner,function = "spi2";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			mmc0_pins_a: mmc0@0 {
+				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+				allwinner,function = "mmc0";
+				allwinner,drive = <2>;
+				allwinner,pull = <0>;
+			};
+
+			mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+				allwinner,pins = "PH1";
+				allwinner,function = "gpio_in";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			mmc3_pins_a: mmc3@0 {
+				allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
+				allwinner,function = "mmc3";
+				allwinner,drive = <2>;
+				allwinner,pull = <0>;
+			};
+
+			ir0_pins_a: ir0@0 {
+				    allwinner,pins = "PB3","PB4";
+				    allwinner,function = "ir0";
+				    allwinner,drive = <0>;
+				    allwinner,pull = <0>;
+			};
+
+			ir1_pins_a: ir1@0 {
+				    allwinner,pins = "PB22","PB23";
+				    allwinner,function = "ir1";
+				    allwinner,drive = <0>;
+				    allwinner,pull = <0>;
+			};
+		};
+
+		timer@01c20c00 {
+			compatible = "allwinner,sun4i-a10-timer";
+			reg = <0x01c20c00 0x90>;
+			interrupts = <0 22 4>,
+				     <0 23 4>,
+				     <0 24 4>,
+				     <0 25 4>,
+				     <0 67 4>,
+				     <0 68 4>;
+			clocks = <&osc24M>;
+		};
+
+		wdt: watchdog@01c20c90 {
+			compatible = "allwinner,sun4i-a10-wdt";
+			reg = <0x01c20c90 0x10>;
+		};
+
+		rtc: rtc@01c20d00 {
+			compatible = "allwinner,sun7i-a20-rtc";
+			reg = <0x01c20d00 0x20>;
+			interrupts = <0 24 4>;
+		};
+
+		pwm: pwm@01c20e00 {
+			compatible = "allwinner,sun7i-a20-pwm";
+			reg = <0x01c20e00 0xc>;
+			clocks = <&osc24M>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+		ir0: ir@01c21800 {
+			compatible = "allwinner,sun4i-a10-ir";
+			clocks = <&apb0_gates 6>, <&ir0_clk>;
+			clock-names = "apb", "ir";
+			interrupts = <0 5 4>;
+			reg = <0x01c21800 0x40>;
+			status = "disabled";
+		};
+
+		ir1: ir@01c21c00 {
+			compatible = "allwinner,sun4i-a10-ir";
+			clocks = <&apb0_gates 7>, <&ir1_clk>;
+			clock-names = "apb", "ir";
+			interrupts = <0 6 4>;
+			reg = <0x01c21c00 0x40>;
+			status = "disabled";
+		};
+
+		sid: eeprom@01c23800 {
+			compatible = "allwinner,sun7i-a20-sid";
+			reg = <0x01c23800 0x200>;
+		};
+
+		rtp: rtp@01c25000 {
+			compatible = "allwinner,sun4i-a10-ts";
+			reg = <0x01c25000 0x100>;
+			interrupts = <0 29 4>;
+		};
+
+		uart0: serial@01c28000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28000 0x400>;
+			interrupts = <0 1 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 16>;
+			status = "disabled";
+		};
+
+		uart1: serial@01c28400 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28400 0x400>;
+			interrupts = <0 2 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 17>;
+			status = "disabled";
+		};
+
+		uart2: serial@01c28800 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28800 0x400>;
+			interrupts = <0 3 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 18>;
+			status = "disabled";
+		};
+
+		uart3: serial@01c28c00 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28c00 0x400>;
+			interrupts = <0 4 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 19>;
+			status = "disabled";
+		};
+
+		uart4: serial@01c29000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c29000 0x400>;
+			interrupts = <0 17 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 20>;
+			status = "disabled";
+		};
+
+		uart5: serial@01c29400 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c29400 0x400>;
+			interrupts = <0 18 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 21>;
+			status = "disabled";
+		};
+
+		uart6: serial@01c29800 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c29800 0x400>;
+			interrupts = <0 19 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 22>;
+			status = "disabled";
+		};
+
+		uart7: serial@01c29c00 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c29c00 0x400>;
+			interrupts = <0 20 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&apb1_gates 23>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@01c2ac00 {
+			compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <0 7 4>;
+			clocks = <&apb1_gates 0>;
+			clock-frequency = <100000>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@01c2b000 {
+			compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <0 8 4>;
+			clocks = <&apb1_gates 1>;
+			clock-frequency = <100000>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@01c2b400 {
+			compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <0 9 4>;
+			clocks = <&apb1_gates 2>;
+			clock-frequency = <100000>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@01c2b800 {
+			compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+			reg = <0x01c2b800 0x400>;
+			interrupts = <0 88 4>;
+			clocks = <&apb1_gates 3>;
+			clock-frequency = <100000>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c4: i2c@01c2c000 {
+			compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+			reg = <0x01c2c000 0x400>;
+			interrupts = <0 89 4>;
+			clocks = <&apb1_gates 15>;
+			clock-frequency = <100000>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		gmac: ethernet@01c50000 {
+			compatible = "allwinner,sun7i-a20-gmac";
+			reg = <0x01c50000 0x10000>;
+			interrupts = <0 85 4>;
+			interrupt-names = "macirq";
+			clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
+			clock-names = "stmmaceth", "allwinner_gmac_tx";
+			snps,pbl = <2>;
+			snps,fixed-burst;
+			snps,force_sf_dma_mode;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		hstimer@01c60000 {
+			compatible = "allwinner,sun7i-a20-hstimer";
+			reg = <0x01c60000 0x1000>;
+			interrupts = <0 81 4>,
+				     <0 82 4>,
+				     <0 83 4>,
+				     <0 84 4>;
+			clocks = <&ahb_gates 28>;
+		};
+
+		gic: interrupt-controller@01c81000 {
+			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+			reg = <0x01c81000 0x1000>,
+			      <0x01c82000 0x1000>,
+			      <0x01c84000 0x2000>,
+			      <0x01c86000 0x2000>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <1 9 0xf04>;
+		};
+	};
+};
diff --git a/arch/arm/dts/sunxi-common-regulators.dtsi b/arch/arm/dts/sunxi-common-regulators.dtsi
new file mode 100644
index 00000000000..3d021efd1a3
--- /dev/null
+++ b/arch/arm/dts/sunxi-common-regulators.dtsi
@@ -0,0 +1,89 @@
+/*
+ * sunxi boards common regulator (ahci target power supply, usb-vbus) code
+ *
+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/ {
+	soc@01c00000 {
+		pio: pinctrl@01c20800 {
+			ahci_pwr_pin_a: ahci_pwr_pin@0 {
+				allwinner,pins = "PB8";
+				allwinner,function = "gpio_out";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			usb1_vbus_pin_a: usb1_vbus_pin@0 {
+				allwinner,pins = "PH6";
+				allwinner,function = "gpio_out";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			usb2_vbus_pin_a: usb2_vbus_pin@0 {
+				allwinner,pins = "PH3";
+				allwinner,function = "gpio_out";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+		};
+	};
+
+	reg_ahci_5v: ahci-5v {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&ahci_pwr_pin_a>;
+		regulator-name = "ahci-5v";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&pio 1 8 0>;
+		status = "disabled";
+	};
+
+	reg_usb1_vbus: usb1-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb1_vbus_pin_a>;
+		regulator-name = "usb1-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&pio 7 6 0>;
+		status = "disabled";
+	};
+
+	reg_usb2_vbus: usb2-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb2_vbus_pin_a>;
+		regulator-name = "usb2-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&pio 7 3 0>;
+		status = "disabled";
+	};
+
+	reg_vcc3v0: vcc3v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v0";
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+	};
+
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts
index cee5cfe0d2d..74e8a16280b 100644
--- a/arch/arm/dts/tegra20-trimslice.dts
+++ b/arch/arm/dts/tegra20-trimslice.dts
@@ -15,6 +15,7 @@
 		usb1 = "/usb@c5000000";
 		sdhci0 = "/sdhci@c8000600";
 		sdhci1 = "/sdhci@c8000000";
+		spi0 = "/spi@7000c380";
 	};
 
 	memory {
diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
new file mode 100644
index 00000000000..5bad3e77698
--- /dev/null
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -0,0 +1,304 @@
+/dts-v1/;
+
+#include "tegra30.dtsi"
+
+/ {
+	model = "Toradex Apalis T30";
+	compatible = "toradex,apalis_t30", "nvidia,tegra30";
+
+	chosen {
+		stdout-path = &uarta;
+	};
+
+	aliases {
+		i2c0 = "/i2c@7000d000";
+		i2c1 = "/i2c@7000c000";
+		i2c2 = "/i2c@7000c500";
+		i2c3 = "/i2c@7000c700";
+		sdhci0 = "/sdhci@78000600";
+		sdhci1 = "/sdhci@78000400";
+		sdhci2 = "/sdhci@78000000";
+		usb0 = "/usb@7d000000";
+		usb1 = "/usb@7d004000";
+		usb2 = "/usb@7d008000";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+
+	pcie-controller@00003000 {
+		status = "okay";
+		avdd-pexa-supply = <&vdd2_reg>;
+		vdd-pexa-supply = <&vdd2_reg>;
+		avdd-pexb-supply = <&vdd2_reg>;
+		vdd-pexb-supply = <&vdd2_reg>;
+		avdd-pex-pll-supply = <&vdd2_reg>;
+		avdd-plle-supply = <&ldo6_reg>;
+		vddio-pex-ctl-supply = <&sys_3v3_reg>;
+		hvdd-pex-supply = <&sys_3v3_reg>;
+
+		pci@1,0 {
+			nvidia,num-lanes = <4>;
+		};
+
+		pci@2,0 {
+			nvidia,num-lanes = <1>;
+		};
+
+		pci@3,0 {
+			status = "okay";
+			nvidia,num-lanes = <1>;
+		};
+	};
+
+	/*
+	 * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
+	 * board)
+	 */
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	/* GEN2_I2C: unused */
+
+	/*
+	 * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
+	 * carrier board)
+	 */
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	/* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
+	i2c@7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	/*
+	 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+	 * touch screen controller
+	 */
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <100000>;
+
+		pmic: tps65911@2d {
+			compatible = "ti,tps65911";
+			reg = <0x2d>;
+
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			ti,system-power-controller;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			vcc1-supply = <&sys_3v3_reg>;
+			vcc2-supply = <&sys_3v3_reg>;
+			vcc3-supply = <&vio_reg>;
+			vcc4-supply = <&sys_3v3_reg>;
+			vcc5-supply = <&sys_3v3_reg>;
+			vcc6-supply = <&vio_reg>;
+			vcc7-supply = <&charge_pump_5v0_reg>;
+			vccio-supply = <&sys_3v3_reg>;
+
+			regulators {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				/* SW1: +V1.35_VDDIO_DDR */
+				vdd1_reg: vdd1 {
+					regulator-name = "vddio_ddr_1v35";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-always-on;
+				};
+
+				/* SW2: +V1.05 */
+				vdd2_reg: vdd2 {
+					regulator-name =
+						"vdd_pexa,vdd_pexb,vdd_sata";
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1050000>;
+				};
+
+				/* SW CTRL: +V1.0_VDD_CPU */
+				vddctrl_reg: vddctrl {
+					regulator-name = "vdd_cpu,vdd_sys";
+					regulator-min-microvolt = <1150000>;
+					regulator-max-microvolt = <1150000>;
+					regulator-always-on;
+				};
+
+				/* SWIO: +V1.8 */
+				vio_reg: vio {
+					regulator-name = "vdd_1v8_gen";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				/* LDO1: unused */
+
+				/*
+				 * EN_+V3.3 switching via FET:
+				 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
+				 * see also v3_3 fixed supply
+				 */
+				ldo2_reg: ldo2 {
+					regulator-name = "en_3v3";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				/* +V1.2_CSI */
+				ldo3_reg: ldo3 {
+					regulator-name =
+						"avdd_dsi_csi,pwrdet_mipi";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				/* +V1.2_VDD_RTC */
+				ldo4_reg: ldo4 {
+					regulator-name = "vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				/*
+				 * +V2.8_AVDD_VDAC:
+				 * only required for analog RGB
+				 */
+				ldo5_reg: ldo5 {
+					regulator-name = "avdd_vdac";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-always-on;
+				};
+
+				/*
+				 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
+				 * but LDO6 can't set voltage in 50mV
+				 * granularity
+				 */
+				ldo6_reg: ldo6 {
+					regulator-name = "avdd_plle";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+				};
+
+				/* +V1.2_AVDD_PLL */
+				ldo7_reg: ldo7 {
+					regulator-name = "avdd_pll";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				/* +V1.0_VDD_DDR_HS */
+				ldo8_reg: ldo8 {
+					regulator-name = "vdd_ddr_hs";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+			};
+		};
+	};
+
+	/* SPI1: Apalis SPI1 */
+	spi@7000d400 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	/* SPI4: CAN2 */
+	spi@7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	/* SPI5: Apalis SPI2 */
+	spi@7000dc00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	/* SPI6: CAN1 */
+	spi@7000de00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	sdhci@78000000 {
+		status = "okay";
+		bus-width = <4>;
+		cd-gpios = <&gpio 229 1>; /* PCC5, SD1_CD# */
+	};
+
+	sdhci@78000400 {
+		status = "okay";
+		bus-width = <8>;
+		cd-gpios = <&gpio 171 1>; /* PV3, MMC1_CD# */
+	};
+
+	sdhci@78000600 {
+		status = "okay";
+		bus-width = <8>;
+		non-removable;
+	};
+
+	/* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
+	usb@7d000000 {
+		status = "okay";
+		dr_mode = "peripheral";
+		nvidia,vbus-gpio = <&gpio 157 0>;	/* PT5, USBO1_EN */
+	};
+
+	/* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
+	usb@7d004000 {
+		status = "okay";
+		nvidia,vbus-gpio = <&gpio 233 0>;	/* PDD1, USBH_EN */
+		phy_type = "utmi";
+	};
+
+	/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
+	usb@7d008000 {
+		status = "okay";
+		nvidia,vbus-gpio = <&gpio 233 0>;	/* PDD1, USBH_EN */
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sys_3v3_reg: regulator@100 {
+			compatible = "regulator-fixed";
+			reg = <100>;
+			regulator-name = "3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		charge_pump_5v0_reg: regulator@101 {
+			compatible = "regulator-fixed";
+			reg = <101>;
+			regulator-name = "5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+	};
+};
diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts
index ad140def95f..9acd84d8029 100644
--- a/arch/arm/dts/tegra30-beaver.dts
+++ b/arch/arm/dts/tegra30-beaver.dts
@@ -18,6 +18,7 @@
 		i2c4 = "/i2c@7000c700";
 		sdhci0 = "/sdhci@78000600";
 		sdhci1 = "/sdhci@78000000";
+		spi0 = "/spi@7000da00";
 		usb0 = "/usb@7d000000";
 		usb1 = "/usb@7d008000";
 	};
diff --git a/arch/arm/dts/tegra30-cardhu.dts b/arch/arm/dts/tegra30-cardhu.dts
index b4fbe71aa53..1b8ed737e04 100644
--- a/arch/arm/dts/tegra30-cardhu.dts
+++ b/arch/arm/dts/tegra30-cardhu.dts
@@ -18,6 +18,7 @@
 		i2c4 = "/i2c@7000c700";
 		sdhci0 = "/sdhci@78000600";
 		sdhci1 = "/sdhci@78000000";
+		spi0 = "/spi@7000da00";
 		usb0 = "/usb@7d008000";
 	};
 
diff --git a/arch/arm/dts/tegra30-colibri.dts b/arch/arm/dts/tegra30-colibri.dts
index 43d03ca4fa5..572520a00ec 100644
--- a/arch/arm/dts/tegra30-colibri.dts
+++ b/arch/arm/dts/tegra30-colibri.dts
@@ -6,12 +6,17 @@
 	model = "Toradex Colibri T30";
 	compatible = "toradex,colibri_t30", "nvidia,tegra30";
 
+	chosen {
+		stdout-path = &uarta;
+	};
+
 	aliases {
 		i2c0 = "/i2c@7000d000";
 		i2c1 = "/i2c@7000c000";
 		i2c2 = "/i2c@7000c700";
 		sdhci0 = "/sdhci@78000600";
 		sdhci1 = "/sdhci@78000200";
+		spi0 = "/spi@7000d400";
 		usb0 = "/usb@7d000000";
 		usb1 = "/usb@7d004000"; /* on module only, for ASIX */
 		usb2 = "/usb@7d008000";
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index ed826a0e19c..09fc22760d0 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -7,7 +7,9 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <bootm.h>
 #include <common.h>
+#include <netdev.h>
 #include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
diff --git a/arch/arm/imx-common/i2c-mxv7.c b/arch/arm/imx-common/i2c-mxv7.c
index a58087399ce..34f53872e89 100644
--- a/arch/arm/imx-common/i2c-mxv7.c
+++ b/arch/arm/imx-common/i2c-mxv7.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <malloc.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/errno.h>
@@ -69,15 +70,53 @@ static void * const i2c_bases[] = {
 };
 
 /* i2c_index can be from 0 - 2 */
-void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
-		struct i2c_pads_info *p)
+int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
+	      struct i2c_pads_info *p)
 {
+	char *name1, *name2;
+	int ret;
+
 	if (i2c_index >= ARRAY_SIZE(i2c_bases))
-		return;
+		return -EINVAL;
+
+	name1 = malloc(9);
+	name2 = malloc(9);
+	if (!name1 || !name2)
+		return -ENOMEM;
+
+	sprintf(name1, "i2c_sda%d", i2c_index);
+	sprintf(name2, "i2c_scl%d", i2c_index);
+	ret = gpio_request(p->sda.gp, name1);
+	if (ret)
+		goto err_req1;
+
+	ret = gpio_request(p->scl.gp, name2);
+	if (ret)
+		goto err_req2;
+
 	/* Enable i2c clock */
-	enable_i2c_clk(1, i2c_index);
+	ret = enable_i2c_clk(1, i2c_index);
+	if (ret)
+		goto err_clk;
+
 	/* Make sure bus is idle */
-	force_idle_bus(p);
+	ret = force_idle_bus(p);
+	if (ret)
+		goto err_idle;
+
 	bus_i2c_init(i2c_bases[i2c_index], speed, slave_addr,
 			force_idle_bus, p);
+
+	return 0;
+
+err_idle:
+err_clk:
+	gpio_free(p->scl.gp);
+err_req2:
+	gpio_free(p->sda.gp);
+err_req1:
+	free(name1);
+	free(name2);
+
+	return ret;
 }
diff --git a/arch/arm/imx-common/misc.c b/arch/arm/imx-common/misc.c
index dbecf4e4348..12256a38eb9 100644
--- a/arch/arm/imx-common/misc.c
+++ b/arch/arm/imx-common/misc.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/imx-common/regs-common.h>
diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
index 9a02a644bc4..9d3c31ab089 100644
--- a/arch/arm/imx-common/spl.c
+++ b/arch/arm/imx-common/spl.c
@@ -68,7 +68,7 @@ u32 spl_boot_mode(void)
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
 #ifdef CONFIG_SPL_FAT_SUPPORT
-		return MMCSD_MODE_FAT;
+		return MMCSD_MODE_FS;
 #else
 		return MMCSD_MODE_RAW;
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
index 32494372639..d8bf87258b5 100644
--- a/arch/arm/include/asm/arch-am33xx/mux.h
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -36,7 +36,7 @@ struct module_pin_mux {
 
 /* Pad control register offset */
 #define PAD_CTRL_BASE	0x800
-#define OFFSET(x)	(unsigned int) (&((struct pad_signals *) \
+#define OFFSET(x)	(unsigned int) (&((struct pad_signals *)\
 				(PAD_CTRL_BASE))->x)
 
 /*
diff --git a/arch/arm/include/asm/arch-armada-xp/config.h b/arch/arm/include/asm/arch-armada-xp/config.h
new file mode 100644
index 00000000000..00ee775a451
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada-xp/config.h
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file should be included in board config header file.
+ *
+ * It supports common definitions for Armada XP platforms
+ */
+
+#ifndef _ARMADA_XP_CONFIG_H
+#define _ARMADA_XP_CONFIG_H
+
+#include <asm/arch/soc.h>
+
+#define MV88F78X60 /* for the DDR training bin_hdr code */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/*
+ * By default kwbimage.cfg from board specific folder is used
+ * If for some board, different configuration file need to be used,
+ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
+ */
+#ifndef CONFIG_SYS_KWD_CONFIG
+#define	CONFIG_SYS_KWD_CONFIG	$(CONFIG_BOARDDIR)/kwbimage.cfg
+#endif /* CONFIG_SYS_KWD_CONFIG */
+
+/* Add target to build it automatically upon "make" */
+#define CONFIG_BUILD_TARGET	"u-boot.kwb"
+
+/* end of 16M scrubbed by training in bootrom */
+#define CONFIG_SYS_INIT_SP_ADDR		0x00FF0000
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+#define MV_UART_CONSOLE_BASE		MVEBU_UART0_BASE
+
+/*
+ * SPI Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_HARD_SPI			1
+#define CONFIG_KIRKWOOD_SPI		1
+#ifndef CONFIG_ENV_SPI_BUS
+# define CONFIG_ENV_SPI_BUS		0
+#endif
+#ifndef CONFIG_ENV_SPI_CS
+# define CONFIG_ENV_SPI_CS		0
+#endif
+#ifndef CONFIG_ENV_SPI_MAX_HZ
+# define CONFIG_ENV_SPI_MAX_HZ		50000000
+#endif
+#endif
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_MII		/* expose smi ove miiphy interface */
+#define CONFIG_MVNETA		/* Enable Marvell Gbe Controller Driver */
+#define CONFIG_PHYLIB
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_PHY_GIGE		/* GbE speed/duplex detect */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#ifndef CONFIG_SYS_I2C_SOFT
+#define CONFIG_I2C_MVTWSI
+#endif
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#endif /* _ARMADA_XP_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-armada-xp/cpu.h b/arch/arm/include/asm/arch-armada-xp/cpu.h
new file mode 100644
index 00000000000..6b60c21ceb8
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada-xp/cpu.h
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ARMADA_XP_CPU_H
+#define _ARMADA_XP_CPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define MVEBU_REG_PCIE_DEVID		(MVEBU_REG_PCIE_BASE + 0x00)
+#define MVEBU_REG_PCIE_REVID		(MVEBU_REG_PCIE_BASE + 0x08)
+
+enum memory_bank {
+	BANK0,
+	BANK1,
+	BANK2,
+	BANK3
+};
+
+enum cpu_winen {
+	CPU_WIN_DISABLE,
+	CPU_WIN_ENABLE
+};
+
+enum cpu_target {
+	CPU_TARGET_DRAM = 0x0,
+	CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
+	CPU_TARGET_ETH23 = 0x3,
+	CPU_TARGET_PCIE02 = 0x4,
+	CPU_TARGET_ETH01 = 0x7,
+	CPU_TARGET_PCIE13 = 0x8,
+	CPU_TARGET_SASRAM = 0x9,
+	CPU_TARGET_NAND = 0xd,
+};
+
+enum cpu_attrib {
+	CPU_ATTR_SASRAM = 0x01,
+	CPU_ATTR_DRAM_CS0 = 0x0e,
+	CPU_ATTR_DRAM_CS1 = 0x0d,
+	CPU_ATTR_DRAM_CS2 = 0x0b,
+	CPU_ATTR_DRAM_CS3 = 0x07,
+	CPU_ATTR_NANDFLASH = 0x2f,
+	CPU_ATTR_SPIFLASH = 0x1e,
+	CPU_ATTR_BOOTROM = 0x1d,
+	CPU_ATTR_PCIE_IO = 0xe0,
+	CPU_ATTR_PCIE_MEM = 0xe8,
+	CPU_ATTR_DEV_CS0 = 0x3e,
+	CPU_ATTR_DEV_CS1 = 0x3d,
+	CPU_ATTR_DEV_CS2 = 0x3b,
+	CPU_ATTR_DEV_CS3 = 0x37,
+};
+
+/*
+ * Default Device Address MAP BAR values
+ */
+#define DEFADR_PCI_MEM		0x90000000
+#define DEFADR_PCI_IO		0xC0000000
+#define DEFADR_SPIF		0xF4000000
+#define DEFADR_BOOTROM		0xF8000000
+
+struct mbus_win {
+	u32 base;
+	u32 size;
+	u8 target;
+	u8 attr;
+};
+
+/*
+ * System registers
+ * Ref: Datasheet sec:A.28
+ */
+struct mvebu_system_registers {
+	u8 pad1[0x60];
+	u32 rstoutn_mask; /* 0x60 */
+	u32 sys_soft_rst; /* 0x64 */
+};
+
+/*
+ * GPIO Registers
+ * Ref: Datasheet sec:A.19
+ */
+struct kwgpio_registers {
+	u32 dout;
+	u32 oe;
+	u32 blink_en;
+	u32 din_pol;
+	u32 din;
+	u32 irq_cause;
+	u32 irq_mask;
+	u32 irq_level;
+};
+
+/*
+ * functions
+ */
+unsigned int mvebu_sdram_bar(enum memory_bank bank);
+unsigned int mvebu_sdram_bs(enum memory_bank bank);
+void mvebu_sdram_size_adjust(enum memory_bank bank);
+int mvebu_mbus_probe(struct mbus_win windows[], int count);
+#endif /* __ASSEMBLY__ */
+#endif /* _ARMADA_XP_CPU_H */
diff --git a/arch/arm/include/asm/arch-armada-xp/soc.h b/arch/arm/include/asm/arch-armada-xp/soc.h
new file mode 100644
index 00000000000..963e7ac5b76
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada-xp/soc.h
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for the Marvell's Feroceon CPU core.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_ARMADA_XP_H
+#define _ASM_ARCH_ARMADA_XP_H
+
+#define SOC_MV78460_ID		0x7846
+
+/* TCLK Core Clock definition */
+#ifndef CONFIG_SYS_TCLK
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+#endif
+
+/* SOC specific definations */
+#define INTREG_BASE		0xd0000000
+#define INTREG_BASE_ADDR_REG	(INTREG_BASE + 0x20080)
+#define SOC_REGS_PHY_BASE	0xf1000000
+#define MVEBU_REGISTER(x)	(SOC_REGS_PHY_BASE + x)
+
+#define MVEBU_SDRAM_SCRATCH	(MVEBU_REGISTER(0x01504))
+#define MVEBU_SPI_BASE		(MVEBU_REGISTER(0x10600))
+#define MVEBU_TWSI_BASE		(MVEBU_REGISTER(0x11000))
+#define MVEBU_UART0_BASE	(MVEBU_REGISTER(0x12000))
+#define MVEBU_UART1_BASE	(MVEBU_REGISTER(0x12100))
+#define MVEBU_MPP_BASE		(MVEBU_REGISTER(0x18000))
+#define MVEBU_GPIO0_BASE	(MVEBU_REGISTER(0x18100))
+#define MVEBU_GPIO1_BASE	(MVEBU_REGISTER(0x18140))
+#define MVEBU_GPIO2_BASE	(MVEBU_REGISTER(0x18180))
+#define MVEBU_SYSTEM_REG_BASE	(MVEBU_REGISTER(0x18200))
+#define MVEBU_CPU_WIN_BASE	(MVEBU_REGISTER(0x20000))
+#define MVEBU_SDRAM_BASE	(MVEBU_REGISTER(0x20180))
+#define MVEBU_TIMER_BASE	(MVEBU_REGISTER(0x20300))
+#define MVEBU_EGIGA2_BASE	(MVEBU_REGISTER(0x30000))
+#define MVEBU_EGIGA3_BASE	(MVEBU_REGISTER(0x34000))
+#define MVEBU_REG_PCIE_BASE	(MVEBU_REGISTER(0x40000))
+#define MVEBU_EGIGA0_BASE	(MVEBU_REGISTER(0x70000))
+#define MVEBU_EGIGA1_BASE	(MVEBU_REGISTER(0x74000))
+
+#define SDRAM_MAX_CS		4
+#define SDRAM_ADDR_MASK		0xFF000000
+
+/* Armada XP GbE controller has 4 ports */
+#define MAX_MVNETA_DEVS		4
+
+/* Kirkwood CPU memory windows */
+#define MVCPU_WIN_CTRL_DATA	CPU_WIN_CTRL_DATA
+#define MVCPU_WIN_ENABLE	CPU_WIN_ENABLE
+#define MVCPU_WIN_DISABLE	CPU_WIN_DISABLE
+
+#endif /* _ASM_ARCH_ARMADA_XP_H */
diff --git a/arch/arm/include/asm/arch-at91/at91_shdwn.h b/arch/arm/include/asm/arch-at91/at91_shdwn.h
deleted file mode 100644
index 18d9ea690e8..00000000000
--- a/arch/arm/include/asm/arch-at91/at91_shdwn.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Shutdown Controller
- * Based on AT91SAM9XE datasheet
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_SHDWN_H
-#define AT91_SHDWN_H
-
-#ifndef __ASSEMBLY__
-
-struct at91_shdwn {
-	u32	cr;	/* Control Rer.    WO */
-	u32	mr;	/* Mode Register   RW 0x00000003 */
-	u32	sr;	/* Status Register RO 0x00000000 */
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_SHDW_CR_KEY	0xa5000000
-#define AT91_SHDW_CR_SHDW	0x00000001
-
-#define AT91_SHDW_MR_RTTWKEN	0x00010000
-#define AT91_SHDW_MR_CPTWK0	0x000000f0
-#define AT91_SHDW_MR_WKMODE0H2L	0x00000002
-#define AT91_SHDW_MR_WKMODE0L2H	0x00000001
-
-#define AT91_SHDW_SR_RTTWK	0x00010000
-#define AT91_SHDW_SR_WAKEUP0	0x00000001
-
-#endif
diff --git a/arch/arm/include/asm/arch-bcm2835/gpio.h b/arch/arm/include/asm/arch-bcm2835/gpio.h
index 9a49b6e05ef..db42896201b 100644
--- a/arch/arm/include/asm/arch-bcm2835/gpio.h
+++ b/arch/arm/include/asm/arch-bcm2835/gpio.h
@@ -52,4 +52,13 @@ struct bcm2835_gpio_regs {
 	u32 gppudclk[2];
 };
 
+/**
+ * struct bcm2835_gpio_platdata - GPIO platform description
+ *
+ * @base: Base address of GPIO controller
+ */
+struct bcm2835_gpio_platdata {
+	unsigned long base;
+};
+
 #endif /* _BCM2835_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h
index dded857c3ad..61f427d914c 100644
--- a/arch/arm/include/asm/arch-bcm2835/mbox.h
+++ b/arch/arm/include/asm/arch-bcm2835/mbox.h
@@ -119,6 +119,20 @@ struct bcm2835_mbox_tag_hdr {
  * };
  */
 
+#define BCM2835_MBOX_TAG_GET_MAC_ADDRESS	0x00010003
+
+struct bcm2835_mbox_tag_get_mac_address {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct {
+		} req;
+		struct {
+			u8 mac[6];
+			u8 pad[2];
+		} resp;
+	} body;
+};
+
 #define BCM2835_MBOX_TAG_GET_ARM_MEMORY		0x00010005
 
 struct bcm2835_mbox_tag_get_arm_mem {
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index ba717146f51..78aceef17b1 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -29,6 +29,8 @@
 #define EXYNOS4_MIU_BASE		0x10600000
 #define EXYNOS4_ACE_SFR_BASE		0x10830000
 #define EXYNOS4_GPIO_PART2_BASE		0x11000000
+#define EXYNOS4_GPIO_PART2_0		0x11000000 /* GPJ0 */
+#define EXYNOS4_GPIO_PART2_1		0x11000c00 /* GPX0 */
 #define EXYNOS4_GPIO_PART1_BASE		0x11400000
 #define EXYNOS4_FIMD_BASE		0x11C00000
 #define EXYNOS4_MIPI_DSIM_BASE		0x11C80000
@@ -70,7 +72,14 @@
 #define EXYNOS4X12_GPIO_PART4_BASE	0x106E0000
 #define EXYNOS4X12_ACE_SFR_BASE		0x10830000
 #define EXYNOS4X12_GPIO_PART2_BASE	0x11000000
+#define EXYNOS4X12_GPIO_PART2_0		0x11000000
+#define EXYNOS4X12_GPIO_PART2_1		0x11000040 /* GPK0 */
+#define EXYNOS4X12_GPIO_PART2_2		0x11000260 /* GPM0 */
+#define EXYNOS4X12_GPIO_PART2_3		0x11000c00 /* GPX0 */
 #define EXYNOS4X12_GPIO_PART1_BASE	0x11400000
+#define EXYNOS4X12_GPIO_PART1_0		0x11400000 /* GPA0 */
+#define EXYNOS4X12_GPIO_PART1_1		0x11400180 /* GPF0 */
+#define EXYNOS4X12_GPIO_PART1_2		0x11400240 /* GPJ0 */
 #define EXYNOS4X12_FIMD_BASE		0x11C00000
 #define EXYNOS4X12_MIPI_DSIM_BASE	0x11C80000
 #define EXYNOS4X12_USBOTG_BASE		0x12480000
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index 8fb5c2321ec..02287decc2f 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -284,7 +284,10 @@ enum exynos4_gpio_pin {
 	EXYNOS4_GPIO_Y65,
 	EXYNOS4_GPIO_Y66,
 	EXYNOS4_GPIO_Y67,
-	EXYNOS4_GPIO_X00 = 896,		/* 896 0x380 */
+
+	/* GPIO_PART2_1 STARTS */
+	EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */
+	EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0,
 	EXYNOS4_GPIO_X01,
 	EXYNOS4_GPIO_X02,
 	EXYNOS4_GPIO_X03,
@@ -292,7 +295,7 @@ enum exynos4_gpio_pin {
 	EXYNOS4_GPIO_X05,
 	EXYNOS4_GPIO_X06,
 	EXYNOS4_GPIO_X07,
-	EXYNOS4_GPIO_X10,		/* 904 0x388 */
+	EXYNOS4_GPIO_X10,		/* 264 0x108 */
 	EXYNOS4_GPIO_X11,
 	EXYNOS4_GPIO_X12,
 	EXYNOS4_GPIO_X13,
@@ -300,7 +303,7 @@ enum exynos4_gpio_pin {
 	EXYNOS4_GPIO_X15,
 	EXYNOS4_GPIO_X16,
 	EXYNOS4_GPIO_X17,
-	EXYNOS4_GPIO_X20,		/* 912 0x390 */
+	EXYNOS4_GPIO_X20,		/* 272 0x110 */
 	EXYNOS4_GPIO_X21,
 	EXYNOS4_GPIO_X22,
 	EXYNOS4_GPIO_X23,
@@ -308,7 +311,7 @@ enum exynos4_gpio_pin {
 	EXYNOS4_GPIO_X25,
 	EXYNOS4_GPIO_X26,
 	EXYNOS4_GPIO_X27,
-	EXYNOS4_GPIO_X30,		/* 920 0x398 */
+	EXYNOS4_GPIO_X30,		/* 280 0x118 */
 	EXYNOS4_GPIO_X31,
 	EXYNOS4_GPIO_X32,
 	EXYNOS4_GPIO_X33,
@@ -318,8 +321,8 @@ enum exynos4_gpio_pin {
 	EXYNOS4_GPIO_X37,
 
 	/* GPIO_PART3_STARTS */
-	EXYNOS4_GPIO_MAX_PORT_PART_2,	/* 928 0x3A0 */
-	EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2,
+	EXYNOS4_GPIO_MAX_PORT_PART_2_1,	/* 288 0x120 */
+	EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1,
 	EXYNOS4_GPIO_Z1,
 	EXYNOS4_GPIO_Z2,
 	EXYNOS4_GPIO_Z3,
@@ -332,7 +335,7 @@ enum exynos4_gpio_pin {
 };
 
 enum exynos4X12_gpio_pin {
-	/* GPIO_PART1_STARTS */
+	/* EXYNOS4X12_GPIO_PART1_0 starts here */
 	EXYNOS4X12_GPIO_A00,		/* 0 */
 	EXYNOS4X12_GPIO_A01,
 	EXYNOS4X12_GPIO_A02,
@@ -389,7 +392,9 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_D15,
 	EXYNOS4X12_GPIO_D16,
 	EXYNOS4X12_GPIO_D17,
-	EXYNOS4X12_GPIO_F00 = 96,	/* 96 0x60 */
+	EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 */
+	/* EXYNOS4X12_GPIO_PART1_1 starts here */
+	EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0,
 	EXYNOS4X12_GPIO_F01,
 	EXYNOS4X12_GPIO_F02,
 	EXYNOS4X12_GPIO_F03,
@@ -397,7 +402,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_F05,
 	EXYNOS4X12_GPIO_F06,
 	EXYNOS4X12_GPIO_F07,
-	EXYNOS4X12_GPIO_F10,		/* 104 0x68 */
+	EXYNOS4X12_GPIO_F10,		/* 64 0x40 */
 	EXYNOS4X12_GPIO_F11,
 	EXYNOS4X12_GPIO_F12,
 	EXYNOS4X12_GPIO_F13,
@@ -405,7 +410,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_F15,
 	EXYNOS4X12_GPIO_F16,
 	EXYNOS4X12_GPIO_F17,
-	EXYNOS4X12_GPIO_F20,		/* 112 0x70 */
+	EXYNOS4X12_GPIO_F20,		/* 72 0x48 */
 	EXYNOS4X12_GPIO_F21,
 	EXYNOS4X12_GPIO_F22,
 	EXYNOS4X12_GPIO_F23,
@@ -413,7 +418,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_F25,
 	EXYNOS4X12_GPIO_F26,
 	EXYNOS4X12_GPIO_F27,
-	EXYNOS4X12_GPIO_F30,		/* 120 0x78 */
+	EXYNOS4X12_GPIO_F30,		/* 80 0x50 */
 	EXYNOS4X12_GPIO_F31,
 	EXYNOS4X12_GPIO_F32,
 	EXYNOS4X12_GPIO_F33,
@@ -421,7 +426,9 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_F35,
 	EXYNOS4X12_GPIO_F36,
 	EXYNOS4X12_GPIO_F37,
-	EXYNOS4X12_GPIO_J00 = 144,	/* 144 0x90 */
+	EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 */
+	/* EXYNOS4X12_GPIO_PART1_2 starts here */
+	EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1,
 	EXYNOS4X12_GPIO_J01,
 	EXYNOS4X12_GPIO_J02,
 	EXYNOS4X12_GPIO_J03,
@@ -429,7 +436,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_J05,
 	EXYNOS4X12_GPIO_J06,
 	EXYNOS4X12_GPIO_J07,
-	EXYNOS4X12_GPIO_J10,		/* 152 0x98 */
+	EXYNOS4X12_GPIO_J10,		/* 96 0x60 */
 	EXYNOS4X12_GPIO_J11,
 	EXYNOS4X12_GPIO_J12,
 	EXYNOS4X12_GPIO_J13,
@@ -438,9 +445,12 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_J16,
 	EXYNOS4X12_GPIO_J17,
 
-	/* GPIO_PART2_STARTS */
-	EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 160 0xA0 */
-	EXYNOS4X12_GPIO_K00 = 176,	/* 176 0xB0 */
+	/**
+	 * EXYNOS4X12_GPIO_PART2_0 is not used
+	 * EXYNOS4X12_GPIO_PART2_1 starts here
+	 */
+	EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */
+	EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2,
 	EXYNOS4X12_GPIO_K01,
 	EXYNOS4X12_GPIO_K02,
 	EXYNOS4X12_GPIO_K03,
@@ -448,7 +458,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_K05,
 	EXYNOS4X12_GPIO_K06,
 	EXYNOS4X12_GPIO_K07,
-	EXYNOS4X12_GPIO_K10,		/* 184 0xB8 */
+	EXYNOS4X12_GPIO_K10,		/* 112 0x70 */
 	EXYNOS4X12_GPIO_K11,
 	EXYNOS4X12_GPIO_K12,
 	EXYNOS4X12_GPIO_K13,
@@ -456,7 +466,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_K15,
 	EXYNOS4X12_GPIO_K16,
 	EXYNOS4X12_GPIO_K17,
-	EXYNOS4X12_GPIO_K20,		/* 192 0xC0 */
+	EXYNOS4X12_GPIO_K20,		/* 120 0x78 */
 	EXYNOS4X12_GPIO_K21,
 	EXYNOS4X12_GPIO_K22,
 	EXYNOS4X12_GPIO_K23,
@@ -464,7 +474,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_K25,
 	EXYNOS4X12_GPIO_K26,
 	EXYNOS4X12_GPIO_K27,
-	EXYNOS4X12_GPIO_K30,		/* 200 0xC8 */
+	EXYNOS4X12_GPIO_K30,		/* 128 0x80 */
 	EXYNOS4X12_GPIO_K31,
 	EXYNOS4X12_GPIO_K32,
 	EXYNOS4X12_GPIO_K33,
@@ -472,7 +482,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_K35,
 	EXYNOS4X12_GPIO_K36,
 	EXYNOS4X12_GPIO_K37,
-	EXYNOS4X12_GPIO_L00,		/* 208 0xD0 */
+	EXYNOS4X12_GPIO_L00,		/* 136 0x88 */
 	EXYNOS4X12_GPIO_L01,
 	EXYNOS4X12_GPIO_L02,
 	EXYNOS4X12_GPIO_L03,
@@ -480,7 +490,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_L05,
 	EXYNOS4X12_GPIO_L06,
 	EXYNOS4X12_GPIO_L07,
-	EXYNOS4X12_GPIO_L10,		/* 216 0xD8 */
+	EXYNOS4X12_GPIO_L10,		/* 144 0x90 */
 	EXYNOS4X12_GPIO_L11,
 	EXYNOS4X12_GPIO_L12,
 	EXYNOS4X12_GPIO_L13,
@@ -488,7 +498,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_L15,
 	EXYNOS4X12_GPIO_L16,
 	EXYNOS4X12_GPIO_L17,
-	EXYNOS4X12_GPIO_L20,		/* 224 0xE0 */
+	EXYNOS4X12_GPIO_L20,		/* 152 0x98 */
 	EXYNOS4X12_GPIO_L21,
 	EXYNOS4X12_GPIO_L22,
 	EXYNOS4X12_GPIO_L23,
@@ -496,7 +506,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_L25,
 	EXYNOS4X12_GPIO_L26,
 	EXYNOS4X12_GPIO_L27,
-	EXYNOS4X12_GPIO_Y00,		/* 232 0xE8 */
+	EXYNOS4X12_GPIO_Y00,		/* 160 0xa0 */
 	EXYNOS4X12_GPIO_Y01,
 	EXYNOS4X12_GPIO_Y02,
 	EXYNOS4X12_GPIO_Y03,
@@ -504,7 +514,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_Y05,
 	EXYNOS4X12_GPIO_Y06,
 	EXYNOS4X12_GPIO_Y07,
-	EXYNOS4X12_GPIO_Y10,		/* 240 0xF0 */
+	EXYNOS4X12_GPIO_Y10,		/* 168 0xa8 */
 	EXYNOS4X12_GPIO_Y11,
 	EXYNOS4X12_GPIO_Y12,
 	EXYNOS4X12_GPIO_Y13,
@@ -512,7 +522,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_Y15,
 	EXYNOS4X12_GPIO_Y16,
 	EXYNOS4X12_GPIO_Y17,
-	EXYNOS4X12_GPIO_Y20,		/* 248 0xF8 */
+	EXYNOS4X12_GPIO_Y20,		/* 176 0xb0 */
 	EXYNOS4X12_GPIO_Y21,
 	EXYNOS4X12_GPIO_Y22,
 	EXYNOS4X12_GPIO_Y23,
@@ -520,7 +530,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_Y25,
 	EXYNOS4X12_GPIO_Y26,
 	EXYNOS4X12_GPIO_Y27,
-	EXYNOS4X12_GPIO_Y30,		/* 256 0x100 */
+	EXYNOS4X12_GPIO_Y30,		/* 184 0xb8 */
 	EXYNOS4X12_GPIO_Y31,
 	EXYNOS4X12_GPIO_Y32,
 	EXYNOS4X12_GPIO_Y33,
@@ -528,7 +538,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_Y35,
 	EXYNOS4X12_GPIO_Y36,
 	EXYNOS4X12_GPIO_Y37,
-	EXYNOS4X12_GPIO_Y40,		/* 264 0x108 */
+	EXYNOS4X12_GPIO_Y40,		/* 192 0xc0 */
 	EXYNOS4X12_GPIO_Y41,
 	EXYNOS4X12_GPIO_Y42,
 	EXYNOS4X12_GPIO_Y43,
@@ -536,7 +546,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_Y45,
 	EXYNOS4X12_GPIO_Y46,
 	EXYNOS4X12_GPIO_Y47,
-	EXYNOS4X12_GPIO_Y50,		/* 272 0x110 */
+	EXYNOS4X12_GPIO_Y50,		/* 200 0xc8 */
 	EXYNOS4X12_GPIO_Y51,
 	EXYNOS4X12_GPIO_Y52,
 	EXYNOS4X12_GPIO_Y53,
@@ -544,7 +554,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_Y55,
 	EXYNOS4X12_GPIO_Y56,
 	EXYNOS4X12_GPIO_Y57,
-	EXYNOS4X12_GPIO_Y60,		/* 280 0x118 */
+	EXYNOS4X12_GPIO_Y60,		/* 208 0xd0 */
 	EXYNOS4X12_GPIO_Y61,
 	EXYNOS4X12_GPIO_Y62,
 	EXYNOS4X12_GPIO_Y63,
@@ -552,7 +562,9 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_Y65,
 	EXYNOS4X12_GPIO_Y66,
 	EXYNOS4X12_GPIO_Y67,
-	EXYNOS4X12_GPIO_M00 = 312,	/* 312 0xF0 */
+	EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 */
+	/* EXYNOS4X12_GPIO_PART2_2 starts here */
+	EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1,
 	EXYNOS4X12_GPIO_M01,
 	EXYNOS4X12_GPIO_M02,
 	EXYNOS4X12_GPIO_M03,
@@ -560,7 +572,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_M05,
 	EXYNOS4X12_GPIO_M06,
 	EXYNOS4X12_GPIO_M07,
-	EXYNOS4X12_GPIO_M10,		/* 320 0xF8 */
+	EXYNOS4X12_GPIO_M10,		/* 224 0xe0 */
 	EXYNOS4X12_GPIO_M11,
 	EXYNOS4X12_GPIO_M12,
 	EXYNOS4X12_GPIO_M13,
@@ -568,7 +580,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_M15,
 	EXYNOS4X12_GPIO_M16,
 	EXYNOS4X12_GPIO_M17,
-	EXYNOS4X12_GPIO_M20,		/* 328 0x100 */
+	EXYNOS4X12_GPIO_M20,		/* 232 0xe8 */
 	EXYNOS4X12_GPIO_M21,
 	EXYNOS4X12_GPIO_M22,
 	EXYNOS4X12_GPIO_M23,
@@ -576,7 +588,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_M25,
 	EXYNOS4X12_GPIO_M26,
 	EXYNOS4X12_GPIO_M27,
-	EXYNOS4X12_GPIO_M30,		/* 336 0x108 */
+	EXYNOS4X12_GPIO_M30,		/* 240 0xf0 */
 	EXYNOS4X12_GPIO_M31,
 	EXYNOS4X12_GPIO_M32,
 	EXYNOS4X12_GPIO_M33,
@@ -584,7 +596,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_M35,
 	EXYNOS4X12_GPIO_M36,
 	EXYNOS4X12_GPIO_M37,
-	EXYNOS4X12_GPIO_M40,		/* 344 0x110 */
+	EXYNOS4X12_GPIO_M40,		/* 248 0xf8 */
 	EXYNOS4X12_GPIO_M41,
 	EXYNOS4X12_GPIO_M42,
 	EXYNOS4X12_GPIO_M43,
@@ -592,7 +604,9 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_M45,
 	EXYNOS4X12_GPIO_M46,
 	EXYNOS4X12_GPIO_M47,
-	EXYNOS4X12_GPIO_X00 = 928,	/* 928 0x3A0 */
+	EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 */
+	/* EXYNOS4X12_GPIO_PART2_3 starts here */
+	EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2,
 	EXYNOS4X12_GPIO_X01,
 	EXYNOS4X12_GPIO_X02,
 	EXYNOS4X12_GPIO_X03,
@@ -600,7 +614,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_X05,
 	EXYNOS4X12_GPIO_X06,
 	EXYNOS4X12_GPIO_X07,
-	EXYNOS4X12_GPIO_X10,		/* 936 0x3A8 */
+	EXYNOS4X12_GPIO_X10,		/* 264 0x108 */
 	EXYNOS4X12_GPIO_X11,
 	EXYNOS4X12_GPIO_X12,
 	EXYNOS4X12_GPIO_X13,
@@ -608,7 +622,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_X15,
 	EXYNOS4X12_GPIO_X16,
 	EXYNOS4X12_GPIO_X17,
-	EXYNOS4X12_GPIO_X20,		/* 944 0x3B0 */
+	EXYNOS4X12_GPIO_X20,		/* 272 0x110 */
 	EXYNOS4X12_GPIO_X21,
 	EXYNOS4X12_GPIO_X22,
 	EXYNOS4X12_GPIO_X23,
@@ -616,7 +630,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_X25,
 	EXYNOS4X12_GPIO_X26,
 	EXYNOS4X12_GPIO_X27,
-	EXYNOS4X12_GPIO_X30,		/* 952 0x3B8 */
+	EXYNOS4X12_GPIO_X30,		/* 280 0x118 */
 	EXYNOS4X12_GPIO_X31,
 	EXYNOS4X12_GPIO_X32,
 	EXYNOS4X12_GPIO_X33,
@@ -625,9 +639,9 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_X36,
 	EXYNOS4X12_GPIO_X37,
 
-	/* GPIO_PART3_STARTS */
-	EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 960 0x3C0 */
-	EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2,
+	/* EXYNOS4X12_GPIO_PART3 starts here */
+	EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */
+	EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3,
 	EXYNOS4X12_GPIO_Z1,
 	EXYNOS4X12_GPIO_Z2,
 	EXYNOS4X12_GPIO_Z3,
@@ -636,8 +650,8 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_Z6,
 	EXYNOS4X12_GPIO_Z7,
 
-	/* GPIO_PART4_STARTS */
-	EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 968 0x3C8 */
+	/* EXYNOS4X12_GPIO_PART4 starts here */
+	EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */
 	EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3,
 	EXYNOS4X12_GPIO_V01,
 	EXYNOS4X12_GPIO_V02,
@@ -646,7 +660,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_V05,
 	EXYNOS4X12_GPIO_V06,
 	EXYNOS4X12_GPIO_V07,
-	EXYNOS4X12_GPIO_V10,		/* 976 0x3D0 */
+	EXYNOS4X12_GPIO_V10,		/* 304 0x130 */
 	EXYNOS4X12_GPIO_V11,
 	EXYNOS4X12_GPIO_V12,
 	EXYNOS4X12_GPIO_V13,
@@ -654,7 +668,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_V15,
 	EXYNOS4X12_GPIO_V16,
 	EXYNOS4X12_GPIO_V17,
-	EXYNOS4X12_GPIO_V20 = 992,	/* 992 0x3E0 */
+	EXYNOS4X12_GPIO_V20,		/* 312 0x138 */
 	EXYNOS4X12_GPIO_V21,
 	EXYNOS4X12_GPIO_V22,
 	EXYNOS4X12_GPIO_V23,
@@ -662,7 +676,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_V25,
 	EXYNOS4X12_GPIO_V26,
 	EXYNOS4X12_GPIO_V27,
-	EXYNOS4X12_GPIO_V30 = 1000,	/* 1000 0x3E8 */
+	EXYNOS4X12_GPIO_V30,		/* 320 0x140 */
 	EXYNOS4X12_GPIO_V31,
 	EXYNOS4X12_GPIO_V32,
 	EXYNOS4X12_GPIO_V33,
@@ -670,7 +684,7 @@ enum exynos4X12_gpio_pin {
 	EXYNOS4X12_GPIO_V35,
 	EXYNOS4X12_GPIO_V36,
 	EXYNOS4X12_GPIO_V37,
-	EXYNOS4X12_GPIO_V40 = 1016,	/* 1016 0x3F8 */
+	EXYNOS4X12_GPIO_V40,		/* 328 0x148 */
 	EXYNOS4X12_GPIO_V41,
 	EXYNOS4X12_GPIO_V42,
 	EXYNOS4X12_GPIO_V43,
@@ -1339,17 +1353,22 @@ struct gpio_info {
 	unsigned int max_gpio;	/* Maximum GPIO in this part */
 };
 
-#define EXYNOS4_GPIO_NUM_PARTS	3
+#define EXYNOS4_GPIO_NUM_PARTS	4
 static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = {
 	{ EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
-	{ EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 },
+	{ EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 },
+	{ EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 },
 	{ EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT },
 };
 
-#define EXYNOS4X12_GPIO_NUM_PARTS	4
+#define EXYNOS4X12_GPIO_NUM_PARTS	8
 static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = {
-	{ EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 },
-	{ EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 },
+	{ EXYNOS4X12_GPIO_PART1_0, EXYNOS4X12_GPIO_MAX_PORT_PART_1_0 },
+	{ EXYNOS4X12_GPIO_PART1_1, EXYNOS4X12_GPIO_MAX_PORT_PART_1_1 },
+	{ EXYNOS4X12_GPIO_PART1_2, EXYNOS4X12_GPIO_MAX_PORT_PART_1_2 },
+	{ EXYNOS4X12_GPIO_PART2_1, EXYNOS4X12_GPIO_MAX_PORT_PART_2_1 },
+	{ EXYNOS4X12_GPIO_PART2_2, EXYNOS4X12_GPIO_MAX_PORT_PART_2_2 },
+	{ EXYNOS4X12_GPIO_PART2_3, EXYNOS4X12_GPIO_MAX_PORT_PART_2_3 },
 	{ EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 },
 	{ EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT },
 };
@@ -1504,12 +1523,7 @@ static const struct gpio_name_num_table exynos5420_gpio_table[] = {
 void gpio_cfg_pin(int gpio, int cfg);
 void gpio_set_pull(int gpio, int mode);
 void gpio_set_drv(int gpio, int mode);
-int gpio_direction_input(unsigned gpio);
-int gpio_direction_output(unsigned gpio, int value);
-int gpio_set_value(unsigned gpio, int value);
-int gpio_get_value(unsigned gpio);
 void gpio_set_rate(int gpio, int mode);
-struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio);
 int s5p_gpio_get_pin(unsigned gpio);
 #endif
 
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h
index df33a78a103..d013b830ed5 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2e.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h
@@ -25,27 +25,28 @@ enum ext_clk_e {
 
 extern unsigned int external_clk[ext_clk_count];
 
-enum clk_e {
-	core_pll_clk,
-	pass_pll_clk,
-	ddr3_pll_clk,
-	sys_clk0_clk,
-	sys_clk0_1_clk,
-	sys_clk0_2_clk,
-	sys_clk0_3_clk,
-	sys_clk0_4_clk,
-	sys_clk0_6_clk,
-	sys_clk0_8_clk,
-	sys_clk0_12_clk,
-	sys_clk0_24_clk,
-	sys_clk1_clk,
-	sys_clk1_3_clk,
-	sys_clk1_4_clk,
-	sys_clk1_6_clk,
-	sys_clk1_12_clk,
-	sys_clk2_clk,
-	sys_clk3_clk
-};
+#define CLK_LIST(CLK)\
+	CLK(0, core_pll_clk)\
+	CLK(1, pass_pll_clk)\
+	CLK(2, ddr3_pll_clk)\
+	CLK(3, sys_clk0_clk)\
+	CLK(4, sys_clk0_1_clk)\
+	CLK(5, sys_clk0_2_clk)\
+	CLK(6, sys_clk0_3_clk)\
+	CLK(7, sys_clk0_4_clk)\
+	CLK(8, sys_clk0_6_clk)\
+	CLK(9, sys_clk0_8_clk)\
+	CLK(10, sys_clk0_12_clk)\
+	CLK(11, sys_clk0_24_clk)\
+	CLK(12, sys_clk1_clk)\
+	CLK(13, sys_clk1_3_clk)\
+	CLK(14, sys_clk1_4_clk)\
+	CLK(15, sys_clk1_6_clk)\
+	CLK(16, sys_clk1_12_clk)\
+	CLK(17, sys_clk2_clk)\
+	CLK(18, sys_clk3_clk)
+
+#define PLLSET_CMD_LIST	"<pa|ddr3>"
 
 #define KS2_CLK1_6	sys_clk0_6_clk
 
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
index bdb869bed41..f28d5f0c4e9 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
@@ -28,29 +28,30 @@ enum ext_clk_e {
 
 extern unsigned int external_clk[ext_clk_count];
 
-enum clk_e {
-	core_pll_clk,
-	pass_pll_clk,
-	tetris_pll_clk,
-	ddr3a_pll_clk,
-	ddr3b_pll_clk,
-	sys_clk0_clk,
-	sys_clk0_1_clk,
-	sys_clk0_2_clk,
-	sys_clk0_3_clk,
-	sys_clk0_4_clk,
-	sys_clk0_6_clk,
-	sys_clk0_8_clk,
-	sys_clk0_12_clk,
-	sys_clk0_24_clk,
-	sys_clk1_clk,
-	sys_clk1_3_clk,
-	sys_clk1_4_clk,
-	sys_clk1_6_clk,
-	sys_clk1_12_clk,
-	sys_clk2_clk,
-	sys_clk3_clk
-};
+#define CLK_LIST(CLK)\
+	CLK(0, core_pll_clk)\
+	CLK(1, pass_pll_clk)\
+	CLK(2, tetris_pll_clk)\
+	CLK(3, ddr3a_pll_clk)\
+	CLK(4, ddr3b_pll_clk)\
+	CLK(5, sys_clk0_clk)\
+	CLK(6, sys_clk0_1_clk)\
+	CLK(7, sys_clk0_2_clk)\
+	CLK(8, sys_clk0_3_clk)\
+	CLK(9, sys_clk0_4_clk)\
+	CLK(10, sys_clk0_6_clk)\
+	CLK(11, sys_clk0_8_clk)\
+	CLK(12, sys_clk0_12_clk)\
+	CLK(13, sys_clk0_24_clk)\
+	CLK(14, sys_clk1_clk)\
+	CLK(15, sys_clk1_3_clk)\
+	CLK(16, sys_clk1_4_clk)\
+	CLK(17, sys_clk1_6_clk)\
+	CLK(18, sys_clk1_12_clk)\
+	CLK(19, sys_clk2_clk)\
+	CLK(20, sys_clk3_clk)
+
+#define PLLSET_CMD_LIST		"<pa|arm|ddr3a|ddr3b>"
 
 #define KS2_CLK1_6 sys_clk0_6_clk
 
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2l.h b/arch/arm/include/asm/arch-keystone/clock-k2l.h
new file mode 100644
index 00000000000..bb9a5c4dcf3
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/clock-k2l.h
@@ -0,0 +1,95 @@
+/*
+ * K2L: Clock management APIs
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_K2L_H
+#define __ASM_ARCH_CLOCK_K2L_H
+
+enum ext_clk_e {
+	sys_clk,
+	alt_core_clk,
+	pa_clk,
+	tetris_clk,
+	ddr3_clk,
+	pcie_clk,
+	sgmii_clk,
+	usb_clk,
+	rp1_clk,
+	ext_clk_count /* number of external clocks */
+};
+
+extern unsigned int external_clk[ext_clk_count];
+
+#define CLK_LIST(CLK)\
+	CLK(0, core_pll_clk)\
+	CLK(1, pass_pll_clk)\
+	CLK(2, tetris_pll_clk)\
+	CLK(3, ddr3_pll_clk)\
+	CLK(4, sys_clk0_clk)\
+	CLK(5, sys_clk0_1_clk)\
+	CLK(6, sys_clk0_2_clk)\
+	CLK(7, sys_clk0_3_clk)\
+	CLK(8, sys_clk0_4_clk)\
+	CLK(9, sys_clk0_6_clk)\
+	CLK(10, sys_clk0_8_clk)\
+	CLK(11, sys_clk0_12_clk)\
+	CLK(12, sys_clk0_24_clk)\
+	CLK(13, sys_clk1_clk)\
+	CLK(14, sys_clk1_3_clk)\
+	CLK(15, sys_clk1_4_clk)\
+	CLK(16, sys_clk1_6_clk)\
+	CLK(17, sys_clk1_12_clk)\
+	CLK(18, sys_clk2_clk)\
+	CLK(19, sys_clk3_clk)\
+
+#define PLLSET_CMD_LIST	"<pa|arm|ddr3>"
+
+#define KS2_CLK1_6	sys_clk0_6_clk
+
+/* PLL identifiers */
+enum pll_type_e {
+	CORE_PLL,
+	PASS_PLL,
+	TETRIS_PLL,
+	DDR3_PLL,
+};
+
+enum {
+	SPD800,
+	SPD1000,
+	SPD1200,
+	SPD1350,
+	SPD1400,
+	SPD_RSV
+};
+
+#define CORE_PLL_799	{CORE_PLL, 13, 1, 2}
+#define CORE_PLL_983	{CORE_PLL, 16, 1, 2}
+#define CORE_PLL_1000	{CORE_PLL, 114, 7, 2}
+#define CORE_PLL_1167	{CORE_PLL, 19, 1, 2}
+#define CORE_PLL_1198	{CORE_PLL, 39, 2, 2}
+#define CORE_PLL_1228	{CORE_PLL, 20, 1, 2}
+#define PASS_PLL_1228	{PASS_PLL, 20, 1, 2}
+#define PASS_PLL_983	{PASS_PLL, 16, 1, 2}
+#define PASS_PLL_1050	{PASS_PLL, 205, 12, 2}
+#define TETRIS_PLL_491	{TETRIS_PLL, 8, 1, 2}
+#define TETRIS_PLL_737	{TETRIS_PLL, 12, 1, 2}
+#define TETRIS_PLL_799	{TETRIS_PLL, 13, 1, 2}
+#define TETRIS_PLL_983	{TETRIS_PLL, 16, 1, 2}
+#define TETRIS_PLL_1000	{TETRIS_PLL, 114, 7, 2}
+#define TETRIS_PLL_1167	{TETRIS_PLL, 19, 1, 2}
+#define TETRIS_PLL_1198	{TETRIS_PLL, 39, 2, 2}
+#define TETRIS_PLL_1228	{TETRIS_PLL, 20, 1, 2}
+#define TETRIS_PLL_1352	{TETRIS_PLL, 22, 1, 2}
+#define TETRIS_PLL_1401	{TETRIS_PLL, 114, 5, 2}
+#define DDR3_PLL_200	{DDR3_PLL, 4, 1, 2}
+#define DDR3_PLL_400	{DDR3_PLL, 16, 1, 4}
+#define DDR3_PLL_800	{DDR3_PLL, 16, 1, 2}
+#define DDR3_PLL_333	{DDR3_PLL, 20, 1, 6}
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h
index dae000e43ae..9f6cfb265f4 100644
--- a/arch/arm/include/asm/arch-keystone/clock.h
+++ b/arch/arm/include/asm/arch-keystone/clock.h
@@ -20,10 +20,22 @@
 #include <asm/arch/clock-k2e.h>
 #endif
 
+#ifdef CONFIG_SOC_K2L
+#include <asm/arch/clock-k2l.h>
+#endif
+
 #define MAIN_PLL CORE_PLL
 
 #include <asm/types.h>
 
+#define GENERATE_ENUM(NUM, ENUM) ENUM = NUM,
+#define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n"
+#define CLOCK_INDEXES_LIST	CLK_LIST(GENERATE_INDX_STR)
+
+enum clk_e {
+	CLK_LIST(GENERATE_ENUM)
+};
+
 struct keystone_pll_regs {
 	u32 reg0;
 	u32 reg1;
@@ -46,6 +58,7 @@ void init_pll(const struct pll_init_data *data);
 unsigned long clk_get_rate(unsigned int clk);
 unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
 int clk_set_rate(unsigned int clk, unsigned long hz);
+void pass_pll_pa_clk_enable(void);
 int get_max_dev_speed(void);
 int get_max_arm_speed(void);
 
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h
index 6bf35d35436..b044d6f18ff 100644
--- a/arch/arm/include/asm/arch-keystone/ddr3.h
+++ b/arch/arm/include/asm/arch-keystone/ddr3.h
@@ -49,8 +49,14 @@ struct ddr3_emif_config {
 };
 
 void ddr3_init(void);
+int ddr3_get_size(void);
 void ddr3_reset_ddrphy(void);
+void ddr3_init_ecc(u32 base);
+void ddr3_disable_ecc(u32 base);
+void ddr3_check_ecc_int(u32 base);
+int ddr3_ecc_support_rmw(u32 base);
 void ddr3_err_reset_workaround(void);
+void ddr3_enable_ecc(u32 base, int test);
 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
 
diff --git a/arch/arm/include/asm/arch-keystone/emac_defs.h b/arch/arm/include/asm/arch-keystone/emac_defs.h
deleted file mode 100644
index 9cd89258199..00000000000
--- a/arch/arm/include/asm/arch-keystone/emac_defs.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * emac definitions for keystone2 devices
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef _EMAC_DEFS_H_
-#define _EMAC_DEFS_H_
-
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-#define EMAC_EMACSL_BASE_ADDR           (KS2_PASS_BASE + 0x00090900)
-#define EMAC_MDIO_BASE_ADDR             (KS2_PASS_BASE + 0x00090300)
-#define EMAC_SGMII_BASE_ADDR            (KS2_PASS_BASE + 0x00090100)
-
-#define KEYSTONE2_EMAC_GIG_ENABLE
-
-#define MAC_ID_BASE_ADDR                (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
-
-#ifdef CONFIG_SOC_K2HK
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ              (clk_get_rate(pass_pll_clk))
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ            1000000		/* 1.0 MHz */
-#endif
-
-/* MII Status Register */
-#define MII_STATUS_REG                  1
-#define MII_STATUS_LINK_MASK            (0x4)
-
-/* Marvell 88E1111 PHY ID */
-#define PHY_MARVELL_88E1111             (0x01410cc0)
-
-#define MDIO_CONTROL_IDLE               (0x80000000)
-#define MDIO_CONTROL_ENABLE             (0x40000000)
-#define MDIO_CONTROL_FAULT_ENABLE       (0x40000)
-#define MDIO_CONTROL_FAULT              (0x80000)
-#define MDIO_USERACCESS0_GO             (0x80000000)
-#define MDIO_USERACCESS0_WRITE_READ     (0x0)
-#define MDIO_USERACCESS0_WRITE_WRITE    (0x40000000)
-#define MDIO_USERACCESS0_ACK            (0x20000000)
-
-#define EMAC_MACCONTROL_MIIEN_ENABLE       (0x20)
-#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE  (0x1)
-#define EMAC_MACCONTROL_GIGABIT_ENABLE     (1 << 7)
-#define EMAC_MACCONTROL_GIGFORCE           (1 << 17)
-#define EMAC_MACCONTROL_RMIISPEED_100      (1 << 15)
-
-#define EMAC_MIN_ETHERNET_PKT_SIZE         60
-
-struct mac_sl_cfg {
-	u_int32_t max_rx_len;	/* Maximum receive packet length. */
-	u_int32_t ctl;		/* Control bitfield */
-};
-
-/*
- * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t
- */
-#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES       (1 << 24)
-#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES         (1 << 23)
-#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES         (1 << 22)
-#define GMACSL_RX_ENABLE_EXT_CTL                  (1 << 18)
-#define GMACSL_RX_ENABLE_GIG_FORCE                (1 << 17)
-#define GMACSL_RX_ENABLE_IFCTL_B                  (1 << 16)
-#define GMACSL_RX_ENABLE_IFCTL_A                  (1 << 15)
-#define GMACSL_RX_ENABLE_CMD_IDLE                 (1 << 11)
-#define GMACSL_TX_ENABLE_SHORT_GAP                (1 << 10)
-#define GMACSL_ENABLE_GIG_MODE                    (1 <<  7)
-#define GMACSL_TX_ENABLE_PACE                     (1 <<  6)
-#define GMACSL_ENABLE                             (1 <<  5)
-#define GMACSL_TX_ENABLE_FLOW_CTL                 (1 <<  4)
-#define GMACSL_RX_ENABLE_FLOW_CTL                 (1 <<  3)
-#define GMACSL_ENABLE_LOOPBACK                    (1 <<  1)
-#define GMACSL_ENABLE_FULL_DUPLEX                 (1 <<  0)
-
-/*
- * DEFINTITION: function return values
- */
-#define GMACSL_RET_OK                        0
-#define GMACSL_RET_INVALID_PORT             -1
-#define GMACSL_RET_WARN_RESET_INCOMPLETE    -2
-#define GMACSL_RET_WARN_MAXLEN_TOO_BIG      -3
-#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
-
-/* Register offsets */
-#define CPGMACSL_REG_ID         0x00
-#define CPGMACSL_REG_CTL        0x04
-#define CPGMACSL_REG_STATUS     0x08
-#define CPGMACSL_REG_RESET      0x0c
-#define CPGMACSL_REG_MAXLEN     0x10
-#define CPGMACSL_REG_BOFF       0x14
-#define CPGMACSL_REG_RX_PAUSE   0x18
-#define CPGMACSL_REG_TX_PAURSE  0x1c
-#define CPGMACSL_REG_EM_CTL     0x20
-#define CPGMACSL_REG_PRI        0x24
-
-/* Soft reset register values */
-#define CPGMAC_REG_RESET_VAL_RESET_MASK      (1 << 0)
-#define CPGMAC_REG_RESET_VAL_RESET           (1 << 0)
-
-/* Maxlen register values */
-#define CPGMAC_REG_MAXLEN_LEN                0x3fff
-
-/* Control bitfields */
-#define CPSW_CTL_P2_PASS_PRI_TAGGED     (1 << 5)
-#define CPSW_CTL_P1_PASS_PRI_TAGGED     (1 << 4)
-#define CPSW_CTL_P0_PASS_PRI_TAGGED     (1 << 3)
-#define CPSW_CTL_P0_ENABLE              (1 << 2)
-#define CPSW_CTL_VLAN_AWARE             (1 << 1)
-#define CPSW_CTL_FIFO_LOOPBACK          (1 << 0)
-
-#define DEVICE_CPSW_NUM_PORTS       5                    /* 5 switch ports */
-#define DEVICE_CPSW_BASE            (0x02090800)
-#define target_get_switch_ctl()     CPSW_CTL_P0_ENABLE   /* Enable port 0 */
-#define SWITCH_MAX_PKT_SIZE         9000
-
-/* Register offsets */
-#define CPSW_REG_CTL                0x004
-#define CPSW_REG_STAT_PORT_EN       0x00c
-#define CPSW_REG_MAXLEN             0x040
-#define CPSW_REG_ALE_CONTROL        0x608
-#define CPSW_REG_ALE_PORTCTL(x)     (0x640 + (x)*4)
-
-/* Register values */
-#define CPSW_REG_VAL_STAT_ENABLE_ALL             0xf
-#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE    ((u_int32_t)0xc0000000)
-#define CPSW_REG_VAL_ALE_CTL_BYPASS              ((u_int32_t)0x00000010)
-#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE        0x3
-
-#define SGMII_REG_STATUS_LOCK           BIT(4)
-#define SGMII_REG_STATUS_LINK           BIT(0)
-#define SGMII_REG_STATUS_AUTONEG        BIT(2)
-#define SGMII_REG_CONTROL_AUTONEG       BIT(0)
-#define SGMII_REG_CONTROL_MASTER        BIT(5)
-#define	SGMII_REG_MR_ADV_ENABLE         BIT(0)
-#define	SGMII_REG_MR_ADV_LINK           BIT(15)
-#define	SGMII_REG_MR_ADV_FULL_DUPLEX    BIT(12)
-#define SGMII_REG_MR_ADV_GIG_MODE       BIT(11)
-
-#define SGMII_LINK_MAC_MAC_AUTONEG      0
-#define SGMII_LINK_MAC_PHY              1
-#define SGMII_LINK_MAC_MAC_FORCED       2
-#define SGMII_LINK_MAC_FIBER            3
-#define SGMII_LINK_MAC_PHY_FORCED       4
-
-#define TARGET_SGMII_BASE              KS2_PASS_BASE + 0x00090100
-#define TARGET_SGMII_BASE_ADDRESSES    {KS2_PASS_BASE + 0x00090100, \
-					KS2_PASS_BASE + 0x00090200, \
-					KS2_PASS_BASE + 0x00090400, \
-					KS2_PASS_BASE + 0x00090500}
-
-#define SGMII_OFFSET(x)	((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
-
-/*
- * SGMII registers
- */
-#define SGMII_IDVER_REG(x)    (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x000)
-#define SGMII_SRESET_REG(x)   (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x004)
-#define SGMII_CTL_REG(x)      (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x010)
-#define SGMII_STATUS_REG(x)   (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x014)
-#define SGMII_MRADV_REG(x)    (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x018)
-#define SGMII_LPADV_REG(x)    (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x020)
-#define SGMII_TXCFG_REG(x)    (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x030)
-#define SGMII_RXCFG_REG(x)    (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x034)
-#define SGMII_AUXCFG_REG(x)   (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x038)
-
-#define DEVICE_EMACSL_BASE(x)      (KS2_PASS_BASE + 0x00090900 + (x) * 0x040)
-#define DEVICE_N_GMACSL_PORTS           4
-#define DEVICE_EMACSL_RESET_POLL_COUNT  100
-
-#define DEVICE_PSTREAM_CFG_REG_ADDR                 (KS2_PASS_BASE + 0x604)
-
-#ifdef CONFIG_SOC_K2HK
-#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI      0x06060606
-#endif
-
-#define hw_config_streaming_switch() \
-	writel(DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI,\
-	       DEVICE_PSTREAM_CFG_REG_ADDR);
-
-/* EMAC MDIO Registers Structure */
-struct mdio_regs {
-	dv_reg		version;
-	dv_reg		control;
-	dv_reg		alive;
-	dv_reg		link;
-	dv_reg		linkintraw;
-	dv_reg		linkintmasked;
-	u_int8_t	rsvd0[8];
-	dv_reg		userintraw;
-	dv_reg		userintmasked;
-	dv_reg		userintmaskset;
-	dv_reg		userintmaskclear;
-	u_int8_t	rsvd1[80];
-	dv_reg		useraccess0;
-	dv_reg		userphysel0;
-	dv_reg		useraccess1;
-	dv_reg		userphysel1;
-};
-
-/* Ethernet MAC Registers Structure */
-struct emac_regs {
-	dv_reg		idver;
-	dv_reg		maccontrol;
-	dv_reg		macstatus;
-	dv_reg		soft_reset;
-	dv_reg		rx_maxlen;
-	u32		rsvd0;
-	dv_reg		rx_pause;
-	dv_reg		tx_pause;
-	dv_reg		emcontrol;
-	dv_reg		pri_map;
-	u32		rsvd1[6];
-};
-
-#define SGMII_ACCESS(port, reg) \
-	*((volatile unsigned int *)(sgmiis[port] + reg))
-
-struct eth_priv_t {
-	char	int_name[32];
-	int	rx_flow;
-	int	phy_addr;
-	int	slave_port;
-	int	sgmii_link_type;
-};
-
-extern struct eth_priv_t eth_priv_cfg[];
-
-int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
-void sgmii_serdes_setup_156p25mhz(void);
-void sgmii_serdes_shutdown(void);
-
-#endif  /* _EMAC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h
index 62172a4b84d..9512756619b 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2e.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h
@@ -34,11 +34,34 @@
 #define KS2_LPSC_PCIE_1			27
 #define KS2_LPSC_XGE			50
 
+/* MSMC */
+#define KS2_MSMC_SEGMENT_PCIE1		13
+
 /* Chip Interrupt Controller */
 #define KS2_CIC2_DDR3_ECC_IRQ_NUM	-1	/* not defined in K2E */
 #define KS2_CIC2_DDR3_ECC_CHAN_NUM	-1	/* not defined in K2E */
 
+/* SGMII SerDes */
+#define KS2_SGMII_SERDES2_BASE		0x02324000
+#define KS2_LANES_PER_SGMII_SERDES	4
+
 /* Number of DSP cores */
 #define KS2_NUM_DSPS			1
 
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE	0x24186000
+#define KS2_NETCP_PDMA_TX_BASE		0x24187000
+#define KS2_NETCP_PDMA_TX_CH_NUM	21
+#define KS2_NETCP_PDMA_RX_BASE		0x24188000
+#define KS2_NETCP_PDMA_RX_CH_NUM	91
+#define KS2_NETCP_PDMA_SCHED_BASE	0x24186100
+#define KS2_NETCP_PDMA_RX_FLOW_BASE	0x24189000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM	96
+#define KS2_NETCP_PDMA_RX_FREE_QUEUE	4001
+#define KS2_NETCP_PDMA_RX_RCV_QUEUE	4002
+#define KS2_NETCP_PDMA_TX_SND_QUEUE	896
+
+/* NETCP */
+#define KS2_NETCP_BASE			0x24000000
+
 #endif
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index eb132f73e60..5a9ea4fbca5 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -10,8 +10,6 @@
 #ifndef __ASM_ARCH_HARDWARE_K2HK_H
 #define __ASM_ARCH_HARDWARE_K2HK_H
 
-#define KS2_MISC_CTRL			(KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-
 #define KS2_ARM_PLL_EN			BIT(13)
 
 /* PA SS Registers */
@@ -81,7 +79,30 @@
 #define KS2_DDR3B_EMIF_DATA_BASE	0x60000000
 #define KS2_DDR3B_DDRPHYC		0x02328000
 
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM	0x0D3 /* DDR3 ECC system irq number */
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM	0x01D /* DDR3 ECC int mapped to CIC2
+						 channel 29 */
+
+/* SGMII SerDes */
+#define KS2_LANES_PER_SGMII_SERDES	4
+
 /* Number of DSP cores */
 #define KS2_NUM_DSPS			8
 
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE	0x02004000
+#define KS2_NETCP_PDMA_TX_BASE		0x02004400
+#define KS2_NETCP_PDMA_TX_CH_NUM	9
+#define KS2_NETCP_PDMA_RX_BASE		0x02004800
+#define KS2_NETCP_PDMA_RX_CH_NUM	26
+#define KS2_NETCP_PDMA_SCHED_BASE	0x02004c00
+#define KS2_NETCP_PDMA_RX_FLOW_BASE	0x02005000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM	32
+#define KS2_NETCP_PDMA_RX_FREE_QUEUE	4001
+#define KS2_NETCP_PDMA_RX_RCV_QUEUE	4002
+#define KS2_NETCP_PDMA_TX_SND_QUEUE	648
+
+/* NETCP */
+#define KS2_NETCP_BASE			0x02000000
+
 #endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
new file mode 100644
index 00000000000..05532ada70d
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
@@ -0,0 +1,101 @@
+/*
+ * K2L: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_K2L_H
+#define __ASM_ARCH_HARDWARE_K2L_H
+
+#define KS2_ARM_PLL_EN			BIT(13)
+
+/* PA SS Registers */
+#define KS2_PASS_BASE			0x26000000
+
+/* Power and Sleep Controller (PSC) Domains */
+#define KS2_LPSC_MOD			0
+#define KS2_LPSC_DFE_IQN_SYS		1
+#define KS2_LPSC_USB			2
+#define KS2_LPSC_EMIF25_SPI		3
+#define KS2_LPSC_TSIP                   4
+#define KS2_LPSC_DEBUGSS_TRC		5
+#define KS2_LPSC_TETB_TRC		6
+#define KS2_LPSC_PKTPROC		7
+#define KS2_LPSC_PA			KS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII			8
+#define KS2_LPSC_CPGMAC			KS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO			9
+#define KS2_LPSC_PCIE0			10
+#define KS2_LPSC_PCIE1			11
+#define KS2_LPSC_JESD_MISC		12
+#define KS2_LPSC_CHIP_SRSS		13
+#define KS2_LPSC_MSMC			14
+#define KS2_LPSC_GEM_1			16
+#define KS2_LPSC_GEM_2			17
+#define KS2_LPSC_GEM_3			18
+#define KS2_LPSC_EMIF4F_DDR3		23
+#define KS2_LPSC_TAC			25
+#define KS2_LPSC_RAC			26
+#define KS2_LPSC_DDUC4X_CFR2X_BB	27
+#define KS2_LPSC_FFTC_A			28
+#define KS2_LPSC_OSR			34
+#define KS2_LPSC_TCP3D_0		35
+#define KS2_LPSC_TCP3D_1		37
+#define KS2_LPSC_VCP2X4_A		39
+#define KS2_LPSC_VCP2X4_B		40
+#define KS2_LPSC_VCP2X4_C		41
+#define KS2_LPSC_VCP2X4_D		42
+#define KS2_LPSC_BCP			47
+#define KS2_LPSC_DPD4X			48
+#define KS2_LPSC_FFTC_B			49
+#define KS2_LPSC_IQN_AIL		50
+
+/* MSMC */
+#define KS2_MSMC_SEGMENT_PCIE1		14
+
+/* Chip Interrupt Controller */
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM	0x0D3
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM	0x01D
+
+/* OSR */
+#define KS2_OSR_DATA_BASE		0x70000000	/* OSR data base */
+#define KS2_OSR_CFG_BASE		0x02348c00	/* OSR config base */
+#define KS2_OSR_ECC_VEC			0x08		/* ECC Vector reg */
+#define KS2_OSR_ECC_CTRL		0x14		/* ECC control reg */
+
+/* OSR ECC Vector register */
+#define KS2_OSR_ECC_VEC_TRIG_RD		BIT(15)		/* trigger a read op */
+#define KS2_OSR_ECC_VEC_RD_DONE		BIT(24)		/* read complete */
+
+#define KS2_OSR_ECC_VEC_RAM_ID_SH	0		/* RAM ID shift */
+#define KS2_OSR_ECC_VEC_RD_ADDR_SH	16		/* read address shift */
+
+/* OSR ECC control register */
+#define KS2_OSR_ECC_CTRL_EN		BIT(0)		/* ECC enable bit */
+#define KS2_OSR_ECC_CTRL_CHK		BIT(1)		/* ECC check bit */
+#define KS2_OSR_ECC_CTRL_RMW		BIT(2)		/* ECC check bit */
+
+/* Number of OSR RAM banks */
+#define KS2_OSR_NUM_RAM_BANKS		4
+
+/* OSR memory size */
+#define KS2_OSR_SIZE			0x100000
+
+/* Number of DSP cores */
+#define KS2_NUM_DSPS			4
+
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE	0x26186000
+#define KS2_NETCP_PDMA_TX_BASE		0x26187000
+#define KS2_NETCP_PDMA_TX_CH_NUM	21
+#define KS2_NETCP_PDMA_RX_BASE		0x26188000
+#define KS2_NETCP_PDMA_RX_CH_NUM	91
+#define KS2_NETCP_PDMA_SCHED_BASE	0x26186100
+#define KS2_NETCP_PDMA_RX_FLOW_BASE	0x26189000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM	96
+#define KS2_NETCP_PDMA_TX_SND_QUEUE	896
+
+#endif /* __ASM_ARCH_HARDWARE_K2L_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index 76e6441e579..c6a54d8b91b 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -87,6 +87,52 @@ typedef volatile unsigned int   *dv_reg_p;
 
 #define KS2_DDR3_PLLCTRL_PHY_RESET	0x80000000
 
+/* DDR3 ECC */
+#define KS2_DDR3_ECC_INT_STATUS_OFFSET			0x0AC
+#define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET		0x0B4
+#define KS2_DDR3_ECC_CTRL_OFFSET			0x110
+#define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET			0x114
+#define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET		0x130
+#define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET	0x13C
+
+/* DDR3 ECC Interrupt Status register */
+#define KS2_DDR3_1B_ECC_ERR_SYS		BIT(5)
+#define KS2_DDR3_2B_ECC_ERR_SYS		BIT(4)
+#define KS2_DDR3_WR_ECC_ERR_SYS		BIT(3)
+
+/* DDR3 ECC Control register */
+#define KS2_DDR3_ECC_EN			BIT(31)
+#define KS2_DDR3_ECC_ADDR_RNG_PROT	BIT(30)
+#define KS2_DDR3_ECC_VERIFY_EN		BIT(29)
+#define KS2_DDR3_ECC_RMW_EN		BIT(28)
+#define KS2_DDR3_ECC_ADDR_RNG_1_EN	BIT(0)
+
+#define KS2_DDR3_ECC_ENABLE		(KS2_DDR3_ECC_EN | \
+					KS2_DDR3_ECC_ADDR_RNG_PROT | \
+					KS2_DDR3_ECC_VERIFY_EN)
+
+/* EDMA */
+#define KS2_EDMA0_BASE			0x02700000
+
+/* EDMA3 register offsets */
+#define KS2_EDMA_QCHMAP0		0x0200
+#define KS2_EDMA_IPR			0x1068
+#define KS2_EDMA_ICR			0x1070
+#define KS2_EDMA_QEECR			0x1088
+#define KS2_EDMA_QEESR			0x108c
+#define KS2_EDMA_PARAM_1(x)		(0x4020 + (4 * x))
+
+/* Chip Interrupt Controller */
+#define KS2_CIC2_BASE			0x02608000
+
+/* Chip Interrupt Controller register offsets */
+#define KS2_CIC_CTRL			0x04
+#define KS2_CIC_HOST_CTRL		0x0C
+#define KS2_CIC_GLOBAL_ENABLE		0x10
+#define KS2_CIC_SYS_ENABLE_IDX_SET	0x28
+#define KS2_CIC_HOST_ENABLE_IDX_SET	0x34
+#define KS2_CIC_CHAN_MAP(n)		(0x0400 + (n << 2))
+
 #define KS2_UART0_BASE                	0x02530c00
 #define KS2_UART1_BASE                	0x02531000
 
@@ -140,19 +186,51 @@ typedef volatile unsigned int   *dv_reg_p;
 /* Flag from ks2_debug options to check if DSPs need to stay ON */
 #define DBG_LEAVE_DSPS_ON		0x1
 
+/* MSMC control */
+#define KS2_MSMC_CTRL_BASE		0x0bc00000
+#define KS2_MSMC_DATA_BASE		0x0c000000
+#define KS2_MSMC_SEGMENT_TETRIS		8
+#define KS2_MSMC_SEGMENT_NETCP		9
+#define KS2_MSMC_SEGMENT_QM_PDSP	10
+#define KS2_MSMC_SEGMENT_PCIE0		11
+
+/* MSMC segment size shift bits */
+#define KS2_MSMC_SEG_SIZE_SHIFT		12
+#define KS2_MSMC_MAP_SEG_NUM		(2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT))
+#define KS2_MSMC_DST_SEG_BASE		(CONFIG_SYS_LPAE_SDRAM_BASE >> \
+					KS2_MSMC_SEG_SIZE_SHIFT)
+
 /* Device speed */
 #define KS2_REV1_DEVSPEED		(KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
 #define KS2_EFUSE_BOOTROM		(KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
+#define KS2_MISC_CTRL			(KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
 
 /* Queue manager */
-#define KS2_QM_MANAGER_BASE		0x02a02000
+#define KS2_QM_BASE_ADDRESS		0x23a80000
+#define KS2_QM_CONF_BASE		0x02a02000
 #define KS2_QM_DESC_SETUP_BASE		0x02a03000
-#define KS2_QM_MANAGER_QUEUES_BASEi	0x02a80000
+#define KS2_QM_STATUS_RAM_BASE		0x02a06000
+#define KS2_QM_INTD_CONF_BASE		0x02a0c000
+#define KS2_QM_PDSP1_CMD_BASE		0x02a20000
+#define KS2_QM_PDSP1_CTRL_BASE		0x02a0f000
+#define KS2_QM_PDSP1_IRAM_BASE		0x02a10000
+#define KS2_QM_MANAGER_QUEUES_BASE	0x02a80000
 #define KS2_QM_MANAGER_Q_PROXY_BASE	0x02ac0000
 #define KS2_QM_QUEUE_STATUS_BASE	0x02a40000
+#define KS2_QM_LINK_RAM_BASE		0x00100000
+#define KS2_QM_REGION_NUM		64
+#define KS2_QM_QPOOL_NUM		4000
 
-/* MSMC control */
-#define KS2_MSMC_CTRL_BASE		0x0bc00000
+/* USB */
+#define KS2_USB_SS_BASE			0x02680000
+#define KS2_USB_HOST_XHCI_BASE		(KS2_USB_SS_BASE + 0x10000)
+#define KS2_DEV_USB_PHY_BASE		0x02620738
+#define KS2_USB_PHY_CFG_BASE		0x02630000
+
+#define KS2_MAC_ID_BASE_ADDR		(KS2_DEVICE_STATE_CTRL_BASE + 0x110)
+
+/* SGMII SerDes */
+#define KS2_SGMII_SERDES_BASE		0x0232a000
 
 #ifdef CONFIG_SOC_K2HK
 #include <asm/arch/hardware-k2hk.h>
@@ -162,6 +240,10 @@ typedef volatile unsigned int   *dv_reg_p;
 #include <asm/arch/hardware-k2e.h>
 #endif
 
+#ifdef CONFIG_SOC_K2L
+#include <asm/arch/hardware-k2l.h>
+#endif
+
 #ifndef __ASSEMBLY__
 static inline int cpu_is_k2hk(void)
 {
@@ -179,6 +261,14 @@ static inline int cpu_is_k2e(void)
 	return (part_no == 0xb9a6) ? 1 : 0;
 }
 
+static inline int cpu_is_k2l(void)
+{
+	unsigned int jtag_id    = __raw_readl(KS2_JTAG_ID_REG);
+	unsigned int part_no    = (jtag_id >> 12) & 0xffff;
+
+	return (part_no == 0xb9a7) ? 1 : 0;
+}
+
 static inline int cpu_revision(void)
 {
 	unsigned int jtag_id	= __raw_readl(KS2_JTAG_ID_REG);
diff --git a/arch/arm/include/asm/arch-keystone/msmc.h b/arch/arm/include/asm/arch-keystone/msmc.h
index c320db5b65c..083f5ba0522 100644
--- a/arch/arm/include/asm/arch-keystone/msmc.h
+++ b/arch/arm/include/asm/arch-keystone/msmc.h
@@ -12,6 +12,34 @@
 
 #include <asm/arch/hardware.h>
 
+enum mpax_seg_size {
+	MPAX_SEG_4K = 0x0b,
+	MPAX_SEG_8K,
+	MPAX_SEG_16K,
+	MPAX_SEG_32K,
+	MPAX_SEG_64K,
+	MPAX_SEG_128K,
+	MPAX_SEG_256K,
+	MPAX_SEG_512K,
+	MPAX_SEG_1M,
+	MPAX_SEG_2M,
+	MPAX_SEG_4M,
+	MPAX_SEG_8M,
+	MPAX_SEG_16M,
+	MPAX_SEG_32M,
+	MPAX_SEG_64M,
+	MPAX_SEG_128M,
+	MPAX_SEG_256M,
+	MPAX_SEG_512M,
+	MPAX_SEG_1G,
+	MPAX_SEG_2G,
+	MPAX_SEG_4G
+};
+
 void msmc_share_all_segments(int priv_id);
+void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax);
+void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax);
+void msmc_map_ses_segment(int priv_id, int ses_pair,
+			  u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size);
 
 #endif
diff --git a/arch/arm/include/asm/arch-keystone/spl.h b/arch/arm/include/asm/arch-keystone/spl.h
deleted file mode 100644
index a7102d56409..00000000000
--- a/arch/arm/include/asm/arch-keystone/spl.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * (C) Copyright 2012-2014
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_SPI        2
-
-#endif
diff --git a/arch/arm/include/asm/arch-keystone/xhci-keystone.h b/arch/arm/include/asm/arch-keystone/xhci-keystone.h
new file mode 100644
index 00000000000..3aab4e045f1
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/xhci-keystone.h
@@ -0,0 +1,21 @@
+/*
+ * USB 3.0 DRD Controller
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#define USB3_PHY_REF_SSP_EN		BIT(29)
+#define USB3_PHY_OTG_VBUSVLDECTSEL	BIT(16)
+
+/* KEYSTONE2 XHCI PHY register structure */
+struct keystone_xhci_phy {
+	unsigned int phy_utmi;		/* ctl0 */
+	unsigned int phy_pipe;		/* ctl1 */
+	unsigned int phy_param_ctrl_1;	/* ctl2 */
+	unsigned int phy_param_ctrl_2;	/* ctl3 */
+	unsigned int phy_clock;		/* ctl4 */
+	unsigned int phy_pll;		/* ctl5 */
+};
diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h
index f7bfa0e74d7..ccc8e4e7d64 100644
--- a/arch/arm/include/asm/arch-kirkwood/config.h
+++ b/arch/arm/include/asm/arch-kirkwood/config.h
@@ -23,7 +23,7 @@
 #error "SOC Name not defined"
 #endif /* CONFIG_KW88F6281 */
 
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #define CONFIG_ARM926EJS	1	/* Basic Architecture */
 #define CONFIG_SYS_CACHELINE_SIZE	32
 				/* default Dcache Line length for kirkwood */
diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h
index 97daa403ce7..926d347110f 100644
--- a/arch/arm/include/asm/arch-kirkwood/cpu.h
+++ b/arch/arm/include/asm/arch-kirkwood/cpu.h
@@ -140,11 +140,11 @@ struct kwgpio_registers {
  * functions
  */
 unsigned char get_random_hex(void);
-unsigned int kw_sdram_bar(enum memory_bank bank);
-unsigned int kw_sdram_bs(enum memory_bank bank);
-void kw_sdram_size_adjust(enum memory_bank bank);
+unsigned int mvebu_sdram_bar(enum memory_bank bank);
+unsigned int mvebu_sdram_bs(enum memory_bank bank);
+void mvebu_sdram_size_adjust(enum memory_bank bank);
 int kw_config_adr_windows(void);
-void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
+void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
 		unsigned int gpp0_oe, unsigned int gpp1_oe);
 int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
 		unsigned int mpp16_23, unsigned int mpp24_31,
diff --git a/arch/arm/include/asm/arch-kirkwood/gpio.h b/arch/arm/include/asm/arch-kirkwood/gpio.h
index 5f4d7860855..aa8c5da36d3 100644
--- a/arch/arm/include/asm/arch-kirkwood/gpio.h
+++ b/arch/arm/include/asm/arch-kirkwood/gpio.h
@@ -21,14 +21,14 @@
 
 #define GPIO_MAX		50
 #define GPIO_OFF(pin)		(((pin) >> 5) ? 0x0040 : 0x0000)
-#define GPIO_OUT(pin)		(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
-#define GPIO_IO_CONF(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
-#define GPIO_BLINK_EN(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
-#define GPIO_IN_POL(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
-#define GPIO_DATA_IN(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
-#define GPIO_EDGE_CAUSE(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
-#define GPIO_EDGE_MASK(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
-#define GPIO_LEVEL_MASK(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
+#define GPIO_OUT(pin)		(MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
+#define GPIO_IO_CONF(pin)	(MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
+#define GPIO_BLINK_EN(pin)	(MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
+#define GPIO_IN_POL(pin)	(MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
+#define GPIO_DATA_IN(pin)	(MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
+#define GPIO_EDGE_CAUSE(pin)	(MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
+#define GPIO_EDGE_MASK(pin)	(MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
+#define GPIO_LEVEL_MASK(pin)	(MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
 
 /*
  * Kirkwood-specific GPIO API
diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/soc.h
index 3ea51d7848c..58ed71b1864 100644
--- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h
+++ b/arch/arm/include/asm/arch-kirkwood/soc.h
@@ -22,18 +22,19 @@
 #define KW_REG_UNDOC_0x1470		(KW_REGISTER(0x1470))
 #define KW_REG_UNDOC_0x1478		(KW_REGISTER(0x1478))
 
+#define MVEBU_SDRAM_BASE		(KW_REGISTER(0x1500))
 #define KW_TWSI_BASE			(KW_REGISTER(0x11000))
 #define KW_UART0_BASE			(KW_REGISTER(0x12000))
 #define KW_UART1_BASE			(KW_REGISTER(0x12100))
 #define KW_MPP_BASE			(KW_REGISTER(0x10000))
-#define KW_GPIO0_BASE			(KW_REGISTER(0x10100))
-#define KW_GPIO1_BASE			(KW_REGISTER(0x10140))
+#define MVEBU_GPIO0_BASE			(KW_REGISTER(0x10100))
+#define MVEBU_GPIO1_BASE			(KW_REGISTER(0x10140))
 #define KW_RTC_BASE			(KW_REGISTER(0x10300))
 #define KW_NANDF_BASE			(KW_REGISTER(0x10418))
-#define KW_SPI_BASE			(KW_REGISTER(0x10600))
+#define MVEBU_SPI_BASE			(KW_REGISTER(0x10600))
 #define KW_CPU_WIN_BASE			(KW_REGISTER(0x20000))
 #define KW_CPU_REG_BASE			(KW_REGISTER(0x20100))
-#define KW_TIMER_BASE			(KW_REGISTER(0x20300))
+#define MVEBU_TIMER_BASE			(KW_REGISTER(0x20300))
 #define KW_REG_PCIE_BASE		(KW_REGISTER(0x40000))
 #define KW_USB20_BASE			(KW_REGISTER(0x50000))
 #define KW_EGIGA0_BASE			(KW_REGISTER(0x72000))
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index a500b5bc3b6..f2c9687df42 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -19,6 +19,8 @@
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
 #define CONFIG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
+#define CONFIG_SYS_FSL_SEC_ADDR			(CONFIG_SYS_IMMR + 0x700000)
+#define CONFIG_SYS_FSL_JR0_ADDR			(CONFIG_SYS_IMMR + 0x710000)
 #define CONFIG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
 #define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
 #define CONFIG_SYS_FSL_LS1_CLK_ADDR		(CONFIG_SYS_IMMR + 0x00ee1000)
@@ -66,6 +68,7 @@
 #define CONFIG_SYS_FSL_DSPI_BE
 #define CONFIG_SYS_FSL_QSPI_BE
 #define CONFIG_SYS_FSL_DCU_BE
+#define CONFIG_SYS_FSL_SEC_LE
 
 #define DCU_LAYER_MAX_NUM			16
 
@@ -76,6 +79,7 @@
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
 #define CONFIG_NUM_DDR_CONTROLLERS		1
 #define CONFIG_SYS_FSL_DDR_VER			FSL_DDR_VER_5_0
+#define CONFIG_SYS_FSL_SEC_COMPAT		5
 #else
 #error SoC not defined
 #endif
diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h
index e512dcec162..e512dcec162 100644
--- a/arch/arm/include/asm/arch-kirkwood/spi.h
+++ b/arch/arm/include/asm/arch-mvebu/spi.h
diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h
index 09dfc90a9b0..062f3de1d05 100644
--- a/arch/arm/include/asm/arch-mxs/sys_proto.h
+++ b/arch/arm/include/asm/arch-mxs/sys_proto.h
@@ -10,6 +10,8 @@
 #ifndef __SYS_PROTO_H__
 #define __SYS_PROTO_H__
 
+#include <asm/imx-common/regs-common.h>
+
 int mxs_reset_block(struct mxs_register_32 *reg);
 int mxs_wait_mask_set(struct mxs_register_32 *reg,
 		       uint32_t mask,
diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h
index 2f8320629be..eba4a5c7f0c 100644
--- a/arch/arm/include/asm/arch-omap3/mux.h
+++ b/arch/arm/include/asm/arch-omap3/mux.h
@@ -281,7 +281,7 @@
 #define CONTROL_PADCONF_SYS_OFF_MODE	0x0A18
 #define CONTROL_PADCONF_SYS_CLKOUT1	0x0A1A
 #define CONTROL_PADCONF_SYS_CLKOUT2	0x01E2
-#define CONTROL_PADCONF_JTAG_nTRST	0x0A1C
+#define CONTROL_PADCONF_JTAG_NTRST	0x0A1C
 #define CONTROL_PADCONF_JTAG_TCK	0x0A1E
 #define CONTROL_PADCONF_JTAG_TMS	0x0A20
 #define CONTROL_PADCONF_JTAG_TDI	0x0A22
@@ -443,7 +443,7 @@
 #define OMAP34XX_CTRL_WKUP_CTRL		(OMAP34XX_CTRL_BASE + 0x0A5C)
 #define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ	(1<<6)
 
-#define MUX_VAL(OFFSET,VALUE)\
+#define MUX_VAL(OFFSET, VALUE)\
 	writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
 
 #define	CP(x)	(CONTROL_PADCONF_##x)
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 5866bf23e8d..34bd8c509aa 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -64,6 +64,7 @@ void try_unlock_memory(void);
 u32 get_boot_type(void);
 void invalidate_dcache(u32);
 u32 wait_on_value(u32, u32, void *, u32);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
 void sdelay(unsigned long);
 void make_cs1_contiguous(void);
 void omap_nand_switch_ecc(uint32_t, uint32_t);
diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
index d5dbc22c18d..2de205e74b6 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
@@ -682,8 +682,7 @@ enum s5pc110_gpio_pin {
 	S5PC110_GPIO_MP285,
 	S5PC110_GPIO_MP286,
 	S5PC110_GPIO_MP287,
-	S5PC110_GPIO_RES,
-	S5PC110_GPIO_H00 = (S5PC110_GPIO_RES + (48 * 8)),
+	S5PC110_GPIO_H00,
 	S5PC110_GPIO_H01,
 	S5PC110_GPIO_H02,
 	S5PC110_GPIO_H03,
@@ -815,11 +814,7 @@ static const struct gpio_name_num_table s5pc110_gpio_table[] = {
 void gpio_cfg_pin(int gpio, int cfg);
 void gpio_set_pull(int gpio, int mode);
 void gpio_set_drv(int gpio, int mode);
-int gpio_direction_output(unsigned gpio, int value);
-int gpio_set_value(unsigned gpio, int value);
-int gpio_get_value(unsigned gpio);
 void gpio_set_rate(int gpio, int mode);
-struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio);
 int s5p_gpio_get_pin(unsigned gpio);
 
 /* GPIO pins per bank  */
diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h
deleted file mode 100644
index 7e310d5a0c9..00000000000
--- a/arch/arm/include/asm/arch-socfpga/spl.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- *  Copyright (C) 2012 Pavel Machek <pavel@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _SOCFPGA_SPL_H_
-#define _SOCFPGA_SPL_H_
-
-/* Symbols from linker script */
-extern char __malloc_start, __malloc_end, __stack_start;
-
-#define BOOT_DEVICE_RAM 1
-
-#endif
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index 5669f392fab..42382a8ae2f 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -15,12 +15,17 @@
 #define CLK_GATE_CLOSE			0x0
 
 /* clock control module regs definition */
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+#include <asm/arch/clock_sun6i.h>
+#else
 #include <asm/arch/clock_sun4i.h>
+#endif
 
 #ifndef __ASSEMBLY__
 int clock_init(void);
 int clock_twi_onoff(int port, int state);
 void clock_set_pll1(unsigned int hz);
+unsigned int clock_get_pll5p(void);
 unsigned int clock_get_pll6(void);
 void clock_init_safe(void);
 void clock_init_uart(void);
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 1ba997adf9f..90af8e25069 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -199,13 +199,16 @@ struct sunxi_ccm_reg {
 #define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3)
 #define CCM_PLL5_CTRL_M1_X(n) ((n) - 1)
 #define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4)
+#define CCM_PLL5_CTRL_K_SHIFT 4
 #define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3)
 #define CCM_PLL5_CTRL_K_X(n) ((n) - 1)
 #define CCM_PLL5_CTRL_LDO (0x1 << 7)
 #define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8)
+#define CCM_PLL5_CTRL_N_SHIFT 8
 #define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f)
 #define CCM_PLL5_CTRL_N_X(n) (n)
 #define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16)
+#define CCM_PLL5_CTRL_P_SHIFT 16
 #define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3)
 #define CCM_PLL5_CTRL_P_X(n) ((n) - 1)
 #define CCM_PLL5_CTRL_BW (0x1 << 18)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
new file mode 100644
index 00000000000..1397b358898
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -0,0 +1,205 @@
+/*
+ * sun6i clock register definitions
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_CLOCK_SUN6I_H
+#define _SUNXI_CLOCK_SUN6I_H
+
+struct sunxi_ccm_reg {
+	u32 pll1_cfg;		/* 0x00 pll1 control */
+	u32 reserved0;
+	u32 pll2_cfg;		/* 0x08 pll2 control */
+	u32 reserved1;
+	u32 pll3_cfg;		/* 0x10 pll3 control */
+	u32 reserved2;
+	u32 pll4_cfg;		/* 0x18 pll4 control */
+	u32 reserved3;
+	u32 pll5_cfg;		/* 0x20 pll5 control */
+	u32 reserved4;
+	u32 pll6_cfg;		/* 0x28 pll6 control */
+	u32 reserved5;
+	u32 pll7_cfg;		/* 0x30 pll7 control */
+	u32 reserved6;
+	u32 pll8_cfg;		/* 0x38 pll8 control */
+	u32 reserved7;
+	u32 mipi_pll_cfg;	/* 0x40 MIPI pll control */
+	u32 pll9_cfg;		/* 0x44 pll9 control */
+	u32 pll10_cfg;		/* 0x48 pll10 control */
+	u32 reserved8;
+	u32 cpu_axi_cfg;	/* 0x50 CPU/AXI divide ratio */
+	u32 ahb1_apb1_div;	/* 0x54 AHB1/APB1 divide ratio */
+	u32 apb2_div;		/* 0x58 APB2 divide ratio */
+	u32 axi_gate;		/* 0x5c axi module clock gating */
+	u32 ahb_gate0;		/* 0x60 ahb module clock gating 0 */
+	u32 ahb_gate1;		/* 0x64 ahb module clock gating 1 */
+	u32 apb1_gate;		/* 0x68 apb1 module clock gating */
+	u32 apb2_gate;		/* 0x6c apb2 module clock gating */
+	u32 reserved9[4];
+	u32 nand0_clk_cfg;	/* 0x80 nand0 clock control */
+	u32 nand1_clk_cfg;	/* 0x84 nand1 clock control */
+	u32 sd0_clk_cfg;	/* 0x88 sd0 clock control */
+	u32 sd1_clk_cfg;	/* 0x8c sd1 clock control */
+	u32 sd2_clk_cfg;	/* 0x90 sd2 clock control */
+	u32 sd3_clk_cfg;	/* 0x94 sd3 clock control */
+	u32 ts_clk_cfg;		/* 0x98 transport stream clock control */
+	u32 ss_clk_cfg;		/* 0x9c security system clock control */
+	u32 spi0_clk_cfg;	/* 0xa0 spi0 clock control */
+	u32 spi1_clk_cfg;	/* 0xa4 spi1 clock control */
+	u32 spi2_clk_cfg;	/* 0xa8 spi2 clock control */
+	u32 spi3_clk_cfg;	/* 0xac spi3 clock control */
+	u32 i2s0_clk_cfg;	/* 0xb0 I2S0 clock control*/
+	u32 i2s1_clk_cfg;	/* 0xb4 I2S1 clock control */
+	u32 reserved10[2];
+	u32 spdif_clk_cfg;	/* 0xc0 SPDIF clock control */
+	u32 reserved11[2];
+	u32 usb_clk_cfg;	/* 0xcc USB clock control */
+	u32 gmac_clk_cfg;	/* 0xd0 GMAC clock control */
+	u32 reserved12[7];
+	u32 mdfs_clk_cfg;	/* 0xf0 MDFS clock control */
+	u32 dram_clk_cfg;	/* 0xf4 DRAM configuration clock control */
+	u32 reserved13[2];
+	u32 dram_clk_gate;	/* 0x100 DRAM module gating */
+	u32 be0_clk_cfg;	/* 0x104 BE0 module clock */
+	u32 be1_clk_cfg;	/* 0x108 BE1 module clock */
+	u32 fe0_clk_cfg;	/* 0x10c FE0 module clock */
+	u32 fe1_clk_cfg;	/* 0x110 FE1 module clock */
+	u32 mp_clk_cfg;		/* 0x114 MP module clock */
+	u32 lcd0_ch0_clk_cfg;	/* 0x118 LCD0 CH0 module clock */
+	u32 lcd1_ch0_clk_cfg;	/* 0x11c LCD1 CH0 module clock */
+	u32 reserved14[3];
+	u32 lcd0_ch1_clk_cfg;	/* 0x12c LCD0 CH1 module clock */
+	u32 lcd1_ch1_clk_cfg;	/* 0x130 LCD1 CH1 module clock */
+	u32 csi0_clk_cfg;	/* 0x134 CSI0 module clock */
+	u32 csi1_clk_cfg;	/* 0x138 CSI1 module clock */
+	u32 ve_clk_cfg;		/* 0x13c VE module clock */
+	u32 adda_clk_cfg;	/* 0x140 ADDA module clock */
+	u32 avs_clk_cfg;	/* 0x144 AVS module clock */
+	u32 dmic_clk_cfg;	/* 0x148 Digital Mic module clock*/
+	u32 reserved15;
+	u32 hdmi_clk_cfg;	/* 0x150 HDMI module clock */
+	u32 ps_clk_cfg;		/* 0x154 PS module clock */
+	u32 mtc_clk_cfg;	/* 0x158 MTC module clock */
+	u32 mbus0_clk_cfg;	/* 0x15c MBUS0 module clock */
+	u32 mbus1_clk_cfg;	/* 0x160 MBUS1 module clock */
+	u32 reserved16;
+	u32 mipi_dsi_clk_cfg;	/* 0x168 MIPI DSI clock control */
+	u32 mipi_csi_clk_cfg;	/* 0x16c MIPI CSI clock control */
+	u32 reserved17[4];
+	u32 iep_drc0_clk_cfg;	/* 0x180 IEP DRC0 module clock */
+	u32 iep_drc1_clk_cfg;	/* 0x184 IEP DRC1 module clock */
+	u32 iep_deu0_clk_cfg;	/* 0x188 IEP DEU0 module clock */
+	u32 iep_deu1_clk_cfg;	/* 0x18c IEP DEU1 module clock */
+	u32 reserved18[4];
+	u32 gpu_core_clk_cfg;	/* 0x1a0 GPU core clock config */
+	u32 gpu_mem_clk_cfg;	/* 0x1a4 GPU memory clock config */
+	u32 gpu_hyd_clk_cfg;	/* 0x1a0 GPU HYD clock config */
+	u32 reserved19[21];
+	u32 pll_lock;		/* 0x200 PLL Lock Time */
+	u32 pll1_lock;		/* 0x204 PLL1 Lock Time */
+	u32 reserved20[6];
+	u32 pll1_bias_cfg;	/* 0x220 PLL1 Bias config */
+	u32 pll2_bias_cfg;	/* 0x224 PLL2 Bias config */
+	u32 pll3_bias_cfg;	/* 0x228 PLL3 Bias config */
+	u32 pll4_bias_cfg;	/* 0x22c PLL4 Bias config */
+	u32 pll5_bias_cfg;	/* 0x230 PLL5 Bias config */
+	u32 pll6_bias_cfg;	/* 0x234 PLL6 Bias config */
+	u32 pll7_bias_cfg;	/* 0x238 PLL7 Bias config */
+	u32 pll8_bias_cfg;	/* 0x23c PLL8 Bias config */
+	u32 mipi_bias_cfg;	/* 0x240 MIPI Bias config */
+	u32 pll9_bias_cfg;	/* 0x244 PLL9 Bias config */
+	u32 pll10_bias_cfg;	/* 0x248 PLL10 Bias config */
+	u32 reserved21[13];
+	u32 pll1_pattern_cfg;	/* 0x280 PLL1 Pattern config */
+	u32 pll2_pattern_cfg;	/* 0x284 PLL2 Pattern config */
+	u32 pll3_pattern_cfg;	/* 0x288 PLL3 Pattern config */
+	u32 pll4_pattern_cfg;	/* 0x28c PLL4 Pattern config */
+	u32 pll5_pattern_cfg;	/* 0x290 PLL5 Pattern config */
+	u32 pll6_pattern_cfg;	/* 0x294 PLL6 Pattern config */
+	u32 pll7_pattern_cfg;	/* 0x298 PLL7 Pattern config */
+	u32 pll8_pattern_cfg;	/* 0x29c PLL8 Pattern config */
+	u32 mipi_pattern_cfg;	/* 0x2a0 MIPI Pattern config */
+	u32 pll9_pattern_cfg;	/* 0x2a4 PLL9 Pattern config */
+	u32 pll10_pattern_cfg;	/* 0x2a8 PLL10 Pattern config */
+	u32 reserved22[5];
+	u32 ahb_reset0_cfg;	/* 0x2c0 AHB1 Reset 0 config */
+	u32 ahb_reset1_cfg;	/* 0x2c4 AHB1 Reset 1 config */
+	u32 ahb_reset2_cfg;	/* 0x2c8 AHB1 Reset 2 config */
+	u32 reserved23;
+	u32 apb1_reset_cfg;	/* 0x2d0 APB1 Reset config */
+	u32 reserved24;
+	u32 apb2_reset_cfg;	/* 0x2d8 APB2 Reset config */
+};
+
+/* apb2 bit field */
+#define APB2_CLK_SRC_LOSC		(0x0 << 24)
+#define APB2_CLK_SRC_OSC24M		(0x1 << 24)
+#define APB2_CLK_SRC_PLL6		(0x2 << 24)
+#define APB2_CLK_SRC_MASK		(0x3 << 24)
+#define APB2_CLK_RATE_N_1		(0x0 << 16)
+#define APB2_CLK_RATE_N_2		(0x1 << 16)
+#define APB2_CLK_RATE_N_4		(0x2 << 16)
+#define APB2_CLK_RATE_N_8		(0x3 << 16)
+#define APB2_CLK_RATE_N_MASK		(3 << 16)
+#define APB2_CLK_RATE_M(m)		(((m)-1) << 0)
+#define APB2_CLK_RATE_M_MASK            (0x1f << 0)
+
+/* apb2 gate field */
+#define APB2_GATE_UART_SHIFT	(16)
+#define APB2_GATE_UART_MASK		(0xff << APB2_GATE_UART_SHIFT)
+#define APB2_GATE_TWI_SHIFT	(0)
+#define APB2_GATE_TWI_MASK		(0xf << APB2_GATE_TWI_SHIFT)
+
+/* cpu_axi_cfg bits */
+#define AXI_DIV_SHIFT			0
+#define ATB_DIV_SHIFT			8
+#define CPU_CLK_SRC_SHIFT		16
+
+#define AXI_DIV_1			0
+#define AXI_DIV_2			1
+#define AXI_DIV_3			2
+#define AXI_DIV_4			3
+#define ATB_DIV_1			0
+#define ATB_DIV_2			1
+#define ATB_DIV_4			2
+#define CPU_CLK_SRC_OSC24M		1
+#define CPU_CLK_SRC_PLL1		2
+
+#define PLL1_CFG_DEFAULT		0x90011b21
+
+#define PLL6_CFG_DEFAULT		0x90041811
+
+#define CCM_PLL6_CTRL_N_SHIFT		8
+#define CCM_PLL6_CTRL_N_MASK		(0x1f << CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_K_SHIFT		4
+#define CCM_PLL6_CTRL_K_MASK		(0x3 << CCM_PLL6_CTRL_K_SHIFT)
+
+#define AHB_GATE_OFFSET_MMC3		11
+#define AHB_GATE_OFFSET_MMC2		10
+#define AHB_GATE_OFFSET_MMC1		9
+#define AHB_GATE_OFFSET_MMC0		8
+#define AHB_GATE_OFFSET_MMC(n)		(AHB_GATE_OFFSET_MMC0 + (n))
+
+#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
+#define CCM_MMC_CTRL_PLL6   (0x1 << 24)
+
+#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+
+#define AHB_RESET_OFFSET_MMC3		11
+#define AHB_RESET_OFFSET_MMC2		10
+#define AHB_RESET_OFFSET_MMC1		9
+#define AHB_RESET_OFFSET_MMC0		8
+#define AHB_RESET_OFFSET_MMC(n)		(AHB_RESET_OFFSET_MMC0 + (n))
+
+/* apb2 reset */
+#define APB2_RESET_UART_SHIFT		(16)
+#define APB2_RESET_UART_MASK		(0xff << APB2_RESET_UART_SHIFT)
+#define APB2_RESET_TWI_SHIFT		(0)
+#define APB2_RESET_TWI_MASK		(0xf << APB2_RESET_TWI_SHIFT)
+
+#endif /* _SUNXI_CLOCK_SUN6I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index a987e51d576..0de79a0d508 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -95,6 +95,11 @@
 #define SUNXI_MALI400_BASE		0x01c40000
 #define SUNXI_GMAC_BASE			0x01c50000
 
+#define SUNXI_DRAM_COM_BASE		0x01c62000
+#define SUNXI_DRAM_CTL_BASE		0x01c63000
+#define SUNXI_DRAM_PHY_CH1_BASE		0x01c65000
+#define SUNXI_DRAM_PHY_CH2_BASE		0x01c66000
+
 /* module sram */
 #define SUNXI_SRAM_C_BASE		0x01d00000
 
@@ -105,6 +110,11 @@
 #define SUNXI_MP_BASE			0x01e80000
 #define SUNXI_AVG_BASE			0x01ea0000
 
+#define SUNXI_PRCM_BASE			0x01f01400
+#define SUNXI_R_UART_BASE		0x01f02800
+#define SUNXI_R_PIO_BASE		0x01f02c00
+#define SUNXI_P2WI_BASE			0x01f03400
+
 /* CoreSight Debug Module */
 #define SUNXI_CSDM_BASE			0x3f500000
 
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index f7f3d8c41ad..437dd35b68d 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -10,6 +10,7 @@
 #define _SUNXI_GPIO_H
 
 #include <linux/types.h>
+#include <asm/arch/cpu.h>
 
 /*
  * sunxi has 9 banks of gpio, they are:
@@ -27,8 +28,27 @@
 #define SUNXI_GPIO_G	6
 #define SUNXI_GPIO_H	7
 #define SUNXI_GPIO_I	8
+
+/*
+ * This defines the number of GPIO banks for the _main_ GPIO controller.
+ * You should fix up the padding in struct sunxi_gpio_reg below if you
+ * change this.
+ */
 #define SUNXI_GPIO_BANKS 9
 
+/*
+ * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
+ * at a different register offset.
+ *
+ * sun6i has 2 banks:
+ * PL0 - PL8  | PM0 - PM7
+ *
+ * sun8i has 1 bank:
+ * PL0 - PL11
+ */
+#define SUNXI_GPIO_L	11
+#define SUNXI_GPIO_M	12
+
 struct sunxi_gpio {
 	u32 cfg[4];
 	u32 dat;
@@ -50,8 +70,9 @@ struct sunxi_gpio_reg {
 	struct sunxi_gpio_int gpio_int;
 };
 
-#define BANK_TO_GPIO(bank) \
-	&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]
+#define BANK_TO_GPIO(bank)	(((bank) < SUNXI_GPIO_L) ? \
+	&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
+	&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])
 
 #define GPIO_BANK(pin)		((pin) >> 5)
 #define GPIO_NUM(pin)		((pin) & 0x1f)
@@ -75,6 +96,8 @@ struct sunxi_gpio_reg {
 #define SUNXI_GPIO_G_NR		32
 #define SUNXI_GPIO_H_NR		32
 #define SUNXI_GPIO_I_NR		32
+#define SUNXI_GPIO_L_NR		32
+#define SUNXI_GPIO_M_NR		32
 
 #define SUNXI_GPIO_NEXT(__gpio) \
 	((__gpio##_START) + (__gpio##_NR) + 0)
@@ -89,6 +112,8 @@ enum sunxi_gpio_number {
 	SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
 	SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
 	SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
+	SUNXI_GPIO_L_START = 352,
+	SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
 };
 
 /* SUNXI GPIO number definitions */
@@ -101,6 +126,8 @@ enum sunxi_gpio_number {
 #define SUNXI_GPG(_nr)	(SUNXI_GPIO_G_START + (_nr))
 #define SUNXI_GPH(_nr)	(SUNXI_GPIO_H_START + (_nr))
 #define SUNXI_GPI(_nr)	(SUNXI_GPIO_I_START + (_nr))
+#define SUNXI_GPL(_nr)	(SUNXI_GPIO_L_START + (_nr))
+#define SUNXI_GPM(_nr)	(SUNXI_GPIO_M_START + (_nr))
 
 /* GPIO pin function config */
 #define SUNXI_GPIO_INPUT	0
@@ -117,6 +144,8 @@ enum sunxi_gpio_number {
 #define SUN5I_GPB19_UART0_TX	2
 #define SUN5I_GPB20_UART0_RX	2
 
+#define SUN5I_GPG3_SDC1		2
+
 #define SUN5I_GPG3_UART1_TX	4
 #define SUN5I_GPG4_UART1_RX	4
 
@@ -125,21 +154,35 @@ enum sunxi_gpio_number {
 #define SUNXI_GPF0_SDC0		2
 
 #define SUNXI_GPF2_SDC0		2
+
+#ifdef CONFIG_MACH_SUN8I
+#define SUNXI_GPF2_UART0_TX	3
+#define SUNXI_GPF4_UART0_RX	3
+#else
 #define SUNXI_GPF2_UART0_TX	4
 #define SUNXI_GPF4_UART0_RX	4
+#endif
 
 #define SUN4I_GPG0_SDC1		4
 
 #define SUN4I_GPH22_SDC1	5
 
+#define SUN6I_GPH20_UART0_TX	2
+#define SUN6I_GPH21_UART0_RX	2
+
 #define SUN4I_GPI4_SDC3		2
 
+#define SUN8I_GPL2_R_UART_TX	2
+#define SUN8I_GPL3_R_UART_RX	2
+
 /* GPIO pin pull-up/down config */
 #define SUNXI_GPIO_PULL_DISABLE	0
 #define SUNXI_GPIO_PULL_UP	1
 #define SUNXI_GPIO_PULL_DOWN	2
 
-int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
+void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
 int sunxi_gpio_get_cfgpin(u32 pin);
 int sunxi_gpio_set_drv(u32 pin, u32 val);
 int sunxi_gpio_set_pull(u32 pin, u32 val);
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 53196e3b024..537f1455643 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -43,7 +43,10 @@ struct sunxi_mmc {
 	u32 chda;		/* 0x90 */
 	u32 cbda;		/* 0x94 */
 	u32 res1[26];
-	u32 fifo;		/* 0x100 FIFO access address */
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+	u32 res2[64];
+#endif
+	u32 fifo;		/* 0x100 (0x200 on sun6i) FIFO access address */
 };
 
 #define SUNXI_MMC_CLK_POWERSAVE		(0x1 << 17)
@@ -120,5 +123,5 @@ struct sunxi_mmc {
 #define SUNXI_MMC_IDIE_TXIRQ		(0x1 << 0)
 #define SUNXI_MMC_IDIE_RXIRQ		(0x1 << 1)
 
-int sunxi_mmc_init(int sdc_no);
+struct mmc *sunxi_mmc_init(int sdc_no);
 #endif /* _SUNXI_MMC_H */
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
new file mode 100644
index 00000000000..3d3bfa6cd1b
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -0,0 +1,238 @@
+/*
+ * Sunxi A31 Power Management Unit register definition.
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_PRCM_H
+#define _SUNXI_PRCM_H
+
+#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4)
+#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3)
+#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1)
+#define PRCM_CPUS_CFG_PRE_DIV(n) \
+	__PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n))
+#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8)
+#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f)
+#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1)
+#define PRCM_CPUS_CFG_POST_DIV(n) \
+	__PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n))
+#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16)
+#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3)
+#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0
+#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1
+#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2
+#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3
+#define PRCM_CPUS_CFG_CLK_SRC_LOSC \
+	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC)
+#define PRCM_CPUS_CFG_CLK_SRC_HOSC \
+	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC)
+#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \
+	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6)
+#define PRCM_CPUS_CFG_CLK_SRC_PDIV \
+	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV)
+
+#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0)
+#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3)
+#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1)
+#define PRCM_APB0_RATIO_DIV(n) \
+	__PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n))
+
+#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0)
+#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1)
+
+#define PRCM_APB0_GATE_PIO (0x1 << 0)
+#define PRCM_APB0_GATE_IR (0x1 << 1)
+#define PRCM_APB0_GATE_TIMER01 (0x1 << 2)
+#define PRCM_APB0_GATE_P2WI (0x1 << 3)
+#define PRCM_APB0_GATE_UART (0x1 << 4)
+#define PRCM_APB0_GATE_1WIRE (0x1 << 5)
+#define PRCM_APB0_GATE_I2C (0x1 << 6)
+
+#define PRCM_APB0_RESET_PIO (0x1 << 0)
+#define PRCM_APB0_RESET_IR (0x1 << 1)
+#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
+#define PRCM_APB0_RESET_P2WI (0x1 << 3)
+#define PRCM_APB0_RESET_UART (0x1 << 4)
+#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
+#define PRCM_APB0_RESET_I2C (0x1 << 6)
+
+#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0)
+#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1)
+#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4)
+#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(0x3)
+#define __PRCM_PLL_CTRL_USB_CLK_0 0x0
+#define __PRCM_PLL_CTRL_USB_CLK_1 0x1
+#define __PRCM_PLL_CTRL_USB_CLK_2 0x2
+#define __PRCM_PLL_CTRL_USB_CLK_3 0x3
+#define PRCM_PLL_CTRL_USB_CLK_0 \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0)
+#define PRCM_PLL_CTRL_USB_CLK_1 \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1)
+#define PRCM_PLL_CTRL_USB_CLK_2 \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2)
+#define PRCM_PLL_CTRL_USB_CLK_3 \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3)
+#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12)
+#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \
+	__PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3)
+#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \
+	__PRCM_PLL_CTRL_INT_PLL_IN_SEL(n)
+#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20)
+#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3)
+#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0
+#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1
+#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2
+#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3
+#define PRCM_PLL_CTRL_HOSC_CLK_0 \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0)
+#define PRCM_PLL_CTRL_HOSC_CLK_1 \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1)
+#define PRCM_PLL_CTRL_HOSC_CLK_2 \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2)
+#define PRCM_PLL_CTRL_HOSC_CLK_3 \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3)
+#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24)
+#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0)
+#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1)
+#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2)
+#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3)
+#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */
+#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16)
+#define PRCM_PLL_CTRL_LDO_OUT_MASK \
+	__PRCM_PLL_CTRL_LDO_OUT(0x7)
+/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */
+#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
+	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
+#define PRCM_PLL_CTRL_LDO_OUT_H(n) \
+	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)
+#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
+	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
+#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
+	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
+#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
+
+#define PRCM_CLK_1WIRE_GATE (0x1 << 31)
+
+#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0)
+#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf)
+#define __PRCM_CLK_MOD0_M_X(n) (n - 1)
+#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n))
+#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8)
+#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7)
+#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16)
+#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3)
+#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1)
+#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n))
+#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20)
+#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7)
+#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24)
+#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7)
+#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31)
+
+#define PRCM_APB0_RESET_PIO (0x1 << 0)
+#define PRCM_APB0_RESET_IR (0x1 << 1)
+#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
+#define PRCM_APB0_RESET_P2WI (0x1 << 3)
+#define PRCM_APB0_RESET_UART (0x1 << 4)
+#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
+#define PRCM_APB0_RESET_I2C (0x1 << 6)
+
+#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8)
+#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7)
+#define __PRCM_CLK_OUTD_M_X() ((n) - 1)
+#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n))
+#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20)
+#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7)
+#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1)
+#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n)
+#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24)
+#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3)
+#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0
+#define __PRCM_CLK_OUTD_SRC_LOSC 0x1
+#define __PRCM_CLK_OUTD_SRC_HOSC 0x2
+#define __PRCM_CLK_OUTD_SRC_ERR 0x3
+#define PRCM_CLK_OUTD_SRC_LOSC2 \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2)
+#define PRCM_CLK_OUTD_SRC_LOSC \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC)
+#define PRCM_CLK_OUTD_SRC_HOSC \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC)
+#define PRCM_CLK_OUTD_SRC_ERR \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR)
+#define PRCM_CLK_OUTD_EN (0x1 << 31)
+
+#define PRCM_CPU0_PWROFF (0x1 << 0)
+#define PRCM_CPU1_PWROFF (0x1 << 1)
+#define PRCM_CPU2_PWROFF (0x1 << 2)
+#define PRCM_CPU3_PWROFF (0x1 << 3)
+#define PRCM_CPU_ALL_PWROFF (0xf << 0)
+
+#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0)
+#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1)
+#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2)
+#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3)
+
+#define PRCM_VDD_GPU_PWROFF (0x1 << 0)
+
+#define PRCM_VDD_SYS_RESET (0x1 << 0)
+
+#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff)
+
+#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff)
+
+#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)
+
+#ifndef __ASSEMBLY__
+struct sunxi_prcm_reg {
+	u32 cpus_cfg;		/* 0x000 */
+	u8 res0[0x8];		/* 0x004 */
+	u32 apb0_ratio;		/* 0x00c */
+	u32 cpu0_cfg;		/* 0x010 */
+	u32 cpu1_cfg;		/* 0x014 */
+	u32 cpu2_cfg;		/* 0x018 */
+	u32 cpu3_cfg;		/* 0x01c */
+	u8 res1[0x8];		/* 0x020 */
+	u32 apb0_gate;		/* 0x028 */
+	u8 res2[0x14];		/* 0x02c */
+	u32 pll_ctrl0;		/* 0x040 */
+	u32 pll_ctrl1;		/* 0x044 */
+	u8 res3[0x8];		/* 0x048 */
+	u32 clk_1wire;		/* 0x050 */
+	u32 clk_ir;		/* 0x054 */
+	u8 res4[0x58];		/* 0x058 */
+	u32 apb0_reset;		/* 0x0b0 */
+	u8 res5[0x3c];		/* 0x0b4 */
+	u32 clk_outd;		/* 0x0f0 */
+	u8 res6[0xc];		/* 0x0f4 */
+	u32 cpu_pwroff;		/* 0x100 */
+	u8 res7[0xc];		/* 0x104 */
+	u32 vdd_sys_pwroff;	/* 0x110 */
+	u8 res8[0x4];		/* 0x114 */
+	u32 gpu_pwroff;		/* 0x118 */
+	u8 res9[0x4];		/* 0x11c */
+	u32 vdd_pwr_reset;	/* 0x120 */
+	u8 res10[0x20];		/* 0x124 */
+	u32 cpu1_pwr_clamp;	/* 0x144 */
+	u32 cpu2_pwr_clamp;	/* 0x148 */
+	u32 cpu3_pwr_clamp;	/* 0x14c */
+	u8 res11[0x30];		/* 0x150 */
+	u32 dram_pwr;		/* 0x180 */
+	u8 res12[0xc];		/* 0x184 */
+	u32 dram_tst;		/* 0x190 */
+};
+
+void prcm_apb0_enable(u32 flags);
+#endif /* __ASSEMBLY__ */
+#endif /* _PRCM_H */
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
index 58e14fd0f71..9a5e488a380 100644
--- a/arch/arm/include/asm/arch-sunxi/timer.h
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -11,14 +11,10 @@
 #ifndef _SUNXI_TIMER_H_
 #define _SUNXI_TIMER_H_
 
-#define WDT_CTRL_RESTART	(0x1 << 0)
-#define WDT_CTRL_KEY		(0x0a57 << 1)
-#define WDT_MODE_EN		(0x1 << 0)
-#define WDT_MODE_RESET_EN	(0x1 << 1)
-
 #ifndef __ASSEMBLY__
 
 #include <linux/types.h>
+#include <asm/arch/watchdog.h>
 
 /* General purpose timer */
 struct sunxi_timer {
@@ -43,12 +39,6 @@ struct sunxi_64cnt {
 	u32 hi;			/* 0xa8 */
 };
 
-/* Watchdog */
-struct sunxi_wdog {
-	u32 ctl;		/* 0x90 */
-	u32 mode;		/* 0x94 */
-};
-
 /* Rtc */
 struct sunxi_rtc {
 	u32 ctl;		/* 0x100 */
@@ -77,15 +67,20 @@ struct sunxi_timer_reg {
 	struct sunxi_timer timer[6];	/* We have 6 timers */
 	u8 res2[16];
 	struct sunxi_avs avs;
-	struct sunxi_wdog wdog;
-	u8 res3[8];
-	struct sunxi_64cnt cnt64;
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+	struct sunxi_wdog wdog;	/* 0x90 */
+	/* XXX the following is not accurate for sun5i/sun7i */
+	struct sunxi_64cnt cnt64;	/* 0xa0 */
 	u8 res4[0x58];
 	struct sunxi_rtc rtc;
 	struct sunxi_alarm alarm;
 	struct sunxi_tgp tgp[4];
 	u8 res5[8];
 	u32 cpu_cfg;
+#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || ... */
+	u8 res3[16];
+	struct sunxi_wdog wdog[5];	/* We have 5 watchdogs */
+#endif
 };
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h b/arch/arm/include/asm/arch-sunxi/watchdog.h
new file mode 100644
index 00000000000..8108be97bab
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/watchdog.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2014
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * Watchdog register definitions
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_WATCHDOG_H_
+#define _SUNXI_WATCHDOG_H_
+
+#define WDT_CTRL_RESTART	(0x1 << 0)
+#define WDT_CTRL_KEY		(0x0a57 << 1)
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+
+#define WDT_MODE_EN		(0x1 << 0)
+#define WDT_MODE_RESET_EN	(0x1 << 1)
+
+struct sunxi_wdog {
+	u32 ctl;		/* 0x00 */
+	u32 mode;		/* 0x04 */
+	u32 res[2];
+};
+
+#else
+
+#define WDT_CFG_RESET		(0x1)
+#define WDT_MODE_EN		(0x1)
+
+struct sunxi_wdog {
+	u32 irq_en;		/* 0x00 */
+	u32 irq_sta;		/* 0x04 */
+	u32 res1[2];
+	u32 ctl;		/* 0x10 */
+	u32 cfg;		/* 0x14 */
+	u32 mode;		/* 0x18 */
+	u32 res2;
+};
+
+#endif
+
+#endif /* _SUNXI_WATCHDOG_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h
index ff773646cbe..783bb3c0fa1 100644
--- a/arch/arm/include/asm/arch-tegra/board.h
+++ b/arch/arm/include/asm/arch-tegra/board.h
@@ -24,10 +24,11 @@ void gpio_early_init(void);  /* overrideable GPIO config        */
  * an empty stub function will be called.
  */
 
-void pinmux_init(void);      /* overrideable general pinmux setup */
-void pin_mux_usb(void);      /* overrideable USB pinmux setup     */
-void pin_mux_spi(void);      /* overrideable SPI pinmux setup     */
-void pin_mux_nand(void);     /* overrideable NAND pinmux setup    */
-void pin_mux_display(void);  /* overrideable DISPLAY pinmux setup */
+void pinmux_init(void);      /* overridable general pinmux setup */
+void pin_mux_usb(void);      /* overridable USB pinmux setup     */
+void pin_mux_spi(void);      /* overridable SPI pinmux setup     */
+void pin_mux_nand(void);     /* overridable NAND pinmux setup    */
+void pin_mux_mmc(void);      /* overridable mmc pinmux setup     */
+void pin_mux_display(void);  /* overridable DISPLAY pinmux setup */
 
 #endif
diff --git a/arch/arm/include/asm/arch-tegra114/mc.h b/arch/arm/include/asm/arch-tegra114/mc.h
new file mode 100644
index 00000000000..044b1e0b399
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/mc.h
@@ -0,0 +1,37 @@
+/*
+ *  (C) Copyright 2014
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA114_MC_H_
+#define _TEGRA114_MC_H_
+
+/**
+ * Defines the memory controller registers we need/care about
+ */
+struct mc_ctlr {
+	u32 reserved0[4];			/* offset 0x00 - 0x0C */
+	u32 mc_smmu_config;			/* offset 0x10 */
+	u32 mc_smmu_tlb_config;			/* offset 0x14 */
+	u32 mc_smmu_ptc_config;			/* offset 0x18 */
+	u32 mc_smmu_ptb_asid;			/* offset 0x1C */
+	u32 mc_smmu_ptb_data;			/* offset 0x20 */
+	u32 reserved1[3];			/* offset 0x24 - 0x2C */
+	u32 mc_smmu_tlb_flush;			/* offset 0x30 */
+	u32 mc_smmu_ptc_flush;			/* offset 0x34 */
+	u32 reserved2[6];			/* offset 0x38 - 0x4C */
+	u32 mc_emem_cfg;			/* offset 0x50 */
+	u32 mc_emem_adr_cfg;			/* offset 0x54 */
+	u32 mc_emem_adr_cfg_dev0;		/* offset 0x58 */
+	u32 mc_emem_adr_cfg_dev1;		/* offset 0x5C */
+	u32 reserved3[12];			/* offset 0x60 - 0x8C */
+	u32 mc_emem_arb_reserved[28];		/* offset 0x90 - 0xFC */
+	u32 reserved4[338];			/* offset 0x100 - 0x644 */
+	u32 mc_video_protect_bom;		/* offset 0x648 */
+	u32 mc_video_protect_size_mb;		/* offset 0x64c */
+	u32 mc_video_protect_reg_ctrl;		/* offset 0x650 */
+};
+
+#endif	/* _TEGRA114_MC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h
index 5d426b524a1..c3d061ec586 100644
--- a/arch/arm/include/asm/arch-tegra114/tegra.h
+++ b/arch/arm/include/asm/arch-tegra114/tegra.h
@@ -19,6 +19,7 @@
 
 #define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T114 */
 #define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
+#define NV_PA_MC_BASE		0x70019000
 
 #include <asm/arch-tegra/tegra.h>
 
diff --git a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h b/arch/arm/include/asm/arch-tegra114/tegra114_spi.h
deleted file mode 100644
index 48197bc27fc..00000000000
--- a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * NVIDIA Tegra SPI controller
- *
- * Copyright 2010-2013 NVIDIA Corporation
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA114_SPI_H_
-#define _TEGRA114_SPI_H_
-
-#include <asm/types.h>
-
-int tegra114_spi_init(int *node_list, int count);
-int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs);
-struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs,
-				  unsigned int max_hz, unsigned int mode);
-void tegra114_spi_free_slave(struct spi_slave *slave);
-int tegra114_spi_claim_bus(struct spi_slave *slave);
-void tegra114_spi_cs_activate(struct spi_slave *slave);
-void tegra114_spi_cs_deactivate(struct spi_slave *slave);
-int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-		     const void *data_out, void *data_in, unsigned long flags);
-
-#endif	/* _TEGRA114_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/mc.h b/arch/arm/include/asm/arch-tegra20/mc.h
new file mode 100644
index 00000000000..9c6e3ffb6f4
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/mc.h
@@ -0,0 +1,36 @@
+/*
+ *  (C) Copyright 2014
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA20_MC_H_
+#define _TEGRA20_MC_H_
+
+/**
+ * Defines the memory controller registers we need/care about
+ */
+struct mc_ctlr {
+	u32 reserved0[3];			/* offset 0x00 - 0x08 */
+	u32 mc_emem_cfg;			/* offset 0x0C */
+	u32 mc_emem_adr_cfg;			/* offset 0x10 */
+	u32 mc_emem_arb_cfg0;			/* offset 0x14 */
+	u32 mc_emem_arb_cfg1;			/* offset 0x18 */
+	u32 mc_emem_arb_cfg2;			/* offset 0x1C */
+	u32 reserved1;				/* offset 0x20 */
+	u32 mc_gart_cfg;			/* offset 0x24 */
+	u32 mc_gart_entry_addr;			/* offset 0x28 */
+	u32 mc_gart_entry_data;			/* offset 0x2C */
+	u32 mc_gart_error_req;			/* offset 0x30 */
+	u32 mc_gart_error_addr;			/* offset 0x34 */
+	u32 reserved2;				/* offset 0x38 */
+	u32 mc_timeout_ctrl;			/* offset 0x3C */
+	u32 reserved3[6];			/* offset 0x40 - 0x54 */
+	u32 mc_decerr_emem_others_status;	/* offset 0x58 */
+	u32 mc_decerr_emem_others_adr;		/* offset 0x5C */
+	u32 reserved4[40];			/* offset 0x60 - 0xFC */
+	u32 reserved5[93];			/* offset 0x100 - 0x270 */
+};
+
+#endif	/* _TEGRA20_MC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h
index 18856ac3727..22774abb936 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra.h
@@ -9,6 +9,7 @@
 #define _TEGRA20_H_
 
 #define NV_PA_SDRAM_BASE	0x00000000
+#define NV_PA_MC_BASE		0x7000F000
 
 #include <asm/arch-tegra/tegra.h>
 
diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
deleted file mode 100644
index e8cc68c6eaf..00000000000
--- a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * NVIDIA Tegra20 SPI-FLASH controller
- *
- * Copyright 2010-2012 NVIDIA Corporation
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA20_SPI_H_
-#define _TEGRA20_SPI_H_
-
-#include <asm/types.h>
-
-int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs);
-struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs,
-				  unsigned int max_hz, unsigned int mode);
-void tegra20_spi_free_slave(struct spi_slave *slave);
-int tegra20_spi_init(int *node_list, int count);
-int tegra20_spi_claim_bus(struct spi_slave *slave);
-void tegra20_spi_cs_activate(struct spi_slave *slave);
-void tegra20_spi_cs_deactivate(struct spi_slave *slave);
-int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-	     const void *data_out, void *data_in, unsigned long flags);
-
-#endif	/* _TEGRA20_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
deleted file mode 100644
index 5aa74ddd6d2..00000000000
--- a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * NVIDIA Tegra SPI-SLINK controller
- *
- * Copyright 2010-2013 NVIDIA Corporation
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA30_SPI_H_
-#define _TEGRA30_SPI_H_
-
-#include <asm/types.h>
-
-int tegra30_spi_init(int *node_list, int count);
-int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs);
-struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs,
-				  unsigned int max_hz, unsigned int mode);
-void tegra30_spi_free_slave(struct spi_slave *slave);
-int tegra30_spi_claim_bus(struct spi_slave *slave);
-void tegra30_spi_cs_activate(struct spi_slave *slave);
-void tegra30_spi_cs_deactivate(struct spi_slave *slave);
-int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-		     const void *data_out, void *data_in, unsigned long flags);
-
-#endif	/* _TEGRA30_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/mc.h b/arch/arm/include/asm/arch-tegra30/mc.h
new file mode 100644
index 00000000000..242a1fc64b9
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/mc.h
@@ -0,0 +1,38 @@
+/*
+ *  (C) Copyright 2014
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA30_MC_H_
+#define _TEGRA30_MC_H_
+
+/**
+ * Defines the memory controller registers we need/care about
+ */
+struct mc_ctlr {
+	u32 reserved0[4];			/* offset 0x00 - 0x0C */
+	u32 mc_smmu_config;			/* offset 0x10 */
+	u32 mc_smmu_tlb_config;			/* offset 0x14 */
+	u32 mc_smmu_ptc_config;			/* offset 0x18 */
+	u32 mc_smmu_ptb_asid;			/* offset 0x1C */
+	u32 mc_smmu_ptb_data;			/* offset 0x20 */
+	u32 reserved1[3];			/* offset 0x24 - 0x2C */
+	u32 mc_smmu_tlb_flush;			/* offset 0x30 */
+	u32 mc_smmu_ptc_flush;			/* offset 0x34 */
+	u32 mc_smmu_asid_security;		/* offset 0x38 */
+	u32 reserved2[5];			/* offset 0x3C - 0x4C */
+	u32 mc_emem_cfg;			/* offset 0x50 */
+	u32 mc_emem_adr_cfg;			/* offset 0x54 */
+	u32 mc_emem_adr_cfg_dev0;		/* offset 0x58 */
+	u32 mc_emem_adr_cfg_dev1;		/* offset 0x5C */
+	u32 reserved3[12];			/* offset 0x60 - 0x8C */
+	u32 mc_emem_arb_reserved[28];		/* offset 0x90 - 0xFC */
+	u32 reserved4[338];			/* offset 0x100 - 0x644 */
+	u32 mc_video_protect_bom;		/* offset 0x648 */
+	u32 mc_video_protect_size_mb;		/* offset 0x64c */
+	u32 mc_video_protect_reg_ctrl;		/* offset 0x650 */
+};
+
+#endif	/* _TEGRA30_MC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h
index c02c5d85003..93671793a9f 100644
--- a/arch/arm/include/asm/arch-tegra30/tegra.h
+++ b/arch/arm/include/asm/arch-tegra30/tegra.h
@@ -17,6 +17,7 @@
 #ifndef _TEGRA30_H_
 #define _TEGRA30_H_
 
+#define NV_PA_MC_BASE		0x7000F000
 #define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T30 */
 
 #include <asm/arch-tegra/tegra.h>
diff --git a/arch/arm/include/asm/arch-uniphier/platdevice.h b/arch/arm/include/asm/arch-uniphier/platdevice.h
new file mode 100644
index 00000000000..cdf7d132d44
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/platdevice.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_PLATDEVICE_H
+#define ARCH_PLATDEVICE_H
+
+#include <dm/platdata.h>
+#include <dm/platform_data/serial-uniphier.h>
+
+#define SERIAL_DEVICE(n, ba, clk)					\
+static struct uniphier_serial_platform_data serial_device##n = {	\
+	.base = ba,							\
+	.uartclk = clk							\
+};									\
+U_BOOT_DEVICE(serial##n) = {						\
+	.name = DRIVER_NAME,						\
+	.platdata = &serial_device##n					\
+};
+
+#endif /* ARCH_PLATDEVICE_H */
diff --git a/arch/arm/include/asm/imx-common/mxc_i2c.h b/arch/arm/include/asm/imx-common/mxc_i2c.h
index 182c2f397f1..af861635350 100644
--- a/arch/arm/include/asm/imx-common/mxc_i2c.h
+++ b/arch/arm/include/asm/imx-common/mxc_i2c.h
@@ -52,8 +52,8 @@ struct i2c_pads_info {
 					&mx6q_##name : &mx6s_##name
 #endif
 
-void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
-		struct i2c_pads_info *p);
+int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
+	      struct i2c_pads_info *p);
 void bus_i2c_init(void *base, int speed, int slave_addr,
 		int (*idle_bus_fn)(void *p), void *p);
 int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf,
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index 560924e83ff..d4a447b2b8a 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -1107,6 +1107,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_ARMADILLO_800EVA     3863
 #define MACH_TYPE_KZM9G                4140
 #define MACH_TYPE_COLIBRI_T30          4493
+#define MACH_TYPE_APALIS_T30           4513
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type
@@ -14248,6 +14249,18 @@ extern unsigned int __machine_arch_type;
 # define machine_is_colibri_t30()	(0)
 #endif
 
+#ifdef CONFIG_MACH_APALIS_T30
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_APALIS_T30
+# endif
+# define machine_is_apalis_t30()	(machine_arch_type == MACH_TYPE_APALIS_T30)
+#else
+# define machine_is_apalis_t30()	(0)
+#endif
+
 /*
  * These have not yet been registered
  */
diff --git a/arch/arm/include/asm/omap_gpio.h b/arch/arm/include/asm/omap_gpio.h
index 5d25d04c3bf..839af54d482 100644
--- a/arch/arm/include/asm/omap_gpio.h
+++ b/arch/arm/include/asm/omap_gpio.h
@@ -23,6 +23,21 @@
 
 #include <asm/arch/cpu.h>
 
+enum gpio_method {
+	METHOD_GPIO_24XX	= 4,
+};
+
+#ifdef CONFIG_DM_GPIO
+
+/* Information about a GPIO bank */
+struct omap_gpio_platdata {
+	int bank_index;
+	ulong base;	/* address of registers in physical memory */
+	enum gpio_method method;
+};
+
+#else
+
 struct gpio_bank {
 	void *base;
 	int method;
@@ -30,8 +45,6 @@ struct gpio_bank {
 
 extern const struct gpio_bank *const omap_gpio_bank;
 
-#define METHOD_GPIO_24XX	4
-
 /**
  * Check if gpio is valid.
  *
@@ -39,4 +52,6 @@ extern const struct gpio_bank *const omap_gpio_bank;
  * @return 1 if ok, 0 on error
  */
 int gpio_is_valid(int gpio);
+#endif
+
 #endif /* _GPIO_H_ */
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index e5daf891271..8acd7cd1bd5 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -7,7 +7,7 @@
 #ifndef	_ASM_SPL_H_
 #define	_ASM_SPL_H_
 
-#if defined(CONFIG_OMAP) || defined(CONFIG_SOCFPGA) \
+#if defined(CONFIG_OMAP) \
 	|| defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \
 	|| defined(CONFIG_EXYNOS4210)
 /* Platform-specific defines */
diff --git a/arch/arm/include/asm/arch-keystone/keystone_nav.h b/arch/arm/include/asm/ti-common/keystone_nav.h
index ab81eaf1fda..696d8c6fc09 100644
--- a/arch/arm/include/asm/arch-keystone/keystone_nav.h
+++ b/arch/arm/include/asm/ti-common/keystone_nav.h
@@ -13,10 +13,6 @@
 #include <asm/arch/hardware.h>
 #include <asm/io.h>
 
-enum soc_type_t {
-	k2hk
-};
-
 #define QM_OK                    0
 #define QM_ERR                  -1
 #define QM_DESC_TYPE_HOST        0
@@ -173,6 +169,8 @@ struct pktdma_cfg {
 	u32			rx_flow; /* flow that is used for RX */
 };
 
+extern struct pktdma_cfg netcp_pktdma;
+
 /*
  * packet dma user allocates memory for rx buffers
  * and describe it in the following structure
@@ -184,10 +182,10 @@ struct rx_buff_desc {
 	u32	rx_flow;
 };
 
-int netcp_close(void);
-int netcp_init(struct rx_buff_desc *rx_buffers);
-int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2);
-void *netcp_recv(u32 **pkt, int *num_bytes);
-void netcp_release_rxhd(void *hd);
+int ksnav_close(struct pktdma_cfg *pktdma);
+int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers);
+int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2);
+void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes);
+void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd);
 
 #endif  /* _KEYSTONE_NAV_H_ */
diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h
new file mode 100644
index 00000000000..011c03cf888
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/keystone_net.h
@@ -0,0 +1,249 @@
+/*
+ * emac definitions for keystone2 devices
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _KEYSTONE_NET_H_
+#define _KEYSTONE_NET_H_
+
+#include <asm/io.h>
+
+/* EMAC */
+#ifdef CONFIG_KSNET_NETCP_V1_0
+
+#define GBETH_BASE			(CONFIG_KSNET_NETCP_BASE + 0x00090000)
+#define EMAC_EMACSL_BASE_ADDR		(GBETH_BASE + 0x900)
+#define EMAC_MDIO_BASE_ADDR		(GBETH_BASE + 0x300)
+#define EMAC_SGMII_BASE_ADDR		(GBETH_BASE + 0x100)
+#define DEVICE_EMACSL_BASE(x)		(EMAC_EMACSL_BASE_ADDR + (x) * 0x040)
+
+/* Register offsets */
+#define CPGMACSL_REG_CTL		0x04
+#define CPGMACSL_REG_STATUS		0x08
+#define CPGMACSL_REG_RESET		0x0c
+#define CPGMACSL_REG_MAXLEN		0x10
+
+#elif defined CONFIG_KSNET_NETCP_V1_5
+
+#define GBETH_BASE			(CONFIG_KSNET_NETCP_BASE + 0x00200000)
+#define CPGMACSL_REG_RX_PRI_MAP		0x020
+#define EMAC_EMACSL_BASE_ADDR		(GBETH_BASE + 0x22000)
+#define EMAC_MDIO_BASE_ADDR		(GBETH_BASE + 0x00f00)
+#define EMAC_SGMII_BASE_ADDR		(GBETH_BASE + 0x00100)
+#define DEVICE_EMACSL_BASE(x)		(EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
+
+/* Register offsets */
+#define CPGMACSL_REG_CTL		0x330
+#define CPGMACSL_REG_STATUS		0x334
+#define CPGMACSL_REG_RESET		0x338
+#define CPGMACSL_REG_MAXLEN		0x024
+
+#endif
+
+#define KEYSTONE2_EMAC_GIG_ENABLE
+
+#define MAC_ID_BASE_ADDR		CONFIG_KSNET_MAC_ID_BASE
+
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ		(clk_get_rate(pass_pll_clk))
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ		2500000	/* 2.5 MHz */
+
+/* MII Status Register */
+#define MII_STATUS_REG			1
+#define MII_STATUS_LINK_MASK		0x4
+
+#define MDIO_CONTROL_IDLE		0x80000000
+#define MDIO_CONTROL_ENABLE		0x40000000
+#define MDIO_CONTROL_FAULT_ENABLE	0x40000
+#define MDIO_CONTROL_FAULT		0x80000
+#define MDIO_USERACCESS0_GO		0x80000000
+#define MDIO_USERACCESS0_WRITE_READ	0x0
+#define MDIO_USERACCESS0_WRITE_WRITE	0x40000000
+#define MDIO_USERACCESS0_ACK		0x20000000
+
+#define EMAC_MACCONTROL_MIIEN_ENABLE		0x20
+#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE	0x1
+#define EMAC_MACCONTROL_GIGABIT_ENABLE		BIT(7)
+#define EMAC_MACCONTROL_GIGFORCE		BIT(17)
+#define EMAC_MACCONTROL_RMIISPEED_100		BIT(15)
+
+#define EMAC_MIN_ETHERNET_PKT_SIZE		60
+
+struct mac_sl_cfg {
+	u_int32_t max_rx_len;	/* Maximum receive packet length. */
+	u_int32_t ctl;		/* Control bitfield */
+};
+
+/**
+ * Definition: Control bitfields used in the ctl field of mac_sl_cfg
+ */
+#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES	BIT(24)
+#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES	BIT(23)
+#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES	BIT(22)
+#define GMACSL_RX_ENABLE_EXT_CTL		BIT(18)
+#define GMACSL_RX_ENABLE_GIG_FORCE		BIT(17)
+#define GMACSL_RX_ENABLE_IFCTL_B		BIT(16)
+#define GMACSL_RX_ENABLE_IFCTL_A		BIT(15)
+#define GMACSL_RX_ENABLE_CMD_IDLE		BIT(11)
+#define GMACSL_TX_ENABLE_SHORT_GAP		BIT(10)
+#define GMACSL_ENABLE_GIG_MODE			BIT(7)
+#define GMACSL_TX_ENABLE_PACE			BIT(6)
+#define GMACSL_ENABLE				BIT(5)
+#define GMACSL_TX_ENABLE_FLOW_CTL		BIT(4)
+#define GMACSL_RX_ENABLE_FLOW_CTL		BIT(3)
+#define GMACSL_ENABLE_LOOPBACK			BIT(1)
+#define GMACSL_ENABLE_FULL_DUPLEX		BIT(0)
+
+/* EMAC SL function return values */
+#define GMACSL_RET_OK				0
+#define GMACSL_RET_INVALID_PORT			-1
+#define GMACSL_RET_WARN_RESET_INCOMPLETE	-2
+#define GMACSL_RET_WARN_MAXLEN_TOO_BIG		-3
+#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE	-4
+
+/* EMAC SL register definitions */
+#define DEVICE_EMACSL_RESET_POLL_COUNT		100
+
+/* Soft reset register values */
+#define CPGMAC_REG_RESET_VAL_RESET_MASK		BIT(0)
+#define CPGMAC_REG_RESET_VAL_RESET		BIT(0)
+#define CPGMAC_REG_MAXLEN_LEN			0x3fff
+
+/* CPSW */
+/* Control bitfields */
+#define CPSW_CTL_P2_PASS_PRI_TAGGED		BIT(5)
+#define CPSW_CTL_P1_PASS_PRI_TAGGED		BIT(4)
+#define CPSW_CTL_P0_PASS_PRI_TAGGED		BIT(3)
+#define CPSW_CTL_P0_ENABLE			BIT(2)
+#define CPSW_CTL_VLAN_AWARE			BIT(1)
+#define CPSW_CTL_FIFO_LOOPBACK			BIT(0)
+
+#define DEVICE_CPSW_NUM_PORTS			CONFIG_KSNET_CPSW_NUM_PORTS
+#define DEVICE_N_GMACSL_PORTS			(DEVICE_CPSW_NUM_PORTS - 1)
+
+#ifdef CONFIG_KSNET_NETCP_V1_0
+
+#define DEVICE_CPSW_BASE			(GBETH_BASE + 0x800)
+#define CPSW_REG_CTL				0x004
+#define CPSW_REG_STAT_PORT_EN			0x00c
+#define CPSW_REG_MAXLEN				0x040
+#define CPSW_REG_ALE_CONTROL			0x608
+#define CPSW_REG_ALE_PORTCTL(x)			(0x640 + (x) * 4)
+#define CPSW_REG_VAL_STAT_ENABLE_ALL		0xf
+
+#elif defined CONFIG_KSNET_NETCP_V1_5
+
+#define DEVICE_CPSW_BASE			(GBETH_BASE + 0x20000)
+#define CPSW_REG_CTL				0x00004
+#define CPSW_REG_STAT_PORT_EN			0x00014
+#define CPSW_REG_MAXLEN				0x01024
+#define CPSW_REG_ALE_CONTROL			0x1e008
+#define CPSW_REG_ALE_PORTCTL(x)			(0x1e040 + (x) * 4)
+#define CPSW_REG_VAL_STAT_ENABLE_ALL		0x1ff
+
+#endif
+
+#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE	((u_int32_t)0xc0000000)
+#define CPSW_REG_VAL_ALE_CTL_BYPASS		((u_int32_t)0x00000010)
+#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE	0x3
+
+#define target_get_switch_ctl()			CPSW_CTL_P0_ENABLE
+#define SWITCH_MAX_PKT_SIZE			9000
+
+/* SGMII */
+#define SGMII_REG_STATUS_LOCK			BIT(4)
+#define SGMII_REG_STATUS_LINK			BIT(0)
+#define SGMII_REG_STATUS_AUTONEG		BIT(2)
+#define SGMII_REG_CONTROL_AUTONEG		BIT(0)
+#define SGMII_REG_CONTROL_MASTER		BIT(5)
+#define SGMII_REG_MR_ADV_ENABLE			BIT(0)
+#define SGMII_REG_MR_ADV_LINK			BIT(15)
+#define SGMII_REG_MR_ADV_FULL_DUPLEX		BIT(12)
+#define SGMII_REG_MR_ADV_GIG_MODE		BIT(11)
+
+#define SGMII_LINK_MAC_MAC_AUTONEG		0
+#define SGMII_LINK_MAC_PHY			1
+#define SGMII_LINK_MAC_MAC_FORCED		2
+#define SGMII_LINK_MAC_FIBER			3
+#define SGMII_LINK_MAC_PHY_FORCED		4
+
+#ifdef CONFIG_KSNET_NETCP_V1_0
+#define SGMII_OFFSET(x)		((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
+#elif defined CONFIG_KSNET_NETCP_V1_5
+#define SGMII_OFFSET(x)		((x) * 0x100)
+#endif
+
+#define SGMII_IDVER_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
+#define SGMII_SRESET_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
+#define SGMII_CTL_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
+#define SGMII_STATUS_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
+#define SGMII_MRADV_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
+#define SGMII_LPADV_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
+#define SGMII_TXCFG_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
+#define SGMII_RXCFG_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
+#define SGMII_AUXCFG_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
+
+/* PSS */
+#ifdef CONFIG_KSNET_NETCP_V1_0
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR	(CONFIG_KSNET_NETCP_BASE + 0x604)
+#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI	0x06060606
+#define hw_config_streaming_switch()\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
+
+#elif defined CONFIG_KSNET_NETCP_V1_5
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR	(CONFIG_KSNET_NETCP_BASE + 0x500)
+#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI	0x0
+
+#define hw_config_streaming_switch()\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+	       DEVICE_PSTREAM_CFG_REG_ADDR);\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+	       DEVICE_PSTREAM_CFG_REG_ADDR+4);\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+	       DEVICE_PSTREAM_CFG_REG_ADDR+8);\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+	       DEVICE_PSTREAM_CFG_REG_ADDR+12);
+
+#endif
+
+/* EMAC MDIO Registers Structure */
+struct mdio_regs {
+	u32 version;
+	u32 control;
+	u32 alive;
+	u32 link;
+	u32 linkintraw;
+	u32 linkintmasked;
+	u32 rsvd0[2];
+	u32 userintraw;
+	u32 userintmasked;
+	u32 userintmaskset;
+	u32 userintmaskclear;
+	u32 rsvd1[20];
+	u32 useraccess0;
+	u32 userphysel0;
+	u32 useraccess1;
+	u32 userphysel1;
+};
+
+struct eth_priv_t {
+	char int_name[32];
+	int rx_flow;
+	int phy_addr;
+	int slave_port;
+	int sgmii_link_type;
+	struct phy_device *phy_dev;
+};
+
+int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
+void sgmii_serdes_setup_156p25mhz(void);
+void sgmii_serdes_shutdown(void);
+
+#endif  /* _KEYSTONE_NET_H_ */
diff --git a/arch/arm/include/asm/ti-common/keystone_serdes.h b/arch/arm/include/asm/ti-common/keystone_serdes.h
new file mode 100644
index 00000000000..2e92411404b
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/keystone_serdes.h
@@ -0,0 +1,55 @@
+/*
+ * Texas Instruments Keystone SerDes driver
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __TI_KEYSTONE_SERDES_H__
+#define __TI_KEYSTONE_SERDES_H__
+
+/* SERDES Reference clock */
+enum ks2_serdes_clock {
+	SERDES_CLOCK_100M,		/* 100 MHz */
+	SERDES_CLOCK_122P88M,		/* 122.88 MHz */
+	SERDES_CLOCK_125M,		/* 125 MHz */
+	SERDES_CLOCK_156P25M,		/* 156.25 MHz */
+	SERDES_CLOCK_312P5M,		/* 312.5 MHz */
+};
+
+/* SERDES Lane Baud Rate */
+enum ks2_serdes_rate {
+	SERDES_RATE_4P9152G,		/* 4.9152 GBaud */
+	SERDES_RATE_5G,			/* 5 GBaud */
+	SERDES_RATE_6P144G,		/* 6.144 GBaud */
+	SERDES_RATE_6P25G,		/* 6.25 GBaud */
+	SERDES_RATE_10p3125g,		/* 10.3215 GBaud */
+	SERDES_RATE_12p5g,		/* 12.5 GBaud */
+};
+
+/* SERDES Lane Rate Mode */
+enum ks2_serdes_rate_mode {
+	SERDES_FULL_RATE,
+	SERDES_HALF_RATE,
+	SERDES_QUARTER_RATE,
+};
+
+/* SERDES PHY TYPE */
+enum ks2_serdes_interface {
+	SERDES_PHY_SGMII,
+	SERDES_PHY_PCSR,		/* XGE SERDES */
+};
+
+struct ks2_serdes {
+	enum ks2_serdes_clock clk;
+	enum ks2_serdes_rate rate;
+	enum ks2_serdes_rate_mode rate_mode;
+	enum ks2_serdes_interface intf;
+	u32 loopback;
+};
+
+int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes);
+
+#endif /* __TI_KEYSTONE_SERDES_H__ */
diff --git a/arch/arm/include/asm/ti-common/ti-edma3.h b/arch/arm/include/asm/ti-common/ti-edma3.h
new file mode 100644
index 00000000000..5adc1dac0e6
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/ti-edma3.h
@@ -0,0 +1,121 @@
+/*
+ * Enhanced Direct Memory Access (EDMA3) Controller
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _EDMA3_H_
+#define _EDMA3_H_
+
+#include <linux/stddef.h>
+
+#define EDMA3_PARSET_NULL_LINK			0xffff
+
+/*
+ * All parameter RAM set options
+ * opt field in edma3_param_set_config structure
+ */
+#define EDMA3_SLOPT_PRIV_LEVEL			BIT(31)
+#define EDMA3_SLOPT_PRIV_ID(id)			((0xf & (id)) << 24)
+#define EDMA3_SLOPT_INTERM_COMP_CHAIN_ENB	BIT(23)
+#define EDMA3_SLOPT_TRANS_COMP_CHAIN_ENB	BIT(22)
+#define EDMA3_SLOPT_INTERM_COMP_INT_ENB		BIT(21)
+#define EDMA3_SLOPT_TRANS_COMP_INT_ENB		BIT(20)
+#define EDMA3_SLOPT_COMP_CODE(code)		((0x3f & (code)) << 12)
+#define EDMA3_SLOPT_FIFO_WIDTH_8		0
+#define EDMA3_SLOPT_FIFO_WIDTH_16		(1 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_32		(2 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_64		(3 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_128		(4 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_256		(5 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_SET(w)		((w & 0x7) << 8)
+#define EDMA3_SLOPT_STATIC			BIT(3)
+#define EDMA3_SLOPT_AB_SYNC			BIT(2)
+#define EDMA3_SLOPT_DST_ADDR_CONST_MODE		BIT(1)
+#define EDMA3_SLOPT_SRC_ADDR_CONST_MODE		BIT(0)
+
+enum edma3_address_mode {
+	INCR = 0,
+	FIFO = 1
+};
+
+enum edma3_fifo_width {
+	W8BIT = 0,
+	W16BIT = 1,
+	W32BIT = 2,
+	W64BIT = 3,
+	W128BIT = 4,
+	W256BIT = 5
+};
+
+enum edma3_sync_dimension {
+	ASYNC = 0,
+	ABSYNC = 1
+};
+
+/* PaRAM slots are laid out like this */
+struct edma3_slot_layout {
+	u32 opt;
+	u32 src;
+	u32 a_b_cnt;
+	u32 dst;
+	u32 src_dst_bidx;
+	u32 link_bcntrld;
+	u32 src_dst_cidx;
+	u32 ccnt;
+} __packed;
+
+/*
+ * Use this to assign trigger word number of edma3_slot_layout struct.
+ * trigger_word_name - is the exact name from edma3_slot_layout.
+ */
+#define EDMA3_TWORD(trigger_word_name)\
+		(offsetof(struct edma3_slot_layout, trigger_word_name) / 4)
+
+struct edma3_slot_config {
+	u32 opt;
+	u32 src;
+	u32 dst;
+	int bcnt;
+	int acnt;
+	int ccnt;
+	int src_bidx;
+	int dst_bidx;
+	int src_cidx;
+	int dst_cidx;
+	int bcntrld;
+	int link;
+};
+
+struct edma3_channel_config {
+	int slot;
+	int chnum;
+	int complete_code;	/* indicate pending complete interrupt */
+	int trigger_slot_word;	/* only used for qedma */
+};
+
+void qedma3_start(u32 base, struct edma3_channel_config *cfg);
+void qedma3_stop(u32 base, struct edma3_channel_config *cfg);
+void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg);
+int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg);
+void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param);
+void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param);
+
+void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode,
+		    enum edma3_fifo_width width);
+void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx);
+void edma3_set_dest_addr(u32 base, int slot, u32 dst);
+
+void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode,
+		   enum edma3_fifo_width width);
+void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx);
+void edma3_set_src_addr(u32 base, int slot, u32 src);
+
+void edma3_set_transfer_params(u32 base, int slot, int acnt,
+			       int bcnt, int ccnt, u16 bcnt_rld,
+			       enum edma3_sync_dimension sync_mode);
+
+#endif
diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h
index b16694c72f8..f97f3dd1496 100644
--- a/arch/arm/include/asm/u-boot-arm.h
+++ b/arch/arm/include/asm/u-boot-arm.h
@@ -45,4 +45,19 @@ void	reset_timer_masked	(void);
 ulong	get_timer_masked	(void);
 void	udelay_masked		(unsigned long usec);
 
+/* calls to c from vectors.S */
+void bad_mode(void);
+void do_undefined_instruction(struct pt_regs *pt_regs);
+void do_software_interrupt(struct pt_regs *pt_regs);
+void do_prefetch_abort(struct pt_regs *pt_regs);
+void do_data_abort(struct pt_regs *pt_regs);
+void do_not_used(struct pt_regs *pt_regs);
+#ifdef CONFIG_ARM64
+void do_fiq(struct pt_regs *pt_regs, unsigned int esr);
+void do_irq(struct pt_regs *pt_regs, unsigned int esr);
+#else
+void do_fiq(struct pt_regs *pt_regs);
+void do_irq(struct pt_regs *pt_regswq);
+#endif
+
 #endif	/* _U_BOOT_ARM_H_ */
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 76adaf3aa4a..f6062557e66 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -34,6 +34,7 @@
 #include <onenand_uboot.h>
 #include <mmc.h>
 #include <scsi.h>
+#include <status_led.h>
 #include <libfdt.h>
 #include <fdtdec.h>
 #include <post.h>
@@ -63,25 +64,15 @@ extern void dataflash_print_info(void);
  ************************************************************************
  * May be supplied by boards if desired
  */
-inline void __coloured_LED_init(void) {}
-void coloured_LED_init(void)
-	__attribute__((weak, alias("__coloured_LED_init")));
-inline void __red_led_on(void) {}
-void red_led_on(void) __attribute__((weak, alias("__red_led_on")));
-inline void __red_led_off(void) {}
-void red_led_off(void) __attribute__((weak, alias("__red_led_off")));
-inline void __green_led_on(void) {}
-void green_led_on(void) __attribute__((weak, alias("__green_led_on")));
-inline void __green_led_off(void) {}
-void green_led_off(void) __attribute__((weak, alias("__green_led_off")));
-inline void __yellow_led_on(void) {}
-void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on")));
-inline void __yellow_led_off(void) {}
-void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off")));
-inline void __blue_led_on(void) {}
-void blue_led_on(void) __attribute__((weak, alias("__blue_led_on")));
-inline void __blue_led_off(void) {}
-void blue_led_off(void) __attribute__((weak, alias("__blue_led_off")));
+__weak void coloured_LED_init(void) {}
+__weak void red_led_on(void) {}
+__weak void red_led_off(void) {}
+__weak void green_led_on(void) {}
+__weak void green_led_off(void) {}
+__weak void yellow_led_on(void) {}
+__weak void yellow_led_off(void) {}
+__weak void blue_led_on(void) {}
+__weak void blue_led_off(void) {}
 
 /*
  ************************************************************************
@@ -198,27 +189,21 @@ static int arm_pci_init(void)
  */
 typedef int (init_fnc_t) (void);
 
-void __dram_init_banksize(void)
+__weak void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size =  gd->ram_size;
 }
-void dram_init_banksize(void)
-	__attribute__((weak, alias("__dram_init_banksize")));
 
-int __arch_cpu_init(void)
+__weak int arch_cpu_init(void)
 {
 	return 0;
 }
-int arch_cpu_init(void)
-	__attribute__((weak, alias("__arch_cpu_init")));
 
-int __power_init_board(void)
+__weak int power_init_board(void)
 {
 	return 0;
 }
-int power_init_board(void)
-	__attribute__((weak, alias("__power_init_board")));
 
 	/* Record the board_init_f() bootstage (after arch_cpu_init()) */
 static int mark_bootstage(void)
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 4949d573af8..cdb19751058 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -15,6 +15,7 @@
 #include <common.h>
 #include <command.h>
 #include <image.h>
+#include <vxworks.h>
 #include <u-boot/zlib.h>
 #include <asm/byteorder.h>
 #include <libfdt.h>
diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
index f6b7c03578b..4dacfd941f6 100644
--- a/arch/arm/lib/interrupts.c
+++ b/arch/arm/lib/interrupts.c
@@ -21,12 +21,15 @@
 
 #include <common.h>
 #include <asm/proc-armv/ptrace.h>
+#include <asm/u-boot-arm.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_USE_IRQ
 int interrupt_init (void)
 {
+	unsigned long cpsr;
+
 	/*
 	 * setup up stacks if necessary
 	 */
@@ -34,6 +37,31 @@ int interrupt_init (void)
 	IRQ_STACK_START_IN = gd->irq_sp + 8;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 
+
+	__asm__ __volatile__("mrs %0, cpsr\n"
+			     : "=r" (cpsr)
+			     :
+			     : "memory");
+
+	__asm__ __volatile__("msr cpsr_c, %0\n"
+			     "mov sp, %1\n"
+			     :
+			     : "r" (IRQ_MODE | I_BIT | F_BIT | (cpsr & ~FIQ_MODE)),
+			       "r" (IRQ_STACK_START)
+			     : "memory");
+
+	__asm__ __volatile__("msr cpsr_c, %0\n"
+			     "mov sp, %1\n"
+			     :
+			     : "r" (FIQ_MODE | I_BIT | F_BIT | (cpsr & ~IRQ_MODE)),
+			       "r" (FIQ_STACK_START)
+			     : "memory");
+
+	__asm__ __volatile__("msr cpsr_c, %0"
+			     :
+			     : "r" (cpsr)
+			     : "memory");
+
 	return arch_interrupt_init();
 }
 
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index 80352515631..b4a258ce5c7 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -6,6 +6,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <asm-offsets.h>
+#include <config.h>
 #include <linux/linkage.h>
 
 /*
@@ -52,6 +54,34 @@ fixnext:
 	cmp	r2, r3
 	blo	fixloop
 
+	/*
+	 * Relocate the exception vectors
+	 */
+#ifdef CONFIG_HAS_VBAR
+	/*
+	 * If the ARM processor has the security extensions,
+	 * use VBAR to relocate the exception vectors.
+	 */
+	ldr	r0, [r9, #GD_RELOCADDR]	/* r0 = gd->relocaddr */
+	mcr     p15, 0, r0, c12, c0, 0  /* Set VBAR */
+#else
+	/*
+	 * Copy the relocated exception vectors to the
+	 * correct address
+	 * CP15 c1 V bit gives us the location of the vectors:
+	 * 0x00000000 or 0xFFFF0000.
+	 */
+	ldr	r0, [r9, #GD_RELOCADDR]	/* r0 = gd->relocaddr */
+	mrc	p15, 0, r2, c1, c0, 0	/* V bit (bit[13]) in CP15 c1 */
+	ands	r2, r2, #(1 << 13)
+	ldreq	r1, =0x00000000 	/* If V=0 */
+	ldrne	r1, =0xFFFF0000 	/* If V=1 */
+	ldmia	r0!, {r2-r8,r10}
+	stmia	r1!, {r2-r8,r10}
+	ldmia	r0!, {r2-r8,r10}
+	stmia	r1!, {r2-r8,r10}
+#endif
+
 relocate_done:
 
 #ifdef __XSCALE__
diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index 0cb87cee7f6..49238ed21ed 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -33,7 +33,7 @@
  *************************************************************************
  */
 
-	.section ".vectors", "x"
+	.section ".vectors", "ax"
 
 /*
  *************************************************************************
diff --git a/arch/arm/mvebu-common/Makefile b/arch/arm/mvebu-common/Makefile
new file mode 100644
index 00000000000..9dcab6958c5
--- /dev/null
+++ b/arch/arm/mvebu-common/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= dram.o
+obj-y	+= gpio.o
+obj-$(CONFIG_ARMADA_XP) += mbus.o
+obj-y	+= timer.o
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/mvebu-common/dram.c
index d73ae47c341..db18791a862 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c
+++ b/arch/arm/mvebu-common/dram.c
@@ -10,31 +10,31 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct kw_sdram_bank {
+struct sdram_bank {
 	u32	win_bar;
 	u32	win_sz;
 };
 
-struct kw_sdram_addr_dec {
-	struct kw_sdram_bank	sdram_bank[4];
+struct sdram_addr_dec {
+	struct sdram_bank sdram_bank[4];
 };
 
-#define KW_REG_CPUCS_WIN_ENABLE		(1 << 0)
-#define KW_REG_CPUCS_WIN_WR_PROTECT	(1 << 1)
-#define KW_REG_CPUCS_WIN_WIN0_CS(x)	(((x) & 0x3) << 2)
-#define KW_REG_CPUCS_WIN_SIZE(x)	(((x) & 0xff) << 24)
+#define REG_CPUCS_WIN_ENABLE		(1 << 0)
+#define REG_CPUCS_WIN_WR_PROTECT	(1 << 1)
+#define REG_CPUCS_WIN_WIN0_CS(x)	(((x) & 0x3) << 2)
+#define REG_CPUCS_WIN_SIZE(x)		(((x) & 0xff) << 24)
 
 /*
- * kw_sdram_bar - reads SDRAM Base Address Register
+ * mvebu_sdram_bar - reads SDRAM Base Address Register
  */
-u32 kw_sdram_bar(enum memory_bank bank)
+u32 mvebu_sdram_bar(enum memory_bank bank)
 {
-	struct kw_sdram_addr_dec *base =
-		(struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+	struct sdram_addr_dec *base =
+		(struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
 	u32 result = 0;
 	u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
 
@@ -46,31 +46,31 @@ u32 kw_sdram_bar(enum memory_bank bank)
 }
 
 /*
- * kw_sdram_bs_set - writes SDRAM Bank size
+ * mvebu_sdram_bs_set - writes SDRAM Bank size
  */
-static void kw_sdram_bs_set(enum memory_bank bank, u32 size)
+static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
 {
-	struct kw_sdram_addr_dec *base =
-		(struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+	struct sdram_addr_dec *base =
+		(struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
 	/* Read current register value */
 	u32 reg = readl(&base->sdram_bank[bank].win_sz);
 
 	/* Clear window size */
-	reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF);
+	reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
 
 	/* Set new window size */
-	reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24);
+	reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
 
 	writel(reg, &base->sdram_bank[bank].win_sz);
 }
 
 /*
- * kw_sdram_bs - reads SDRAM Bank size
+ * mvebu_sdram_bs - reads SDRAM Bank size
  */
-u32 kw_sdram_bs(enum memory_bank bank)
+u32 mvebu_sdram_bs(enum memory_bank bank)
 {
-	struct kw_sdram_addr_dec *base =
-		(struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+	struct sdram_addr_dec *base =
+		(struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
 	u32 result = 0;
 	u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
 
@@ -81,15 +81,16 @@ u32 kw_sdram_bs(enum memory_bank bank)
 	return result;
 }
 
-void kw_sdram_size_adjust(enum memory_bank bank)
+void mvebu_sdram_size_adjust(enum memory_bank bank)
 {
 	u32 size;
 
 	/* probe currently equipped RAM size */
-	size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank));
+	size = get_ram_size((void *)mvebu_sdram_bar(bank),
+			    mvebu_sdram_bs(bank));
 
 	/* adjust SDRAM window size accordingly */
-	kw_sdram_bs_set(bank, size);
+	mvebu_sdram_bs_set(bank, size);
 }
 
 #ifndef CONFIG_SYS_BOARD_DRAM_INIT
@@ -99,8 +100,8 @@ int dram_init(void)
 
 	gd->ram_size = 0;
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
-		gd->bd->bi_dram[i].size = kw_sdram_bs(i);
+		gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
+		gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
 		/*
 		 * It is assumed that all memory banks are consecutive
 		 * and without gaps.
@@ -110,7 +111,13 @@ int dram_init(void)
 		if (gd->bd->bi_dram[i].start != gd->ram_size)
 			break;
 
-		gd->ram_size += gd->bd->bi_dram[i].size;
+		/*
+		 * Don't report more than 3GiB of SDRAM, otherwise there is no
+		 * address space left for the internal registers etc.
+		 */
+		if ((gd->ram_size + gd->bd->bi_dram[i].size != 0) &&
+		    (gd->ram_size + gd->bd->bi_dram[i].size <= (3 << 30)))
+			gd->ram_size += gd->bd->bi_dram[i].size;
 
 	}
 
diff --git a/arch/arm/mvebu-common/gpio.c b/arch/arm/mvebu-common/gpio.c
new file mode 100644
index 00000000000..56e54e0a621
--- /dev/null
+++ b/arch/arm/mvebu-common/gpio.c
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+/*
+ * mvebu_config_gpio - GPIO configuration
+ */
+void mvebu_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val,
+		       u32 gpp0_oe, u32 gpp1_oe)
+{
+	struct kwgpio_registers *gpio0reg =
+		(struct kwgpio_registers *)MVEBU_GPIO0_BASE;
+	struct kwgpio_registers *gpio1reg =
+		(struct kwgpio_registers *)MVEBU_GPIO1_BASE;
+
+	/* Init GPIOS to default values as per board requirement */
+	writel(gpp0_oe_val, &gpio0reg->dout);
+	writel(gpp1_oe_val, &gpio1reg->dout);
+	writel(gpp0_oe, &gpio0reg->oe);
+	writel(gpp1_oe, &gpio1reg->oe);
+}
diff --git a/arch/arm/mvebu-common/mbus.c b/arch/arm/mvebu-common/mbus.c
new file mode 100644
index 00000000000..05c9ef2cbbc
--- /dev/null
+++ b/arch/arm/mvebu-common/mbus.c
@@ -0,0 +1,471 @@
+/*
+ * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
+ * 370/XP, Dove, Orion5x and MV78xx0)
+ *
+ * Ported from the Barebox version to U-Boot by:
+ * Stefan Roese <sr@denx.de>
+ *
+ * The Barebox version is:
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on mbus driver from Linux
+ *   (C) Copyright 2008 Marvell Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ * The Marvell EBU SoCs have a configurable physical address space:
+ * the physical address at which certain devices (PCIe, NOR, NAND,
+ * etc.) sit can be configured. The configuration takes place through
+ * two sets of registers:
+ *
+ * - One to configure the access of the CPU to the devices. Depending
+ *   on the families, there are between 8 and 20 configurable windows,
+ *   each can be use to create a physical memory window that maps to a
+ *   specific device. Devices are identified by a tuple (target,
+ *   attribute).
+ *
+ * - One to configure the access to the CPU to the SDRAM. There are
+ *   either 2 (for Dove) or 4 (for other families) windows to map the
+ *   SDRAM into the physical address space.
+ *
+ * This driver:
+ *
+ * - Reads out the SDRAM address decoding windows at initialization
+ *   time, and fills the mbus_dram_info structure with these
+ *   informations. The exported function mv_mbus_dram_info() allow
+ *   device drivers to get those informations related to the SDRAM
+ *   address decoding windows. This is because devices also have their
+ *   own windows (configured through registers that are part of each
+ *   device register space), and therefore the drivers for Marvell
+ *   devices have to configure those device -> SDRAM windows to ensure
+ *   that DMA works properly.
+ *
+ * - Provides an API for platform code or device drivers to
+ *   dynamically add or remove address decoding windows for the CPU ->
+ *   device accesses. This API is mvebu_mbus_add_window_by_id(),
+ *   mvebu_mbus_add_window_remap_by_id() and
+ *   mvebu_mbus_del_window().
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/mbus.h>
+
+#define BIT(nr)			(1UL << (nr))
+
+/* DDR target is the same on all platforms */
+#define TARGET_DDR		0
+
+/* CPU Address Decode Windows registers */
+#define WIN_CTRL_OFF		0x0000
+#define   WIN_CTRL_ENABLE       BIT(0)
+#define   WIN_CTRL_TGT_MASK     0xf0
+#define   WIN_CTRL_TGT_SHIFT    4
+#define   WIN_CTRL_ATTR_MASK    0xff00
+#define   WIN_CTRL_ATTR_SHIFT   8
+#define   WIN_CTRL_SIZE_MASK    0xffff0000
+#define   WIN_CTRL_SIZE_SHIFT   16
+#define WIN_BASE_OFF		0x0004
+#define   WIN_BASE_LOW          0xffff0000
+#define   WIN_BASE_HIGH         0xf
+#define WIN_REMAP_LO_OFF	0x0008
+#define   WIN_REMAP_LOW         0xffff0000
+#define WIN_REMAP_HI_OFF	0x000c
+
+#define ATTR_HW_COHERENCY	(0x1 << 4)
+
+#define DDR_BASE_CS_OFF(n)	(0x0000 + ((n) << 3))
+#define  DDR_BASE_CS_HIGH_MASK  0xf
+#define  DDR_BASE_CS_LOW_MASK   0xff000000
+#define DDR_SIZE_CS_OFF(n)	(0x0004 + ((n) << 3))
+#define  DDR_SIZE_ENABLED       BIT(0)
+#define  DDR_SIZE_CS_MASK       0x1c
+#define  DDR_SIZE_CS_SHIFT      2
+#define  DDR_SIZE_MASK          0xff000000
+
+#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
+
+struct mvebu_mbus_state;
+
+struct mvebu_mbus_soc_data {
+	unsigned int num_wins;
+	unsigned int num_remappable_wins;
+	unsigned int (*win_cfg_offset)(const int win);
+	void (*setup_cpu_target)(struct mvebu_mbus_state *s);
+};
+
+struct mvebu_mbus_state mbus_state
+	__attribute__ ((section(".data")));
+static struct mbus_dram_target_info mbus_dram_info
+	__attribute__ ((section(".data")));
+
+/*
+ * Functions to manipulate the address decoding windows
+ */
+
+static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
+				   int win, int *enabled, u64 *base,
+				   u32 *size, u8 *target, u8 *attr,
+				   u64 *remap)
+{
+	void __iomem *addr = mbus->mbuswins_base +
+		mbus->soc->win_cfg_offset(win);
+	u32 basereg = readl(addr + WIN_BASE_OFF);
+	u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
+
+	if (!(ctrlreg & WIN_CTRL_ENABLE)) {
+		*enabled = 0;
+		return;
+	}
+
+	*enabled = 1;
+	*base = ((u64)basereg & WIN_BASE_HIGH) << 32;
+	*base |= (basereg & WIN_BASE_LOW);
+	*size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
+
+	if (target)
+		*target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
+
+	if (attr)
+		*attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
+
+	if (remap) {
+		if (win < mbus->soc->num_remappable_wins) {
+			u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
+			u32 remap_hi  = readl(addr + WIN_REMAP_HI_OFF);
+			*remap = ((u64)remap_hi << 32) | remap_low;
+		} else {
+			*remap = 0;
+		}
+	}
+}
+
+static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
+				      int win)
+{
+	void __iomem *addr;
+
+	addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
+
+	writel(0, addr + WIN_BASE_OFF);
+	writel(0, addr + WIN_CTRL_OFF);
+	if (win < mbus->soc->num_remappable_wins) {
+		writel(0, addr + WIN_REMAP_LO_OFF);
+		writel(0, addr + WIN_REMAP_HI_OFF);
+	}
+}
+
+/* Checks whether the given window number is available */
+static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
+				     const int win)
+{
+	void __iomem *addr = mbus->mbuswins_base +
+		mbus->soc->win_cfg_offset(win);
+	u32 ctrl = readl(addr + WIN_CTRL_OFF);
+	return !(ctrl & WIN_CTRL_ENABLE);
+}
+
+/*
+ * Checks whether the given (base, base+size) area doesn't overlap an
+ * existing region
+ */
+static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
+				       phys_addr_t base, size_t size,
+				       u8 target, u8 attr)
+{
+	u64 end = (u64)base + size;
+	int win;
+
+	for (win = 0; win < mbus->soc->num_wins; win++) {
+		u64 wbase, wend;
+		u32 wsize;
+		u8 wtarget, wattr;
+		int enabled;
+
+		mvebu_mbus_read_window(mbus, win,
+				       &enabled, &wbase, &wsize,
+				       &wtarget, &wattr, NULL);
+
+		if (!enabled)
+			continue;
+
+		wend = wbase + wsize;
+
+		/*
+		 * Check if the current window overlaps with the
+		 * proposed physical range
+		 */
+		if ((u64)base < wend && end > wbase)
+			return 0;
+
+		/*
+		 * Check if target/attribute conflicts
+		 */
+		if (target == wtarget && attr == wattr)
+			return 0;
+	}
+
+	return 1;
+}
+
+static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
+				  phys_addr_t base, size_t size)
+{
+	int win;
+
+	for (win = 0; win < mbus->soc->num_wins; win++) {
+		u64 wbase;
+		u32 wsize;
+		int enabled;
+
+		mvebu_mbus_read_window(mbus, win,
+				       &enabled, &wbase, &wsize,
+				       NULL, NULL, NULL);
+
+		if (!enabled)
+			continue;
+
+		if (base == wbase && size == wsize)
+			return win;
+	}
+
+	return -ENODEV;
+}
+
+static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
+				   int win, phys_addr_t base, size_t size,
+				   phys_addr_t remap, u8 target,
+				   u8 attr)
+{
+	void __iomem *addr = mbus->mbuswins_base +
+		mbus->soc->win_cfg_offset(win);
+	u32 ctrl, remap_addr;
+
+	ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
+		(attr << WIN_CTRL_ATTR_SHIFT)    |
+		(target << WIN_CTRL_TGT_SHIFT)   |
+		WIN_CTRL_ENABLE;
+
+	writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
+	writel(ctrl, addr + WIN_CTRL_OFF);
+	if (win < mbus->soc->num_remappable_wins) {
+		if (remap == MVEBU_MBUS_NO_REMAP)
+			remap_addr = base;
+		else
+			remap_addr = remap;
+		writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
+		writel(0, addr + WIN_REMAP_HI_OFF);
+	}
+
+	return 0;
+}
+
+static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
+				   phys_addr_t base, size_t size,
+				   phys_addr_t remap, u8 target,
+				   u8 attr)
+{
+	int win;
+
+	if (remap == MVEBU_MBUS_NO_REMAP) {
+		for (win = mbus->soc->num_remappable_wins;
+		     win < mbus->soc->num_wins; win++)
+			if (mvebu_mbus_window_is_free(mbus, win))
+				return mvebu_mbus_setup_window(mbus, win, base,
+							       size, remap,
+							       target, attr);
+	}
+
+
+	for (win = 0; win < mbus->soc->num_wins; win++)
+		if (mvebu_mbus_window_is_free(mbus, win))
+			return mvebu_mbus_setup_window(mbus, win, base, size,
+						       remap, target, attr);
+
+	return -ENOMEM;
+}
+
+/*
+ * SoC-specific functions and definitions
+ */
+
+static unsigned int armada_370_xp_mbus_win_offset(int win)
+{
+	/* The register layout is a bit annoying and the below code
+	 * tries to cope with it.
+	 * - At offset 0x0, there are the registers for the first 8
+	 *   windows, with 4 registers of 32 bits per window (ctrl,
+	 *   base, remap low, remap high)
+	 * - Then at offset 0x80, there is a hole of 0x10 bytes for
+	 *   the internal registers base address and internal units
+	 *   sync barrier register.
+	 * - Then at offset 0x90, there the registers for 12
+	 *   windows, with only 2 registers of 32 bits per window
+	 *   (ctrl, base).
+	 */
+	if (win < 8)
+		return win << 4;
+	else
+		return 0x90 + ((win - 8) << 3);
+}
+
+static unsigned int orion5x_mbus_win_offset(int win)
+{
+	return win << 4;
+}
+
+static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
+{
+	int i;
+	int cs;
+
+	mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+
+	for (i = 0, cs = 0; i < 4; i++) {
+		u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
+		u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
+
+		/*
+		 * We only take care of entries for which the chip
+		 * select is enabled, and that don't have high base
+		 * address bits set (devices can only access the first
+		 * 32 bits of the memory).
+		 */
+		if ((size & DDR_SIZE_ENABLED) &&
+		    !(base & DDR_BASE_CS_HIGH_MASK)) {
+			struct mbus_dram_window *w;
+
+			w = &mbus_dram_info.cs[cs++];
+			w->cs_index = i;
+			w->mbus_attr = 0xf & ~(1 << i);
+#if defined(CONFIG_ARMADA_XP)
+			w->mbus_attr |= ATTR_HW_COHERENCY;
+#endif
+			w->base = base & DDR_BASE_CS_LOW_MASK;
+			w->size = (size | ~DDR_SIZE_MASK) + 1;
+		}
+	}
+	mbus_dram_info.num_cs = cs;
+}
+
+static const struct mvebu_mbus_soc_data
+armada_370_xp_mbus_data __maybe_unused = {
+	.num_wins            = 20,
+	.num_remappable_wins = 8,
+	.win_cfg_offset      = armada_370_xp_mbus_win_offset,
+	.setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
+};
+
+static const struct mvebu_mbus_soc_data
+kirkwood_mbus_data __maybe_unused = {
+	.num_wins            = 8,
+	.num_remappable_wins = 4,
+	.win_cfg_offset      = orion5x_mbus_win_offset,
+	.setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
+};
+
+/*
+ * Public API of the driver
+ */
+const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
+{
+	return &mbus_dram_info;
+}
+
+int mvebu_mbus_add_window_remap_by_id(unsigned int target,
+				      unsigned int attribute,
+				      phys_addr_t base, size_t size,
+				      phys_addr_t remap)
+{
+	struct mvebu_mbus_state *s = &mbus_state;
+
+	if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
+		printf("Cannot add window '%x:%x', conflicts with another window\n",
+		       target, attribute);
+		return -EINVAL;
+	}
+
+	return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
+}
+
+int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
+				phys_addr_t base, size_t size)
+{
+	return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
+						 size, MVEBU_MBUS_NO_REMAP);
+}
+
+int mvebu_mbus_del_window(phys_addr_t base, size_t size)
+{
+	int win;
+
+	win = mvebu_mbus_find_window(&mbus_state, base, size);
+	if (win < 0)
+		return win;
+
+	mvebu_mbus_disable_window(&mbus_state, win);
+	return 0;
+}
+
+int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
+		      u32 base, u32 size, u8 target, u8 attr)
+{
+	if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
+		printf("Cannot add window '%04x:%04x', conflicts with another window\n",
+		       target, attr);
+		return -EBUSY;
+	}
+
+	/*
+	 * In U-Boot we first try to add the mbus window to the remap windows.
+	 * If this fails, lets try to add the windows to the non-remap windows.
+	 */
+	if (mvebu_mbus_alloc_window(mbus, base, size, base, target, attr)) {
+		if (mvebu_mbus_alloc_window(mbus, base, size,
+					    MVEBU_MBUS_NO_REMAP, target, attr))
+			return -ENOMEM;
+	}
+
+	return 0;
+}
+
+int mvebu_mbus_probe(struct mbus_win windows[], int count)
+{
+	int win;
+	int ret;
+	int i;
+
+#if defined(CONFIG_KIRKWOOD)
+	mbus_state.soc = &kirkwood_mbus_data;
+#endif
+#if defined(CONFIG_ARMADA_XP)
+	mbus_state.soc = &armada_370_xp_mbus_data;
+#endif
+
+	mbus_state.mbuswins_base = (void __iomem *)MVEBU_CPU_WIN_BASE;
+	mbus_state.sdramwins_base = (void __iomem *)MVEBU_SDRAM_BASE;
+
+	for (win = 0; win < mbus_state.soc->num_wins; win++)
+		mvebu_mbus_disable_window(&mbus_state, win);
+
+	mbus_state.soc->setup_cpu_target(&mbus_state);
+
+	/* Setup statically declared windows in the DT */
+	for (i = 0; i < count; i++) {
+		u32 base, size;
+		u8 target, attr;
+
+		target = windows[i].target;
+		attr = windows[i].attr;
+		base = windows[i].base;
+		size = windows[i].size;
+		ret = mbus_dt_setup_win(&mbus_state, base, size, target, attr);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/timer.c b/arch/arm/mvebu-common/timer.c
index a08f4a1456c..40c4bc2da1b 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/timer.c
+++ b/arch/arm/mvebu-common/timer.c
@@ -7,75 +7,68 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 
-#define UBOOT_CNTR	0	/* counter to use for uboot timer */
-
-/* Timer reload and current value registers */
-struct kwtmr_val {
-	u32 reload;	/* Timer reload reg */
-	u32 val;	/* Timer value reg */
-};
-
-/* Timer registers */
-struct kwtmr_registers {
-	u32 ctrl;	/* Timer control reg */
-	u32 pad[3];
-	struct kwtmr_val tmr[2];
-	u32 wdt_reload;
-	u32 wdt_val;
-};
-
-struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;
+#define UBOOT_CNTR	0	/* counter to use for U-Boot timer */
 
 /*
  * ARM Timers Registers Map
  */
-#define CNTMR_CTRL_REG			&kwtmr_regs->ctrl
-#define CNTMR_RELOAD_REG(tmrnum)	&kwtmr_regs->tmr[tmrnum].reload
-#define CNTMR_VAL_REG(tmrnum)		&kwtmr_regs->tmr[tmrnum].val
+#define CNTMR_CTRL_REG			&tmr_regs->ctrl
+#define CNTMR_RELOAD_REG(tmrnum)	&tmr_regs->tmr[tmrnum].reload
+#define CNTMR_VAL_REG(tmrnum)		&tmr_regs->tmr[tmrnum].val
 
 /*
  * ARM Timers Control Register
  * CPU_TIMERS_CTRL_REG (CTCR)
  */
 #define CTCR_ARM_TIMER_EN_OFFS(cntr)	(cntr * 2)
-#define CTCR_ARM_TIMER_EN_MASK(cntr)	(1 << CTCR_ARM_TIMER_EN_OFFS)
 #define CTCR_ARM_TIMER_EN(cntr)		(1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-#define CTCR_ARM_TIMER_DIS(cntr)	(0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
 
 #define CTCR_ARM_TIMER_AUTO_OFFS(cntr)	((cntr * 2) + 1)
-#define CTCR_ARM_TIMER_AUTO_MASK(cntr)	(1 << 1)
 #define CTCR_ARM_TIMER_AUTO_EN(cntr)	(1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-#define CTCR_ARM_TIMER_AUTO_DIS(cntr)	(0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
 
-/*
- * ARM Timer\Watchdog Reload Register
- * CNTMR_RELOAD_REG (TRR)
- */
-#define TRG_ARM_TIMER_REL_OFFS		0
-#define TRG_ARM_TIMER_REL_MASK		0xffffffff
+/* Only Armada XP have the 25MHz enable bit (Kirkwood doesn't) */
+#if defined(CONFIG_ARMADA_XP)
+#define CTCR_ARM_TIMER_25MHZ_OFFS(cntr)	(cntr + 11)
+#define CTCR_ARM_TIMER_25MHZ(cntr)	(1 << CTCR_ARM_TIMER_25MHZ_OFFS(cntr))
+#else
+#define CTCR_ARM_TIMER_25MHZ(cntr)	0
+#endif
 
-/*
- * ARM Timer\Watchdog Register
- * CNTMR_VAL_REG (TVRG)
- */
-#define TVR_ARM_TIMER_OFFS		0
-#define TVR_ARM_TIMER_MASK		0xffffffff
-#define TVR_ARM_TIMER_MAX		0xffffffff
 #define TIMER_LOAD_VAL 			0xffffffff
 
-#define READ_TIMER			(readl(CNTMR_VAL_REG(UBOOT_CNTR)) /	\
-					 (CONFIG_SYS_TCLK / 1000))
+#define timestamp			gd->arch.tbl
+#define lastdec				gd->arch.lastinc
+
+/* Timer reload and current value registers */
+struct kwtmr_val {
+	u32 reload;	/* Timer reload reg */
+	u32 val;	/* Timer value reg */
+};
+
+/* Timer registers */
+struct kwtmr_registers {
+	u32 ctrl;	/* Timer control reg */
+	u32 pad[3];
+	struct kwtmr_val tmr[4];
+	u32 wdt_reload;
+	u32 wdt_val;
+};
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
+static struct kwtmr_registers *tmr_regs =
+	(struct kwtmr_registers *)MVEBU_TIMER_BASE;
+
+static inline ulong read_timer(void)
+{
+	return readl(CNTMR_VAL_REG(UBOOT_CNTR))	/ (CONFIG_SYS_TCLK / 1000);
+}
 
 ulong get_timer_masked(void)
 {
-	ulong now = READ_TIMER;
+	ulong now = read_timer();
 
 	if (lastdec >= now) {
 		/* normal mode */
@@ -119,20 +112,17 @@ void __udelay(unsigned long usec)
  */
 int timer_init(void)
 {
-	unsigned int cntmrctrl;
-
 	/* load value into timer */
 	writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
 	writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
 
 	/* enable timer in auto reload mode */
-	cntmrctrl = readl(CNTMR_CTRL_REG);
-	cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
-	cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
-	writel(cntmrctrl, CNTMR_CTRL_REG);
+	clrsetbits_le32(CNTMR_CTRL_REG, CTCR_ARM_TIMER_25MHZ(UBOOT_CNTR),
+			CTCR_ARM_TIMER_EN(UBOOT_CNTR) |
+			CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR));
 
 	/* init the timestamp and lastdec value */
-	lastdec = READ_TIMER;
+	lastdec = read_timer();
 	timestamp = 0;
 
 	return 0;
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 33bfd9f2f4f..6f419f050dd 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -9,6 +9,7 @@ choice
 
 config TARGET_MICROBLAZE_GENERIC
 	bool "Support microblaze-generic"
+	select SUPPORT_SPL
 
 endchoice
 
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 7686b779bf7..4991da22265 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -4,26 +4,51 @@ menu "MIPS architecture"
 config SYS_ARCH
 	default "mips"
 
+config SYS_CPU
+	default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2
+	default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2
+
+config USE_PRIVATE_LIBGCC
+	default y
+
 choice
 	prompt "Target select"
 
 config TARGET_QEMU_MIPS
 	bool "Support qemu-mips"
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_LITTLE_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select SUPPORTS_CPU_MIPS32_R2
+	select SUPPORTS_CPU_MIPS64_R1
+	select SUPPORTS_CPU_MIPS64_R2
 
 config TARGET_MALTA
 	bool "Support malta"
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_LITTLE_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select SUPPORTS_CPU_MIPS32_R2
 
 config TARGET_VCT
 	bool "Support vct"
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select SUPPORTS_CPU_MIPS32_R2
 
 config TARGET_DBAU1X00
 	bool "Support dbau1x00"
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_LITTLE_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select SUPPORTS_CPU_MIPS32_R2
 
 config TARGET_PB1X00
 	bool "Support pb1x00"
+	select SUPPORTS_LITTLE_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select SUPPORTS_CPU_MIPS32_R2
 
-config TARGET_QEMU_MIPS64
-	bool "Support qemu-mips64"
 
 endchoice
 
@@ -33,4 +58,88 @@ source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
 
+if MIPS
+
+choice
+	prompt "Endianness selection"
+	help
+	  Some MIPS boards can be configured for either little or big endian
+	  byte order. These modes require different U-Boot images. In general there
+	  is one preferred byteorder for a particular system but some systems are
+	  just as commonly used in the one or the other endianness.
+
+config SYS_BIG_ENDIAN
+	bool "Big endian"
+	depends on SUPPORTS_BIG_ENDIAN
+
+config SYS_LITTLE_ENDIAN
+	bool "Little endian"
+	depends on SUPPORTS_LITTLE_ENDIAN
+
+endchoice
+
+choice
+	prompt "CPU selection"
+	default CPU_MIPS32_R2
+
+config CPU_MIPS32_R1
+	bool "MIPS32 Release 1"
+	depends on SUPPORTS_CPU_MIPS32_R1
+	select 32BIT
+	help
+	  Choose this option to build an U-Boot for release 1 or later of the
+	  MIPS32 architecture.
+
+config CPU_MIPS32_R2
+	bool "MIPS32 Release 2"
+	depends on SUPPORTS_CPU_MIPS32_R2
+	select 32BIT
+	help
+	  Choose this option to build an U-Boot for release 2 or later of the
+	  MIPS32 architecture.
+
+config CPU_MIPS64_R1
+	bool "MIPS64 Release 1"
+	depends on SUPPORTS_CPU_MIPS64_R1
+	select 64BIT
+	help
+	  Choose this option to build a kernel for release 1 or later of the
+	  MIPS64 architecture.
+
+config CPU_MIPS64_R2
+	bool "MIPS64 Release 2"
+	depends on SUPPORTS_CPU_MIPS64_R2
+	select 64BIT
+	help
+	  Choose this option to build a kernel for release 2 or later of the
+	  MIPS64 architecture.
+
+endchoice
+
+config SUPPORTS_BIG_ENDIAN
+	bool
+
+config SUPPORTS_LITTLE_ENDIAN
+	bool
+
+config SUPPORTS_CPU_MIPS32_R1
+	bool
+
+config SUPPORTS_CPU_MIPS32_R2
+	bool
+
+config SUPPORTS_CPU_MIPS64_R1
+	bool
+
+config SUPPORTS_CPU_MIPS64_R2
+	bool
+
+config 32BIT
+	bool
+
+config 64BIT
+	bool
+
+endif
+
 endmenu
diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index a2d07aff1b1..4dc88f4d51f 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -5,25 +5,41 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := mips_4KC-
+ifdef CONFIG_SYS_BIG_ENDIAN
+32bit-emul		:= elf32btsmip
+64bit-emul		:= elf64btsmip
+32bit-bfd		:= elf32-tradbigmips
+64bit-bfd		:= elf64-tradbigmips
+PLATFORM_CPPFLAGS	+= -EB
+PLATFORM_LDFLAGS	+= -EB
 endif
 
-# Handle special prefix in ELDK 4.0 toolchain
-ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
-ENDIANNESS := -EL
+ifdef CONFIG_SYS_LITTLE_ENDIAN
+32bit-emul		:= elf32ltsmip
+64bit-emul		:= elf64ltsmip
+32bit-bfd		:= elf32-tradlittlemips
+64bit-bfd		:= elf64-tradlittlemips
+PLATFORM_CPPFLAGS	+= -EL
+PLATFORM_LDFLAGS	+= -EL
 endif
 
-ifdef CONFIG_SYS_LITTLE_ENDIAN
-ENDIANNESS := -EL
+ifdef CONFIG_32BIT
+PLATFORM_CPPFLAGS	+= -mabi=32
+PLATFORM_LDFLAGS	+= -m $(32bit-emul)
+OBJCOPYFLAGS		+= -O $(32bit-bfd)
 endif
 
-ifdef CONFIG_SYS_BIG_ENDIAN
-ENDIANNESS := -EB
+ifdef CONFIG_64BIT
+PLATFORM_CPPFLAGS	+= -mabi=64
+PLATFORM_LDFLAGS	+= -m$(64bit-emul)
+OBJCOPYFLAGS		+= -O $(64bit-bfd)
 endif
 
-# Default to EB if no endianess is configured
-ENDIANNESS ?= -EB
+cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32
+cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2
+cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
+cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
+PLATFORM_CPPFLAGS += $(cpuflags-y)
 
 PLATFORM_CPPFLAGS += -D__MIPS__
 
@@ -49,10 +65,10 @@ __HAVE_ARCH_GENERIC_BOARD := y
 # On the other hand, we want PIC in the U-Boot code to relocate it from ROM
 # to RAM. $28 is always used as gp.
 #
-PLATFORM_CPPFLAGS		+= -G 0 -mabicalls -fpic $(ENDIANNESS)
+PLATFORM_CPPFLAGS		+= -G 0 -mabicalls -fpic
 PLATFORM_CPPFLAGS		+= -msoft-float
-PLATFORM_LDFLAGS		+= -G 0 -static -n -nostdlib $(ENDIANNESS)
+PLATFORM_LDFLAGS		+= -G 0 -static -n -nostdlib
 PLATFORM_RELFLAGS		+= -ffunction-sections -fdata-sections
 LDFLAGS_FINAL			+= --gc-sections -pie
 OBJCOPYFLAGS			+= -j .text -j .rodata -j .data -j .got
-OBJCOPYFLAGS			+= -j .u_boot_list -j .rel.dyn
+OBJCOPYFLAGS			+= -j .u_boot_list -j .rel.dyn -j .padding
diff --git a/arch/mips/cpu/mips32/config.mk b/arch/mips/cpu/mips32/config.mk
index 332cd62c749..4257c56d59e 100644
--- a/arch/mips/cpu/mips32/config.mk
+++ b/arch/mips/cpu/mips32/config.mk
@@ -5,19 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-#
-# Default optimization level for MIPS32
-#
-# Note: Toolchains with binutils prior to v2.16
-# are no longer supported by U-Boot MIPS tree!
-#
-PLATFORM_CPPFLAGS += -DCONFIG_MIPS32 -march=mips32r2
-PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
-ifdef CONFIG_SYS_BIG_ENDIAN
-PLATFORM_LDFLAGS  += -m elf32btsmip
-else
-PLATFORM_LDFLAGS  += -m elf32ltsmip
-endif
-
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
 			       -T $(srctree)/examples/standalone/mips.lds
diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk
index c55eb7f2ee9..96eb82948d4 100644
--- a/arch/mips/cpu/mips64/config.mk
+++ b/arch/mips/cpu/mips64/config.mk
@@ -5,19 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-#
-# Default optimization level for MIPS64
-#
-# Note: Toolchains with binutils prior to v2.16
-# are no longer supported by U-Boot MIPS tree!
-#
-PLATFORM_CPPFLAGS += -DCONFIG_MIPS64 -march=mips64
-PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
-ifdef CONFIG_SYS_BIG_ENDIAN
-PLATFORM_LDFLAGS  += -m elf64btsmip
-else
-PLATFORM_LDFLAGS  += -m elf64ltsmip
-endif
-
 CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 \
 			       -T $(srctree)/examples/standalone/mips64.lds
diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds
index e504ea75440..7d71c11ae4c 100644
--- a/arch/mips/cpu/u-boot.lds
+++ b/arch/mips/cpu/u-boot.lds
@@ -61,6 +61,24 @@ SECTIONS
 		__rel_dyn_end = .;
 	}
 
+	.padding : {
+		/*
+		 * Workaround for a binutils feature (or bug?).
+		 *
+		 * The GNU ld from binutils puts the dynamic relocation
+		 * entries into the .rel.dyn section. Sometimes it
+		 * allocates more dynamic relocation entries than it needs
+		 * and the unused slots are set to R_MIPS_NONE entries.
+		 *
+		 * However the size of the .rel.dyn section in the ELF
+		 * section header does not cover the unused entries, so
+		 * objcopy removes those during stripping.
+		 *
+		 * Create a small section here to avoid that.
+		 */
+		LONG(0xFFFFFFFF)
+	}
+
 	_end = .;
 
 	.bss __rel_dyn_start (OVERLAY) : {
diff --git a/arch/powerpc/cpu/74xx_7xx/Kconfig b/arch/powerpc/cpu/74xx_7xx/Kconfig
index 3378c91645a..b2f1a598e3b 100644
--- a/arch/powerpc/cpu/74xx_7xx/Kconfig
+++ b/arch/powerpc/cpu/74xx_7xx/Kconfig
@@ -19,30 +19,14 @@ config TARGET_PPMC7XX
 config TARGET_ELPPC
 	bool "Support ELPPC"
 
-config TARGET_CPCI750
-	bool "Support CPCI750"
-
 config TARGET_MPC7448HPC2
 	bool "Support mpc7448hpc2"
 
-config TARGET_DB64360
-	bool "Support DB64360"
-
-config TARGET_DB64460
-	bool "Support DB64460"
-
-config TARGET_P3MX
-	bool "Support p3mx"
-
 endchoice
 
-source "board/Marvell/db64360/Kconfig"
-source "board/Marvell/db64460/Kconfig"
 source "board/eltec/elppc/Kconfig"
-source "board/esd/cpci750/Kconfig"
 source "board/evb64260/Kconfig"
 source "board/freescale/mpc7448hpc2/Kconfig"
 source "board/ppmc7xx/Kconfig"
-source "board/prodrive/p3mx/Kconfig"
 
 endmenu
diff --git a/arch/powerpc/cpu/74xx_7xx/start.S b/arch/powerpc/cpu/74xx_7xx/start.S
index b0e102c668b..83937812bd2 100644
--- a/arch/powerpc/cpu/74xx_7xx/start.S
+++ b/arch/powerpc/cpu/74xx_7xx/start.S
@@ -28,13 +28,6 @@
 #include <asm/mmu.h>
 #include <asm/u-boot.h>
 
-#if !defined(CONFIG_DB64360) && \
-    !defined(CONFIG_DB64460) && \
-    !defined(CONFIG_CPCI750) && \
-    !defined(CONFIG_P3Mx)
-#include <galileo/gt64260R.h>
-#endif
-
 /* We don't want the  MMU yet.
 */
 #undef	MSR_KERNEL
@@ -712,11 +705,7 @@ in_ram:
 	bne	5b
 6:
 	mr	r3, r10		/* Destination Address		*/
-#if defined(CONFIG_DB64360)	|| \
-    defined(CONFIG_DB64460)     || \
-    defined(CONFIG_CPCI750)	|| \
-    defined(CONFIG_PPMC7XX)     || \
-    defined(CONFIG_P3Mx)
+#if defined(CONFIG_PPMC7XX)
 	mr	r4, r9		/* Use RAM copy of the global data */
 #endif
 	bl	after_reloc
diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig
index 8a477e7e0c3..c1fb92af4bd 100644
--- a/arch/powerpc/cpu/mpc5xxx/Kconfig
+++ b/arch/powerpc/cpu/mpc5xxx/Kconfig
@@ -9,6 +9,7 @@ choice
 
 config TARGET_A3M071
 	bool "Support a3m071"
+	select SUPPORT_SPL
 
 config TARGET_A4M072
 	bool "Support a4m072"
@@ -55,9 +56,6 @@ config TARGET_TOTAL5200
 config TARGET_V38B
 	bool "Support v38b"
 
-config TARGET_TOP5200
-	bool "Support TOP5200"
-
 config TARGET_CPCI5200
 	bool "Support cpci5200"
 
@@ -119,7 +117,6 @@ source "board/a4m072/Kconfig"
 source "board/bc3450/Kconfig"
 source "board/canmb/Kconfig"
 source "board/cm5200/Kconfig"
-source "board/emk/top5200/Kconfig"
 source "board/esd/cpci5200/Kconfig"
 source "board/esd/mecp5200/Kconfig"
 source "board/esd/pf5200/Kconfig"
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig
index 41e4e5f1ecc..2541400e727 100644
--- a/arch/powerpc/cpu/mpc8260/Kconfig
+++ b/arch/powerpc/cpu/mpc8260/Kconfig
@@ -28,9 +28,6 @@ config TARGET_EP82XXM
 config TARGET_GW8260
 	bool "Support gw8260"
 
-config TARGET_HYMOD
-	bool "Support hymod"
-
 config TARGET_IPHASE4539
 	bool "Support IPHASE4539"
 
@@ -55,18 +52,9 @@ config TARGET_MPC8266ADS
 config TARGET_VOVPN_GW
 	bool "Support VoVPN-GW"
 
-config TARGET_IDS8247
-	bool "Support IDS8247"
-
 config TARGET_KM82XX
 	bool "Support km82xx"
 
-config TARGET_TQM8260
-	bool "Support TQM8260"
-
-config TARGET_TQM8272
-	bool "Support TQM8272"
-
 endchoice
 
 source "board/atc/Kconfig"
@@ -78,8 +66,6 @@ source "board/ep82xxm/Kconfig"
 source "board/freescale/mpc8266ads/Kconfig"
 source "board/funkwerk/vovpn-gw/Kconfig"
 source "board/gw8260/Kconfig"
-source "board/hymod/Kconfig"
-source "board/ids/ids8247/Kconfig"
 source "board/iphase4539/Kconfig"
 source "board/keymile/km82xx/Kconfig"
 source "board/muas3001/Kconfig"
@@ -87,7 +73,5 @@ source "board/pm826/Kconfig"
 source "board/pm828/Kconfig"
 source "board/ppmc8260/Kconfig"
 source "board/sacsng/Kconfig"
-source "board/tqc/tqm8260/Kconfig"
-source "board/tqc/tqm8272/Kconfig"
 
 endmenu
diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c
index d93a99109f8..f9f15b59e53 100644
--- a/arch/powerpc/cpu/mpc8260/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c
@@ -645,32 +645,7 @@ eth_loopback_test (void)
 
 	/* 28.9 - (1-2): ioports have been set up already */
 
-#if defined(CONFIG_HYMOD)
-	/*
-	 * Attention: this is board-specific
-	 * 0, FCC1
-	 * 1, FCC2
-	 * 2, FCC3
-	 */
-#       define FCC_START_LOOP 0
-#       define FCC_END_LOOP   2
-
-	/*
-	 * Attention: this is board-specific
-	 * - FCC1 Rx-CLK is CLK10
-	 * - FCC1 Tx-CLK is CLK11
-	 * - FCC2 Rx-CLK is CLK13
-	 * - FCC2 Tx-CLK is CLK14
-	 * - FCC3 Rx-CLK is CLK15
-	 * - FCC3 Tx-CLK is CLK16
-	 */
-
-	/* 28.9 - (3): connect FCC's tx and rx clocks */
-	immr->im_cpmux.cmx_uar = 0;
-	immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\
-	    CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\
-	    CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16;
-#elif defined(CONFIG_SACSng)
+#if defined(CONFIG_SACSng)
 	/*
 	 * Attention: this is board-specific
 	 * 1, FCC2
diff --git a/arch/powerpc/cpu/mpc8260/interrupts.c b/arch/powerpc/cpu/mpc8260/interrupts.c
index 30125a7a730..41d2c04c856 100644
--- a/arch/powerpc/cpu/mpc8260/interrupts.c
+++ b/arch/powerpc/cpu/mpc8260/interrupts.c
@@ -142,15 +142,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
 	immr->im_intctl.ic_sipnrh = 0xffffffff;
 	immr->im_intctl.ic_sipnrl = 0xffffffff;
 
-#ifdef CONFIG_HYMOD
-	/*
-	 * ensure all external interrupt sources default to trigger on
-	 * high-to-low transition (i.e. edge triggered active low)
-	 */
-	immr->im_intctl.ic_siexr = -1;
-#endif
-
-	return (0);
+	return 0;
 }
 
 /****************************************************************************/
diff --git a/arch/powerpc/cpu/mpc8260/pci.c b/arch/powerpc/cpu/mpc8260/pci.c
index 0a47fdc1d36..f7bb05d204d 100644
--- a/arch/powerpc/cpu/mpc8260/pci.c
+++ b/arch/powerpc/cpu/mpc8260/pci.c
@@ -262,8 +262,6 @@ void pci_mpc8250_init (struct pci_controller *hose)
 				  | SIUMCR_CS10PC00
 				  | SIUMCR_BCTLC00
 				  | SIUMCR_MMR11;
-#elif defined(CONFIG_TQM8272)
-/* nothing to do for this Board here */
 #else
 	/*
 	 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S
index d7eaf13e0bd..5f1e174ec82 100644
--- a/arch/powerpc/cpu/mpc8260/start.S
+++ b/arch/powerpc/cpu/mpc8260/start.S
@@ -48,9 +48,6 @@
 	GOT_ENTRY(__init_end)
 	GOT_ENTRY(__bss_end)
 	GOT_ENTRY(__bss_start)
-#if defined(CONFIG_HYMOD)
-	GOT_ENTRY(environment)
-#endif
 	END_GOT
 
 /*
@@ -878,18 +875,7 @@ clear_bss:
 	 * Now clear BSS segment
 	 */
 	lwz	r3,GOT(__bss_start)
-#if defined(CONFIG_HYMOD)
-	/*
-	 * For HYMOD - the environment is the very last item in flash.
-	 * The real .bss stops just before environment starts, so only
-	 * clear up to that point.
-	 *
-	 * taken from mods for FADS board
-	 */
-	lwz	r4,GOT(environment)
-#else
 	lwz	r4,GOT(__bss_end)
-#endif
 
 	cmplw	0, r3, r4
 	beq	6f
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 42e0e296688..2a1abe03a9e 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -24,6 +24,7 @@ config TARGET_MPC8308RDB
 
 config TARGET_MPC8313ERDB
 	bool "Support MPC8313ERDB"
+	select SUPPORT_SPL
 
 config TARGET_MPC8315ERDB
 	bool "Support MPC8315ERDB"
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 36724e5aa53..af75c63eb3f 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -958,18 +958,7 @@ clear_bss:
 	 * Now clear BSS segment
 	 */
 	lwz	r3,GOT(__bss_start)
-#if defined(CONFIG_HYMOD)
-	/*
-	 * For HYMOD - the environment is the very last item in flash.
-	 * The real .bss stops just before environment starts, so only
-	 * clear up to that point.
-	 *
-	 * taken from mods for FADS board
-	 */
-	lwz	r4,GOT(environment)
-#else
 	lwz	r4,GOT(__bss_end)
-#endif
 
 	cmplw	0, r3, r4
 	beq	6f
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 8c1c01c3424..7b42d06952c 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -13,20 +13,22 @@ config TARGET_SBC8548
 config TARGET_SOCRATES
 	bool "Support socrates"
 
-config TARGET_HWW1U1A
-	bool "Support HWW1U1A"
-
 config TARGET_B4860QDS
 	bool "Support B4860QDS"
+	select SUPPORT_SPL
 
 config TARGET_BSC9131RDB
 	bool "Support BSC9131RDB"
+	select SUPPORT_SPL
 
 config TARGET_BSC9132QDS
 	bool "Support BSC9132QDS"
+	select SUPPORT_SPL
 
 config TARGET_C29XPCIE
 	bool "Support C29XPCIE"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
 
 config TARGET_P3041DS
 	bool "Support P3041DS"
@@ -72,18 +74,26 @@ config TARGET_MPC8572DS
 
 config TARGET_P1010RDB
 	bool "Support P1010RDB"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
 
 config TARGET_P1022DS
 	bool "Support P1022DS"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
 
 config TARGET_P1023RDB
 	bool "Support P1023RDB"
 
 config TARGET_P1_P2_RDB
 	bool "Support P1_P2_RDB"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
 
 config TARGET_P1_P2_RDB_PC
 	bool "Support p1_p2_rdb_pc"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
 
 config TARGET_P1_TWR
 	bool "Support p1_twr"
@@ -105,18 +115,22 @@ config TARGET_T1040QDS
 
 config TARGET_T104XRDB
 	bool "Support T104xRDB"
+	select SUPPORT_SPL
 
 config TARGET_T208XQDS
 	bool "Support T208xQDS"
+	select SUPPORT_SPL
 
 config TARGET_T208XRDB
 	bool "Support T208xRDB"
+	select SUPPORT_SPL
 
 config TARGET_T4240EMU
 	bool "Support T4240EMU"
 
 config TARGET_T4240QDS
 	bool "Support T4240QDS"
+	select SUPPORT_SPL
 
 config TARGET_T4240RDB
 	bool "Support T4240RDB"
@@ -144,7 +158,6 @@ config TARGET_XPEDITE550X
 
 endchoice
 
-source "board/exmeritus/hww1u1a/Kconfig"
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 5bfab70b7ed..85d32fc6128 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -27,6 +27,9 @@
 #include <hwconfig.h>
 #include <linux/compiler.h>
 #include "mp.h"
+#ifdef CONFIG_FSL_CAAM
+#include <fsl_sec.h>
+#endif
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #include <nand.h>
 #include <errno.h>
@@ -423,7 +426,8 @@ ulong cpu_init_f(void)
 {
 	ulong flag = 0;
 	extern void m8560_cpm_reset (void);
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
+	(defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 #if defined(CONFIG_SECURE_BOOT)
@@ -455,6 +459,12 @@ ulong cpu_init_f(void)
 #if defined(CONFIG_SYS_CPC_REINIT_F)
 	disable_cpc_sram();
 #endif
+
+#if defined(CONFIG_FSL_CORENET)
+	/* Put PAMU in bypass mode */
+	out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS);
+#endif
+
 #endif
 
 #ifdef CONFIG_CPM2
@@ -803,7 +813,7 @@ int cpu_init_r(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 #define MCFGR_AXIPIPE 0x000000f0
 	if (IS_SVR_REV(svr, 1, 0))
-		clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
+		sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
 #endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
@@ -938,6 +948,10 @@ int cpu_init_r(void)
 	fman_enet_init();
 #endif
 
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
 	/*
 	 * For P1022/1013 Rev1.0 silicon, after power on SATA host
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 3222e26a5aa..d4c3d9df9b8 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -714,7 +714,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 		ccsr_sec_t __iomem *sec;
 
 		sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
-		fdt_fixup_crypto_node(blob, in_be32(&sec->secvid_ms));
+		fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
 	}
 #endif
 
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 19e130e87f1..7a2d4be42ce 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -66,12 +66,12 @@ static void setup_sec_liodn_base(void)
 		return;
 
 	/* QILCR[QSLOM] */
-	out_be32(&sec->qilcr_ms, 0x3ff<<16);
+	sec_out32(&sec->qilcr_ms, 0x3ff<<16);
 
 	base = (liodn_bases[FSL_HW_PORTAL_SEC].id[0] << 16) |
 		liodn_bases[FSL_HW_PORTAL_SEC].id[1];
 
-	out_be32(&sec->qilcr_ls, base);
+	sec_out32(&sec->qilcr_ls, base);
 }
 
 #ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index f1dca90eba9..e447748e120 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -16,9 +16,6 @@ config TARGET_ESTEEM192E
 config TARGET_HERMES
 	bool "Support hermes"
 
-config TARGET_ICU862
-	bool "Support ICU862"
-
 config TARGET_IP860
 	bool "Support IP860"
 
@@ -43,12 +40,6 @@ config TARGET_RRVISION
 config TARGET_SPD823TS
 	bool "Support SPD823TS"
 
-config TARGET_MHPC
-	bool "Support MHPC"
-
-config TARGET_TOP860
-	bool "Support TOP860"
-
 config TARGET_KUP4K
 	bool "Support KUP4K"
 
@@ -120,11 +111,8 @@ endchoice
 source "board/LEOX/elpt860/Kconfig"
 source "board/RRvision/Kconfig"
 source "board/cogent/Kconfig"
-source "board/eltec/mhpc/Kconfig"
-source "board/emk/top860/Kconfig"
 source "board/esteem192e/Kconfig"
 source "board/hermes/Kconfig"
-source "board/icu862/Kconfig"
 source "board/ip860/Kconfig"
 source "board/ivm/Kconfig"
 source "board/kup/kup4k/Kconfig"
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index 90c7e61d835..60c401e311e 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -126,12 +126,10 @@ void cpu_init_f (volatile immap_t * immr)
 	 */
 
 #if defined(CONFIG_HERMES)	|| \
-    defined(CONFIG_ICU862)	|| \
     defined(CONFIG_IP860)	|| \
     defined(CONFIG_IVML24)	|| \
     defined(CONFIG_IVMS8)	|| \
     defined(CONFIG_LWMON)	|| \
-    defined(CONFIG_MHPC)	|| \
     defined(CONFIG_R360MPI)	|| \
     defined(CONFIG_RMU)		|| \
     defined(CONFIG_SPD823TS)
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index d12b3df4a15..22b8ec752bc 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -205,11 +205,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
 
 	j = 0;
 	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
-#if defined(CONFIG_ICU862)
-		udelay(10);
-#else
 		udelay(1);
-#endif
 		j++;
 	}
 	if (j>=TOUT_LOOP) {
@@ -424,7 +420,7 @@ static void fec_pin_init(int fecidx)
 
 #endif /* !CONFIG_RMII */
 
-#elif !defined(CONFIG_ICU862)
+#else
 		/*
 		 * Configure all of port D for MII.
 		 */
@@ -437,42 +433,8 @@ static void fec_pin_init(int fecidx)
 			immr->im_ioport.iop_pddir = 0x1c58;	/* Pre rev. D */
 		else
 			immr->im_ioport.iop_pddir = 0x1fff;	/* Rev. D and later */
-#else
-		/*
-		 * Configure port A for MII.
-		 */
-
-#if defined(CONFIG_ICU862) && defined(CONFIG_SYS_DISCOVER_PHY)
-
-		/*
-		 * On the ICU862 board the MII-MDC pin is routed to PD8 pin
-		 * * of CPU, so for this board we need to configure Utopia and
-		 * * enable PD8 to MII-MDC function
-		 */
-		immr->im_ioport.iop_pdpar |= 0x4080;
 #endif
 
-		/*
-		 * Has Utopia been configured?
-		 */
-		if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
-			/*
-			 * YES - Use MUXED mode for UTOPIA bus.
-			 * This frees Port A for use by MII (see 862UM table 41-6).
-			 */
-			immr->im_ioport.utmode &= ~0x80;
-		} else {
-			/*
-			 * NO - set SPLIT mode for UTOPIA bus.
-			 *
-			 * This doesn't really effect UTOPIA (which isn't
-			 * enabled anyway) but just tells the 862
-			 * to use port A for MII (see 862UM table 41-6).
-			 */
-			immr->im_ioport.utmode |= 0x80;
-		}
-#endif				/* !defined(CONFIG_ICU862) */
-
 #endif	/* CONFIG_ETHER_ON_FEC1 */
 	} else if (fecidx == 1) {
 
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 4cec5e118ff..c6b4d955496 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -287,8 +287,8 @@ static u8 caam_get_era(void)
 	};
 
 	ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
-	u32 secvid_ms = in_be32(&sec->secvid_ms);
-	u32 ccbvid = in_be32(&sec->ccbvid);
+	u32 secvid_ms = sec_in32(&sec->secvid_ms);
+	u32 ccbvid = sec_in32(&sec->ccbvid);
 	u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >>
 				SEC_SECVID_MS_IPID_SHIFT;
 	u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >>
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 56abe8dc56f..8f8860163c9 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -24,6 +24,7 @@ config TARGET_KORAT
 
 config TARGET_LWMON5
 	bool "Support lwmon5"
+	select SUPPORT_SPL
 
 config TARGET_PCS440EP
 	bool "Support pcs440ep"
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index 22561231cb8..e5a0e21e369 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -451,6 +451,9 @@ cpu_init_f (void)
 #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
 
 	gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+	/* Clear initial global data */
+	memset((void *)gd, 0, sizeof(gd_t));
 }
 
 /*
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 712f2ef4b30..4c1774f503c 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -24,6 +24,7 @@
 
 /* IP endianness */
 #define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_SEC_BE
 
 /* Number of TLB CAM entries we have on FSL Book-E chips */
 #if defined(CONFIG_E500MC)
diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h
index 6086a73ba95..bed80aa9332 100644
--- a/arch/powerpc/include/asm/immap_512x.h
+++ b/arch/powerpc/include/asm/immap_512x.h
@@ -59,6 +59,7 @@ typedef struct sysconf512x {
 	u8 res2[0x28];
 	law512x_t ddrlaw;	/* DDR Local Access Window */
 	u8 res3[0x18];
+	u32 mbxbar;		/* MBX Base Address */
 	u32 srambar;		/* SRAM Base Address */
 	u32 nfcbar;		/* NFC Base Address */
 	u8 res4[0x34];
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index dfb370e051b..0264523d640 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -16,6 +16,7 @@
 #include <asm/fsl_dma.h>
 #include <asm/fsl_i2c.h>
 #include <fsl_ifc.h>
+#include <fsl_sec.h>
 #include <asm/fsl_lbc.h>
 #include <asm/fsl_fman.h>
 #include <fsl_immap.h>
@@ -1911,6 +1912,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 	u8	res24[64];
 	u32	pblsr;		/* Preboot loader status */
 	u32	pamubypenr;	/* PAMU bypass enable */
+#define FSL_CORENET_PAMU_BYPASS		0xffff0000
 	u32	dmacr1;		/* DMA control */
 	u8	res25[4];
 	u32	gensr1;		/* General status */
@@ -2675,72 +2677,6 @@ enum {
 	FSL_SRDS_B3_LANE_D = 23,
 };
 
-/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
-#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
-typedef struct ccsr_sec {
-	u32	res0;
-	u32	mcfgr;		/* Master CFG Register */
-	u8	res1[0x8];
-	struct {
-		u32	ms;	/* Job Ring LIODN Register, MS */
-		u32	ls;	/* Job Ring LIODN Register, LS */
-	} jrliodnr[4];
-	u8	res2[0x30];
-	struct {
-		u32	ms;	/* RTIC LIODN Register, MS */
-		u32	ls;	/* RTIC LIODN Register, LS */
-	} rticliodnr[4];
-	u8	res3[0x1c];
-	u32	decorr;		/* DECO Request Register */
-	struct {
-		u32	ms;	/* DECO LIODN Register, MS */
-		u32	ls;	/* DECO LIODN Register, LS */
-	} decoliodnr[8];
-	u8	res4[0x40];
-	u32	dar;		/* DECO Avail Register */
-	u32	drr;		/* DECO Reset Register */
-	u8	res5[0xe78];
-	u32	crnr_ms;	/* CHA Revision Number Register, MS */
-	u32	crnr_ls;	/* CHA Revision Number Register, LS */
-	u32	ctpr_ms;	/* Compile Time Parameters Register, MS */
-	u32	ctpr_ls;	/* Compile Time Parameters Register, LS */
-	u8	res6[0x10];
-	u32	far_ms;		/* Fault Address Register, MS */
-	u32	far_ls;		/* Fault Address Register, LS */
-	u32	falr;		/* Fault Address LIODN Register */
-	u32	fadr;		/* Fault Address Detail Register */
-	u8	res7[0x4];
-	u32	csta;		/* CAAM Status Register */
-	u8	res8[0x8];
-	u32	rvid;		/* Run Time Integrity Checking Version ID Reg.*/
-	u32	ccbvid;		/* CHA Cluster Block Version ID Register */
-	u32	chavid_ms;	/* CHA Version ID Register, MS */
-	u32	chavid_ls;	/* CHA Version ID Register, LS */
-	u32	chanum_ms;	/* CHA Number Register, MS */
-	u32	chanum_ls;	/* CHA Number Register, LS */
-	u32	secvid_ms;	/* SEC Version ID Register, MS */
-	u32	secvid_ls;	/* SEC Version ID Register, LS */
-	u8	res9[0x6020];
-	u32	qilcr_ms;	/* Queue Interface LIODN CFG Register, MS */
-	u32	qilcr_ls;	/* Queue Interface LIODN CFG Register, LS */
-	u8	res10[0x8fd8];
-} ccsr_sec_t;
-
-#define SEC_CTPR_MS_AXI_LIODN		0x08000000
-#define SEC_CTPR_MS_QI			0x02000000
-#define SEC_RVID_MA			0x0f000000
-#define SEC_CHANUM_MS_JRNUM_MASK	0xf0000000
-#define SEC_CHANUM_MS_JRNUM_SHIFT	28
-#define SEC_CHANUM_MS_DECONUM_MASK	0x0f000000
-#define SEC_CHANUM_MS_DECONUM_SHIFT	24
-#define SEC_SECVID_MS_IPID_MASK	0xffff0000
-#define SEC_SECVID_MS_IPID_SHIFT	16
-#define SEC_SECVID_MS_MAJ_REV_MASK	0x0000ff00
-#define SEC_SECVID_MS_MAJ_REV_SHIFT	8
-#define SEC_CCBVID_ERA_MASK		0xff000000
-#define SEC_CCBVID_ERA_SHIFT		24
-#endif
-
 typedef struct ccsr_qman {
 #ifdef CONFIG_SYS_FSL_QMAN_V3
 	u8	res0[0x200];
@@ -2940,6 +2876,7 @@ struct ccsr_sfp_regs {
 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET		0x220000
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x221000
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x300000
+#define CONFIG_SYS_FSL_JR0_OFFSET		0x301000
 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET	0x316000
 #define CONFIG_SYS_FSL_QMAN_OFFSET		0x318000
 #define CONFIG_SYS_FSL_BMAN_OFFSET		0x31a000
@@ -3000,8 +2937,10 @@ struct ccsr_sfp_regs {
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
 #if defined(CONFIG_PPC_C29X)
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x80000
+#define CONFIG_SYS_FSL_JR0_OFFSET               0x81000
 #else
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x30000
+#define CONFIG_SYS_FSL_JR0_OFFSET               0x31000
 #endif
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
@@ -3106,6 +3045,8 @@ struct ccsr_sfp_regs {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
 #define CONFIG_SYS_FSL_SEC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
 #define CONFIG_SYS_FSL_FM1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h
index b27a6b753a0..b29ce792f72 100644
--- a/arch/powerpc/include/asm/types.h
+++ b/arch/powerpc/include/asm/types.h
@@ -41,8 +41,12 @@ typedef unsigned long long u64;
 
 #define BITS_PER_LONG 32
 
+#ifdef CONFIG_PHYS_64BIT
+typedef unsigned long long dma_addr_t;
+#else
 /* DMA addresses are 32-bits wide */
 typedef u32 dma_addr_t;
+#endif
 
 #ifdef CONFIG_PHYS_64BIT
 typedef unsigned long long phys_addr_t;
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
index e1b566fa568..a61e998df68 100644
--- a/arch/powerpc/include/asm/u-boot.h
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -77,9 +77,6 @@ typedef struct bd_info {
 	unsigned int	bi_pci_busfreq;	/* PCI Bus speed, in Hz */
 	unsigned char	bi_pci_enetaddr[6];	/* PCI Ethernet MAC address */
 #endif
-#if defined(CONFIG_HYMOD)
-	hymod_conf_t	bi_hymod_conf;	/* hymod configuration information */
-#endif
 
 #ifdef CONFIG_HAS_ETH1
 	unsigned char   bi_enet1addr[6];	/* OLD: see README.enetaddr */
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 797478a2c7f..76147154c22 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -1,6 +1,9 @@
 /dts-v1/;
 
 / {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
 	chosen {
 		stdout-path = "/serial";
 	};
@@ -131,4 +134,27 @@
 		num-gpios = <20>;
 	};
 
+	spi@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+		compatible = "sandbox,spi";
+		cs-gpios = <0>, <&gpio_a 0>;
+		flash@0 {
+			reg = <0>;
+			compatible = "spansion,m25p16", "sandbox,spi-flash";
+			spi-max-frequency = <40000000>;
+			sandbox,filename = "spi.bin";
+		};
+	};
+
+	cros-ec@0 {
+		compatible = "google,cros-ec";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		firmware_storage_spi: flash@0 {
+			reg = <0 0x400000>;
+		};
+	};
+
 };
diff --git a/arch/sandbox/include/asm/spi.h b/arch/sandbox/include/asm/spi.h
index 49b4a0f103a..9985e3c4949 100644
--- a/arch/sandbox/include/asm/spi.h
+++ b/arch/sandbox/include/asm/spi.h
@@ -33,19 +33,6 @@ struct sandbox_spi_emu_ops {
 };
 
 /*
- * There are times when the data lines are allowed to tristate.  What
- * is actually sensed on the line depends on the hardware.  It could
- * always be 0xFF/0x00 (if there are pull ups/downs), or things could
- * float and so we'd get garbage back.  This func encapsulates that
- * scenario so we can worry about the details here.
- */
-static inline void sandbox_spi_tristate(u8 *buf, uint len)
-{
-	/* XXX: make this into a user config option ? */
-	memset(buf, 0xff, len);
-}
-
-/*
  * Extract the bus/cs from the spi spec and return the start of the spi
  * client spec.  If the bus/cs are invalid for the current config, then
  * it returns NULL.
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
index d17a82e90fc..32d55ccc4c2 100644
--- a/arch/sandbox/include/asm/state.h
+++ b/arch/sandbox/include/asm/state.h
@@ -42,7 +42,7 @@ enum state_terminal_raw {
 
 struct sandbox_spi_info {
 	const char *spec;
-	const struct sandbox_spi_emu_ops *ops;
+	struct udevice *emul;
 };
 
 /* The complete state of the test system */
diff --git a/arch/sandbox/include/asm/types.h b/arch/sandbox/include/asm/types.h
index 6d3eb1f3de2..42c09e2fff2 100644
--- a/arch/sandbox/include/asm/types.h
+++ b/arch/sandbox/include/asm/types.h
@@ -42,8 +42,13 @@ typedef unsigned short u16;
 typedef signed int s32;
 typedef unsigned int u32;
 
+#if !defined(CONFIG_USE_STDINT) || !defined(__INT64_TYPE__)
 typedef signed long long s64;
 typedef unsigned long long u64;
+#else
+typedef __INT64_TYPE__ s64;
+typedef __UINT64_TYPE__ u64;
+#endif
 
 #define BITS_PER_LONG	CONFIG_SANDBOX_BITS_PER_LONG
 
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 733334f9318..2df09b2e50e 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -1,29 +1,56 @@
 menu "SPARC architecture"
 	depends on SPARC
 
-config SYS_ARCH
-	default "sparc"
+config LEON
+	bool
+
+config LEON2
+	bool
+	select LEON
+
+config LEON3
+	bool
+	select LEON
 
 choice
-	prompt "Target select"
+	prompt "Board select"
 
 config TARGET_GRSIM_LEON2
-	bool "Support grsim_leon2"
+	bool "GRSIM simulating a LEON2 board"
+	select LEON2
 
 config TARGET_GR_CPCI_AX2000
-	bool "Support gr_cpci_ax2000"
+	bool "Gaisler GR-CPCI-AX2000 board"
+	select LEON3
 
 config TARGET_GR_EP2S60
-	bool "Support gr_ep2s60"
+	bool "Gaisler Template design for Altera NIOS board with Stratix EP2S60"
+	select LEON3
+	help
+	  Gaisler Research AB's Template design (GPL Open Source SPARC/LEON3
+	  96MHz) for Altera NIOS Development board Stratix II edition,
+	  with the FPGA device EP2S60.
 
 config TARGET_GR_XC3S_1500
-	bool "Support gr_xc3s_1500"
+	bool "Gaisler GR-XC3S-1500 spartan board"
+	select LEON3
 
 config TARGET_GRSIM
-	bool "Support grsim"
+	bool "GRSIM simulating a LEON3 GR-XC3S-1500 board"
+	select LEON3
 
 endchoice
 
+config SYS_ARCH
+	default "sparc"
+
+config SYS_CPU
+	default "leon2" if LEON2
+	default "leon3" if LEON3
+
+config SYS_VENDOR
+	default "gaisler"
+
 source "board/gaisler/gr_cpci_ax2000/Kconfig"
 source "board/gaisler/gr_ep2s60/Kconfig"
 source "board/gaisler/gr_xc3s_1500/Kconfig"
diff --git a/arch/sparc/config.mk b/arch/sparc/config.mk
index 196d28af84e..d615f294fed 100644
--- a/arch/sparc/config.mk
+++ b/arch/sparc/config.mk
@@ -15,3 +15,5 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) \
 			       -T $(srctree)/examples/standalone/sparc.lds
 
 PLATFORM_CPPFLAGS += -D__sparc__
+
+PLATFORM_RELFLAGS += -fPIC
diff --git a/arch/sparc/cpu/leon2/config.mk b/arch/sparc/cpu/leon2/config.mk
deleted file mode 100644
index c44b0930ec0..00000000000
--- a/arch/sparc/cpu/leon2/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_RELFLAGS += -fPIC
-
-PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON2
diff --git a/arch/sparc/cpu/leon3/config.mk b/arch/sparc/cpu/leon3/config.mk
deleted file mode 100644
index ca6c9b13ec2..00000000000
--- a/arch/sparc/cpu/leon3/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_RELFLAGS += -fPIC
-
-PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON3
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index ff9935acc4f..0dba8acbb2b 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -4,6 +4,9 @@ menu "x86 architecture"
 config SYS_ARCH
 	default "x86"
 
+config USE_PRIVATE_LIBGCC
+	default y
+
 choice
 	prompt "Target select"
 
diff --git a/arch/x86/config.mk b/arch/x86/config.mk
index 3106079c852..3e7fedb913b 100644
--- a/arch/x86/config.mk
+++ b/arch/x86/config.mk
@@ -28,6 +28,3 @@ PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions -m elf_i386
 LDFLAGS_FINAL += --gc-sections -pie
 LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3
 LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3
-
-export NORMAL_LIBGCC = $(shell $(CC) $(PLATFORM_CPPFLAGS) -print-libgcc-file-name)
-CONFIG_USE_PRIVATE_LIBGCC := arch/x86/lib
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 415bc249893..9d38ef73a7d 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -9,5 +9,5 @@
 #
 
 extra-y	= start.o
-extra-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
-obj-y	= interrupts.o cpu.o
+obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
+obj-y	+= interrupts.o cpu.o call64.o
diff --git a/arch/x86/cpu/call64.S b/arch/x86/cpu/call64.S
new file mode 100644
index 00000000000..74dd5a89dce
--- /dev/null
+++ b/arch/x86/cpu/call64.S
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2014 Google, Inc
+ * Copyright (C) 1991, 1992, 1993  Linus Torvalds
+ *
+ * Parts of this copied from Linux arch/x86/boot/compressed/head_64.S
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/global_data.h>
+#include <asm/msr-index.h>
+#include <asm/processor-flags.h>
+
+.code32
+.globl cpu_call64
+cpu_call64:
+	/*
+	 * cpu_call64(ulong pgtable, ulong setup_base, ulong target)
+	 *
+	 * eax - pgtable
+	 * edx - setup_base
+	 * ecx - target
+	 */
+	cli
+	push	%ecx		/* arg2 = target */
+	push	%edx		/* arg1 = setup_base */
+	mov	%eax, %ebx
+
+	/* Load new GDT with the 64bit segments using 32bit descriptor */
+	leal	gdt, %eax
+	movl	%eax, gdt+2
+	lgdt	gdt
+
+	/* Enable PAE mode */
+	movl	$(X86_CR4_PAE), %eax
+	movl	%eax, %cr4
+
+	/* Enable the boot page tables */
+	leal	(%ebx), %eax
+	movl	%eax, %cr3
+
+	/* Enable Long mode in EFER (Extended Feature Enable Register) */
+	movl	$MSR_EFER, %ecx
+	rdmsr
+	btsl	$_EFER_LME, %eax
+	wrmsr
+
+	/* After gdt is loaded */
+	xorl	%eax, %eax
+	lldt	%ax
+	movl    $0x20, %eax
+	ltr	%ax
+
+	/*
+	 * Setup for the jump to 64bit mode
+	 *
+	 * When the jump is performed we will be in long mode but
+	 * in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1
+	 * (and in turn EFER.LMA = 1). To jump into 64bit mode we use
+	 * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
+	 * We place all of the values on our mini stack so lret can
+	 * used to perform that far jump. See the gdt below.
+	 */
+	pop	%esi			/* setup_base */
+
+	pushl	$0x10
+	leal	lret_target, %eax
+	pushl	%eax
+
+	/* Enter paged protected Mode, activating Long Mode */
+	movl	$(X86_CR0_PG | X86_CR0_PE), %eax
+	movl	%eax, %cr0
+
+	/* Jump from 32bit compatibility mode into 64bit mode. */
+	lret
+
+code64:
+lret_target:
+	pop	%eax			/* target */
+	mov	%eax, %eax		/* Clear bits 63:32 */
+	jmp	*%eax			/* Jump to the 64-bit target */
+
+	.data
+gdt:
+	.word	gdt_end - gdt
+	.long	gdt
+	.word	0
+	.quad	0x0000000000000000	/* NULL descriptor */
+	.quad	0x00af9a000000ffff	/* __KERNEL_CS */
+	.quad	0x00cf92000000ffff	/* __KERNEL_DS */
+	.quad	0x0080890000000000	/* TS descriptor */
+	.quad   0x0000000000000000	/* TS continued */
+gdt_end:
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 623e3af61f0..2e252532d61 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -18,7 +18,10 @@
 
 #include <common.h>
 #include <command.h>
+#include <errno.h>
+#include <malloc.h>
 #include <asm/control_regs.h>
+#include <asm/cpu.h>
 #include <asm/processor.h>
 #include <asm/processor-flags.h>
 #include <asm/interrupt.h>
@@ -240,3 +243,144 @@ int icache_status(void)
 {
 	return 1;
 }
+
+void cpu_enable_paging_pae(ulong cr3)
+{
+	__asm__ __volatile__(
+		/* Load the page table address */
+		"movl	%0, %%cr3\n"
+		/* Enable pae */
+		"movl	%%cr4, %%eax\n"
+		"orl	$0x00000020, %%eax\n"
+		"movl	%%eax, %%cr4\n"
+		/* Enable paging */
+		"movl	%%cr0, %%eax\n"
+		"orl	$0x80000000, %%eax\n"
+		"movl	%%eax, %%cr0\n"
+		:
+		: "r" (cr3)
+		: "eax");
+}
+
+void cpu_disable_paging_pae(void)
+{
+	/* Turn off paging */
+	__asm__ __volatile__ (
+		/* Disable paging */
+		"movl	%%cr0, %%eax\n"
+		"andl	$0x7fffffff, %%eax\n"
+		"movl	%%eax, %%cr0\n"
+		/* Disable pae */
+		"movl	%%cr4, %%eax\n"
+		"andl	$0xffffffdf, %%eax\n"
+		"movl	%%eax, %%cr4\n"
+		:
+		:
+		: "eax");
+}
+
+static bool has_cpuid(void)
+{
+	unsigned long flag;
+
+	asm volatile("pushf\n" \
+		"pop %%eax\n"
+		"mov %%eax, %%ecx\n"	/* ecx = flags */
+		"xor %1, %%eax\n"
+		"push %%eax\n"
+		"popf\n"		/* flags ^= $2 */
+		"pushf\n"
+		"pop %%eax\n"		/* eax = flags */
+		"push %%ecx\n"
+		"popf\n"		/* flags = ecx */
+		"xor %%ecx, %%eax\n"
+		"mov %%eax, %0"
+		: "=r" (flag)
+		: "i" (1 << 21)
+		: "eax", "ecx", "memory");
+
+	return flag != 0;
+}
+
+static bool can_detect_long_mode(void)
+{
+	unsigned long flag;
+
+	asm volatile("mov $0x80000000, %%eax\n"
+		"cpuid\n"
+		"mov %%eax, %0"
+		: "=r" (flag)
+		:
+		: "eax", "ebx", "ecx", "edx", "memory");
+
+	return flag > 0x80000000UL;
+}
+
+static bool has_long_mode(void)
+{
+	unsigned long flag;
+
+	asm volatile("mov $0x80000001, %%eax\n"
+		"cpuid\n"
+		"mov %%edx, %0"
+		: "=r" (flag)
+		:
+		: "eax", "ebx", "ecx", "edx", "memory");
+
+	return flag & (1 << 29) ? true : false;
+}
+
+int cpu_has_64bit(void)
+{
+	return has_cpuid() && can_detect_long_mode() &&
+		has_long_mode();
+}
+
+int print_cpuinfo(void)
+{
+	printf("CPU:   %s\n", cpu_has_64bit() ? "x86_64" : "x86");
+
+	return 0;
+}
+
+#define PAGETABLE_SIZE		(6 * 4096)
+
+/**
+ * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
+ *
+ * @pgtable: Pointer to a 24iKB block of memory
+ */
+static void build_pagetable(uint32_t *pgtable)
+{
+	uint i;
+
+	memset(pgtable, '\0', PAGETABLE_SIZE);
+
+	/* Level 4 needs a single entry */
+	pgtable[0] = (uint32_t)&pgtable[1024] + 7;
+
+	/* Level 3 has one 64-bit entry for each GiB of memory */
+	for (i = 0; i < 4; i++) {
+		pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
+							0x1000 * i + 7;
+	}
+
+	/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
+	for (i = 0; i < 2048; i++)
+		pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
+}
+
+int cpu_jump_to_64bit(ulong setup_base, ulong target)
+{
+	uint32_t *pgtable;
+
+	pgtable = memalign(4096, PAGETABLE_SIZE);
+	if (!pgtable)
+		return -ENOMEM;
+
+	build_pagetable(pgtable);
+	cpu_call64((ulong)pgtable, setup_base, target);
+	free(pgtable);
+
+	return -EFAULT;
+}
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 329bb3ab35b..338bab19e47 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -85,12 +85,25 @@ car_init_ret:
 	/* Align global data to 16-byte boundary */
 	andl	$0xfffffff0, %esp
 
+	/* Zero the global data since it won't happen later */
+	xorl	%eax, %eax
+	movl	$GENERATED_GBL_DATA_SIZE, %ecx
+	movl	%esp, %edi
+	rep	stosb
+
 	/* Setup first parameter to setup_gdt */
 	movl	%esp, %eax
 
 	/* Reserve space for global descriptor table */
 	subl	$X86_GDT_SIZE, %esp
 
+#if defined(CONFIG_SYS_MALLOC_F_LEN)
+	subl	$CONFIG_SYS_MALLOC_F_LEN, %esp
+	movl	%eax, %edx
+	addl	$GD_MALLOC_BASE, %edx
+	movl	%esp, (%edx)
+#endif
+
 	/* Align temporary global descriptor table to 16-byte boundary */
 	andl	$0xfffffff0, %esp
 
diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S
index 8b9b327cd48..6968fda6494 100644
--- a/arch/x86/cpu/start16.S
+++ b/arch/x86/cpu/start16.S
@@ -70,7 +70,7 @@ idt_ptr:
  * GDT is setup in a safe location in RAM
  */
 gdt_ptr:
-	.word	0x20		/* limit (32 bytes = 4 GDT entries) */
+	.word	0x1f		/* limit (31 bytes = 4 GDT entries - 1) */
 	.long	BOOT_SEG + gdt	/* base */
 
 /* Some CPUs are picky about GDT alignment... */
diff --git a/arch/x86/dts/coreboot.dtsi b/arch/x86/dts/coreboot.dtsi
index 4862a59704e..c8dc4cec3c9 100644
--- a/arch/x86/dts/coreboot.dtsi
+++ b/arch/x86/dts/coreboot.dtsi
@@ -1,13 +1,14 @@
 /include/ "skeleton.dtsi"
 
 / {
-	aliases {
-		console = "/serial";
+	chosen {
+		stdout-path = "/serial";
 	};
 
 	serial {
-		compatible = "ns16550";
-		reg-shift = <1>;
+		compatible = "coreboot-uart";
+		reg = <0x3f8 0x10>;
+		reg-shift = <0>;
 		io-mapped = <1>;
 		multiplier = <1>;
 		baudrate = <115200>;
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
index 4a37dac4ea9..f2fcb3927cb 100644
--- a/arch/x86/dts/link.dts
+++ b/arch/x86/dts/link.dts
@@ -12,7 +12,23 @@
 	       silent_console = <0>;
 	};
 
-	gpio: gpio {};
+	gpioa {
+		compatible = "intel,ich6-gpio";
+		reg = <0 0x10>;
+		bank-name = "A";
+	};
+
+	gpiob {
+		compatible = "intel,ich6-gpio";
+		reg = <0x30 0x10>;
+		bank-name = "B";
+	};
+
+	gpioc {
+		compatible = "intel,ich6-gpio";
+		reg = <0x40 0x10>;
+		bank-name = "C";
+	};
 
 	serial {
 		reg = <0x3f8 8>;
@@ -32,4 +48,22 @@
 			memory-map = <0xff800000 0x00800000>;
 		};
 	};
+
+	lpc {
+		compatible = "intel,lpc";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		cros-ec@200 {
+			compatible = "google,cros-ec";
+			reg = <0x204 1 0x200 1 0x880 0x80>;
+
+			/* This describes the flash memory within the EC */
+			#address-cells = <1>;
+			#size-cells = <1>;
+			flash@8000000 {
+				reg = <0x08000000 0x20000>;
+				erase-value = <0xff>;
+			};
+		};
+	};
 };
diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h b/arch/x86/include/asm/arch-coreboot/gpio.h
new file mode 100644
index 00000000000..3ec18168339
--- /dev/null
+++ b/arch/x86/include/asm/arch-coreboot/gpio.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2014, Google Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_GPIO_H_
+#define _X86_ARCH_GPIO_H_
+
+struct ich6_bank_platdata {
+	uint32_t base_addr;
+	const char *bank_name;
+};
+
+#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/bootm.h b/arch/x86/include/asm/bootm.h
new file mode 100644
index 00000000000..f6a64ce2c91
--- /dev/null
+++ b/arch/x86/include/asm/bootm.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARM_BOOTM_H
+#define ARM_BOOTM_H
+
+void bootm_announce_and_cleanup(void);
+
+/**
+ * boot_linux_kernel() - boot a linux kernel
+ *
+ * This boots a kernel image, either 32-bit or 64-bit. It will also work with
+ * a self-extracting kernel, if you set @image_64bit to false.
+ *
+ * @setup_base:		Pointer to the setup.bin information for the kernel
+ * @load_address:	Pointer to the start of the kernel image
+ * @image_64bit:	true if the image is a raw 64-bit kernel, false if it
+ *			is raw 32-bit or any type of self-extracting kernel
+ *			such as a bzImage.
+ * @return -ve error code. This function does not return if the kernel was
+ * booted successfully.
+ */
+int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit);
+
+#endif
diff --git a/arch/x86/include/asm/config.h b/arch/x86/include/asm/config.h
index f06a15cdfca..ff15828a713 100644
--- a/arch/x86/include/asm/config.h
+++ b/arch/x86/include/asm/config.h
@@ -8,4 +8,7 @@
 #define _ASM_CONFIG_H_
 
 #define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
 #endif
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
new file mode 100644
index 00000000000..6c6774af76c
--- /dev/null
+++ b/arch/x86/include/asm/cpu.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2014 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __X86_CPU_H
+#define __X86_CPU_H
+
+ /**
+ * cpu_enable_paging_pae() - Enable PAE-paging
+ *
+ * @pdpt:	Value to set in cr3 (PDPT or PML4T)
+ */
+void cpu_enable_paging_pae(ulong cr3);
+
+/**
+ * cpu_disable_paging_pae() - Disable paging and PAE
+ */
+void cpu_disable_paging_pae(void);
+
+/**
+ * cpu_has_64bit() - Check if the CPU has 64-bit support
+ *
+ * @return 1 if this CPU supports long mode (64-bit), 0 if not
+ */
+int cpu_has_64bit(void);
+
+/**
+ * cpu_call64() - Jump to a 64-bit Linux kernel (internal function)
+ *
+ * The kernel is uncompressed and the 64-bit entry point is expected to be
+ * at @target.
+ *
+ * This function is used internally - see cpu_jump_to_64bit() for a more
+ * useful function.
+ *
+ * @pgtable:	Address of 24KB area containing the page table
+ * @setup_base:	Pointer to the setup.bin information for the kernel
+ * @target:	Pointer to the start of the kernel image
+ */
+void cpu_call64(ulong pgtable, ulong setup_base, ulong target);
+
+/**
+ * cpu_jump_to_64bit() - Jump to a 64-bit Linux kernel
+ *
+ * The kernel is uncompressed and the 64-bit entry point is expected to be
+ * at @target.
+ *
+ * @setup_base:	Pointer to the setup.bin information for the kernel
+ * @target:	Pointer to the start of the kernel image
+ */
+int cpu_jump_to_64bit(ulong setup_base, ulong target);
+
+#endif
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index fe09f315154..8bda414dbd7 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -6,6 +6,7 @@
 #ifndef _X86_GPIO_H_
 #define _X86_GPIO_H_
 
+#include <asm/arch/gpio.h>
 #include <asm-generic/gpio.h>
 
 #endif /* _X86_GPIO_H_ */
diff --git a/arch/x86/include/asm/ibmpc.h b/arch/x86/include/asm/ibmpc.h
index 0f9665f5495..e6d183b4796 100644
--- a/arch/x86/include/asm/ibmpc.h
+++ b/arch/x86/include/asm/ibmpc.h
@@ -18,14 +18,4 @@
 #define SYSCTLA         0x92
 #define SLAVE_PIC       0xa0
 
-#if 1
-#define UART0_BASE     0x3f8
-#define UART1_BASE     0x2f8
-#else
-/* FixMe: uarts swapped */
-#define UART0_BASE     0x2f8
-#define UART1_BASE     0x3f8
-#endif
-
-
 #endif
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 0a36e178f57..6027d593ff1 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -44,12 +44,16 @@
 #define MSR_IA32_PERFCTR0		0x000000c1
 #define MSR_IA32_PERFCTR1		0x000000c2
 #define MSR_FSB_FREQ			0x000000cd
+#define MSR_NHM_PLATFORM_INFO		0x000000ce
 
 #define MSR_NHM_SNB_PKG_CST_CFG_CTL	0x000000e2
 #define NHM_C3_AUTO_DEMOTE		(1UL << 25)
 #define NHM_C1_AUTO_DEMOTE		(1UL << 26)
 #define ATM_LNC_C6_AUTO_DEMOTE		(1UL << 25)
+#define SNB_C1_AUTO_UNDEMOTE		(1UL << 27)
+#define SNB_C3_AUTO_UNDEMOTE		(1UL << 28)
 
+#define MSR_PLATFORM_INFO		0x000000ce
 #define MSR_MTRRcap			0x000000fe
 #define MSR_IA32_BBL_CR_CTL		0x00000119
 #define MSR_IA32_BBL_CR_CTL3		0x0000011e
@@ -64,10 +68,20 @@
 
 #define MSR_OFFCORE_RSP_0		0x000001a6
 #define MSR_OFFCORE_RSP_1		0x000001a7
+#define MSR_NHM_TURBO_RATIO_LIMIT	0x000001ad
+#define MSR_IVT_TURBO_RATIO_LIMIT	0x000001ae
+
+#define MSR_LBR_SELECT			0x000001c8
+#define MSR_LBR_TOS			0x000001c9
+#define MSR_LBR_NHM_FROM		0x00000680
+#define MSR_LBR_NHM_TO			0x000006c0
+#define MSR_LBR_CORE_FROM		0x00000040
+#define MSR_LBR_CORE_TO			0x00000060
 
 #define MSR_IA32_PEBS_ENABLE		0x000003f1
 #define MSR_IA32_DS_AREA		0x00000600
 #define MSR_IA32_PERF_CAPABILITIES	0x00000345
+#define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6
 
 #define MSR_MTRRfix64K_00000		0x00000250
 #define MSR_MTRRfix16K_80000		0x00000258
@@ -91,7 +105,8 @@
 #define MSR_IA32_LASTINTTOIP		0x000001de
 
 /* DEBUGCTLMSR bits (others vary by model): */
-#define DEBUGCTLMSR_LBR			(1UL <<  0)
+#define DEBUGCTLMSR_LBR			(1UL <<  0) /* last branch recording */
+/* single-step on branches */
 #define DEBUGCTLMSR_BTF			(1UL <<  1)
 #define DEBUGCTLMSR_TR			(1UL <<  6)
 #define DEBUGCTLMSR_BTS			(1UL <<  7)
@@ -100,11 +115,50 @@
 #define DEBUGCTLMSR_BTS_OFF_USR		(1UL << 10)
 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI	(1UL << 11)
 
+#define MSR_IA32_POWER_CTL		0x000001fc
+
 #define MSR_IA32_MC0_CTL		0x00000400
 #define MSR_IA32_MC0_STATUS		0x00000401
 #define MSR_IA32_MC0_ADDR		0x00000402
 #define MSR_IA32_MC0_MISC		0x00000403
 
+/* C-state Residency Counters */
+#define MSR_PKG_C3_RESIDENCY		0x000003f8
+#define MSR_PKG_C6_RESIDENCY		0x000003f9
+#define MSR_PKG_C7_RESIDENCY		0x000003fa
+#define MSR_CORE_C3_RESIDENCY		0x000003fc
+#define MSR_CORE_C6_RESIDENCY		0x000003fd
+#define MSR_CORE_C7_RESIDENCY		0x000003fe
+#define MSR_PKG_C2_RESIDENCY		0x0000060d
+#define MSR_PKG_C8_RESIDENCY		0x00000630
+#define MSR_PKG_C9_RESIDENCY		0x00000631
+#define MSR_PKG_C10_RESIDENCY		0x00000632
+
+/* Run Time Average Power Limiting (RAPL) Interface */
+
+#define MSR_RAPL_POWER_UNIT		0x00000606
+
+#define MSR_PKG_POWER_LIMIT		0x00000610
+#define MSR_PKG_ENERGY_STATUS		0x00000611
+#define MSR_PKG_PERF_STATUS		0x00000613
+#define MSR_PKG_POWER_INFO		0x00000614
+
+#define MSR_DRAM_POWER_LIMIT		0x00000618
+#define MSR_DRAM_ENERGY_STATUS		0x00000619
+#define MSR_DRAM_PERF_STATUS		0x0000061b
+#define MSR_DRAM_POWER_INFO		0x0000061c
+
+#define MSR_PP0_POWER_LIMIT		0x00000638
+#define MSR_PP0_ENERGY_STATUS		0x00000639
+#define MSR_PP0_POLICY			0x0000063a
+#define MSR_PP0_PERF_STATUS		0x0000063b
+
+#define MSR_PP1_POWER_LIMIT		0x00000640
+#define MSR_PP1_ENERGY_STATUS		0x00000641
+#define MSR_PP1_POLICY			0x00000642
+
+#define MSR_CORE_C1_RES			0x00000660
+
 #define MSR_AMD64_MC0_MASK		0xc0010044
 
 #define MSR_IA32_MCx_CTL(x)		(MSR_IA32_MC0_CTL + 4*(x))
@@ -123,18 +177,31 @@
 #define MSR_P6_EVNTSEL0			0x00000186
 #define MSR_P6_EVNTSEL1			0x00000187
 
+#define MSR_KNC_PERFCTR0               0x00000020
+#define MSR_KNC_PERFCTR1               0x00000021
+#define MSR_KNC_EVNTSEL0               0x00000028
+#define MSR_KNC_EVNTSEL1               0x00000029
+
+/* Alternative perfctr range with full access. */
+#define MSR_IA32_PMC0			0x000004c1
+
 /* AMD64 MSRs. Not complete. See the architecture manual for a more
    complete list. */
 
 #define MSR_AMD64_PATCH_LEVEL		0x0000008b
+#define MSR_AMD64_TSC_RATIO		0xc0000104
 #define MSR_AMD64_NB_CFG		0xc001001f
 #define MSR_AMD64_PATCH_LOADER		0xc0010020
 #define MSR_AMD64_OSVW_ID_LENGTH	0xc0010140
 #define MSR_AMD64_OSVW_STATUS		0xc0010141
+#define MSR_AMD64_LS_CFG		0xc0011020
 #define MSR_AMD64_DC_CFG		0xc0011022
+#define MSR_AMD64_BU_CFG2		0xc001102a
 #define MSR_AMD64_IBSFETCHCTL		0xc0011030
 #define MSR_AMD64_IBSFETCHLINAD		0xc0011031
 #define MSR_AMD64_IBSFETCHPHYSAD	0xc0011032
+#define MSR_AMD64_IBSFETCH_REG_COUNT	3
+#define MSR_AMD64_IBSFETCH_REG_MASK	((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
 #define MSR_AMD64_IBSOPCTL		0xc0011033
 #define MSR_AMD64_IBSOPRIP		0xc0011034
 #define MSR_AMD64_IBSOPDATA		0xc0011035
@@ -142,12 +209,21 @@
 #define MSR_AMD64_IBSOPDATA3		0xc0011037
 #define MSR_AMD64_IBSDCLINAD		0xc0011038
 #define MSR_AMD64_IBSDCPHYSAD		0xc0011039
+#define MSR_AMD64_IBSOP_REG_COUNT	7
+#define MSR_AMD64_IBSOP_REG_MASK	((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
 #define MSR_AMD64_IBSCTL		0xc001103a
 #define MSR_AMD64_IBSBRTARGET		0xc001103b
+#define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */
+
+/* Fam 16h MSRs */
+#define MSR_F16H_L2I_PERF_CTL		0xc0010230
+#define MSR_F16H_L2I_PERF_CTR		0xc0010231
 
 /* Fam 15h MSRs */
 #define MSR_F15H_PERF_CTL		0xc0010200
 #define MSR_F15H_PERF_CTR		0xc0010201
+#define MSR_F15H_NB_PERF_CTL		0xc0010240
+#define MSR_F15H_NB_PERF_CTR		0xc0010241
 
 /* Fam 10h MSRs */
 #define MSR_FAM10H_MMIO_CONF_BASE	0xc0010058
@@ -226,7 +302,9 @@
 #define MSR_IA32_PLATFORM_ID		0x00000017
 #define MSR_IA32_EBL_CR_POWERON		0x0000002a
 #define MSR_EBC_FREQUENCY_ID		0x0000002c
+#define MSR_SMI_COUNT			0x00000034
 #define MSR_IA32_FEATURE_CONTROL        0x0000003a
+#define MSR_IA32_TSC_ADJUST             0x0000003b
 
 #define FEATURE_CONTROL_LOCKED				(1<<0)
 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX	(1<<1)
@@ -237,11 +315,16 @@
 #define MSR_IA32_APICBASE_ENABLE	(1<<11)
 #define MSR_IA32_APICBASE_BASE		(0xfffff<<12)
 
+#define MSR_IA32_TSCDEADLINE		0x000006e0
+
 #define MSR_IA32_UCODE_WRITE		0x00000079
 #define MSR_IA32_UCODE_REV		0x0000008b
 
 #define MSR_IA32_PERF_STATUS		0x00000198
 #define MSR_IA32_PERF_CTL		0x00000199
+#define MSR_AMD_PSTATE_DEF_BASE		0xc0010064
+#define MSR_AMD_PERF_STATUS		0xc0010063
+#define MSR_AMD_PERF_CTL		0xc0010062
 
 #define MSR_IA32_MPERF			0x000000e7
 #define MSR_IA32_APERF			0x000000e8
@@ -267,6 +350,9 @@
 #define MSR_IA32_TEMPERATURE_TARGET	0x000001a2
 
 #define MSR_IA32_ENERGY_PERF_BIAS	0x000001b0
+#define ENERGY_PERF_BIAS_PERFORMANCE	0
+#define ENERGY_PERF_BIAS_NORMAL		6
+#define ENERGY_PERF_BIAS_POWERSAVE	15
 
 #define MSR_IA32_PACKAGE_THERM_STATUS		0x000001b1
 
@@ -320,6 +406,8 @@
 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE	(1ULL << 38)
 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE	(1ULL << 39)
 
+#define MSR_IA32_TSC_DEADLINE		0x000006E0
+
 /* P4/Xeon+ specific */
 #define MSR_IA32_MCG_EAX		0x00000180
 #define MSR_IA32_MCG_EBX		0x00000181
@@ -446,7 +534,23 @@
 #define MSR_IA32_VMX_VMCS_ENUM          0x0000048a
 #define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
 #define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
-
+#define MSR_IA32_VMX_TRUE_PINBASED_CTLS  0x0000048d
+#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
+#define MSR_IA32_VMX_TRUE_EXIT_CTLS      0x0000048f
+#define MSR_IA32_VMX_TRUE_ENTRY_CTLS     0x00000490
+#define MSR_IA32_VMX_VMFUNC             0x00000491
+
+/* VMX_BASIC bits and bitmasks */
+#define VMX_BASIC_VMCS_SIZE_SHIFT	32
+#define VMX_BASIC_64		0x0001000000000000LLU
+#define VMX_BASIC_MEM_TYPE_SHIFT	50
+#define VMX_BASIC_MEM_TYPE_MASK	0x003c000000000000LLU
+#define VMX_BASIC_MEM_TYPE_WB	6LLU
+#define VMX_BASIC_INOUT		0x0040000000000000LLU
+
+/* MSR_IA32_VMX_MISC bits */
+#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
+#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE   0x1F
 /* AMD-V MSRs */
 
 #define MSR_VM_CR                       0xc0010114
diff --git a/arch/x86/include/asm/types.h b/arch/x86/include/asm/types.h
index e9fde88f7d4..e272c90eb7f 100644
--- a/arch/x86/include/asm/types.h
+++ b/arch/x86/include/asm/types.h
@@ -36,8 +36,13 @@ typedef unsigned short u16;
 typedef signed int s32;
 typedef unsigned int u32;
 
+#if !defined(CONFIG_USE_STDINT) || !defined(__INT64_TYPE__)
 typedef signed long long s64;
 typedef unsigned long long u64;
+#else
+typedef __INT64_TYPE__ s64;
+typedef __UINT64_TYPE__ u64;
+#endif
 
 #define BITS_PER_LONG 32
 
diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
index 0f366626880..8e7dd424ca5 100644
--- a/arch/x86/include/asm/zimage.h
+++ b/arch/x86/include/asm/zimage.h
@@ -35,10 +35,8 @@
 unsigned install_e820_map(unsigned max_entries, struct e820entry *);
 
 struct boot_params *load_zimage(char *image, unsigned long kernel_size,
-				void **load_address);
+				ulong *load_addressp);
 int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
 		 unsigned long initrd_addr, unsigned long initrd_size);
 
-void boot_zimage(void *setup_base, void *load_address);
-
 #endif
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index f7303abccbd..25b672a0c13 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -20,9 +20,9 @@ obj-$(CONFIG_SYS_X86_TSC_TIMER)	+= tsc_timer.o
 obj-$(CONFIG_VIDEO_VGA)	+= video.o
 obj-$(CONFIG_CMD_ZBOOT)	+= zimage.o
 
-LIBGCC := $(notdir $(NORMAL_LIBGCC))
-extra-y := $(LIBGCC)
+extra-$(CONFIG_USE_PRIVATE_LIBGCC) := lib.a
 
+NORMAL_LIBGCC = $(shell $(CC) $(PLATFORM_CPPFLAGS) -print-libgcc-file-name)
 OBJCOPYFLAGS := --prefix-symbols=__normal_
-$(obj)/$(LIBGCC): $(NORMAL_LIBGCC) FORCE
+$(obj)/lib.a: $(NORMAL_LIBGCC) FORCE
 	$(call if_changed,objcopy)
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index ff158dd6a9d..86030cf52aa 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -10,80 +10,195 @@
 
 #include <common.h>
 #include <command.h>
+#include <errno.h>
+#include <fdt_support.h>
 #include <image.h>
 #include <u-boot/zlib.h>
 #include <asm/bootparam.h>
+#include <asm/cpu.h>
 #include <asm/byteorder.h>
 #include <asm/zimage.h>
+#ifdef CONFIG_SYS_COREBOOT
+#include <asm/arch/timestamp.h>
+#endif
 
 #define COMMAND_LINE_OFFSET 0x9000
 
-/*cmd_boot.c*/
-int do_bootm_linux(int flag, int argc, char * const argv[],
-		bootm_headers_t *images)
+/*
+ * Implement a weak default function for boards that optionally
+ * need to clean up the system before jumping to the kernel.
+ */
+__weak void board_final_cleanup(void)
 {
-	struct boot_params *base_ptr = NULL;
-	ulong os_data, os_len;
-	image_header_t *hdr;
-	void *load_address;
+}
 
-#if defined(CONFIG_FIT)
-	const void	*data;
-	size_t		len;
+void bootm_announce_and_cleanup(void)
+{
+	printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_SYS_COREBOOT
+	timestamp_add_now(TS_U_BOOT_START_KERNEL);
 #endif
+	bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
+#ifdef CONFIG_BOOTSTAGE_REPORT
+	bootstage_report();
+#endif
+	board_final_cleanup();
+}
 
-	if (flag & BOOTM_STATE_OS_PREP)
-		return 0;
-	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
-		return 1;
+#if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL)
+int arch_fixup_memory_node(void *blob)
+{
+	bd_t	*bd = gd->bd;
+	int bank;
+	u64 start[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
 
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		start[bank] = bd->bi_dram[bank].start;
+		size[bank] = bd->bi_dram[bank].size;
+	}
+
+	return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
+}
+#endif
+
+/* Subcommand: PREP */
+static int boot_prep_linux(bootm_headers_t *images)
+{
+	char *cmd_line_dest = NULL;
+	image_header_t *hdr;
+	int is_zimage = 0;
+	void *data = NULL;
+	size_t len;
+	int ret;
+
+#ifdef CONFIG_OF_LIBFDT
+	if (images->ft_len) {
+		debug("using: FDT\n");
+		if (image_setup_linux(images)) {
+			puts("FDT creation failed! hanging...");
+			hang();
+		}
+	}
+#endif
 	if (images->legacy_hdr_valid) {
 		hdr = images->legacy_hdr_os;
 		if (image_check_type(hdr, IH_TYPE_MULTI)) {
+			ulong os_data, os_len;
+
 			/* if multi-part image, we need to get first subimage */
 			image_multi_getimg(hdr, 0, &os_data, &os_len);
+			data = (void *)os_data;
+			len = os_len;
 		} else {
 			/* otherwise get image data */
-			os_data = image_get_data(hdr);
-			os_len = image_get_data_size(hdr);
+			data = (void *)image_get_data(hdr);
+			len = image_get_data_size(hdr);
 		}
+		is_zimage = 1;
 #if defined(CONFIG_FIT)
-	} else if (images->fit_uname_os) {
-		int ret;
-
+	} else if (images->fit_uname_os && is_zimage) {
 		ret = fit_image_get_data(images->fit_hdr_os,
-					images->fit_noffset_os, &data, &len);
+				images->fit_noffset_os,
+				(const void **)&data, &len);
 		if (ret) {
 			puts("Can't get image data/size!\n");
 			goto error;
 		}
-		os_data = (ulong)data;
-		os_len = (ulong)len;
+		is_zimage = 1;
 #endif
-	} else {
-		puts("Could not find kernel image!\n");
-		goto error;
 	}
 
-#ifdef CONFIG_CMD_ZBOOT
-	base_ptr = load_zimage((void *)os_data, os_len, &load_address);
-#endif
+	if (is_zimage) {
+		ulong load_address;
+		char *base_ptr;
 
-	if (NULL == base_ptr) {
-		printf("## Kernel loading failed ...\n");
+		base_ptr = (char *)load_zimage(data, len, &load_address);
+		images->os.load = load_address;
+		cmd_line_dest = base_ptr + COMMAND_LINE_OFFSET;
+		images->ep = (ulong)base_ptr;
+	} else if (images->ep) {
+		cmd_line_dest = (void *)images->ep + COMMAND_LINE_OFFSET;
+	} else {
+		printf("## Kernel loading failed (missing x86 kernel setup) ...\n");
 		goto error;
 	}
 
-	if (setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET,
+	printf("Setup at %#08lx\n", images->ep);
+	ret = setup_zimage((void *)images->ep, cmd_line_dest,
 			0, images->rd_start,
-			images->rd_end - images->rd_start)) {
+			images->rd_end - images->rd_start);
+
+	if (ret) {
 		printf("## Setting up boot parameters failed ...\n");
-		goto error;
+		return 1;
 	}
 
-	boot_zimage(base_ptr, load_address);
-	/* does not return */
+	return 0;
 
 error:
 	return 1;
 }
+
+int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit)
+{
+	bootm_announce_and_cleanup();
+
+#ifdef CONFIG_SYS_COREBOOT
+	timestamp_add_now(TS_U_BOOT_START_KERNEL);
+#endif
+	if (image_64bit) {
+		if (!cpu_has_64bit()) {
+			puts("Cannot boot 64-bit kernel on 32-bit machine\n");
+			return -EFAULT;
+		}
+		return cpu_jump_to_64bit(setup_base, load_address);
+	} else {
+		/*
+		* Set %ebx, %ebp, and %edi to 0, %esi to point to the
+		* boot_params structure, and then jump to the kernel. We
+		* assume that %cs is 0x10, 4GB flat, and read/execute, and
+		* the data segments are 0x18, 4GB flat, and read/write.
+		* U-boot is setting them up that way for itself in
+		* arch/i386/cpu/cpu.c.
+		*/
+		__asm__ __volatile__ (
+		"movl $0, %%ebp\n"
+		"cli\n"
+		"jmp *%[kernel_entry]\n"
+		:: [kernel_entry]"a"(load_address),
+		[boot_params] "S"(setup_base),
+		"b"(0), "D"(0)
+		);
+	}
+
+	/* We can't get to here */
+	return -EFAULT;
+}
+
+/* Subcommand: GO */
+static int boot_jump_linux(bootm_headers_t *images)
+{
+	debug("## Transferring control to Linux (at address %08lx, kernel %08lx) ...\n",
+	      images->ep, images->os.load);
+
+	return boot_linux_kernel(images->ep, images->os.load,
+				 images->os.arch == IH_ARCH_X86_64);
+}
+
+int do_bootm_linux(int flag, int argc, char * const argv[],
+		bootm_headers_t *images)
+{
+	/* No need for those on x86 */
+	if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE)
+		return -1;
+
+	if (flag & BOOTM_STATE_OS_PREP)
+		return boot_prep_linux(images);
+
+	if (flag & BOOTM_STATE_OS_GO)
+		return boot_jump_linux(images);
+
+	return boot_jump_linux(images);
+}
diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c
index b57b2c30fe3..c3c709ec072 100644
--- a/arch/x86/lib/physmem.c
+++ b/arch/x86/lib/physmem.c
@@ -10,6 +10,7 @@
 
 #include <common.h>
 #include <physmem.h>
+#include <asm/cpu.h>
 #include <linux/compiler.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -112,41 +113,13 @@ static void x86_phys_enter_paging(void)
 		x86_phys_map_page(page_addr, page_addr, 0);
 	}
 
-	/* Turn on paging */
-	__asm__ __volatile__(
-		/* Load the page table address */
-		"movl	%0, %%cr3\n\t"
-		/* Enable pae */
-		"movl	%%cr4, %%eax\n\t"
-		"orl	$0x00000020, %%eax\n\t"
-		"movl	%%eax, %%cr4\n\t"
-		/* Enable paging */
-		"movl	%%cr0, %%eax\n\t"
-		"orl	$0x80000000, %%eax\n\t"
-		"movl	%%eax, %%cr0\n\t"
-		:
-		: "r" (pdpt)
-		: "eax"
-	);
+	cpu_enable_paging_pae((ulong)pdpt);
 }
 
 /* Disable paging and PAE mode. */
 static void x86_phys_exit_paging(void)
 {
-	/* Turn off paging */
-	__asm__ __volatile__ (
-		/* Disable paging */
-		"movl	%%cr0, %%eax\n\t"
-		"andl	$0x7fffffff, %%eax\n\t"
-		"movl	%%eax, %%cr0\n\t"
-		/* Disable pae */
-		"movl	%%cr4, %%eax\n\t"
-		"andl	$0xffffffdf, %%eax\n\t"
-		"movl	%%eax, %%cr4\n\t"
-		:
-		:
-		: "eax"
-	);
+	cpu_disable_paging_pae();
 }
 
 /*
diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c
index 526daaf93a6..faca38fff4b 100644
--- a/arch/x86/lib/relocate.c
+++ b/arch/x86/lib/relocate.c
@@ -16,6 +16,7 @@
  */
 
 #include <common.h>
+#include <inttypes.h>
 #include <libfdt.h>
 #include <malloc.h>
 #include <asm/u-boot-x86.h>
@@ -94,7 +95,7 @@ int do_elf_reloc_fixups(void)
 				*offset_ptr_ram += gd->reloc_off;
 			} else {
 				debug("   %p: rom reloc %x, ram %p, value %x,"
-					" limit %lx\n", re_src,
+					" limit %" PRIXPTR "\n", re_src,
 					re_src->r_offset, offset_ptr_ram,
 					*offset_ptr_ram,
 					CONFIG_SYS_TEXT_BASE + size);
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 1dab3cc7887..566b048c88f 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -18,6 +18,7 @@
 #include <asm/ptrace.h>
 #include <asm/zimage.h>
 #include <asm/byteorder.h>
+#include <asm/bootm.h>
 #include <asm/bootparam.h>
 #ifdef CONFIG_SYS_COREBOOT
 #include <asm/arch/timestamp.h>
@@ -102,7 +103,7 @@ static int get_boot_protocol(struct setup_header *hdr)
 }
 
 struct boot_params *load_zimage(char *image, unsigned long kernel_size,
-				void **load_address)
+				ulong *load_addressp)
 {
 	struct boot_params *setup_base;
 	int setup_size;
@@ -154,9 +155,9 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size,
 
 	/* Determine load address */
 	if (big_image)
-		*load_address = (void *)BZIMAGE_LOAD_ADDR;
+		*load_addressp = BZIMAGE_LOAD_ADDR;
 	else
-		*load_address = (void *)ZIMAGE_LOAD_ADDR;
+		*load_addressp = ZIMAGE_LOAD_ADDR;
 
 	printf("Building boot_params at 0x%8.8lx\n", (ulong)setup_base);
 	memset(setup_base, 0, sizeof(*setup_base));
@@ -203,10 +204,10 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size,
 		return 0;
 	}
 
-	printf("Loading %s at address %p (%ld bytes)\n",
-		big_image ? "bzImage" : "zImage", *load_address, kernel_size);
+	printf("Loading %s at address %lx (%ld bytes)\n",
+	       big_image ? "bzImage" : "zImage", *load_addressp, kernel_size);
 
-	memmove(*load_address, image + setup_size, kernel_size);
+	memmove((void *)*load_addressp, image + setup_size, kernel_size);
 
 	return setup_base;
 }
@@ -242,63 +243,24 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
 		hdr->loadflags |= HEAP_FLAG;
 	}
 
-	if (bootproto >= 0x0202) {
-		hdr->cmd_line_ptr = (uintptr_t)cmd_line;
-	} else if (bootproto >= 0x0200) {
-		setup_base->screen_info.cl_magic = COMMAND_LINE_MAGIC;
-		setup_base->screen_info.cl_offset =
-			(uintptr_t)cmd_line - (uintptr_t)setup_base;
+	if (cmd_line) {
+		if (bootproto >= 0x0202) {
+			hdr->cmd_line_ptr = (uintptr_t)cmd_line;
+		} else if (bootproto >= 0x0200) {
+			setup_base->screen_info.cl_magic = COMMAND_LINE_MAGIC;
+			setup_base->screen_info.cl_offset =
+				(uintptr_t)cmd_line - (uintptr_t)setup_base;
+
+			hdr->setup_move_size = 0x9100;
+		}
 
-		hdr->setup_move_size = 0x9100;
+		/* build command line at COMMAND_LINE_OFFSET */
+		build_command_line(cmd_line, auto_boot);
 	}
 
-	/* build command line at COMMAND_LINE_OFFSET */
-	build_command_line(cmd_line, auto_boot);
 	return 0;
 }
 
-/*
- * Implement a weak default function for boards that optionally
- * need to clean up the system before jumping to the kernel.
- */
-__weak void board_final_cleanup(void)
-{
-}
-
-void boot_zimage(void *setup_base, void *load_address)
-{
-	debug("## Transferring control to Linux (at address %08x) ...\n",
-	      (u32)setup_base);
-
-	bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
-#ifdef CONFIG_BOOTSTAGE_REPORT
-	bootstage_report();
-#endif
-	board_final_cleanup();
-
-	printf("\nStarting kernel ...\n\n");
-
-#ifdef CONFIG_SYS_COREBOOT
-	timestamp_add_now(TS_U_BOOT_START_KERNEL);
-#endif
-	/*
-	 * Set %ebx, %ebp, and %edi to 0, %esi to point to the boot_params
-	 * structure, and then jump to the kernel. We assume that %cs is
-	 * 0x10, 4GB flat, and read/execute, and the data segments are 0x18,
-	 * 4GB flat, and read/write. U-boot is setting them up that way for
-	 * itself in arch/i386/cpu/cpu.c.
-	 */
-	__asm__ __volatile__ (
-	"movl $0, %%ebp\n"
-	"cli\n"
-	"jmp *%[kernel_entry]\n"
-	:: [kernel_entry]"a"(load_address),
-	   [boot_params] "S"(setup_base),
-	   "b"(0), "D"(0)
-	:  "%ebp"
-	);
-}
-
 void setup_pcat_compatibility(void)
 	__attribute__((weak, alias("__setup_pcat_compatibility")));
 
@@ -310,7 +272,7 @@ int do_zboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
 	struct boot_params *base_ptr;
 	void *bzImage_addr = NULL;
-	void *load_address;
+	ulong load_address;
 	char *s;
 	ulong bzImage_size = 0;
 	ulong initrd_addr = 0;
@@ -345,20 +307,17 @@ int do_zboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 	base_ptr = load_zimage(bzImage_addr, bzImage_size, &load_address);
 
 	if (!base_ptr) {
-		printf("## Kernel loading failed ...\n");
+		puts("## Kernel loading failed ...\n");
 		return -1;
 	}
 	if (setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET,
 			0, initrd_addr, initrd_size)) {
-		printf("Setting up boot parameters failed ...\n");
+		puts("Setting up boot parameters failed ...\n");
 		return -1;
 	}
 
 	/* we assume that the kernel is in place */
-	boot_zimage(base_ptr, load_address);
-	/* does not return */
-
-	return -1;
+	return boot_linux_kernel((ulong)base_ptr, load_address, false);
 }
 
 U_BOOT_CMD(
diff --git a/board/8dtech/eco5pk/eco5pk.h b/board/8dtech/eco5pk/eco5pk.h
index a7947648527..acf2b803079 100644
--- a/board/8dtech/eco5pk/eco5pk.h
+++ b/board/8dtech/eco5pk/eco5pk.h
@@ -332,7 +332,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
 	/* JTAG */\
-	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_NTRST),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) \
diff --git a/board/BuR/kwb/Kconfig b/board/BuR/kwb/Kconfig
index f9107a9a4b0..4beefbf7714 100644
--- a/board/BuR/kwb/Kconfig
+++ b/board/BuR/kwb/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_KWB
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "kwb"
 
diff --git a/board/BuR/tseries/Kconfig b/board/BuR/tseries/Kconfig
index ee510d3480b..ed48300c0a8 100644
--- a/board/BuR/tseries/Kconfig
+++ b/board/BuR/tseries/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_TSERIES
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "tseries"
 
diff --git a/board/BuS/eb_cpux9k2/Kconfig b/board/BuS/eb_cpux9k2/Kconfig
index 85d335a0e5b..230e64d8fc8 100644
--- a/board/BuS/eb_cpux9k2/Kconfig
+++ b/board/BuS/eb_cpux9k2/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_EB_CPUX9K2
 
-config SYS_CPU
-	default "arm920t"
-
 config SYS_BOARD
 	default "eb_cpux9k2"
 
diff --git a/board/BuS/vl_ma2sc/Kconfig b/board/BuS/vl_ma2sc/Kconfig
index bb6a7e787d4..2f43519089b 100644
--- a/board/BuS/vl_ma2sc/Kconfig
+++ b/board/BuS/vl_ma2sc/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_VL_MA2SC
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "vl_ma2sc"
 
diff --git a/board/CarMediaLab/flea3/Kconfig b/board/CarMediaLab/flea3/Kconfig
index 1448703dc10..7113f2b51f6 100644
--- a/board/CarMediaLab/flea3/Kconfig
+++ b/board/CarMediaLab/flea3/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_FLEA3
 
-config SYS_CPU
-	default "arm1136"
-
 config SYS_BOARD
 	default "flea3"
 
diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c
index 4c3a9ba785a..263bb5426c0 100644
--- a/board/LaCie/net2big_v2/net2big_v2.c
+++ b/board/LaCie/net2big_v2/net2big_v2.c
@@ -13,7 +13,7 @@
 #include <command.h>
 #include <i2c.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include <asm/arch/gpio.h>
 
@@ -26,8 +26,8 @@ DECLARE_GLOBAL_DATA_PTR;
 int board_early_init_f(void)
 {
 	/* GPIO configuration */
-	kw_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
-			NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
+	mvebu_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
+			  NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
 	static const u32 kwmpp_config[] = {
@@ -77,7 +77,7 @@ int board_init(void)
 	gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2;
 
 	/* Boot parameters address */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c
index 3773587cc6d..17e629622ff 100644
--- a/board/LaCie/netspace_v2/netspace_v2.c
+++ b/board/LaCie/netspace_v2/netspace_v2.c
@@ -12,7 +12,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include <asm/arch/gpio.h>
 
@@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR;
 int board_early_init_f(void)
 {
 	/* Gpio configuration */
-	kw_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
-			NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
+	mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
+			  NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
 	static const u32 kwmpp_config[] = {
@@ -73,7 +73,7 @@ int board_init(void)
 	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
 
 	/* Boot parameters address */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
diff --git a/board/LaCie/wireless_space/MAINTAINERS b/board/LaCie/wireless_space/MAINTAINERS
index 8a27b9a234a..c32ecb8b73c 100644
--- a/board/LaCie/wireless_space/MAINTAINERS
+++ b/board/LaCie/wireless_space/MAINTAINERS
@@ -1,5 +1,5 @@
 WIRELESS_SPACE BOARD
-#M:	-
+M:	Albert ARIBAUD <albert.u.boot@aribaud.net>
 S:	Maintained
 F:	board/LaCie/wireless_space/
 F:	include/configs/wireless_space.h
diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c
index 2dc50185604..8620e4b5d13 100644
--- a/board/LaCie/wireless_space/wireless_space.c
+++ b/board/LaCie/wireless_space/wireless_space.c
@@ -12,7 +12,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include <asm/arch/gpio.h>
 
@@ -97,8 +97,8 @@ struct mv88e61xx_config swcfg = {
 int board_early_init_f(void)
 {
 	/* Gpio configuration */
-	kw_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH,
-			WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH);
+	mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH,
+			  WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
 	kirkwood_mpp_conf(kwmpp_config, NULL);
@@ -112,7 +112,7 @@ int board_init(void)
 	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
 
 	/* Boot parameters address */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
diff --git a/board/Marvell/aspenite/Kconfig b/board/Marvell/aspenite/Kconfig
index ee2ec06f1eb..4dd49c4452b 100644
--- a/board/Marvell/aspenite/Kconfig
+++ b/board/Marvell/aspenite/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_ASPENITE
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "aspenite"
 
diff --git a/board/Marvell/common/flash.c b/board/Marvell/common/flash.c
deleted file mode 100644
index 32f226dcc33..00000000000
--- a/board/Marvell/common/flash.c
+++ /dev/null
@@ -1,1056 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * flash.c - flash support for the 512k, 8bit boot flash
-	and the 8MB 32bit extra flash on the DB64360
- *           most of this file was based on the existing U-Boot
- *           flash drivers.
- *
- * written or collected and sometimes rewritten by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include "../include/mv_gen_reg.h"
-#include "../include/memory.h"
-#include "intel_flash.h"
-
-#define FLASH_ROM       0xFFFD	/* unknown flash type                   */
-#define FLASH_RAM       0xFFFE	/* unknown flash type                   */
-#define FLASH_MAN_UNKNOWN 0xFFFF0000
-
-/* #define DEBUG */
-
-/* Intel flash commands */
-int flash_erase_intel (flash_info_t * info, int s_first, int s_last);
-int write_word_intel (bank_addr_t addr, bank_word_t value);
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (int portwidth, vu_long * addr,
-			     flash_info_t * info);
-static int write_word (flash_info_t * info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	unsigned int i;
-	unsigned long size_b0 = 0, size_b1 = 0;
-	unsigned long base, flash_size;
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* the boot flash */
-	base = CONFIG_SYS_FLASH_BASE;
-	size_b0 =
-		flash_get_size (CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *) base,
-				&flash_info[0]);
-
-	printf ("[%ldkB@%lx] ", size_b0 / 1024, base);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b0, size_b0 << 20);
-	}
-
-	base = memoryGetDeviceBaseAddress (CONFIG_SYS_EXTRA_FLASH_DEVICE);
-/*	base = memoryGetDeviceBaseAddress(DEV_CS3_BASE_ADDR);*/
-	for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		unsigned long size =
-			flash_get_size (CONFIG_SYS_EXTRA_FLASH_WIDTH,
-					(vu_long *) base, &flash_info[i]);
-
-		printf ("[%ldMB@%lx] ", size >> 20, base);
-
-		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-			if (i == 1) {
-				printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b1, size_b1 << 20);
-			}
-			break;
-		}
-		size_b1 += size;
-		base += size;
-	}
-
-	flash_size = size_b0 + size_b1;
-	return flash_size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-	int i;
-	int sector_size;
-
-	if (!info->sector_count)
-		return;
-
-	/* set up sector start address table */
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM040:
-	case FLASH_28F128J3A:
-	case FLASH_28F640J3A:
-	case FLASH_RAM:
-		/* this chip has uniformly spaced sectors */
-		sector_size = info->size / info->sector_count;
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * sector_size);
-		break;
-	default:
-		if (info->flash_id & FLASH_BTYPE) {
-			/* set sector offsets for bottom boot block type    */
-			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00008000;
-			info->start[2] = base + 0x0000C000;
-			info->start[3] = base + 0x00010000;
-			for (i = 4; i < info->sector_count; i++) {
-				info->start[i] =
-					base + (i * 0x00020000) - 0x00060000;
-			}
-		} else {
-			/* set sector offsets for top boot block type               */
-			i = info->sector_count - 1;
-			info->start[i--] = base + info->size - 0x00008000;
-			info->start[i--] = base + info->size - 0x0000C000;
-			info->start[i--] = base + info->size - 0x00010000;
-			for (; i >= 0; i--) {
-				info->start[i] = base + i * 0x00020000;
-			}
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_STM:
-		printf ("STM ");
-		break;
-	case FLASH_MAN_AMD:
-		printf ("AMD ");
-		break;
-	case FLASH_MAN_FUJ:
-		printf ("FUJITSU ");
-		break;
-	case FLASH_MAN_INTEL:
-		printf ("INTEL ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM040:
-		printf ("AM29LV040B (4 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM400B:
-		printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM400T:
-		printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-		break;
-	case FLASH_AM800B:
-		printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM800T:
-		printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-		break;
-	case FLASH_AM160B:
-		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM160T:
-		printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-		break;
-	case FLASH_AM320B:
-		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM320T:
-		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-		break;
-	case FLASH_28F640J3A:
-		printf ("28F640J3A (64 Mbit)\n");
-		break;
-	case FLASH_28F128J3A:
-		printf ("28F128J3A (128 Mbit)\n");
-		break;
-	case FLASH_ROM:
-		printf ("ROM\n");
-		break;
-	case FLASH_RAM:
-		printf ("RAM\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	if ((info->size >> 20) > 0) {
-		printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-	} else {
-		printf ("  Size: %ld kB in %d Sectors\n",
-			info->size >> 10, info->sector_count);
-	}
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i], info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-	return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static inline void flash_cmd (int width, volatile unsigned char *addr,
-			      int offset, unsigned char cmd)
-{
-	/* supports 1x8, 1x16, and 2x16 */
-	/* 2x8 and 4x8 are not supported */
-	if (width == 4) {
-		/* assuming chips are in 16 bit mode */
-		/* 2x16 */
-		unsigned long cmd32 = (cmd << 16) | cmd;
-
-		*(volatile unsigned long *) (addr + offset * 2) = cmd32;
-	} else {
-		/* 1x16 or 1x8 */
-		*(volatile unsigned char *) (addr + offset) = cmd;
-	}
-}
-
-static ulong
-flash_get_size (int portwidth, vu_long * addr, flash_info_t * info)
-{
-	short i;
-	volatile unsigned char *caddr = (unsigned char *) addr;
-	volatile unsigned short *saddr = (unsigned short *) addr;
-	volatile unsigned long *laddr = (unsigned long *) addr;
-	char old[2], save;
-	ulong id = 0, manu = 0, base = (ulong) addr;
-
-#ifdef DEBUG
-	printf ("%s: enter\n", __FUNCTION__);
-#endif
-	info->portwidth = portwidth;
-
-	save = *caddr;
-
-	flash_cmd (portwidth, caddr, 0, 0xf0);
-	flash_cmd (portwidth, caddr, 0, 0xf0);
-
-	udelay (10);
-
-	old[0] = caddr[0];
-	old[1] = caddr[1];
-
-
-	if (old[0] != 0xf0) {
-		flash_cmd (portwidth, caddr, 0, 0xf0);
-		flash_cmd (portwidth, caddr, 0, 0xf0);
-
-		udelay (10);
-
-		if (*caddr == 0xf0) {
-			/* this area is ROM */
-			*caddr = save;
-			info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
-			info->sector_count = 8;
-			info->size = 0x80000;
-			flash_get_offsets (base, info);
-			return info->size;
-		}
-	} else {
-		*caddr = 0;
-
-		udelay (10);
-
-		if (*caddr == 0) {
-			/* this area is RAM */
-			*caddr = save;
-			info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN;
-			info->sector_count = 8;
-			info->size = 0x80000;
-			flash_get_offsets (base, info);
-			return info->size;
-		}
-		flash_cmd (portwidth, caddr, 0, 0xf0);
-
-		udelay (10);
-	}
-
-	/* Write auto select command: read Manufacturer ID */
-	flash_cmd (portwidth, caddr, 0x555, 0xAA);
-	flash_cmd (portwidth, caddr, 0x2AA, 0x55);
-	flash_cmd (portwidth, caddr, 0x555, 0x90);
-
-	udelay (10);
-
-	if ((caddr[0] == old[0]) && (caddr[1] == old[1])) {
-
-		/* this area is ROM */
-		info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
-		info->sector_count = 8;
-		info->size = 0x80000;
-		flash_get_offsets (base, info);
-		return info->size;
-#ifdef DEBUG
-	} else {
-		printf ("%px%d: %02x:%02x -> %02x:%02x\n",
-			caddr, portwidth, old[0], old[1], caddr[0], caddr[1]);
-#endif
-	}
-
-	switch (portwidth) {
-	case 1:
-		manu = caddr[0];
-		manu |= manu << 16;
-		id = caddr[1];
-		break;
-	case 2:
-		manu = saddr[0];
-		manu |= manu << 16;
-		id = saddr[1];
-		id |= id << 16;
-		break;
-	case 4:
-		manu = laddr[0];
-		id = laddr[1];
-		break;
-	}
-
-#ifdef DEBUG
-	flash_cmd (portwidth, caddr, 0, 0xf0);
-
-	printf ("\n%08lx:%08lx:%08lx\n", base, manu, id);
-	printf ("%08lx %08lx %08lx %08lx\n",
-		laddr[0], laddr[1], laddr[2], laddr[3]);
-#endif
-
-	switch (manu) {
-	case STM_MANUFACT:
-		info->flash_id = FLASH_MAN_STM;
-		break;
-	case AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	case INTEL_MANUFACT:
-		info->flash_id = FLASH_MAN_INTEL;
-		break;
-	default:
-		flash_cmd (portwidth, caddr, 0, 0xf0);
-
-		printf ("Unknown Mfr [%08lx]:%08lx\n", manu, id);
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);	/* no or unknown flash  */
-	}
-
-	switch (id) {
-	case AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		info->chipwidth = 1;
-		break;		/* => 1 MB      */
-
-	case AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		info->chipwidth = 1;
-		break;		/* => 1 MB      */
-
-	case AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		info->chipwidth = 1;
-		break;		/* => 2 MB      */
-
-	case AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		info->chipwidth = 1;
-		break;		/* => 2 MB      */
-
-	case AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		info->chipwidth = 1;
-		break;		/* => 4 MB      */
-
-	case AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		info->chipwidth = 1;
-		break;		/* => 4 MB      */
-#if 0				/* enable when device IDs are available */
-	case AMD_ID_LV320T:
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;		/* => 8 MB      */
-
-	case AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;		/* => 8 MB      */
-#endif
-	case AMD_ID_LV040B:
-		info->flash_id += FLASH_AM040;
-		info->sector_count = 8;
-		info->size = 0x80000;
-		info->chipwidth = 1;
-		break;		/* => 512 kB    */
-
-	case INTEL_ID_28F640J3A:
-		info->flash_id += FLASH_28F640J3A;
-		info->sector_count = 64;
-		info->size = 128 * 1024 * 64;	/* 128kbytes x 64 blocks */
-		info->chipwidth = 2;
-		if (portwidth == 4)
-			info->size *= 2;	/* 2x16 */
-		break;
-
-	case INTEL_ID_28F128J3A:
-		info->flash_id += FLASH_28F128J3A;
-		info->sector_count = 128;
-		info->size = 128 * 1024 * 128;	/* 128kbytes x 128 blocks */
-		info->chipwidth = 2;
-		if (portwidth == 4)
-			info->size *= 2;	/* 2x16 */
-		break;
-
-	default:
-		flash_cmd (portwidth, caddr, 0, 0xf0);
-
-		printf ("Unknown id %lx:[%lx]\n", manu, id);
-		info->flash_id = FLASH_UNKNOWN;
-		info->chipwidth = 1;
-		return (0);	/* => no or unknown flash */
-
-	}
-
-	flash_get_offsets (base, info);
-
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0)=0x02 */
-		/* D0 = 1 if protected */
-		caddr = (volatile unsigned char *) (info->start[i]);
-		saddr = (volatile unsigned short *) (info->start[i]);
-		laddr = (volatile unsigned long *) (info->start[i]);
-		if (portwidth == 1)
-			info->protect[i] = caddr[2] & 1;
-		else if (portwidth == 2)
-			info->protect[i] = saddr[2] & 1;
-		else
-			info->protect[i] = laddr[2] & 1;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		caddr = (volatile unsigned char *) info->start[0];
-
-		flash_cmd (portwidth, caddr, 0, 0xF0);	/* reset bank */
-	}
-
-	return (info->size);
-}
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	volatile unsigned char *addr = (uchar *) (info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-/* modified to support 2x16 Intel flash */
-/* Note that the code will not exit on a flash erasure error or timeout */
-/* but will print and error message and continue processing sectors */
-/* until they are all erased. */
-/* 10-16-2002 P. Marchese */
-	ulong mask;
-	int timeout;
-
-	if (info->portwidth == 4)
-/*		{
-		printf ("- Warning: erasing of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n");
-		return 1;
-		}*/
-	{
-		/* make sure it's Intel flash */
-		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-			/* yup! it's an Intel flash */
-			/* is it 16-bits wide? */
-			if (info->chipwidth == 2) {
-				/* yup! it's 16-bits wide */
-				/* are there any sectors to process? */
-				if ((s_first < 0) || (s_first > s_last)) {
-					printf ("Error:  There are no sectors to erase\n");
-					printf ("Either sector %d is less than zero\n", s_first);
-					printf ("or sector %d is greater than sector %d\n", s_first, s_last);
-					return 1;
-				}
-				/* check for protected sectors */
-				prot = 0;
-				for (sect = s_first; sect <= s_last; ++sect)
-					if (info->protect[sect])
-						prot++;
-				/* if variable "prot" is nonzero, there are protected sectors */
-				if (prot)
-					printf ("- Warning: %d protected sectors will not be erased!\n", prot);
-				/* reset the flash */
-				flash_cmd (info->portwidth, addr, 0,
-					   CHIP_CMD_RST);
-				/* Disable interrupts which might cause a timeout here */
-				flag = disable_interrupts ();
-				/* Clear the status register */
-				flash_cmd (info->portwidth, addr, 0,
-					   CHIP_CMD_CLR_STAT);
-				flash_cmd (info->portwidth, addr, 0,
-					   CHIP_CMD_RST);
-				/* Start erase on unprotected sectors */
-				for (sect = s_first; sect <= s_last; sect++) {
-					/* is the sector unprotected? */
-					if (info->protect[sect] == 0) {	/* not protected */
-						/* issue the single block erase command, 0x20 */
-						flash_cmd (info->portwidth,
-							   (volatile unsigned
-							    char *) info->
-							   start[sect], 0,
-							   CHIP_CMD_ERASE1);
-						/* issue the erase confirm command, 0xD0 */
-						flash_cmd (info->portwidth,
-							   (volatile unsigned
-							    char *) info->
-							   start[sect], 0,
-							   CHIP_CMD_ERASE2);
-						l_sect = sect;
-						/* re-enable interrupts if necessary */
-						if (flag)
-							enable_interrupts ();
-						/* poll for erasure completion */
-						/* put flash into read status mode by writing 0x70 to it */
-						flash_cmd (info->portwidth,
-							   addr, 0,
-							   CHIP_CMD_RD_STAT);
-						/* setup the status register mask */
-						mask = CHIP_STAT_RDY |
-							(CHIP_STAT_RDY << 16);
-						/* init. the timeout counter */
-						start = get_timer (0);
-						/* keep looping while the flash is not ready */
-						/* exit the loop by timing out or the flash */
-						/* becomes ready again */
-						timeout = 0;
-						while ((*
-							(volatile unsigned
-							 long *) info->
-							start[sect] & mask) !=
-						       mask) {
-							/* has the timeout limit been reached? */
-							if (get_timer (start)
-							    >
-							    CONFIG_SYS_FLASH_ERASE_TOUT)
-							{
-								/* timeout limit reached */
-								printf ("Time out limit reached erasing sector at address %08lx\n", info->start[sect]);
-								printf ("Continuing with next sector\n");
-								timeout = 1;
-								goto timed_out_error;
-							}
-							/* put flash into read status mode by writing 0x70 to it */
-							flash_cmd (info->
-								   portwidth,
-								   addr, 0,
-								   CHIP_CMD_RD_STAT);
-						}
-						/* did we timeout? */
-					      timed_out_error:if (timeout == 0)
-						{
-							/* didn't timeout, so check the status register */
-							/* create the status mask to check for errors */
-							mask = CHIP_STAT_ECLBS;
-							mask = mask | (mask <<
-								       16);
-							/* put flash into read status mode by writing 0x70 to it */
-							flash_cmd (info->
-								   portwidth,
-								   addr, 0,
-								   CHIP_CMD_RD_STAT);
-							/* are there any errors? */
-							if ((*
-							     (volatile
-							      unsigned long *)
-							     info->
-							     start[sect] &
-							     mask) != 0) {
-								/* We got an erasure error */
-								printf ("Flash erasure error at address 0x%08lx\n", info->start[sect]);
-								printf ("Continuing with next sector\n");
-								/* reset the flash */
-								flash_cmd
-									(info->
-									 portwidth,
-									 addr,
-									 0,
-									 CHIP_CMD_RST);
-							}
-						}
-						/* erasure completed without errors */
-						/* reset the flash */
-						flash_cmd (info->portwidth,
-							   addr, 0,
-							   CHIP_CMD_RST);
-					}	/* end if not protected */
-				}	/* end for loop */
-				printf ("Flash erasure done\n");
-				return 0;
-			} else {
-				/* The Intel flash is not 16-bit wide */
-				/* print and error message and return */
-				/* NOTE: you can add routines here to handle other size flash */
-				printf ("Error: Intel flash device is only %d-bits wide\n", info->chipwidth * 8);
-				printf ("The erasure code only handles Intel 16-bit wide flash memory\n");
-				return 1;
-			}
-		} else {
-			/* Not Intel flash so return an error as a write timeout */
-			/* NOTE: if it's another type flash, stick its routine here */
-			printf ("Error: The flash device is not Intel type\n");
-			printf ("The erasure code only supports Intel flash in a 32-bit port width\n");
-			return 1;
-		}
-	}
-
-	/* end 32-bit wide flash code */
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM)
-		return 1;	/* Rom can not be erased */
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {	/* RAM just copy 0s to RAM */
-		for (sect = s_first; sect <= s_last; sect++) {
-			int sector_size = info->size / info->sector_count;
-
-			addr = (uchar *) (info->start[sect]);
-			memset ((void *) addr, 0, sector_size);
-		}
-		return 0;
-	}
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {	/* Intel works spezial */
-		return flash_erase_intel (info,
-					  (unsigned short) s_first,
-					  (unsigned short) s_last);
-	}
-#if 0
-	if ((info->flash_id == FLASH_UNKNOWN) ||	/* Flash is unknown to PPCBoot */
-	    (info->flash_id > FLASH_AMD_COMP)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-#endif
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	flash_cmd (info->portwidth, addr, 0x555, 0xAA);	/* start erase routine */
-	flash_cmd (info->portwidth, addr, 0x2AA, 0x55);
-	flash_cmd (info->portwidth, addr, 0x555, 0x80);
-	flash_cmd (info->portwidth, addr, 0x555, 0xAA);
-	flash_cmd (info->portwidth, addr, 0x2AA, 0x55);
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (uchar *) (info->start[sect]);
-			flash_cmd (info->portwidth, addr, 0, 0x30);
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last = start;
-	addr = (volatile unsigned char *) (info->start[l_sect]);
-	/* broken for 2x16: TODO */
-	while ((addr[0] & 0x80) != 0x80) {
-		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-      DONE:
-	/* reset to read mode */
-	addr = (volatile unsigned char *) info->start[0];
-	flash_cmd (info->portwidth, addr, 0, 0xf0);
-	flash_cmd (info->portwidth, addr, 0, 0xf0);
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-/* broken for 2x16: TODO */
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-/* Commented out since the below code should work for 32-bit(2x 16 flash) */
-/* 10-16-2002 P. Marchese */
-/*	if(info->portwidth==4) return 1; */
-/*	if(info->portwidth==4) {
-		printf ("- Warning: writting of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n");
-		return 1;
-		}*/
-
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM)
-		return 0;
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
-		memcpy ((void *) addr, src, cnt);
-		return 0;
-	}
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-		for (; i < 4 && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < 4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-
-		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i = 0; i < 4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < 4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *) cp);
-	}
-
-	return (write_word (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-/* broken for 2x16: TODO */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
-	volatile unsigned char *addr = (uchar *) (info->start[0]);
-	ulong start;
-	int flag, i;
-	ulong mask;
-
-/* modified so that it handles 32-bit(2x16 Intel flash programming */
-/* 10-16-2002 P. Marchese */
-
-	if (info->portwidth == 4)
-/*		{
-		printf ("- Warning: writting of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n");
-		return 1;
-		}*/
-	{
-		/* make sure it's Intel flash */
-		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-			/* yup! it's an Intel flash */
-			/* is it 16-bits wide? */
-			if (info->chipwidth == 2) {
-				/* yup! it's 16-bits wide */
-				/* so we know how to program it */
-				/* reset the flash */
-				flash_cmd (info->portwidth, addr, 0,
-					   CHIP_CMD_RST);
-				/* Disable interrupts which might cause a timeout here */
-				flag = disable_interrupts ();
-				/* Clear the status register */
-				flash_cmd (info->portwidth, addr, 0,
-					   CHIP_CMD_CLR_STAT);
-				flash_cmd (info->portwidth, addr, 0,
-					   CHIP_CMD_RST);
-				/* 1st cycle of word/byte program */
-				/* write 0x40 to the location to program */
-				flash_cmd (info->portwidth, (uchar *) dest, 0,
-					   CHIP_CMD_PROG);
-				/* 2nd cycle of word/byte program */
-				/* write the data to the destination address */
-				*(ulong *) dest = data;
-				/* re-enable interrupts if necessary */
-				if (flag)
-					enable_interrupts ();
-				/* setup the status register mask */
-				mask = CHIP_STAT_RDY | (CHIP_STAT_RDY << 16);
-				/* put flash into read status mode by writing 0x70 to it */
-				flash_cmd (info->portwidth, addr, 0,
-					   CHIP_CMD_RD_STAT);
-				/* init. the timeout counter */
-				start = get_timer (0);
-				/* keep looping while the flash is not ready */
-				/* exit the loop by timing out or the flash */
-				/* becomes ready again */
-/* 11-13-2002 Paul Marchese */
-/* modified while loop conditional statement */
-/* because we were always timing out.  */
-/* there is a type mismatch, "addr[0]" */
-/* returns a byte but "mask" is a 32-bit value */
-				while ((*(volatile unsigned long *) info->
-					start[0] & mask) != mask)
-/* original code */
-/* while (addr[0] & mask) != mask) */
-				{
-					/* has the timeout limit been reached? */
-					if (get_timer (start) >
-					    CONFIG_SYS_FLASH_WRITE_TOUT) {
-						/* timeout limit reached */
-						printf ("Time out limit reached programming address %08lx with data %08lx\n", dest, data);
-						/* reset the flash */
-						flash_cmd (info->portwidth,
-							   addr, 0,
-							   CHIP_CMD_RST);
-						return (1);
-					}
-					/* put flash into read status mode by writing 0x70 to it */
-					flash_cmd (info->portwidth, addr, 0,
-						   CHIP_CMD_RD_STAT);
-				}
-				/* flash is ready, so check the status */
-				/* create the status mask to check for errors */
-				mask = CHIP_STAT_DPS | CHIP_STAT_VPPS |
-					CHIP_STAT_PSLBS;
-				mask = mask | (mask << 16);
-				/* put flash into read status mode by writing 0x70 to it */
-				flash_cmd (info->portwidth, addr, 0,
-					   CHIP_CMD_RD_STAT);
-				/* are there any errors? */
-				if ((addr[0] & mask) != 0) {
-					/* We got a one of the following errors: */
-					/* Voltage range, Device protect, or programming */
-					/* return the error as a device timeout */
-					/* put flash into read status mode by writing 0x70 to it */
-					flash_cmd (info->portwidth, addr, 0,
-						   CHIP_CMD_RD_STAT);
-					printf ("Flash programming error at address 0x%08lx\n", dest);
-					printf ("Flash status register contains 0x%08lx\n", (unsigned long) addr[0]);
-					/* reset the flash */
-					flash_cmd (info->portwidth, addr, 0,
-						   CHIP_CMD_RST);
-					return 1;
-				}
-				/* write completed without errors */
-				/* reset the flash */
-				flash_cmd (info->portwidth, addr, 0,
-					   CHIP_CMD_RST);
-				return 0;
-			} else {
-				/* it's not 16-bits wide, so return an error as a write timeout */
-				/* NOTE: you can add routines here to handle other size flash */
-				printf ("Error: Intel flash device is only %d-bits wide\n", info->chipwidth * 8);
-				printf ("The write code only handles Intel 16-bit wide flash memory\n");
-				return 1;
-			}
-		} else {
-			/* not Intel flash so return an error as a write timeout */
-			/* NOTE: if it's another type flash, stick its routine here */
-			printf ("Error: The flash device is not Intel type\n");
-			printf ("The code only supports Intel flash in a 32-bit port width\n");
-			return 1;
-		}
-	}
-
-	/* end of 32-bit flash code */
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM)
-		return 1;
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
-		*(unsigned long *) dest = data;
-		return 0;
-	}
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-		unsigned short low = data & 0xffff;
-		unsigned short hi = (data >> 16) & 0xffff;
-		int ret = write_word_intel ((bank_addr_t) dest, hi);
-
-		if (!ret)
-			ret = write_word_intel ((bank_addr_t) (dest + 2),
-						low);
-
-		return ret;
-	}
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *) dest) & data) != data) {
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	/* first, perform an unlock bypass command to speed up flash writes */
-	addr[0x555] = 0xAA;
-	addr[0x2AA] = 0x55;
-	addr[0x555] = 0x20;
-
-	/* write each byte out */
-	for (i = 0; i < 4; i++) {
-		char *data_ch = (char *) &data;
-
-		addr[0] = 0xA0;
-		*(((char *) dest) + i) = data_ch[i];
-		udelay (10);	/* XXX */
-	}
-
-	/* we're done, now do an unlock bypass reset */
-	addr[0] = 0x90;
-	addr[0] = 0x00;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			return (1);
-		}
-	}
-	return (0);
-}
diff --git a/board/Marvell/common/i2c.c b/board/Marvell/common/i2c.c
deleted file mode 100644
index abdde868a74..00000000000
--- a/board/Marvell/common/i2c.c
+++ /dev/null
@@ -1,521 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
- * extra improvments by Brain Waite
- */
-#include <common.h>
-#include <mpc8xx.h>
-#include <malloc.h>
-#include <i2c.h>
-#include "../include/mv_gen_reg.h"
-#include "../include/core.h"
-
-#define MAX_I2C_RETRYS	    10
-#define I2C_DELAY	    1000	/* Should be at least the # of MHz of Tclk */
-#undef	DEBUG_I2C
-/*#define DEBUG_I2C*/
-
-#ifdef DEBUG_I2C
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-/* Assuming that there is only one master on the bus (us) */
-
-void i2c_init (int speed, int slaveaddr)
-{
-	unsigned int n, m, freq, margin, power;
-	unsigned int actualN = 0, actualM = 0;
-	unsigned int control, status;
-	unsigned int minMargin = 0xffffffff;
-	unsigned int tclk = CONFIG_SYS_TCLK;
-	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
-
-	DP (puts ("i2c_init\n"));
-/* gtI2cMasterInit */
-	for (n = 0; n < 8; n++) {
-		for (m = 0; m < 16; m++) {
-			power = 2 << n;	/* power = 2^(n+1) */
-			freq = tclk / (10 * (m + 1) * power);
-			if (i2cFreq > freq)
-				margin = i2cFreq - freq;
-			else
-				margin = freq - i2cFreq;
-			if (margin < minMargin) {
-				minMargin = margin;
-				actualN = n;
-				actualM = m;
-			}
-		}
-	}
-
-	DP (puts ("setup i2c bus\n"));
-
-	/* Setup bus */
-/* gtI2cReset */
-	GT_REG_WRITE (I2C_SOFT_RESET, 0);
-
-	DP (puts ("udelay...\n"));
-
-	udelay (I2C_DELAY);
-
-	DP (puts ("set baudrate\n"));
-
-	GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
-	GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
-
-	udelay (I2C_DELAY * 10);
-
-	DP (puts ("read control, baudrate\n"));
-
-	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-	GT_REG_READ (I2C_CONTROL, &control);
-}
-
-static uchar i2c_start (void)
-{				/* DB64360 checked -> ok */
-	unsigned int control, status;
-	int count = 0;
-
-	DP (puts ("i2c_start\n"));
-
-	/* Set the start bit */
-
-/* gtI2cGenerateStartBit() */
-
-	GT_REG_READ (I2C_CONTROL, &control);
-	control |= (0x1 << 5);	/* generate the I2C_START_BIT */
-	GT_REG_WRITE (I2C_CONTROL, control);
-
-	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-
-	count = 0;
-	while ((status & 0xff) != 0x08) {
-		udelay (I2C_DELAY);
-		if (count > 20) {
-			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-			return (status);
-		}
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-	}
-
-	return (0);
-}
-
-static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
-{
-	unsigned int status, data, bits = 7;
-	int count = 0;
-
-	DP (puts ("i2c_select_device\n"));
-
-	/* Output slave address */
-
-	if (ten_bit) {
-		bits = 10;
-	}
-
-	data = (dev_addr << 1);
-	/* set the read bit */
-	data |= read;
-	GT_REG_WRITE (I2C_DATA, data);
-	/* assert the address */
-	RESET_REG_BITS (I2C_CONTROL, BIT3);
-
-	udelay (I2C_DELAY);
-
-	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-	count = 0;
-	while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
-		udelay (I2C_DELAY);
-		if (count > 20) {
-			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-			return (status);
-		}
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-	}
-
-	if (bits == 10) {
-		printf ("10 bit I2C addressing not yet implemented\n");
-		return (0xff);
-	}
-
-	return (0);
-}
-
-static uchar i2c_get_data (uchar * return_data, int len)
-{
-
-	unsigned int data, status = 0;
-	int count = 0;
-
-	DP (puts ("i2c_get_data\n"));
-
-	while (len) {
-
-		/* Get and return the data */
-
-		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
-
-		udelay (I2C_DELAY * 5);
-
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-		while ((status & 0xff) != 0x50) {
-			udelay (I2C_DELAY);
-			if (count > 2) {
-				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-				return 0;
-			}
-			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-			count++;
-		}
-		GT_REG_READ (I2C_DATA, &data);
-		len--;
-		*return_data = (uchar) data;
-		return_data++;
-	}
-	RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
-	while ((status & 0xff) != 0x58) {
-		udelay (I2C_DELAY);
-		if (count > 200) {
-			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-			return (status);
-		}
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-	}
-	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/* stop */
-
-	return (0);
-}
-
-static uchar i2c_write_data (unsigned int *data, int len)
-{
-	unsigned int status;
-	int count = 0;
-	unsigned int temp;
-	unsigned int *temp_ptr = data;
-
-	DP (puts ("i2c_write_data\n"));
-
-	while (len) {
-		temp = (unsigned int) (*temp_ptr);
-		GT_REG_WRITE (I2C_DATA, temp);
-		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
-
-		udelay (I2C_DELAY);
-
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-		while ((status & 0xff) != 0x28) {
-			udelay (I2C_DELAY);
-			if (count > 20) {
-				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-				return (status);
-			}
-			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-			count++;
-		}
-		len--;
-		temp_ptr++;
-	}
-/* 11-14-2002 Paul Marchese */
-/* Can't have the write issuing a stop command */
-/* it's wrong to have a stop bit in read stream or write stream */
-/* since we don't know if it's really the end of the command */
-/* or whether we have just send the device address + offset */
-/* we will push issuing the stop command off to the original */
-/* calling function */
-	/* set the interrupt bit in the control register */
-	GT_REG_WRITE (I2C_CONTROL, (0x1 << 3));
-	udelay (I2C_DELAY * 10);
-	return (0);
-}
-
-/* 11-14-2002 Paul Marchese */
-/* created this function to get the i2c_write() */
-/* function working properly. */
-/* function to write bytes out on the i2c bus */
-/* this is identical to the function i2c_write_data() */
-/* except that it requires a buffer that is an */
-/* unsigned character array.  You can't use */
-/* i2c_write_data() to send an array of unsigned characters */
-/* since the byte of interest ends up on the wrong end of the bus */
-/* aah, the joys of big endian versus little endian! */
-/* */
-/* returns 0 = success */
-/*         anything other than zero is failure */
-static uchar i2c_write_byte (unsigned char *data, int len)
-{
-	unsigned int status;
-	int count = 0;
-	unsigned int temp;
-	unsigned char *temp_ptr = data;
-
-	DP (puts ("i2c_write_byte\n"));
-
-	while (len) {
-		/* Set and assert the data */
-		temp = *temp_ptr;
-		GT_REG_WRITE (I2C_DATA, temp);
-		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
-
-		udelay (I2C_DELAY);
-
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-		while ((status & 0xff) != 0x28) {
-			udelay (I2C_DELAY);
-			if (count > 20) {
-				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-				return (status);
-			}
-			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-			count++;
-		}
-		len--;
-		temp_ptr++;
-	}
-/* Can't have the write issuing a stop command */
-/* it's wrong to have a stop bit in read stream or write stream */
-/* since we don't know if it's really the end of the command */
-/* or whether we have just send the device address + offset */
-/* we will push issuing the stop command off to the original */
-/* calling function */
-/*	GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4));
-	GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); */
-	/* set the interrupt bit in the control register */
-	GT_REG_WRITE (I2C_CONTROL, (0x1 << 3));
-	udelay (I2C_DELAY * 10);
-
-	return (0);
-}
-
-static uchar
-i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
-		    int alen)
-{
-	uchar status;
-	unsigned int table[2];
-
-/* initialize the table of address offset bytes */
-/* utilized for 2 byte address offsets */
-/* NOTE: the order is high byte first! */
-	table[1] = offset & 0xff;	/* low byte */
-	table[0] = offset / 0x100;	/* high byte */
-
-	DP (puts ("i2c_set_dev_offset\n"));
-
-	status = i2c_select_device (dev_addr, 0, ten_bit);
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Failed to select device setting offset: 0x%02x\n",
-			status);
-#endif
-		return status;
-	}
-/* check the address offset length */
-	if (alen == 0)
-		/* no address offset */
-		return (0);
-	else if (alen == 1) {
-		/* 1 byte address offset */
-		status = i2c_write_data (&offset, 1);
-		if (status) {
-#ifdef DEBUG_I2C
-			printf ("Failed to write data: 0x%02x\n", status);
-#endif
-			return status;
-		}
-	} else if (alen == 2) {
-		/* 2 bytes address offset */
-		status = i2c_write_data (table, 2);
-		if (status) {
-#ifdef DEBUG_I2C
-			printf ("Failed to write data: 0x%02x\n", status);
-#endif
-			return status;
-		}
-	} else {
-		/* address offset unknown or not supported */
-		printf ("Address length offset %d is not supported\n", alen);
-		return 1;
-	}
-	return 0;		/* sucessful completion */
-}
-
-int
-i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
-	  int len)
-{
-	uchar status = 0;
-	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
-
-	DP (puts ("i2c_read\n"));
-
-	/* set the i2c frequency */
-	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
-
-	status = i2c_start ();
-
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Transaction start failed: 0x%02x\n", status);
-#endif
-		return status;
-	}
-
-	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Failed to set slave address & offset: 0x%02x\n",
-			status);
-#endif
-		return status;
-	}
-
-	/* set the i2c frequency again */
-	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
-
-	status = i2c_start ();
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Transaction restart failed: 0x%02x\n", status);
-#endif
-		return status;
-	}
-
-	status = i2c_select_device (dev_addr, 1, 0);	/* send the slave address */
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Address not acknowledged: 0x%02x\n", status);
-#endif
-		return status;
-	}
-
-	status = i2c_get_data (data, len);
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Data not received: 0x%02x\n", status);
-#endif
-		return status;
-	}
-
-	return 0;
-}
-
-/* 11-14-2002 Paul Marchese */
-/* Function to set the I2C stop bit */
-void i2c_stop (void)
-{
-	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
-}
-
-/* 11-14-2002 Paul Marchese */
-/* I2C write function */
-/* dev_addr = device address */
-/* offset = address offset */
-/* alen = length in bytes of the address offset */
-/* data = pointer to buffer to read data into */
-/* len = # of bytes to read */
-/* */
-/* returns 0 = succesful */
-/*         anything but zero is failure */
-int
-i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
-	   int len)
-{
-	uchar status = 0;
-	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
-
-	DP (puts ("i2c_write\n"));
-
-	/* set the i2c frequency */
-	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
-
-	status = i2c_start ();	/* send a start bit */
-
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Transaction start failed: 0x%02x\n", status);
-#endif
-		return status;
-	}
-
-	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Failed to set slave address & offset: 0x%02x\n",
-			status);
-#endif
-		return status;
-	}
-
-
-	status = i2c_write_byte (data, len);	/* write the data */
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Data not written: 0x%02x\n", status);
-#endif
-		return status;
-	}
-	/* issue a stop bit */
-	i2c_stop ();
-	return 0;
-}
-
-/* 11-14-2002 Paul Marchese */
-/* function to determine if an I2C device is present */
-/* chip = device address of chip to check for */
-/* */
-/* returns 0 = sucessful, the device exists */
-/*         anything other than zero is failure, no device */
-int i2c_probe (uchar chip)
-{
-
-	/* We are just looking for an <ACK> back. */
-	/* To see if the device/chip is there */
-
-#ifdef DEBUG_I2C
-	unsigned int i2c_status;
-#endif
-	uchar status = 0;
-	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
-
-	DP (puts ("i2c_probe\n"));
-
-	/* set the i2c frequency */
-	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
-
-	status = i2c_start ();	/* send a start bit */
-
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Transaction start failed: 0x%02x\n", status);
-#endif
-		return (int) status;
-	}
-
-	status = i2c_set_dev_offset (chip, 0, 0, 0);	/* send the slave address + no offset */
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Failed to set slave address: 0x%02x\n", status);
-#endif
-		return (int) status;
-	}
-#ifdef DEBUG_I2C
-	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
-	printf ("address %#x returned %#x\n", chip, i2c_status);
-#endif
-	/* issue a stop bit */
-	i2c_stop ();
-	return 0;		/* successful completion */
-}
diff --git a/board/Marvell/common/intel_flash.c b/board/Marvell/common/intel_flash.c
deleted file mode 100644
index d6970d4e952..00000000000
--- a/board/Marvell/common/intel_flash.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Hacked for the marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include "../include/mv_gen_reg.h"
-#include "../include/memory.h"
-#include "intel_flash.h"
-
-
-/*-----------------------------------------------------------------------
- * Protection Flags:
- */
-#define FLAG_PROTECT_SET	0x01
-#define FLAG_PROTECT_CLEAR	0x02
-
-static void bank_reset (flash_info_t * info, int sect)
-{
-	bank_addr_t addrw, eaddrw;
-
-	addrw = (bank_addr_t) info->start[sect];
-	eaddrw = BANK_ADDR_NEXT_WORD (addrw);
-
-	while (addrw < eaddrw) {
-#ifdef FLASH_DEBUG
-		printf ("  writing reset cmd to addr 0x%08lx\n",
-			(unsigned long) addrw);
-#endif
-		*addrw = BANK_CMD_RST;
-		addrw++;
-	}
-}
-
-static void bank_erase_init (flash_info_t * info, int sect)
-{
-	bank_addr_t addrw, saddrw, eaddrw;
-	int flag;
-
-#ifdef FLASH_DEBUG
-	printf ("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG);
-	printf ("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1);
-	printf ("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2);
-	printf ("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT);
-	printf ("0x%08x BANK_CMD_RST\n", BANK_CMD_RST);
-	printf ("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY);
-	printf ("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR);
-#endif
-
-	saddrw = (bank_addr_t) info->start[sect];
-	eaddrw = BANK_ADDR_NEXT_WORD (saddrw);
-
-#ifdef FLASH_DEBUG
-	printf ("erasing sector %d, start addr = 0x%08lx "
-		"(bank next word addr = 0x%08lx)\n", sect,
-		(unsigned long) saddrw, (unsigned long) eaddrw);
-#endif
-
-	/* Disable intrs which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	for (addrw = saddrw; addrw < eaddrw; addrw++) {
-#ifdef FLASH_DEBUG
-		printf ("  writing erase cmd to addr 0x%08lx\n",
-			(unsigned long) addrw);
-#endif
-		*addrw = BANK_CMD_ERASE1;
-		*addrw = BANK_CMD_ERASE2;
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-}
-
-static int bank_erase_poll (flash_info_t * info, int sect)
-{
-	bank_addr_t addrw, saddrw, eaddrw;
-	int sectdone, haderr;
-
-	saddrw = (bank_addr_t) info->start[sect];
-	eaddrw = BANK_ADDR_NEXT_WORD (saddrw);
-
-	sectdone = 1;
-	haderr = 0;
-
-	for (addrw = saddrw; addrw < eaddrw; addrw++) {
-		bank_word_t stat = *addrw;
-
-#ifdef FLASH_DEBUG
-		printf ("  checking status at addr "
-			"0x%08x [0x%08x]\n", (unsigned long) addrw, stat);
-#endif
-		if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY)
-			sectdone = 0;
-		else if ((stat & BANK_STAT_ERR) != 0) {
-			printf (" failed on sector %d "
-				"(stat = 0x%08x) at "
-				"address 0x%p\n", sect, stat, addrw);
-			*addrw = BANK_CMD_CLR_STAT;
-			haderr = 1;
-		}
-	}
-
-	if (haderr)
-		return (-1);
-	else
-		return (sectdone);
-}
-
-int write_word_intel (bank_addr_t addr, bank_word_t value)
-{
-	bank_word_t stat;
-	ulong start;
-	int flag, retval;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	*addr = BANK_CMD_PROG;
-
-	*addr = value;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	retval = 0;
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	do {
-		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			retval = 1;
-			goto done;
-		}
-		stat = *addr;
-	} while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
-
-	if ((stat & BANK_STAT_ERR) != 0) {
-		printf ("flash program failed (stat = 0x%08lx) "
-			"at address 0x%08lx\n", (ulong) stat, (ulong) addr);
-		*addr = BANK_CMD_CLR_STAT;
-		retval = 3;
-	}
-
-      done:
-	/* reset to read mode */
-	*addr = BANK_CMD_RST;
-
-	return (retval);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase_intel (flash_info_t * info, int s_first, int s_last)
-{
-	int prot, sect, haderr;
-	ulong start, now, last;
-
-#ifdef FLASH_DEBUG
-	printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
-		"  Bank # %d: ", s_last - s_first + 1, s_first, s_last,
-		(info - flash_info) + 1);
-	flash_print_info (info);
-#endif
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sector%s will not be erased!\n", prot, (prot > 1 ? "s" : ""));
-	}
-
-	start = get_timer (0);
-	last = 0;
-	haderr = 0;
-
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			ulong estart;
-			int sectdone;
-
-			bank_erase_init (info, sect);
-
-			/* wait at least 80us - let's wait 1 ms */
-			udelay (1000);
-
-			estart = get_timer (start);
-
-			do {
-				now = get_timer (start);
-
-				if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
-					printf ("Timeout (sect %d)\n", sect);
-					haderr = 1;
-					break;
-				}
-#ifndef FLASH_DEBUG
-				/* show that we're waiting */
-				if ((now - last) > 1000) {	/* every second */
-					putc ('.');
-					last = now;
-				}
-#endif
-
-				sectdone = bank_erase_poll (info, sect);
-
-				if (sectdone < 0) {
-					haderr = 1;
-					break;
-				}
-
-			} while (!sectdone);
-
-			if (haderr)
-				break;
-		}
-	}
-
-	if (haderr > 0)
-		printf (" failed\n");
-	else
-		printf (" done\n");
-
-	/* reset to read mode */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			bank_reset (info, sect);
-		}
-	}
-	return haderr;
-}
diff --git a/board/Marvell/common/misc.S b/board/Marvell/common/misc.S
deleted file mode 100644
index b3a089803aa..00000000000
--- a/board/Marvell/common/misc.S
+++ /dev/null
@@ -1,235 +0,0 @@
-#include <config.h>
-#include <74xx_7xx.h>
-#include "version.h"
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#include "../include/mv_gen_reg.h"
-
-#ifdef CONFIG_ECC
-	/* Galileo specific asm code for initializing ECC */
-	.globl board_relocate_rom
-board_relocate_rom:
-	mflr	r7
-	/* update the location of the GT registers */
-	lis	r11, CONFIG_SYS_GT_REGS@h
-	/* if we're using ECC, we must use the DMA engine to copy ourselves */
-	bl	start_idma_transfer_0
-	bl	wait_for_idma_0
-	bl	stop_idma_engine_0
-
-	mtlr	r7
-	blr
-
-	.globl board_init_ecc
-board_init_ecc:
-	mflr	r7
-	/* NOTE: r10 still contains the location we've been relocated to
-	 * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
-
-	/* now that we're running from ram, init the rest of main memory
-	 * for ECC use */
-	lis	r8, CONFIG_SYS_MONITOR_LEN@h
-	ori	r8, r8, CONFIG_SYS_MONITOR_LEN@l
-
-	divw	r3, r10, r8
-
-	/* set up the counter, and init the starting address */
-	mtctr	r3
-	li	r12, 0
-
-	/* bytes per transfer */
-	mr	r5, r8
-about_to_init_ecc:
-1:	mr	r3, r12
-	mr	r4, r12
-	bl	start_idma_transfer_0
-	bl	wait_for_idma_0
-	bl	stop_idma_engine_0
-	add	r12, r12, r8
-	bdnz	1b
-
-	mtlr	r7
-	blr
-
-	/* r3:	dest addr
-	 * r4:	source addr
-	 * r5:	byte count
-	 * r11: gt regbase
-	 * trashes:	 r6, r5
-	 */
-start_idma_transfer_0:
-	/* set the byte count, including the OWN bit */
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0_DMA_BYTE_COUNT
-	stwbrx	r5, 0, (r6)
-
-	/* set the source address */
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
-	stwbrx	r4, 0, (r6)
-
-	/* set the dest address */
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
-	stwbrx	r3, 0, (r6)
-
-	/* set the next record pointer */
-	li	r5, 0
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0NEXT_RECORD_POINTER
-	stwbrx	r5, 0, (r6)
-
-	/* set the low control register */
-	/* bit 9 is NON chained mode, bit 31 is new style descriptors.
-	   bit 12 is channel enable */
-	ori	r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
-	/* 15 shifted by 16 (oris) == bit 31 */
-	oris	r5, r5, (1 << 15)
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0CONTROL
-	stwbrx	r5, 0, (r6)
-
-	blr
-
-	/* this waits for the bytecount to return to zero, indicating
-	 * that the trasfer is complete */
-wait_for_idma_0:
-	mr	r5, r11
-	lis	r6, 0xff
-	ori	r6, r6, 0xffff
-	ori	r5, r5, CHANNEL0_DMA_BYTE_COUNT
-1:	lwbrx	r4, 0, (r5)
-	and.	r4, r4, r6
-	bne	1b
-
-	blr
-
-	/* this turns off channel 0 of the idma engine */
-stop_idma_engine_0:
-	/* shut off the DMA engine */
-	li	r5, 0
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0CONTROL
-	stwbrx	r5, 0, (r6)
-
-	blr
-#endif
-
-#ifdef CONFIG_SYS_BOARD_ASM_INIT
-	/* NOTE: trashes r3-r7 */
-	.globl board_asm_init
-board_asm_init:
-	/* just move the GT registers to where they belong */
-	lis	r3, CONFIG_SYS_DFL_GT_REGS@h
-	ori	r3, r3, CONFIG_SYS_DFL_GT_REGS@l
-	lis	r4, CONFIG_SYS_GT_REGS@h
-	ori	r4, r4, CONFIG_SYS_GT_REGS@l
-	li	r5, INTERNAL_SPACE_DECODE
-
-	/* test to see if we've already moved */
-	lwbrx	r6, r5, r4
-	andi.	r6, r6, 0xffff
-	/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
-/*	rlwinm	r7, r4, 8, 16, 31
-	rlwinm	r7, r4, 12, 16, 31	*/ /* original */
-	rlwinm	r7, r4, 16, 16, 31
-	/* -----------------------------------------------------*/
-	cmp	cr0, r7, r6
-	beqlr
-
-	/* nope, have to move the registers */
-	lwbrx	r6, r5, r3
-	andis.	r6, r6, 0xffff
-	or	r6, r6, r7
-	stwbrx	r6, r5, r3
-
-	/* now, poll for the change */
-1:	lwbrx	r7, r5, r4
-	cmp	cr0, r7, r6
-	bne	1b
-
-	/* done! */
-	blr
-#endif
-
-/* For use of the debug LEDs */
-	.global led_on0_relocated
-led_on0_relocated:
-	xor	r21, r21, r21
-	xor	r18, r18, r18
-	lis	r18, 0xFC80
-	ori	r18, r18, 0x8000
-	stw	r21, 0x0(r18)
-/*	  stw	  r18, 0x0(r18) */
-	sync
-	blr
-
-	.global led_off0_relocated
-led_off0_relocated:
-	xor	r21, r21, r21
-	xor	r18, r18, r18
-	lis	r18, 0xFC81
-	ori	r18, r18, 0x4000
-	stw	r21, 0x0(r18)
-/*	  stw	  r18, 0x0(r18) */
-	sync
-	blr
-
-	.global led_on0
-led_on0:
-	xor	r18, r18, r18
-	lis	r18, 0x1c80
-	ori	r18, r18, 0x8000
-	stw	r18, 0x0(r18)
-	sync
-	blr
-
-	.global led_off0
-led_off0:
-	xor	r18, r18, r18
-	lis	r18, 0x1c81
-	ori	r18, r18, 0x4000
-	stw	r18, 0x0(r18)
-	sync
-	blr
-
-	.global led_on1
-led_on1:
-	xor	r18, r18, r18
-	lis	r18, 0x1c80
-	ori	r18, r18, 0xc000
-	stw	r18, 0x0(r18)
-	sync
-	blr
-
-	.global led_off1
-led_off1:
-	xor	r18, r18, r18
-	lis	r18, 0x1c81
-	ori	r18, r18, 0x8000
-	stw	r18, 0x0(r18)
-	sync
-	blr
-
-	.global led_on2
-led_on2:
-	xor	r18, r18, r18
-	lis	r18, 0x1c81
-	ori	r18, r18, 0x0000
-	stw	r18, 0x0(r18)
-	sync
-	blr
-
-	.global led_off2
-led_off2:
-	xor	r18, r18, r18
-	lis	r18, 0x1c81
-	ori	r18, r18, 0xc000
-	stw	r18, 0x0(r18)
-	sync
-	blr
diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c
index 752492fc7d1..432aa0660ef 100644
--- a/board/Marvell/common/serial.c
+++ b/board/Marvell/common/serial.c
@@ -21,14 +21,6 @@
 
 #include "../include/memory.h"
 
-#ifdef CONFIG_DB64360
-#include "../db64360/mpsc.h"
-#endif
-
-#ifdef CONFIG_DB64460
-#include "../db64460/mpsc.h"
-#endif
-
 #include "ns16550.h"
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/Marvell/db-mv784mp-gp/Kconfig b/board/Marvell/db-mv784mp-gp/Kconfig
new file mode 100644
index 00000000000..f94a444cf23
--- /dev/null
+++ b/board/Marvell/db-mv784mp-gp/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_DB_MV784MP_GP
+
+config SYS_CPU
+	string
+	default "armv7"
+
+config SYS_BOARD
+	string
+	default "db-mv784mp-gp"
+
+config SYS_VENDOR
+	string
+	default "Marvell"
+
+config SYS_SOC
+	string
+	default "armada-xp"
+
+config SYS_CONFIG_NAME
+	string
+	default "db-mv784mp-gp"
+
+endif
diff --git a/board/Marvell/db-mv784mp-gp/MAINTAINERS b/board/Marvell/db-mv784mp-gp/MAINTAINERS
new file mode 100644
index 00000000000..a095f898d40
--- /dev/null
+++ b/board/Marvell/db-mv784mp-gp/MAINTAINERS
@@ -0,0 +1,6 @@
+DB_MV784MP_GP BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/Marvell/db-mv784mp-gp/
+F:	include/configs/db-mv784mp-gp.h
+F:	configs/db-mv784mp-gp_defconfig
diff --git a/board/Marvell/db-mv784mp-gp/Makefile b/board/Marvell/db-mv784mp-gp/Makefile
new file mode 100644
index 00000000000..8f5a7fb6cba
--- /dev/null
+++ b/board/Marvell/db-mv784mp-gp/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= db-mv784mp-gp.o
diff --git a/board/Marvell/db-mv784mp-gp/binary.0 b/board/Marvell/db-mv784mp-gp/binary.0
new file mode 100644
index 00000000000..17bfad99dc9
--- /dev/null
+++ b/board/Marvell/db-mv784mp-gp/binary.0
@@ -0,0 +1,17 @@
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
+
+In a few weeks, mainline U-Boot will get support to generate the
+bin_hdr with the DDR training code itself. By implementing this code
+as SPL U-Boot. Then this file will not be needed any more and will
+get removed.
+
diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
new file mode 100644
index 00000000000..b3dae8910d4
--- /dev/null
+++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BIT(nr)				(1UL << (nr))
+
+#define ETH_PHY_CTRL_REG		0
+#define ETH_PHY_CTRL_POWER_DOWN_BIT	11
+#define ETH_PHY_CTRL_POWER_DOWN_MASK	(1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka
+ * "RD-AXP-GP rev 1.0".
+ *
+ * GPPs
+ * MPP#		NAME			IN/OUT
+ * ----------------------------------------------
+ * 21		SW_Reset_		OUT
+ * 25		Phy_Int#		IN
+ * 28		SDI_WP			IN
+ * 29		SDI_Status		IN
+ * 54-61	On GPP Connector	?
+ * 62		Switch Interrupt	IN
+ * 63-65	Reserved from SW Board	?
+ * 66		SW_BRD connected	IN
+ */
+#define RD_78460_GP_GPP_OUT_ENA_LOW	(~(BIT(21) | BIT(20)))
+#define RD_78460_GP_GPP_OUT_ENA_MID	(~(BIT(26) | BIT(27)))
+#define RD_78460_GP_GPP_OUT_ENA_HIGH	(~(0x0))
+
+#define RD_78460_GP_GPP_OUT_VAL_LOW	(BIT(21) | BIT(20))
+#define RD_78460_GP_GPP_OUT_VAL_MID	(BIT(26) | BIT(27))
+#define RD_78460_GP_GPP_OUT_VAL_HIGH	0x0
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x00000000, MVEBU_MPP_BASE + 0x00);
+	writel(0x00000000, MVEBU_MPP_BASE + 0x04);
+	writel(0x33000000, MVEBU_MPP_BASE + 0x08);
+	writel(0x11000000, MVEBU_MPP_BASE + 0x0c);
+	writel(0x11111111, MVEBU_MPP_BASE + 0x10);
+	writel(0x00221100, MVEBU_MPP_BASE + 0x14);
+	writel(0x00000003, MVEBU_MPP_BASE + 0x18);
+	writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
+	writel(0x00000000, MVEBU_MPP_BASE + 0x20);
+
+	/* Configure GPIO */
+	writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+	writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+	writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
+	writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Marvell DB-MV784MP-GP\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1545 PHY */
+void reset_phy(void)
+{
+	u16 devadr = CONFIG_PHY_BASE_ADDR;
+	char *name = "neta0";
+	u16 reg;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* Enable QSGMII AN */
+	/* Set page to 4 */
+	miiphy_write(name, devadr, 0x16, 4);
+	/* Enable AN */
+	miiphy_write(name, devadr, 0x0, 0x1140);
+	/* Set page to 0 */
+	miiphy_write(name, devadr, 0x16, 0);
+
+	/* Phy C_ANEG */
+	miiphy_read(name, devadr, 0x4, &reg);
+	reg |= 0x1E0;
+	miiphy_write(name, devadr, 0x4, reg);
+
+	/* Soft-Reset */
+	miiphy_write(name, devadr, 22, 0x0000);
+	miiphy_write(name, devadr, 0, 0x9140);
+
+	/* Power up the phy */
+	miiphy_read(name, devadr, ETH_PHY_CTRL_REG, &reg);
+	reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
+	miiphy_write(name, devadr, ETH_PHY_CTRL_REG, reg);
+
+	printf("88E1545 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/db-mv784mp-gp/kwbimage.cfg b/board/Marvell/db-mv784mp-gp/kwbimage.cfg
new file mode 100644
index 00000000000..d7ef4071dd0
--- /dev/null
+++ b/board/Marvell/db-mv784mp-gp/kwbimage.cfg
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/Marvell/db-mv784mp-gp/binary.0 0000005b 00000068
diff --git a/board/Marvell/db64360/64360.h b/board/Marvell/db64360/64360.h
deleted file mode 100644
index 99512629c21..00000000000
--- a/board/Marvell/db64360/64360.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * main board support/init for the Galileo Eval board DB64360.
- */
-
-#ifndef __64360_H__
-#define __64360_H__
-
-/* CPU Configuration bits */
-#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
-#define	CPU_CONF_SINGLE_CPU	(1 << 11)
-#define	CPU_CONF_ENDIANESS	(1 << 12)
-#define CPU_CONF_PIPELINE	(1 << 13)
-#define CPU_CONF_STOP_RETRY	(1 << 17)
-#define CPU_CONF_MULTI_DECODE	(1 << 18)
-#define CPU_CONF_DP_VALID	(1 << 19)
-#define CPU_CONF_PERR_PROP	(1 << 22)
-#define CPU_CONF_AACK_DELAY_2	(1 << 25)
-#define CPU_CONF_AP_VALID	(1 << 26)
-#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
-
-/* CPU Master Control bits */
-#define CPU_MAST_CTL_ARB_EN	(1 << 8)
-#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
-#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
-#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
-#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
-#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
-
-#endif /* __64360_H__ */
diff --git a/board/Marvell/db64360/Kconfig b/board/Marvell/db64360/Kconfig
deleted file mode 100644
index c5118f8c881..00000000000
--- a/board/Marvell/db64360/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DB64360
-
-config SYS_BOARD
-	default "db64360"
-
-config SYS_VENDOR
-	default "Marvell"
-
-config SYS_CONFIG_NAME
-	default "DB64360"
-
-endif
diff --git a/board/Marvell/db64360/MAINTAINERS b/board/Marvell/db64360/MAINTAINERS
deleted file mode 100644
index af3eb24a2b0..00000000000
--- a/board/Marvell/db64360/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DB64360 BOARD
-#M:	-
-S:	Maintained
-F:	board/Marvell/db64360/
-F:	include/configs/DB64360.h
-F:	configs/DB64360_defconfig
diff --git a/board/Marvell/db64360/Makefile b/board/Marvell/db64360/Makefile
deleted file mode 100644
index aefe0a789af..00000000000
--- a/board/Marvell/db64360/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2001
-# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= db64360.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
-	  mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
-	  sdram_init.o ../common/intel_flash.o ../common/misc.o
diff --git a/board/Marvell/db64360/README b/board/Marvell/db64360/README
deleted file mode 100644
index ebac4cec197..00000000000
--- a/board/Marvell/db64360/README
+++ /dev/null
@@ -1,105 +0,0 @@
-This file contains status information for the port of the U-Boot to the Marvell Development Board DB64360.
-
-Author: Ronen Shitrit <rshitrit@il.marvell.com>
-
-This U-Boot version is based on the work of Brian Waite and his team from Sky Computers, THANKS A LOT.
-
-Supported CPU Types :
-+++++++++++++++++++++
- IBM750FX (ver 2.3)
- MPC7455 (ver 2.1)
-
-Supported CPU Cache Library:
-++++++++++++++++++++++++++++
- L1 and L2 only.
-
-CPU Control:
-++++++++++++
- Marvell optimized CPU control settings:
-  Big Endian
-  Enable CPU pipeline
-  Data and address parity checking
-  AACK# assert after 2 cycles
-
-U-Boot I/O Interface Support:
-+++++++++++++++++++++++++++++
-- Serial Interface (UART)
-  This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module.
-- Network Interface
-  This LSP supports the following network devices:
-  o MV64360 Gigabit Ethernet Controller device
-  o Intel 82559 PCI NIC device
-- PCI Interface
-  This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units:
-  o Local PCI configuration header control.
-  o External PCI configuration header control (for other agents on the bus).
-  o PCI configuration application. Scans and configures the PCI agents on the bus.
-  o PCI Internal Arbiter activation and configuration.
-
-Memory Interface Support:
-+++++++++++++++++++++++++
-- DDR
-  o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs).
-  o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma.
-
-- Devices
-  o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM.
-  o JFFS2
-    JFFS2 is a crash/power down safe file system for disk-less embedded devices.
-    This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it.
-
-Unsupported Features:
-+++++++++++++++++++++
- Messaging unit - No support for MV64360 Messaging unit.
- Watchdog Timer - No support for MV64360 Watchdog unit.
- L3 cache - No support for L3 cache on MPC7455
- Dual PCU - No support for Dual CPU
- PCI-X was never tested
- IDMA driver - No support for MV64360 IDMA unit.
-
-BSP Special Considerations:
-+++++++++++++++++++++++++++
-- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots.
-- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical.
-
-Test Cases:
-###########
-UART:
-+++++
-Check that the UART baud rate is configured to 57600 and 115200, and check:
-	Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom.
-	Load S-Record file over the UART using Windows HyperTerminal.
-
-Network:
-++++++++
-Use TFTP application to load a debugged executable and execute it.
-Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC.
-
-Memory:
-+++++++
-Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters:
-o	128MB DIMM consist of 16 x 64Mbit devices
-o	128MB DIMM consist of 09 x 128Mbit devices @ 266MHz.
-o	256MB DIMM consist of 16 x 128Mbit devices @ 266MHz.
-o	256MB DIMM consist of 09 x 256Mbit devices @ 400MHz.
-o	512MB DIMM consist of 16 x 256Mbit devices @ 333MHz.
-o	512MB DIMM consist of 18 x 256Mbit devices @ 266MHz.
-o	GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered
-
-For each chip select device perform data access to verify its accessibility.
-
-Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage.
-Load the U-Boot and:
-use the ls command to check correct scan of the JFFS2 on the large flash.
-Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage.
-
-PCI:
-++++
-1)Insert different PCI cards:
-Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech  NIC 8139 rev10
-on different slots (0-3) of the PCI and check:
-o	Correct detection of the PCI devices.
-o	Correct address mapping of the PCI devices.
-2)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot.
-
-Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal)
diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c
deleted file mode 100644
index 36d26e3f14f..00000000000
--- a/board/Marvell/db64360/db64360.c
+++ /dev/null
@@ -1,922 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
- */
-
-/*
- * db64360.c - main board support/init for the Galileo Eval board.
- */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include "../include/memory.h"
-#include "../include/pci.h"
-#include "../include/mv_gen_reg.h"
-#include <net.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "i2c.h"
-#include "64360.h"
-#include "mv_regs.h"
-
-#undef	DEBUG
-/*#define	DEBUG */
-
-#define	MAP_PCI
-
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-/* this is the current GT register space location */
-/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
-
-/* Unfortunately, we cant change it while we are in flash, so we initialize it
- * to the "final" value. This means that any debug_led calls before
- * board_early_init_f wont work right (like in cpu_init_f).
- * See also my_remap_gt_regs below. (NTL)
- */
-
-void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
-int display_mem_map (void);
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * This is a version of the GT register space remapping function that
- * doesn't touch globals (meaning, it's ok to run from flash.)
- *
- * Unfortunately, this has the side effect that a writable
- * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
- */
-
-void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
-{
-	u32 temp;
-
-	/* check and see if it's already moved */
-
-/* original ppcboot 1.1.6 source
-
-	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 20)
-		return;
-
-	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 20);
-
-	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
-original ppcboot 1.1.6 source end */
-
-	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 16)
-		return;
-
-	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 16);
-
-	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
-}
-
-#ifdef CONFIG_PCI
-
-static void gt_pci_config (void)
-{
-	unsigned int stat;
-	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
-
-	/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
-	 * config registers by writing ones to the bus and device.
-	 * We then update the Virtual register with the correct value for the bus and device.
-	 */
-	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
-		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
-
-		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
-
-		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
-		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
-
-	}
-	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
-		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
-		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
-
-		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
-		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
-	}
-
-	/* Enable master */
-	PCI_MASTER_ENABLE (0, SELF);
-	PCI_MASTER_ENABLE (1, SELF);
-
-	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
-	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
-	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
-									     <<
-									     18);
-	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
-	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
-
-	/* ronen- add write to pci remap registers for 64460.
-	   in 64360 when writing to pci base go and overide remap automaticaly,
-	   in 64460 it doesn't */
-	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
-
-	/* PCI interface settings */
-	/* Timeout set to retry forever */
-	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
-	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
-
-	/* ronen - enable only CS0 and Internal reg!! */
-	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-
-/*ronen update the pci internal registers base address.*/
-#ifdef MAP_PCI
-	for (stat = 0; stat <= PCI_HOST1; stat++)
-		pciWriteConfigReg (stat,
-				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
-				   SELF, CONFIG_SYS_GT_REGS);
-#endif
-
-}
-#endif
-
-/* Setup CPU interface paramaters */
-static void gt_cpu_config (void)
-{
-	cpu_t cpu = get_cpu_type ();
-	ulong tmp;
-
-	/* cpu configuration register */
-	tmp = GTREGREAD (CPU_CONFIGURATION);
-
-	/* set the SINGLE_CPU bit  see MV64360 P.399 */
-#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
-	tmp |= CPU_CONF_SINGLE_CPU;
-#endif
-
-	tmp &= ~CPU_CONF_AACK_DELAY_2;
-
-	tmp |= CPU_CONF_DP_VALID;
-	tmp |= CPU_CONF_AP_VALID;
-
-	tmp |= CPU_CONF_PIPELINE;
-
-	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
-
-	/* CPU master control register */
-	tmp = GTREGREAD (CPU_MASTER_CONTROL);
-
-	tmp |= CPU_MAST_CTL_ARB_EN;
-
-	if ((cpu == CPU_7400) ||
-	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
-
-		tmp |= CPU_MAST_CTL_CLEAN_BLK;
-		tmp |= CPU_MAST_CTL_FLUSH_BLK;
-
-	} else {
-		/* cleanblock must be cleared for CPUs
-		 * that do not support this command (603e, 750)
-		 * see Res#1 */
-		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
-		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
-	}
-	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
-}
-
-/*
- * board_early_init_f.
- *
- * set up gal. device mappings, etc.
- */
-int board_early_init_f (void)
-{
-	uchar sram_boot = 0;
-
-	/*
-	 * set up the GT the way the kernel wants it
-	 * the call to move the GT register space will obviously
-	 * fail if it has already been done, but we're going to assume
-	 * that if it's not at the power-on location, it's where we put
-	 * it last time. (huber)
-	 */
-
-	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
-
-	/* No PCI in first release of Port To_do: enable it. */
-#ifdef CONFIG_PCI
-	gt_pci_config ();
-#endif
-	/* mask all external interrupt sources */
-	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
-	/* new in MV6436x */
-	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
-	/* --------------------- */
-	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
-	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
-	/* does not exist in MV6436x
-	   GT_REG_WRITE(CPU_INT_0_MASK, 0);
-	   GT_REG_WRITE(CPU_INT_1_MASK, 0);
-	   GT_REG_WRITE(CPU_INT_2_MASK, 0);
-	   GT_REG_WRITE(CPU_INT_3_MASK, 0);
-	   --------------------- */
-
-
-	/* ----- DEVICE BUS SETTINGS ------ */
-
-	/*
-	 * EVB
-	 * 0 - SRAM   ????
-	 * 1 - RTC      ????
-	 * 2 - UART     ????
-	 * 3 - Flash    checked 32Bit Intel Strata
-	 * boot - BootCS checked 8Bit 29LV040B
-	 *
-	 * Zuma
-	 * 0 - Flash
-	 * boot - BootCS
-	 */
-
-	/*
-	 * the dual 7450 module requires burst access to the boot
-	 * device, so the serial rom copies the boot device to the
-	 * on-board sram on the eval board, and updates the correct
-	 * registers to boot from the sram. (device0)
-	 */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
-		sram_boot = 1;
-	if (!sram_boot)
-		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
-
-	memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
-	memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
-	memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
-
-
-	/* configure device timing */
-#ifdef CONFIG_SYS_DEV0_PAR		/* set port parameters for SRAM device module access */
-	if (!sram_boot)
-		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
-#endif
-
-#ifdef CONFIG_SYS_DEV1_PAR		/* set port parameters for RTC device module access */
-	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
-#endif
-#ifdef CONFIG_SYS_DEV2_PAR		/* set port parameters for DUART device module access */
-	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
-#endif
-
-#ifdef CONFIG_SYS_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
-	/* detect if we are booting from the 32 bit flash */
-	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
-		/* 32 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
-			      CONFIG_SYS_32BIT_BOOT_PAR);
-	} else {
-		/* 8 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
-	}
-#else
-	/* 8 bit boot flash only */
-/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
-#endif
-
-
-	gt_cpu_config ();
-
-	/* MPP setup */
-	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
-	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
-	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
-	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
-
-	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
-	DEBUG_LED0_ON ();
-	DEBUG_LED1_ON ();
-	DEBUG_LED2_ON ();
-
-	return 0;
-}
-
-/* various things to do after relocation */
-
-int misc_init_r ()
-{
-	icache_enable ();
-#ifdef CONFIG_SYS_L2
-	l2cache_enable ();
-#endif
-#ifdef CONFIG_MPSC
-
-	mpsc_sdma_init ();
-	mpsc_init2 ();
-#endif
-
-#if 0
-	/* disable the dcache and MMU */
-	dcache_lock ();
-#endif
-	return 0;
-}
-
-void after_reloc (ulong dest_addr, gd_t * gd)
-{
-	/* check to see if we booted from the sram.  If so, move things
-	 * back to the way they should be. (we're running from main
-	 * memory at this point now */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
-		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
-		memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
-	}
-	display_mem_map ();
-	/* now, jump to the main ppcboot board init code */
-	board_init_r (gd, dest_addr);
-	/* NOTREACHED */
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- *
- * right now, assume borad type. (there is just one...after all)
- */
-
-int checkboard (void)
-{
-	int l_type = 0;
-
-	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
-	return (l_type);
-}
-
-/* utility functions */
-void debug_led (int led, int mode)
-{
-	volatile int *addr = 0;
-	__maybe_unused int dummy;
-
-	if (mode == 1) {
-		switch (led) {
-		case 0:
-			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
-					0x08000);
-			break;
-
-		case 1:
-			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
-					0x0c000);
-			break;
-
-		case 2:
-			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
-					0x10000);
-			break;
-		}
-	} else if (mode == 0) {
-		switch (led) {
-		case 0:
-			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
-					0x14000);
-			break;
-
-		case 1:
-			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
-					0x18000);
-			break;
-
-		case 2:
-			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
-					0x1c000);
-			break;
-		}
-	}
-
-	dummy = *addr;
-}
-
-int display_mem_map (void)
-{
-	int i, j;
-	unsigned int base, size, width;
-
-	/* SDRAM */
-	printf ("SD (DDR) RAM\n");
-	for (i = 0; i <= BANK3; i++) {
-		base = memoryGetBankBaseAddress (i);
-		size = memoryGetBankSize (i);
-		if (size != 0) {
-			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
-				i, base, size >> 20);
-		}
-	}
-
-	/* CPU's PCI windows */
-	for (i = 0; i <= PCI_HOST1; i++) {
-		printf ("\nCPU's PCI %d windows\n", i);
-		base = pciGetSpaceBase (i, PCI_IO);
-		size = pciGetSpaceSize (i, PCI_IO);
-		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
-			size >> 20);
-		for (j = 0;
-		     j <=
-		     PCI_REGION0
-		     /*ronen currently only first PCI MEM is used 3 */ ;
-		     j++) {
-			base = pciGetSpaceBase (i, j);
-			size = pciGetSpaceSize (i, j);
-			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
-		}
-	}
-
-	/* Devices */
-	printf ("\nDEVICES\n");
-	for (i = 0; i <= DEVICE3; i++) {
-		base = memoryGetDeviceBaseAddress (i);
-		size = memoryGetDeviceSize (i);
-		width = memoryGetDeviceWidth (i) * 8;
-		printf ("DEV %d:  base - 0x%08x  size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
-		if (i == 0)
-			printf ("\t- EXT SRAM (actual - 1M)\n");
-		else if (i == 1)
-			printf ("\t- RTC\n");
-		else if (i == 2)
-			printf ("\t- UART\n");
-		else
-			printf ("\t- LARGE FLASH\n");
-	}
-
-	/* Bootrom */
-	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
-	size = memoryGetDeviceSize (BOOT_DEVICE);
-	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
-	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\n",
-		base, size >> 20, width);
-	return (0);
-}
-
-/* DRAM check routines copied from gw8260 */
-
-#if defined (CONFIG_SYS_DRAM_TEST)
-
-/*********************************************************************/
-/* NAME:  move64() -  moves a double word (64-bit)		     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   this function performs a double word move from the data at	     */
-/*   the source pointer to the location at the destination pointer.  */
-/*								     */
-/* INPUTS:							     */
-/*   unsigned long long *src  - pointer to data to move		     */
-/*								     */
-/* OUTPUTS:							     */
-/*   unsigned long long *dest - pointer to locate to move data	     */
-/*								     */
-/* RETURNS:							     */
-/*   None							     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*   May cloober fr0.						     */
-/*								     */
-/*********************************************************************/
-static void move64 (unsigned long long *src, unsigned long long *dest)
-{
-	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
-	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
-      : : : "fr0");		/* Clobbers fr0         */
-	return;
-}
-
-
-#if defined (CONFIG_SYS_DRAM_TEST_DATA)
-
-unsigned long long pattern[] = {
-	0xaaaaaaaaaaaaaaaaULL,
-	0xccccccccccccccccULL,
-	0xf0f0f0f0f0f0f0f0ULL,
-	0xff00ff00ff00ff00ULL,
-	0xffff0000ffff0000ULL,
-	0xffffffff00000000ULL,
-	0x00000000ffffffffULL,
-	0x0000ffff0000ffffULL,
-	0x00ff00ff00ff00ffULL,
-	0x0f0f0f0f0f0f0f0fULL,
-	0x3333333333333333ULL,
-	0x5555555555555555ULL,
-};
-
-/*********************************************************************/
-/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Tests data lines for shorts and opens by forcing adjacent data  */
-/*   to opposite states. Because the data lines could be routed in   */
-/*   an arbitrary manner the must ensure test patterns ensure that   */
-/*   every case is tested. By using the following series of binary   */
-/*   patterns every combination of adjacent bits is test regardless  */
-/*   of routing.						     */
-/*								     */
-/*     ...101010101010101010101010				     */
-/*     ...110011001100110011001100				     */
-/*     ...111100001111000011110000				     */
-/*     ...111111110000000011111111				     */
-/*								     */
-/*   Carrying this out, gives us six hex patterns as follows:	     */
-/*								     */
-/*     0xaaaaaaaaaaaaaaaa					     */
-/*     0xcccccccccccccccc					     */
-/*     0xf0f0f0f0f0f0f0f0					     */
-/*     0xff00ff00ff00ff00					     */
-/*     0xffff0000ffff0000					     */
-/*     0xffffffff00000000					     */
-/*								     */
-/*   The number test patterns will always be given by:		     */
-/*								     */
-/*   log(base 2)(number data bits) = log2 (64) = 6		     */
-/*								     */
-/*   To test for short and opens to other signals on our boards. we  */
-/*   simply							     */
-/*   test with the 1's complemnt of the paterns as well.	     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern				     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*  Assumes only one one SDRAM bank				     */
-/*								     */
-/*********************************************************************/
-int mem_test_data (void)
-{
-	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
-	unsigned long long temp64 = 0;
-	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
-	int i;
-	unsigned int hi, lo;
-
-	for (i = 0; i < num_patterns; i++) {
-		move64 (&(pattern[i]), pmem);
-		move64 (pmem, &temp64);
-
-		/* hi = (temp64>>32) & 0xffffffff;          */
-		/* lo = temp64 & 0xffffffff;                */
-		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
-
-		hi = (pattern[i] >> 32) & 0xffffffff;
-		lo = pattern[i] & 0xffffffff;
-		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
-
-		if (temp64 != pattern[i]) {
-			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
-				hi, lo);
-			return 1;
-		}
-	}
-
-	return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_DATA */
-
-#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
-/*********************************************************************/
-/* NAME:  mem_test_address() -	test address lines		     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   This function performs a test to verify that each word im	     */
-/*   memory is uniquly addressable. The test sequence is as follows: */
-/*								     */
-/*   1) write the address of each word to each word.		     */
-/*   2) verify that each location equals its address		     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern and address			     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_test_address (void)
-{
-	volatile unsigned int *pmem =
-		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
-	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
-	unsigned int i;
-
-	/* write address to each location */
-	for (i = 0; i < size; i++) {
-		pmem[i] = i;
-	}
-
-	/* verify each loaction */
-	for (i = 0; i < size; i++) {
-		if (pmem[i] != i) {
-			printf ("\n   Address Test Failed at 0x%x", i);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
-
-#if defined (CONFIG_SYS_DRAM_TEST_WALK)
-/*********************************************************************/
-/* NAME:   mem_march() -  memory march				     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Marches up through memory. At each location verifies rmask if   */
-/*   read = 1. At each location write wmask if	write = 1. Displays  */
-/*   failing address and pattern.				     */
-/*								     */
-/* INPUTS:							     */
-/*   volatile unsigned long long * base - start address of test	     */
-/*   unsigned int size - number of dwords(64-bit) to test	     */
-/*   unsigned long long rmask - read verify mask		     */
-/*   unsigned long long wmask - wrtie verify mask		     */
-/*   short read - verifies rmask if read = 1			     */
-/*   short write  - writes wmask if write = 1			     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern and address			     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_march (volatile unsigned long long *base,
-	       unsigned int size,
-	       unsigned long long rmask,
-	       unsigned long long wmask, short read, short write)
-{
-	unsigned int i;
-	unsigned long long temp = 0;
-	unsigned int hitemp, lotemp, himask, lomask;
-
-	for (i = 0; i < size; i++) {
-		if (read != 0) {
-			/* temp = base[i]; */
-			move64 ((unsigned long long *) &(base[i]), &temp);
-			if (rmask != temp) {
-				hitemp = (temp >> 32) & 0xffffffff;
-				lotemp = temp & 0xffffffff;
-				himask = (rmask >> 32) & 0xffffffff;
-				lomask = rmask & 0xffffffff;
-
-				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
-				return 1;
-			}
-		}
-		if (write != 0) {
-			/*  base[i] = wmask; */
-			move64 (&wmask, (unsigned long long *) &(base[i]));
-		}
-	}
-	return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_WALK */
-
-/*********************************************************************/
-/* NAME:   mem_test_walk() -  a simple walking ones test	     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Performs a walking ones through entire physical memory. The     */
-/*   test uses as series of memory marches, mem_march(), to verify   */
-/*   and write the test patterns to memory. The test sequence is as  */
-/*   follows:							     */
-/*     1) march writing 0000...0001				     */
-/*     2) march verifying 0000...0001  , writing  0000...0010	     */
-/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
-/*	   the write mask equals 1000...0000			     */
-/*     4) march verifying 1000...0000				     */
-/*   The test fails if any of the memory marches return a failure.   */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays which pass on the memory test is executing	     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_test_walk (void)
-{
-	unsigned long long mask;
-	volatile unsigned long long *pmem =
-		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
-	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
-
-	unsigned int i;
-
-	mask = 0x01;
-
-	printf ("Initial Pass");
-	mem_march (pmem, size, 0x0, 0x1, 0, 1);
-
-	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-	printf ("		");
-	printf ("         ");
-	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-
-	for (i = 0; i < 63; i++) {
-		printf ("Pass %2d", i + 2);
-		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
-			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
-			return 1;
-		}
-		mask = mask << 1;
-		printf ("\b\b\b\b\b\b\b");
-	}
-
-	printf ("Last Pass");
-	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
-		/* printf("mask: 0x%x", mask); */
-		return 1;
-	}
-	printf ("\b\b\b\b\b\b\b\b\b");
-	printf ("	     ");
-	printf ("\b\b\b\b\b\b\b\b\b");
-
-	return 0;
-}
-
-/*********************************************************************/
-/* NAME:    testdram() -  calls any enabled memory tests	     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Runs memory tests if the environment test variables are set to  */
-/*   'y'.							     */
-/*								     */
-/* INPUTS:							     */
-/*   testdramdata    - If set to 'y', data test is run.		     */
-/*   testdramaddress - If set to 'y', address test is run.	     */
-/*   testdramwalk    - If set to 'y', walking ones test is run	     */
-/*								     */
-/* OUTPUTS:							     */
-/*   None							     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int testdram (void)
-{
-	int rundata, runaddress, runwalk;
-
-	rundata = getenv_yesno("testdramdata") == 1;
-	runaddress = getenv_yesno("testdramaddress") == 1;
-	runwalk = getenv_yesno("testdramwalk") == 1;
-
-/*    rundata = 1; */
-/*    runaddress = 0; */
-/*    runwalk = 0; */
-
-	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
-	}
-#ifdef CONFIG_SYS_DRAM_TEST_DATA
-	if (rundata == 1) {
-		printf ("Test DATA ...  ");
-		if (mem_test_data () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
-	if (runaddress == 1) {
-		printf ("Test ADDRESS ...  ");
-		if (mem_test_address () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_WALK
-	if (runwalk == 1) {
-		printf ("Test WALKING ONEs ...  ");
-		if (mem_test_walk () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("passed\n");
-	}
-	return 0;
-
-}
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-/* ronen - the below functions are used by the bootm function           */
-/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
-/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
-/*    the kernel data areas.                                            */
-/*  - we diable and invalidate the icache and dcache.                   */
-void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
-{
-	u32 temp;
-
-	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 16)
-		return;
-
-	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 16);
-
-	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
-							new_loc |
-							(INTERNAL_SPACE_DECODE)))))
-	       != temp);
-
-}
-
-void board_prebootm_init ()
-{
-
-/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
-		GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
-
-/* Stop GigE Rx DMA engines */
-	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
-	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
-/* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */
-
-/* Relocate MV64360 internal regs */
-	my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
-
-	icache_disable ();
-	dcache_disable ();
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int ret;
-	ret = pci_eth_init(bis);
-	if (!ret)
-		ret = mv6436x_eth_initialize(bis);
-	return ret;
-}
diff --git a/board/Marvell/db64360/eth.h b/board/Marvell/db64360/eth.h
deleted file mode 100644
index 4e427683b41..00000000000
--- a/board/Marvell/db64360/eth.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __EVB64360_ETH_H__
-#define __EVB64360_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-
-
-int db64360_eth0_poll(void);
-int db64360_eth0_transmit(unsigned int s, volatile char *p);
-void db64360_eth0_disable(void);
-bool network_start(bd_t *bis);
-
-int mv6436x_eth_initialize(bd_t *);
-
-#endif /* __EVB64360_ETH_H__ */
diff --git a/board/Marvell/db64360/mpsc.c b/board/Marvell/db64360/mpsc.c
deleted file mode 100644
index d87f18eea38..00000000000
--- a/board/Marvell/db64360/mpsc.c
+++ /dev/null
@@ -1,1001 +0,0 @@
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*************************************************************************
- * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
-  ************************************************************************/
-
-/*
- * mpsc.c - driver for console over the MPSC.
- */
-
-
-#include <common.h>
-#include <config.h>
-#include <asm/cache.h>
-
-#include <malloc.h>
-#include "mpsc.h"
-
-#include "mv_regs.h"
-
-#include "../include/memory.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Define this if you wish to use the MPSC as a register based UART.
- * This will force the serial port to not use the SDMA engine at all.
- */
-#undef CONFIG_MPSC_DEBUG_PORT
-
-
-int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
-char (*mpsc_getchar) (void) = mpsc_getchar_debug;
-int (*mpsc_test_char) (void) = mpsc_test_char_debug;
-
-
-static volatile unsigned int *rx_desc_base = NULL;
-static unsigned int rx_desc_index = 0;
-static volatile unsigned int *tx_desc_base = NULL;
-static unsigned int tx_desc_index = 0;
-
-/* local function declarations */
-static int galmpsc_connect (int channel, int connect);
-static int galmpsc_route_rx_clock (int channel, int brg);
-static int galmpsc_route_tx_clock (int channel, int brg);
-static int galmpsc_write_config_regs (int mpsc, int mode);
-static int galmpsc_config_channel_regs (int mpsc);
-static int galmpsc_set_char_length (int mpsc, int value);
-static int galmpsc_set_stop_bit_length (int mpsc, int value);
-static int galmpsc_set_parity (int mpsc, int value);
-static int galmpsc_enter_hunt (int mpsc);
-static int galmpsc_set_brkcnt (int mpsc, int value);
-static int galmpsc_set_tcschar (int mpsc, int value);
-static int galmpsc_set_snoop (int mpsc, int value);
-static int galmpsc_shutdown (int mpsc);
-
-static int galsdma_set_RFT (int channel);
-static int galsdma_set_SFM (int channel);
-static int galsdma_set_rxle (int channel);
-static int galsdma_set_txle (int channel);
-static int galsdma_set_burstsize (int channel, unsigned int value);
-static int galsdma_set_RC (int channel, unsigned int value);
-
-static int galbrg_set_CDV (int channel, int value);
-static int galbrg_enable (int channel);
-static int galbrg_disable (int channel);
-static int galbrg_set_clksrc (int channel, int value);
-static int galbrg_set_CUV (int channel, int value);
-
-static void galsdma_enable_rx (void);
-static int galsdma_set_mem_space (unsigned int memSpace,
-				  unsigned int memSpaceTarget,
-				  unsigned int memSpaceAttr,
-				  unsigned int baseAddress,
-				  unsigned int size);
-
-
-#define SOFTWARE_CACHE_MANAGEMENT
-
-#ifdef SOFTWARE_CACHE_MANAGEMENT
-#define FLUSH_DCACHE(a,b)		 if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
-#define INVALIDATE_DCACHE(a,b)		 if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
-#else
-#define FLUSH_DCACHE(a,b)
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
-#define INVALIDATE_DCACHE(a,b)
-#endif
-
-#ifdef CONFIG_MPSC_DEBUG_PORT
-static void mpsc_debug_init (void)
-{
-
-	volatile unsigned int temp;
-
-	/* Clear the CFR  (CHR4) */
-	/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
-	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
-	temp &= 0xffffff00;
-	temp |= BIT29;
-	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
-		      temp);
-
-	/* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
-	temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
-	temp |= (BIT12 | BIT15);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
-		      temp);
-
-	/* Set int mask */
-	temp = GTREGREAD (GALMPSC_0_INT_MASK);
-	temp |= BIT6;
-	GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
-}
-#endif
-
-char mpsc_getchar_debug (void)
-{
-	volatile int temp;
-	volatile unsigned int cause;
-
-	cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
-	while ((cause & BIT6) == 0) {
-		cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
-	}
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
-			  (CHANNEL * GALMPSC_REG_GAP));
-	/* By writing 1's to the set bits, the register is cleared */
-	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
-		      temp);
-	GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
-	return (temp >> 16) & 0xff;
-}
-
-/* special function for running out of flash.  doesn't modify any
- * global variables [josh] */
-int mpsc_putchar_early (char ch)
-{
-	int mpsc = CHANNEL;
-	int temp =
-		GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
-	galmpsc_set_tcschar (mpsc, ch);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
-		      temp | 0x200);
-
-#define MAGIC_FACTOR	(10*1000000)
-
-	udelay (MAGIC_FACTOR / gd->baudrate);
-	return 0;
-}
-
-/* This is used after relocation, see serial.c and mpsc_init2 */
-static int mpsc_putchar_sdma (char ch)
-{
-	volatile unsigned int *p;
-	unsigned int temp;
-
-
-	/* align the descriptor */
-	p = tx_desc_base;
-	memset ((void *) p, 0, 8 * sizeof (unsigned int));
-
-	/* fill one 64 bit buffer */
-	/* word swap, pad with 0 */
-	p[4] = 0;		/* x */
-	p[5] = (unsigned int) ch;	/* x */
-
-	/* CHANGED completely according to GT64260A dox - NTL */
-	p[0] = 0x00010001;	/* 0 */
-	p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* 4 */
-	p[2] = 0;		/* 8 */
-	p[3] = (unsigned int) &p[4];	/* c */
-
-#if 0
-	p[9] = DESC_FIRST | DESC_LAST;
-	p[10] = (unsigned int) &p[0];
-	p[11] = (unsigned int) &p[12];
-#endif
-
-	FLUSH_DCACHE (&p[0], &p[8]);
-
-	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
-		      (unsigned int) &p[0]);
-	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
-		      (unsigned int) &p[0]);
-
-	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
-	temp |= (TX_DEMAND | TX_STOP);
-	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
-
-	INVALIDATE_DCACHE (&p[1], &p[2]);
-
-	while (p[1] & DESC_OWNER_BIT) {
-		udelay (100);
-		INVALIDATE_DCACHE (&p[1], &p[2]);
-	}
-	return 0;
-}
-
-char mpsc_getchar_sdma (void)
-{
-	static unsigned int done = 0;
-	volatile char ch;
-	unsigned int len = 0, idx = 0, temp;
-
-	volatile unsigned int *p;
-
-
-	do {
-		p = &rx_desc_base[rx_desc_index * 8];
-
-		INVALIDATE_DCACHE (&p[0], &p[1]);
-		/* Wait for character */
-		while (p[1] & DESC_OWNER_BIT) {
-			udelay (100);
-			INVALIDATE_DCACHE (&p[0], &p[1]);
-		}
-
-		/* Handle error case */
-		if (p[1] & (1 << 15)) {
-			printf ("oops, error: %08x\n", p[1]);
-
-			temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
-					  (CHANNEL * GALMPSC_REG_GAP));
-			temp |= (1 << 23);
-			GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
-				      (CHANNEL * GALMPSC_REG_GAP), temp);
-
-			/* Can't poll on abort bit, so we just wait. */
-			udelay (100);
-
-			galsdma_enable_rx ();
-		}
-
-		/* Number of bytes left in this descriptor */
-		len = p[0] & 0xffff;
-
-		if (len) {
-			/* Where to look */
-			idx = 5;
-			if (done > 3)
-				idx = 4;
-			if (done > 7)
-				idx = 7;
-			if (done > 11)
-				idx = 6;
-
-			INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
-			ch = p[idx] & 0xff;
-			done++;
-		}
-
-		if (done < len) {
-			/* this descriptor has more bytes still
-			 * shift down the char we just read, and leave the
-			 * buffer in place for the next time around
-			 */
-			p[idx] = p[idx] >> 8;
-			FLUSH_DCACHE (&p[idx], &p[idx + 1]);
-		}
-
-		if (done == len) {
-			/* nothing left in this descriptor.
-			 * go to next one
-			 */
-			p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
-			p[0] = 0x00100000;
-			FLUSH_DCACHE (&p[0], &p[1]);
-			/* Next descriptor */
-			rx_desc_index = (rx_desc_index + 1) % RX_DESC;
-			done = 0;
-		}
-	} while (len == 0);	/* galileo bug.. len might be zero */
-
-	return ch;
-}
-
-
-int mpsc_test_char_debug (void)
-{
-	if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
-		return 0;
-	else {
-		return 1;
-	}
-}
-
-
-int mpsc_test_char_sdma (void)
-{
-	volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
-
-	INVALIDATE_DCACHE (&p[1], &p[2]);
-
-	if (p[1] & DESC_OWNER_BIT)
-		return 0;
-	else
-		return 1;
-}
-
-int mpsc_init (int baud)
-{
-	/* BRG CONFIG */
-	galbrg_set_baudrate (CHANNEL, baud);
-	galbrg_set_clksrc (CHANNEL, 8);	/* set source=Tclk */
-	galbrg_set_CUV (CHANNEL, 0);	/* set up CountUpValue */
-	galbrg_enable (CHANNEL);	/* Enable BRG */
-
-	/* Set up clock routing */
-	galmpsc_connect (CHANNEL, GALMPSC_CONNECT);	/* connect it */
-
-	galmpsc_route_rx_clock (CHANNEL, CHANNEL);	/* chosse BRG0 for Rx */
-	galmpsc_route_tx_clock (CHANNEL, CHANNEL);	/* chose BRG0 for Tx */
-
-	/* reset MPSC state */
-	galmpsc_shutdown (CHANNEL);
-
-	/* SDMA CONFIG */
-	galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8);	/* in 64 bit words (8 bytes) */
-	galsdma_set_txle (CHANNEL);
-	galsdma_set_rxle (CHANNEL);
-	galsdma_set_RC (CHANNEL, 0xf);
-	galsdma_set_SFM (CHANNEL);
-	galsdma_set_RFT (CHANNEL);
-
-	/* MPSC CONFIG */
-	galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
-	galmpsc_config_channel_regs (CHANNEL);
-	galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8);	/* 8 */
-	galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE);	/* N */
-	galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1);	/* 1 */
-
-#ifdef CONFIG_MPSC_DEBUG_PORT
-	mpsc_debug_init ();
-#endif
-
-	/* COMM_MPSC CONFIG */
-#ifdef SOFTWARE_CACHE_MANAGEMENT
-	galmpsc_set_snoop (CHANNEL, 0);	/* disable snoop */
-#else
-	galmpsc_set_snoop (CHANNEL, 1);	/* enable snoop */
-#endif
-
-	return 0;
-}
-
-
-void mpsc_sdma_init (void)
-{
-/* Setup SDMA channel0 SDMA_CONFIG_REG*/
-	GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
-
-/*  Enable MPSC-Window0 for DRAM Bank0   */
-	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT,
-				   MV64360_SDMA_DRAM_CS_0_TARGET,
-				   0,
-				   memoryGetBankBaseAddress
-				   (CS_0_LOW_DECODE_ADDRESS),
-				   memoryGetBankSize (BANK0)) != true)
-		printf ("%s: SDMA_Window0 memory setup failed !!! \n",
-			__FUNCTION__);
-
-
-/*  Disable MPSC-Window1    */
-	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT,
-				   MV64360_SDMA_DRAM_CS_0_TARGET,
-				   0,
-				   memoryGetBankBaseAddress
-				   (CS_1_LOW_DECODE_ADDRESS),
-				   memoryGetBankSize (BANK3)) != true)
-		printf ("%s: SDMA_Window1 memory setup failed !!! \n",
-			__FUNCTION__);
-
-
-/*  Disable MPSC-Window2 */
-	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT,
-				   MV64360_SDMA_DRAM_CS_0_TARGET,
-				   0,
-				   memoryGetBankBaseAddress
-				   (CS_2_LOW_DECODE_ADDRESS),
-				   memoryGetBankSize (BANK3)) != true)
-		printf ("%s: SDMA_Window2 memory setup failed !!! \n",
-			__FUNCTION__);
-
-
-/*  Disable MPSC-Window3 */
-	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT,
-				   MV64360_SDMA_DRAM_CS_0_TARGET,
-				   0,
-				   memoryGetBankBaseAddress
-				   (CS_3_LOW_DECODE_ADDRESS),
-				   memoryGetBankSize (BANK3)) != true)
-		printf ("%s: SDMA_Window3 memory setup failed !!! \n",
-			__FUNCTION__);
-
-/*  Setup MPSC0 access mode Window0 full access */
-	GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
-			 (MV64360_SDMA_WIN_ACCESS_FULL <<
-			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
-
-/*  Setup MPSC1 access mode Window1 full access */
-	GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
-			 (MV64360_SDMA_WIN_ACCESS_FULL <<
-			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
-
-/* Setup MPSC internal address space base address	*/
-	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
-
-/* no high address remap*/
-	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
-	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
-
-/* clear interrupt cause register for MPSC (fault register)*/
-	GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
-}
-
-
-void mpsc_init2 (void)
-{
-	int i;
-
-#ifndef CONFIG_MPSC_DEBUG_PORT
-	mpsc_putchar = mpsc_putchar_sdma;
-	mpsc_getchar = mpsc_getchar_sdma;
-	mpsc_test_char = mpsc_test_char_sdma;
-#endif
-	/* RX descriptors */
-	rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
-						sizeof (unsigned int));
-
-	/* align descriptors */
-	rx_desc_base = (unsigned int *)
-		(((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
-
-	rx_desc_index = 0;
-
-	memset ((void *) rx_desc_base, 0,
-		(RX_DESC * 8) * sizeof (unsigned int));
-
-	for (i = 0; i < RX_DESC; i++) {
-		rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4];	/* Buffer */
-		rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8];	/* Next descriptor */
-		rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* Command & control */
-		rx_desc_base[i * 8] = 0x00100000;
-	}
-	rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
-
-	FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
-	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
-		      (unsigned int) &rx_desc_base[0]);
-
-	/* TX descriptors */
-	tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
-						sizeof (unsigned int));
-
-	/* align descriptors */
-	tx_desc_base = (unsigned int *)
-		(((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
-
-	tx_desc_index = -1;
-
-	memset ((void *) tx_desc_base, 0,
-		(TX_DESC * 8) * sizeof (unsigned int));
-
-	for (i = 0; i < TX_DESC; i++) {
-		tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
-		tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
-		tx_desc_base[i * 8 + 3] =
-			(unsigned int) &tx_desc_base[i * 8 + 4];
-		tx_desc_base[i * 8 + 2] =
-			(unsigned int) &tx_desc_base[(i + 1) * 8];
-		tx_desc_base[i * 8 + 1] =
-			DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
-
-		/* set sbytecnt and shadow byte cnt to 1 */
-		tx_desc_base[i * 8] = 0x00010001;
-	}
-	tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
-
-	FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
-
-	udelay (100);
-
-	galsdma_enable_rx ();
-
-	return;
-}
-
-int galbrg_set_baudrate (int channel, int rate)
-{
-	int clock;
-
-	galbrg_disable (channel);	/*ok */
-
-#ifdef ZUMA_NTL
-	/* from tclk */
-	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
-#else
-	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
-#endif
-
-	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
-
-	galbrg_enable (channel);
-
-	gd->baudrate = rate;
-
-	return 0;
-}
-
-/* ------------------------------------------------------------------ */
-
-/* Below are all the private functions that no one else needs */
-
-static int galbrg_set_CDV (int channel, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp &= 0xFFFF0000;
-	temp |= (value & 0x0000FFFF);
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galbrg_enable (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp |= 0x00010000;
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galbrg_disable (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp &= 0xFFFEFFFF;
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galbrg_set_clksrc (int channel, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp &= 0xFFC3FFFF;	/* Bit 18 - 21 (MV 64260 18-22) */
-	temp |= (value << 18);
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-	return 0;
-}
-
-static int galbrg_set_CUV (int channel, int value)
-{
-	/* set CountUpValue */
-	GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
-
-	return 0;
-}
-
-#if 0
-static int galbrg_reset (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp |= 0x20000;
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
-	return 0;
-}
-#endif
-
-static int galsdma_set_RFT (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp |= 0x00000001;
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_SFM (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp |= 0x00000002;
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_rxle (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp |= 0x00000040;
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_txle (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp |= 0x00000080;
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_RC (int channel, unsigned int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp &= ~0x0000003c;
-	temp |= (value << 2);
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_burstsize (int channel, unsigned int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp &= 0xFFFFCFFF;
-	switch (value) {
-	case 8:
-		GT_REG_WRITE (GALSDMA_0_CONF_REG +
-			      (channel * GALSDMA_REG_DIFF),
-			      (temp | (0x3 << 12)));
-		break;
-
-	case 4:
-		GT_REG_WRITE (GALSDMA_0_CONF_REG +
-			      (channel * GALSDMA_REG_DIFF),
-			      (temp | (0x2 << 12)));
-		break;
-
-	case 2:
-		GT_REG_WRITE (GALSDMA_0_CONF_REG +
-			      (channel * GALSDMA_REG_DIFF),
-			      (temp | (0x1 << 12)));
-		break;
-
-	case 1:
-		GT_REG_WRITE (GALSDMA_0_CONF_REG +
-			      (channel * GALSDMA_REG_DIFF),
-			      (temp | (0x0 << 12)));
-		break;
-
-	default:
-		return -1;
-		break;
-	}
-
-	return 0;
-}
-
-static int galmpsc_connect (int channel, int connect)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
-
-	if ((channel == 0) && connect)
-		temp &= ~0x00000007;
-	else if ((channel == 1) && connect)
-		temp &= ~(0x00000007 << 6);
-	else if ((channel == 0) && !connect)
-		temp |= 0x00000007;
-	else
-		temp |= (0x00000007 << 6);
-
-	/* Just in case... */
-	temp &= 0x3fffffff;
-
-	GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
-
-	return 0;
-}
-
-static int galmpsc_route_rx_clock (int channel, int brg)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_RxC_ROUTE);
-
-	if (channel == 0) {
-		temp &= ~0x0000000F;
-		temp |= brg;
-	} else {
-		temp &= ~0x00000F00;
-		temp |= (brg << 8);
-	}
-
-	GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
-
-	return 0;
-}
-
-static int galmpsc_route_tx_clock (int channel, int brg)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_TxC_ROUTE);
-
-	if (channel == 0) {
-		temp &= ~0x0000000F;
-		temp |= brg;
-	} else {
-		temp &= ~0x00000F00;
-		temp |= (brg << 8);
-	}
-
-	GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
-
-	return 0;
-}
-
-static int galmpsc_write_config_regs (int mpsc, int mode)
-{
-	if (mode == GALMPSC_UART) {
-		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
-		GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
-			      0x000004c4);
-
-		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
-		GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
-			      0x024003f8);
-		/*        22 2222 1111 */
-		/*        54 3210 9876 */
-		/* 0000 0010 0000 0000 */
-		/*       1 */
-		/*       098 7654 3210 */
-		/* 0000 0011 1111 1000 */
-	} else
-		return -1;
-
-	return 0;
-}
-
-static int galmpsc_config_channel_regs (int mpsc)
-{
-	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
-
-	galmpsc_set_brkcnt (mpsc, 0x3);
-	galmpsc_set_tcschar (mpsc, 0xab);
-
-	return 0;
-}
-
-static int galmpsc_set_brkcnt (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
-	temp &= 0x0000FFFF;
-	temp |= (value << 16);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_set_tcschar (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
-	temp &= 0xFFFF0000;
-	temp |= value;
-	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_set_char_length (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
-	temp &= 0xFFFFCFFF;
-	temp |= (value << 12);
-	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_set_stop_bit_length (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
-	temp &= 0xFFFFBFFF;
-	temp |= (value << 14);
-	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_set_parity (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
-	if (value != -1) {
-		temp &= 0xFFF3FFF3;
-		temp |= ((value << 18) | (value << 2));
-		temp |= ((value << 17) | (value << 1));
-	} else {
-		temp &= 0xFFF1FFF1;
-	}
-
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_enter_hunt (int mpsc)
-{
-	int temp;
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
-	temp |= 0x80000000;
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
-	       MPSC_ENTER_HUNT) {
-		udelay (1);
-	}
-	return 0;
-}
-
-
-static int galmpsc_shutdown (int mpsc)
-{
-	unsigned int temp;
-
-	/* cause RX abort (clears RX) */
-	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
-	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
-	temp &= ~MPSC_ENTER_HUNT;
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
-	GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
-
-	/* shut down the MPSC */
-	GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
-	GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
-	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
-
-	udelay (100);
-
-	/* shut down the sdma engines. */
-	/* reset config to default */
-	GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
-
-	udelay (100);
-
-	/* clear the SDMA current and first TX and RX pointers */
-	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
-	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
-	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
-
-	udelay (100);
-
-	return 0;
-}
-
-static void galsdma_enable_rx (void)
-{
-	int temp;
-
-	/* Enable RX processing */
-	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
-	temp |= RX_ENABLE;
-	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
-
-	galmpsc_enter_hunt (CHANNEL);
-}
-
-static int galmpsc_set_snoop (int mpsc, int value)
-{
-	int reg =
-		mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
-		MPSC_0_ADDRESS_CONTROL_LOW;
-	int temp = GTREGREAD (reg);
-
-	if (value)
-		temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
-	else
-		temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
-	GT_REG_WRITE (reg, temp);
-	return 0;
-}
-
-/*******************************************************************************
-* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map.
-*
-* DESCRIPTION:
-*       the MV64360 SDMA has its own address decoding map that is de-coupled
-*       from the CPU interface address decoding windows. The SDMA channels
-*       share four address windows. Each region can be individually configured
-*       by this function by associating it to a target interface and setting
-*       base and size values.
-*
-*      NOTE!!!
-*       The size must be in 64Kbyte granularity.
-*       The base address must be aligned to the size.
-*       The size must be a series of 1s followed by a series of zeros
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       true for success, false otherwise.
-*
-*******************************************************************************/
-
-static int galsdma_set_mem_space (unsigned int memSpace,
-				  unsigned int memSpaceTarget,
-				  unsigned int memSpaceAttr,
-				  unsigned int baseAddress, unsigned int size)
-{
-	unsigned int temp;
-
-	if (size == 0) {
-		GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
-				   1 << memSpace);
-		return true;
-	}
-
-	/* The base address must be aligned to the size.  */
-	if (baseAddress % size != 0) {
-		return false;
-	}
-	if (size < 0x10000) {
-		return false;
-	}
-
-	/* Align size and base to 64K */
-	baseAddress &= 0xffff0000;
-	size &= 0xffff0000;
-	temp = size >> 16;
-
-	/* Checking that the size is a sequence of '1' followed by a
-	   sequence of '0' starting from LSB to MSB. */
-	while ((temp > 0) && (temp & 0x1)) {
-		temp = temp >> 1;
-	}
-
-	if (temp != 0) {
-		GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
-			      (baseAddress | memSpaceTarget | memSpaceAttr));
-		GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8),
-			      (size - 1) & 0xffff0000);
-		GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
-				   1 << memSpace);
-	} else {
-		/* An invalid size was specified */
-		return false;
-	}
-	return true;
-}
diff --git a/board/Marvell/db64360/mpsc.h b/board/Marvell/db64360/mpsc.h
deleted file mode 100644
index ca1e89a6f6a..00000000000
--- a/board/Marvell/db64360/mpsc.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*************************************************************************
- * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
-  ************************************************************************/
-
-
-/*
- * mpsc.h - header file for MPSC in uart mode (console driver)
- */
-
-#ifndef __MPSC_H__
-#define __MPSC_H__
-
-/* include actual Galileo defines */
-#include "../include/mv_gen_reg.h"
-
-/* driver related defines */
-
-int mpsc_init(int baud);
-void mpsc_sdma_init(void);
-void mpsc_init2(void);
-int galbrg_set_baudrate(int channel, int rate);
-
-int mpsc_putchar_early(char ch);
-char mpsc_getchar_debug(void);
-int mpsc_test_char_debug(void);
-
-int mpsc_test_char_sdma(void);
-
-extern int (*mpsc_putchar)(char ch);
-extern char (*mpsc_getchar)(void);
-extern int (*mpsc_test_char)(void);
-
-#define CHANNEL CONFIG_MPSC_PORT
-
-#define TX_DESC     5
-#define RX_DESC     20
-
-#define DESC_FIRST  0x00010000
-#define DESC_LAST   0x00020000
-#define DESC_OWNER_BIT  0x80000000
-
-#define TX_DEMAND   0x00800000
-#define TX_STOP     0x00010000
-#define RX_ENABLE   0x00000080
-
-#define SDMA_RX_ABORT		  (1 << 15)
-#define SDMA_TX_ABORT		  (1 << 31)
-#define MPSC_TX_ABORT		  (1 << 7)
-#define MPSC_RX_ABORT             (1 << 23)
-#define MPSC_ENTER_HUNT           (1 << 31)
-
-/* MPSC defines */
-
-#define GALMPSC_CONNECT            0x1
-#define GALMPSC_DISCONNECT         0x0
-
-#define GALMPSC_UART               0x1
-
-#define GALMPSC_STOP_BITS_1        0x0
-#define GALMPSC_STOP_BITS_2        0x1
-#define GALMPSC_CHAR_LENGTH_8      0x3
-#define GALMPSC_CHAR_LENGTH_7      0x2
-
-#define GALMPSC_PARITY_ODD         0x0
-#define GALMPSC_PARITY_EVEN        0x2
-#define GALMPSC_PARITY_MARK        0x3
-#define GALMPSC_PARITY_SPACE       0x1
-#define GALMPSC_PARITY_NONE        -1
-
-#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
-#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
-#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
-#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
-#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
-#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
-#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
-
-#define GALMPSC_REG_GAP            0x1000
-
-#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
-#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
-#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
-#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
-#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
-#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
-#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
-#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
-#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
-#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
-#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
-#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
-
-#define GALSDMA_COMMAND_FIRST     (1 << 16)
-#define GALSDMA_COMMAND_LAST      (1 << 17)
-#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
-#define GALSDMA_COMMAND_AUTO      (1 << 30)
-#define GALSDMA_COMMAND_OWNER     (1 << 31)
-
-#define GALSDMA_RX                 0
-#define GALSDMA_TX                 1
-
-/* CHANNEL2 should be CHANNEL1, according to documentation,
- * but to work with the current GTREGS file...
- */
-#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
-#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
-#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
-#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
-#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
-#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
-#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
-#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
-#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
-#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
-#define GALSDMA_REG_DIFF           0x2000
-
-/* WRONG in gt64260R.h */
-#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
-#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
-#define GALMPSC_0_INT_CAUSE        0xb804
-#define GALMPSC_0_INT_MASK         0xb884
-
-#define GALSDMA_MODE_UART          0
-#define GALSDMA_MODE_BISYNC        1
-#define GALSDMA_MODE_HDLC          2
-#define GALSDMA_MODE_TRANSPARENT   3
-
-#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
-#define GALBRG_REG_GAP             0x0008
-#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
-
-#endif /* __MPSC_H__ */
diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c
deleted file mode 100644
index b2df1f743d4..00000000000
--- a/board/Marvell/db64360/mv_eth.c
+++ /dev/null
@@ -1,3128 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * mv_eth.c - header file for the polled mode GT ethernet driver
- */
-#include <common.h>
-#include <net.h>
-#include <malloc.h>
-
-#include "mv_eth.h"
-
-/* enable Debug outputs */
-
-#undef DEBUG_MV_ETH
-
-#ifdef DEBUG_MV_ETH
-#define DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-#undef MV64360_CHECKSUM_OFFLOAD
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The first part is the high level driver of the gigE ethernet ports.   *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-
-/* Definition for configuring driver */
-/* #define UPDATE_STATS_BY_SOFTWARE */
-#undef MV64360_RX_QUEUE_FILL_ON_TASK
-
-
-/* Constants */
-#define MAGIC_ETH_RUNNING		8031971
-#define MV64360_INTERNAL_SRAM_SIZE                      _256K
-#define EXTRA_BYTES 32
-#define WRAP       ETH_HLEN + 2 + 4 + 16
-#define BUFFER_MTU dev->mtu + WRAP
-#define INT_CAUSE_UNMASK_ALL		0x0007ffff
-#define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
-#ifdef MV64360_RX_FILL_ON_TASK
-#define INT_CAUSE_MASK_ALL		0x00000000
-#define INT_CAUSE_CHECK_BITS		INT_CAUSE_UNMASK_ALL
-#define INT_CAUSE_CHECK_BITS_EXT	INT_CAUSE_UNMASK_ALL_EXT
-#endif
-
-/* Read/Write to/from MV64360 internal registers */
-#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
-#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
-#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
-#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
-
-/* Static function declarations */
-static int mv64360_eth_real_open (struct eth_device *eth);
-static int mv64360_eth_real_stop (struct eth_device *eth);
-static struct net_device_stats *mv64360_eth_get_stats (struct eth_device
-						       *dev);
-static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
-static void mv64360_eth_update_stat (struct eth_device *dev);
-bool db64360_eth_start (struct eth_device *eth);
-unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
-				   unsigned int mib_offset);
-int mv64360_eth_receive (struct eth_device *dev);
-
-int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
-
-#ifndef  UPDATE_STATS_BY_SOFTWARE
-static void mv64360_eth_print_stat (struct eth_device *dev);
-#endif
-
-extern unsigned int INTERNAL_REG_BASE_ADDR;
-
-/*************************************************
- *Helper functions - used inside the driver only *
- *************************************************/
-#ifdef DEBUG_MV_ETH
-void print_globals (struct eth_device *dev)
-{
-	printf ("Ethernet PRINT_Globals-Debug function\n");
-	printf ("Base Address for ETH_PORT_INFO:	%08x\n",
-		(unsigned int) dev->priv);
-	printf ("Base Address for mv64360_eth_priv:	%08x\n",
-		(unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
-				 port_private));
-
-	printf ("GT Internal Base Address:	%08x\n",
-		INTERNAL_REG_BASE_ADDR);
-	printf ("Base Address for TX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE);
-	printf ("Base Address for RX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE);
-	printf ("Base Address for RX-Buffer:	%08x	allocated Bytes %d\n",
-		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
-		p_rx_buffer_base[0],
-		(MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32);
-	printf ("Base Address for TX-Buffer:	%08x	allocated Bytes %d\n",
-		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
-		p_tx_buffer_base[0],
-		(MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32);
-}
-#endif
-
-#define my_cpu_to_le32(x) my_le32_to_cpu((x))
-
-unsigned long my_le32_to_cpu (unsigned long x)
-{
-	return (((x & 0x000000ffU) << 24) |
-		((x & 0x0000ff00U) << 8) |
-		((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
-}
-
-
-/**********************************************************************
- * mv64360_eth_print_phy_status
- *
- * Prints gigabit ethenret phy status
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64360_eth_print_phy_status (struct eth_device *dev)
-{
-	struct mv64360_eth_priv *port_private;
-	unsigned int port_num;
-	ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	unsigned int port_status, phy_reg_data;
-
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-	/* Check Link status on phy */
-	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
-	if (!(phy_reg_data & 0x20)) {
-		printf ("Ethernet port changed link status to DOWN\n");
-	} else {
-		port_status =
-			MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
-		printf ("Ethernet status port %d: Link up", port_num);
-		printf (", %s",
-			(port_status & BIT2) ? "Full Duplex" : "Half Duplex");
-		if (port_status & BIT4)
-			printf (", Speed 1 Gbps");
-		else
-			printf (", %s",
-				(port_status & BIT5) ? "Speed 100 Mbps" :
-				"Speed 10 Mbps");
-		printf ("\n");
-	}
-}
-
-/**********************************************************************
- * u-boot entry functions for mv64360_eth
- *
- **********************************************************************/
-int db64360_eth_probe (struct eth_device *dev)
-{
-	return ((int) db64360_eth_start (dev));
-}
-
-int db64360_eth_poll (struct eth_device *dev)
-{
-	return mv64360_eth_receive (dev);
-}
-
-int db64360_eth_transmit(struct eth_device *dev, void *packet, int length)
-{
-	mv64360_eth_xmit (dev, packet, length);
-	return 0;
-}
-
-void db64360_eth_disable (struct eth_device *dev)
-{
-	mv64360_eth_stop (dev);
-}
-
-
-void mv6436x_eth_initialize (bd_t * bis)
-{
-	struct eth_device *dev;
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	int devnum, x, temp;
-	char *s, *e, buf[64];
-
-	for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
-		dev = calloc (sizeof (*dev), 1);
-		if (!dev) {
-			printf ("%s: mv_enet%d allocation failure, %s\n",
-				__FUNCTION__, devnum, "eth_device structure");
-			return;
-		}
-
-		/* must be less than sizeof(dev->name) */
-		sprintf (dev->name, "mv_enet%d", devnum);
-
-#ifdef DEBUG
-		printf ("Initializing %s\n", dev->name);
-#endif
-
-		/* Extract the MAC address from the environment */
-		switch (devnum) {
-		case 0:
-			s = "ethaddr";
-			break;
-
-		case 1:
-			s = "eth1addr";
-			break;
-
-		case 2:
-			s = "eth2addr";
-			break;
-
-		default:	/* this should never happen */
-			printf ("%s: Invalid device number %d\n",
-				__FUNCTION__, devnum);
-			return;
-		}
-
-		temp = getenv_f(s, buf, sizeof (buf));
-		s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
-		printf ("Setting MAC %d to %s\n", devnum, s);
-#endif
-		for (x = 0; x < 6; ++x) {
-			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
-			if (s)
-				s = (*e) ? e + 1 : e;
-		}
-		/* ronen - set the MAC addr in the HW */
-		eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
-
-		dev->init = (void *) db64360_eth_probe;
-		dev->halt = (void *) ethernet_phy_reset;
-		dev->send = (void *) db64360_eth_transmit;
-		dev->recv = (void *) db64360_eth_poll;
-
-		ethernet_private = calloc (sizeof (*ethernet_private), 1);
-		dev->priv = (void *) ethernet_private;
-
-		if (!ethernet_private) {
-			printf ("%s: %s allocation failure, %s\n",
-				__FUNCTION__, dev->name,
-				"Private Device Structure");
-			free (dev);
-			return;
-		}
-		/* start with an zeroed ETH_PORT_INFO */
-		memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
-		memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
-
-		/* set pointer to memory for stats data structure etc... */
-		port_private = calloc (sizeof (*ethernet_private), 1);
-		ethernet_private->port_private = (void *)port_private;
-		if (!port_private) {
-			printf ("%s: %s allocation failure, %s\n",
-				__FUNCTION__, dev->name,
-				"Port Private Device Structure");
-
-			free (ethernet_private);
-			free (dev);
-			return;
-		}
-
-		port_private->stats =
-			calloc (sizeof (struct net_device_stats), 1);
-		if (!port_private->stats) {
-			printf ("%s: %s allocation failure, %s\n",
-				__FUNCTION__, dev->name,
-				"Net stat Structure");
-
-			free (port_private);
-			free (ethernet_private);
-			free (dev);
-			return;
-		}
-		memset (ethernet_private->port_private, 0,
-			sizeof (struct mv64360_eth_priv));
-		switch (devnum) {
-		case 0:
-			ethernet_private->port_num = ETH_0;
-			break;
-		case 1:
-			ethernet_private->port_num = ETH_1;
-			break;
-		case 2:
-			ethernet_private->port_num = ETH_2;
-			break;
-		default:
-			printf ("Invalid device number %d\n", devnum);
-			break;
-		};
-
-		port_private->port_num = devnum;
-		/*
-		 * Read MIB counter on the GT in order to reset them,
-		 * then zero all the stats fields in memory
-		 */
-		mv64360_eth_update_stat (dev);
-		memset (port_private->stats, 0,
-			sizeof (struct net_device_stats));
-		/* Extract the MAC address from the environment */
-		switch (devnum) {
-		case 0:
-			s = "ethaddr";
-			break;
-
-		case 1:
-			s = "eth1addr";
-			break;
-
-		case 2:
-			s = "eth2addr";
-			break;
-
-		default:	/* this should never happen */
-			printf ("%s: Invalid device number %d\n",
-				__FUNCTION__, devnum);
-			return;
-		}
-
-		temp = getenv_f(s, buf, sizeof (buf));
-		s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
-		printf ("Setting MAC %d to %s\n", devnum, s);
-#endif
-		for (x = 0; x < 6; ++x) {
-			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
-			if (s)
-				s = (*e) ? e + 1 : e;
-		}
-
-		DP (printf ("Allocating descriptor and buffer rings\n"));
-
-		ethernet_private->p_rx_desc_area_base[0] =
-			(ETH_RX_DESC *) memalign (16,
-						  RX_DESC_ALIGNED_SIZE *
-						  MV64360_RX_QUEUE_SIZE + 1);
-		ethernet_private->p_tx_desc_area_base[0] =
-			(ETH_TX_DESC *) memalign (16,
-						  TX_DESC_ALIGNED_SIZE *
-						  MV64360_TX_QUEUE_SIZE + 1);
-
-		ethernet_private->p_rx_buffer_base[0] =
-			(char *) memalign (16,
-					   MV64360_RX_QUEUE_SIZE *
-					   MV64360_TX_BUFFER_SIZE + 1);
-		ethernet_private->p_tx_buffer_base[0] =
-			(char *) memalign (16,
-					   MV64360_RX_QUEUE_SIZE *
-					   MV64360_TX_BUFFER_SIZE + 1);
-
-#ifdef DEBUG_MV_ETH
-		/* DEBUG OUTPUT prints adresses of globals */
-		print_globals (dev);
-#endif
-		eth_register (dev);
-
-	}
-	DP (printf ("%s: exit\n", __FUNCTION__));
-
-}
-
-/**********************************************************************
- * mv64360_eth_open
- *
- * This function is called when openning the network device. The function
- * should initialize all the hardware, initialize cyclic Rx/Tx
- * descriptors chain and buffers and allocate an IRQ to the network
- * device.
- *
- * Input : a pointer to the network device structure
- * / / ronen - changed the output to match  net/eth.c needs
- * Output : nonzero of success , zero if fails.
- * under construction
- **********************************************************************/
-
-int mv64360_eth_open (struct eth_device *dev)
-{
-	return (mv64360_eth_real_open (dev));
-}
-
-/* Helper function for mv64360_eth_open */
-static int mv64360_eth_real_open (struct eth_device *dev)
-{
-
-	unsigned int queue;
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	unsigned int port_num;
-	u32 phy_reg_data;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	/* ronen - when we update the MAC env params we only update dev->enetaddr
-	   see ./net/eth.c eth_set_enetaddr() */
-	memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
-
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-	/* Stop RX Queues */
-	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
-		      0x0000ff00);
-
-	/* Clear the ethernet port interrupts */
-	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
-	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
-
-	/* Unmask RX buffer and TX end interrupt */
-	MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num),
-		      INT_CAUSE_UNMASK_ALL);
-
-	/* Unmask phy and link status changes interrupts */
-	MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
-		      INT_CAUSE_UNMASK_ALL_EXT);
-
-	/* Set phy address of the port */
-	ethernet_private->port_phy_addr = 0x8 + port_num;
-
-	/* Activate the DMA channels etc */
-	eth_port_init (ethernet_private);
-
-
-	/* "Allocate" setup TX rings */
-
-	for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
-		unsigned int size;
-
-		port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE;
-		size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE);	/*size = no of DESCs times DESC-size */
-		ethernet_private->tx_desc_area_size[queue] = size;
-
-		/* first clear desc area completely */
-		memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
-			0, ethernet_private->tx_desc_area_size[queue]);
-
-		/* initialize tx desc ring with low level driver */
-		if (ether_init_tx_desc_ring
-		    (ethernet_private, ETH_Q0,
-		     port_private->tx_ring_size[queue],
-		     MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
-		     (unsigned int) ethernet_private->
-		     p_tx_desc_area_base[queue],
-		     (unsigned int) ethernet_private->
-		     p_tx_buffer_base[queue]) == false)
-			printf ("### Error initializing TX Ring\n");
-	}
-
-	/* "Allocate" setup RX rings */
-	for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
-		unsigned int size;
-
-		/* Meantime RX Ring are fixed - but must be configurable by user */
-		port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE;
-		size = (port_private->rx_ring_size[queue] *
-			RX_DESC_ALIGNED_SIZE);
-		ethernet_private->rx_desc_area_size[queue] = size;
-
-		/* first clear desc area completely */
-		memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
-			0, ethernet_private->rx_desc_area_size[queue]);
-		if ((ether_init_rx_desc_ring
-		     (ethernet_private, ETH_Q0,
-		      port_private->rx_ring_size[queue],
-		      MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
-		      (unsigned int) ethernet_private->
-		      p_rx_desc_area_base[queue],
-		      (unsigned int) ethernet_private->
-		      p_rx_buffer_base[queue])) == false)
-			printf ("### Error initializing RX Ring\n");
-	}
-
-	eth_port_start (ethernet_private);
-
-	/* Set maximum receive buffer to 9700 bytes */
-	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num),
-		      (0x5 << 17) |
-		      (MV_REG_READ
-		       (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num))
-		       & 0xfff1ffff));
-
-	/*
-	 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
-	 * disable the leaky bucket mechanism .
-	 */
-
-	MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
-	MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
-
-	/* Check Link status on phy */
-	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
-	if (!(phy_reg_data & 0x20)) {
-		/* Reset PHY */
-		if ((ethernet_phy_reset (port_num)) != true) {
-			printf ("$$ Warnning: No link on port %d \n",
-				port_num);
-			return 0;
-		} else {
-			eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
-			if (!(phy_reg_data & 0x20)) {
-				printf ("### Error: Phy is not active\n");
-				return 0;
-			}
-		}
-	} else {
-		mv64360_eth_print_phy_status (dev);
-	}
-	port_private->eth_running = MAGIC_ETH_RUNNING;
-	return 1;
-}
-
-
-static int mv64360_eth_free_tx_rings (struct eth_device *dev)
-{
-	unsigned int queue;
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	unsigned int port_num;
-	volatile ETH_TX_DESC *p_tx_curr_desc;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-	/* Stop Tx Queues */
-	MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
-		      0x0000ff00);
-
-	/* Free TX rings */
-	DP (printf ("Clearing previously allocated TX queues... "));
-	for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
-		/* Free on TX rings */
-		for (p_tx_curr_desc =
-		     ethernet_private->p_tx_desc_area_base[queue];
-		     ((unsigned int) p_tx_curr_desc <= (unsigned int)
-		      ethernet_private->p_tx_desc_area_base[queue] +
-		      ethernet_private->tx_desc_area_size[queue]);
-		     p_tx_curr_desc =
-		     (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
-				      TX_DESC_ALIGNED_SIZE)) {
-			/* this is inside for loop */
-			if (p_tx_curr_desc->return_info != 0) {
-				p_tx_curr_desc->return_info = 0;
-				DP (printf ("freed\n"));
-			}
-		}
-		DP (printf ("Done\n"));
-	}
-	return 0;
-}
-
-static int mv64360_eth_free_rx_rings (struct eth_device *dev)
-{
-	unsigned int queue;
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	unsigned int port_num;
-	volatile ETH_RX_DESC *p_rx_curr_desc;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-
-	/* Stop RX Queues */
-	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
-		      0x0000ff00);
-
-	/* Free RX rings */
-	DP (printf ("Clearing previously allocated RX queues... "));
-	for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
-		/* Free preallocated skb's on RX rings */
-		for (p_rx_curr_desc =
-		     ethernet_private->p_rx_desc_area_base[queue];
-		     (((unsigned int) p_rx_curr_desc <
-		       ((unsigned int) ethernet_private->
-			p_rx_desc_area_base[queue] +
-			ethernet_private->rx_desc_area_size[queue])));
-		     p_rx_curr_desc =
-		     (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
-				      RX_DESC_ALIGNED_SIZE)) {
-			if (p_rx_curr_desc->return_info != 0) {
-				p_rx_curr_desc->return_info = 0;
-				DP (printf ("freed\n"));
-			}
-		}
-		DP (printf ("Done\n"));
-	}
-	return 0;
-}
-
-/**********************************************************************
- * mv64360_eth_stop
- *
- * This function is used when closing the network device.
- * It updates the hardware,
- * release all memory that holds buffers and descriptors and release the IRQ.
- * Input : a pointer to the device structure
- * Output : zero if success , nonzero if fails
- *********************************************************************/
-
-int mv64360_eth_stop (struct eth_device *dev)
-{
-	/* Disable all gigE address decoder */
-	MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
-	DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
-	mv64360_eth_real_stop (dev);
-
-	return 0;
-};
-
-/* Helper function for mv64360_eth_stop */
-
-static int mv64360_eth_real_stop (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	unsigned int port_num;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-
-	mv64360_eth_free_tx_rings (dev);
-	mv64360_eth_free_rx_rings (dev);
-
-	eth_port_reset (ethernet_private->port_num);
-	/* Disable ethernet port interrupts */
-	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
-	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
-	/* Mask RX buffer and TX end interrupt */
-	MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0);
-	/* Mask phy and link status changes interrupts */
-	MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
-	MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH,
-			   BIT0 << port_num);
-	/* Print Network statistics */
-#ifndef  UPDATE_STATS_BY_SOFTWARE
-	/*
-	 * Print statistics (only if ethernet is running),
-	 * then zero all the stats fields in memory
-	 */
-	if (port_private->eth_running == MAGIC_ETH_RUNNING) {
-		port_private->eth_running = 0;
-		mv64360_eth_print_stat (dev);
-	}
-	memset (port_private->stats, 0, sizeof (struct net_device_stats));
-#endif
-	DP (printf ("\nEthernet stopped ... \n"));
-	return 0;
-}
-
-
-/**********************************************************************
- * mv64360_eth_start_xmit
- *
- * This function is queues a packet in the Tx descriptor for
- * required port.
- *
- * Input : skb - a pointer to socket buffer
- *         dev - a pointer to the required port
- *
- * Output : zero upon success
- **********************************************************************/
-
-int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
-		      int dataSize)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	PKT_INFO pkt_info;
-	ETH_FUNC_RET_STATUS status;
-	struct net_device_stats *stats;
-	ETH_FUNC_RET_STATUS release_result;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-
-	stats = port_private->stats;
-
-	/* Update packet info data structure */
-	pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;	/* DMA owned, first last */
-	pkt_info.byte_cnt = dataSize;
-	pkt_info.buf_ptr = (unsigned int) dataPtr;
-	pkt_info.return_info = 0;
-
-	status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
-	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
-		printf ("Error on transmitting packet ..");
-		if (status == ETH_QUEUE_FULL)
-			printf ("ETH Queue is full. \n");
-		if (status == ETH_QUEUE_LAST_RESOURCE)
-			printf ("ETH Queue: using last available resource. \n");
-		goto error;
-	}
-
-	/* Update statistics and start of transmittion time */
-	stats->tx_bytes += dataSize;
-	stats->tx_packets++;
-
-	/* Check if packet(s) is(are) transmitted correctly (release everything) */
-	do {
-		release_result =
-			eth_tx_return_desc (ethernet_private, ETH_Q0,
-					    &pkt_info);
-		switch (release_result) {
-		case ETH_OK:
-			DP (printf ("descriptor released\n"));
-			if (pkt_info.cmd_sts & BIT0) {
-				printf ("Error in TX\n");
-				stats->tx_errors++;
-
-			}
-			break;
-		case ETH_RETRY:
-			DP (printf ("transmission still in process\n"));
-			break;
-
-		case ETH_ERROR:
-			printf ("routine can not access Tx desc ring\n");
-			break;
-
-		case ETH_END_OF_JOB:
-			DP (printf ("the routine has nothing to release\n"));
-			break;
-		default:	/* should not happen */
-			break;
-		}
-	} while (release_result == ETH_OK);
-
-
-	return 0;		/* success */
-      error:
-	return 1;		/* Failed - higher layers will free the skb */
-}
-
-/**********************************************************************
- * mv64360_eth_receive
- *
- * This function is forward packets that are received from the port's
- * queues toward kernel core or FastRoute them to another interface.
- *
- * Input : dev - a pointer to the required interface
- *         max - maximum number to receive (0 means unlimted)
- *
- * Output : number of served packets
- **********************************************************************/
-
-int mv64360_eth_receive (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	PKT_INFO pkt_info;
-	struct net_device_stats *stats;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-	stats = port_private->stats;
-
-	while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
-		ETH_OK)) {
-
-#ifdef DEBUG_MV_ETH
-		if (pkt_info.byte_cnt != 0) {
-			printf ("%s: Received %d byte Packet @ 0x%x\n",
-				__FUNCTION__, pkt_info.byte_cnt,
-				pkt_info.buf_ptr);
-		}
-#endif
-		/* Update statistics. Note byte count includes 4 byte CRC count */
-		stats->rx_packets++;
-		stats->rx_bytes += pkt_info.byte_cnt;
-
-		/*
-		 * In case received a packet without first / last bits on OR the error
-		 * summary bit is on, the packets needs to be dropeed.
-		 */
-		if (((pkt_info.
-		      cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
-		     (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
-		    || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
-			stats->rx_dropped++;
-
-			printf ("Received packet spread on multiple descriptors\n");
-
-			/* Is this caused by an error ? */
-			if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
-				stats->rx_errors++;
-			}
-
-			/* free these descriptors again without forwarding them to the higher layers */
-			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
-			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
-
-			if (eth_rx_return_buff
-			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
-				printf ("Error while returning the RX Desc to Ring\n");
-			} else {
-				DP (printf ("RX Desc returned to Ring\n"));
-			}
-			/* /free these descriptors again */
-		} else {
-
-/* !!! call higher layer processing */
-#ifdef DEBUG_MV_ETH
-			printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
-#endif
-			/* let the upper layer handle the packet */
-			NetReceive ((uchar *) pkt_info.buf_ptr,
-				    (int) pkt_info.byte_cnt);
-
-/* **************************************************************** */
-/* free descriptor  */
-			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
-			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
-			DP (printf
-			    ("RX: pkt_info.buf_ptr =	%x\n",
-			     pkt_info.buf_ptr));
-			if (eth_rx_return_buff
-			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
-				printf ("Error while returning the RX Desc to Ring\n");
-			} else {
-				DP (printf ("RX Desc returned to Ring\n"));
-			}
-
-/* **************************************************************** */
-
-		}
-	}
-	mv64360_eth_get_stats (dev);	/* update statistics */
-	return 1;
-}
-
-/**********************************************************************
- * mv64360_eth_get_stats
- *
- * Returns a pointer to the interface statistics.
- *
- * Input : dev - a pointer to the required interface
- *
- * Output : a pointer to the interface's statistics
- **********************************************************************/
-
-static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-
-	mv64360_eth_update_stat (dev);
-
-	return port_private->stats;
-}
-
-
-/**********************************************************************
- * mv64360_eth_update_stat
- *
- * Update the statistics structure in the private data structure
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64360_eth_update_stat (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	struct net_device_stats *stats;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-	stats = port_private->stats;
-
-	/* These are false updates */
-	stats->rx_packets += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_FRAMES_RECEIVED);
-	stats->tx_packets += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_FRAMES_SENT);
-	stats->rx_bytes += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
-	/*
-	 * Ideally this should be as follows -
-	 *
-	 *   stats->rx_bytes   += stats->rx_bytes +
-	 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
-	 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
-	 *
-	 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
-	 * is just a dummy read for proper work of the GigE port
-	 */
-	eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
-	stats->tx_bytes += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_OCTETS_SENT_LOW);
-	eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_OCTETS_SENT_HIGH);
-	stats->rx_errors += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_MAC_RECEIVE_ERROR);
-
-	/* Rx dropped is for received packet with CRC error */
-	stats->rx_dropped +=
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_BAD_CRC_EVENT);
-	stats->multicast += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_MULTICAST_FRAMES_RECEIVED);
-	stats->collisions +=
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_COLLISION) +
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_LATE_COLLISION);
-	/* detailed rx errors */
-	stats->rx_length_errors +=
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_UNDERSIZE_RECEIVED)
-		+
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_OVERSIZE_RECEIVED);
-	/* detailed tx errors */
-}
-
-#ifndef  UPDATE_STATS_BY_SOFTWARE
-/**********************************************************************
- * mv64360_eth_print_stat
- *
- * Update the statistics structure in the private data structure
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64360_eth_print_stat (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	struct net_device_stats *stats;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-	stats = port_private->stats;
-
-	/* These are false updates */
-	printf ("\n### Network statistics: ###\n");
-	printf ("--------------------------\n");
-	printf (" Packets received:		%ld\n", stats->rx_packets);
-	printf (" Packets send:			%ld\n", stats->tx_packets);
-	printf (" Received bytes:		%ld\n", stats->rx_bytes);
-	printf (" Send bytes:			%ld\n", stats->tx_bytes);
-	if (stats->rx_errors != 0)
-		printf (" Rx Errors:			%ld\n",
-			stats->rx_errors);
-	if (stats->rx_dropped != 0)
-		printf (" Rx dropped (CRC Errors):	%ld\n",
-			stats->rx_dropped);
-	if (stats->multicast != 0)
-		printf (" Rx mulicast frames:		%ld\n",
-			stats->multicast);
-	if (stats->collisions != 0)
-		printf (" No. of collisions:		%ld\n",
-			stats->collisions);
-	if (stats->rx_length_errors != 0)
-		printf (" Rx length errors:		%ld\n",
-			stats->rx_length_errors);
-}
-#endif
-
-/**************************************************************************
- *network_start - Network Kick Off Routine UBoot
- *Inputs :
- *Outputs :
- **************************************************************************/
-
-bool db64360_eth_start (struct eth_device *dev)
-{
-	return (mv64360_eth_open (dev));	/* calls real open */
-}
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The second part is the low level driver of the gigE ethernet ports.   *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-/*
- * based on Linux code
- * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/********************************************************************************
- * Marvell's Gigabit Ethernet controller low level driver
- *
- * DESCRIPTION:
- *       This file introduce low level API to Marvell's Gigabit Ethernet
- *		controller. This Gigabit Ethernet Controller driver API controls
- *		1) Operations (i.e. port init, start, reset etc').
- *		2) Data flow (i.e. port send, receive etc').
- *		Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
- *		struct.
- *		This struct includes user configuration information as well as
- *		driver internal data needed for its operations.
- *
- *		Supported Features:
- *		- This low level driver is OS independent. Allocating memory for
- *		  the descriptor rings and buffers are not within the scope of
- *		  this driver.
- *		- The user is free from Rx/Tx queue managing.
- *		- This low level driver introduce functionality API that enable
- *		  the to operate Marvell's Gigabit Ethernet Controller in a
- *		  convenient way.
- *		- Simple Gigabit Ethernet port operation API.
- *		- Simple Gigabit Ethernet port data flow API.
- *		- Data flow and operation API support per queue functionality.
- *		- Support cached descriptors for better performance.
- *		- Enable access to all four DRAM banks and internal SRAM memory
- *		  spaces.
- *		- PHY access and control API.
- *		- Port control register configuration API.
- *		- Full control over Unicast and Multicast MAC configurations.
- *
- *		Operation flow:
- *
- *		Initialization phase
- *		This phase complete the initialization of the ETH_PORT_INFO
- *		struct.
- *		User information regarding port configuration has to be set
- *		prior to calling the port initialization routine. For example,
- *		the user has to assign the port_phy_addr field which is board
- *		depended parameter.
- *		In this phase any port Tx/Rx activity is halted, MIB counters
- *		are cleared, PHY address is set according to user parameter and
- *		access to DRAM and internal SRAM memory spaces.
- *
- *		Driver ring initialization
- *		Allocating memory for the descriptor rings and buffers is not
- *		within the scope of this driver. Thus, the user is required to
- *		allocate memory for the descriptors ring and buffers. Those
- *		memory parameters are used by the Rx and Tx ring initialization
- *		routines in order to curve the descriptor linked list in a form
- *		of a ring.
- *		Note: Pay special attention to alignment issues when using
- *		cached descriptors/buffers. In this phase the driver store
- *		information in the ETH_PORT_INFO struct regarding each queue
- *		ring.
- *
- *		Driver start
- *		This phase prepares the Ethernet port for Rx and Tx activity.
- *		It uses the information stored in the ETH_PORT_INFO struct to
- *		initialize the various port registers.
- *
- *		Data flow:
- *		All packet references to/from the driver are done using PKT_INFO
- *		struct.
- *		This struct is a unified struct used with Rx and Tx operations.
- *		This way the user is not required to be familiar with neither
- *		Tx nor Rx descriptors structures.
- *		The driver's descriptors rings are management by indexes.
- *		Those indexes controls the ring resources and used to indicate
- *		a SW resource error:
- *		'current'
- *		This index points to the current available resource for use. For
- *		example in Rx process this index will point to the descriptor
- *		that will be passed to the user upon calling the receive routine.
- *		In Tx process, this index will point to the descriptor
- *		that will be assigned with the user packet info and transmitted.
- *		'used'
- *		This index points to the descriptor that need to restore its
- *		resources. For example in Rx process, using the Rx buffer return
- *		API will attach the buffer returned in packet info to the
- *		descriptor pointed by 'used'. In Tx process, using the Tx
- *		descriptor return will merely return the user packet info with
- *		the command status of  the transmitted buffer pointed by the
- *		'used' index. Nevertheless, it is essential to use this routine
- *		to update the 'used' index.
- *		'first'
- *		This index supports Tx Scatter-Gather. It points to the first
- *		descriptor of a packet assembled of multiple buffers. For example
- *		when in middle of Such packet we have a Tx resource error the
- *		'curr' index get the value of 'first' to indicate that the ring
- *		returned to its state before trying to transmit this packet.
- *
- *		Receive operation:
- *		The eth_port_receive API set the packet information struct,
- *		passed by the caller, with received information from the
- *		'current' SDMA descriptor.
- *		It is the user responsibility to return this resource back
- *		to the Rx descriptor ring to enable the reuse of this source.
- *		Return Rx resource is done using the eth_rx_return_buff API.
- *
- *		Transmit operation:
- *		The eth_port_send API supports Scatter-Gather which enables to
- *		send a packet spanned over multiple buffers. This means that
- *		for each packet info structure given by the user and put into
- *		the Tx descriptors ring, will be transmitted only if the 'LAST'
- *		bit will be set in the packet info command status field. This
- *		API also consider restriction regarding buffer alignments and
- *		sizes.
- *		The user must return a Tx resource after ensuring the buffer
- *		has been transmitted to enable the Tx ring indexes to update.
- *
- *		BOARD LAYOUT
- *		This device is on-board.  No jumper diagram is necessary.
- *
- *		EXTERNAL INTERFACE
- *
- *       Prior to calling the initialization routine eth_port_init() the user
- *	 must set the following fields under ETH_PORT_INFO struct:
- *       port_num             User Ethernet port number.
- *       port_phy_addr		    User PHY address of Ethernet port.
- *       port_mac_addr[6]	    User defined port MAC address.
- *       port_config          User port configuration value.
- *       port_config_extend    User port config extend value.
- *       port_sdma_config      User port SDMA config value.
- *       port_serial_control   User port serial control value.
- *       *port_virt_to_phys ()  User function to cast virtual addr to CPU bus addr.
- *       *port_private        User scratch pad for user specific data structures.
- *
- *       This driver introduce a set of default values:
- *       PORT_CONFIG_VALUE           Default port configuration value
- *       PORT_CONFIG_EXTEND_VALUE    Default port extend configuration value
- *       PORT_SDMA_CONFIG_VALUE      Default sdma control value
- *       PORT_SERIAL_CONTROL_VALUE   Default port serial control value
- *
- *		This driver data flow is done using the PKT_INFO struct which is
- *		a unified struct for Rx and Tx operations:
- *		byte_cnt	Tx/Rx descriptor buffer byte count.
- *		l4i_chk		CPU provided TCP Checksum. For Tx operation only.
- *		cmd_sts		Tx/Rx descriptor command status.
- *		buf_ptr		Tx/Rx descriptor buffer pointer.
- *		return_info	Tx/Rx user resource return information.
- *
- *
- *		EXTERNAL SUPPORT REQUIREMENTS
- *
- *		This driver requires the following external support:
- *
- *		D_CACHE_FLUSH_LINE (address, address offset)
- *
- *		This macro applies assembly code to flush and invalidate cache
- *		line.
- *		address        - address base.
- *		address offset - address offset
- *
- *
- *		CPU_PIPE_FLUSH
- *
- *		This macro applies assembly code to flush the CPU pipeline.
- *
- *******************************************************************************/
-/* includes */
-
-/* defines */
-/* SDMA command macros */
-#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
- MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
-
-#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
- MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
- (1 << (8 + tx_queue)))
-
-#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
-MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
-
-#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
-MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
-
-#define CURR_RFD_GET(p_curr_desc, queue) \
- ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
-
-#define CURR_RFD_SET(p_curr_desc, queue) \
- (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
-
-#define USED_RFD_GET(p_used_desc, queue) \
- ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
-
-#define USED_RFD_SET(p_used_desc, queue)\
-(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
-
-
-#define CURR_TFD_GET(p_curr_desc, queue) \
- ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
-
-#define CURR_TFD_SET(p_curr_desc, queue) \
- (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
-
-#define USED_TFD_GET(p_used_desc, queue) \
- ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
-
-#define USED_TFD_SET(p_used_desc, queue) \
- (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
-
-#define FIRST_TFD_GET(p_first_desc, queue) \
- ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
-
-#define FIRST_TFD_SET(p_first_desc, queue) \
- (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
-
-
-/* Macros that save access to desc in order to find next desc pointer  */
-#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
-
-#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
-
-#define LINK_UP_TIMEOUT		100000
-#define PHY_BUSY_TIMEOUT    10000000
-
-/* locals */
-
-/* PHY routines */
-static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
-static int ethernet_phy_get (ETH_PORT eth_port_num);
-
-/* Ethernet Port routines */
-static void eth_set_access_control (ETH_PORT eth_port_num,
-				    ETH_WIN_PARAM * param);
-static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
-			      ETH_QUEUE queue, int option);
-#if 0				/* FIXME */
-static bool eth_port_smc_addr (ETH_PORT eth_port_num,
-			       unsigned char mc_byte,
-			       ETH_QUEUE queue, int option);
-static bool eth_port_omc_addr (ETH_PORT eth_port_num,
-			       unsigned char crc8,
-			       ETH_QUEUE queue, int option);
-#endif
-
-static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
-			int byte_count);
-
-void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
-
-
-typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
-u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
-{
-	u32 result = 0;
-	u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
-
-	if (enable & (1 << bank))
-		return 0;
-	if (bank == BANK0)
-		result = MV_REG_READ (MV64360_CS_0_BASE_ADDR);
-	if (bank == BANK1)
-		result = MV_REG_READ (MV64360_CS_1_BASE_ADDR);
-	if (bank == BANK2)
-		result = MV_REG_READ (MV64360_CS_2_BASE_ADDR);
-	if (bank == BANK3)
-		result = MV_REG_READ (MV64360_CS_3_BASE_ADDR);
-	result &= 0x0000ffff;
-	result = result << 16;
-	return result;
-}
-
-u32 mv_get_dram_bank_size (MEMORY_BANK bank)
-{
-	u32 result = 0;
-	u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
-
-	if (enable & (1 << bank))
-		return 0;
-	if (bank == BANK0)
-		result = MV_REG_READ (MV64360_CS_0_SIZE);
-	if (bank == BANK1)
-		result = MV_REG_READ (MV64360_CS_1_SIZE);
-	if (bank == BANK2)
-		result = MV_REG_READ (MV64360_CS_2_SIZE);
-	if (bank == BANK3)
-		result = MV_REG_READ (MV64360_CS_3_SIZE);
-	result += 1;
-	result &= 0x0000ffff;
-	result = result << 16;
-	return result;
-}
-
-u32 mv_get_internal_sram_base (void)
-{
-	u32 result;
-
-	result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR);
-	result &= 0x0000ffff;
-	result = result << 16;
-	return result;
-}
-
-/*******************************************************************************
-* eth_port_init - Initialize the Ethernet port driver
-*
-* DESCRIPTION:
-*       This function prepares the ethernet port to start its activity:
-*       1) Completes the ethernet port driver struct initialization toward port
-*           start routine.
-*       2) Resets the device to a quiescent state in case of warm reboot.
-*       3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
-*       4) Clean MAC tables. The reset status of those tables is unknown.
-*       5) Set PHY address.
-*       Note: Call this routine prior to eth_port_start routine and after setting
-*       user values in the user fields of Ethernet port control struct (i.e.
-*       port_phy_addr).
-*
-* INPUT:
-*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
-*
-* OUTPUT:
-*       See description.
-*
-* RETURN:
-*       None.
-*
-*******************************************************************************/
-static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
-{
-	int queue;
-	ETH_WIN_PARAM win_param;
-
-	p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
-	p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
-	p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
-	p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
-
-	p_eth_port_ctrl->port_rx_queue_command = 0;
-	p_eth_port_ctrl->port_tx_queue_command = 0;
-
-	/* Zero out SW structs */
-	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
-		CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
-		USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
-		p_eth_port_ctrl->rx_resource_err[queue] = false;
-	}
-
-	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
-		CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
-		USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
-		FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
-		p_eth_port_ctrl->tx_resource_err[queue] = false;
-	}
-
-	eth_port_reset (p_eth_port_ctrl->port_num);
-
-	/* Set access parameters for DRAM bank 0 */
-	win_param.win = ETH_WIN0;	/* Use Ethernet window 0 */
-	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR  */
-	win_param.attributes = EBAR_ATTR_DRAM_CS0;	/* Enable DRAM bank   */
-#ifndef CONFIG_NOT_COHERENT_CACHE
-	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
-	win_param.high_addr = 0;
-	/* Get bank base */
-	win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
-	win_param.size = mv_get_dram_bank_size (BANK0);	/* Get bank size */
-	if (win_param.size == 0)
-		win_param.enable = 0;
-	else
-		win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	/* Set access parameters for DRAM bank 1 */
-	win_param.win = ETH_WIN1;	/* Use Ethernet window 1 */
-	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
-	win_param.attributes = EBAR_ATTR_DRAM_CS1;	/* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
-	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
-	win_param.high_addr = 0;
-	/* Get bank base */
-	win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
-	win_param.size = mv_get_dram_bank_size (BANK1);	/* Get bank size */
-	if (win_param.size == 0)
-		win_param.enable = 0;
-	else
-		win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	/* Set access parameters for DRAM bank 2 */
-	win_param.win = ETH_WIN2;	/* Use Ethernet window 2 */
-	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
-	win_param.attributes = EBAR_ATTR_DRAM_CS2;	/* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
-	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
-	win_param.high_addr = 0;
-	/* Get bank base */
-	win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
-	win_param.size = mv_get_dram_bank_size (BANK2);	/* Get bank size */
-	if (win_param.size == 0)
-		win_param.enable = 0;
-	else
-		win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	/* Set access parameters for DRAM bank 3 */
-	win_param.win = ETH_WIN3;	/* Use Ethernet window 3 */
-	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
-	win_param.attributes = EBAR_ATTR_DRAM_CS3;	/* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
-	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
-	win_param.high_addr = 0;
-	/* Get bank base */
-	win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
-	win_param.size = mv_get_dram_bank_size (BANK3);	/* Get bank size */
-	if (win_param.size == 0)
-		win_param.enable = 0;
-	else
-		win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	/* Set access parameters for Internal SRAM */
-	win_param.win = ETH_WIN4;	/* Use Ethernet window 0 */
-	win_param.target = EBAR_TARGET_CBS;	/* Target - Internal SRAM */
-	win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
-	win_param.high_addr = 0;
-	win_param.base_addr = mv_get_internal_sram_base ();	/* Get base addr */
-	win_param.size = MV64360_INTERNAL_SRAM_SIZE;	/* Get bank size */
-	win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
-
-	ethernet_phy_set (p_eth_port_ctrl->port_num,
-			  p_eth_port_ctrl->port_phy_addr);
-
-	return;
-
-}
-
-/*******************************************************************************
-* eth_port_start - Start the Ethernet port activity.
-*
-* DESCRIPTION:
-*       This routine prepares the Ethernet port for Rx and Tx activity:
-*       1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
-*           has been initialized a descriptor's ring (using ether_init_tx_desc_ring
-*           for Tx and ether_init_rx_desc_ring for Rx)
-*       2. Initialize and enable the Ethernet configuration port by writing to
-*           the port's configuration and command registers.
-*       3. Initialize and enable the SDMA by writing to the SDMA's
-*    configuration and command registers.
-*       After completing these steps, the ethernet port SDMA can starts to
-*       perform Rx and Tx activities.
-*
-*       Note: Each Rx and Tx queue descriptor's list must be initialized prior
-*       to calling this function (use ether_init_tx_desc_ring for Tx queues and
-*       ether_init_rx_desc_ring for Rx queues).
-*
-* INPUT:
-*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
-*
-* OUTPUT:
-*       Ethernet port is ready to receive and transmit.
-*
-* RETURN:
-*       false if the port PHY is not up.
-*       true otherwise.
-*
-*******************************************************************************/
-static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
-{
-	int queue;
-	volatile ETH_TX_DESC *p_tx_curr_desc;
-	volatile ETH_RX_DESC *p_rx_curr_desc;
-	unsigned int phy_reg_data;
-	ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
-
-
-	/* Assignment of Tx CTRP of given queue */
-	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
-		CURR_TFD_GET (p_tx_curr_desc, queue);
-		MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
-			       (eth_port_num)
-			       + (4 * queue)),
-			      ((unsigned int) p_tx_curr_desc));
-
-	}
-
-	/* Assignment of Rx CRDP of given queue */
-	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
-		CURR_RFD_GET (p_rx_curr_desc, queue);
-		MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
-			       (eth_port_num)
-			       + (4 * queue)),
-			      ((unsigned int) p_rx_curr_desc));
-
-		if (p_rx_curr_desc != NULL)
-			/* Add the assigned Ethernet address to the port's address table */
-			eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
-					      p_eth_port_ctrl->port_mac_addr,
-					      queue);
-	}
-
-	/* Assign port configuration and command. */
-	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
-		      p_eth_port_ctrl->port_config);
-
-	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
-		      p_eth_port_ctrl->port_config_extend);
-
-	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
-		      p_eth_port_ctrl->port_serial_control);
-
-	MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
-			 ETH_SERIAL_PORT_ENABLE);
-
-	/* Assign port SDMA configuration */
-	MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
-		      p_eth_port_ctrl->port_sdma_config);
-
-	MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
-		      (eth_port_num), 0x3fffffff);
-	MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
-		      (eth_port_num), 0x03fffcff);
-	/* Turn off the port/queue bandwidth limitation */
-	MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
-
-	/* Enable port Rx. */
-	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
-		      p_eth_port_ctrl->port_rx_queue_command);
-
-	/* Check if link is up */
-	eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
-
-	if (!(phy_reg_data & 0x20))
-		return false;
-
-	return true;
-}
-
-/*******************************************************************************
-* eth_port_uc_addr_set - This function Set the port Unicast address.
-*
-* DESCRIPTION:
-*		This function Set the port Ethernet MAC address.
-*
-* INPUT:
-*	ETH_PORT eth_port_num     Port number.
-*	char *        p_addr		Address to be set
-*	ETH_QUEUE	  queue		Rx queue number for this MAC address.
-*
-* OUTPUT:
-*	Set MAC address low and high registers. also calls eth_port_uc_addr()
-*       To set the unicast table with the proper information.
-*
-* RETURN:
-*	N/A.
-*
-*******************************************************************************/
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
-				  unsigned char *p_addr, ETH_QUEUE queue)
-{
-	unsigned int mac_h;
-	unsigned int mac_l;
-
-	mac_l = (p_addr[4] << 8) | (p_addr[5]);
-	mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
-		(p_addr[2] << 8) | (p_addr[3] << 0);
-
-	MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
-	MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
-
-	/* Accept frames of this address */
-	eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
-
-	return;
-}
-
-/*******************************************************************************
-* eth_port_uc_addr - This function Set the port unicast address table
-*
-* DESCRIPTION:
-*	This function locates the proper entry in the Unicast table for the
-*	specified MAC nibble and sets its properties according to function
-*	parameters.
-*
-* INPUT:
-*	ETH_PORT	eth_port_num      Port number.
-*	unsigned char uc_nibble		Unicast MAC Address last nibble.
-*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
-*	int			option      0 = Add, 1 = remove address.
-*
-* OUTPUT:
-*	This function add/removes MAC addresses from the port unicast address
-*	table.
-*
-* RETURN:
-*	true is output succeeded.
-*	false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_uc_addr (ETH_PORT eth_port_num,
-			      unsigned char uc_nibble,
-			      ETH_QUEUE queue, int option)
-{
-	unsigned int unicast_reg;
-	unsigned int tbl_offset;
-	unsigned int reg_offset;
-
-	/* Locate the Unicast table entry */
-	uc_nibble = (0xf & uc_nibble);
-	tbl_offset = (uc_nibble / 4) * 4;	/* Register offset from unicast table base */
-	reg_offset = uc_nibble % 4;	/* Entry offset within the above register */
-
-	switch (option) {
-	case REJECT_MAC_ADDR:
-		/* Clear accepts frame bit at specified unicast DA table entry */
-		unicast_reg =
-			MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
-				      (eth_port_num)
-				      + tbl_offset));
-
-		unicast_reg &= (0x0E << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
-			       (eth_port_num)
-			       + tbl_offset), unicast_reg);
-		break;
-
-	case ACCEPT_MAC_ADDR:
-		/* Set accepts frame bit at unicast DA filter table entry */
-		unicast_reg =
-			MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
-				      (eth_port_num)
-				      + tbl_offset));
-
-		unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
-			       (eth_port_num)
-			       + tbl_offset), unicast_reg);
-
-		break;
-
-	default:
-		return false;
-	}
-	return true;
-}
-
-#if 0				/* FIXME */
-/*******************************************************************************
-* eth_port_mc_addr - Multicast address settings.
-*
-* DESCRIPTION:
-*	This API controls the MV device MAC multicast support.
-*	The MV device supports multicast using two tables:
-*	1) Special Multicast Table for MAC addresses of the form
-*	   0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
-*	   The MAC DA[7:0] bits are used as a pointer to the Special Multicast
-*	   Table entries in the DA-Filter table.
-*	   In this case, the function calls eth_port_smc_addr() routine to set the
-*	   Special Multicast Table.
-*	2) Other Multicast Table for multicast of another type. A CRC-8bit
-*	   is used as an index to the Other Multicast Table entries in the
-*	   DA-Filter table.
-*	   In this case, the function calculates the CRC-8bit value and calls
-*	   eth_port_omc_addr() routine to set the Other Multicast Table.
-* INPUT:
-*	ETH_PORT	eth_port_num      Port number.
-*	unsigned char	*p_addr		Unicast MAC Address.
-*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
-*	int			option      0 = Add, 1 = remove address.
-*
-* OUTPUT:
-*	See description.
-*
-* RETURN:
-*	true is output succeeded.
-*	false if add_address_table_entry( ) failed.
-*
-*******************************************************************************/
-static void eth_port_mc_addr (ETH_PORT eth_port_num,
-			      unsigned char *p_addr,
-			      ETH_QUEUE queue, int option)
-{
-	unsigned int mac_h;
-	unsigned int mac_l;
-	unsigned char crc_result = 0;
-	int mac_array[48];
-	int crc[8];
-	int i;
-
-
-	if ((p_addr[0] == 0x01) &&
-	    (p_addr[1] == 0x00) &&
-	    (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
-
-		eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
-	else {
-		/* Calculate CRC-8 out of the given address */
-		mac_h = (p_addr[0] << 8) | (p_addr[1]);
-		mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
-			(p_addr[4] << 8) | (p_addr[5] << 0);
-
-		for (i = 0; i < 32; i++)
-			mac_array[i] = (mac_l >> i) & 0x1;
-		for (i = 32; i < 48; i++)
-			mac_array[i] = (mac_h >> (i - 32)) & 0x1;
-
-
-		crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
-			mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
-			mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
-			mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
-			mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
-			mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
-			mac_array[6] ^ mac_array[0];
-
-		crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
-			mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
-			mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
-			mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
-			mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
-			mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
-			mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
-			mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
-			mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
-			mac_array[0];
-
-		crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
-			mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
-			mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
-			mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
-			mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
-			mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
-			mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
-			mac_array[2] ^ mac_array[1] ^ mac_array[0];
-
-		crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
-			mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
-			mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
-			mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
-			mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
-			mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
-			mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
-			mac_array[2] ^ mac_array[1];
-
-		crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
-			mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
-			mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
-			mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
-			mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
-			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
-			mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
-			mac_array[2];
-
-		crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
-			mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
-			mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
-			mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
-			mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
-			mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
-			mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
-			mac_array[3];
-
-		crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
-			mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
-			mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
-			mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
-			mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
-			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
-			mac_array[6] ^ mac_array[5] ^ mac_array[4];
-
-		crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
-			mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
-			mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
-			mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
-			mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
-			mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
-			mac_array[6] ^ mac_array[5];
-
-		for (i = 0; i < 8; i++)
-			crc_result = crc_result | (crc[i] << i);
-
-		eth_port_omc_addr (eth_port_num, crc_result, queue, option);
-	}
-	return;
-}
-
-/*******************************************************************************
-* eth_port_smc_addr - Special Multicast address settings.
-*
-* DESCRIPTION:
-*	This routine controls the MV device special MAC multicast support.
-*	The Special Multicast Table for MAC addresses supports MAC of the form
-*	0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
-*	The MAC DA[7:0] bits are used as a pointer to the Special Multicast
-*	Table entries in the DA-Filter table.
-*	This function set the Special Multicast Table appropriate entry
-*	according to the argument given.
-*
-* INPUT:
-*	ETH_PORT	eth_port_num      Port number.
-*	unsigned char	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
-*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
-*	int			option      0 = Add, 1 = remove address.
-*
-* OUTPUT:
-*	See description.
-*
-* RETURN:
-*	true is output succeeded.
-*	false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_smc_addr (ETH_PORT eth_port_num,
-			       unsigned char mc_byte,
-			       ETH_QUEUE queue, int option)
-{
-	unsigned int smc_table_reg;
-	unsigned int tbl_offset;
-	unsigned int reg_offset;
-
-	/* Locate the SMC table entry */
-	tbl_offset = (mc_byte / 4) * 4;	/* Register offset from SMC table base */
-	reg_offset = mc_byte % 4;	/* Entry offset within the above register */
-	queue &= 0x7;
-
-	switch (option) {
-	case REJECT_MAC_ADDR:
-		/* Clear accepts frame bit at specified Special DA table entry */
-		smc_table_reg =
-			MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
-		smc_table_reg &= (0x0E << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
-		break;
-
-	case ACCEPT_MAC_ADDR:
-		/* Set accepts frame bit at specified Special DA table entry */
-		smc_table_reg =
-			MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
-		smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
-		break;
-
-	default:
-		return false;
-	}
-	return true;
-}
-
-/*******************************************************************************
-* eth_port_omc_addr - Multicast address settings.
-*
-* DESCRIPTION:
-*	This routine controls the MV device Other MAC multicast support.
-*	The Other Multicast Table is used for multicast of another type.
-*	A CRC-8bit is used as an index to the Other Multicast Table entries
-*	in the DA-Filter table.
-*	The function gets the CRC-8bit value from the calling routine and
-*      set the Other Multicast Table appropriate entry according to the
-*	CRC-8 argument given.
-*
-* INPUT:
-*	ETH_PORT	eth_port_num      Port number.
-*	unsigned char	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
-*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
-*	int			option      0 = Add, 1 = remove address.
-*
-* OUTPUT:
-*	See description.
-*
-* RETURN:
-*	true is output succeeded.
-*	false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_omc_addr (ETH_PORT eth_port_num,
-			       unsigned char crc8,
-			       ETH_QUEUE queue, int option)
-{
-	unsigned int omc_table_reg;
-	unsigned int tbl_offset;
-	unsigned int reg_offset;
-
-	/* Locate the OMC table entry */
-	tbl_offset = (crc8 / 4) * 4;	/* Register offset from OMC table base */
-	reg_offset = crc8 % 4;	/* Entry offset within the above register */
-	queue &= 0x7;
-
-	switch (option) {
-	case REJECT_MAC_ADDR:
-		/* Clear accepts frame bit at specified Other DA table entry */
-		omc_table_reg =
-			MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
-		omc_table_reg &= (0x0E << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
-		break;
-
-	case ACCEPT_MAC_ADDR:
-		/* Set accepts frame bit at specified Other DA table entry */
-		omc_table_reg =
-			MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
-		omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
-		break;
-
-	default:
-		return false;
-	}
-	return true;
-}
-#endif
-
-/*******************************************************************************
-* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
-*
-* DESCRIPTION:
-*       Go through all the DA filter tables (Unicast, Special Multicast & Other
-*       Multicast) and set each entry to 0.
-*
-* INPUT:
-*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-*       Multicast and Unicast packets are rejected.
-*
-* RETURN:
-*       None.
-*
-*******************************************************************************/
-static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
-{
-	int table_index;
-
-	/* Clear DA filter unicast table (Ex_dFUT) */
-	for (table_index = 0; table_index <= 0xC; table_index += 4)
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
-			       (eth_port_num) + table_index), 0);
-
-	for (table_index = 0; table_index <= 0xFC; table_index += 4) {
-		/* Clear DA filter special multicast table (Ex_dFSMT) */
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
-		/* Clear DA filter other multicast table (Ex_dFOMT) */
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
-	}
-}
-
-/*******************************************************************************
-* eth_clear_mib_counters - Clear all MIB counters
-*
-* DESCRIPTION:
-*       This function clears all MIB counters of a specific ethernet port.
-*       A read from the MIB counter will reset the counter.
-*
-* INPUT:
-*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-*       After reading all MIB counters, the counters resets.
-*
-* RETURN:
-*       MIB counter value.
-*
-*******************************************************************************/
-static void eth_clear_mib_counters (ETH_PORT eth_port_num)
-{
-	int i;
-
-	/* Perform dummy reads from MIB counters */
-	for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
-	     i += 4)
-		MV_REG_READ((MV64360_ETH_MIB_COUNTERS_BASE(eth_port_num) + i));
-
-	return;
-}
-
-/*******************************************************************************
-* eth_read_mib_counter - Read a MIB counter
-*
-* DESCRIPTION:
-*       This function reads a MIB counter of a specific ethernet port.
-*       NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
-*       following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
-*       register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
-*       ETH_MIB_GOOD_OCTETS_SENT_HIGH
-*
-* INPUT:
-*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
-*       unsigned int mib_offset   MIB counter offset (use ETH_MIB_... macros).
-*
-* OUTPUT:
-*       After reading the MIB counter, the counter resets.
-*
-* RETURN:
-*       MIB counter value.
-*
-*******************************************************************************/
-unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
-				   unsigned int mib_offset)
-{
-	return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num)
-			     + mib_offset));
-}
-
-/*******************************************************************************
-* ethernet_phy_set - Set the ethernet port PHY address.
-*
-* DESCRIPTION:
-*       This routine set the ethernet port PHY address according to given
-*       parameter.
-*
-* INPUT:
-*		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-*       Set PHY Address Register with given PHY address parameter.
-*
-* RETURN:
-*       None.
-*
-*******************************************************************************/
-static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
-{
-	unsigned int reg_data;
-
-	reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
-
-	reg_data &= ~(0x1F << (5 * eth_port_num));
-	reg_data |= (phy_addr << (5 * eth_port_num));
-
-	MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data);
-
-	return;
-}
-
-/*******************************************************************************
- * ethernet_phy_get - Get the ethernet port PHY address.
- *
- * DESCRIPTION:
- *       This routine returns the given ethernet port PHY address.
- *
- * INPUT:
- *		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- *       None.
- *
- * RETURN:
- *       PHY address.
- *
- *******************************************************************************/
-static int ethernet_phy_get (ETH_PORT eth_port_num)
-{
-	unsigned int reg_data;
-
-	reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
-
-	return ((reg_data >> (5 * eth_port_num)) & 0x1f);
-}
-
-/*******************************************************************************
- * ethernet_phy_reset - Reset Ethernet port PHY.
- *
- * DESCRIPTION:
- *       This routine utilize the SMI interface to reset the ethernet port PHY.
- *       The routine waits until the link is up again or link up is timeout.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- *       The ethernet port PHY renew its link.
- *
- * RETURN:
- *       None.
- *
-*******************************************************************************/
-static bool ethernet_phy_reset (ETH_PORT eth_port_num)
-{
-	unsigned int time_out = 50;
-	unsigned int phy_reg_data;
-
-	/* Reset the PHY */
-	eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
-	phy_reg_data |= 0x8000;	/* Set bit 15 to reset the PHY */
-	eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
-
-	/* Poll on the PHY LINK */
-	do {
-		eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
-
-		if (time_out-- == 0)
-			return false;
-	}
-	while (!(phy_reg_data & 0x20));
-
-	return true;
-}
-
-/*******************************************************************************
- * eth_port_reset - Reset Ethernet port
- *
- * DESCRIPTION:
- *	This routine resets the chip by aborting any SDMA engine activity and
- *      clearing the MIB counters. The Receiver and the Transmit unit are in
- *      idle state after this command is performed and the port is disabled.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- *       Channel activity is halted.
- *
- * RETURN:
- *       None.
- *
- *******************************************************************************/
-static void eth_port_reset (ETH_PORT eth_port_num)
-{
-	unsigned int reg_data;
-
-	/* Stop Tx port activity. Check port Tx activity. */
-	reg_data =
-		MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
-			     (eth_port_num));
-
-	if (reg_data & 0xFF) {
-		/* Issue stop command for active channels only */
-		MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
-			      (eth_port_num), (reg_data << 8));
-
-		/* Wait for all Tx activity to terminate. */
-		do {
-			/* Check port cause register that all Tx queues are stopped */
-			reg_data =
-				MV_REG_READ
-				(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
-				 (eth_port_num));
-		}
-		while (reg_data & 0xFF);
-	}
-
-	/* Stop Rx port activity. Check port Rx activity. */
-	reg_data =
-		MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
-			     (eth_port_num));
-
-	if (reg_data & 0xFF) {
-		/* Issue stop command for active channels only */
-		MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
-			      (eth_port_num), (reg_data << 8));
-
-		/* Wait for all Rx activity to terminate. */
-		do {
-			/* Check port cause register that all Rx queues are stopped */
-			reg_data =
-				MV_REG_READ
-				(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
-				 (eth_port_num));
-		}
-		while (reg_data & 0xFF);
-	}
-
-
-	/* Clear all MIB counters */
-	eth_clear_mib_counters (eth_port_num);
-
-	/* Reset the Enable bit in the Configuration Register */
-	reg_data =
-		MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG
-			     (eth_port_num));
-	reg_data &= ~ETH_SERIAL_PORT_ENABLE;
-	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
-		      reg_data);
-
-	return;
-}
-
-#if 0				/* Not needed here */
-/*******************************************************************************
- * ethernet_set_config_reg - Set specified bits in configuration register.
- *
- * DESCRIPTION:
- *       This function sets specified bits in the given ethernet
- *       configuration register.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *      unsigned int    value   32 bit value.
- *
- * OUTPUT:
- *      The set bits in the value parameter are set in the configuration
- *      register.
- *
- * RETURN:
- *      None.
- *
- *******************************************************************************/
-static void ethernet_set_config_reg (ETH_PORT eth_port_num,
-				     unsigned int value)
-{
-	unsigned int eth_config_reg;
-
-	eth_config_reg =
-		MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num));
-	eth_config_reg |= value;
-	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
-		      eth_config_reg);
-
-	return;
-}
-#endif
-
-#if 0				/* FIXME */
-/*******************************************************************************
- * ethernet_reset_config_reg - Reset specified bits in configuration register.
- *
- * DESCRIPTION:
- *       This function resets specified bits in the given Ethernet
- *       configuration register.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *      unsigned int    value   32 bit value.
- *
- * OUTPUT:
- *      The set bits in the value parameter are reset in the configuration
- *      register.
- *
- * RETURN:
- *      None.
- *
- *******************************************************************************/
-static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
-				       unsigned int value)
-{
-	unsigned int eth_config_reg;
-
-	eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
-				      (eth_port_num));
-	eth_config_reg &= ~value;
-	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
-		      eth_config_reg);
-
-	return;
-}
-#endif
-
-#if 0				/* Not needed here */
-/*******************************************************************************
- * ethernet_get_config_reg - Get the port configuration register
- *
- * DESCRIPTION:
- *       This function returns the configuration register value of the given
- *       ethernet port.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- *       None.
- *
- * RETURN:
- *       Port configuration register value.
- *
- *******************************************************************************/
-static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
-{
-	unsigned int eth_config_reg;
-
-	eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
-				      (eth_port_num));
-	return eth_config_reg;
-}
-
-#endif
-
-/*******************************************************************************
- * eth_port_read_smi_reg - Read PHY registers
- *
- * DESCRIPTION:
- *       This routine utilize the SMI interface to interact with the PHY in
- *       order to perform PHY register read.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *       unsigned int   phy_reg   PHY register address offset.
- *       unsigned int   *value   Register value buffer.
- *
- * OUTPUT:
- *       Write the value of a specified PHY register into given buffer.
- *
- * RETURN:
- *       false if the PHY is busy or read data is not in valid state.
- *       true otherwise.
- *
- *******************************************************************************/
-static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
-				   unsigned int phy_reg, unsigned int *value)
-{
-	unsigned int reg_value;
-	unsigned int time_out = PHY_BUSY_TIMEOUT;
-	int phy_addr;
-
-	phy_addr = ethernet_phy_get (eth_port_num);
-/*    printf("     Phy-Port %d has addess %d  \n",eth_port_num, phy_addr );*/
-
-	/* first check that it is not busy */
-	do {
-		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
-		if (time_out-- == 0) {
-			return false;
-		}
-	}
-	while (reg_value & ETH_SMI_BUSY);
-
-	/* not busy */
-
-	MV_REG_WRITE (MV64360_ETH_SMI_REG,
-		      (phy_addr << 16) | (phy_reg << 21) |
-		      ETH_SMI_OPCODE_READ);
-
-	time_out = PHY_BUSY_TIMEOUT;	/* initialize the time out var again */
-
-	do {
-		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
-		if (time_out-- == 0) {
-			return false;
-		}
-	}
-	while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID);	/* Bit set equ operation done */
-
-	/* Wait for the data to update in the SMI register */
-#define PHY_UPDATE_TIMEOUT	10000
-	for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
-
-	reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
-
-	*value = reg_value & 0xffff;
-
-	return true;
-}
-
-/*******************************************************************************
- * eth_port_write_smi_reg - Write to PHY registers
- *
- * DESCRIPTION:
- *       This routine utilize the SMI interface to interact with the PHY in
- *       order to perform writes to PHY registers.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *      unsigned int   phy_reg   PHY register address offset.
- *      unsigned int    value   Register value.
- *
- * OUTPUT:
- *      Write the given value to the specified PHY register.
- *
- * RETURN:
- *      false if the PHY is busy.
- *      true otherwise.
- *
- *******************************************************************************/
-static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
-				    unsigned int phy_reg, unsigned int value)
-{
-	unsigned int reg_value;
-	unsigned int time_out = PHY_BUSY_TIMEOUT;
-	int phy_addr;
-
-	phy_addr = ethernet_phy_get (eth_port_num);
-
-	/* first check that it is not busy */
-	do {
-		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
-		if (time_out-- == 0) {
-			return false;
-		}
-	}
-	while (reg_value & ETH_SMI_BUSY);
-
-	/* not busy */
-	MV_REG_WRITE (MV64360_ETH_SMI_REG,
-		      (phy_addr << 16) | (phy_reg << 21) |
-		      ETH_SMI_OPCODE_WRITE | (value & 0xffff));
-	return true;
-}
-
-/*******************************************************************************
- * eth_set_access_control - Config address decode parameters for Ethernet unit
- *
- * DESCRIPTION:
- *       This function configures the address decode parameters for the Gigabit
- *       Ethernet Controller according the given parameters struct.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *       ETH_WIN_PARAM  *param   Address decode parameter struct.
- *
- * OUTPUT:
- *       An access window is opened using the given access parameters.
- *
- * RETURN:
- *       None.
- *
- *******************************************************************************/
-static void eth_set_access_control (ETH_PORT eth_port_num,
-				    ETH_WIN_PARAM * param)
-{
-	unsigned int access_prot_reg;
-
-	/* Set access control register */
-	access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG
-				       (eth_port_num));
-	access_prot_reg &= (~(3 << (param->win * 2)));	/* clear window permission */
-	access_prot_reg |= (param->access_ctrl << (param->win * 2));
-	MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num),
-		      access_prot_reg);
-
-	/* Set window Size reg (SR) */
-	MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 +
-		       (ETH_SIZE_REG_GAP * param->win)),
-		      (((param->size / 0x10000) - 1) << 16));
-
-	/* Set window Base address reg (BA) */
-	MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
-		      (param->target | param->attributes | param->base_addr));
-	/* High address remap reg (HARR) */
-	if (param->win < 4)
-		MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 +
-			       (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
-			      param->high_addr);
-
-	/* Base address enable reg (BARER) */
-	if (param->enable == 1)
-		MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
-				   (1 << param->win));
-	else
-		MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
-				 (1 << param->win));
-}
-
-/*******************************************************************************
- * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
- *
- * DESCRIPTION:
- *       This function prepares a Rx chained list of descriptors and packet
- *       buffers in a form of a ring. The routine must be called after port
- *       initialization routine and before port start routine.
- *       The Ethernet SDMA engine uses CPU bus addresses to access the various
- *       devices in the system (i.e. DRAM). This function uses the ethernet
- *       struct 'virtual to physical' routine (set by the user) to set the ring
- *       with physical addresses.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	rx_queue         Number of Rx queue.
- *      int			rx_desc_num       Number of Rx descriptors
- *      int			rx_buff_size      Size of Rx buffer
- *      unsigned int    rx_desc_base_addr  Rx descriptors memory area base addr.
- *      unsigned int    rx_buff_base_addr  Rx buffer memory area base addr.
- *
- * OUTPUT:
- *      The routine updates the Ethernet port control struct with information
- *      regarding the Rx descriptors and buffers.
- *
- * RETURN:
- *      false if the given descriptors memory area is not aligned according to
- *      Ethernet SDMA specifications.
- *      true otherwise.
- *
- *******************************************************************************/
-static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
-				     ETH_QUEUE rx_queue,
-				     int rx_desc_num,
-				     int rx_buff_size,
-				     unsigned int rx_desc_base_addr,
-				     unsigned int rx_buff_base_addr)
-{
-	ETH_RX_DESC *p_rx_desc;
-	ETH_RX_DESC *p_rx_prev_desc;	/* pointer to link with the last descriptor */
-	unsigned int buffer_addr;
-	int ix;			/* a counter */
-
-
-	p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
-	p_rx_prev_desc = p_rx_desc;
-	buffer_addr = rx_buff_base_addr;
-
-	/* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
-	if (rx_buff_base_addr & 0xF)
-		return false;
-
-	/* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
-	if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
-		return false;
-
-	/* Rx buffers must be 64-bit aligned.       */
-	if ((rx_buff_base_addr + rx_buff_size) & 0x7)
-		return false;
-
-	/* initialize the Rx descriptors ring */
-	for (ix = 0; ix < rx_desc_num; ix++) {
-		p_rx_desc->buf_size = rx_buff_size;
-		p_rx_desc->byte_cnt = 0x0000;
-		p_rx_desc->cmd_sts =
-			ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
-		p_rx_desc->next_desc_ptr =
-			((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
-		p_rx_desc->buf_ptr = buffer_addr;
-		p_rx_desc->return_info = 0x00000000;
-		D_CACHE_FLUSH_LINE (p_rx_desc, 0);
-		buffer_addr += rx_buff_size;
-		p_rx_prev_desc = p_rx_desc;
-		p_rx_desc = (ETH_RX_DESC *)
-			((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
-	}
-
-	/* Closing Rx descriptors ring */
-	p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
-	D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
-
-	/* Save Rx desc pointer to driver struct. */
-	CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
-	USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
-
-	p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
-		(ETH_RX_DESC *) rx_desc_base_addr;
-	p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
-		rx_desc_num * RX_DESC_ALIGNED_SIZE;
-
-	p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
-
-	return true;
-}
-
-/*******************************************************************************
- * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
- *
- * DESCRIPTION:
- *       This function prepares a Tx chained list of descriptors and packet
- *       buffers in a form of a ring. The routine must be called after port
- *       initialization routine and before port start routine.
- *       The Ethernet SDMA engine uses CPU bus addresses to access the various
- *       devices in the system (i.e. DRAM). This function uses the ethernet
- *       struct 'virtual to physical' routine (set by the user) to set the ring
- *       with physical addresses.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	tx_queue         Number of Tx queue.
- *      int			tx_desc_num       Number of Tx descriptors
- *      int			tx_buff_size      Size of Tx buffer
- *      unsigned int    tx_desc_base_addr  Tx descriptors memory area base addr.
- *      unsigned int    tx_buff_base_addr  Tx buffer memory area base addr.
- *
- * OUTPUT:
- *      The routine updates the Ethernet port control struct with information
- *      regarding the Tx descriptors and buffers.
- *
- * RETURN:
- *      false if the given descriptors memory area is not aligned according to
- *      Ethernet SDMA specifications.
- *      true otherwise.
- *
- *******************************************************************************/
-static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
-				     ETH_QUEUE tx_queue,
-				     int tx_desc_num,
-				     int tx_buff_size,
-				     unsigned int tx_desc_base_addr,
-				     unsigned int tx_buff_base_addr)
-{
-
-	ETH_TX_DESC *p_tx_desc;
-	ETH_TX_DESC *p_tx_prev_desc;
-	unsigned int buffer_addr;
-	int ix;			/* a counter */
-
-
-	/* save the first desc pointer to link with the last descriptor */
-	p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
-	p_tx_prev_desc = p_tx_desc;
-	buffer_addr = tx_buff_base_addr;
-
-	/* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
-	if (tx_buff_base_addr & 0xF)
-		return false;
-
-	/* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
-	if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
-	    || (tx_buff_size < TX_BUFFER_MIN_SIZE))
-		return false;
-
-	/* Initialize the Tx descriptors ring */
-	for (ix = 0; ix < tx_desc_num; ix++) {
-		p_tx_desc->byte_cnt = 0x0000;
-		p_tx_desc->l4i_chk = 0x0000;
-		p_tx_desc->cmd_sts = 0x00000000;
-		p_tx_desc->next_desc_ptr =
-			((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
-
-		p_tx_desc->buf_ptr = buffer_addr;
-		p_tx_desc->return_info = 0x00000000;
-		D_CACHE_FLUSH_LINE (p_tx_desc, 0);
-		buffer_addr += tx_buff_size;
-		p_tx_prev_desc = p_tx_desc;
-		p_tx_desc = (ETH_TX_DESC *)
-			((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
-
-	}
-	/* Closing Tx descriptors ring */
-	p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
-	D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
-	/* Set Tx desc pointer in driver struct. */
-	CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
-	USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
-
-	/* Init Tx ring base and size parameters */
-	p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
-		(ETH_TX_DESC *) tx_desc_base_addr;
-	p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
-		(tx_desc_num * TX_DESC_ALIGNED_SIZE);
-
-	/* Add the queue to the list of Tx queues of this port */
-	p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
-
-	return true;
-}
-
-/*******************************************************************************
- * eth_port_send - Send an Ethernet packet
- *
- * DESCRIPTION:
- *	This routine send a given packet described by p_pktinfo parameter. It
- *      supports transmitting of a packet spaned over multiple buffers. The
- *      routine updates 'curr' and 'first' indexes according to the packet
- *      segment passed to the routine. In case the packet segment is first,
- *      the 'first' index is update. In any case, the 'curr' index is updated.
- *      If the routine get into Tx resource error it assigns 'curr' index as
- *      'first'. This way the function can abort Tx process of multiple
- *      descriptors per packet.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	tx_queue         Number of Tx queue.
- *	PKT_INFO        *p_pkt_info       User packet buffer.
- *
- * OUTPUT:
- *	Tx ring 'curr' and 'first' indexes are updated.
- *
- * RETURN:
- *      ETH_QUEUE_FULL in case of Tx resource error.
- *	ETH_ERROR in case the routine can not access Tx desc ring.
- *	ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
- *      ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
-					  ETH_QUEUE tx_queue,
-					  PKT_INFO * p_pkt_info)
-{
-	volatile ETH_TX_DESC *p_tx_desc_first;
-	volatile ETH_TX_DESC *p_tx_desc_curr;
-	volatile ETH_TX_DESC *p_tx_next_desc_curr;
-	volatile ETH_TX_DESC *p_tx_desc_used;
-	unsigned int command_status;
-
-	/* Do not process Tx ring in case of Tx ring resource error */
-	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
-		return ETH_QUEUE_FULL;
-
-	/* Get the Tx Desc ring indexes */
-	CURR_TFD_GET (p_tx_desc_curr, tx_queue);
-	USED_TFD_GET (p_tx_desc_used, tx_queue);
-
-	if (p_tx_desc_curr == NULL)
-		return ETH_ERROR;
-
-	/* The following parameters are used to save readings from memory */
-	p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
-	command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
-
-	if (command_status & (ETH_TX_FIRST_DESC)) {
-		/* Update first desc */
-		FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
-		p_tx_desc_first = p_tx_desc_curr;
-	} else {
-		FIRST_TFD_GET (p_tx_desc_first, tx_queue);
-		command_status |= ETH_BUFFER_OWNED_BY_DMA;
-	}
-
-	/* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
-	/* boundary. We use the memory allocated for Tx descriptor. This memory  */
-	/* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
-	if (p_pkt_info->byte_cnt <= 8) {
-		printf ("You have failed in the < 8 bytes errata - fixme\n");	/* RABEEH - TBD */
-		return ETH_ERROR;
-
-		p_tx_desc_curr->buf_ptr =
-			(unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
-		eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
-			    p_pkt_info->byte_cnt);
-	} else
-		p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
-
-	p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
-	p_tx_desc_curr->return_info = p_pkt_info->return_info;
-
-	if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
-		/* Set last desc with DMA ownership and interrupt enable. */
-		p_tx_desc_curr->cmd_sts = command_status |
-			ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
-
-		if (p_tx_desc_curr != p_tx_desc_first)
-			p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
-
-		/* Flush CPU pipe */
-
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
-		CPU_PIPE_FLUSH;
-
-		/* Apply send command */
-		ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
-
-		/* Finish Tx packet. Update first desc in case of Tx resource error */
-		p_tx_desc_first = p_tx_next_desc_curr;
-		FIRST_TFD_SET (p_tx_desc_first, tx_queue);
-
-	} else {
-		p_tx_desc_curr->cmd_sts = command_status;
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
-	}
-
-	/* Check for ring index overlap in the Tx desc ring */
-	if (p_tx_next_desc_curr == p_tx_desc_used) {
-		/* Update the current descriptor */
-		CURR_TFD_SET (p_tx_desc_first, tx_queue);
-
-		p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
-		return ETH_QUEUE_LAST_RESOURCE;
-	} else {
-		/* Update the current descriptor */
-		CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
-		return ETH_OK;
-	}
-}
-
-/*******************************************************************************
- * eth_tx_return_desc - Free all used Tx descriptors
- *
- * DESCRIPTION:
- *	This routine returns the transmitted packet information to the caller.
- *      It uses the 'first' index to support Tx desc return in case a transmit
- *      of a packet spanned over multiple buffer still in process.
- *      In case the Tx queue was in "resource error" condition, where there are
- *      no available Tx resources, the function resets the resource error flag.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	tx_queue         Number of Tx queue.
- *	PKT_INFO        *p_pkt_info       User packet buffer.
- *
- * OUTPUT:
- *	Tx ring 'first' and 'used' indexes are updated.
- *
- * RETURN:
- *	ETH_ERROR in case the routine can not access Tx desc ring.
- *      ETH_RETRY in case there is transmission in process.
- *	ETH_END_OF_JOB if the routine has nothing to release.
- *      ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
-					       p_eth_port_ctrl,
-					       ETH_QUEUE tx_queue,
-					       PKT_INFO * p_pkt_info)
-{
-	volatile ETH_TX_DESC *p_tx_desc_used = NULL;
-	volatile ETH_TX_DESC *p_tx_desc_first = NULL;
-	unsigned int command_status;
-
-
-	/* Get the Tx Desc ring indexes */
-	USED_TFD_GET (p_tx_desc_used, tx_queue);
-	FIRST_TFD_GET (p_tx_desc_first, tx_queue);
-
-
-	/* Sanity check */
-	if (p_tx_desc_used == NULL)
-		return ETH_ERROR;
-
-	command_status = p_tx_desc_used->cmd_sts;
-
-	/* Still transmitting... */
-	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
-		return ETH_RETRY;
-	}
-
-	/* Stop release. About to overlap the current available Tx descriptor */
-	if ((p_tx_desc_used == p_tx_desc_first) &&
-	    (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
-		return ETH_END_OF_JOB;
-	}
-
-	/* Pass the packet information to the caller */
-	p_pkt_info->cmd_sts = command_status;
-	p_pkt_info->return_info = p_tx_desc_used->return_info;
-	p_tx_desc_used->return_info = 0;
-
-	/* Update the next descriptor to release. */
-	USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
-
-	/* Any Tx return cancels the Tx resource error status */
-	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
-		p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
-
-	D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
-
-	return ETH_OK;
-
-}
-
-/*******************************************************************************
- * eth_port_receive - Get received information from Rx ring.
- *
- * DESCRIPTION:
- *	This routine returns the received data to the caller. There is no
- *	data copying during routine operation. All information is returned
- *	using pointer to packet information struct passed from the caller.
- *      If the routine exhausts	Rx ring resources then the resource error flag
- *      is set.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	rx_queue         Number of Rx queue.
- *	PKT_INFO        *p_pkt_info       User packet buffer.
- *
- * OUTPUT:
- *	Rx ring current and used indexes are updated.
- *
- * RETURN:
- *	ETH_ERROR in case the routine can not access Rx desc ring.
- *	ETH_QUEUE_FULL if Rx ring resources are exhausted.
- *	ETH_END_OF_JOB if there is no received data.
- *      ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
-					     ETH_QUEUE rx_queue,
-					     PKT_INFO * p_pkt_info)
-{
-	volatile ETH_RX_DESC *p_rx_curr_desc;
-	volatile ETH_RX_DESC *p_rx_next_curr_desc;
-	volatile ETH_RX_DESC *p_rx_used_desc;
-	unsigned int command_status;
-
-	/* Do not process Rx ring in case of Rx ring resource error */
-	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
-		printf ("\nRx Queue is full ...\n");
-		return ETH_QUEUE_FULL;
-	}
-
-	/* Get the Rx Desc ring 'curr and 'used' indexes */
-	CURR_RFD_GET (p_rx_curr_desc, rx_queue);
-	USED_RFD_GET (p_rx_used_desc, rx_queue);
-
-	/* Sanity check */
-	if (p_rx_curr_desc == NULL)
-		return ETH_ERROR;
-
-	/* The following parameters are used to save readings from memory */
-	p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
-	command_status = p_rx_curr_desc->cmd_sts;
-
-	/* Nothing to receive... */
-	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
-/*	DP(printf("Rx: command_status: %08x\n", command_status)); */
-		D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
-/*	DP(printf("\nETH_END_OF_JOB ...\n"));*/
-		return ETH_END_OF_JOB;
-	}
-
-	p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
-	p_pkt_info->cmd_sts = command_status;
-	p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
-	p_pkt_info->return_info = p_rx_curr_desc->return_info;
-	p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size;	/* IP fragment indicator */
-
-	/* Clean the return info field to indicate that the packet has been */
-	/* moved to the upper layers                                        */
-	p_rx_curr_desc->return_info = 0;
-
-	/* Update 'curr' in data structure */
-	CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
-
-	/* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
-	if (p_rx_next_curr_desc == p_rx_used_desc)
-		p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
-
-	D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
-	CPU_PIPE_FLUSH;
-	return ETH_OK;
-}
-
-/*******************************************************************************
- * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
- *
- * DESCRIPTION:
- *	This routine returns a Rx buffer back to the Rx ring. It retrieves the
- *      next 'used' descriptor and attached the returned buffer to it.
- *      In case the Rx ring was in "resource error" condition, where there are
- *      no available Rx resources, the function resets the resource error flag.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	rx_queue         Number of Rx queue.
- *      PKT_INFO        *p_pkt_info       Information on the returned buffer.
- *
- * OUTPUT:
- *	New available Rx resource in Rx descriptor ring.
- *
- * RETURN:
- *	ETH_ERROR in case the routine can not access Rx desc ring.
- *      ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
-					       p_eth_port_ctrl,
-					       ETH_QUEUE rx_queue,
-					       PKT_INFO * p_pkt_info)
-{
-	volatile ETH_RX_DESC *p_used_rx_desc;	/* Where to return Rx resource */
-
-	/* Get 'used' Rx descriptor */
-	USED_RFD_GET (p_used_rx_desc, rx_queue);
-
-	/* Sanity check */
-	if (p_used_rx_desc == NULL)
-		return ETH_ERROR;
-
-	p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
-	p_used_rx_desc->return_info = p_pkt_info->return_info;
-	p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
-	p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE;	/* Reset Buffer size */
-
-	/* Flush the write pipe */
-	CPU_PIPE_FLUSH;
-
-	/* Return the descriptor to DMA ownership */
-	p_used_rx_desc->cmd_sts =
-		ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
-
-	/* Flush descriptor and CPU pipe */
-	D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
-	CPU_PIPE_FLUSH;
-
-	/* Move the used descriptor pointer to the next descriptor */
-	USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
-
-	/* Any Rx return cancels the Rx resource error status */
-	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
-		p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
-
-	return ETH_OK;
-}
-
-/*******************************************************************************
- * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
- *
- * DESCRIPTION:
- *	This routine sets the RX coalescing interrupt mechanism parameter.
- *	This parameter is a timeout counter, that counts in 64 t_clk
- *	chunks ; that when timeout event occurs a maskable interrupt
- *	occurs.
- *	The parameter is calculated using the tClk of the MV-643xx chip
- *	, and the required delay of the interrupt in usec.
- *
- * INPUT:
- *	ETH_PORT eth_port_num      Ethernet port number
- *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
- *	unsigned int delay       Delay in usec
- *
- * OUTPUT:
- *	Interrupt coalescing mechanism value is set in MV-643xx chip.
- *
- * RETURN:
- *	The interrupt coalescing value set in the gigE port.
- *
- *******************************************************************************/
-#if 0				/* FIXME */
-static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
-					  unsigned int t_clk,
-					  unsigned int delay)
-{
-	unsigned int coal;
-
-	coal = ((t_clk / 1000000) * delay) / 64;
-	/* Set RX Coalescing mechanism */
-	MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
-		      ((coal & 0x3fff) << 8) |
-		      (MV_REG_READ
-		       (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num))
-		       & 0xffc000ff));
-	return coal;
-}
-
-#endif
-/*******************************************************************************
- * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
- *
- * DESCRIPTION:
- *	This routine sets the TX coalescing interrupt mechanism parameter.
- *	This parameter is a timeout counter, that counts in 64 t_clk
- *	chunks ; that when timeout event occurs a maskable interrupt
- *	occurs.
- *	The parameter is calculated using the t_cLK frequency of the
- *	MV-643xx chip and the required delay in the interrupt in uSec
- *
- * INPUT:
- *	ETH_PORT eth_port_num      Ethernet port number
- *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
- *	unsigned int delay       Delay in uSeconds
- *
- * OUTPUT:
- *	Interrupt coalescing mechanism value is set in MV-643xx chip.
- *
- * RETURN:
- *	The interrupt coalescing value set in the gigE port.
- *
- *******************************************************************************/
-#if 0				/* FIXME */
-static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
-					  unsigned int t_clk,
-					  unsigned int delay)
-{
-	unsigned int coal;
-
-	coal = ((t_clk / 1000000) * delay) / 64;
-	/* Set TX Coalescing mechanism */
-	MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
-		      coal << 4);
-	return coal;
-}
-#endif
-
-/*******************************************************************************
- * eth_b_copy - Copy bytes from source to destination
- *
- * DESCRIPTION:
- *       This function supports the eight bytes limitation on Tx buffer size.
- *       The routine will zero eight bytes starting from the destination address
- *       followed by copying bytes from the source address to the destination.
- *
- * INPUT:
- *       unsigned int src_addr    32 bit source address.
- *       unsigned int dst_addr    32 bit destination address.
- *       int        byte_count    Number of bytes to copy.
- *
- * OUTPUT:
- *       See description.
- *
- * RETURN:
- *       None.
- *
- *******************************************************************************/
-static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
-			int byte_count)
-{
-	/* Zero the dst_addr area */
-	*(unsigned int *) dst_addr = 0x0;
-
-	while (byte_count != 0) {
-		*(char *) dst_addr = *(char *) src_addr;
-		dst_addr++;
-		src_addr++;
-		byte_count--;
-	}
-}
diff --git a/board/Marvell/db64360/mv_eth.h b/board/Marvell/db64360/mv_eth.h
deleted file mode 100644
index d960eb4c5dc..00000000000
--- a/board/Marvell/db64360/mv_eth.h
+++ /dev/null
@@ -1,818 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * mv_eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __DB64360_ETH_H__
-#define __DB64360_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-#include <net.h>
-#include "mv_regs.h"
-#include <asm/errno.h>
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The first part is the high level driver of the gigE ethernet ports.	 *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
-#ifndef MAX_SKB_FRAGS
-#define MAX_SKB_FRAGS 0
-#endif
-
-/* Port attributes */
-/*#define MAX_RX_QUEUE_NUM	8*/
-/*#define MAX_TX_QUEUE_NUM	8*/
-#define MAX_RX_QUEUE_NUM	1
-#define MAX_TX_QUEUE_NUM	1
-
-
-/* Use one TX queue and one RX queue */
-#define MV64360_TX_QUEUE_NUM 1
-#define MV64360_RX_QUEUE_NUM 1
-
-/*
- * Number of RX / TX descriptors on RX / TX rings.
- * Note that allocating RX descriptors is done by allocating the RX
- * ring AND a preallocated RX buffers (skb's) for each descriptor.
- * The TX descriptors only allocates the TX descriptors ring,
- * with no pre allocated TX buffers (skb's are allocated by higher layers.
- */
-
-/* Default TX ring size is 10 descriptors */
-#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
-#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
-#else
-#define MV64360_TX_QUEUE_SIZE 4
-#endif
-
-/* Default RX ring size is 4 descriptors */
-#ifdef	CONFIG_MV64360_ETH_RXQUEUE_SIZE
-#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
-#else
-#define MV64360_RX_QUEUE_SIZE 4
-#endif
-
-#ifdef CONFIG_RX_BUFFER_SIZE
-#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
-#else
-#define MV64360_RX_BUFFER_SIZE 1600
-#endif
-
-#ifdef CONFIG_TX_BUFFER_SIZE
-#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
-#else
-#define MV64360_TX_BUFFER_SIZE 1600
-#endif
-
-
-/*
- *	Network device statistics. Akin to the 2.0 ether stats but
- *	with byte counters.
- */
-
-struct net_device_stats
-{
-	unsigned long	rx_packets;		/* total packets received	*/
-	unsigned long	tx_packets;		/* total packets transmitted	*/
-	unsigned long	rx_bytes;		/* total bytes received		*/
-	unsigned long	tx_bytes;		/* total bytes transmitted	*/
-	unsigned long	rx_errors;		/* bad packets received		*/
-	unsigned long	tx_errors;		/* packet transmit problems	*/
-	unsigned long	rx_dropped;		/* no space in linux buffers	*/
-	unsigned long	tx_dropped;		/* no space available in linux	*/
-	unsigned long	multicast;		/* multicast packets received	*/
-	unsigned long	collisions;
-
-	/* detailed rx_errors: */
-	unsigned long	rx_length_errors;
-	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
-	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
-	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
-	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
-	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
-
-	/* detailed tx_errors */
-	unsigned long	tx_aborted_errors;
-	unsigned long	tx_carrier_errors;
-	unsigned long	tx_fifo_errors;
-	unsigned long	tx_heartbeat_errors;
-	unsigned long	tx_window_errors;
-
-	/* for cslip etc */
-	unsigned long	rx_compressed;
-	unsigned long	tx_compressed;
-};
-
-
-/* Private data structure used for ethernet device */
-struct mv64360_eth_priv {
-    unsigned int port_num;
-    struct net_device_stats *stats;
-
-/* to buffer area aligned */
-    char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
-    char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
-
-    /* Size of Tx Ring per queue */
-    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
-
-
-    /* Size of Rx Ring per queue */
-    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
-
-    /* Magic Number for Ethernet running */
-    unsigned int eth_running;
-
-};
-
-
-int mv64360_eth_init (struct eth_device *dev);
-int mv64360_eth_stop (struct eth_device *dev);
-int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length);
-int mv64360_eth_open (struct eth_device *dev);
-
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The second part is the low level driver of the gigE ethernet ports.	 *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-
-
-/********************************************************************************
- * Header File for : MV-643xx network interface header
- *
- * DESCRIPTION:
- *	 This header file contains macros typedefs and function declaration for
- *	 the Marvell Gig Bit Ethernet Controller.
- *
- * DEPENDENCIES:
- *	 None.
- *
- *******************************************************************************/
-
-
-#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
-#ifdef CONFIG_MV64360_SRAM_CACHEABLE
-/* In case SRAM is cacheable but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset)       \
-{		    \
-  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case SRAM is cache coherent or non-cacheable */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif
-#else
-#ifdef CONFIG_NOT_COHERENT_CACHE
-/* In case of descriptors on DDR but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset)       \
-{		    \
-  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case of descriptors on DDR and cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif /* CONFIG_NOT_COHERENT_CACHE */
-#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
-
-
-#define CPU_PIPE_FLUSH		   \
-{		  \
-  __asm__ __volatile__ ("eieio");	  \
-}
-
-
-/* defines  */
-
-/* Default port configuration value */
-#define PORT_CONFIG_VALUE			\
-	     ETH_UNICAST_NORMAL_MODE		|   \
-	     ETH_DEFAULT_RX_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
-	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
-	     ETH_RECEIVE_BC_IF_IP		|   \
-	     ETH_RECEIVE_BC_IF_ARP		|   \
-	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
-	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
-	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_BPDU_QUEUE_0
-
-/* Default port extend configuration value */
-#define PORT_CONFIG_EXTEND_VALUE		\
-	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
-	     ETH_PARTITION_DISABLE
-
-
-/* Default sdma control value */
-#ifdef CONFIG_NOT_COHERENT_CACHE
-#define PORT_SDMA_CONFIG_VALUE				\
-			 ETH_RX_BURST_SIZE_16_64BIT	|	\
-			 GT_ETH_IPG_INT_RX(0)			|	\
-			 ETH_TX_BURST_SIZE_16_64BIT;
-#else
-#define PORT_SDMA_CONFIG_VALUE			\
-			 ETH_RX_BURST_SIZE_4_64BIT	|	\
-			 GT_ETH_IPG_INT_RX(0)			|	\
-			 ETH_TX_BURST_SIZE_4_64BIT;
-#endif
-
-#define GT_ETH_IPG_INT_RX(value)		\
-	    ((value & 0x3fff) << 8)
-
-/* Default port serial control value */
-#define PORT_SERIAL_CONTROL_VALUE			    \
-			ETH_FORCE_LINK_PASS			|	\
-			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
-			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
-			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
-			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
-			ETH_FORCE_BP_MODE_NO_JAM		|	\
-			BIT9					|	\
-			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
-			ETH_RETRANSMIT_16_ETTEMPTS		|	\
-			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
-			ETH_DTE_ADV_0				|	\
-			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
-			ETH_AUTO_NEG_NO_CHANGE			|	\
-			ETH_MAX_RX_PACKET_1552BYTE		|	\
-			ETH_CLR_EXT_LOOPBACK			|	\
-			ETH_SET_FULL_DUPLEX_MODE		|	\
-			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
-
-#define RX_BUFFER_MAX_SIZE  0xFFFF
-#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
-
-#define RX_BUFFER_MIN_SIZE  0x8
-#define TX_BUFFER_MIN_SIZE  0x8
-
-/* Tx WRR confoguration macros */
-#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
-#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
-#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
-
-/* MAC accepet/reject macros */
-#define ACCEPT_MAC_ADDR	    0
-#define REJECT_MAC_ADDR	    1
-
-/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define RX_DESC_ALIGNED_SIZE		0x20
-#define TX_DESC_ALIGNED_SIZE		0x20
-
-/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
-#define TX_BUF_OFFSET_IN_DESC	    0x18
-/* Buffer offset from buffer pointer */
-#define RX_BUF_OFFSET				0x2
-
-/* Gap define */
-#define ETH_BAR_GAP					0x8
-#define ETH_SIZE_REG_GAP				0x8
-#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
-#define ETH_PORT_ACCESS_CTRL_GAP			0x4
-
-/* Gigabit Ethernet Unit Global Registers */
-
-/* MIB Counters register definitions */
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
-#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
-#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
-#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
-#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
-#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
-#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
-#define ETH_MIB_FRAMES_64_OCTETS	   0x20
-#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
-#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
-#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
-#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
-#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
-#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
-#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
-#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
-#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
-#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
-#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
-#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
-#define ETH_MIB_FC_SENT			   0x54
-#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
-#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
-#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
-#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
-#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
-#define ETH_MIB_JABBER_RECEIVED		   0x6c
-#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
-#define ETH_MIB_BAD_CRC_EVENT		   0x74
-#define ETH_MIB_COLLISION		   0x78
-#define ETH_MIB_LATE_COLLISION		   0x7c
-
-/* Port serial status reg (PSR) */
-#define ETH_INTERFACE_GMII_MII				0
-#define ETH_INTERFACE_PCM				BIT0
-#define ETH_LINK_IS_DOWN				0
-#define ETH_LINK_IS_UP					BIT1
-#define ETH_PORT_AT_HALF_DUPLEX				0
-#define ETH_PORT_AT_FULL_DUPLEX				BIT2
-#define ETH_RX_FLOW_CTRL_DISABLED			0
-#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
-#define ETH_GMII_SPEED_100_10				0
-#define ETH_GMII_SPEED_1000				BIT4
-#define ETH_MII_SPEED_10				0
-#define ETH_MII_SPEED_100				BIT5
-#define ETH_NO_TX					0
-#define ETH_TX_IN_PROGRESS				BIT7
-#define ETH_BYPASS_NO_ACTIVE				0
-#define ETH_BYPASS_ACTIVE				BIT8
-#define ETH_PORT_NOT_AT_PARTITION_STATE			0
-#define ETH_PORT_AT_PARTITION_STATE			BIT9
-#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
-#define ETH_PORT_TX_FIFO_EMPTY				BIT10
-
-
-/* These macros describes the Port configuration reg (Px_cR) bits */
-#define ETH_UNICAST_NORMAL_MODE				0
-#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
-#define ETH_DEFAULT_RX_QUEUE_0				0
-#define ETH_DEFAULT_RX_QUEUE_1				BIT1
-#define ETH_DEFAULT_RX_QUEUE_2				BIT2
-#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_4				BIT3
-#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
-#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
-#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
-#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
-#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
-#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
-#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
-#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
-#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
-#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
-#define ETH_RECEIVE_BC_IF_IP				0
-#define ETH_REJECT_BC_IF_IP				BIT8
-#define ETH_RECEIVE_BC_IF_ARP				0
-#define ETH_REJECT_BC_IF_ARP				BIT9
-#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
-#define ETH_CAPTURE_TCP_FRAMES_DIS			0
-#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
-#define ETH_CAPTURE_UDP_FRAMES_DIS			0
-#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
-#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
-#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
-#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
-#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
-#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
-#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
-#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
-#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
-#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
-#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
-#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
-#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
-#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
-#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
-#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
-#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
-
-
-/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
-#define ETH_CLASSIFY_EN					BIT0
-#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
-#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
-#define ETH_PARTITION_DISABLE				0
-#define ETH_PARTITION_ENABLE				BIT2
-
-
-/* Tx/Rx queue command reg (RQCR/TQCR)*/
-#define ETH_QUEUE_0_ENABLE				BIT0
-#define ETH_QUEUE_1_ENABLE				BIT1
-#define ETH_QUEUE_2_ENABLE				BIT2
-#define ETH_QUEUE_3_ENABLE				BIT3
-#define ETH_QUEUE_4_ENABLE				BIT4
-#define ETH_QUEUE_5_ENABLE				BIT5
-#define ETH_QUEUE_6_ENABLE				BIT6
-#define ETH_QUEUE_7_ENABLE				BIT7
-#define ETH_QUEUE_0_DISABLE				BIT8
-#define ETH_QUEUE_1_DISABLE				BIT9
-#define ETH_QUEUE_2_DISABLE				BIT10
-#define ETH_QUEUE_3_DISABLE				BIT11
-#define ETH_QUEUE_4_DISABLE				BIT12
-#define ETH_QUEUE_5_DISABLE				BIT13
-#define ETH_QUEUE_6_DISABLE				BIT14
-#define ETH_QUEUE_7_DISABLE				BIT15
-
-
-/* These macros describes the Port Sdma configuration reg (SDCR) bits */
-#define ETH_RIFB					BIT0
-#define ETH_RX_BURST_SIZE_1_64BIT			0
-#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
-#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
-#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
-#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
-#define ETH_BLM_RX_NO_SWAP				BIT4
-#define ETH_BLM_RX_BYTE_SWAP				0
-#define ETH_BLM_TX_NO_SWAP				BIT5
-#define ETH_BLM_TX_BYTE_SWAP				0
-#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
-#define ETH_DESCRIPTORS_NO_SWAP				0
-#define ETH_TX_BURST_SIZE_1_64BIT			0
-#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
-#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
-#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
-#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
-
-
-/* These macros describes the Port serial control reg (PSCR) bits */
-#define ETH_SERIAL_PORT_DISABLE				0
-#define ETH_SERIAL_PORT_ENABLE				BIT0
-#define ETH_FORCE_LINK_PASS				BIT1
-#define ETH_DO_NOT_FORCE_LINK_PASS			0
-#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
-#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
-#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
-#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
-#define ETH_ADV_NO_FLOW_CTRL				0
-#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
-#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
-#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
-#define ETH_FORCE_BP_MODE_NO_JAM			0
-#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
-#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
-#define ETH_FORCE_LINK_FAIL				0
-#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
-#define ETH_RETRANSMIT_16_ETTEMPTS			0
-#define ETH_RETRANSMIT_FOREVER				BIT11
-#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
-#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
-#define ETH_DTE_ADV_0					0
-#define ETH_DTE_ADV_1					BIT14
-#define ETH_DISABLE_AUTO_NEG_BYPASS			0
-#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
-#define ETH_AUTO_NEG_NO_CHANGE				0
-#define ETH_RESTART_AUTO_NEG				BIT16
-#define ETH_MAX_RX_PACKET_1518BYTE			0
-#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
-#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
-#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
-#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
-#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
-#define ETH_SET_EXT_LOOPBACK				BIT20
-#define ETH_CLR_EXT_LOOPBACK				0
-#define ETH_SET_FULL_DUPLEX_MODE			BIT21
-#define ETH_SET_HALF_DUPLEX_MODE			0
-#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
-#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
-#define ETH_SET_GMII_SPEED_TO_10_100			0
-#define ETH_SET_GMII_SPEED_TO_1000			BIT23
-#define ETH_SET_MII_SPEED_TO_10				0
-#define ETH_SET_MII_SPEED_TO_100			BIT24
-
-
-/* SMI reg */
-#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
-#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
-#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
-#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
-
-/* SDMA command status fields macros */
-
-/* Tx & Rx descriptors status */
-#define ETH_ERROR_SUMMARY		    (BIT0)
-
-/* Tx & Rx descriptors command */
-#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
-
-/* Tx descriptors status */
-#define ETH_LC_ERROR			    (0	  )
-#define ETH_UR_ERROR			    (BIT1 )
-#define ETH_RL_ERROR			    (BIT2 )
-#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
-
-/* Rx descriptors status */
-#define ETH_CRC_ERROR			    (0	  )
-#define ETH_OVERRUN_ERROR		    (BIT1 )
-#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
-#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
-#define ETH_VLAN_TAGGED			    (BIT19)
-#define ETH_BPDU_FRAME			    (BIT20)
-#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
-#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
-#define ETH_OTHER_FRAME_TYPE		    (BIT22)
-#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
-#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
-#define ETH_FRAME_HEADER_OK		    (BIT25)
-#define ETH_RX_LAST_DESC		    (BIT26)
-#define ETH_RX_FIRST_DESC		    (BIT27)
-#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
-#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
-#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
-
-/* Rx descriptors byte count */
-#define ETH_FRAME_FRAGMENTED		    (BIT2)
-
-/* Tx descriptors command */
-#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
-#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
-#define ETH_TCP_FRAME			    (0	  )
-#define ETH_UDP_FRAME			    (BIT16)
-#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
-#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
-#define ETH_ZERO_PADDING		    (BIT19)
-#define ETH_TX_LAST_DESC		    (BIT20)
-#define ETH_TX_FIRST_DESC		    (BIT21)
-#define ETH_GEN_CRC			    (BIT22)
-#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
-#define ETH_AUTO_MODE			    (BIT30)
-
-/* Address decode parameters */
-/* Ethernet Base Address Register bits */
-#define EBAR_TARGET_DRAM					0x00000000
-#define EBAR_TARGET_DEVICE					0x00000001
-#define EBAR_TARGET_CBS						0x00000002
-#define EBAR_TARGET_PCI0					0x00000003
-#define EBAR_TARGET_PCI1					0x00000004
-#define EBAR_TARGET_CUNIT					0x00000005
-#define EBAR_TARGET_AUNIT					0x00000006
-#define EBAR_TARGET_GUNIT					0x00000007
-
-/* Window attributes */
-#define EBAR_ATTR_DRAM_CS0					0x00000E00
-#define EBAR_ATTR_DRAM_CS1					0x00000D00
-#define EBAR_ATTR_DRAM_CS2					0x00000B00
-#define EBAR_ATTR_DRAM_CS3					0x00000700
-
-/* DRAM Target interface */
-#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
-
-/* Device Bus Target interface */
-#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
-#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
-#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
-#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
-#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
-
-/* PCI Target interface */
-#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
-#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
-#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
-#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
-#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
-#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
-#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
-#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
-#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
-#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
-
-/* CPU 60x bus or internal SRAM interface */
-#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
-#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
-#define EBAR_ATTR_CBS_SRAM					0x00000000
-#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
-
-/* Window access control */
-#define EWIN_ACCESS_NOT_ALLOWED 0
-#define EWIN_ACCESS_READ_ONLY	BIT0
-#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
-#define EWIN0_ACCESS_MASK		0x0003
-#define EWIN1_ACCESS_MASK		0x000C
-#define EWIN2_ACCESS_MASK		0x0030
-#define EWIN3_ACCESS_MASK		0x00C0
-
-/* typedefs */
-
-typedef enum _eth_port
-{
-    ETH_0 = 0,
-	ETH_1 = 1,
-	ETH_2 = 2
-}ETH_PORT;
-
-typedef enum _eth_func_ret_status
-{
-    ETH_OK,			/* Returned as expected.		    */
-    ETH_ERROR,			/* Fundamental error.			    */
-    ETH_RETRY,			/* Could not process request. Try later.    */
-    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
-    ETH_QUEUE_FULL,		/* Ring resource error.			    */
-    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
-}ETH_FUNC_RET_STATUS;
-
-typedef enum _eth_queue
-{
-	ETH_Q0 = 0,
-	ETH_Q1 = 1,
-	ETH_Q2 = 2,
-	ETH_Q3 = 3,
-	ETH_Q4 = 4,
-	ETH_Q5 = 5,
-	ETH_Q6 = 6,
-    ETH_Q7 = 7
-} ETH_QUEUE;
-
-typedef enum _addr_win
-{
-	ETH_WIN0,
-	ETH_WIN1,
-	ETH_WIN2,
-	ETH_WIN3,
-	ETH_WIN4,
-    ETH_WIN5
-} ETH_ADDR_WIN;
-
-typedef enum _eth_target
-{
-	ETH_TARGET_DRAM	 ,
-	ETH_TARGET_DEVICE,
-	ETH_TARGET_CBS	 ,
-	ETH_TARGET_PCI0	 ,
-	ETH_TARGET_PCI1
-}ETH_TARGET;
-
-typedef struct _eth_rx_desc
-{
-	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
-	unsigned short	buf_size	   ;	/* Buffer size			    */
-	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
-	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
-	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} ETH_RX_DESC;
-
-
-typedef struct _eth_tx_desc
-{
-    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
-    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
-    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
-    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
-    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} ETH_TX_DESC;
-
-/* Unified struct for Rx and Tx operations. The user is not required to */
-/* be familier with neither Tx nor Rx descriptors.			 */
-typedef struct _pkt_info
-{
-	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
-	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
-	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
-	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} PKT_INFO;
-
-
-typedef struct _eth_win_param
-{
-    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
-    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
-    unsigned short attributes;	/* BAR attributes. See above macros. */
-    unsigned int base_addr; /* Window base address in unsigned int form */
-    unsigned int high_addr; /* Window high address in unsigned int form */
-    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
-    bool enable; /* Enable/disable access to the window. */
-    unsigned short access_ctrl; /* Access ctrl register. see above macros */
-} ETH_WIN_PARAM;
-
-
-/* Ethernet port specific infomation */
-
-typedef struct _eth_port_ctrl
-{
-    ETH_PORT  port_num; /* User Ethernet port number */
-    int port_phy_addr;	/* User phy address of Ethrnet port */
-    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
-    unsigned int  port_config; /* User port configuration value */
-    unsigned int  port_config_extend; /* User port config extend value */
-    unsigned int  port_sdma_config; /* User port SDMA config value */
-    unsigned int  port_serial_control; /* User port serial control value */
-    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
-    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
-
-    /* User function to cast virtual address to CPU bus address */
-    unsigned int  (*port_virt_to_phys)(unsigned int addr);
-    /* User scratch pad for user specific data structures */
-    void *port_private;
-
-    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
-    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
-
-    /* Tx/Rx rings managment indexes fields. For driver use */
-
-    /* Next available Rx resource */
-    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
-    /* Returning Rx resource */
-    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
-
-    /* Next available Tx resource */
-    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
-    /* Returning Tx resource */
-    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
-    /* An extra Tx index to support transmit of multiple buffers per packet */
-    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
-
-    /* Tx/Rx rings size and base variables fields. For driver use */
-
-    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
-    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
-    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
-
-    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
-    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
-    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
-
-} ETH_PORT_INFO;
-
-
-/* ethernet.h API list */
-
-/* Port operation control routines */
-static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
-static void eth_port_reset(ETH_PORT	eth_port_num);
-static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
-
-
-/* Port MAC address routines */
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
-				  unsigned char *p_addr,
-				  ETH_QUEUE queue);
-#if 0	/* FIXME */
-static void eth_port_mc_addr	(ETH_PORT eth_port_num,
-				 unsigned char *p_addr,
-				 ETH_QUEUE queue,
-				 int option);
-#endif
-
-/* PHY and MIB routines */
-static bool ethernet_phy_reset(ETH_PORT eth_port_num);
-
-static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
-				   unsigned int phy_reg,
-				   unsigned int value);
-
-static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
-				  unsigned int phy_reg,
-				  unsigned int* value);
-
-static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
-
-/* Port data flow control routines */
-static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
-					     ETH_QUEUE tx_queue,
-					     PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
-					      ETH_QUEUE tx_queue,
-					      PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
-					     ETH_QUEUE rx_queue,
-					     PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
-					      ETH_QUEUE rx_queue,
-					      PKT_INFO *p_pkt_info);
-
-
-static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
-				    ETH_QUEUE	tx_queue,
-				    int				tx_desc_num,
-				    int				tx_buff_size,
-				    unsigned int	tx_desc_base_addr,
-				    unsigned int	tx_buff_base_addr);
-
-static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
-				    ETH_QUEUE	rx_queue,
-				    int				rx_desc_num,
-				    int				rx_buff_size,
-				    unsigned int	rx_desc_base_addr,
-				    unsigned int	rx_buff_base_addr);
-
-#endif /* MV64360_ETH_ */
diff --git a/board/Marvell/db64360/mv_regs.h b/board/Marvell/db64360/mv_regs.h
deleted file mode 100644
index 9a54a976d93..00000000000
--- a/board/Marvell/db64360/mv_regs.h
+++ /dev/null
@@ -1,1108 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/********************************************************************************
-* gt64360r.h - GT-64360 Internal registers definition file.
-*
-* DESCRIPTION:
-*	None.
-*
-* DEPENDENCIES:
-*	None.
-*
-*******************************************************************************/
-
-#ifndef __INCmv_regsh
-#define __INCmv_regsh
-
-#define MV64360
-
-/* Supported by the Atlantis */
-#define MV64360_INCLUDE_PCI_1
-#define MV64360_INCLUDE_PCI_0_ARBITER
-#define MV64360_INCLUDE_PCI_1_ARBITER
-#define MV64360_INCLUDE_SNOOP_SUPPORT
-#define MV64360_INCLUDE_P2P
-#define MV64360_INCLUDE_ETH_PORT_2
-#define MV64360_INCLUDE_CPU_MAPPING
-#define MV64360_INCLUDE_MPSC
-
-/* Not supported features */
-#undef	INCLUDE_CNTMR_4_7
-#undef	INCLUDE_DMA_4_7
-
-/****************************************/
-/* Processor Address Space		*/
-/****************************************/
-
-/* DDR SDRAM BAR and size registers */
-
-#define MV64360_CS_0_BASE_ADDR					    0x008
-#define MV64360_CS_0_SIZE					    0x010
-#define MV64360_CS_1_BASE_ADDR					    0x208
-#define MV64360_CS_1_SIZE					    0x210
-#define MV64360_CS_2_BASE_ADDR					    0x018
-#define MV64360_CS_2_SIZE					    0x020
-#define MV64360_CS_3_BASE_ADDR					    0x218
-#define MV64360_CS_3_SIZE					    0x220
-
-/* Devices BAR and size registers */
-
-#define MV64360_DEV_CS0_BASE_ADDR				    0x028
-#define MV64360_DEV_CS0_SIZE					    0x030
-#define MV64360_DEV_CS1_BASE_ADDR				    0x228
-#define MV64360_DEV_CS1_SIZE					    0x230
-#define MV64360_DEV_CS2_BASE_ADDR				    0x248
-#define MV64360_DEV_CS2_SIZE					    0x250
-#define MV64360_DEV_CS3_BASE_ADDR				    0x038
-#define MV64360_DEV_CS3_SIZE					    0x040
-#define MV64360_BOOTCS_BASE_ADDR				    0x238
-#define MV64360_BOOTCS_SIZE					    0x240
-
-/* PCI 0 BAR and size registers */
-
-#define MV64360_PCI_0_IO_BASE_ADDR				    0x048
-#define MV64360_PCI_0_IO_SIZE					    0x050
-#define MV64360_PCI_0_MEMORY0_BASE_ADDR				    0x058
-#define MV64360_PCI_0_MEMORY0_SIZE				    0x060
-#define MV64360_PCI_0_MEMORY1_BASE_ADDR				    0x080
-#define MV64360_PCI_0_MEMORY1_SIZE				    0x088
-#define MV64360_PCI_0_MEMORY2_BASE_ADDR				    0x258
-#define MV64360_PCI_0_MEMORY2_SIZE				    0x260
-#define MV64360_PCI_0_MEMORY3_BASE_ADDR				    0x280
-#define MV64360_PCI_0_MEMORY3_SIZE				    0x288
-
-/* PCI 1 BAR and size registers */
-#define MV64360_PCI_1_IO_BASE_ADDR				    0x090
-#define MV64360_PCI_1_IO_SIZE					    0x098
-#define MV64360_PCI_1_MEMORY0_BASE_ADDR				    0x0a0
-#define MV64360_PCI_1_MEMORY0_SIZE				    0x0a8
-#define MV64360_PCI_1_MEMORY1_BASE_ADDR				    0x0b0
-#define MV64360_PCI_1_MEMORY1_SIZE				    0x0b8
-#define MV64360_PCI_1_MEMORY2_BASE_ADDR				    0x2a0
-#define MV64360_PCI_1_MEMORY2_SIZE				    0x2a8
-#define MV64360_PCI_1_MEMORY3_BASE_ADDR				    0x2b0
-#define MV64360_PCI_1_MEMORY3_SIZE				    0x2b8
-
-/* SRAM base address */
-#define MV64360_INTEGRATED_SRAM_BASE_ADDR			    0x268
-
-/* internal registers space base address */
-#define MV64360_INTERNAL_SPACE_BASE_ADDR			    0x068
-
-/* Enables the CS , DEV_CS , PCI 0 and PCI 1
-   windows above */
-#define MV64360_BASE_ADDR_ENABLE				    0x278
-
-/****************************************/
-/* PCI remap registers			*/
-/****************************************/
-      /* PCI 0 */
-#define MV64360_PCI_0_IO_ADDR_REMAP				    0x0f0
-#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP			    0x0f8
-#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP			    0x320
-#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP			    0x100
-#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP			    0x328
-#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP			    0x2f8
-#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP			    0x330
-#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP			    0x300
-#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP			    0x338
-      /* PCI 1 */
-#define MV64360_PCI_1_IO_ADDR_REMAP				    0x108
-#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP			    0x110
-#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP			    0x340
-#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP			    0x118
-#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP			    0x348
-#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP			    0x310
-#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP			    0x350
-#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP			    0x318
-#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP			    0x358
-
-#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL		    0x3b0
-#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE			    0x3b8
-#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL		    0x3c0
-#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE			    0x3c8
-#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL			    0x3d0
-#define MV64360_CPU_GE_HEADERS_RETARGET_BASE			    0x3d8
-#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL		    0x3e0
-#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE			    0x3e8
-
-/****************************************/
-/*	   CPU Control Registers	*/
-/****************************************/
-
-#define MV64360_CPU_CONFIG					    0x000
-#define MV64360_CPU_MODE					    0x120
-#define MV64360_CPU_MASTER_CONTROL				    0x160
-#define MV64360_CPU_CROSS_BAR_CONTROL_LOW			    0x150
-#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH			    0x158
-#define MV64360_CPU_CROSS_BAR_TIMEOUT				    0x168
-
-/****************************************/
-/* SMP RegisterS			*/
-/****************************************/
-
-#define MV64360_SMP_WHO_AM_I					    0x200
-#define MV64360_SMP_CPU0_DOORBELL				    0x214
-#define MV64360_SMP_CPU0_DOORBELL_CLEAR				    0x21C
-#define MV64360_SMP_CPU1_DOORBELL				    0x224
-#define MV64360_SMP_CPU1_DOORBELL_CLEAR				    0x22C
-#define MV64360_SMP_CPU0_DOORBELL_MASK				    0x234
-#define MV64360_SMP_CPU1_DOORBELL_MASK				    0x23C
-#define MV64360_SMP_SEMAPHOR0					    0x244
-#define MV64360_SMP_SEMAPHOR1					    0x24c
-#define MV64360_SMP_SEMAPHOR2					    0x254
-#define MV64360_SMP_SEMAPHOR3					    0x25c
-#define MV64360_SMP_SEMAPHOR4					    0x264
-#define MV64360_SMP_SEMAPHOR5					    0x26c
-#define MV64360_SMP_SEMAPHOR6					    0x274
-#define MV64360_SMP_SEMAPHOR7					    0x27c
-
-/****************************************/
-/*  CPU Sync Barrier Register		*/
-/****************************************/
-
-#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER			    0x0c0
-#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL			    0x0c8
-#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER			    0x0d0
-#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL			    0x0d8
-
-/****************************************/
-/* CPU Access Protect			*/
-/****************************************/
-
-#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR			    0x180
-#define MV64360_CPU_PROTECT_WINDOW_0_SIZE			    0x188
-#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR			    0x190
-#define MV64360_CPU_PROTECT_WINDOW_1_SIZE			    0x198
-#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR			    0x1a0
-#define MV64360_CPU_PROTECT_WINDOW_2_SIZE			    0x1a8
-#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR			    0x1b0
-#define MV64360_CPU_PROTECT_WINDOW_3_SIZE			    0x1b8
-
-
-/****************************************/
-/*	    CPU Error Report		*/
-/****************************************/
-
-#define MV64360_CPU_ERROR_ADDR_LOW				    0x070
-#define MV64360_CPU_ERROR_ADDR_HIGH				    0x078
-#define MV64360_CPU_ERROR_DATA_LOW				    0x128
-#define MV64360_CPU_ERROR_DATA_HIGH				    0x130
-#define MV64360_CPU_ERROR_PARITY				    0x138
-#define MV64360_CPU_ERROR_CAUSE					    0x140
-#define MV64360_CPU_ERROR_MASK					    0x148
-
-/****************************************/
-/*	CPU Interface Debug Registers	*/
-/****************************************/
-
-#define MV64360_PUNIT_SLAVE_DEBUG_LOW				    0x360
-#define MV64360_PUNIT_SLAVE_DEBUG_HIGH				    0x368
-#define MV64360_PUNIT_MASTER_DEBUG_LOW				    0x370
-#define MV64360_PUNIT_MASTER_DEBUG_HIGH				    0x378
-#define MV64360_PUNIT_MMASK					    0x3e4
-
-/****************************************/
-/*  Integrated SRAM Registers		*/
-/****************************************/
-
-#define MV64360_SRAM_CONFIG					    0x380
-#define MV64360_SRAM_TEST_MODE					    0X3F4
-#define MV64360_SRAM_ERROR_CAUSE				    0x388
-#define MV64360_SRAM_ERROR_ADDR					    0x390
-#define MV64360_SRAM_ERROR_ADDR_HIGH				    0X3F8
-#define MV64360_SRAM_ERROR_DATA_LOW				    0x398
-#define MV64360_SRAM_ERROR_DATA_HIGH				    0x3a0
-#define MV64360_SRAM_ERROR_DATA_PARITY				    0x3a8
-
-/****************************************/
-/* SDRAM Configuration			*/
-/****************************************/
-
-#define MV64360_SDRAM_CONFIG					    0x1400
-#define MV64360_D_UNIT_CONTROL_LOW				    0x1404
-#define MV64360_D_UNIT_CONTROL_HIGH				    0x1424
-#define MV64360_SDRAM_TIMING_CONTROL_LOW			    0x1408
-#define MV64360_SDRAM_TIMING_CONTROL_HIGH			    0x140c
-#define MV64360_SDRAM_ADDR_CONTROL				    0x1410
-#define MV64360_SDRAM_OPEN_PAGES_CONTROL			    0x1414
-#define MV64360_SDRAM_OPERATION					    0x1418
-#define MV64360_SDRAM_MODE					    0x141c
-#define MV64360_EXTENDED_DRAM_MODE				    0x1420
-#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW			    0x1430
-#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH			    0x1434
-#define MV64360_SDRAM_CROSS_BAR_TIMEOUT				    0x1438
-#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION		    0x14c0
-#define MV64360_SDRAM_DATA_PADS_CALIBRATION			    0x14c4
-
-/****************************************/
-/* SDRAM Error Report			*/
-/****************************************/
-
-#define MV64360_SDRAM_ERROR_DATA_LOW				    0x1444
-#define MV64360_SDRAM_ERROR_DATA_HIGH				    0x1440
-#define MV64360_SDRAM_ERROR_ADDR				    0x1450
-#define MV64360_SDRAM_RECEIVED_ECC				    0x1448
-#define MV64360_SDRAM_CALCULATED_ECC				    0x144c
-#define MV64360_SDRAM_ECC_CONTROL				    0x1454
-#define MV64360_SDRAM_ECC_ERROR_COUNTER				    0x1458
-
-/******************************************/
-/*  Controlled Delay Line (CDL) Registers */
-/******************************************/
-
-#define MV64360_DFCDL_CONFIG0					    0x1480
-#define MV64360_DFCDL_CONFIG1					    0x1484
-#define MV64360_DLL_WRITE					    0x1488
-#define MV64360_DLL_READ					    0x148c
-#define MV64360_SRAM_ADDR					    0x1490
-#define MV64360_SRAM_DATA0					    0x1494
-#define MV64360_SRAM_DATA1					    0x1498
-#define MV64360_SRAM_DATA2					    0x149c
-#define MV64360_DFCL_PROBE					    0x14a0
-
-/******************************************/
-/*   Debug Registers			  */
-/******************************************/
-
-#define MV64360_DUNIT_DEBUG_LOW					    0x1460
-#define MV64360_DUNIT_DEBUG_HIGH				    0x1464
-#define MV64360_DUNIT_MMASK					    0X1b40
-
-/****************************************/
-/* Device Parameters			*/
-/****************************************/
-
-#define MV64360_DEVICE_BANK0_PARAMETERS				    0x45c
-#define MV64360_DEVICE_BANK1_PARAMETERS				    0x460
-#define MV64360_DEVICE_BANK2_PARAMETERS				    0x464
-#define MV64360_DEVICE_BANK3_PARAMETERS				    0x468
-#define MV64360_DEVICE_BOOT_BANK_PARAMETERS			    0x46c
-#define MV64360_DEVICE_INTERFACE_CONTROL			    0x4c0
-#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		    0x4c8
-#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		    0x4cc
-#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT		    0x4c4
-
-/****************************************/
-/* Device interrupt registers		*/
-/****************************************/
-
-#define MV64360_DEVICE_INTERRUPT_CAUSE				    0x4d0
-#define MV64360_DEVICE_INTERRUPT_MASK				    0x4d4
-#define MV64360_DEVICE_ERROR_ADDR				    0x4d8
-#define MV64360_DEVICE_ERROR_DATA				    0x4dc
-#define MV64360_DEVICE_ERROR_PARITY				    0x4e0
-
-/****************************************/
-/* Device debug registers		*/
-/****************************************/
-
-#define MV64360_DEVICE_DEBUG_LOW				    0x4e4
-#define MV64360_DEVICE_DEBUG_HIGH				    0x4e8
-#define MV64360_RUNIT_MMASK					    0x4f0
-
-/****************************************/
-/* PCI Slave Address Decoding registers */
-/****************************************/
-
-#define MV64360_PCI_0_CS_0_BANK_SIZE				    0xc08
-#define MV64360_PCI_1_CS_0_BANK_SIZE				    0xc88
-#define MV64360_PCI_0_CS_1_BANK_SIZE				    0xd08
-#define MV64360_PCI_1_CS_1_BANK_SIZE				    0xd88
-#define MV64360_PCI_0_CS_2_BANK_SIZE				    0xc0c
-#define MV64360_PCI_1_CS_2_BANK_SIZE				    0xc8c
-#define MV64360_PCI_0_CS_3_BANK_SIZE				    0xd0c
-#define MV64360_PCI_1_CS_3_BANK_SIZE				    0xd8c
-#define MV64360_PCI_0_DEVCS_0_BANK_SIZE				    0xc10
-#define MV64360_PCI_1_DEVCS_0_BANK_SIZE				    0xc90
-#define MV64360_PCI_0_DEVCS_1_BANK_SIZE				    0xd10
-#define MV64360_PCI_1_DEVCS_1_BANK_SIZE				    0xd90
-#define MV64360_PCI_0_DEVCS_2_BANK_SIZE				    0xd18
-#define MV64360_PCI_1_DEVCS_2_BANK_SIZE				    0xd98
-#define MV64360_PCI_0_DEVCS_3_BANK_SIZE				    0xc14
-#define MV64360_PCI_1_DEVCS_3_BANK_SIZE				    0xc94
-#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE			    0xd14
-#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE			    0xd94
-#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE				    0xd1c
-#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE				    0xd9c
-#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE				    0xd20
-#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE				    0xda0
-#define MV64360_PCI_0_P2P_I_O_BAR_SIZE				    0xd24
-#define MV64360_PCI_1_P2P_I_O_BAR_SIZE				    0xda4
-#define MV64360_PCI_0_CPU_BAR_SIZE				    0xd28
-#define MV64360_PCI_1_CPU_BAR_SIZE				    0xda8
-#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE			    0xe00
-#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE			    0xe80
-#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE			    0xd2c
-#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE			    0xd9c
-#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE			    0xc3c
-#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE			    0xcbc
-#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP			    0xc48
-#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP			    0xcc8
-#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP			    0xd48
-#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP			    0xdc8
-#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP			    0xc4c
-#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP			    0xccc
-#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP			    0xd4c
-#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP			    0xdcc
-#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP			    0xF04
-#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP			    0xF84
-#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP			    0xF08
-#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP			    0xF88
-#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP			    0xF0C
-#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP			    0xF8C
-#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP			    0xF10
-#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP			    0xF90
-#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP			    0xc50
-#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP			    0xcd0
-#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP			    0xd50
-#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP			    0xdd0
-#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP			    0xd58
-#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP			    0xdd8
-#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP			    0xc54
-#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP			    0xcd4
-#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xd54
-#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xdd4
-#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xd5c
-#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xddc
-#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xd60
-#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xde0
-#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xd64
-#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xde4
-#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xd68
-#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xde8
-#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP			    0xd6c
-#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP			    0xdec
-#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW			    0xd70
-#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW			    0xdf0
-#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH			    0xd74
-#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH			    0xdf4
-#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf00
-#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf80
-#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		    0xf38
-#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		    0xfb8
-#define MV64360_PCI_0_ADDR_DECODE_CONTROL			    0xd3c
-#define MV64360_PCI_1_ADDR_DECODE_CONTROL			    0xdbc
-#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL			    0xF40
-#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL			    0xFc0
-#define MV64360_PCI_0_HEADERS_RETARGET_BASE			    0xF44
-#define MV64360_PCI_1_HEADERS_RETARGET_BASE			    0xFc4
-#define MV64360_PCI_0_HEADERS_RETARGET_HIGH			    0xF48
-#define MV64360_PCI_1_HEADERS_RETARGET_HIGH			    0xFc8
-
-/***********************************/
-/*   PCI Control Register Map	   */
-/***********************************/
-
-#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND			    0x1d20
-#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND			    0x1da0
-#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL			    0x1d1C
-#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL			    0x1d9C
-#define MV64360_PCI_0_COMMAND					    0xc00
-#define MV64360_PCI_1_COMMAND					    0xc80
-#define MV64360_PCI_0_MODE					    0xd00
-#define MV64360_PCI_1_MODE					    0xd80
-#define MV64360_PCI_0_RETRY					    0xc04
-#define MV64360_PCI_1_RETRY					    0xc84
-#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER			    0xd04
-#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER			    0xd84
-#define MV64360_PCI_0_MSI_TRIGGER_TIMER				    0xc38
-#define MV64360_PCI_1_MSI_TRIGGER_TIMER				    0xcb8
-#define MV64360_PCI_0_ARBITER_CONTROL				    0x1d00
-#define MV64360_PCI_1_ARBITER_CONTROL				    0x1d80
-#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW			    0x1d08
-#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW			    0x1d88
-#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH			    0x1d0c
-#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH			    0x1d8c
-#define MV64360_PCI_0_CROSS_BAR_TIMEOUT				    0x1d04
-#define MV64360_PCI_1_CROSS_BAR_TIMEOUT				    0x1d84
-#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG			    0x1D18
-#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG			    0x1D98
-#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG			    0x1d10
-#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG			    0x1d90
-#define MV64360_PCI_0_P2P_CONFIG				    0x1d14
-#define MV64360_PCI_1_P2P_CONFIG				    0x1d94
-
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW			    0x1e00
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH		    0x1e04
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0			    0x1e08
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW			    0x1e10
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH		    0x1e14
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1			    0x1e18
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW			    0x1e20
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH		    0x1e24
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2			    0x1e28
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW			    0x1e30
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH		    0x1e34
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3			    0x1e38
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW			    0x1e40
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH		    0x1e44
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4			    0x1e48
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW			    0x1e50
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH		    0x1e54
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5			    0x1e58
-
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW			    0x1e80
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH		    0x1e84
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0			    0x1e88
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW			    0x1e90
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH		    0x1e94
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1			    0x1e98
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW			    0x1ea0
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH		    0x1ea4
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2			    0x1ea8
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW			    0x1eb0
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH		    0x1eb4
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3			    0x1eb8
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW			    0x1ec0
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH		    0x1ec4
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4			    0x1ec8
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW			    0x1ed0
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH		    0x1ed4
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5			    0x1ed8
-
-/****************************************/
-/*   PCI Configuration Access Registers */
-/****************************************/
-
-#define MV64360_PCI_0_CONFIG_ADDR				    0xcf8
-#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG			    0xcfc
-#define MV64360_PCI_1_CONFIG_ADDR				    0xc78
-#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG			    0xc7c
-#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xc34
-#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xcb4
-
-/****************************************/
-/*   PCI Error Report Registers		*/
-/****************************************/
-
-#define MV64360_PCI_0_SERR_MASK					    0xc28
-#define MV64360_PCI_1_SERR_MASK					    0xca8
-#define MV64360_PCI_0_ERROR_ADDR_LOW				    0x1d40
-#define MV64360_PCI_1_ERROR_ADDR_LOW				    0x1dc0
-#define MV64360_PCI_0_ERROR_ADDR_HIGH				    0x1d44
-#define MV64360_PCI_1_ERROR_ADDR_HIGH				    0x1dc4
-#define MV64360_PCI_0_ERROR_ATTRIBUTE				    0x1d48
-#define MV64360_PCI_1_ERROR_ATTRIBUTE				    0x1dc8
-#define MV64360_PCI_0_ERROR_COMMAND				    0x1d50
-#define MV64360_PCI_1_ERROR_COMMAND				    0x1dd0
-#define MV64360_PCI_0_ERROR_CAUSE				    0x1d58
-#define MV64360_PCI_1_ERROR_CAUSE				    0x1dd8
-#define MV64360_PCI_0_ERROR_MASK				    0x1d5c
-#define MV64360_PCI_1_ERROR_MASK				    0x1ddc
-
-/****************************************/
-/*   PCI Debug Registers		*/
-/****************************************/
-
-#define MV64360_PCI_0_MMASK					    0X1D24
-#define MV64360_PCI_1_MMASK					    0X1DA4
-
-/*********************************************/
-/* PCI Configuration, Function 0, Registers  */
-/*********************************************/
-
-#define MV64360_PCI_DEVICE_AND_VENDOR_ID			    0x000
-#define MV64360_PCI_STATUS_AND_COMMAND				    0x004
-#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID			    0x008
-#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	    0x00C
-
-#define MV64360_PCI_SCS_0_BASE_ADDR_LOW				    0x010
-#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH			    0x014
-#define MV64360_PCI_SCS_1_BASE_ADDR_LOW				    0x018
-#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH			    0x01C
-#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW	    0x020
-#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH	    0x024
-#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	    0x02c
-#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG			    0x030
-#define MV64360_PCI_CAPABILTY_LIST_POINTER			    0x034
-#define MV64360_PCI_INTERRUPT_PIN_AND_LINE			    0x03C
-       /* capability list */
-#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY			    0x040
-#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044
-#define MV64360_PCI_VPD_ADDR					    0x048
-#define MV64360_PCI_VPD_DATA					    0x04c
-#define MV64360_PCI_MSI_MESSAGE_CONTROL				    0x050
-#define MV64360_PCI_MSI_MESSAGE_ADDR				    0x054
-#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR			    0x058
-#define MV64360_PCI_MSI_MESSAGE_DATA				    0x05c
-#define MV64360_PCI_X_COMMAND					    0x060
-#define MV64360_PCI_X_STATUS					    0x064
-#define MV64360_PCI_COMPACT_PCI_HOT_SWAP			    0x068
-
-/***********************************************/
-/*   PCI Configuration, Function 1, Registers  */
-/***********************************************/
-
-#define MV64360_PCI_SCS_2_BASE_ADDR_LOW				    0x110
-#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH			    0x114
-#define MV64360_PCI_SCS_3_BASE_ADDR_LOW				    0x118
-#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH			    0x11c
-#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW			    0x120
-#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH		    0x124
-
-/***********************************************/
-/*  PCI Configuration, Function 2, Registers   */
-/***********************************************/
-
-#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW			    0x210
-#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH			    0x214
-#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW			    0x218
-#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH			    0x21c
-#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW			    0x220
-#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH			    0x224
-
-/***********************************************/
-/*  PCI Configuration, Function 3, Registers   */
-/***********************************************/
-
-#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW			    0x310
-#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH			    0x314
-#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW			    0x318
-#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH			    0x31c
-#define MV64360_PCI_CPU_BASE_ADDR_LOW				    0x220
-#define MV64360_PCI_CPU_BASE_ADDR_HIGH				    0x224
-
-/***********************************************/
-/*  PCI Configuration, Function 4, Registers   */
-/***********************************************/
-
-#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW			    0x410
-#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH			    0x414
-#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW			    0x418
-#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH			    0x41c
-#define MV64360_PCI_P2P_I_O_BASE_ADDR				    0x420
-#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR		    0x424
-
-/****************************************/
-/* Messaging Unit Registers (I20)	*/
-/****************************************/
-
-#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x010
-#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x014
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x018
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x01C
-#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE		    0x020
-#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x024
-#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x028
-#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE		    0x02C
-#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x030
-#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x034
-#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x040
-#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x044
-#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE		    0x050
-#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE		    0x054
-#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x060
-#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x064
-#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x068
-#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x06C
-#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x070
-#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x074
-#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x0F8
-#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x0FC
-
-#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x090
-#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x094
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x098
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x09C
-#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0A0
-#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0A4
-#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0A8
-#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0AC
-#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0B0
-#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0B4
-#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C0
-#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C4
-#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE		    0x0D0
-#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE		    0x0D4
-#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E0
-#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0E4
-#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E8
-#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x0EC
-#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0F0
-#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0F4
-#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x078
-#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x07C
-
-#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C10
-#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C14
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C18
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C1C
-#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C20
-#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C24
-#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C28
-#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C2C
-#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C30
-#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C34
-#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C40
-#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C44
-#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE			    0x1C50
-#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE		    0x1C54
-#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C60
-#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C64
-#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1C68
-#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1C6C
-#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C70
-#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C74
-#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1CF8
-#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1CFC
-#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C90
-#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C94
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C98
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C9C
-#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CA0
-#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CA4
-#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CA8
-#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CAC
-#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CB0
-#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CB4
-#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC0
-#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC4
-#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE			    0x1CD0
-#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE		    0x1CD4
-#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE0
-#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CE4
-#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE8
-#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1CEC
-#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CF0
-#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CF4
-#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1C78
-#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1C7C
-
-/****************************************/
-/*	  Ethernet Unit Registers		*/
-/****************************************/
-
-#define MV64360_ETH_PHY_ADDR_REG				    0x2000
-#define MV64360_ETH_SMI_REG					    0x2004
-#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG			    0x2008
-#define MV64360_ETH_UNIT_DEFAULTID_REG				    0x200c
-#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG			    0x2080
-#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG			    0x2084
-#define MV64360_ETH_UNIT_INTERNAL_USE_REG			    0x24fc
-#define MV64360_ETH_UNIT_ERROR_ADDR_REG				    0x2094
-#define MV64360_ETH_BAR_0					    0x2200
-#define MV64360_ETH_BAR_1					    0x2208
-#define MV64360_ETH_BAR_2					    0x2210
-#define MV64360_ETH_BAR_3					    0x2218
-#define MV64360_ETH_BAR_4					    0x2220
-#define MV64360_ETH_BAR_5					    0x2228
-#define MV64360_ETH_SIZE_REG_0					    0x2204
-#define MV64360_ETH_SIZE_REG_1					    0x220c
-#define MV64360_ETH_SIZE_REG_2					    0x2214
-#define MV64360_ETH_SIZE_REG_3					    0x221c
-#define MV64360_ETH_SIZE_REG_4					    0x2224
-#define MV64360_ETH_SIZE_REG_5					    0x222c
-#define MV64360_ETH_HEADERS_RETARGET_BASE_REG			    0x2230
-#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG		    0x2234
-#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0			    0x2280
-#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1			    0x2284
-#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2			    0x2288
-#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3			    0x228c
-#define MV64360_ETH_BASE_ADDR_ENABLE_REG			    0x2290
-#define MV64360_ETH_ACCESS_PROTECTION_REG(port)			   (0x2294 + (port<<2))
-#define MV64360_ETH_MIB_COUNTERS_BASE(port)			   (0x3000 + (port<<7))
-#define MV64360_ETH_PORT_CONFIG_REG(port)			   (0x2400 + (port<<10))
-#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port)		   (0x2404 + (port<<10))
-#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port)		   (0x2408 + (port<<10))
-#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port)		   (0x240c + (port<<10))
-#define MV64360_ETH_VLAN_ETHERTYPE_REG(port)			   (0x2410 + (port<<10))
-#define MV64360_ETH_MAC_ADDR_LOW(port)				   (0x2414 + (port<<10))
-#define MV64360_ETH_MAC_ADDR_HIGH(port)				   (0x2418 + (port<<10))
-#define MV64360_ETH_SDMA_CONFIG_REG(port)			   (0x241c + (port<<10))
-#define MV64360_ETH_DSCP_0(port)				   (0x2420 + (port<<10))
-#define MV64360_ETH_DSCP_1(port)				   (0x2424 + (port<<10))
-#define MV64360_ETH_DSCP_2(port)				   (0x2428 + (port<<10))
-#define MV64360_ETH_DSCP_3(port)				   (0x242c + (port<<10))
-#define MV64360_ETH_DSCP_4(port)				   (0x2430 + (port<<10))
-#define MV64360_ETH_DSCP_5(port)				   (0x2434 + (port<<10))
-#define MV64360_ETH_DSCP_6(port)				   (0x2438 + (port<<10))
-#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port)		   (0x243c + (port<<10))
-#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		   (0x2440 + (port<<10))
-#define MV64360_ETH_PORT_STATUS_REG(port)			   (0x2444 + (port<<10))
-#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port)		   (0x2448 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port)		   (0x244c + (port<<10))
-#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)	   (0x2450 + (port<<10))
-#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port)			   (0x2458 + (port<<10))
-#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)	   (0x245c + (port<<10))
-#define MV64360_ETH_INTERRUPT_CAUSE_REG(port)			   (0x2460 + (port<<10))
-#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port)		   (0x2464 + (port<<10))
-#define MV64360_ETH_INTERRUPT_MASK_REG(port)			   (0x2468 + (port<<10))
-#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port)		   (0x246c + (port<<10))
-#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2470 + (port<<10))
-#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2474 + (port<<10))
-#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port)		   (0x247c + (port<<10))
-#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port)		   (0x2484 + (port<<10)
-#define MV64360_ETH_PORT_DEBUG_0_REG(port)			   (0x248c + (port<<10))
-#define MV64360_ETH_PORT_DEBUG_1_REG(port)			   (0x2490 + (port<<10))
-#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)		   (0x2494 + (port<<10))
-#define MV64360_ETH_INTERNAL_USE_REG(port)			   (0x24fc + (port<<10))
-#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port)		   (0x2680 + (port<<10))
-#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port)		   (0x2684 + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x260c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x261c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x262c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x263c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x264c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x265c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x266c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x267c + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x26c0 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x26c4 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x26c8 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x26cc + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x26d0 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x26d4 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x26d8 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x26dc + (port<<10))
-#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)		   (0x2700 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)		   (0x2710 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)		   (0x2720 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)		   (0x2730 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)		   (0x2740 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)		   (0x2750 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)		   (0x2760 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)		   (0x2770 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)	   (0x2704 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)	   (0x2714 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)	   (0x2724 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)	   (0x2734 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)	   (0x2744 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)	   (0x2754 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)	   (0x2764 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)	   (0x2774 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port)		   (0x2708 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port)		   (0x2718 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port)		   (0x2728 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port)		   (0x2738 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port)		   (0x2748 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port)		   (0x2758 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port)		   (0x2768 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port)		   (0x2778 + (port<<10))
-#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)		   (0x2780 + (port<<10))
-#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
-#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)	   (0x3500 + (port<<10))
-#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port)		   (0x3600 + (port<<10))
-
-/*******************************************/
-/*	    CUNIT  Registers		   */
-/*******************************************/
-
-	 /* Address Decoding Register Map */
-
-#define MV64360_CUNIT_BASE_ADDR_REG0				    0xf200
-#define MV64360_CUNIT_BASE_ADDR_REG1				    0xf208
-#define MV64360_CUNIT_BASE_ADDR_REG2				    0xf210
-#define MV64360_CUNIT_BASE_ADDR_REG3				    0xf218
-#define MV64360_CUNIT_SIZE0					    0xf204
-#define MV64360_CUNIT_SIZE1					    0xf20c
-#define MV64360_CUNIT_SIZE2					    0xf214
-#define MV64360_CUNIT_SIZE3					    0xf21c
-#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0			    0xf240
-#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1			    0xf244
-#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG			    0xf250
-#define MV64360_MPSC0_ACCESS_PROTECTION_REG			    0xf254
-#define MV64360_MPSC1_ACCESS_PROTECTION_REG			    0xf258
-#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG		    0xf25C
-
-	/*  Error Report Registers  */
-
-#define MV64360_CUNIT_INTERRUPT_CAUSE_REG			    0xf310
-#define MV64360_CUNIT_INTERRUPT_MASK_REG			    0xf314
-#define MV64360_CUNIT_ERROR_ADDR				    0xf318
-
-	/*  Cunit Control Registers */
-
-#define MV64360_CUNIT_ARBITER_CONTROL_REG			    0xf300
-#define MV64360_CUNIT_CONFIG_REG				    0xb40c
-#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG			    0xf304
-
-	/*  Cunit Debug Registers   */
-
-#define MV64360_CUNIT_DEBUG_LOW					    0xf340
-#define MV64360_CUNIT_DEBUG_HIGH				    0xf344
-#define MV64360_CUNIT_MMASK					    0xf380
-
-	/*  Cunit Base Address Enable Window Bits*/
-#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT			 0x0
-#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT			 0x1
-#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT			 0x2
-#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT			 0x3
-
-	/*  MPSCs Clocks Routing Registers  */
-
-#define MV64360_MPSC_ROUTING_REG				    0xb400
-#define MV64360_MPSC_RX_CLOCK_ROUTING_REG			    0xb404
-#define MV64360_MPSC_TX_CLOCK_ROUTING_REG			    0xb408
-
-	/*  MPSCs Interrupts Registers	  */
-
-#define MV64360_MPSC_CAUSE_REG(port)				   (0xb804 + (port<<3))
-#define MV64360_MPSC_MASK_REG(port)				   (0xb884 + (port<<3))
-
-#define MV64360_MPSC_MAIN_CONFIG_LOW(port)			   (0x8000 + (port<<12))
-#define MV64360_MPSC_MAIN_CONFIG_HIGH(port)			   (0x8004 + (port<<12))
-#define MV64360_MPSC_PROTOCOL_CONFIG(port)			   (0x8008 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG1(port)				   (0x800c + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG2(port)				   (0x8010 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG3(port)				   (0x8014 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG4(port)				   (0x8018 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG5(port)				   (0x801c + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG6(port)				   (0x8020 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG7(port)				   (0x8024 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG8(port)				   (0x8028 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG9(port)				   (0x802c + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG10(port)			   (0x8030 + (port<<12))
-
-	/*  MPSC0 Registers	 */
-
-
-/***************************************/
-/*	    SDMA Registers	       */
-/***************************************/
-
-#define MV64360_SDMA_CONFIG_REG(channel)			(0x4000 + (channel<<13))
-#define MV64360_SDMA_COMMAND_REG(channel)			(0x4008 + (channel<<13))
-#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)	(0x4810 + (channel<<13))
-#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
-#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))
-
-#define MV64360_SDMA_CAUSE_REG					    0xb800
-#define MV64360_SDMA_MASK_REG					    0xb880
-
-
-/****************************************/
-/* SDMA Address Space Targets		*/
-/****************************************/
-
-#define MV64360_SDMA_DRAM_CS_0_TARGET				    0x0e00
-#define MV64360_SDMA_DRAM_CS_1_TARGET				    0x0d00
-#define MV64360_SDMA_DRAM_CS_2_TARGET				    0x0b00
-#define MV64360_SDMA_DRAM_CS_3_TARGET				    0x0700
-
-#define MV64360_SDMA_DEV_CS_0_TARGET				    0x1e01
-#define MV64360_SDMA_DEV_CS_1_TARGET				    0x1d01
-#define MV64360_SDMA_DEV_CS_2_TARGET				    0x1b01
-#define MV64360_SDMA_DEV_CS_3_TARGET				    0x1701
-
-#define MV64360_SDMA_BOOT_CS_TARGET				    0x0f00
-
-#define MV64360_SDMA_SRAM_TARGET				    0x0003
-#define MV64360_SDMA_60X_BUS_TARGET				    0x4003
-
-#define MV64360_PCI_0_TARGET					    0x0003
-#define MV64360_PCI_1_TARGET					    0x0004
-
-
-/* Devices BAR and size registers */
-
-#define MV64360_DEV_CS0_BASE_ADDR				    0x028
-#define MV64360_DEV_CS0_SIZE					    0x030
-#define MV64360_DEV_CS1_BASE_ADDR				    0x228
-#define MV64360_DEV_CS1_SIZE					    0x230
-#define MV64360_DEV_CS2_BASE_ADDR				    0x248
-#define MV64360_DEV_CS2_SIZE					    0x250
-#define MV64360_DEV_CS3_BASE_ADDR				    0x038
-#define MV64360_DEV_CS3_SIZE					    0x040
-#define MV64360_BOOTCS_BASE_ADDR				    0x238
-#define MV64360_BOOTCS_SIZE					    0x240
-
-/* SDMA Window access protection */
-#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0
-#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1
-#define MV64360_SDMA_WIN_ACCESS_FULL 2
-
-/* BRG Interrupts */
-
-#define MV64360_BRG_CONFIG_REG(brg)				 (0xb200 + (brg<<3))
-#define MV64360_BRG_BAUDE_TUNING_REG(brg)			 (0xb204 + (brg<<3))
-#define MV64360_BRG_CAUSE_REG					    0xb834
-#define MV64360_BRG_MASK_REG					    0xb8b4
-
-/****************************************/
-/* DMA Channel Control			*/
-/****************************************/
-
-#define MV64360_DMA_CHANNEL0_CONTROL				    0x840
-#define MV64360_DMA_CHANNEL0_CONTROL_HIGH			    0x880
-#define MV64360_DMA_CHANNEL1_CONTROL				    0x844
-#define MV64360_DMA_CHANNEL1_CONTROL_HIGH			    0x884
-#define MV64360_DMA_CHANNEL2_CONTROL				    0x848
-#define MV64360_DMA_CHANNEL2_CONTROL_HIGH			    0x888
-#define MV64360_DMA_CHANNEL3_CONTROL				    0x84C
-#define MV64360_DMA_CHANNEL3_CONTROL_HIGH			    0x88C
-
-
-/****************************************/
-/*	     IDMA Registers		*/
-/****************************************/
-
-#define MV64360_DMA_CHANNEL0_BYTE_COUNT				    0x800
-#define MV64360_DMA_CHANNEL1_BYTE_COUNT				    0x804
-#define MV64360_DMA_CHANNEL2_BYTE_COUNT				    0x808
-#define MV64360_DMA_CHANNEL3_BYTE_COUNT				    0x80C
-#define MV64360_DMA_CHANNEL0_SOURCE_ADDR			    0x810
-#define MV64360_DMA_CHANNEL1_SOURCE_ADDR			    0x814
-#define MV64360_DMA_CHANNEL2_SOURCE_ADDR			    0x818
-#define MV64360_DMA_CHANNEL3_SOURCE_ADDR			    0x81c
-#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR			    0x820
-#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR			    0x824
-#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR			    0x828
-#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR			    0x82C
-#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		    0x830
-#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		    0x834
-#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		    0x838
-#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		    0x83C
-#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		    0x870
-#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		    0x874
-#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		    0x878
-#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		    0x87C
-
- /*  IDMA Address Decoding Base Address Registers  */
-
-#define MV64360_DMA_BASE_ADDR_REG0				    0xa00
-#define MV64360_DMA_BASE_ADDR_REG1				    0xa08
-#define MV64360_DMA_BASE_ADDR_REG2				    0xa10
-#define MV64360_DMA_BASE_ADDR_REG3				    0xa18
-#define MV64360_DMA_BASE_ADDR_REG4				    0xa20
-#define MV64360_DMA_BASE_ADDR_REG5				    0xa28
-#define MV64360_DMA_BASE_ADDR_REG6				    0xa30
-#define MV64360_DMA_BASE_ADDR_REG7				    0xa38
-
- /*  IDMA Address Decoding Size Address Register   */
-
-#define MV64360_DMA_SIZE_REG0					    0xa04
-#define MV64360_DMA_SIZE_REG1					    0xa0c
-#define MV64360_DMA_SIZE_REG2					    0xa14
-#define MV64360_DMA_SIZE_REG3					    0xa1c
-#define MV64360_DMA_SIZE_REG4					    0xa24
-#define MV64360_DMA_SIZE_REG5					    0xa2c
-#define MV64360_DMA_SIZE_REG6					    0xa34
-#define MV64360_DMA_SIZE_REG7					    0xa3C
-
- /* IDMA Address Decoding High Address Remap and Access
-		  Protection Registers			  */
-
-#define MV64360_DMA_HIGH_ADDR_REMAP_REG0			    0xa60
-#define MV64360_DMA_HIGH_ADDR_REMAP_REG1			    0xa64
-#define MV64360_DMA_HIGH_ADDR_REMAP_REG2			    0xa68
-#define MV64360_DMA_HIGH_ADDR_REMAP_REG3			    0xa6C
-#define MV64360_DMA_BASE_ADDR_ENABLE_REG			    0xa80
-#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG		    0xa70
-#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG		    0xa74
-#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG		    0xa78
-#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG		    0xa7c
-#define MV64360_DMA_ARBITER_CONTROL				    0x860
-#define MV64360_DMA_CROSS_BAR_TIMEOUT				    0x8d0
-
- /*  IDMA Headers Retarget Registers   */
-
-#define MV64360_DMA_HEADERS_RETARGET_CONTROL			    0xa84
-#define MV64360_DMA_HEADERS_RETARGET_BASE			    0xa88
-
- /*  IDMA Interrupt Register  */
-
-#define MV64360_DMA_INTERRUPT_CAUSE_REG				    0x8c0
-#define MV64360_DMA_INTERRUPT_CAUSE_MASK			    0x8c4
-#define MV64360_DMA_ERROR_ADDR					    0x8c8
-#define MV64360_DMA_ERROR_SELECT				    0x8cc
-
- /*  IDMA Debug Register ( for internal use )	 */
-
-#define MV64360_DMA_DEBUG_LOW					    0x8e0
-#define MV64360_DMA_DEBUG_HIGH					    0x8e4
-#define MV64360_DMA_SPARE					    0xA8C
-
-/****************************************/
-/* Timer_Counter			*/
-/****************************************/
-
-#define MV64360_TIMER_COUNTER0					    0x850
-#define MV64360_TIMER_COUNTER1					    0x854
-#define MV64360_TIMER_COUNTER2					    0x858
-#define MV64360_TIMER_COUNTER3					    0x85C
-#define MV64360_TIMER_COUNTER_0_3_CONTROL			    0x864
-#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE		    0x868
-#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK		    0x86c
-
-/****************************************/
-/*	   Watchdog registers		*/
-/****************************************/
-
-#define MV64360_WATCHDOG_CONFIG_REG				    0xb410
-#define MV64360_WATCHDOG_VALUE_REG				    0xb414
-
-/****************************************/
-/* I2C Registers			*/
-/****************************************/
-
-#define MV64360_I2C_SLAVE_ADDR					    0xc000
-#define MV64360_I2C_EXTENDED_SLAVE_ADDR				    0xc010
-#define MV64360_I2C_DATA					    0xc004
-#define MV64360_I2C_CONTROL					    0xc008
-#define MV64360_I2C_STATUS_BAUDE_RATE				    0xc00C
-#define MV64360_I2C_SOFT_RESET					    0xc01c
-
-/****************************************/
-/* GPP Interface Registers		*/
-/****************************************/
-
-#define MV64360_GPP_IO_CONTROL					    0xf100
-#define MV64360_GPP_LEVEL_CONTROL				    0xf110
-#define MV64360_GPP_VALUE					    0xf104
-#define MV64360_GPP_INTERRUPT_CAUSE				    0xf108
-#define MV64360_GPP_INTERRUPT_MASK0				    0xf10c
-#define MV64360_GPP_INTERRUPT_MASK1				    0xf114
-#define MV64360_GPP_VALUE_SET					    0xf118
-#define MV64360_GPP_VALUE_CLEAR					    0xf11c
-
-/****************************************/
-/* Interrupt Controller Registers	*/
-/****************************************/
-
-/****************************************/
-/* Interrupts				*/
-/****************************************/
-
-#define MV64360_MAIN_INTERRUPT_CAUSE_LOW			    0x004
-#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH			    0x00c
-#define MV64360_CPU_INTERRUPT0_MASK_LOW				    0x014
-#define MV64360_CPU_INTERRUPT0_MASK_HIGH			    0x01c
-#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE			    0x024
-#define MV64360_CPU_INTERRUPT1_MASK_LOW				    0x034
-#define MV64360_CPU_INTERRUPT1_MASK_HIGH			    0x03c
-#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE			    0x044
-#define MV64360_INTERRUPT0_MASK_0_LOW				    0x054
-#define MV64360_INTERRUPT0_MASK_0_HIGH				    0x05c
-#define MV64360_INTERRUPT0_SELECT_CAUSE				    0x064
-#define MV64360_INTERRUPT1_MASK_0_LOW				    0x074
-#define MV64360_INTERRUPT1_MASK_0_HIGH				    0x07c
-#define MV64360_INTERRUPT1_SELECT_CAUSE				    0x084
-
-/****************************************/
-/*	MPP Interface Registers		*/
-/****************************************/
-
-#define MV64360_MPP_CONTROL0					    0xf000
-#define MV64360_MPP_CONTROL1					    0xf004
-#define MV64360_MPP_CONTROL2					    0xf008
-#define MV64360_MPP_CONTROL3					    0xf00c
-
-/****************************************/
-/*    Serial Initialization registers	*/
-/****************************************/
-
-#define MV64360_SERIAL_INIT_LAST_DATA				    0xf324
-#define MV64360_SERIAL_INIT_CONTROL				    0xf328
-#define MV64360_SERIAL_INIT_STATUS				    0xf32c
-
-
-#endif /* __INCgt64360rh */
diff --git a/board/Marvell/db64360/pci.c b/board/Marvell/db64360/pci.c
deleted file mode 100644
index 8c25198e3b2..00000000000
--- a/board/Marvell/db64360/pci.c
+++ /dev/null
@@ -1,923 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/* PCI.c - PCI functions */
-
-
-#include <common.h>
-#include <pci.h>
-
-#include "../include/pci.h"
-
-#undef DEBUG
-#undef IDE_SET_NATIVE_MODE
-static unsigned int local_buses[] = { 0, 0 };
-
-static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
-	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
-	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
-};
-
-
-#ifdef DEBUG
-static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
-static void gt_pci_bus_mode_display (PCI_HOST host)
-{
-	unsigned int mode;
-
-
-	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
-	switch (mode) {
-	case 0:
-		printf ("PCI %d bus mode: Conventional PCI\n", host);
-		break;
-	case 1:
-		printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
-		break;
-	case 2:
-		printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
-		break;
-	case 3:
-		printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
-		break;
-	default:
-		printf ("Unknown BUS %d\n", mode);
-	}
-}
-#endif
-
-static const unsigned int pci_p2p_configuration_reg[] = {
-	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-static const unsigned int pci_configuration_address[] = {
-	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
-};
-
-static const unsigned int pci_configuration_data[] = {
-	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
-	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
-};
-
-static const unsigned int pci_error_cause_reg[] = {
-	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
-};
-
-static const unsigned int pci_arbiter_control[] = {
-	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
-};
-
-static const unsigned int pci_address_space_en[] = {
-	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
-};
-
-static const unsigned int pci_snoop_control_base_0_low[] = {
-	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_snoop_control_top_0[] = {
-	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
-};
-
-static const unsigned int pci_access_control_base_0_low[] = {
-	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_access_control_top_0[] = {
-	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
-};
-
-static const unsigned int pci_scs_bank_size[2][4] = {
-	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
-	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
-	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
-	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
-};
-
-static const unsigned int pci_p2p_configuration[] = {
-	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-
-/********************************************************************
-* pciWriteConfigReg - Write to a PCI configuration register
-*                    - Make sure the GT is configured as a master before writing
-*                      to another device on the PCI.
-*                    - The function takes care of Big/Little endian conversion.
-*
-*
-* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
-*                   (or any other PCI device spec)
-*           pciDevNum: The device number needs to be addressed.
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|00|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*********************************************************************/
-void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
-			unsigned int pciDevNum, unsigned int data)
-{
-	volatile unsigned int DataForAddrReg;
-	unsigned int functionNum;
-	unsigned int busNum = 0;
-	unsigned int addr;
-
-	if (pciDevNum > 32)	/* illegal device Number */
-		return;
-	if (pciDevNum == SELF) {	/* configure our configuration space. */
-		pciDevNum =
-			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
-			0x1f;
-		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
-			0xff0000;
-	}
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xfc;
-	DataForAddrReg =
-		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
-	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
-	GT_REG_READ (pci_configuration_address[host], &addr);
-	if (addr != DataForAddrReg)
-		return;
-	GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-/********************************************************************
-* pciReadConfigReg  - Read from a PCI0 configuration register
-*                    - Make sure the GT is configured as a master before reading
-*                     from another device on the PCI.
-*                   - The function takes care of Big/Little endian conversion.
-* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
-*                        spec)
-*           pciDevNum: The device number needs to be addressed.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-*                 cause register to make sure the data is valid
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|00|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*********************************************************************/
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
-			       unsigned int pciDevNum)
-{
-	volatile unsigned int DataForAddrReg;
-	unsigned int data;
-	unsigned int functionNum;
-	unsigned int busNum = 0;
-
-	if (pciDevNum > 32)	/* illegal device Number */
-		return 0xffffffff;
-	if (pciDevNum == SELF) {	/* configure our configuration space. */
-		pciDevNum =
-			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
-			0x1f;
-		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
-			0xff0000;
-	}
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xfc;
-	DataForAddrReg =
-		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
-	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
-	GT_REG_READ (pci_configuration_address[host], &data);
-	if (data != DataForAddrReg)
-		return 0xffffffff;
-	GT_REG_READ (pci_configuration_data[host], &data);
-	return data;
-}
-
-/********************************************************************
-* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
-*                               the agent is placed on another Bus. For more
-*                               information read P2P in the PCI spec.
-*
-* Inputs:   unsigned int regOffset - The register offset as it apears in the
-*           GT spec (or any other PCI device spec).
-*           unsigned int pciDevNum - The device number needs to be addressed.
-*           unsigned int busNum - On which bus does the Target agent connect
-*                                 to.
-*           unsigned int data - data to be written.
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|01|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
-*   PCI spec referring to P2P.
-*
-*********************************************************************/
-void pciOverBridgeWriteConfigReg (PCI_HOST host,
-				  unsigned int regOffset,
-				  unsigned int pciDevNum,
-				  unsigned int busNum, unsigned int data)
-{
-	unsigned int DataForReg;
-	unsigned int functionNum;
-
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xff;
-	busNum = busNum << 16;
-	if (pciDevNum == SELF) {	/* This board */
-		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
-	} else {
-		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
-			BIT31 | BIT0;
-	}
-	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
-	GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-
-/********************************************************************
-* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
-*                               the agent target locate on another PCI bus.
-*                             - Make sure the GT is configured as a master
-*                               before reading from another device on the PCI.
-*                             - The function takes care of Big/Little endian
-*                               conversion.
-* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
-*                        spec). (configuration register offset.)
-*           pciDevNum: The device number needs to be addressed.
-*           busNum: the Bus number where the agent is place.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-*                 cause register to make sure the data is valid
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|01|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*********************************************************************/
-unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
-					 unsigned int regOffset,
-					 unsigned int pciDevNum,
-					 unsigned int busNum)
-{
-	unsigned int DataForReg;
-	unsigned int data;
-	unsigned int functionNum;
-
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xff;
-	busNum = busNum << 16;
-	if (pciDevNum == SELF) {	/* This board */
-		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
-	} else {		/* agent on another bus */
-
-		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
-			BIT0 | BIT31;
-	}
-	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
-	GT_REG_READ (pci_configuration_data[host], &data);
-	return data;
-}
-
-
-/********************************************************************
-* pciGetRegOffset - Gets the register offset for this region config.
-*
-* INPUT:   Bus, Region - The bus and region we ask for its base address.
-* OUTPUT:   N/A
-* RETURNS: PCI register base address
-*********************************************************************/
-static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
-{
-	switch (host) {
-	case PCI_HOST0:
-		switch (region) {
-		case PCI_IO:
-			return PCI_0I_O_LOW_DECODE_ADDRESS;
-		case PCI_REGION0:
-			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-		case PCI_REGION1:
-			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
-		case PCI_REGION2:
-			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
-		case PCI_REGION3:
-			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
-		}
-	case PCI_HOST1:
-		switch (region) {
-		case PCI_IO:
-			return PCI_1I_O_LOW_DECODE_ADDRESS;
-		case PCI_REGION0:
-			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
-		case PCI_REGION1:
-			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
-		case PCI_REGION2:
-			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
-		case PCI_REGION3:
-			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
-		}
-	}
-	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-}
-
-static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
-{
-	switch (host) {
-	case PCI_HOST0:
-		switch (region) {
-		case PCI_IO:
-			return PCI_0I_O_ADDRESS_REMAP;
-		case PCI_REGION0:
-			return PCI_0MEMORY0_ADDRESS_REMAP;
-		case PCI_REGION1:
-			return PCI_0MEMORY1_ADDRESS_REMAP;
-		case PCI_REGION2:
-			return PCI_0MEMORY2_ADDRESS_REMAP;
-		case PCI_REGION3:
-			return PCI_0MEMORY3_ADDRESS_REMAP;
-		}
-	case PCI_HOST1:
-		switch (region) {
-		case PCI_IO:
-			return PCI_1I_O_ADDRESS_REMAP;
-		case PCI_REGION0:
-			return PCI_1MEMORY0_ADDRESS_REMAP;
-		case PCI_REGION1:
-			return PCI_1MEMORY1_ADDRESS_REMAP;
-		case PCI_REGION2:
-			return PCI_1MEMORY2_ADDRESS_REMAP;
-		case PCI_REGION3:
-			return PCI_1MEMORY3_ADDRESS_REMAP;
-		}
-	}
-	return PCI_0MEMORY0_ADDRESS_REMAP;
-}
-
-/********************************************************************
-* pciGetBaseAddress - Gets the base address of a PCI.
-*           - If the PCI size is 0 then this base address has no meaning!!!
-*
-*
-* INPUT:   Bus, Region - The bus and region we ask for its base address.
-* OUTPUT:   N/A
-* RETURNS: PCI base address.
-*********************************************************************/
-unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int regBase;
-	unsigned int regEnd;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &regBase);
-	GT_REG_READ (regOffset + 8, &regEnd);
-
-	if (regEnd <= regBase)
-		return 0xffffffff;	/* ERROR !!! */
-
-	regBase = regBase << 16;
-	return regBase;
-}
-
-bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
-		  unsigned int bankBase, unsigned int bankLength)
-{
-	unsigned int low = 0xfff;
-	unsigned int high = 0x0;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-	unsigned int remapOffset = pciGetRemapOffset (host, region);
-
-	if (bankLength != 0) {
-		low = (bankBase >> 16) & 0xffff;
-		high = ((bankBase + bankLength) >> 16) - 1;
-	}
-
-	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
-	GT_REG_WRITE (regOffset + 8, high);
-
-	if (bankLength != 0) {	/* must do AFTER writing maps */
-		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
-								   dont support upper 32
-								   in this driver */
-	}
-	return true;
-}
-
-unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int low;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &low);
-	return (low & 0xffff) << 16;
-}
-
-unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int low, high;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &low);
-	GT_REG_READ (regOffset + 8, &high);
-	return ((high & 0xffff) + 1) << 16;
-}
-
-
-/* ronen - 7/Dec/03*/
-/********************************************************************
-* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
-* Inputs: one of the PCI BAR
-*********************************************************************/
-void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
-	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
-	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-/********************************************************************
-* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
-*
-* Inputs: base and size of PCI SCS
-*********************************************************************/
-void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
-		       unsigned int pciDramBase, unsigned int pciDramSize)
-{
-	/*ronen different function for 3rd bank. */
-	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
-
-	pciDramBase = pciDramBase & 0xfffff000;
-	pciDramBase = pciDramBase | (pciReadConfigReg (host,
-						       PCI_SCS_0_BASE_ADDRESS
-						       + offset,
-						       SELF) & 0x00000fff);
-	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
-			   pciDramBase);
-	if (pciDramSize == 0)
-		pciDramSize++;
-	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
-	gtPciEnableInternalBAR (host, bank);
-}
-
-/********************************************************************
-* pciSetRegionFeatures - This function modifys one of the 8 regions with
-*                         feature bits given as an input.
-*                       - Be advised to check the spec before modifying them.
-* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
-*         unsigned int features - See file: pci.h there are defintion for those
-*                                 region features.
-*         unsigned int baseAddress - The region base Address.
-*         unsigned int topAddress - The region top Address.
-* Returns: false if one of the parameters is erroneous true otherwise.
-*********************************************************************/
-bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
-			   unsigned int features, unsigned int baseAddress,
-			   unsigned int regionLength)
-{
-	unsigned int accessLow;
-	unsigned int accessHigh;
-	unsigned int accessTop = baseAddress + regionLength;
-
-	if (regionLength == 0) {	/* close the region. */
-		pciDisableAccessRegion (host, region);
-		return true;
-	}
-	/* base Address is store is bits [11:0] */
-	accessLow = (baseAddress & 0xfff00000) >> 20;
-	/* All the features are update according to the defines in pci.h (to be on
-	   the safe side we disable bits: [11:0] */
-	accessLow = accessLow | (features & 0xfffff000);
-	/* write to the Low Access Region register */
-	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
-		      accessLow);
-
-	accessHigh = (accessTop & 0xfff00000) >> 20;
-
-	/* write to the High Access Region register */
-	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
-		      accessHigh - 1);
-	return true;
-}
-
-/********************************************************************
-* pciDisableAccessRegion - Disable The given Region by writing MAX size
-*                           to its low Address and MIN size to its high Address.
-*
-* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
-* Returns:  N/A.
-*********************************************************************/
-void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
-{
-	/* writing back the registers default values. */
-	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
-		      0x01001fff);
-	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
-}
-
-/********************************************************************
-* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
-*
-* Inputs:   N/A
-* Returns:  true.
-*********************************************************************/
-bool pciArbiterEnable (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
-	return true;
-}
-
-/********************************************************************
-* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
-*
-* Inputs:   N/A
-* Returns:  true
-*********************************************************************/
-bool pciArbiterDisable (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
-	return true;
-}
-
-/********************************************************************
-* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
-*
-* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
-*           PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
-*           PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
-*           PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
-*           PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
-*           PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
-*           PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
-* Returns:  true
-*********************************************************************/
-bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
-				  PCI_AGENT_PRIO externalAgent0,
-				  PCI_AGENT_PRIO externalAgent1,
-				  PCI_AGENT_PRIO externalAgent2,
-				  PCI_AGENT_PRIO externalAgent3,
-				  PCI_AGENT_PRIO externalAgent4,
-				  PCI_AGENT_PRIO externalAgent5)
-{
-	unsigned int regData;
-	unsigned int writeData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
-		(externalAgent1 << 9) + (externalAgent2 << 10) +
-		(externalAgent3 << 11) + (externalAgent4 << 12) +
-		(externalAgent5 << 13);
-	regData = (regData & 0xffffc07f) | writeData;
-	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
-	return true;
-}
-
-/********************************************************************
-* pciParkingDisable - Park on last option disable, with this function you can
-*                      disable the park on last mechanism for each agent.
-*                      disabling this option for all agents results parking
-*                      on the internal master.
-*
-* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
-*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
-*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
-*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
-*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
-*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
-*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
-* Returns:  true
-*********************************************************************/
-bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
-			PCI_AGENT_PARK externalAgent0,
-			PCI_AGENT_PARK externalAgent1,
-			PCI_AGENT_PARK externalAgent2,
-			PCI_AGENT_PARK externalAgent3,
-			PCI_AGENT_PARK externalAgent4,
-			PCI_AGENT_PARK externalAgent5)
-{
-	unsigned int regData;
-	unsigned int writeData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
-		(externalAgent1 << 16) + (externalAgent2 << 17) +
-		(externalAgent3 << 18) + (externalAgent4 << 19) +
-		(externalAgent5 << 20);
-	regData = (regData & ~(0x7f << 14)) | writeData;
-	GT_REG_WRITE (pci_arbiter_control[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
-*                       respond to grant assertion within a window specified in
-*                       the input value: 'brokenValue'.
-*
-* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
-*                       grant without asserting frame.
-* Returns:  Error for illegal broken value otherwise true.
-*********************************************************************/
-bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
-{
-	unsigned int data;
-	unsigned int regData;
-
-	if (brokenValue > 0xf)
-		return false;	/* brokenValue must be 4 bit */
-	data = brokenValue << 3;
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	regData = (regData & 0xffffff87) | data;
-	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
-	return true;
-}
-
-/********************************************************************
-* pciDisableBrokenAgentDetection - This function disable the Broken agent
-*                           Detection mechanism.
-*                           NOTE: This operation may cause a dead lock on the
-*                           pci0 arbitration.
-*
-* Inputs:   N/A
-* Returns:  true.
-*********************************************************************/
-bool pciDisableBrokenAgentDetection (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	regData = regData & 0xfffffffd;
-	GT_REG_WRITE (pci_arbiter_control[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciP2PConfig - This function set the PCI_n P2P configurate.
-*                 For more information on the P2P read PCI spec.
-*
-* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
-*                                      Boundry.
-*          unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
-*                                      Boundry.
-*          unsigned int busNum - The CPI bus number to which the PCI interface
-*                                      is connected.
-*          unsigned int devNum - The PCI interface's device number.
-*
-* Returns:  true.
-*********************************************************************/
-bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
-		   unsigned int SecondBusHigh,
-		   unsigned int busNum, unsigned int devNum)
-{
-	unsigned int regData;
-
-	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
-		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
-	GT_REG_WRITE (pci_p2p_configuration[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
-*                          supports Cache Coherency in the PCI_n interface.
-* Inputs: region - One of the four regions.
-*         snoopType - There is four optional Types:
-*                        1. No Snoop.
-*                        2. Snoop to WT region.
-*                        3. Snoop to WB region.
-*                        4. Snoop & Invalidate to WB region.
-*         baseAddress - Base Address of this region.
-*         regionLength - Region length.
-* Returns: false if one of the parameters is wrong otherwise return true.
-*********************************************************************/
-bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
-			    PCI_SNOOP_TYPE snoopType,
-			    unsigned int baseAddress,
-			    unsigned int regionLength)
-{
-	unsigned int snoopXbaseAddress;
-	unsigned int snoopXtopAddress;
-	unsigned int data;
-	unsigned int snoopHigh = baseAddress + regionLength;
-
-	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
-		return false;
-	snoopXbaseAddress =
-		pci_snoop_control_base_0_low[host] + 0x10 * region;
-	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
-	if (regionLength == 0) {	/* closing the region */
-		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
-		GT_REG_WRITE (snoopXtopAddress, 0);
-		return true;
-	}
-	baseAddress = baseAddress & 0xfff00000;	/* Granularity of 1MByte */
-	data = (baseAddress >> 20) | snoopType << 12;
-	GT_REG_WRITE (snoopXbaseAddress, data);
-	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
-	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
-	return true;
-}
-
-static int gt_read_config_dword (struct pci_controller *hose,
-				 pci_dev_t dev, int offset, u32 * value)
-{
-	int bus = PCI_BUS (dev);
-
-	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
-		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
-					   PCI_DEV (dev));
-	} else {
-		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
-						     cfg_addr, offset,
-						     PCI_DEV (dev), bus);
-	}
-
-	return 0;
-}
-
-static int gt_write_config_dword (struct pci_controller *hose,
-				  pci_dev_t dev, int offset, u32 value)
-{
-	int bus = PCI_BUS (dev);
-
-	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
-		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
-				   PCI_DEV (dev), value);
-	} else {
-		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
-					     offset, PCI_DEV (dev), bus,
-					     value);
-	}
-	return 0;
-}
-
-
-static void gt_setup_ide (struct pci_controller *hose,
-			  pci_dev_t dev, struct pci_config_table *entry)
-{
-	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
-	u32 bar_response, bar_value;
-	int bar;
-
-	for (bar = 0; bar < 6; bar++) {
-		/*ronen different function for 3rd bank. */
-		unsigned int offset =
-			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
-
-		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
-					0x0);
-		pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
-				       &bar_response);
-
-		pciauto_region_allocate (bar_response &
-					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
-					 pci_io : hose->pci_mem, ide_bar[bar],
-					 &bar_value);
-
-		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
-					bar_value);
-	}
-}
-
-
-/* TODO BJW: Change this for DB64360. This was pulled from the EV64260  */
-/* and is curently not called *. */
-#if 0
-static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
-{
-	unsigned char pin, irq;
-
-	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
-
-	if (pin == 1) {		/* only allow INT A */
-		irq = pci_irq_swizzle[(PCI_HOST) hose->
-				      cfg_addr][PCI_DEV (dev)];
-		if (irq)
-			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
-	}
-}
-#endif
-
-struct pci_config_table gt_config_table[] = {
-	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
-	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
-
-	{}
-};
-
-struct pci_controller pci0_hose = {
-/*    fixup_irq: gt_fixup_irq, */
-	config_table:gt_config_table,
-};
-
-struct pci_controller pci1_hose = {
-/*    fixup_irq: gt_fixup_irq, */
-	config_table:gt_config_table,
-};
-
-void pci_init_board (void)
-{
-	unsigned int command;
-
-#ifdef DEBUG
-	gt_pci_bus_mode_display (PCI_HOST0);
-#endif
-
-	pci0_hose.first_busno = 0;
-	pci0_hose.last_busno = 0xff;
-	local_buses[0] = pci0_hose.first_busno;
-
-	/* PCI memory space */
-	pci_set_region (pci0_hose.regions + 0,
-			CONFIG_SYS_PCI0_0_MEM_SPACE,
-			CONFIG_SYS_PCI0_0_MEM_SPACE,
-			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region (pci0_hose.regions + 1,
-			CONFIG_SYS_PCI0_IO_SPACE_PCI,
-			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
-
-	pci_set_ops (&pci0_hose,
-		     pci_hose_read_config_byte_via_dword,
-		     pci_hose_read_config_word_via_dword,
-		     gt_read_config_dword,
-		     pci_hose_write_config_byte_via_dword,
-		     pci_hose_write_config_word_via_dword,
-		     gt_write_config_dword);
-	pci0_hose.region_count = 2;
-
-	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
-
-	pci_register_hose (&pci0_hose);
-	pciArbiterEnable (PCI_HOST0);
-	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
-	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MASTER;
-	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MEMORY;
-	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-
-	pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
-
-#ifdef DEBUG
-	gt_pci_bus_mode_display (PCI_HOST1);
-#endif
-	pci1_hose.first_busno = pci0_hose.last_busno + 1;
-	pci1_hose.last_busno = 0xff;
-	pci1_hose.current_busno = pci1_hose.first_busno;
-	local_buses[1] = pci1_hose.first_busno;
-
-	/* PCI memory space */
-	pci_set_region (pci1_hose.regions + 0,
-			CONFIG_SYS_PCI1_0_MEM_SPACE,
-			CONFIG_SYS_PCI1_0_MEM_SPACE,
-			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region (pci1_hose.regions + 1,
-			CONFIG_SYS_PCI1_IO_SPACE_PCI,
-			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
-
-	pci_set_ops (&pci1_hose,
-		     pci_hose_read_config_byte_via_dword,
-		     pci_hose_read_config_word_via_dword,
-		     gt_read_config_dword,
-		     pci_hose_write_config_byte_via_dword,
-		     pci_hose_write_config_word_via_dword,
-		     gt_write_config_dword);
-
-	pci1_hose.region_count = 2;
-
-	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
-
-	pci_register_hose (&pci1_hose);
-
-	pciArbiterEnable (PCI_HOST1);
-	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
-
-	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MASTER;
-	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-	pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
-
-	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MEMORY;
-	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-}
diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c
deleted file mode 100644
index 5954b4cea24..00000000000
--- a/board/Marvell/db64360/sdram_init.c
+++ /dev/null
@@ -1,1945 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*************************************************************************
- * adaption for the Marvell DB64360 Board
- * Ingo Assmus (ingo.assmus@keymile.com)
- ************************************************************************/
-
-
-/* sdram_init.c - automatic memory sizing */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include "../include/memory.h"
-#include "../include/pci.h"
-#include "../include/mv_gen_reg.h"
-#include <net.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "../common/i2c.h"
-#include "64360.h"
-#include "mv_regs.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define MAP_PCI
-
-int set_dfcdlInit (void);	/* setup delay line of Mv64360 */
-int mvDmaIsChannelActive (int);
-int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
-int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
-
-/* ------------------------------------------------------------------------- */
-
-int
-memory_map_bank (unsigned int bankNo,
-		 unsigned int bankBase, unsigned int bankLength)
-{
-#ifdef MAP_PCI
-	PCI_HOST host;
-#endif
-
-
-#ifdef DEBUG
-	if (bankLength > 0) {
-		printf ("mapping bank %d at %08x - %08x\n",
-			bankNo, bankBase, bankBase + bankLength - 1);
-	} else {
-		printf ("unmapping bank %d\n", bankNo);
-	}
-#endif
-
-	memoryMapBank (bankNo, bankBase, bankLength);
-
-#ifdef MAP_PCI
-	for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
-		const int features =
-			PREFETCH_ENABLE |
-			DELAYED_READ_ENABLE |
-			AGGRESSIVE_PREFETCH |
-			READ_LINE_AGGRESSIVE_PREFETCH |
-			READ_MULTI_AGGRESSIVE_PREFETCH |
-			MAX_BURST_4 | PCI_NO_SWAP;
-
-		pciMapMemoryBank (host, bankNo, bankBase, bankLength);
-
-		pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
-				       bankLength);
-
-		pciSetRegionFeatures (host, bankNo, features, bankBase,
-				      bankLength);
-	}
-#endif
-	return 0;
-}
-
-#define GB	   (1 << 30)
-
-/* much of this code is based on (or is) the code in the pip405 port */
-/* thanks go to the authors of said port - Josh */
-
-/* structure to store the relevant information about an sdram bank */
-typedef struct sdram_info {
-	uchar drb_size;
-	uchar registered, ecc;
-	uchar tpar;
-	uchar tras_clocks;
-	uchar burst_len;
-	uchar banks, slot;
-} sdram_info_t;
-
-/* Typedefs for 'gtAuxilGetDIMMinfo' function */
-
-typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE;
-
-typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
-	SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
-} VOLTAGE_INTERFACE;
-
-typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 =
-		4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 =
-		32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR;
-typedef enum _max_CL_supported_SD { SD_CL_1 =
-		1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7,
-		SD_FAULT } MAX_CL_SUPPORTED_SD;
-
-
-/* SDRAM/DDR information struct */
-typedef struct _gtMemoryDimmInfo {
-	MEMORY_TYPE memoryType;
-	unsigned int numOfRowAddresses;
-	unsigned int numOfColAddresses;
-	unsigned int numOfModuleBanks;
-	unsigned int dataWidth;
-	VOLTAGE_INTERFACE voltageInterface;
-	unsigned int errorCheckType;	/* ECC , PARITY.. */
-	unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
-	unsigned int errorCheckDataWidth;	/* 0 - no, 1 - Yes */
-	unsigned int minClkDelay;
-	unsigned int burstLengthSupported;
-	unsigned int numOfBanksOnEachDevice;
-	unsigned int suportedCasLatencies;
-	unsigned int RefreshInterval;
-	unsigned int maxCASlatencySupported_LoP;	/* LoP left of point (measured in ns) */
-	unsigned int maxCASlatencySupported_RoP;	/* RoP right of point (measured in ns) */
-	MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
-	MAX_CL_SUPPORTED_SD maxClSupported_SD;
-	unsigned int moduleBankDensity;
-	/* module attributes (true for yes) */
-	bool bufferedAddrAndControlInputs;
-	bool registeredAddrAndControlInputs;
-	bool onCardPLL;
-	bool bufferedDQMBinputs;
-	bool registeredDQMBinputs;
-	bool differentialClockInput;
-	bool redundantRowAddressing;
-
-	/* module general attributes */
-	bool suportedAutoPreCharge;
-	bool suportedPreChargeAll;
-	bool suportedEarlyRasPreCharge;
-	bool suportedWrite1ReadBurst;
-	bool suported5PercentLowVCC;
-	bool suported5PercentUpperVCC;
-	/* module timing parameters */
-	unsigned int minRasToCasDelay;
-	unsigned int minRowActiveRowActiveDelay;
-	unsigned int minRasPulseWidth;
-	unsigned int minRowPrechargeTime;	/* measured in ns */
-
-	int addrAndCommandHoldTime;	/* LoP left of point (measured in ns) */
-	int addrAndCommandSetupTime;	/* (measured in ns/100) */
-	int dataInputSetupTime; /* LoP left of point (measured in ns) */
-	int dataInputHoldTime;	/* LoP left of point (measured in ns) */
-/* tAC times for highest 2nd and 3rd highest CAS Latency values */
-	unsigned int clockToDataOut_LoP;	/* LoP left of point (measured in ns) */
-	unsigned int clockToDataOut_RoP;	/* RoP right of point (measured in ns) */
-	unsigned int clockToDataOutMinus1_LoP;	/* LoP left of point (measured in ns) */
-	unsigned int clockToDataOutMinus1_RoP;	/* RoP right of point (measured in ns) */
-	unsigned int clockToDataOutMinus2_LoP;	/* LoP left of point (measured in ns) */
-	unsigned int clockToDataOutMinus2_RoP;	/* RoP right of point (measured in ns) */
-
-	unsigned int minimumCycleTimeAtMaxCasLatancy_LoP;	/* LoP left of point (measured in ns) */
-	unsigned int minimumCycleTimeAtMaxCasLatancy_RoP;	/* RoP right of point (measured in ns) */
-
-	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
-	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
-
-	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
-	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
-
-	/* Parameters calculated from
-	   the extracted DIMM information */
-	unsigned int size;
-	unsigned int deviceDensity;	/* 16,64,128,256 or 512 Mbit */
-	unsigned int numberOfDevices;
-	uchar drb_size;		/* DRAM size in n*64Mbit */
-	uchar slot;		/* Slot Number this module is inserted in */
-	uchar spd_raw_data[128];	/* Content of SPD-EEPROM copied 1:1 */
-#ifdef DEBUG
-	uchar manufactura[8];	/* Content of SPD-EEPROM Byte 64-71 */
-	uchar modul_id[18];	/* Content of SPD-EEPROM Byte 73-90 */
-	uchar vendor_data[27];	/* Content of SPD-EEPROM Byte 99-125 */
-	unsigned long modul_serial_no;	/* Content of SPD-EEPROM Byte 95-98 */
-	unsigned int manufac_date;	/* Content of SPD-EEPROM Byte 93-94 */
-	unsigned int modul_revision;	/* Content of SPD-EEPROM Byte 91-92 */
-	uchar manufac_place;	/* Content of SPD-EEPROM Byte 72 */
-
-#endif
-} AUX_MEM_DIMM_INFO;
-
-
-/*
- * translate ns.ns/10 coding of SPD timing values
- * into 10 ps unit values
- */
-static inline unsigned short NS10to10PS (unsigned char spd_byte)
-{
-	unsigned short ns, ns10;
-
-	/* isolate upper nibble */
-	ns = (spd_byte >> 4) & 0x0F;
-	/* isolate lower nibble */
-	ns10 = (spd_byte & 0x0F);
-
-	return (ns * 100 + ns10 * 10);
-}
-
-/*
- * translate ns coding of SPD timing values
- * into 10 ps unit values
- */
-static inline unsigned short NSto10PS (unsigned char spd_byte)
-{
-	return (spd_byte * 100);
-}
-
-/* This code reads the SPD chip on the sdram and populates
- * the array which is passed in with the relevant information */
-/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
-static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
-{
-	unsigned long spd_checksum;
-
-#ifdef ZUMA_NTL
-	/* zero all the values */
-	memset (info, 0, sizeof (*info));
-
-/*
-	if (!slot) {
-	    info->slot = 0;
-	    info->banks = 1;
-	    info->registered = 0;
-		    info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */
-/*	    info->tpar = 3;
-	    info->tras_clocks = 5;
-	    info->burst_len = 4;
-*/
-#ifdef CONFIG_MV64360_ECC
-	/* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
-	dimmInfo->errorCheckType = 2;
-/*	    info->ecc = 2;*/
-#endif
-}
-
-return 0;
-
-#else
-	uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
-	int ret;
-	unsigned int i, j, density = 1;
-
-#ifdef DEBUG
-	unsigned int k;
-#endif
-	unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
-	int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
-	uchar supp_cal, cal_val;
-	ulong memclk, tmemclk;
-	ulong tmp;
-	uchar trp_clocks = 0, tras_clocks;
-	uchar data[128];
-
-	memclk = gd->bus_clk;
-	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */
-
-	debug("before i2c read\n");
-
-	ret = i2c_read (addr, 0, 1, data, 128);
-
-	debug("after i2c read\n");
-
-	/* zero all the values */
-	memset (dimmInfo, 0, sizeof (*dimmInfo));
-
-	/* copy the SPD content 1:1 into the dimmInfo structure */
-	for (i = 0; i <= 127; i++) {
-		dimmInfo->spd_raw_data[i] = data[i];
-	}
-
-	if (ret) {
-		debug("No DIMM in slot %d [err = %x]\n", slot, ret);
-		return 0;
-	} else
-		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
-
-#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
-
-	for (i = 0; i <= 127; i++) {
-		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
-			data[i]);
-	}
-
-#endif
-#ifdef DEBUG
-/* find Manufactura of Dimm Module */
-	for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
-		dimmInfo->manufactura[i] = data[64 + i];
-	}
-	printf ("\nThis RAM-Module is produced by:		%s\n",
-		dimmInfo->manufactura);
-
-/* find Manul-ID of Dimm Module */
-	for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
-		dimmInfo->modul_id[i] = data[73 + i];
-	}
-	printf ("The Module-ID of this RAM-Module is:		%s\n",
-		dimmInfo->modul_id);
-
-/* find Vendor-Data of Dimm Module */
-	for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
-		dimmInfo->vendor_data[i] = data[99 + i];
-	}
-	printf ("Vendor Data of this RAM-Module is:		%s\n",
-		dimmInfo->vendor_data);
-
-/* find modul_serial_no of Dimm Module */
-	dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
-	printf ("Serial No. of this RAM-Module is:		%ld (%lx)\n",
-		dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
-
-/* find Manufac-Data of Dimm Module */
-	dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
-	printf ("Manufactoring Date of this RAM-Module is:	%d.%d\n", data[93], data[94]);	/*dimmInfo->manufac_date */
-
-/* find modul_revision of Dimm Module */
-	dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
-	printf ("Module Revision of this RAM-Module is:			%d.%d\n", data[91], data[92]);	/* dimmInfo->modul_revision */
-
-/* find manufac_place of Dimm Module */
-	dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
-	printf ("manufac_place of this RAM-Module is:		%d\n",
-		dimmInfo->manufac_place);
-
-#endif
-
-/*------------------------------------------------------------------------------------------------------------------------------*/
-/* calculate SPD checksum */
-/*------------------------------------------------------------------------------------------------------------------------------*/
-	spd_checksum = 0;
-
-	for (i = 0; i <= 62; i++) {
-		spd_checksum += data[i];
-	}
-
-	if ((spd_checksum & 0xff) != data[63]) {
-		printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
-		hang ();
-	}
-
-	else
-		printf ("SPD Checksum ok!\n");
-
-
-/*------------------------------------------------------------------------------------------------------------------------------*/
-	for (i = 2; i <= 35; i++) {
-		switch (i) {
-		case 2: /* Memory type (DDR / SDRAM) */
-			dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
-			if (dimmInfo->memoryType == 0)
-				debug
-				    ("Dram_type in slot %d is:			SDRAM\n",
-				     dimmInfo->slot);
-			if (dimmInfo->memoryType == 1)
-				debug
-				    ("Dram_type in slot %d is:			DDRAM\n",
-				     dimmInfo->slot);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 3: /* Number Of Row Addresses */
-			dimmInfo->numOfRowAddresses = data[i];
-			debug
-			    ("Module Number of row addresses:		%d\n",
-			     dimmInfo->numOfRowAddresses);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 4: /* Number Of Column Addresses */
-			dimmInfo->numOfColAddresses = data[i];
-			debug
-			    ("Module Number of col addresses:		%d\n",
-			     dimmInfo->numOfColAddresses);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 5: /* Number Of Module Banks */
-			dimmInfo->numOfModuleBanks = data[i];
-			debug
-			    ("Number of Banks on Mod. :					%d\n",
-			     dimmInfo->numOfModuleBanks);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 6: /* Data Width */
-			dimmInfo->dataWidth = data[i];
-			debug
-			    ("Module Data Width:				%d\n",
-			     dimmInfo->dataWidth);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 8: /* Voltage Interface */
-			switch (data[i]) {
-			case 0x0:
-				dimmInfo->voltageInterface = TTL_5V_TOLERANT;
-				debug
-				    ("Module is						TTL_5V_TOLERANT\n");
-				break;
-			case 0x1:
-				dimmInfo->voltageInterface = LVTTL;
-				debug
-				    ("Module is						LVTTL\n");
-				break;
-			case 0x2:
-				dimmInfo->voltageInterface = HSTL_1_5V;
-				debug
-				    ("Module is						TTL_5V_TOLERANT\n");
-				break;
-			case 0x3:
-				dimmInfo->voltageInterface = SSTL_3_3V;
-				debug
-				    ("Module is						HSTL_1_5V\n");
-				break;
-			case 0x4:
-				dimmInfo->voltageInterface = SSTL_2_5V;
-				debug
-				    ("Module is						SSTL_2_5V\n");
-				break;
-			default:
-				dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
-				debug
-				    ("Module is						VOLTAGE_UNKNOWN\n");
-				break;
-			}
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 9: /* Minimum Cycle Time At Max CasLatancy */
-			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
-			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
-			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
-			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
-				leftOfPoint;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
-				rightOfPoint;
-			debug
-			    ("Minimum Cycle Time At Max CasLatancy:		%d.%d [ns]\n",
-			     leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 10:	/* Clock To Data Out */
-			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
-			time_tmp =
-				(((data[i] & 0xf0) >> 4) * 10) +
-				((data[i] & 0x0f));
-			leftOfPoint = time_tmp / div;
-			rightOfPoint = time_tmp % div;
-			dimmInfo->clockToDataOut_LoP = leftOfPoint;
-			dimmInfo->clockToDataOut_RoP = rightOfPoint;
-			debug("Clock To Data Out:					%d.%2d [ns]\n", leftOfPoint, rightOfPoint);	/*dimmInfo->clockToDataOut */
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-/*#ifdef CONFIG_ECC */
-		case 11:	/* Error Check Type */
-			dimmInfo->errorCheckType = data[i];
-			debug
-			    ("Error Check Type (0=NONE):			%d\n",
-			     dimmInfo->errorCheckType);
-			break;
-/* #endif */
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 12:	/* Refresh Interval */
-			dimmInfo->RefreshInterval = data[i];
-			debug
-			    ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
-			     dimmInfo->RefreshInterval);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 13:	/* Sdram Width */
-			dimmInfo->sdramWidth = data[i];
-			debug
-			    ("Sdram Width:					%d\n",
-			     dimmInfo->sdramWidth);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 14:	/* Error Check Data Width */
-			dimmInfo->errorCheckDataWidth = data[i];
-			debug
-			    ("Error Check Data Width:			%d\n",
-			     dimmInfo->errorCheckDataWidth);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 15:	/* Minimum Clock Delay */
-			dimmInfo->minClkDelay = data[i];
-			debug
-			    ("Minimum Clock Delay:				%d\n",
-			     dimmInfo->minClkDelay);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 16:	/* Burst Length Supported */
-			   /******-******-******-*******
-			   * bit3 | bit2 | bit1 | bit0 *
-			   *******-******-******-*******
-	    burst length = *  8	  |  4	 |   2	|   1  *
-			   *****************************
-
-	    If for example bit0 and bit2 are set, the burst
-	    length supported are 1 and 4. */
-
-			dimmInfo->burstLengthSupported = data[i];
-#ifdef DEBUG
-			debug
-			    ("Burst Length Supported:			");
-			if (dimmInfo->burstLengthSupported & 0x01)
-				debug("1, ");
-			if (dimmInfo->burstLengthSupported & 0x02)
-				debug("2, ");
-			if (dimmInfo->burstLengthSupported & 0x04)
-				debug("4, ");
-			if (dimmInfo->burstLengthSupported & 0x08)
-				debug("8, ");
-			debug(" Bit \n");
-#endif
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 17:	/* Number Of Banks On Each Device */
-			dimmInfo->numOfBanksOnEachDevice = data[i];
-			debug
-			    ("Number Of Banks On Each Chip:			%d\n",
-			     dimmInfo->numOfBanksOnEachDevice);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 18:	/* Suported Cas Latencies */
-
-			/*     DDR:
-			 *******-******-******-******-******-******-******-*******
-			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
-			 *******-******-******-******-******-******-******-*******
-			 CAS =	 * TBD	| TBD  | 3.5  |	  3  | 2.5  |  2   | 1.5  |   1	 *
-			 *********************************************************
-			 SDRAM:
-			 *******-******-******-******-******-******-******-*******
-			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
-			 *******-******-******-******-******-******-******-*******
-			 CAS =	 * TBD	|  7   |  6   |	 5   |	4   |  3   |   2  |   1	 *
-			 ********************************************************/
-			dimmInfo->suportedCasLatencies = data[i];
-#ifdef DEBUG
-			debug
-			    ("Suported Cas Latencies: (CL)			");
-			if (dimmInfo->memoryType == 0) {	/* SDRAM */
-				for (k = 0; k <= 7; k++) {
-					if (dimmInfo->
-					    suportedCasLatencies & (1 << k))
-						debug
-						    ("%d,			",
-						     k + 1);
-				}
-
-			} else {	/* DDR-RAM */
-
-				if (dimmInfo->suportedCasLatencies & 1)
-					debug("1, ");
-				if (dimmInfo->suportedCasLatencies & 2)
-					debug("1.5, ");
-				if (dimmInfo->suportedCasLatencies & 4)
-					debug("2, ");
-				if (dimmInfo->suportedCasLatencies & 8)
-					debug("2.5, ");
-				if (dimmInfo->suportedCasLatencies & 16)
-					debug("3, ");
-				if (dimmInfo->suportedCasLatencies & 32)
-					debug("3.5, ");
-
-			}
-			debug("\n");
-#endif
-			/* Calculating MAX CAS latency */
-			for (j = 7; j > 0; j--) {
-				if (((dimmInfo->
-				      suportedCasLatencies >> j) & 0x1) ==
-				    1) {
-					switch (dimmInfo->memoryType) {
-					case DDR:
-						/* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
-						switch (j) {
-						case 7:
-							debug
-							    ("Max. Cas Latencies (DDR):				ERROR !!!\n");
-							dimmInfo->
-								maxClSupported_DDR
-								=
-								DDR_CL_FAULT;
-							hang ();
-							break;
-						case 6:
-							debug
-							    ("Max. Cas Latencies (DDR):				ERROR !!!\n");
-							dimmInfo->
-								maxClSupported_DDR
-								=
-								DDR_CL_FAULT;
-							hang ();
-							break;
-						case 5:
-							debug
-							    ("Max. Cas Latencies (DDR):				3.5 clk's\n");
-							dimmInfo->
-								maxClSupported_DDR
-								= DDR_CL_3_5;
-							break;
-						case 4:
-							debug
-							    ("Max. Cas Latencies (DDR):				3 clk's \n");
-							dimmInfo->
-								maxClSupported_DDR
-								= DDR_CL_3;
-							break;
-						case 3:
-							debug
-							    ("Max. Cas Latencies (DDR):				2.5 clk's \n");
-							dimmInfo->
-								maxClSupported_DDR
-								= DDR_CL_2_5;
-							break;
-						case 2:
-							debug
-							    ("Max. Cas Latencies (DDR):				2 clk's \n");
-							dimmInfo->
-								maxClSupported_DDR
-								= DDR_CL_2;
-							break;
-						case 1:
-							debug
-							    ("Max. Cas Latencies (DDR):				1.5 clk's \n");
-							dimmInfo->
-								maxClSupported_DDR
-								= DDR_CL_1_5;
-							break;
-						}
-
-						/* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy
-						   lower then our SDRAM cycle count, we won't be able to support this CAL
-						   and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */
-						if ((dimmInfo->
-						     minimumCycleTimeAtMaxCasLatancy_LoP
-						     <
-						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
-						    ||
-						    ((dimmInfo->
-						      minimumCycleTimeAtMaxCasLatancy_LoP
-						      ==
-						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
-						     && (dimmInfo->
-							 minimumCycleTimeAtMaxCasLatancy_RoP
-							 <
-							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
-						{
-							dimmInfo->
-								maxClSupported_DDR
-								=
-								dimmInfo->
-								maxClSupported_DDR
-								>> 1;
-							debug
-							    ("*** Change actual Cas Latencies cause of minimumCycleTime n");
-						}
-						/* ronen - checkif the Dimm frequency compared to the Sysclock. */
-						if ((dimmInfo->
-						     minimumCycleTimeAtMaxCasLatancy_LoP
-						     >
-						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
-						    ||
-						    ((dimmInfo->
-						      minimumCycleTimeAtMaxCasLatancy_LoP
-						      ==
-						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
-						     && (dimmInfo->
-							 minimumCycleTimeAtMaxCasLatancy_RoP
-							 >
-							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
-						{
-							printf ("*********************************************************\n");
-							printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
-							printf ("*********************************************************\n");
-							hang ();
-						}
-
-						dimmInfo->
-							maxCASlatencySupported_LoP
-							=
-							1 +
-							(int) (5 * j / 10);
-						if (((5 * j) % 10) != 0)
-							dimmInfo->
-								maxCASlatencySupported_RoP
-								= 5;
-						else
-							dimmInfo->
-								maxCASlatencySupported_RoP
-								= 0;
-						debug
-						    ("Max. Cas Latencies (DDR LoP.RoP Notation):	%d.%d \n",
-						     dimmInfo->
-						     maxCASlatencySupported_LoP,
-						     dimmInfo->
-						     maxCASlatencySupported_RoP);
-						break;
-					case SDRAM:
-						/* CAS latency 1, 2, 3, 4, 5, 6, 7 */
-						dimmInfo->maxClSupported_SD = j;	/*  Cas Latency DDR-RAM Coded			*/
-						debug
-						    ("Max. Cas Latencies (SD): %d\n",
-						     dimmInfo->
-						     maxClSupported_SD);
-						dimmInfo->
-							maxCASlatencySupported_LoP
-							= j;
-						dimmInfo->
-							maxCASlatencySupported_RoP
-							= 0;
-						debug
-						    ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
-						     dimmInfo->
-						     maxCASlatencySupported_LoP,
-						     dimmInfo->
-						     maxCASlatencySupported_RoP);
-						break;
-					}
-					break;
-				}
-			}
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 21:	/* Buffered Address And Control Inputs */
-			debug("\nModul Attributes (SPD Byte 21): \n");
-			dimmInfo->bufferedAddrAndControlInputs =
-				data[i] & BIT0;
-			dimmInfo->registeredAddrAndControlInputs =
-				(data[i] & BIT1) >> 1;
-			dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
-			dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
-			dimmInfo->registeredDQMBinputs =
-				(data[i] & BIT4) >> 4;
-			dimmInfo->differentialClockInput =
-				(data[i] & BIT5) >> 5;
-			dimmInfo->redundantRowAddressing =
-				(data[i] & BIT6) >> 6;
-#ifdef DEBUG
-			if (dimmInfo->bufferedAddrAndControlInputs == 1)
-				debug
-				    (" - Buffered Address/Control Input:		Yes \n");
-			else
-				debug
-				    (" - Buffered Address/Control Input:		No \n");
-
-			if (dimmInfo->registeredAddrAndControlInputs == 1)
-				debug
-				    (" - Registered Address/Control Input:		Yes \n");
-			else
-				debug
-				    (" - Registered Address/Control Input:		No \n");
-
-			if (dimmInfo->onCardPLL == 1)
-				debug
-				    (" - On-Card PLL (clock):				Yes \n");
-			else
-				debug
-				    (" - On-Card PLL (clock):				No \n");
-
-			if (dimmInfo->bufferedDQMBinputs == 1)
-				debug
-				    (" - Bufferd DQMB Inputs:				Yes \n");
-			else
-				debug
-				    (" - Bufferd DQMB Inputs:				No \n");
-
-			if (dimmInfo->registeredDQMBinputs == 1)
-				debug
-				    (" - Registered DQMB Inputs:			Yes \n");
-			else
-				debug
-				    (" - Registered DQMB Inputs:			No \n");
-
-			if (dimmInfo->differentialClockInput == 1)
-				debug
-				    (" - Differential Clock Input:			Yes \n");
-			else
-				debug
-				    (" - Differential Clock Input:			No \n");
-
-			if (dimmInfo->redundantRowAddressing == 1)
-				debug
-				    (" - redundant Row Addressing:			Yes \n");
-			else
-				debug
-				    (" - redundant Row Addressing:			No \n");
-
-#endif
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 22:	/* Suported AutoPreCharge */
-			debug("\nModul Attributes (SPD Byte 22): \n");
-			dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
-			dimmInfo->suportedAutoPreCharge =
-				(data[i] & BIT1) >> 1;
-			dimmInfo->suportedPreChargeAll =
-				(data[i] & BIT2) >> 2;
-			dimmInfo->suportedWrite1ReadBurst =
-				(data[i] & BIT3) >> 3;
-			dimmInfo->suported5PercentLowVCC =
-				(data[i] & BIT4) >> 4;
-			dimmInfo->suported5PercentUpperVCC =
-				(data[i] & BIT5) >> 5;
-#ifdef DEBUG
-			if (dimmInfo->suportedEarlyRasPreCharge == 1)
-				debug
-				    (" - Early Ras Precharge:			Yes \n");
-			else
-				debug
-				    (" -  Early Ras Precharge:			No \n");
-
-			if (dimmInfo->suportedAutoPreCharge == 1)
-				debug
-				    (" - AutoPreCharge:				Yes \n");
-			else
-				debug
-				    (" -  AutoPreCharge:				No \n");
-
-			if (dimmInfo->suportedPreChargeAll == 1)
-				debug
-				    (" - Precharge All:				Yes \n");
-			else
-				debug
-				    (" -  Precharge All:				No \n");
-
-			if (dimmInfo->suportedWrite1ReadBurst == 1)
-				debug
-				    (" - Write 1/ReadBurst:				Yes \n");
-			else
-				debug
-				    (" -  Write 1/ReadBurst:				No \n");
-
-			if (dimmInfo->suported5PercentLowVCC == 1)
-				debug
-				    (" - lower VCC tolerance:			5 Percent \n");
-			else
-				debug
-				    ("	- lower VCC tolerance:			10 Percent \n");
-
-			if (dimmInfo->suported5PercentUpperVCC == 1)
-				debug
-				    (" - upper VCC tolerance:			5 Percent \n");
-			else
-				debug
-				    (" -  upper VCC tolerance:			10 Percent \n");
-
-#endif
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 23:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
-			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
-			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
-			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
-			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
-				leftOfPoint;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
-				rightOfPoint;
-			debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint);	/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 24:	/* Clock To Data Out 2nd highest Cas Latency Value */
-			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
-			time_tmp =
-				(((data[i] & 0xf0) >> 4) * 10) +
-				((data[i] & 0x0f));
-			leftOfPoint = time_tmp / div;
-			rightOfPoint = time_tmp % div;
-			dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
-			dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
-			debug
-			    ("Clock To Data Out (2nd CL value):			%d.%2d [ns]\n",
-			     leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 25:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
-			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
-			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
-			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
-			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
-				leftOfPoint;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
-				rightOfPoint;
-			debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint);	/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 26:	/* Clock To Data Out 3rd highest Cas Latency Value */
-			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
-			time_tmp =
-				(((data[i] & 0xf0) >> 4) * 10) +
-				((data[i] & 0x0f));
-			leftOfPoint = time_tmp / div;
-			rightOfPoint = time_tmp % div;
-			dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
-			dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
-			debug
-			    ("Clock To Data Out (3rd CL value):			%d.%2d [ns]\n",
-			     leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 27:	/* Minimum Row Precharge Time */
-			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
-			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
-			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
-			dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint);	/* measured in n times 10ps Intervals */
-			trp_clocks =
-				(dimmInfo->minRowPrechargeTime +
-				 (tmemclk - 1)) / tmemclk;
-			debug
-			    ("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
-			     tmemclk, tmemclk / 100, tmemclk % 100);
-			debug
-			    ("Minimum Row Precharge Time [ns]:		%d.%2d = in Clk cycles %d\n",
-			     leftOfPoint, rightOfPoint, trp_clocks);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 28:	/* Minimum Row Active to Row Active Time */
-			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
-			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
-			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
-			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
-			debug
-			    ("Minimum Row Active -To- Row Active Delay [ns]:	%d.%2d = in Clk cycles %d\n",
-			     leftOfPoint, rightOfPoint, trp_clocks);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 29:	/* Minimum Ras-To-Cas Delay */
-			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
-			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
-			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
-			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
-			debug
-			    ("Minimum Ras-To-Cas Delay [ns]:			%d.%2d = in Clk cycles %d\n",
-			     leftOfPoint, rightOfPoint, trp_clocks);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 30:	/* Minimum Ras Pulse Width */
-			dimmInfo->minRasPulseWidth = data[i];
-			tras_clocks =
-				(NSto10PS (data[i]) +
-				 (tmemclk - 1)) / tmemclk;
-			debug
-			    ("Minimum Ras Pulse Width [ns]:			%d = in Clk cycles %d\n",
-			     dimmInfo->minRasPulseWidth, tras_clocks);
-
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 31:	/* Module Bank Density */
-			dimmInfo->moduleBankDensity = data[i];
-			debug
-			    ("Module Bank Density:				%d\n",
-			     dimmInfo->moduleBankDensity);
-#ifdef DEBUG
-			debug
-			    ("*** Offered Densities (more than 1 = Multisize-Module): ");
-			{
-				if (dimmInfo->moduleBankDensity & 1)
-					debug("4MB, ");
-				if (dimmInfo->moduleBankDensity & 2)
-					debug("8MB, ");
-				if (dimmInfo->moduleBankDensity & 4)
-					debug("16MB, ");
-				if (dimmInfo->moduleBankDensity & 8)
-					debug("32MB, ");
-				if (dimmInfo->moduleBankDensity & 16)
-					debug("64MB, ");
-				if (dimmInfo->moduleBankDensity & 32)
-					debug("128MB, ");
-				if ((dimmInfo->moduleBankDensity & 64)
-				    || (dimmInfo->moduleBankDensity & 128)) {
-					debug("ERROR, ");
-					hang ();
-				}
-			}
-			debug("\n");
-#endif
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 32:	/* Address And Command Setup Time (measured in ns/1000) */
-			sign = 1;
-			switch (dimmInfo->memoryType) {
-			case DDR:
-				time_tmp =
-					(((data[i] & 0xf0) >> 4) * 10) +
-					((data[i] & 0x0f));
-				leftOfPoint = time_tmp / 100;
-				rightOfPoint = time_tmp % 100;
-				break;
-			case SDRAM:
-				leftOfPoint = (data[i] & 0xf0) >> 4;
-				if (leftOfPoint > 7) {
-					leftOfPoint = data[i] & 0x70 >> 4;
-					sign = -1;
-				}
-				rightOfPoint = (data[i] & 0x0f);
-				break;
-			}
-			dimmInfo->addrAndCommandSetupTime =
-				(leftOfPoint * 100 + rightOfPoint) * sign;
-			debug
-			    ("Address And Command Setup Time [ns]:		%d.%d\n",
-			     sign * leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 33:	/* Address And Command Hold Time */
-			sign = 1;
-			switch (dimmInfo->memoryType) {
-			case DDR:
-				time_tmp =
-					(((data[i] & 0xf0) >> 4) * 10) +
-					((data[i] & 0x0f));
-				leftOfPoint = time_tmp / 100;
-				rightOfPoint = time_tmp % 100;
-				break;
-			case SDRAM:
-				leftOfPoint = (data[i] & 0xf0) >> 4;
-				if (leftOfPoint > 7) {
-					leftOfPoint = data[i] & 0x70 >> 4;
-					sign = -1;
-				}
-				rightOfPoint = (data[i] & 0x0f);
-				break;
-			}
-			dimmInfo->addrAndCommandHoldTime =
-				(leftOfPoint * 100 + rightOfPoint) * sign;
-			debug
-			    ("Address And Command Hold Time [ns]:		%d.%d\n",
-			     sign * leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 34:	/* Data Input Setup Time */
-			sign = 1;
-			switch (dimmInfo->memoryType) {
-			case DDR:
-				time_tmp =
-					(((data[i] & 0xf0) >> 4) * 10) +
-					((data[i] & 0x0f));
-				leftOfPoint = time_tmp / 100;
-				rightOfPoint = time_tmp % 100;
-				break;
-			case SDRAM:
-				leftOfPoint = (data[i] & 0xf0) >> 4;
-				if (leftOfPoint > 7) {
-					leftOfPoint = data[i] & 0x70 >> 4;
-					sign = -1;
-				}
-				rightOfPoint = (data[i] & 0x0f);
-				break;
-			}
-			dimmInfo->dataInputSetupTime =
-				(leftOfPoint * 100 + rightOfPoint) * sign;
-			debug
-			    ("Data Input Setup Time [ns]:			%d.%d\n",
-			     sign * leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 35:	/* Data Input Hold Time */
-			sign = 1;
-			switch (dimmInfo->memoryType) {
-			case DDR:
-				time_tmp =
-					(((data[i] & 0xf0) >> 4) * 10) +
-					((data[i] & 0x0f));
-				leftOfPoint = time_tmp / 100;
-				rightOfPoint = time_tmp % 100;
-				break;
-			case SDRAM:
-				leftOfPoint = (data[i] & 0xf0) >> 4;
-				if (leftOfPoint > 7) {
-					leftOfPoint = data[i] & 0x70 >> 4;
-					sign = -1;
-				}
-				rightOfPoint = (data[i] & 0x0f);
-				break;
-			}
-			dimmInfo->dataInputHoldTime =
-				(leftOfPoint * 100 + rightOfPoint) * sign;
-			debug
-			    ("Data Input Hold Time [ns]:			%d.%d\n\n",
-			     sign * leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-		}
-	}
-	/* calculating the sdram density */
-	for (i = 0;
-	     i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
-	     i++) {
-		density = density * 2;
-	}
-	dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
-		dimmInfo->sdramWidth;
-	dimmInfo->numberOfDevices =
-		(dimmInfo->dataWidth / dimmInfo->sdramWidth) *
-		dimmInfo->numOfModuleBanks;
-	if ((dimmInfo->errorCheckType == 0x1)
-	    || (dimmInfo->errorCheckType == 0x2)
-	    || (dimmInfo->errorCheckType == 0x3)) {
-		dimmInfo->size =
-			(dimmInfo->deviceDensity / 8) *
-			(dimmInfo->numberOfDevices -
-			 /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */
-			 dimmInfo->numberOfDevices / 8);
-	} else {
-		dimmInfo->size =
-			(dimmInfo->deviceDensity / 8) *
-			dimmInfo->numberOfDevices;
-	}
-
-	/* compute the module DRB size */
-	tmp = (1 <<
-	       (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
-	tmp *= dimmInfo->numOfModuleBanks;
-	tmp *= dimmInfo->sdramWidth;
-	tmp = tmp >> 24;	/* div by 0x4000000 (64M)	*/
-	dimmInfo->drb_size = (uchar) tmp;
-	debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
-
-	/* try a CAS latency of 3 first... */
-
-	/* bit 1 is CL2, bit 2 is CL3 */
-	supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1;
-
-	cal_val = 0;
-	if (supp_cal & 3) {
-		if (NS10to10PS (data[9]) <= tmemclk)
-			cal_val = 3;
-	}
-
-	/* then 2... */
-	if (supp_cal & 2) {
-		if (NS10to10PS (data[23]) <= tmemclk)
-			cal_val = 2;
-	}
-
-	debug("cal_val = %d\n", cal_val);
-
-	/* bummer, did't work... */
-	if (cal_val == 0) {
-		debug("Couldn't find a good CAS latency\n");
-		hang ();
-		return 0;
-	}
-
-	return true;
-
-#endif
-}
-
-/* sets up the GT properly with information passed in */
-int setup_sdram (AUX_MEM_DIMM_INFO * info)
-{
-	ulong tmp, check;
-	ulong tmp_sdram_mode = 0;	/* 0x141c */
-	ulong tmp_dunit_control_low = 0;	/* 0x1404 */
-	int i;
-
-	/* added 8/21/2003 P. Marchese */
-	unsigned int sdram_config_reg;
-
-	/* added 10/10/2003 P. Marchese */
-	ulong sdram_chip_size;
-
-	/* sanity checking */
-	if (!info->numOfModuleBanks) {
-		printf ("setup_sdram called with 0 banks\n");
-		return 1;
-	}
-
-	/* delay line */
-	set_dfcdlInit ();	/* may be its not needed */
-	debug("Delay line set done\n");
-
-	/* set SDRAM mode NOP */ /* To_do check it */
-	GT_REG_WRITE (SDRAM_OPERATION, 0x5);
-	while (GTREGREAD (SDRAM_OPERATION) != 0) {
-		debug
-		    ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
-	}
-
-	/* SDRAM configuration */
-/* added 8/21/2003 P. Marchese */
-/* code allows usage of registered DIMMS */
-
-	/* figure out the memory refresh internal */
-	switch (info->RefreshInterval) {
-	case 0x0:
-	case 0x80:		/* refresh period is 15.625 usec */
-		sdram_config_reg =
-			(unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_CLK)
-					/ (float) 1000000.0);
-		break;
-	case 0x1:
-	case 0x81:		/* refresh period is 3.9 usec */
-		sdram_config_reg =
-			(unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_CLK) /
-					(float) 1000000.0);
-		break;
-	case 0x2:
-	case 0x82:		/* refresh period is 7.8 usec */
-		sdram_config_reg =
-			(unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_CLK) /
-					(float) 1000000.0);
-		break;
-	case 0x3:
-	case 0x83:		/* refresh period is 31.3 usec */
-		sdram_config_reg =
-			(unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_CLK) /
-					(float) 1000000.0);
-		break;
-	case 0x4:
-	case 0x84:		/* refresh period is 62.5 usec */
-		sdram_config_reg =
-			(unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_CLK) /
-					(float) 1000000.0);
-		break;
-	case 0x5:
-	case 0x85:		/* refresh period is 125 usec */
-		sdram_config_reg =
-			(unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_CLK) /
-					(float) 1000000.0);
-		break;
-	default:		/* refresh period undefined */
-		printf ("DRAM refresh period is unknown!\n");
-		printf ("Aborting DRAM setup with an error\n");
-		hang ();
-		break;
-	}
-	debug("calculated refresh interval %0x\n", sdram_config_reg);
-
-	/* make sure the refresh value is only 14 bits */
-	if (sdram_config_reg > 0x1fff)
-		sdram_config_reg = 0x1fff;
-	debug("adjusted refresh interval %0x\n", sdram_config_reg);
-
-	/* we want physical bank interleaving and */
-	/* virtual bank interleaving enabled so do nothing */
-	/* since these bits need to be zero to enable the interleaving */
-
-	/*  registered DRAM ? */
-	if (info->registeredAddrAndControlInputs == 1) {
-		/* it's registered DRAM, so set the reg. DRAM bit */
-		sdram_config_reg = sdram_config_reg | BIT17;
-		debug("Enabling registered DRAM bit\n");
-	}
-	/* turn on DRAM ECC? */
-#ifdef CONFIG_MV64360_ECC
-	if (info->errorCheckType == 0x2) {
-		/* DRAM has ECC, so turn it on */
-		sdram_config_reg = sdram_config_reg | BIT18;
-		debug("Enabling ECC\n");
-	}
-#endif
-	/* set the data DQS pin configuration */
-	switch (info->sdramWidth) {
-	case 0x4:		/* memory is x4 */
-		sdram_config_reg = sdram_config_reg | BIT20 | BIT21;
-		debug("Data DQS pins set for 16 pins\n");
-		break;
-	case 0x8:		/* memory is x8 or x16 */
-	case 0x10:
-		sdram_config_reg = sdram_config_reg | BIT21;
-		debug("Data DQS pins set for 8 pins\n");
-		break;
-	case 0x20:		/* memory is x32 */
-		/* both bits are cleared for x32 so nothing to do */
-		debug("Data DQS pins set for 2 pins\n");
-		break;
-	default:		/* memory width unsupported */
-		printf ("DRAM chip width is unknown!\n");
-		printf ("Aborting DRAM setup with an error\n");
-		hang ();
-		break;
-	}
-
-	/* perform read buffer assignments */
-	/* we are going to use the Power-up defaults */
-	/* bit 26 = CPU = buffer 1 */
-	/* bit 27 = PCI bus #0 = buffer 0 */
-	/* bit 28 = PCI bus #1 = buffer 0 */
-	/* bit 29 = MPSC = buffer 0 */
-	/* bit 30 = IDMA = buffer 0 */
-	/* bit 31 = Gigabit = buffer 0 */
-	sdram_config_reg = sdram_config_reg | BIT26;
-	/*  sdram_config_reg = sdram_config_reg | 0x58000000; */
-	/* sdram_config_reg = sdram_config_reg & 0xffffff00;  */
-
-	/* write the value into the SDRAM configuration register */
-	GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg);
-	debug
-	    ("OOOOOOOOO sdram_conf 0x1400: %08x\n",
-	     GTREGREAD (SDRAM_CONFIG));
-
-	/* SDRAM open pages control keep open as much as I can */
-	GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
-	debug
-	    ("sdram_open_pages_controll 0x1414: %08x\n",
-	     GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
-
-	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
-	tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);	/* Clock Domain Sync from power on reset */
-	if (tmp == 0)
-		debug("Core Signals are sync (by HW-Setting)!!!\n");
-	else
-		debug
-		    ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
-
-	/* SDRAM set CAS Latency according to SPD information */
-	switch (info->memoryType) {
-	case SDRAM:
-		printf ("### SD-RAM not supported !!!\n");
-		printf ("Aborting!!!\n");
-		hang ();
-		/* ToDo fill SD-RAM if needed !!!!! */
-		break;
-		/* Calculate the settings for SDRAM mode and Dunit control low registers */
-		/* Values set according to technical bulletin TB-92 rev. c */
-	case DDR:
-		debug("### SET-CL for DDR-RAM\n");
-		switch (info->maxClSupported_DDR) {
-		case DDR_CL_3:
-			tmp_sdram_mode = 0x32;	/* CL=3 Burstlength = 4 */
-			if (tmp == 1) { /* clocks sync */
-				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
-					tmp_dunit_control_low = 0x05110051;
-				else
-					tmp_dunit_control_low = 0x24110051;
-				debug
-				    ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			} else {	/* clk sync. bypassed	*/
-
-				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
-					tmp_dunit_control_low = 0x2C1107F2;
-				else
-					tmp_dunit_control_low = 0x3C1107d2;
-				debug
-				    ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			}
-			break;
-		case DDR_CL_2_5:
-			tmp_sdram_mode = 0x62;	/* CL=2.5 Burstlength = 4 */
-			if (tmp == 1) { /* clocks sync */
-				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
-					tmp_dunit_control_low = 0x25110051;
-				else
-					tmp_dunit_control_low = 0x24110051;
-				debug
-				    ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			} else {	/* clk sync. bypassed	*/
-
-				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
-					printf ("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
-					printf ("Aborting!!!\n");
-					hang ();
-				} else
-					tmp_dunit_control_low = 0x1B1107d2;
-				debug
-				    ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			}
-			break;
-		case DDR_CL_2:
-			tmp_sdram_mode = 0x22;	/* CL=2 Burstlength = 4 */
-			if (tmp == 1) { /* clocks sync */
-				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
-					tmp_dunit_control_low = 0x04110051;
-				else
-					tmp_dunit_control_low = 0x03110051;
-				debug
-				    ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			} else {	/* clk sync. bypassed	*/
-
-				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
-					printf ("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
-					printf ("Aborting!!!\n");
-					hang ();
-				} else
-					tmp_dunit_control_low = 0x3B1107d2;
-				debug
-				    ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			}
-			break;
-		case DDR_CL_1_5:
-			tmp_sdram_mode = 0x52;	/* CL=1.5 Burstlength = 4 */
-			if (tmp == 1) { /* clocks sync */
-				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
-					tmp_dunit_control_low = 0x24110051;
-				else
-					tmp_dunit_control_low = 0x23110051;
-				debug
-				    ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			} else {	/* clk sync. bypassed	*/
-
-				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
-					printf ("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
-					printf ("Aborting!!!\n");
-					hang ();
-				} else
-					tmp_dunit_control_low = 0x1A1107d2;
-				debug
-				    ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			}
-			break;
-
-		default:
-			printf ("Max. CL is out of range %d\n",
-				info->maxClSupported_DDR);
-			hang ();
-			break;
-		}		/* end DDR switch */
-		break;
-	}			/* end CL switch */
-
-	/* Write results of CL detection procedure */
-	/* set SDRAM mode reg. 0x141c */
-	GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
-
-	/* set SDRAM mode SetCommand 0x1418 */
-	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
-	while (GTREGREAD (SDRAM_OPERATION) != 0) {
-		debug
-		    ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
-	}
-
-	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
-	GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low);
-
-	/* set SDRAM mode SetCommand 0x1418 */
-	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
-	while (GTREGREAD (SDRAM_OPERATION) != 0) {
-		debug
-		    ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
-	}
-
-/*------------------------------------------------------------------------------ */
-
-	/* bank parameters */
-	/* SDRAM address decode register 0x1410 */
-	/* program this with the default value */
-	tmp = 0x02;		/* power-up default address select decoding value */
-
-	debug("drb_size (n*64Mbit): %d\n", info->drb_size);
-/* figure out the DRAM chip size */
-	sdram_chip_size =
-		(1 << (info->numOfRowAddresses + info->numOfColAddresses));
-	sdram_chip_size *= info->sdramWidth;
-	sdram_chip_size *= 4;
-	debug("computed sdram chip size is %#lx\n", sdram_chip_size);
-	/* divide sdram chip size by 64 Mbits */
-	sdram_chip_size = sdram_chip_size / 0x4000000;
-	switch (sdram_chip_size) {
-	case 1:		/* 64 Mbit */
-	case 2:		/* 128 Mbit */
-		debug("RAM-Device_size 64Mbit or 128Mbit)\n");
-		tmp |= (0x00 << 4);
-		break;
-	case 4:		/* 256 Mbit */
-	case 8:		/* 512 Mbit */
-		debug("RAM-Device_size 256Mbit or 512Mbit)\n");
-		tmp |= (0x01 << 4);
-		break;
-	case 16:		/* 1 Gbit */
-	case 32:		/* 2 Gbit */
-		debug("RAM-Device_size 1Gbit or 2Gbit)\n");
-		tmp |= (0x02 << 4);
-		break;
-	default:
-		printf ("Error in dram size calculation\n");
-		printf ("RAM-Device_size is unsupported\n");
-		hang ();
-	}
-
-	/* SDRAM address control */
-	GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
-	debug
-	    ("setting up sdram address control (0x1410) with: %08lx \n",
-	     tmp);
-
-/* ------------------------------------------------------------------------------ */
-/* same settings for registerd & non-registerd DDR SDRAM */
-	debug
-	    ("setting up sdram_timing_control_low (0x1408) with: %08x \n",
-	     0x11511220);
-	GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
-
-
-/* ------------------------------------------------------------------------------ */
-
-	/* SDRAM configuration */
-	tmp = GTREGREAD (SDRAM_CONFIG);
-
-	if (info->registeredAddrAndControlInputs
-	    || info->registeredDQMBinputs) {
-		tmp |= (1 << 17);
-		debug
-		    ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
-		     info->registeredAddrAndControlInputs,
-		     info->registeredDQMBinputs);
-	}
-
-	/* Use buffer 1 to return read data to the CPU
-	 * Page 426 MV64360 */
-	tmp |= (1 << 26);
-	debug
-	    ("Before Buffer assignment - sdram_conf (0x1400): %08x\n",
-	     GTREGREAD (SDRAM_CONFIG));
-	debug
-	    ("After Buffer assignment - sdram_conf (0x1400): %08x\n",
-	     GTREGREAD (SDRAM_CONFIG));
-
-	/* SDRAM timing To_do: */
-/* ------------------------------------------------------------------------------ */
-
-	debug
-	    ("setting up sdram_timing_control_high (0x140c) with: %08x \n",
-	     0x9);
-	GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0x9);
-
-	debug
-	    ("setting up sdram address pads control (0x14c0) with: %08x \n",
-	     0x7d5014a);
-	GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a);
-
-	debug
-  ("setting up sdram data pads control (0x14c4) with: %08x \n",
-	     0x7d5014a);
-	GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a);
-
-/* ------------------------------------------------------------------------------ */
-
-	/* set the SDRAM configuration for each bank */
-
-/*	for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
-	{
-		i = info->slot;
-		debug
-		    ("\n*** Running a MRS cycle for bank %d ***\n", i);
-
-		/* map the bank */
-		memory_map_bank (i, 0, GB / 4);
-
-		/* set SDRAM mode */ /* To_do check it */
-		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
-		check = GTREGREAD (SDRAM_OPERATION);
-		debug
-		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
-		     check);
-
-
-		/* switch back to normal operation mode */
-		GT_REG_WRITE (SDRAM_OPERATION, 0);
-		check = GTREGREAD (SDRAM_OPERATION);
-		debug
-		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
-		     check);
-
-		/* unmap the bank */
-		memory_map_bank (i, 0, 0);
-	}
-
-	return 0;
-
-}
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-long int dram_size (long int *base, long int maxsize)
-{
-	volatile long int *addr, *b = base;
-	long int cnt, val, save1, save2;
-
-#define STARTVAL (1<<20)	/* start test at 1M */
-	for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
-	     cnt <<= 1) {
-		addr = base + cnt;	/* pointer arith! */
-
-		save1 = *addr;	/* save contents of addr */
-		save2 = *b;	/* save contents of base */
-
-		*addr = cnt;	/* write cnt to addr */
-		*b = 0;		/* put null at base */
-
-		/* check at base address */
-		if ((*b) != 0) {
-			*addr = save1;	/* restore *addr */
-			*b = save2;	/* restore *b */
-			return (0);
-		}
-		val = *addr;	/* read *addr */
-		val = *addr;	/* read *addr */
-
-		*addr = save1;
-		*b = save2;
-
-		if (val != cnt) {
-			debug
-			    ("Found %08x  at Address %08x (failure)\n",
-			     (unsigned int) val, (unsigned int) addr);
-			/* fix boundary condition.. STARTVAL means zero */
-			if (cnt == STARTVAL / sizeof (long))
-				cnt = 0;
-			return (cnt * sizeof (long));
-		}
-	}
-	return maxsize;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* ppcboot interface function to SDRAM init - this is where all the
- * controlling logic happens */
-phys_size_t initdram (int board_type)
-{
-	int checkbank[4] = {[0 ... 3] = 0 };
-	ulong realsize, total;
-	AUX_MEM_DIMM_INFO dimmInfo1;
-	AUX_MEM_DIMM_INFO dimmInfo2;
-	int nhr, bank_no;
-	ulong dest, memSpaceAttr;
-
-	/* first, use the SPD to get info about the SDRAM/ DDRRAM */
-
-	/* check the NHR bit and skip mem init if it's already done */
-	nhr = get_hid0 () & (1 << 16);
-
-	if (nhr) {
-		printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n");
-	} else {
-		/* DIMM0 */
-		check_dimm (0, &dimmInfo1);
-
-		/* DIMM1 */
-		check_dimm (1, &dimmInfo2);
-
-		memory_map_bank (0, 0, 0);
-		memory_map_bank (1, 0, 0);
-		memory_map_bank (2, 0, 0);
-		memory_map_bank (3, 0, 0);
-
-		/* ronen check correct set of DIMMS */
-		if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) {
-			if (dimmInfo1.errorCheckType !=
-			    dimmInfo2.errorCheckType)
-				printf ("***WARNNING***!!!! different ECC support of the DIMMS\n");
-			if (dimmInfo1.maxClSupported_DDR !=
-			    dimmInfo2.maxClSupported_DDR)
-				printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n");
-			if (dimmInfo1.registeredAddrAndControlInputs !=
-			    dimmInfo2.registeredAddrAndControlInputs)
-				printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n");
-		}
-
-		if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) {
-			printf ("Setup for DIMM1 failed.\n");
-		}
-
-		if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) {
-			printf ("Setup for DIMM2 failed.\n");
-		}
-
-		/* set the NHR bit */
-		set_hid0 (get_hid0 () | (1 << 16));
-	}
-	/* next, size the SDRAM banks */
-
-	realsize = total = 0;
-	if (dimmInfo1.numOfModuleBanks > 0) {
-		checkbank[0] = 1;
-	}
-	if (dimmInfo1.numOfModuleBanks > 1) {
-		checkbank[1] = 1;
-	}
-	if (dimmInfo1.numOfModuleBanks > 2)
-		printf ("Error, SPD claims DIMM1 has >2 banks\n");
-
-	printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks);
-
-	if (dimmInfo2.numOfModuleBanks > 0) {
-		checkbank[2] = 1;
-	}
-	if (dimmInfo2.numOfModuleBanks > 1) {
-		checkbank[3] = 1;
-	}
-	if (dimmInfo2.numOfModuleBanks > 2)
-		printf ("Error, SPD claims DIMM2 has >2 banks\n");
-
-	printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
-
-	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
-		/* skip over banks that are not populated */
-		if (!checkbank[bank_no])
-			continue;
-
-		/* ronen - realsize = dram_size((long int *)total, check); */
-		if (bank_no == 0 || bank_no == 1) {
-			if (checkbank[1] == 1)
-				realsize = dimmInfo1.size / 2;
-			else
-				realsize = dimmInfo1.size;
-		}
-		if (bank_no == 2 || bank_no == 3) {
-			if (checkbank[3] == 1)
-				realsize = dimmInfo2.size / 2;
-			else
-				realsize = dimmInfo2.size;
-		}
-		memory_map_bank (bank_no, total, realsize);
-
-		/* ronen - initialize the DRAM for ECC */
-#ifdef CONFIG_MV64360_ECC
-		if ((dimmInfo1.errorCheckType != 0) &&
-		    ((dimmInfo2.errorCheckType != 0)
-		     || (dimmInfo2.numOfModuleBanks == 0))) {
-			printf ("ECC Initialization of Bank %d:", bank_no);
-			memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8;
-			mvDmaSetMemorySpace (0, 0, memSpaceAttr, total,
-					     realsize);
-			for (dest = total; dest < total + realsize;
-			     dest += _8M) {
-				mvDmaTransfer (0, total, dest, _8M,
-					       BIT8 /*DMA_DTL_128BYTES */  |
-					       BIT3 /*DMA_HOLD_SOURCE_ADDR */
-					       |
-					       BIT11
-					       /*DMA_BLOCK_TRANSFER_MODE */ );
-				while (mvDmaIsChannelActive (0));
-			}
-			printf (" PASS\n");
-		}
-#endif
-
-		total += realsize;
-	}
-
-	/* ronen- add DRAM conf prints */
-	switch ((GTREGREAD (0x141c) >> 4) & 0x7) {
-	case 0x2:
-		printf ("CAS Latency = 2");
-		break;
-	case 0x3:
-		printf ("CAS Latency = 3");
-		break;
-	case 0x5:
-		printf ("CAS Latency = 1.5");
-		break;
-	case 0x6:
-		printf ("CAS Latency = 2.5");
-		break;
-	}
-	printf (" tRP = %d tRAS = %d tRCD=%d\n",
-		((GTREGREAD (0x1408) >> 8) & 0xf) + 1,
-		((GTREGREAD (0x1408) >> 20) & 0xf) + 1,
-		((GTREGREAD (0x1408) >> 4) & 0xf) + 1);
-
-/*	Setup Ethernet DMA Adress window to DRAM Area */
-	if (total > _256M)
-		printf ("*** ONLY the first 256MB DRAM memory are used out of the ");
-	else
-		printf ("Total SDRAM memory is ");
-	/* (cause all the 4 BATS are taken) */
-	return (total);
-}
-
-
-/* ronen- add Idma functions for usage of the ecc dram init. */
-/*******************************************************************************
-* mvDmaIsChannelActive - Checks if a engine is busy.
-********************************************************************************/
-int mvDmaIsChannelActive (int engine)
-{
-	ulong data;
-
-	data = GTREGREAD (MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
-	if (data & BIT14 /*activity status */ ) {
-		return 1;
-	}
-	return 0;
-}
-
-/*******************************************************************************
-* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
-*			map.
-*******************************************************************************/
-int mvDmaSetMemorySpace (ulong memSpace,
-			 ulong memSpaceTarget,
-			 ulong memSpaceAttr, ulong baseAddress, ulong size)
-{
-	ulong temp;
-
-	/* The base address must be aligned to the size.  */
-	if (baseAddress % size != 0) {
-		return 0;
-	}
-	if (size >= 0x10000 /*64K */ ) {
-		size &= 0xffff0000;
-		baseAddress = (baseAddress & 0xffff0000);
-		/* Set the new attributes */
-		GT_REG_WRITE (MV64360_DMA_BASE_ADDR_REG0 + memSpace * 8,
-			      (baseAddress | memSpaceTarget | memSpaceAttr));
-		GT_REG_WRITE ((MV64360_DMA_SIZE_REG0 + memSpace * 8),
-			      (size - 1) & 0xffff0000);
-		temp = GTREGREAD (MV64360_DMA_BASE_ADDR_ENABLE_REG);
-		GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
-			      (temp & ~(BIT0 << memSpace)));
-		return 1;
-	}
-	return 0;
-}
-
-
-/*******************************************************************************
-* mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4
-*		  DMA channels.
-********************************************************************************/
-int mvDmaTransfer (int engine, ulong sourceAddr,
-		   ulong destAddr, ulong numOfBytes, ulong command)
-{
-	ulong engOffReg = 0;	/* Engine Offset Register */
-
-	if (numOfBytes > 0xffff) {
-		command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ;
-	}
-	command = command | ((command >> 6) & 0x7);
-	engOffReg = engine * 4;
-	GT_REG_WRITE (MV64360_DMA_CHANNEL0_BYTE_COUNT + engOffReg,
-		      numOfBytes);
-	GT_REG_WRITE (MV64360_DMA_CHANNEL0_SOURCE_ADDR + engOffReg,
-		      sourceAddr);
-	GT_REG_WRITE (MV64360_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg,
-		      destAddr);
-	command =
-		command | BIT12 /*DMA_CHANNEL_ENABLE */	 | BIT9
-		/*DMA_NON_CHAIN_MODE */ ;
-	/* Activate DMA engine By writting to mvDmaControlRegister */
-	GT_REG_WRITE (MV64360_DMA_CHANNEL0_CONTROL + engOffReg, command);
-	return 1;
-}
-
-/****************************************************************************************
- *				SDRAM INIT						*
- *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb	*
- *		  This procedure fits only the Atlantis					*
- *											*
- ***************************************************************************************/
-
-
-/****************************************************************************************
- *				DFCDL initialize MV643xx Design Considerations		*
- *											*
- ***************************************************************************************/
-int set_dfcdlInit (void)
-{
-	int i;
-	unsigned int dfcdl_word = 0x391;	/*   0x14f;  ronen new dfcdl */
-
-	for (i = 0; i < 64; i++) {
-		GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
-/*	dfcdl_word += 0x41;  - ronen new dfcdl */
-	}
-	GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000);	/* enable dynamic delay line updating */
-
-	return (0);
-}
diff --git a/board/Marvell/db64460/64460.h b/board/Marvell/db64460/64460.h
deleted file mode 100644
index 9cf7feea584..00000000000
--- a/board/Marvell/db64460/64460.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * main board support/init for the Galileo Eval board DB64460.
- */
-
-#ifndef __64460_H__
-#define __64460_H__
-
-/* CPU Configuration bits */
-#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
-#define	CPU_CONF_SINGLE_CPU	(1 << 11)
-#define	CPU_CONF_ENDIANESS	(1 << 12)
-#define CPU_CONF_PIPELINE	(1 << 13)
-#define CPU_CONF_STOP_RETRY	(1 << 17)
-#define CPU_CONF_MULTI_DECODE	(1 << 18)
-#define CPU_CONF_DP_VALID	(1 << 19)
-#define CPU_CONF_PERR_PROP	(1 << 22)
-#define CPU_CONF_AACK_DELAY_2	(1 << 25)
-#define CPU_CONF_AP_VALID	(1 << 26)
-#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
-
-/* CPU Master Control bits */
-#define CPU_MAST_CTL_ARB_EN	(1 << 8)
-#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
-#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
-#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
-#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
-#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
-
-#endif /* __64460_H__ */
diff --git a/board/Marvell/db64460/Kconfig b/board/Marvell/db64460/Kconfig
deleted file mode 100644
index f53e3a9c857..00000000000
--- a/board/Marvell/db64460/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DB64460
-
-config SYS_BOARD
-	default "db64460"
-
-config SYS_VENDOR
-	default "Marvell"
-
-config SYS_CONFIG_NAME
-	default "DB64460"
-
-endif
diff --git a/board/Marvell/db64460/MAINTAINERS b/board/Marvell/db64460/MAINTAINERS
deleted file mode 100644
index a30c51c54be..00000000000
--- a/board/Marvell/db64460/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DB64460 BOARD
-#M:	-
-S:	Maintained
-F:	board/Marvell/db64460/
-F:	include/configs/DB64460.h
-F:	configs/DB64460_defconfig
diff --git a/board/Marvell/db64460/Makefile b/board/Marvell/db64460/Makefile
deleted file mode 100644
index a970f9afde1..00000000000
--- a/board/Marvell/db64460/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2001
-# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= db64460.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
-	  mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
-	  sdram_init.o ../common/intel_flash.o ../common/misc.o
diff --git a/board/Marvell/db64460/README b/board/Marvell/db64460/README
deleted file mode 100644
index c6e01fe1efb..00000000000
--- a/board/Marvell/db64460/README
+++ /dev/null
@@ -1,105 +0,0 @@
-This file contains status information for the port of the U-Boot to the Marvell Development Board DB64460.
-
-Author: Ronen Shitrit <rshitrit@il.marvell.com>
-
-
-Supported CPU Types :
-+++++++++++++++++++++
-IBM750Gx Rev 1.0
-MPC7457 Rev 1.1
-
-Supported CPU Cache Library:
-++++++++++++++++++++++++++++
- L1 and L2 only.
-
-CPU Control:
-++++++++++++
- Marvell optimized CPU control settings:
-  Big Endian
-  Enable CPU pipeline
-  Data and address parity checking
-  AACK# assert after 2 cycles
-
-U-Boot I/O Interface Support:
-+++++++++++++++++++++++++++++
-- Serial Interface (UART)
-  This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module.
-- Network Interface
-  This LSP supports the following network devices:
-  o MV64360 Gigabit Ethernet Controller device
-  o Intel 82559 PCI NIC device
-- PCI Interface
-  This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units:
-  o Local PCI configuration header control.
-  o External PCI configuration header control (for other agents on the bus).
-  o PCI configuration application. Scans and configures the PCI agents on the bus.
-  o PCI Internal Arbiter activation and configuration.
-
-Memory Interface Support:
-+++++++++++++++++++++++++
-- DDR
-  o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs).
-  o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma.
-
-- Devices
-  o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM.
-  o JFFS2
-    JFFS2 is a crash/power down safe file system for disk-less embedded devices.
-    This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it.
-
-Unsupported Features:
-+++++++++++++++++++++
- Messaging unit - No support for MV64360 Messaging unit.
- Watchdog Timer - No support for MV64360 Watchdog unit.
- L3 cache - No support for L3 cache on MPC7455
- Dual PCU - No support for Dual CPU
- PCI-X was never tested
- IDMA driver - No support for MV64360 IDMA unit.
- XOR Engine - No support for MV64460 XOR Engine
-
-BSP Special Considerations:
-+++++++++++++++++++++++++++
-- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots.
-- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical.
-
-Test Cases:
-###########
-UART:
-+++++
-Check that the UART baud rate is configured to 57600 and 115200, and check:
-	Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom.
-	Load S-Record file over the UART using Windows HyperTerminal.
-
-Network:
-++++++++
-Use TFTP application to load a debugged executable and execute it.
-Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC.
-
-Memory:
-+++++++
-Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters:
-o	128MB DIMM consist of 16 x 64Mbit devices
-o	128MB DIMM consist of 09 x 128Mbit devices @ 266MHz.
-o	256MB DIMM consist of 16 x 128Mbit devices @ 266MHz.
-o	256MB DIMM consist of 09 x 256Mbit devices @ 400MHz.
-o	512MB DIMM consist of 16 x 256Mbit devices @ 333MHz.
-o	512MB DIMM consist of 18 x 256Mbit devices @ 266MHz.
-o	GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered
-
-For each chip select device perform data access to verify its accessibility.
-
-Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage.
-Load the U-Boot and:
-use the ls command to check correct scan of the JFFS2 on the large flash.
-Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage.
-
-PCI:
-++++
-1)Insert different PCI cards:
-Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech  NIC 8139 rev10
-on different slots (0-3) of the PCI and check:
-o	Correct detection of the PCI devices.
-o	Correct address mapping of the PCI devices.
-2)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot.
-
-Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal)
diff --git a/board/Marvell/db64460/db64460.c b/board/Marvell/db64460/db64460.c
deleted file mode 100644
index 9baaaac8a8a..00000000000
--- a/board/Marvell/db64460/db64460.c
+++ /dev/null
@@ -1,922 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * modifications for the DB64460 eval board based by Ingo.Assmus@keymile.com
- */
-
-/*
- * db64460.c - main board support/init for the Galileo Eval board.
- */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include "../include/memory.h"
-#include "../include/pci.h"
-#include "../include/mv_gen_reg.h"
-#include <net.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "i2c.h"
-#include "64460.h"
-#include "mv_regs.h"
-
-#undef	DEBUG
-/*#define	DEBUG */
-
-#define	MAP_PCI
-
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-/* this is the current GT register space location */
-/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
-
-/* Unfortunately, we cant change it while we are in flash, so we initialize it
- * to the "final" value. This means that any debug_led calls before
- * board_early_init_f wont work right (like in cpu_init_f).
- * See also my_remap_gt_regs below. (NTL)
- */
-
-void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
-int display_mem_map (void);
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * This is a version of the GT register space remapping function that
- * doesn't touch globals (meaning, it's ok to run from flash.)
- *
- * Unfortunately, this has the side effect that a writable
- * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
- */
-
-void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
-{
-	u32 temp;
-
-	/* check and see if it's already moved */
-
-/* original ppcboot 1.1.6 source
-
-	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 20)
-		return;
-
-	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 20);
-
-	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
-original ppcboot 1.1.6 source end */
-
-	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 16)
-		return;
-
-	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 16);
-
-	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
-}
-
-#ifdef CONFIG_PCI
-
-static void gt_pci_config (void)
-{
-	unsigned int stat;
-	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
-
-	/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
-	 * config registers by writing ones to the bus and device.
-	 * We then update the Virtual register with the correct value for the bus and device.
-	 */
-	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
-		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
-
-		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
-
-		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
-		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
-
-	}
-	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
-		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
-		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
-
-		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
-		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
-	}
-
-	/* Enable master */
-	PCI_MASTER_ENABLE (0, SELF);
-	PCI_MASTER_ENABLE (1, SELF);
-
-	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
-	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
-	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
-									     <<
-									     18);
-	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
-	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
-
-	/* ronen- add write to pci remap registers for 64460.
-	   in 64360 when writing to pci base go and overide remap automaticaly,
-	   in 64460 it doesn't */
-	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
-
-	/* PCI interface settings */
-	/* Timeout set to retry forever */
-	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
-	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
-
-	/* ronen - enable only CS0 and Internal reg!! */
-	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-
-/*ronen update the pci internal registers base address.*/
-#ifdef MAP_PCI
-	for (stat = 0; stat <= PCI_HOST1; stat++)
-		pciWriteConfigReg (stat,
-				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
-				   SELF, CONFIG_SYS_GT_REGS);
-#endif
-
-}
-#endif
-
-/* Setup CPU interface paramaters */
-static void gt_cpu_config (void)
-{
-	cpu_t cpu = get_cpu_type ();
-	ulong tmp;
-
-	/* cpu configuration register */
-	tmp = GTREGREAD (CPU_CONFIGURATION);
-
-	/* set the SINGLE_CPU bit  see MV64460 P.399 */
-#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
-	tmp |= CPU_CONF_SINGLE_CPU;
-#endif
-
-	tmp &= ~CPU_CONF_AACK_DELAY_2;
-
-	tmp |= CPU_CONF_DP_VALID;
-	tmp |= CPU_CONF_AP_VALID;
-
-	tmp |= CPU_CONF_PIPELINE;
-
-	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
-
-	/* CPU master control register */
-	tmp = GTREGREAD (CPU_MASTER_CONTROL);
-
-	tmp |= CPU_MAST_CTL_ARB_EN;
-
-	if ((cpu == CPU_7400) ||
-	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
-
-		tmp |= CPU_MAST_CTL_CLEAN_BLK;
-		tmp |= CPU_MAST_CTL_FLUSH_BLK;
-
-	} else {
-		/* cleanblock must be cleared for CPUs
-		 * that do not support this command (603e, 750)
-		 * see Res#1 */
-		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
-		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
-	}
-	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
-}
-
-/*
- * board_early_init_f.
- *
- * set up gal. device mappings, etc.
- */
-int board_early_init_f (void)
-{
-	uchar sram_boot = 0;
-
-	/*
-	 * set up the GT the way the kernel wants it
-	 * the call to move the GT register space will obviously
-	 * fail if it has already been done, but we're going to assume
-	 * that if it's not at the power-on location, it's where we put
-	 * it last time. (huber)
-	 */
-
-	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
-
-	/* No PCI in first release of Port To_do: enable it. */
-#ifdef CONFIG_PCI
-	gt_pci_config ();
-#endif
-	/* mask all external interrupt sources */
-	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
-	/* new in MV6446x */
-	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
-	/* --------------------- */
-	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
-	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
-	/* does not exist in MV6446x
-	   GT_REG_WRITE(CPU_INT_0_MASK, 0);
-	   GT_REG_WRITE(CPU_INT_1_MASK, 0);
-	   GT_REG_WRITE(CPU_INT_2_MASK, 0);
-	   GT_REG_WRITE(CPU_INT_3_MASK, 0);
-	   --------------------- */
-
-
-	/* ----- DEVICE BUS SETTINGS ------ */
-
-	/*
-	 * EVB
-	 * 0 - SRAM   ????
-	 * 1 - RTC      ????
-	 * 2 - UART     ????
-	 * 3 - Flash    checked 32Bit Intel Strata
-	 * boot - BootCS checked 8Bit 29LV040B
-	 *
-	 * Zuma
-	 * 0 - Flash
-	 * boot - BootCS
-	 */
-
-	/*
-	 * the dual 7450 module requires burst access to the boot
-	 * device, so the serial rom copies the boot device to the
-	 * on-board sram on the eval board, and updates the correct
-	 * registers to boot from the sram. (device0)
-	 */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
-		sram_boot = 1;
-	if (!sram_boot)
-		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
-
-	memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
-	memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
-	memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
-
-
-	/* configure device timing */
-#ifdef CONFIG_SYS_DEV0_PAR		/* set port parameters for SRAM device module access */
-	if (!sram_boot)
-		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
-#endif
-
-#ifdef CONFIG_SYS_DEV1_PAR		/* set port parameters for RTC device module access */
-	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
-#endif
-#ifdef CONFIG_SYS_DEV2_PAR		/* set port parameters for DUART device module access */
-	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
-#endif
-
-#ifdef CONFIG_SYS_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
-	/* detect if we are booting from the 32 bit flash */
-	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
-		/* 32 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
-			      CONFIG_SYS_32BIT_BOOT_PAR);
-	} else {
-		/* 8 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
-	}
-#else
-	/* 8 bit boot flash only */
-/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
-#endif
-
-
-	gt_cpu_config ();
-
-	/* MPP setup */
-	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
-	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
-	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
-	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
-
-	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
-	DEBUG_LED0_ON ();
-	DEBUG_LED1_ON ();
-	DEBUG_LED2_ON ();
-
-	return 0;
-}
-
-/* various things to do after relocation */
-
-int misc_init_r ()
-{
-	icache_enable ();
-#ifdef CONFIG_SYS_L2
-	l2cache_enable ();
-#endif
-#ifdef CONFIG_MPSC
-
-	mpsc_sdma_init ();
-	mpsc_init2 ();
-#endif
-
-#if 0
-	/* disable the dcache and MMU */
-	dcache_lock ();
-#endif
-	return 0;
-}
-
-void after_reloc (ulong dest_addr, gd_t * gd)
-{
-	/* check to see if we booted from the sram.  If so, move things
-	 * back to the way they should be. (we're running from main
-	 * memory at this point now */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
-		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
-		memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
-	}
-	display_mem_map ();
-	/* now, jump to the main ppcboot board init code */
-	board_init_r (gd, dest_addr);
-	/* NOTREACHED */
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- *
- * right now, assume borad type. (there is just one...after all)
- */
-
-int checkboard (void)
-{
-	int l_type = 0;
-
-	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
-	return (l_type);
-}
-
-/* utility functions */
-void debug_led (int led, int mode)
-{
-	volatile int *addr = 0;
-	__maybe_unused int dummy;
-
-	if (mode == 1) {
-		switch (led) {
-		case 0:
-			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
-					0x08000);
-			break;
-
-		case 1:
-			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
-					0x0c000);
-			break;
-
-		case 2:
-			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
-					0x10000);
-			break;
-		}
-	} else if (mode == 0) {
-		switch (led) {
-		case 0:
-			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
-					0x14000);
-			break;
-
-		case 1:
-			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
-					0x18000);
-			break;
-
-		case 2:
-			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
-					0x1c000);
-			break;
-		}
-	}
-
-	dummy = *addr;
-}
-
-int display_mem_map (void)
-{
-	int i, j;
-	unsigned int base, size, width;
-
-	/* SDRAM */
-	printf ("SD (DDR) RAM\n");
-	for (i = 0; i <= BANK3; i++) {
-		base = memoryGetBankBaseAddress (i);
-		size = memoryGetBankSize (i);
-		if (size != 0) {
-			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
-				i, base, size >> 20);
-		}
-	}
-
-	/* CPU's PCI windows */
-	for (i = 0; i <= PCI_HOST1; i++) {
-		printf ("\nCPU's PCI %d windows\n", i);
-		base = pciGetSpaceBase (i, PCI_IO);
-		size = pciGetSpaceSize (i, PCI_IO);
-		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
-			size >> 20);
-		for (j = 0;
-		     j <=
-		     PCI_REGION0
-		     /*ronen currently only first PCI MEM is used 3 */ ;
-		     j++) {
-			base = pciGetSpaceBase (i, j);
-			size = pciGetSpaceSize (i, j);
-			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
-		}
-	}
-
-	/* Devices */
-	printf ("\nDEVICES\n");
-	for (i = 0; i <= DEVICE3; i++) {
-		base = memoryGetDeviceBaseAddress (i);
-		size = memoryGetDeviceSize (i);
-		width = memoryGetDeviceWidth (i) * 8;
-		printf ("DEV %d:  base - 0x%08x  size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
-		if (i == 0)
-			printf ("\t- EXT SRAM (actual - 1M)\n");
-		else if (i == 1)
-			printf ("\t- RTC\n");
-		else if (i == 2)
-			printf ("\t- UART\n");
-		else
-			printf ("\t- LARGE FLASH\n");
-	}
-
-	/* Bootrom */
-	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
-	size = memoryGetDeviceSize (BOOT_DEVICE);
-	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
-	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\n",
-		base, size >> 20, width);
-	return (0);
-}
-
-/* DRAM check routines copied from gw8260 */
-
-#if defined (CONFIG_SYS_DRAM_TEST)
-
-/*********************************************************************/
-/* NAME:  move64() -  moves a double word (64-bit)		     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   this function performs a double word move from the data at	     */
-/*   the source pointer to the location at the destination pointer.  */
-/*								     */
-/* INPUTS:							     */
-/*   unsigned long long *src  - pointer to data to move		     */
-/*								     */
-/* OUTPUTS:							     */
-/*   unsigned long long *dest - pointer to locate to move data	     */
-/*								     */
-/* RETURNS:							     */
-/*   None							     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*   May cloober fr0.						     */
-/*								     */
-/*********************************************************************/
-static void move64 (unsigned long long *src, unsigned long long *dest)
-{
-	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
-	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
-      : : : "fr0");		/* Clobbers fr0         */
-	return;
-}
-
-
-#if defined (CONFIG_SYS_DRAM_TEST_DATA)
-
-unsigned long long pattern[] = {
-	0xaaaaaaaaaaaaaaaaULL,
-	0xccccccccccccccccULL,
-	0xf0f0f0f0f0f0f0f0ULL,
-	0xff00ff00ff00ff00ULL,
-	0xffff0000ffff0000ULL,
-	0xffffffff00000000ULL,
-	0x00000000ffffffffULL,
-	0x0000ffff0000ffffULL,
-	0x00ff00ff00ff00ffULL,
-	0x0f0f0f0f0f0f0f0fULL,
-	0x3333333333333333ULL,
-	0x5555555555555555ULL,
-};
-
-/*********************************************************************/
-/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Tests data lines for shorts and opens by forcing adjacent data  */
-/*   to opposite states. Because the data lines could be routed in   */
-/*   an arbitrary manner the must ensure test patterns ensure that   */
-/*   every case is tested. By using the following series of binary   */
-/*   patterns every combination of adjacent bits is test regardless  */
-/*   of routing.						     */
-/*								     */
-/*     ...101010101010101010101010				     */
-/*     ...110011001100110011001100				     */
-/*     ...111100001111000011110000				     */
-/*     ...111111110000000011111111				     */
-/*								     */
-/*   Carrying this out, gives us six hex patterns as follows:	     */
-/*								     */
-/*     0xaaaaaaaaaaaaaaaa					     */
-/*     0xcccccccccccccccc					     */
-/*     0xf0f0f0f0f0f0f0f0					     */
-/*     0xff00ff00ff00ff00					     */
-/*     0xffff0000ffff0000					     */
-/*     0xffffffff00000000					     */
-/*								     */
-/*   The number test patterns will always be given by:		     */
-/*								     */
-/*   log(base 2)(number data bits) = log2 (64) = 6		     */
-/*								     */
-/*   To test for short and opens to other signals on our boards. we  */
-/*   simply							     */
-/*   test with the 1's complemnt of the paterns as well.	     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern				     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*  Assumes only one one SDRAM bank				     */
-/*								     */
-/*********************************************************************/
-int mem_test_data (void)
-{
-	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
-	unsigned long long temp64 = 0;
-	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
-	int i;
-	unsigned int hi, lo;
-
-	for (i = 0; i < num_patterns; i++) {
-		move64 (&(pattern[i]), pmem);
-		move64 (pmem, &temp64);
-
-		/* hi = (temp64>>32) & 0xffffffff;          */
-		/* lo = temp64 & 0xffffffff;                */
-		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
-
-		hi = (pattern[i] >> 32) & 0xffffffff;
-		lo = pattern[i] & 0xffffffff;
-		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
-
-		if (temp64 != pattern[i]) {
-			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
-				hi, lo);
-			return 1;
-		}
-	}
-
-	return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_DATA */
-
-#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
-/*********************************************************************/
-/* NAME:  mem_test_address() -	test address lines		     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   This function performs a test to verify that each word im	     */
-/*   memory is uniquly addressable. The test sequence is as follows: */
-/*								     */
-/*   1) write the address of each word to each word.		     */
-/*   2) verify that each location equals its address		     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern and address			     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_test_address (void)
-{
-	volatile unsigned int *pmem =
-		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
-	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
-	unsigned int i;
-
-	/* write address to each location */
-	for (i = 0; i < size; i++) {
-		pmem[i] = i;
-	}
-
-	/* verify each loaction */
-	for (i = 0; i < size; i++) {
-		if (pmem[i] != i) {
-			printf ("\n   Address Test Failed at 0x%x", i);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
-
-#if defined (CONFIG_SYS_DRAM_TEST_WALK)
-/*********************************************************************/
-/* NAME:   mem_march() -  memory march				     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Marches up through memory. At each location verifies rmask if   */
-/*   read = 1. At each location write wmask if	write = 1. Displays  */
-/*   failing address and pattern.				     */
-/*								     */
-/* INPUTS:							     */
-/*   volatile unsigned long long * base - start address of test	     */
-/*   unsigned int size - number of dwords(64-bit) to test	     */
-/*   unsigned long long rmask - read verify mask		     */
-/*   unsigned long long wmask - wrtie verify mask		     */
-/*   short read - verifies rmask if read = 1			     */
-/*   short write  - writes wmask if write = 1			     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern and address			     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_march (volatile unsigned long long *base,
-	       unsigned int size,
-	       unsigned long long rmask,
-	       unsigned long long wmask, short read, short write)
-{
-	unsigned int i;
-	unsigned long long temp = 0;
-	unsigned int hitemp, lotemp, himask, lomask;
-
-	for (i = 0; i < size; i++) {
-		if (read != 0) {
-			/* temp = base[i]; */
-			move64 ((unsigned long long *) &(base[i]), &temp);
-			if (rmask != temp) {
-				hitemp = (temp >> 32) & 0xffffffff;
-				lotemp = temp & 0xffffffff;
-				himask = (rmask >> 32) & 0xffffffff;
-				lomask = rmask & 0xffffffff;
-
-				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
-				return 1;
-			}
-		}
-		if (write != 0) {
-			/*  base[i] = wmask; */
-			move64 (&wmask, (unsigned long long *) &(base[i]));
-		}
-	}
-	return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_WALK */
-
-/*********************************************************************/
-/* NAME:   mem_test_walk() -  a simple walking ones test	     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Performs a walking ones through entire physical memory. The     */
-/*   test uses as series of memory marches, mem_march(), to verify   */
-/*   and write the test patterns to memory. The test sequence is as  */
-/*   follows:							     */
-/*     1) march writing 0000...0001				     */
-/*     2) march verifying 0000...0001  , writing  0000...0010	     */
-/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
-/*	   the write mask equals 1000...0000			     */
-/*     4) march verifying 1000...0000				     */
-/*   The test fails if any of the memory marches return a failure.   */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays which pass on the memory test is executing	     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_test_walk (void)
-{
-	unsigned long long mask;
-	volatile unsigned long long *pmem =
-		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
-	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
-
-	unsigned int i;
-
-	mask = 0x01;
-
-	printf ("Initial Pass");
-	mem_march (pmem, size, 0x0, 0x1, 0, 1);
-
-	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-	printf ("		");
-	printf ("         ");
-	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-
-	for (i = 0; i < 63; i++) {
-		printf ("Pass %2d", i + 2);
-		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
-			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
-			return 1;
-		}
-		mask = mask << 1;
-		printf ("\b\b\b\b\b\b\b");
-	}
-
-	printf ("Last Pass");
-	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
-		/* printf("mask: 0x%x", mask); */
-		return 1;
-	}
-	printf ("\b\b\b\b\b\b\b\b\b");
-	printf ("	     ");
-	printf ("\b\b\b\b\b\b\b\b\b");
-
-	return 0;
-}
-
-/*********************************************************************/
-/* NAME:    testdram() -  calls any enabled memory tests	     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Runs memory tests if the environment test variables are set to  */
-/*   'y'.							     */
-/*								     */
-/* INPUTS:							     */
-/*   testdramdata    - If set to 'y', data test is run.		     */
-/*   testdramaddress - If set to 'y', address test is run.	     */
-/*   testdramwalk    - If set to 'y', walking ones test is run	     */
-/*								     */
-/* OUTPUTS:							     */
-/*   None							     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int testdram (void)
-{
-	int rundata, runaddress, runwalk;
-
-	rundata = getenv_yesno("testdramdata") == 1;
-	runaddress = getenv_yesno("testdramaddress") == 1;
-	runwalk = getenv_yesno("testdramwalk") == 1;
-
-/*    rundata = 1; */
-/*    runaddress = 0; */
-/*    runwalk = 0; */
-
-	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
-	}
-#ifdef CONFIG_SYS_DRAM_TEST_DATA
-	if (rundata == 1) {
-		printf ("Test DATA ...  ");
-		if (mem_test_data () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
-	if (runaddress == 1) {
-		printf ("Test ADDRESS ...  ");
-		if (mem_test_address () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_WALK
-	if (runwalk == 1) {
-		printf ("Test WALKING ONEs ...  ");
-		if (mem_test_walk () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("passed\n");
-	}
-	return 0;
-
-}
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-/* ronen - the below functions are used by the bootm function           */
-/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
-/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
-/*    the kernel data areas.                                            */
-/*  - we diable and invalidate the icache and dcache.                   */
-void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
-{
-	u32 temp;
-
-	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 16)
-		return;
-
-	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 16);
-
-	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
-							new_loc |
-							(INTERNAL_SPACE_DECODE)))))
-	       != temp);
-
-}
-
-void board_prebootm_init ()
-{
-
-/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
-		GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
-
-/* Stop GigE Rx DMA engines */
-	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
-	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
-	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00);
-
-/* Relocate MV64460 internal regs */
-	my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
-
-	icache_disable ();
-	dcache_disable ();
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int ret;
-	ret = pci_eth_init(bis);
-	if (!ret)
-		ret = mv6446x_eth_initialize(bis);
-	return ret;
-}
diff --git a/board/Marvell/db64460/eth.h b/board/Marvell/db64460/eth.h
deleted file mode 100644
index c2067a4d940..00000000000
--- a/board/Marvell/db64460/eth.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __EVB64460_ETH_H__
-#define __EVB64460_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-
-int db64460_eth0_poll(void);
-int db64460_eth0_transmit(unsigned int s, volatile char *p);
-void db64460_eth0_disable(void);
-bool network_start(bd_t *bis);
-
-int mv6446x_eth_initialize(bd_t *);
-
-#endif /* __EVB64460_ETH_H__ */
diff --git a/board/Marvell/db64460/mpsc.c b/board/Marvell/db64460/mpsc.c
deleted file mode 100644
index 9fbbae87fa2..00000000000
--- a/board/Marvell/db64460/mpsc.c
+++ /dev/null
@@ -1,1001 +0,0 @@
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*************************************************************************
- * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
-  ************************************************************************/
-
-/*
- * mpsc.c - driver for console over the MPSC.
- */
-
-
-#include <common.h>
-#include <config.h>
-#include <asm/cache.h>
-
-#include <malloc.h>
-#include "mpsc.h"
-
-#include "mv_regs.h"
-
-#include "../include/memory.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Define this if you wish to use the MPSC as a register based UART.
- * This will force the serial port to not use the SDMA engine at all.
- */
-#undef CONFIG_MPSC_DEBUG_PORT
-
-
-int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
-char (*mpsc_getchar) (void) = mpsc_getchar_debug;
-int (*mpsc_test_char) (void) = mpsc_test_char_debug;
-
-
-static volatile unsigned int *rx_desc_base = NULL;
-static unsigned int rx_desc_index = 0;
-static volatile unsigned int *tx_desc_base = NULL;
-static unsigned int tx_desc_index = 0;
-
-/* local function declarations */
-static int galmpsc_connect (int channel, int connect);
-static int galmpsc_route_rx_clock (int channel, int brg);
-static int galmpsc_route_tx_clock (int channel, int brg);
-static int galmpsc_write_config_regs (int mpsc, int mode);
-static int galmpsc_config_channel_regs (int mpsc);
-static int galmpsc_set_char_length (int mpsc, int value);
-static int galmpsc_set_stop_bit_length (int mpsc, int value);
-static int galmpsc_set_parity (int mpsc, int value);
-static int galmpsc_enter_hunt (int mpsc);
-static int galmpsc_set_brkcnt (int mpsc, int value);
-static int galmpsc_set_tcschar (int mpsc, int value);
-static int galmpsc_set_snoop (int mpsc, int value);
-static int galmpsc_shutdown (int mpsc);
-
-static int galsdma_set_RFT (int channel);
-static int galsdma_set_SFM (int channel);
-static int galsdma_set_rxle (int channel);
-static int galsdma_set_txle (int channel);
-static int galsdma_set_burstsize (int channel, unsigned int value);
-static int galsdma_set_RC (int channel, unsigned int value);
-
-static int galbrg_set_CDV (int channel, int value);
-static int galbrg_enable (int channel);
-static int galbrg_disable (int channel);
-static int galbrg_set_clksrc (int channel, int value);
-static int galbrg_set_CUV (int channel, int value);
-
-static void galsdma_enable_rx (void);
-static int galsdma_set_mem_space (unsigned int memSpace,
-				  unsigned int memSpaceTarget,
-				  unsigned int memSpaceAttr,
-				  unsigned int baseAddress,
-				  unsigned int size);
-
-
-#define SOFTWARE_CACHE_MANAGEMENT
-
-#ifdef SOFTWARE_CACHE_MANAGEMENT
-#define FLUSH_DCACHE(a,b)		 if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
-#define INVALIDATE_DCACHE(a,b)		 if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
-#else
-#define FLUSH_DCACHE(a,b)
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
-#define INVALIDATE_DCACHE(a,b)
-#endif
-
-#ifdef CONFIG_MPSC_DEBUG_PORT
-static void mpsc_debug_init (void)
-{
-
-	volatile unsigned int temp;
-
-	/* Clear the CFR  (CHR4) */
-	/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
-	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
-	temp &= 0xffffff00;
-	temp |= BIT29;
-	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
-		      temp);
-
-	/* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
-	temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
-	temp |= (BIT12 | BIT15);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
-		      temp);
-
-	/* Set int mask */
-	temp = GTREGREAD (GALMPSC_0_INT_MASK);
-	temp |= BIT6;
-	GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
-}
-#endif
-
-char mpsc_getchar_debug (void)
-{
-	volatile int temp;
-	volatile unsigned int cause;
-
-	cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
-	while ((cause & BIT6) == 0) {
-		cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
-	}
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
-			  (CHANNEL * GALMPSC_REG_GAP));
-	/* By writing 1's to the set bits, the register is cleared */
-	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
-		      temp);
-	GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
-	return (temp >> 16) & 0xff;
-}
-
-/* special function for running out of flash.  doesn't modify any
- * global variables [josh] */
-int mpsc_putchar_early (char ch)
-{
-	int mpsc = CHANNEL;
-	int temp =
-		GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
-	galmpsc_set_tcschar (mpsc, ch);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
-		      temp | 0x200);
-
-#define MAGIC_FACTOR	(10*1000000)
-
-	udelay (MAGIC_FACTOR / gd->baudrate);
-	return 0;
-}
-
-/* This is used after relocation, see serial.c and mpsc_init2 */
-static int mpsc_putchar_sdma (char ch)
-{
-	volatile unsigned int *p;
-	unsigned int temp;
-
-
-	/* align the descriptor */
-	p = tx_desc_base;
-	memset ((void *) p, 0, 8 * sizeof (unsigned int));
-
-	/* fill one 64 bit buffer */
-	/* word swap, pad with 0 */
-	p[4] = 0;		/* x */
-	p[5] = (unsigned int) ch;	/* x */
-
-	/* CHANGED completely according to GT64260A dox - NTL */
-	p[0] = 0x00010001;	/* 0 */
-	p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* 4 */
-	p[2] = 0;		/* 8 */
-	p[3] = (unsigned int) &p[4];	/* c */
-
-#if 0
-	p[9] = DESC_FIRST | DESC_LAST;
-	p[10] = (unsigned int) &p[0];
-	p[11] = (unsigned int) &p[12];
-#endif
-
-	FLUSH_DCACHE (&p[0], &p[8]);
-
-	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
-		      (unsigned int) &p[0]);
-	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
-		      (unsigned int) &p[0]);
-
-	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
-	temp |= (TX_DEMAND | TX_STOP);
-	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
-
-	INVALIDATE_DCACHE (&p[1], &p[2]);
-
-	while (p[1] & DESC_OWNER_BIT) {
-		udelay (100);
-		INVALIDATE_DCACHE (&p[1], &p[2]);
-	}
-	return 0;
-}
-
-char mpsc_getchar_sdma (void)
-{
-	static unsigned int done = 0;
-	volatile char ch;
-	unsigned int len = 0, idx = 0, temp;
-
-	volatile unsigned int *p;
-
-
-	do {
-		p = &rx_desc_base[rx_desc_index * 8];
-
-		INVALIDATE_DCACHE (&p[0], &p[1]);
-		/* Wait for character */
-		while (p[1] & DESC_OWNER_BIT) {
-			udelay (100);
-			INVALIDATE_DCACHE (&p[0], &p[1]);
-		}
-
-		/* Handle error case */
-		if (p[1] & (1 << 15)) {
-			printf ("oops, error: %08x\n", p[1]);
-
-			temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
-					  (CHANNEL * GALMPSC_REG_GAP));
-			temp |= (1 << 23);
-			GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
-				      (CHANNEL * GALMPSC_REG_GAP), temp);
-
-			/* Can't poll on abort bit, so we just wait. */
-			udelay (100);
-
-			galsdma_enable_rx ();
-		}
-
-		/* Number of bytes left in this descriptor */
-		len = p[0] & 0xffff;
-
-		if (len) {
-			/* Where to look */
-			idx = 5;
-			if (done > 3)
-				idx = 4;
-			if (done > 7)
-				idx = 7;
-			if (done > 11)
-				idx = 6;
-
-			INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
-			ch = p[idx] & 0xff;
-			done++;
-		}
-
-		if (done < len) {
-			/* this descriptor has more bytes still
-			 * shift down the char we just read, and leave the
-			 * buffer in place for the next time around
-			 */
-			p[idx] = p[idx] >> 8;
-			FLUSH_DCACHE (&p[idx], &p[idx + 1]);
-		}
-
-		if (done == len) {
-			/* nothing left in this descriptor.
-			 * go to next one
-			 */
-			p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
-			p[0] = 0x00100000;
-			FLUSH_DCACHE (&p[0], &p[1]);
-			/* Next descriptor */
-			rx_desc_index = (rx_desc_index + 1) % RX_DESC;
-			done = 0;
-		}
-	} while (len == 0);	/* galileo bug.. len might be zero */
-
-	return ch;
-}
-
-
-int mpsc_test_char_debug (void)
-{
-	if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
-		return 0;
-	else {
-		return 1;
-	}
-}
-
-
-int mpsc_test_char_sdma (void)
-{
-	volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
-
-	INVALIDATE_DCACHE (&p[1], &p[2]);
-
-	if (p[1] & DESC_OWNER_BIT)
-		return 0;
-	else
-		return 1;
-}
-
-int mpsc_init (int baud)
-{
-	/* BRG CONFIG */
-	galbrg_set_baudrate (CHANNEL, baud);
-	galbrg_set_clksrc (CHANNEL, 8);	/* set source=Tclk */
-	galbrg_set_CUV (CHANNEL, 0);	/* set up CountUpValue */
-	galbrg_enable (CHANNEL);	/* Enable BRG */
-
-	/* Set up clock routing */
-	galmpsc_connect (CHANNEL, GALMPSC_CONNECT);	/* connect it */
-
-	galmpsc_route_rx_clock (CHANNEL, CHANNEL);	/* chosse BRG0 for Rx */
-	galmpsc_route_tx_clock (CHANNEL, CHANNEL);	/* chose BRG0 for Tx */
-
-	/* reset MPSC state */
-	galmpsc_shutdown (CHANNEL);
-
-	/* SDMA CONFIG */
-	galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8);	/* in 64 bit words (8 bytes) */
-	galsdma_set_txle (CHANNEL);
-	galsdma_set_rxle (CHANNEL);
-	galsdma_set_RC (CHANNEL, 0xf);
-	galsdma_set_SFM (CHANNEL);
-	galsdma_set_RFT (CHANNEL);
-
-	/* MPSC CONFIG */
-	galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
-	galmpsc_config_channel_regs (CHANNEL);
-	galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8);	/* 8 */
-	galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE);	/* N */
-	galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1);	/* 1 */
-
-#ifdef CONFIG_MPSC_DEBUG_PORT
-	mpsc_debug_init ();
-#endif
-
-	/* COMM_MPSC CONFIG */
-#ifdef SOFTWARE_CACHE_MANAGEMENT
-	galmpsc_set_snoop (CHANNEL, 0);	/* disable snoop */
-#else
-	galmpsc_set_snoop (CHANNEL, 1);	/* enable snoop */
-#endif
-
-	return 0;
-}
-
-
-void mpsc_sdma_init (void)
-{
-/* Setup SDMA channel0 SDMA_CONFIG_REG*/
-	GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
-
-/*  Enable MPSC-Window0 for DRAM Bank0   */
-	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT,
-				   MV64460_SDMA_DRAM_CS_0_TARGET,
-				   0,
-				   memoryGetBankBaseAddress
-				   (CS_0_LOW_DECODE_ADDRESS),
-				   memoryGetBankSize (BANK0)) != true)
-		printf ("%s: SDMA_Window0 memory setup failed !!! \n",
-			__FUNCTION__);
-
-
-/*  Disable MPSC-Window1    */
-	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT,
-				   MV64460_SDMA_DRAM_CS_0_TARGET,
-				   0,
-				   memoryGetBankBaseAddress
-				   (CS_1_LOW_DECODE_ADDRESS),
-				   memoryGetBankSize (BANK3)) != true)
-		printf ("%s: SDMA_Window1 memory setup failed !!! \n",
-			__FUNCTION__);
-
-
-/*  Disable MPSC-Window2 */
-	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT,
-				   MV64460_SDMA_DRAM_CS_0_TARGET,
-				   0,
-				   memoryGetBankBaseAddress
-				   (CS_2_LOW_DECODE_ADDRESS),
-				   memoryGetBankSize (BANK3)) != true)
-		printf ("%s: SDMA_Window2 memory setup failed !!! \n",
-			__FUNCTION__);
-
-
-/*  Disable MPSC-Window3 */
-	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT,
-				   MV64460_SDMA_DRAM_CS_0_TARGET,
-				   0,
-				   memoryGetBankBaseAddress
-				   (CS_3_LOW_DECODE_ADDRESS),
-				   memoryGetBankSize (BANK3)) != true)
-		printf ("%s: SDMA_Window3 memory setup failed !!! \n",
-			__FUNCTION__);
-
-/*  Setup MPSC0 access mode Window0 full access */
-	GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
-			 (MV64460_SDMA_WIN_ACCESS_FULL <<
-			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
-
-/*  Setup MPSC1 access mode Window1 full access */
-	GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
-			 (MV64460_SDMA_WIN_ACCESS_FULL <<
-			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
-
-/* Setup MPSC internal address space base address	*/
-	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
-
-/* no high address remap*/
-	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
-	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
-
-/* clear interrupt cause register for MPSC (fault register)*/
-	GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
-}
-
-
-void mpsc_init2 (void)
-{
-	int i;
-
-#ifndef CONFIG_MPSC_DEBUG_PORT
-	mpsc_putchar = mpsc_putchar_sdma;
-	mpsc_getchar = mpsc_getchar_sdma;
-	mpsc_test_char = mpsc_test_char_sdma;
-#endif
-	/* RX descriptors */
-	rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
-						sizeof (unsigned int));
-
-	/* align descriptors */
-	rx_desc_base = (unsigned int *)
-		(((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
-
-	rx_desc_index = 0;
-
-	memset ((void *) rx_desc_base, 0,
-		(RX_DESC * 8) * sizeof (unsigned int));
-
-	for (i = 0; i < RX_DESC; i++) {
-		rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4];	/* Buffer */
-		rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8];	/* Next descriptor */
-		rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* Command & control */
-		rx_desc_base[i * 8] = 0x00100000;
-	}
-	rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
-
-	FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
-	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
-		      (unsigned int) &rx_desc_base[0]);
-
-	/* TX descriptors */
-	tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
-						sizeof (unsigned int));
-
-	/* align descriptors */
-	tx_desc_base = (unsigned int *)
-		(((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
-
-	tx_desc_index = -1;
-
-	memset ((void *) tx_desc_base, 0,
-		(TX_DESC * 8) * sizeof (unsigned int));
-
-	for (i = 0; i < TX_DESC; i++) {
-		tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
-		tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
-		tx_desc_base[i * 8 + 3] =
-			(unsigned int) &tx_desc_base[i * 8 + 4];
-		tx_desc_base[i * 8 + 2] =
-			(unsigned int) &tx_desc_base[(i + 1) * 8];
-		tx_desc_base[i * 8 + 1] =
-			DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
-
-		/* set sbytecnt and shadow byte cnt to 1 */
-		tx_desc_base[i * 8] = 0x00010001;
-	}
-	tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
-
-	FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
-
-	udelay (100);
-
-	galsdma_enable_rx ();
-
-	return;
-}
-
-int galbrg_set_baudrate (int channel, int rate)
-{
-	int clock;
-
-	galbrg_disable (channel);	/*ok */
-
-#ifdef ZUMA_NTL
-	/* from tclk */
-	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
-#else
-	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
-#endif
-
-	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
-
-	galbrg_enable (channel);
-
-	gd->baudrate = rate;
-
-	return 0;
-}
-
-/* ------------------------------------------------------------------ */
-
-/* Below are all the private functions that no one else needs */
-
-static int galbrg_set_CDV (int channel, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp &= 0xFFFF0000;
-	temp |= (value & 0x0000FFFF);
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galbrg_enable (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp |= 0x00010000;
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galbrg_disable (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp &= 0xFFFEFFFF;
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galbrg_set_clksrc (int channel, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp &= 0xFFC3FFFF;	/* Bit 18 - 21 (MV 64260 18-22) */
-	temp |= (value << 18);
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-	return 0;
-}
-
-static int galbrg_set_CUV (int channel, int value)
-{
-	/* set CountUpValue */
-	GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
-
-	return 0;
-}
-
-#if 0
-static int galbrg_reset (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp |= 0x20000;
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
-	return 0;
-}
-#endif
-
-static int galsdma_set_RFT (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp |= 0x00000001;
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_SFM (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp |= 0x00000002;
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_rxle (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp |= 0x00000040;
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_txle (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp |= 0x00000080;
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_RC (int channel, unsigned int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp &= ~0x0000003c;
-	temp |= (value << 2);
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_burstsize (int channel, unsigned int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp &= 0xFFFFCFFF;
-	switch (value) {
-	case 8:
-		GT_REG_WRITE (GALSDMA_0_CONF_REG +
-			      (channel * GALSDMA_REG_DIFF),
-			      (temp | (0x3 << 12)));
-		break;
-
-	case 4:
-		GT_REG_WRITE (GALSDMA_0_CONF_REG +
-			      (channel * GALSDMA_REG_DIFF),
-			      (temp | (0x2 << 12)));
-		break;
-
-	case 2:
-		GT_REG_WRITE (GALSDMA_0_CONF_REG +
-			      (channel * GALSDMA_REG_DIFF),
-			      (temp | (0x1 << 12)));
-		break;
-
-	case 1:
-		GT_REG_WRITE (GALSDMA_0_CONF_REG +
-			      (channel * GALSDMA_REG_DIFF),
-			      (temp | (0x0 << 12)));
-		break;
-
-	default:
-		return -1;
-		break;
-	}
-
-	return 0;
-}
-
-static int galmpsc_connect (int channel, int connect)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
-
-	if ((channel == 0) && connect)
-		temp &= ~0x00000007;
-	else if ((channel == 1) && connect)
-		temp &= ~(0x00000007 << 6);
-	else if ((channel == 0) && !connect)
-		temp |= 0x00000007;
-	else
-		temp |= (0x00000007 << 6);
-
-	/* Just in case... */
-	temp &= 0x3fffffff;
-
-	GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
-
-	return 0;
-}
-
-static int galmpsc_route_rx_clock (int channel, int brg)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_RxC_ROUTE);
-
-	if (channel == 0) {
-		temp &= ~0x0000000F;
-		temp |= brg;
-	} else {
-		temp &= ~0x00000F00;
-		temp |= (brg << 8);
-	}
-
-	GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
-
-	return 0;
-}
-
-static int galmpsc_route_tx_clock (int channel, int brg)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_TxC_ROUTE);
-
-	if (channel == 0) {
-		temp &= ~0x0000000F;
-		temp |= brg;
-	} else {
-		temp &= ~0x00000F00;
-		temp |= (brg << 8);
-	}
-
-	GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
-
-	return 0;
-}
-
-static int galmpsc_write_config_regs (int mpsc, int mode)
-{
-	if (mode == GALMPSC_UART) {
-		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
-		GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
-			      0x000004c4);
-
-		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
-		GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
-			      0x024003f8);
-		/*        22 2222 1111 */
-		/*        54 3210 9876 */
-		/* 0000 0010 0000 0000 */
-		/*       1 */
-		/*       098 7654 3210 */
-		/* 0000 0011 1111 1000 */
-	} else
-		return -1;
-
-	return 0;
-}
-
-static int galmpsc_config_channel_regs (int mpsc)
-{
-	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
-
-	galmpsc_set_brkcnt (mpsc, 0x3);
-	galmpsc_set_tcschar (mpsc, 0xab);
-
-	return 0;
-}
-
-static int galmpsc_set_brkcnt (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
-	temp &= 0x0000FFFF;
-	temp |= (value << 16);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_set_tcschar (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
-	temp &= 0xFFFF0000;
-	temp |= value;
-	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_set_char_length (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
-	temp &= 0xFFFFCFFF;
-	temp |= (value << 12);
-	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_set_stop_bit_length (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
-	temp &= 0xFFFFBFFF;
-	temp |= (value << 14);
-	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_set_parity (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
-	if (value != -1) {
-		temp &= 0xFFF3FFF3;
-		temp |= ((value << 18) | (value << 2));
-		temp |= ((value << 17) | (value << 1));
-	} else {
-		temp &= 0xFFF1FFF1;
-	}
-
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_enter_hunt (int mpsc)
-{
-	int temp;
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
-	temp |= 0x80000000;
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
-	       MPSC_ENTER_HUNT) {
-		udelay (1);
-	}
-	return 0;
-}
-
-
-static int galmpsc_shutdown (int mpsc)
-{
-	unsigned int temp;
-
-	/* cause RX abort (clears RX) */
-	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
-	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
-	temp &= ~MPSC_ENTER_HUNT;
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
-	GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
-
-	/* shut down the MPSC */
-	GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
-	GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
-	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
-
-	udelay (100);
-
-	/* shut down the sdma engines. */
-	/* reset config to default */
-	GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
-
-	udelay (100);
-
-	/* clear the SDMA current and first TX and RX pointers */
-	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
-	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
-	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
-
-	udelay (100);
-
-	return 0;
-}
-
-static void galsdma_enable_rx (void)
-{
-	int temp;
-
-	/* Enable RX processing */
-	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
-	temp |= RX_ENABLE;
-	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
-
-	galmpsc_enter_hunt (CHANNEL);
-}
-
-static int galmpsc_set_snoop (int mpsc, int value)
-{
-	int reg =
-		mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
-		MPSC_0_ADDRESS_CONTROL_LOW;
-	int temp = GTREGREAD (reg);
-
-	if (value)
-		temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
-	else
-		temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
-	GT_REG_WRITE (reg, temp);
-	return 0;
-}
-
-/*******************************************************************************
-* galsdma_set_mem_space - Set MV64460 IDMA memory decoding map.
-*
-* DESCRIPTION:
-*       the MV64460 SDMA has its own address decoding map that is de-coupled
-*       from the CPU interface address decoding windows. The SDMA channels
-*       share four address windows. Each region can be individually configured
-*       by this function by associating it to a target interface and setting
-*       base and size values.
-*
-*      NOTE!!!
-*       The size must be in 64Kbyte granularity.
-*       The base address must be aligned to the size.
-*       The size must be a series of 1s followed by a series of zeros
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       true for success, false otherwise.
-*
-*******************************************************************************/
-
-static int galsdma_set_mem_space (unsigned int memSpace,
-				  unsigned int memSpaceTarget,
-				  unsigned int memSpaceAttr,
-				  unsigned int baseAddress, unsigned int size)
-{
-	unsigned int temp;
-
-	if (size == 0) {
-		GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
-				   1 << memSpace);
-		return true;
-	}
-
-	/* The base address must be aligned to the size.  */
-	if (baseAddress % size != 0) {
-		return false;
-	}
-	if (size < 0x10000) {
-		return false;
-	}
-
-	/* Align size and base to 64K */
-	baseAddress &= 0xffff0000;
-	size &= 0xffff0000;
-	temp = size >> 16;
-
-	/* Checking that the size is a sequence of '1' followed by a
-	   sequence of '0' starting from LSB to MSB. */
-	while ((temp > 0) && (temp & 0x1)) {
-		temp = temp >> 1;
-	}
-
-	if (temp != 0) {
-		GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
-			      (baseAddress | memSpaceTarget | memSpaceAttr));
-		GT_REG_WRITE ((MV64460_CUNIT_SIZE0 + memSpace * 8),
-			      (size - 1) & 0xffff0000);
-		GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
-				   1 << memSpace);
-	} else {
-		/* An invalid size was specified */
-		return false;
-	}
-	return true;
-}
diff --git a/board/Marvell/db64460/mpsc.h b/board/Marvell/db64460/mpsc.h
deleted file mode 100644
index 9e65e677e21..00000000000
--- a/board/Marvell/db64460/mpsc.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*************************************************************************
- * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
-  ************************************************************************/
-
-
-/*
- * mpsc.h - header file for MPSC in uart mode (console driver)
- */
-
-#ifndef __MPSC_H__
-#define __MPSC_H__
-
-/* include actual Galileo defines */
-#include "../include/mv_gen_reg.h"
-
-/* driver related defines */
-
-int mpsc_init(int baud);
-void mpsc_sdma_init(void);
-void mpsc_init2(void);
-int galbrg_set_baudrate(int channel, int rate);
-
-int mpsc_putchar_early(char ch);
-char mpsc_getchar_debug(void);
-int mpsc_test_char_debug(void);
-
-int mpsc_test_char_sdma(void);
-
-extern int (*mpsc_putchar)(char ch);
-extern char (*mpsc_getchar)(void);
-extern int (*mpsc_test_char)(void);
-
-#define CHANNEL CONFIG_MPSC_PORT
-
-#define TX_DESC     5
-#define RX_DESC     20
-
-#define DESC_FIRST  0x00010000
-#define DESC_LAST   0x00020000
-#define DESC_OWNER_BIT  0x80000000
-
-#define TX_DEMAND   0x00800000
-#define TX_STOP     0x00010000
-#define RX_ENABLE   0x00000080
-
-#define SDMA_RX_ABORT		  (1 << 15)
-#define SDMA_TX_ABORT		  (1 << 31)
-#define MPSC_TX_ABORT		  (1 << 7)
-#define MPSC_RX_ABORT             (1 << 23)
-#define MPSC_ENTER_HUNT           (1 << 31)
-
-/* MPSC defines */
-
-#define GALMPSC_CONNECT            0x1
-#define GALMPSC_DISCONNECT         0x0
-
-#define GALMPSC_UART               0x1
-
-#define GALMPSC_STOP_BITS_1        0x0
-#define GALMPSC_STOP_BITS_2        0x1
-#define GALMPSC_CHAR_LENGTH_8      0x3
-#define GALMPSC_CHAR_LENGTH_7      0x2
-
-#define GALMPSC_PARITY_ODD         0x0
-#define GALMPSC_PARITY_EVEN        0x2
-#define GALMPSC_PARITY_MARK        0x3
-#define GALMPSC_PARITY_SPACE       0x1
-#define GALMPSC_PARITY_NONE        -1
-
-#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
-#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
-#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
-#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
-#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
-#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
-#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
-
-#define GALMPSC_REG_GAP            0x1000
-
-#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
-#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
-#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
-#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
-#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
-#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
-#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
-#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
-#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
-#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
-#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
-#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
-
-#define GALSDMA_COMMAND_FIRST     (1 << 16)
-#define GALSDMA_COMMAND_LAST      (1 << 17)
-#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
-#define GALSDMA_COMMAND_AUTO      (1 << 30)
-#define GALSDMA_COMMAND_OWNER     (1 << 31)
-
-#define GALSDMA_RX                 0
-#define GALSDMA_TX                 1
-
-/* CHANNEL2 should be CHANNEL1, according to documentation,
- * but to work with the current GTREGS file...
- */
-#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
-#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
-#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
-#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
-#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
-#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
-#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
-#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
-#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
-#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
-#define GALSDMA_REG_DIFF           0x2000
-
-/* WRONG in gt64260R.h */
-#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
-#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
-#define GALMPSC_0_INT_CAUSE        0xb804
-#define GALMPSC_0_INT_MASK         0xb884
-
-#define GALSDMA_MODE_UART          0
-#define GALSDMA_MODE_BISYNC        1
-#define GALSDMA_MODE_HDLC          2
-#define GALSDMA_MODE_TRANSPARENT   3
-
-#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
-#define GALBRG_REG_GAP             0x0008
-#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
-
-#endif /* __MPSC_H__ */
diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c
deleted file mode 100644
index 82fcadf31d5..00000000000
--- a/board/Marvell/db64460/mv_eth.c
+++ /dev/null
@@ -1,3127 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * mv_eth.c - header file for the polled mode GT ethernet driver
- */
-#include <common.h>
-#include <net.h>
-#include <malloc.h>
-
-#include "mv_eth.h"
-
-/* enable Debug outputs */
-
-#undef DEBUG_MV_ETH
-
-#ifdef DEBUG_MV_ETH
-#define DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-#undef MV64460_CHECKSUM_OFFLOAD
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The first part is the high level driver of the gigE ethernet ports.   *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-
-/* Definition for configuring driver */
-/* #define UPDATE_STATS_BY_SOFTWARE */
-#undef MV64460_RX_QUEUE_FILL_ON_TASK
-
-
-/* Constants */
-#define MAGIC_ETH_RUNNING		8031971
-#define MV64460_INTERNAL_SRAM_SIZE                      _256K
-#define EXTRA_BYTES 32
-#define WRAP       ETH_HLEN + 2 + 4 + 16
-#define BUFFER_MTU dev->mtu + WRAP
-#define INT_CAUSE_UNMASK_ALL		0x0007ffff
-#define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
-#ifdef MV64460_RX_FILL_ON_TASK
-#define INT_CAUSE_MASK_ALL		0x00000000
-#define INT_CAUSE_CHECK_BITS		INT_CAUSE_UNMASK_ALL
-#define INT_CAUSE_CHECK_BITS_EXT	INT_CAUSE_UNMASK_ALL_EXT
-#endif
-
-/* Read/Write to/from MV64460 internal registers */
-#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
-#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
-#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
-#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
-
-/* Static function declarations */
-static int mv64460_eth_real_open (struct eth_device *eth);
-static int mv64460_eth_real_stop (struct eth_device *eth);
-static struct net_device_stats *mv64460_eth_get_stats (struct eth_device
-						       *dev);
-static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
-static void mv64460_eth_update_stat (struct eth_device *dev);
-bool db64460_eth_start (struct eth_device *eth);
-unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
-				   unsigned int mib_offset);
-int mv64460_eth_receive (struct eth_device *dev);
-
-int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length);
-
-#ifndef  UPDATE_STATS_BY_SOFTWARE
-static void mv64460_eth_print_stat (struct eth_device *dev);
-#endif
-
-extern unsigned int INTERNAL_REG_BASE_ADDR;
-
-/*************************************************
- *Helper functions - used inside the driver only *
- *************************************************/
-#ifdef DEBUG_MV_ETH
-void print_globals (struct eth_device *dev)
-{
-	printf ("Ethernet PRINT_Globals-Debug function\n");
-	printf ("Base Address for ETH_PORT_INFO:	%08x\n",
-		(unsigned int) dev->priv);
-	printf ("Base Address for mv64460_eth_priv:	%08x\n",
-		(unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
-				 port_private));
-
-	printf ("GT Internal Base Address:	%08x\n",
-		INTERNAL_REG_BASE_ADDR);
-	printf ("Base Address for TX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE);
-	printf ("Base Address for RX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE);
-	printf ("Base Address for RX-Buffer:	%08x	allocated Bytes %d\n",
-		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
-		p_rx_buffer_base[0],
-		(MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32);
-	printf ("Base Address for TX-Buffer:	%08x	allocated Bytes %d\n",
-		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
-		p_tx_buffer_base[0],
-		(MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32);
-}
-#endif
-
-#define my_cpu_to_le32(x) my_le32_to_cpu((x))
-
-unsigned long my_le32_to_cpu (unsigned long x)
-{
-	return (((x & 0x000000ffU) << 24) |
-		((x & 0x0000ff00U) << 8) |
-		((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
-}
-
-
-/**********************************************************************
- * mv64460_eth_print_phy_status
- *
- * Prints gigabit ethenret phy status
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64460_eth_print_phy_status (struct eth_device *dev)
-{
-	struct mv64460_eth_priv *port_private;
-	unsigned int port_num;
-	ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	unsigned int port_status, phy_reg_data;
-
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-	/* Check Link status on phy */
-	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
-	if (!(phy_reg_data & 0x20)) {
-		printf ("Ethernet port changed link status to DOWN\n");
-	} else {
-		port_status =
-			MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
-		printf ("Ethernet status port %d: Link up", port_num);
-		printf (", %s",
-			(port_status & BIT2) ? "Full Duplex" : "Half Duplex");
-		if (port_status & BIT4)
-			printf (", Speed 1 Gbps");
-		else
-			printf (", %s",
-				(port_status & BIT5) ? "Speed 100 Mbps" :
-				"Speed 10 Mbps");
-		printf ("\n");
-	}
-}
-
-/**********************************************************************
- * u-boot entry functions for mv64460_eth
- *
- **********************************************************************/
-int db64460_eth_probe (struct eth_device *dev)
-{
-	return ((int) db64460_eth_start (dev));
-}
-
-int db64460_eth_poll (struct eth_device *dev)
-{
-	return mv64460_eth_receive (dev);
-}
-
-int db64460_eth_transmit(struct eth_device *dev, void *packet, int length)
-{
-	mv64460_eth_xmit (dev, packet, length);
-	return 0;
-}
-
-void db64460_eth_disable (struct eth_device *dev)
-{
-	mv64460_eth_stop (dev);
-}
-
-
-void mv6446x_eth_initialize (bd_t * bis)
-{
-	struct eth_device *dev;
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	int devnum, x, temp;
-	char *s, *e, buf[64];
-
-	for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
-		dev = calloc (sizeof (*dev), 1);
-		if (!dev) {
-			printf ("%s: mv_enet%d allocation failure, %s\n",
-				__FUNCTION__, devnum, "eth_device structure");
-			return;
-		}
-
-		/* must be less than sizeof(dev->name) */
-		sprintf (dev->name, "mv_enet%d", devnum);
-
-#ifdef DEBUG
-		printf ("Initializing %s\n", dev->name);
-#endif
-
-		/* Extract the MAC address from the environment */
-		switch (devnum) {
-		case 0:
-			s = "ethaddr";
-			break;
-
-		case 1:
-			s = "eth1addr";
-			break;
-
-		case 2:
-			s = "eth2addr";
-			break;
-
-		default:	/* this should never happen */
-			printf ("%s: Invalid device number %d\n",
-				__FUNCTION__, devnum);
-			return;
-		}
-
-		temp = getenv_f(s, buf, sizeof (buf));
-		s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
-		printf ("Setting MAC %d to %s\n", devnum, s);
-#endif
-		for (x = 0; x < 6; ++x) {
-			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
-			if (s)
-				s = (*e) ? e + 1 : e;
-		}
-		/* ronen - set the MAC addr in the HW */
-		eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
-
-		dev->init = (void *) db64460_eth_probe;
-		dev->halt = (void *) ethernet_phy_reset;
-		dev->send = (void *) db64460_eth_transmit;
-		dev->recv = (void *) db64460_eth_poll;
-
-		ethernet_private = calloc (sizeof (*ethernet_private), 1);
-		dev->priv = (void *)ethernet_private;
-		if (!ethernet_private) {
-			printf ("%s: %s allocation failure, %s\n",
-				__FUNCTION__, dev->name,
-				"Private Device Structure");
-			free (dev);
-			return;
-		}
-		/* start with an zeroed ETH_PORT_INFO */
-		memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
-		memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
-
-		/* set pointer to memory for stats data structure etc... */
-		port_private = calloc (sizeof (*ethernet_private), 1);
-		ethernet_private->port_private = (void *)port_private;
-		if (!port_private) {
-			printf ("%s: %s allocation failure, %s\n",
-				__FUNCTION__, dev->name,
-				"Port Private Device Structure");
-
-			free (ethernet_private);
-			free (dev);
-			return;
-		}
-
-		port_private->stats =
-			calloc (sizeof (struct net_device_stats), 1);
-		if (!port_private->stats) {
-			printf ("%s: %s allocation failure, %s\n",
-				__FUNCTION__, dev->name,
-				"Net stat Structure");
-
-			free (port_private);
-			free (ethernet_private);
-			free (dev);
-			return;
-		}
-		memset (ethernet_private->port_private, 0,
-			sizeof (struct mv64460_eth_priv));
-		switch (devnum) {
-		case 0:
-			ethernet_private->port_num = ETH_0;
-			break;
-		case 1:
-			ethernet_private->port_num = ETH_1;
-			break;
-		case 2:
-			ethernet_private->port_num = ETH_2;
-			break;
-		default:
-			printf ("Invalid device number %d\n", devnum);
-			break;
-		};
-
-		port_private->port_num = devnum;
-		/*
-		 * Read MIB counter on the GT in order to reset them,
-		 * then zero all the stats fields in memory
-		 */
-		mv64460_eth_update_stat (dev);
-		memset (port_private->stats, 0,
-			sizeof (struct net_device_stats));
-		/* Extract the MAC address from the environment */
-		switch (devnum) {
-		case 0:
-			s = "ethaddr";
-			break;
-
-		case 1:
-			s = "eth1addr";
-			break;
-
-		case 2:
-			s = "eth2addr";
-			break;
-
-		default:	/* this should never happen */
-			printf ("%s: Invalid device number %d\n",
-				__FUNCTION__, devnum);
-			return;
-		}
-
-		temp = getenv_f(s, buf, sizeof (buf));
-		s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
-		printf ("Setting MAC %d to %s\n", devnum, s);
-#endif
-		for (x = 0; x < 6; ++x) {
-			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
-			if (s)
-				s = (*e) ? e + 1 : e;
-		}
-
-		DP (printf ("Allocating descriptor and buffer rings\n"));
-
-		ethernet_private->p_rx_desc_area_base[0] =
-			(ETH_RX_DESC *) memalign (16,
-						  RX_DESC_ALIGNED_SIZE *
-						  MV64460_RX_QUEUE_SIZE + 1);
-		ethernet_private->p_tx_desc_area_base[0] =
-			(ETH_TX_DESC *) memalign (16,
-						  TX_DESC_ALIGNED_SIZE *
-						  MV64460_TX_QUEUE_SIZE + 1);
-
-		ethernet_private->p_rx_buffer_base[0] =
-			(char *) memalign (16,
-					   MV64460_RX_QUEUE_SIZE *
-					   MV64460_TX_BUFFER_SIZE + 1);
-		ethernet_private->p_tx_buffer_base[0] =
-			(char *) memalign (16,
-					   MV64460_RX_QUEUE_SIZE *
-					   MV64460_TX_BUFFER_SIZE + 1);
-
-#ifdef DEBUG_MV_ETH
-		/* DEBUG OUTPUT prints adresses of globals */
-		print_globals (dev);
-#endif
-		eth_register (dev);
-
-	}
-	DP (printf ("%s: exit\n", __FUNCTION__));
-
-}
-
-/**********************************************************************
- * mv64460_eth_open
- *
- * This function is called when openning the network device. The function
- * should initialize all the hardware, initialize cyclic Rx/Tx
- * descriptors chain and buffers and allocate an IRQ to the network
- * device.
- *
- * Input : a pointer to the network device structure
- * / / ronen - changed the output to match  net/eth.c needs
- * Output : nonzero of success , zero if fails.
- * under construction
- **********************************************************************/
-
-int mv64460_eth_open (struct eth_device *dev)
-{
-	return (mv64460_eth_real_open (dev));
-}
-
-/* Helper function for mv64460_eth_open */
-static int mv64460_eth_real_open (struct eth_device *dev)
-{
-
-	unsigned int queue;
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	unsigned int port_num;
-	u32 phy_reg_data;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	/* ronen - when we update the MAC env params we only update dev->enetaddr
-	   see ./net/eth.c eth_set_enetaddr() */
-	memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
-
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-	/* Stop RX Queues */
-	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
-		      0x0000ff00);
-
-	/* Clear the ethernet port interrupts */
-	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
-	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
-
-	/* Unmask RX buffer and TX end interrupt */
-	MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num),
-		      INT_CAUSE_UNMASK_ALL);
-
-	/* Unmask phy and link status changes interrupts */
-	MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
-		      INT_CAUSE_UNMASK_ALL_EXT);
-
-	/* Set phy address of the port */
-	ethernet_private->port_phy_addr = 0x8 + port_num;
-
-	/* Activate the DMA channels etc */
-	eth_port_init (ethernet_private);
-
-
-	/* "Allocate" setup TX rings */
-
-	for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
-		unsigned int size;
-
-		port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE;
-		size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE);	/*size = no of DESCs times DESC-size */
-		ethernet_private->tx_desc_area_size[queue] = size;
-
-		/* first clear desc area completely */
-		memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
-			0, ethernet_private->tx_desc_area_size[queue]);
-
-		/* initialize tx desc ring with low level driver */
-		if (ether_init_tx_desc_ring
-		    (ethernet_private, ETH_Q0,
-		     port_private->tx_ring_size[queue],
-		     MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
-		     (unsigned int) ethernet_private->
-		     p_tx_desc_area_base[queue],
-		     (unsigned int) ethernet_private->
-		     p_tx_buffer_base[queue]) == false)
-			printf ("### Error initializing TX Ring\n");
-	}
-
-	/* "Allocate" setup RX rings */
-	for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
-		unsigned int size;
-
-		/* Meantime RX Ring are fixed - but must be configurable by user */
-		port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE;
-		size = (port_private->rx_ring_size[queue] *
-			RX_DESC_ALIGNED_SIZE);
-		ethernet_private->rx_desc_area_size[queue] = size;
-
-		/* first clear desc area completely */
-		memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
-			0, ethernet_private->rx_desc_area_size[queue]);
-		if ((ether_init_rx_desc_ring
-		     (ethernet_private, ETH_Q0,
-		      port_private->rx_ring_size[queue],
-		      MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
-		      (unsigned int) ethernet_private->
-		      p_rx_desc_area_base[queue],
-		      (unsigned int) ethernet_private->
-		      p_rx_buffer_base[queue])) == false)
-			printf ("### Error initializing RX Ring\n");
-	}
-
-	eth_port_start (ethernet_private);
-
-	/* Set maximum receive buffer to 9700 bytes */
-	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num),
-		      (0x5 << 17) |
-		      (MV_REG_READ
-		       (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num))
-		       & 0xfff1ffff));
-
-	/*
-	 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
-	 * disable the leaky bucket mechanism .
-	 */
-
-	MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
-	MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
-
-	/* Check Link status on phy */
-	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
-	if (!(phy_reg_data & 0x20)) {
-		/* Reset PHY */
-		if ((ethernet_phy_reset (port_num)) != true) {
-			printf ("$$ Warnning: No link on port %d \n",
-				port_num);
-			return 0;
-		} else {
-			eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
-			if (!(phy_reg_data & 0x20)) {
-				printf ("### Error: Phy is not active\n");
-				return 0;
-			}
-		}
-	} else {
-		mv64460_eth_print_phy_status (dev);
-	}
-	port_private->eth_running = MAGIC_ETH_RUNNING;
-	return 1;
-}
-
-
-static int mv64460_eth_free_tx_rings (struct eth_device *dev)
-{
-	unsigned int queue;
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	unsigned int port_num;
-	volatile ETH_TX_DESC *p_tx_curr_desc;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-	/* Stop Tx Queues */
-	MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
-		      0x0000ff00);
-
-	/* Free TX rings */
-	DP (printf ("Clearing previously allocated TX queues... "));
-	for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
-		/* Free on TX rings */
-		for (p_tx_curr_desc =
-		     ethernet_private->p_tx_desc_area_base[queue];
-		     ((unsigned int) p_tx_curr_desc <= (unsigned int)
-		      ethernet_private->p_tx_desc_area_base[queue] +
-		      ethernet_private->tx_desc_area_size[queue]);
-		     p_tx_curr_desc =
-		     (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
-				      TX_DESC_ALIGNED_SIZE)) {
-			/* this is inside for loop */
-			if (p_tx_curr_desc->return_info != 0) {
-				p_tx_curr_desc->return_info = 0;
-				DP (printf ("freed\n"));
-			}
-		}
-		DP (printf ("Done\n"));
-	}
-	return 0;
-}
-
-static int mv64460_eth_free_rx_rings (struct eth_device *dev)
-{
-	unsigned int queue;
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	unsigned int port_num;
-	volatile ETH_RX_DESC *p_rx_curr_desc;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-
-	/* Stop RX Queues */
-	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
-		      0x0000ff00);
-
-	/* Free RX rings */
-	DP (printf ("Clearing previously allocated RX queues... "));
-	for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
-		/* Free preallocated skb's on RX rings */
-		for (p_rx_curr_desc =
-		     ethernet_private->p_rx_desc_area_base[queue];
-		     (((unsigned int) p_rx_curr_desc <
-		       ((unsigned int) ethernet_private->
-			p_rx_desc_area_base[queue] +
-			ethernet_private->rx_desc_area_size[queue])));
-		     p_rx_curr_desc =
-		     (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
-				      RX_DESC_ALIGNED_SIZE)) {
-			if (p_rx_curr_desc->return_info != 0) {
-				p_rx_curr_desc->return_info = 0;
-				DP (printf ("freed\n"));
-			}
-		}
-		DP (printf ("Done\n"));
-	}
-	return 0;
-}
-
-/**********************************************************************
- * mv64460_eth_stop
- *
- * This function is used when closing the network device.
- * It updates the hardware,
- * release all memory that holds buffers and descriptors and release the IRQ.
- * Input : a pointer to the device structure
- * Output : zero if success , nonzero if fails
- *********************************************************************/
-
-int mv64460_eth_stop (struct eth_device *dev)
-{
-	/* Disable all gigE address decoder */
-	MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
-	DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
-	mv64460_eth_real_stop (dev);
-
-	return 0;
-};
-
-/* Helper function for mv64460_eth_stop */
-
-static int mv64460_eth_real_stop (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	unsigned int port_num;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-
-	mv64460_eth_free_tx_rings (dev);
-	mv64460_eth_free_rx_rings (dev);
-
-	eth_port_reset (ethernet_private->port_num);
-	/* Disable ethernet port interrupts */
-	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
-	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
-	/* Mask RX buffer and TX end interrupt */
-	MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0);
-	/* Mask phy and link status changes interrupts */
-	MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
-	MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH,
-			   BIT0 << port_num);
-	/* Print Network statistics */
-#ifndef  UPDATE_STATS_BY_SOFTWARE
-	/*
-	 * Print statistics (only if ethernet is running),
-	 * then zero all the stats fields in memory
-	 */
-	if (port_private->eth_running == MAGIC_ETH_RUNNING) {
-		port_private->eth_running = 0;
-		mv64460_eth_print_stat (dev);
-	}
-	memset (port_private->stats, 0, sizeof (struct net_device_stats));
-#endif
-	DP (printf ("\nEthernet stopped ... \n"));
-	return 0;
-}
-
-
-/**********************************************************************
- * mv64460_eth_start_xmit
- *
- * This function is queues a packet in the Tx descriptor for
- * required port.
- *
- * Input : skb - a pointer to socket buffer
- *         dev - a pointer to the required port
- *
- * Output : zero upon success
- **********************************************************************/
-
-int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
-		      int dataSize)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	PKT_INFO pkt_info;
-	ETH_FUNC_RET_STATUS status;
-	struct net_device_stats *stats;
-	ETH_FUNC_RET_STATUS release_result;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-
-	stats = port_private->stats;
-
-	/* Update packet info data structure */
-	pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;	/* DMA owned, first last */
-	pkt_info.byte_cnt = dataSize;
-	pkt_info.buf_ptr = (unsigned int) dataPtr;
-	pkt_info.return_info = 0;
-
-	status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
-	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
-		printf ("Error on transmitting packet ..");
-		if (status == ETH_QUEUE_FULL)
-			printf ("ETH Queue is full. \n");
-		if (status == ETH_QUEUE_LAST_RESOURCE)
-			printf ("ETH Queue: using last available resource. \n");
-		goto error;
-	}
-
-	/* Update statistics and start of transmittion time */
-	stats->tx_bytes += dataSize;
-	stats->tx_packets++;
-
-	/* Check if packet(s) is(are) transmitted correctly (release everything) */
-	do {
-		release_result =
-			eth_tx_return_desc (ethernet_private, ETH_Q0,
-					    &pkt_info);
-		switch (release_result) {
-		case ETH_OK:
-			DP (printf ("descriptor released\n"));
-			if (pkt_info.cmd_sts & BIT0) {
-				printf ("Error in TX\n");
-				stats->tx_errors++;
-
-			}
-			break;
-		case ETH_RETRY:
-			DP (printf ("transmission still in process\n"));
-			break;
-
-		case ETH_ERROR:
-			printf ("routine can not access Tx desc ring\n");
-			break;
-
-		case ETH_END_OF_JOB:
-			DP (printf ("the routine has nothing to release\n"));
-			break;
-		default:	/* should not happen */
-			break;
-		}
-	} while (release_result == ETH_OK);
-
-
-	return 0;		/* success */
-      error:
-	return 1;		/* Failed - higher layers will free the skb */
-}
-
-/**********************************************************************
- * mv64460_eth_receive
- *
- * This function is forward packets that are received from the port's
- * queues toward kernel core or FastRoute them to another interface.
- *
- * Input : dev - a pointer to the required interface
- *         max - maximum number to receive (0 means unlimted)
- *
- * Output : number of served packets
- **********************************************************************/
-
-int mv64460_eth_receive (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	PKT_INFO pkt_info;
-	struct net_device_stats *stats;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-	stats = port_private->stats;
-
-	while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
-		ETH_OK)) {
-
-#ifdef DEBUG_MV_ETH
-		if (pkt_info.byte_cnt != 0) {
-			printf ("%s: Received %d byte Packet @ 0x%x\n",
-				__FUNCTION__, pkt_info.byte_cnt,
-				pkt_info.buf_ptr);
-		}
-#endif
-		/* Update statistics. Note byte count includes 4 byte CRC count */
-		stats->rx_packets++;
-		stats->rx_bytes += pkt_info.byte_cnt;
-
-		/*
-		 * In case received a packet without first / last bits on OR the error
-		 * summary bit is on, the packets needs to be dropeed.
-		 */
-		if (((pkt_info.
-		      cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
-		     (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
-		    || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
-			stats->rx_dropped++;
-
-			printf ("Received packet spread on multiple descriptors\n");
-
-			/* Is this caused by an error ? */
-			if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
-				stats->rx_errors++;
-			}
-
-			/* free these descriptors again without forwarding them to the higher layers */
-			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
-			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
-
-			if (eth_rx_return_buff
-			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
-				printf ("Error while returning the RX Desc to Ring\n");
-			} else {
-				DP (printf ("RX Desc returned to Ring\n"));
-			}
-			/* /free these descriptors again */
-		} else {
-
-/* !!! call higher layer processing */
-#ifdef DEBUG_MV_ETH
-			printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
-#endif
-			/* let the upper layer handle the packet */
-			NetReceive ((uchar *) pkt_info.buf_ptr,
-				    (int) pkt_info.byte_cnt);
-
-/* **************************************************************** */
-/* free descriptor  */
-			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
-			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
-			DP (printf
-			    ("RX: pkt_info.buf_ptr =	%x\n",
-			     pkt_info.buf_ptr));
-			if (eth_rx_return_buff
-			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
-				printf ("Error while returning the RX Desc to Ring\n");
-			} else {
-				DP (printf ("RX Desc returned to Ring\n"));
-			}
-
-/* **************************************************************** */
-
-		}
-	}
-	mv64460_eth_get_stats (dev);	/* update statistics */
-	return 1;
-}
-
-/**********************************************************************
- * mv64460_eth_get_stats
- *
- * Returns a pointer to the interface statistics.
- *
- * Input : dev - a pointer to the required interface
- *
- * Output : a pointer to the interface's statistics
- **********************************************************************/
-
-static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-
-	mv64460_eth_update_stat (dev);
-
-	return port_private->stats;
-}
-
-
-/**********************************************************************
- * mv64460_eth_update_stat
- *
- * Update the statistics structure in the private data structure
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64460_eth_update_stat (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	struct net_device_stats *stats;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-	stats = port_private->stats;
-
-	/* These are false updates */
-	stats->rx_packets += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_FRAMES_RECEIVED);
-	stats->tx_packets += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_FRAMES_SENT);
-	stats->rx_bytes += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
-	/*
-	 * Ideally this should be as follows -
-	 *
-	 *   stats->rx_bytes   += stats->rx_bytes +
-	 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
-	 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
-	 *
-	 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
-	 * is just a dummy read for proper work of the GigE port
-	 */
-	eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
-	stats->tx_bytes += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_OCTETS_SENT_LOW);
-	eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_OCTETS_SENT_HIGH);
-	stats->rx_errors += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_MAC_RECEIVE_ERROR);
-
-	/* Rx dropped is for received packet with CRC error */
-	stats->rx_dropped +=
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_BAD_CRC_EVENT);
-	stats->multicast += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_MULTICAST_FRAMES_RECEIVED);
-	stats->collisions +=
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_COLLISION) +
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_LATE_COLLISION);
-	/* detailed rx errors */
-	stats->rx_length_errors +=
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_UNDERSIZE_RECEIVED)
-		+
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_OVERSIZE_RECEIVED);
-	/* detailed tx errors */
-}
-
-#ifndef  UPDATE_STATS_BY_SOFTWARE
-/**********************************************************************
- * mv64460_eth_print_stat
- *
- * Update the statistics structure in the private data structure
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64460_eth_print_stat (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	struct net_device_stats *stats;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-	stats = port_private->stats;
-
-	/* These are false updates */
-	printf ("\n### Network statistics: ###\n");
-	printf ("--------------------------\n");
-	printf (" Packets received:		%ld\n", stats->rx_packets);
-	printf (" Packets send:			%ld\n", stats->tx_packets);
-	printf (" Received bytes:		%ld\n", stats->rx_bytes);
-	printf (" Send bytes:			%ld\n", stats->tx_bytes);
-	if (stats->rx_errors != 0)
-		printf (" Rx Errors:			%ld\n",
-			stats->rx_errors);
-	if (stats->rx_dropped != 0)
-		printf (" Rx dropped (CRC Errors):	%ld\n",
-			stats->rx_dropped);
-	if (stats->multicast != 0)
-		printf (" Rx mulicast frames:		%ld\n",
-			stats->multicast);
-	if (stats->collisions != 0)
-		printf (" No. of collisions:		%ld\n",
-			stats->collisions);
-	if (stats->rx_length_errors != 0)
-		printf (" Rx length errors:		%ld\n",
-			stats->rx_length_errors);
-}
-#endif
-
-/**************************************************************************
- *network_start - Network Kick Off Routine UBoot
- *Inputs :
- *Outputs :
- **************************************************************************/
-
-bool db64460_eth_start (struct eth_device *dev)
-{
-	return (mv64460_eth_open (dev));	/* calls real open */
-}
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The second part is the low level driver of the gigE ethernet ports.   *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-/*
- * based on Linux code
- * arch/powerpc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/********************************************************************************
- * Marvell's Gigabit Ethernet controller low level driver
- *
- * DESCRIPTION:
- *       This file introduce low level API to Marvell's Gigabit Ethernet
- *		controller. This Gigabit Ethernet Controller driver API controls
- *		1) Operations (i.e. port init, start, reset etc').
- *		2) Data flow (i.e. port send, receive etc').
- *		Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
- *		struct.
- *		This struct includes user configuration information as well as
- *		driver internal data needed for its operations.
- *
- *		Supported Features:
- *		- This low level driver is OS independent. Allocating memory for
- *		  the descriptor rings and buffers are not within the scope of
- *		  this driver.
- *		- The user is free from Rx/Tx queue managing.
- *		- This low level driver introduce functionality API that enable
- *		  the to operate Marvell's Gigabit Ethernet Controller in a
- *		  convenient way.
- *		- Simple Gigabit Ethernet port operation API.
- *		- Simple Gigabit Ethernet port data flow API.
- *		- Data flow and operation API support per queue functionality.
- *		- Support cached descriptors for better performance.
- *		- Enable access to all four DRAM banks and internal SRAM memory
- *		  spaces.
- *		- PHY access and control API.
- *		- Port control register configuration API.
- *		- Full control over Unicast and Multicast MAC configurations.
- *
- *		Operation flow:
- *
- *		Initialization phase
- *		This phase complete the initialization of the ETH_PORT_INFO
- *		struct.
- *		User information regarding port configuration has to be set
- *		prior to calling the port initialization routine. For example,
- *		the user has to assign the port_phy_addr field which is board
- *		depended parameter.
- *		In this phase any port Tx/Rx activity is halted, MIB counters
- *		are cleared, PHY address is set according to user parameter and
- *		access to DRAM and internal SRAM memory spaces.
- *
- *		Driver ring initialization
- *		Allocating memory for the descriptor rings and buffers is not
- *		within the scope of this driver. Thus, the user is required to
- *		allocate memory for the descriptors ring and buffers. Those
- *		memory parameters are used by the Rx and Tx ring initialization
- *		routines in order to curve the descriptor linked list in a form
- *		of a ring.
- *		Note: Pay special attention to alignment issues when using
- *		cached descriptors/buffers. In this phase the driver store
- *		information in the ETH_PORT_INFO struct regarding each queue
- *		ring.
- *
- *		Driver start
- *		This phase prepares the Ethernet port for Rx and Tx activity.
- *		It uses the information stored in the ETH_PORT_INFO struct to
- *		initialize the various port registers.
- *
- *		Data flow:
- *		All packet references to/from the driver are done using PKT_INFO
- *		struct.
- *		This struct is a unified struct used with Rx and Tx operations.
- *		This way the user is not required to be familiar with neither
- *		Tx nor Rx descriptors structures.
- *		The driver's descriptors rings are management by indexes.
- *		Those indexes controls the ring resources and used to indicate
- *		a SW resource error:
- *		'current'
- *		This index points to the current available resource for use. For
- *		example in Rx process this index will point to the descriptor
- *		that will be passed to the user upon calling the receive routine.
- *		In Tx process, this index will point to the descriptor
- *		that will be assigned with the user packet info and transmitted.
- *		'used'
- *		This index points to the descriptor that need to restore its
- *		resources. For example in Rx process, using the Rx buffer return
- *		API will attach the buffer returned in packet info to the
- *		descriptor pointed by 'used'. In Tx process, using the Tx
- *		descriptor return will merely return the user packet info with
- *		the command status of  the transmitted buffer pointed by the
- *		'used' index. Nevertheless, it is essential to use this routine
- *		to update the 'used' index.
- *		'first'
- *		This index supports Tx Scatter-Gather. It points to the first
- *		descriptor of a packet assembled of multiple buffers. For example
- *		when in middle of Such packet we have a Tx resource error the
- *		'curr' index get the value of 'first' to indicate that the ring
- *		returned to its state before trying to transmit this packet.
- *
- *		Receive operation:
- *		The eth_port_receive API set the packet information struct,
- *		passed by the caller, with received information from the
- *		'current' SDMA descriptor.
- *		It is the user responsibility to return this resource back
- *		to the Rx descriptor ring to enable the reuse of this source.
- *		Return Rx resource is done using the eth_rx_return_buff API.
- *
- *		Transmit operation:
- *		The eth_port_send API supports Scatter-Gather which enables to
- *		send a packet spanned over multiple buffers. This means that
- *		for each packet info structure given by the user and put into
- *		the Tx descriptors ring, will be transmitted only if the 'LAST'
- *		bit will be set in the packet info command status field. This
- *		API also consider restriction regarding buffer alignments and
- *		sizes.
- *		The user must return a Tx resource after ensuring the buffer
- *		has been transmitted to enable the Tx ring indexes to update.
- *
- *		BOARD LAYOUT
- *		This device is on-board.  No jumper diagram is necessary.
- *
- *		EXTERNAL INTERFACE
- *
- *       Prior to calling the initialization routine eth_port_init() the user
- *	 must set the following fields under ETH_PORT_INFO struct:
- *       port_num             User Ethernet port number.
- *       port_phy_addr		    User PHY address of Ethernet port.
- *       port_mac_addr[6]	    User defined port MAC address.
- *       port_config          User port configuration value.
- *       port_config_extend    User port config extend value.
- *       port_sdma_config      User port SDMA config value.
- *       port_serial_control   User port serial control value.
- *       *port_virt_to_phys ()  User function to cast virtual addr to CPU bus addr.
- *       *port_private        User scratch pad for user specific data structures.
- *
- *       This driver introduce a set of default values:
- *       PORT_CONFIG_VALUE           Default port configuration value
- *       PORT_CONFIG_EXTEND_VALUE    Default port extend configuration value
- *       PORT_SDMA_CONFIG_VALUE      Default sdma control value
- *       PORT_SERIAL_CONTROL_VALUE   Default port serial control value
- *
- *		This driver data flow is done using the PKT_INFO struct which is
- *		a unified struct for Rx and Tx operations:
- *		byte_cnt	Tx/Rx descriptor buffer byte count.
- *		l4i_chk		CPU provided TCP Checksum. For Tx operation only.
- *		cmd_sts		Tx/Rx descriptor command status.
- *		buf_ptr		Tx/Rx descriptor buffer pointer.
- *		return_info	Tx/Rx user resource return information.
- *
- *
- *		EXTERNAL SUPPORT REQUIREMENTS
- *
- *		This driver requires the following external support:
- *
- *		D_CACHE_FLUSH_LINE (address, address offset)
- *
- *		This macro applies assembly code to flush and invalidate cache
- *		line.
- *		address        - address base.
- *		address offset - address offset
- *
- *
- *		CPU_PIPE_FLUSH
- *
- *		This macro applies assembly code to flush the CPU pipeline.
- *
- *******************************************************************************/
-/* includes */
-
-/* defines */
-/* SDMA command macros */
-#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
- MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
-
-#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
- MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
- (1 << (8 + tx_queue)))
-
-#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
-MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
-
-#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
-MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
-
-#define CURR_RFD_GET(p_curr_desc, queue) \
- ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
-
-#define CURR_RFD_SET(p_curr_desc, queue) \
- (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
-
-#define USED_RFD_GET(p_used_desc, queue) \
- ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
-
-#define USED_RFD_SET(p_used_desc, queue)\
-(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
-
-
-#define CURR_TFD_GET(p_curr_desc, queue) \
- ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
-
-#define CURR_TFD_SET(p_curr_desc, queue) \
- (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
-
-#define USED_TFD_GET(p_used_desc, queue) \
- ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
-
-#define USED_TFD_SET(p_used_desc, queue) \
- (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
-
-#define FIRST_TFD_GET(p_first_desc, queue) \
- ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
-
-#define FIRST_TFD_SET(p_first_desc, queue) \
- (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
-
-
-/* Macros that save access to desc in order to find next desc pointer  */
-#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
-
-#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
-
-#define LINK_UP_TIMEOUT		100000
-#define PHY_BUSY_TIMEOUT    10000000
-
-/* locals */
-
-/* PHY routines */
-static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
-static int ethernet_phy_get (ETH_PORT eth_port_num);
-
-/* Ethernet Port routines */
-static void eth_set_access_control (ETH_PORT eth_port_num,
-				    ETH_WIN_PARAM * param);
-static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
-			      ETH_QUEUE queue, int option);
-#if 0				/* FIXME */
-static bool eth_port_smc_addr (ETH_PORT eth_port_num,
-			       unsigned char mc_byte,
-			       ETH_QUEUE queue, int option);
-static bool eth_port_omc_addr (ETH_PORT eth_port_num,
-			       unsigned char crc8,
-			       ETH_QUEUE queue, int option);
-#endif
-
-static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
-			int byte_count);
-
-void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
-
-
-typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
-u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
-{
-	u32 result = 0;
-	u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
-
-	if (enable & (1 << bank))
-		return 0;
-	if (bank == BANK0)
-		result = MV_REG_READ (MV64460_CS_0_BASE_ADDR);
-	if (bank == BANK1)
-		result = MV_REG_READ (MV64460_CS_1_BASE_ADDR);
-	if (bank == BANK2)
-		result = MV_REG_READ (MV64460_CS_2_BASE_ADDR);
-	if (bank == BANK3)
-		result = MV_REG_READ (MV64460_CS_3_BASE_ADDR);
-	result &= 0x0000ffff;
-	result = result << 16;
-	return result;
-}
-
-u32 mv_get_dram_bank_size (MEMORY_BANK bank)
-{
-	u32 result = 0;
-	u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
-
-	if (enable & (1 << bank))
-		return 0;
-	if (bank == BANK0)
-		result = MV_REG_READ (MV64460_CS_0_SIZE);
-	if (bank == BANK1)
-		result = MV_REG_READ (MV64460_CS_1_SIZE);
-	if (bank == BANK2)
-		result = MV_REG_READ (MV64460_CS_2_SIZE);
-	if (bank == BANK3)
-		result = MV_REG_READ (MV64460_CS_3_SIZE);
-	result += 1;
-	result &= 0x0000ffff;
-	result = result << 16;
-	return result;
-}
-
-u32 mv_get_internal_sram_base (void)
-{
-	u32 result;
-
-	result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR);
-	result &= 0x0000ffff;
-	result = result << 16;
-	return result;
-}
-
-/*******************************************************************************
-* eth_port_init - Initialize the Ethernet port driver
-*
-* DESCRIPTION:
-*       This function prepares the ethernet port to start its activity:
-*       1) Completes the ethernet port driver struct initialization toward port
-*           start routine.
-*       2) Resets the device to a quiescent state in case of warm reboot.
-*       3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
-*       4) Clean MAC tables. The reset status of those tables is unknown.
-*       5) Set PHY address.
-*       Note: Call this routine prior to eth_port_start routine and after setting
-*       user values in the user fields of Ethernet port control struct (i.e.
-*       port_phy_addr).
-*
-* INPUT:
-*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
-*
-* OUTPUT:
-*       See description.
-*
-* RETURN:
-*       None.
-*
-*******************************************************************************/
-static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
-{
-	int queue;
-	ETH_WIN_PARAM win_param;
-
-	p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
-	p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
-	p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
-	p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
-
-	p_eth_port_ctrl->port_rx_queue_command = 0;
-	p_eth_port_ctrl->port_tx_queue_command = 0;
-
-	/* Zero out SW structs */
-	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
-		CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
-		USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
-		p_eth_port_ctrl->rx_resource_err[queue] = false;
-	}
-
-	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
-		CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
-		USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
-		FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
-		p_eth_port_ctrl->tx_resource_err[queue] = false;
-	}
-
-	eth_port_reset (p_eth_port_ctrl->port_num);
-
-	/* Set access parameters for DRAM bank 0 */
-	win_param.win = ETH_WIN0;	/* Use Ethernet window 0 */
-	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR  */
-	win_param.attributes = EBAR_ATTR_DRAM_CS0;	/* Enable DRAM bank   */
-#ifndef CONFIG_NOT_COHERENT_CACHE
-	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
-	win_param.high_addr = 0;
-	/* Get bank base */
-	win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
-	win_param.size = mv_get_dram_bank_size (BANK0);	/* Get bank size */
-	if (win_param.size == 0)
-		win_param.enable = 0;
-	else
-		win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	/* Set access parameters for DRAM bank 1 */
-	win_param.win = ETH_WIN1;	/* Use Ethernet window 1 */
-	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
-	win_param.attributes = EBAR_ATTR_DRAM_CS1;	/* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
-	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
-	win_param.high_addr = 0;
-	/* Get bank base */
-	win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
-	win_param.size = mv_get_dram_bank_size (BANK1);	/* Get bank size */
-	if (win_param.size == 0)
-		win_param.enable = 0;
-	else
-		win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	/* Set access parameters for DRAM bank 2 */
-	win_param.win = ETH_WIN2;	/* Use Ethernet window 2 */
-	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
-	win_param.attributes = EBAR_ATTR_DRAM_CS2;	/* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
-	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
-	win_param.high_addr = 0;
-	/* Get bank base */
-	win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
-	win_param.size = mv_get_dram_bank_size (BANK2);	/* Get bank size */
-	if (win_param.size == 0)
-		win_param.enable = 0;
-	else
-		win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	/* Set access parameters for DRAM bank 3 */
-	win_param.win = ETH_WIN3;	/* Use Ethernet window 3 */
-	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
-	win_param.attributes = EBAR_ATTR_DRAM_CS3;	/* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
-	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
-	win_param.high_addr = 0;
-	/* Get bank base */
-	win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
-	win_param.size = mv_get_dram_bank_size (BANK3);	/* Get bank size */
-	if (win_param.size == 0)
-		win_param.enable = 0;
-	else
-		win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	/* Set access parameters for Internal SRAM */
-	win_param.win = ETH_WIN4;	/* Use Ethernet window 0 */
-	win_param.target = EBAR_TARGET_CBS;	/* Target - Internal SRAM */
-	win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
-	win_param.high_addr = 0;
-	win_param.base_addr = mv_get_internal_sram_base ();	/* Get base addr */
-	win_param.size = MV64460_INTERNAL_SRAM_SIZE;	/* Get bank size */
-	win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
-
-	ethernet_phy_set (p_eth_port_ctrl->port_num,
-			  p_eth_port_ctrl->port_phy_addr);
-
-	return;
-
-}
-
-/*******************************************************************************
-* eth_port_start - Start the Ethernet port activity.
-*
-* DESCRIPTION:
-*       This routine prepares the Ethernet port for Rx and Tx activity:
-*       1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
-*           has been initialized a descriptor's ring (using ether_init_tx_desc_ring
-*           for Tx and ether_init_rx_desc_ring for Rx)
-*       2. Initialize and enable the Ethernet configuration port by writing to
-*           the port's configuration and command registers.
-*       3. Initialize and enable the SDMA by writing to the SDMA's
-*    configuration and command registers.
-*       After completing these steps, the ethernet port SDMA can starts to
-*       perform Rx and Tx activities.
-*
-*       Note: Each Rx and Tx queue descriptor's list must be initialized prior
-*       to calling this function (use ether_init_tx_desc_ring for Tx queues and
-*       ether_init_rx_desc_ring for Rx queues).
-*
-* INPUT:
-*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
-*
-* OUTPUT:
-*       Ethernet port is ready to receive and transmit.
-*
-* RETURN:
-*       false if the port PHY is not up.
-*       true otherwise.
-*
-*******************************************************************************/
-static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
-{
-	int queue;
-	volatile ETH_TX_DESC *p_tx_curr_desc;
-	volatile ETH_RX_DESC *p_rx_curr_desc;
-	unsigned int phy_reg_data;
-	ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
-
-
-	/* Assignment of Tx CTRP of given queue */
-	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
-		CURR_TFD_GET (p_tx_curr_desc, queue);
-		MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
-			       (eth_port_num)
-			       + (4 * queue)),
-			      ((unsigned int) p_tx_curr_desc));
-
-	}
-
-	/* Assignment of Rx CRDP of given queue */
-	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
-		CURR_RFD_GET (p_rx_curr_desc, queue);
-		MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
-			       (eth_port_num)
-			       + (4 * queue)),
-			      ((unsigned int) p_rx_curr_desc));
-
-		if (p_rx_curr_desc != NULL)
-			/* Add the assigned Ethernet address to the port's address table */
-			eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
-					      p_eth_port_ctrl->port_mac_addr,
-					      queue);
-	}
-
-	/* Assign port configuration and command. */
-	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
-		      p_eth_port_ctrl->port_config);
-
-	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
-		      p_eth_port_ctrl->port_config_extend);
-
-	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
-		      p_eth_port_ctrl->port_serial_control);
-
-	MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
-			 ETH_SERIAL_PORT_ENABLE);
-
-	/* Assign port SDMA configuration */
-	MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
-		      p_eth_port_ctrl->port_sdma_config);
-
-	MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
-		      (eth_port_num), 0x3fffffff);
-	MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
-		      (eth_port_num), 0x03fffcff);
-	/* Turn off the port/queue bandwidth limitation */
-	MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
-
-	/* Enable port Rx. */
-	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
-		      p_eth_port_ctrl->port_rx_queue_command);
-
-	/* Check if link is up */
-	eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
-
-	if (!(phy_reg_data & 0x20))
-		return false;
-
-	return true;
-}
-
-/*******************************************************************************
-* eth_port_uc_addr_set - This function Set the port Unicast address.
-*
-* DESCRIPTION:
-*		This function Set the port Ethernet MAC address.
-*
-* INPUT:
-*	ETH_PORT eth_port_num     Port number.
-*	char *        p_addr		Address to be set
-*	ETH_QUEUE	  queue		Rx queue number for this MAC address.
-*
-* OUTPUT:
-*	Set MAC address low and high registers. also calls eth_port_uc_addr()
-*       To set the unicast table with the proper information.
-*
-* RETURN:
-*	N/A.
-*
-*******************************************************************************/
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
-				  unsigned char *p_addr, ETH_QUEUE queue)
-{
-	unsigned int mac_h;
-	unsigned int mac_l;
-
-	mac_l = (p_addr[4] << 8) | (p_addr[5]);
-	mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
-		(p_addr[2] << 8) | (p_addr[3] << 0);
-
-	MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
-	MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
-
-	/* Accept frames of this address */
-	eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
-
-	return;
-}
-
-/*******************************************************************************
-* eth_port_uc_addr - This function Set the port unicast address table
-*
-* DESCRIPTION:
-*	This function locates the proper entry in the Unicast table for the
-*	specified MAC nibble and sets its properties according to function
-*	parameters.
-*
-* INPUT:
-*	ETH_PORT	eth_port_num      Port number.
-*	unsigned char uc_nibble		Unicast MAC Address last nibble.
-*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
-*	int			option      0 = Add, 1 = remove address.
-*
-* OUTPUT:
-*	This function add/removes MAC addresses from the port unicast address
-*	table.
-*
-* RETURN:
-*	true is output succeeded.
-*	false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_uc_addr (ETH_PORT eth_port_num,
-			      unsigned char uc_nibble,
-			      ETH_QUEUE queue, int option)
-{
-	unsigned int unicast_reg;
-	unsigned int tbl_offset;
-	unsigned int reg_offset;
-
-	/* Locate the Unicast table entry */
-	uc_nibble = (0xf & uc_nibble);
-	tbl_offset = (uc_nibble / 4) * 4;	/* Register offset from unicast table base */
-	reg_offset = uc_nibble % 4;	/* Entry offset within the above register */
-
-	switch (option) {
-	case REJECT_MAC_ADDR:
-		/* Clear accepts frame bit at specified unicast DA table entry */
-		unicast_reg =
-			MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
-				      (eth_port_num)
-				      + tbl_offset));
-
-		unicast_reg &= (0x0E << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
-			       (eth_port_num)
-			       + tbl_offset), unicast_reg);
-		break;
-
-	case ACCEPT_MAC_ADDR:
-		/* Set accepts frame bit at unicast DA filter table entry */
-		unicast_reg =
-			MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
-				      (eth_port_num)
-				      + tbl_offset));
-
-		unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
-			       (eth_port_num)
-			       + tbl_offset), unicast_reg);
-
-		break;
-
-	default:
-		return false;
-	}
-	return true;
-}
-
-#if 0				/* FIXME */
-/*******************************************************************************
-* eth_port_mc_addr - Multicast address settings.
-*
-* DESCRIPTION:
-*	This API controls the MV device MAC multicast support.
-*	The MV device supports multicast using two tables:
-*	1) Special Multicast Table for MAC addresses of the form
-*	   0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
-*	   The MAC DA[7:0] bits are used as a pointer to the Special Multicast
-*	   Table entries in the DA-Filter table.
-*	   In this case, the function calls eth_port_smc_addr() routine to set the
-*	   Special Multicast Table.
-*	2) Other Multicast Table for multicast of another type. A CRC-8bit
-*	   is used as an index to the Other Multicast Table entries in the
-*	   DA-Filter table.
-*	   In this case, the function calculates the CRC-8bit value and calls
-*	   eth_port_omc_addr() routine to set the Other Multicast Table.
-* INPUT:
-*	ETH_PORT	eth_port_num      Port number.
-*	unsigned char	*p_addr		Unicast MAC Address.
-*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
-*	int			option      0 = Add, 1 = remove address.
-*
-* OUTPUT:
-*	See description.
-*
-* RETURN:
-*	true is output succeeded.
-*	false if add_address_table_entry( ) failed.
-*
-*******************************************************************************/
-static void eth_port_mc_addr (ETH_PORT eth_port_num,
-			      unsigned char *p_addr,
-			      ETH_QUEUE queue, int option)
-{
-	unsigned int mac_h;
-	unsigned int mac_l;
-	unsigned char crc_result = 0;
-	int mac_array[48];
-	int crc[8];
-	int i;
-
-
-	if ((p_addr[0] == 0x01) &&
-	    (p_addr[1] == 0x00) &&
-	    (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
-
-		eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
-	else {
-		/* Calculate CRC-8 out of the given address */
-		mac_h = (p_addr[0] << 8) | (p_addr[1]);
-		mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
-			(p_addr[4] << 8) | (p_addr[5] << 0);
-
-		for (i = 0; i < 32; i++)
-			mac_array[i] = (mac_l >> i) & 0x1;
-		for (i = 32; i < 48; i++)
-			mac_array[i] = (mac_h >> (i - 32)) & 0x1;
-
-
-		crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
-			mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
-			mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
-			mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
-			mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
-			mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
-			mac_array[6] ^ mac_array[0];
-
-		crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
-			mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
-			mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
-			mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
-			mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
-			mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
-			mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
-			mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
-			mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
-			mac_array[0];
-
-		crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
-			mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
-			mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
-			mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
-			mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
-			mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
-			mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
-			mac_array[2] ^ mac_array[1] ^ mac_array[0];
-
-		crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
-			mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
-			mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
-			mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
-			mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
-			mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
-			mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
-			mac_array[2] ^ mac_array[1];
-
-		crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
-			mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
-			mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
-			mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
-			mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
-			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
-			mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
-			mac_array[2];
-
-		crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
-			mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
-			mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
-			mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
-			mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
-			mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
-			mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
-			mac_array[3];
-
-		crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
-			mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
-			mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
-			mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
-			mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
-			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
-			mac_array[6] ^ mac_array[5] ^ mac_array[4];
-
-		crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
-			mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
-			mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
-			mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
-			mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
-			mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
-			mac_array[6] ^ mac_array[5];
-
-		for (i = 0; i < 8; i++)
-			crc_result = crc_result | (crc[i] << i);
-
-		eth_port_omc_addr (eth_port_num, crc_result, queue, option);
-	}
-	return;
-}
-
-/*******************************************************************************
-* eth_port_smc_addr - Special Multicast address settings.
-*
-* DESCRIPTION:
-*	This routine controls the MV device special MAC multicast support.
-*	The Special Multicast Table for MAC addresses supports MAC of the form
-*	0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
-*	The MAC DA[7:0] bits are used as a pointer to the Special Multicast
-*	Table entries in the DA-Filter table.
-*	This function set the Special Multicast Table appropriate entry
-*	according to the argument given.
-*
-* INPUT:
-*	ETH_PORT	eth_port_num      Port number.
-*	unsigned char	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
-*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
-*	int			option      0 = Add, 1 = remove address.
-*
-* OUTPUT:
-*	See description.
-*
-* RETURN:
-*	true is output succeeded.
-*	false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_smc_addr (ETH_PORT eth_port_num,
-			       unsigned char mc_byte,
-			       ETH_QUEUE queue, int option)
-{
-	unsigned int smc_table_reg;
-	unsigned int tbl_offset;
-	unsigned int reg_offset;
-
-	/* Locate the SMC table entry */
-	tbl_offset = (mc_byte / 4) * 4;	/* Register offset from SMC table base */
-	reg_offset = mc_byte % 4;	/* Entry offset within the above register */
-	queue &= 0x7;
-
-	switch (option) {
-	case REJECT_MAC_ADDR:
-		/* Clear accepts frame bit at specified Special DA table entry */
-		smc_table_reg =
-			MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
-		smc_table_reg &= (0x0E << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
-		break;
-
-	case ACCEPT_MAC_ADDR:
-		/* Set accepts frame bit at specified Special DA table entry */
-		smc_table_reg =
-			MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
-		smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
-		break;
-
-	default:
-		return false;
-	}
-	return true;
-}
-
-/*******************************************************************************
-* eth_port_omc_addr - Multicast address settings.
-*
-* DESCRIPTION:
-*	This routine controls the MV device Other MAC multicast support.
-*	The Other Multicast Table is used for multicast of another type.
-*	A CRC-8bit is used as an index to the Other Multicast Table entries
-*	in the DA-Filter table.
-*	The function gets the CRC-8bit value from the calling routine and
-*      set the Other Multicast Table appropriate entry according to the
-*	CRC-8 argument given.
-*
-* INPUT:
-*	ETH_PORT	eth_port_num      Port number.
-*	unsigned char	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
-*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
-*	int			option      0 = Add, 1 = remove address.
-*
-* OUTPUT:
-*	See description.
-*
-* RETURN:
-*	true is output succeeded.
-*	false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_omc_addr (ETH_PORT eth_port_num,
-			       unsigned char crc8,
-			       ETH_QUEUE queue, int option)
-{
-	unsigned int omc_table_reg;
-	unsigned int tbl_offset;
-	unsigned int reg_offset;
-
-	/* Locate the OMC table entry */
-	tbl_offset = (crc8 / 4) * 4;	/* Register offset from OMC table base */
-	reg_offset = crc8 % 4;	/* Entry offset within the above register */
-	queue &= 0x7;
-
-	switch (option) {
-	case REJECT_MAC_ADDR:
-		/* Clear accepts frame bit at specified Other DA table entry */
-		omc_table_reg =
-			MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
-		omc_table_reg &= (0x0E << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
-		break;
-
-	case ACCEPT_MAC_ADDR:
-		/* Set accepts frame bit at specified Other DA table entry */
-		omc_table_reg =
-			MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
-		omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
-		break;
-
-	default:
-		return false;
-	}
-	return true;
-}
-#endif
-
-/*******************************************************************************
-* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
-*
-* DESCRIPTION:
-*       Go through all the DA filter tables (Unicast, Special Multicast & Other
-*       Multicast) and set each entry to 0.
-*
-* INPUT:
-*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-*       Multicast and Unicast packets are rejected.
-*
-* RETURN:
-*       None.
-*
-*******************************************************************************/
-static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
-{
-	int table_index;
-
-	/* Clear DA filter unicast table (Ex_dFUT) */
-	for (table_index = 0; table_index <= 0xC; table_index += 4)
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
-			       (eth_port_num) + table_index), 0);
-
-	for (table_index = 0; table_index <= 0xFC; table_index += 4) {
-		/* Clear DA filter special multicast table (Ex_dFSMT) */
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
-		/* Clear DA filter other multicast table (Ex_dFOMT) */
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
-	}
-}
-
-/*******************************************************************************
-* eth_clear_mib_counters - Clear all MIB counters
-*
-* DESCRIPTION:
-*       This function clears all MIB counters of a specific ethernet port.
-*       A read from the MIB counter will reset the counter.
-*
-* INPUT:
-*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-*       After reading all MIB counters, the counters resets.
-*
-* RETURN:
-*       MIB counter value.
-*
-*******************************************************************************/
-static void eth_clear_mib_counters (ETH_PORT eth_port_num)
-{
-	int i;
-
-	/* Perform dummy reads from MIB counters */
-	for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
-	     i += 4)
-		MV_REG_READ((MV64460_ETH_MIB_COUNTERS_BASE(eth_port_num) + i));
-
-	return;
-}
-
-/*******************************************************************************
-* eth_read_mib_counter - Read a MIB counter
-*
-* DESCRIPTION:
-*       This function reads a MIB counter of a specific ethernet port.
-*       NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
-*       following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
-*       register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
-*       ETH_MIB_GOOD_OCTETS_SENT_HIGH
-*
-* INPUT:
-*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
-*       unsigned int mib_offset   MIB counter offset (use ETH_MIB_... macros).
-*
-* OUTPUT:
-*       After reading the MIB counter, the counter resets.
-*
-* RETURN:
-*       MIB counter value.
-*
-*******************************************************************************/
-unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
-				   unsigned int mib_offset)
-{
-	return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num)
-			     + mib_offset));
-}
-
-/*******************************************************************************
-* ethernet_phy_set - Set the ethernet port PHY address.
-*
-* DESCRIPTION:
-*       This routine set the ethernet port PHY address according to given
-*       parameter.
-*
-* INPUT:
-*		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-*       Set PHY Address Register with given PHY address parameter.
-*
-* RETURN:
-*       None.
-*
-*******************************************************************************/
-static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
-{
-	unsigned int reg_data;
-
-	reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
-
-	reg_data &= ~(0x1F << (5 * eth_port_num));
-	reg_data |= (phy_addr << (5 * eth_port_num));
-
-	MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data);
-
-	return;
-}
-
-/*******************************************************************************
- * ethernet_phy_get - Get the ethernet port PHY address.
- *
- * DESCRIPTION:
- *       This routine returns the given ethernet port PHY address.
- *
- * INPUT:
- *		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- *       None.
- *
- * RETURN:
- *       PHY address.
- *
- *******************************************************************************/
-static int ethernet_phy_get (ETH_PORT eth_port_num)
-{
-	unsigned int reg_data;
-
-	reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
-
-	return ((reg_data >> (5 * eth_port_num)) & 0x1f);
-}
-
-/*******************************************************************************
- * ethernet_phy_reset - Reset Ethernet port PHY.
- *
- * DESCRIPTION:
- *       This routine utilize the SMI interface to reset the ethernet port PHY.
- *       The routine waits until the link is up again or link up is timeout.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- *       The ethernet port PHY renew its link.
- *
- * RETURN:
- *       None.
- *
-*******************************************************************************/
-static bool ethernet_phy_reset (ETH_PORT eth_port_num)
-{
-	unsigned int time_out = 50;
-	unsigned int phy_reg_data;
-
-	/* Reset the PHY */
-	eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
-	phy_reg_data |= 0x8000;	/* Set bit 15 to reset the PHY */
-	eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
-
-	/* Poll on the PHY LINK */
-	do {
-		eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
-
-		if (time_out-- == 0)
-			return false;
-	}
-	while (!(phy_reg_data & 0x20));
-
-	return true;
-}
-
-/*******************************************************************************
- * eth_port_reset - Reset Ethernet port
- *
- * DESCRIPTION:
- *	This routine resets the chip by aborting any SDMA engine activity and
- *      clearing the MIB counters. The Receiver and the Transmit unit are in
- *      idle state after this command is performed and the port is disabled.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- *       Channel activity is halted.
- *
- * RETURN:
- *       None.
- *
- *******************************************************************************/
-static void eth_port_reset (ETH_PORT eth_port_num)
-{
-	unsigned int reg_data;
-
-	/* Stop Tx port activity. Check port Tx activity. */
-	reg_data =
-		MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
-			     (eth_port_num));
-
-	if (reg_data & 0xFF) {
-		/* Issue stop command for active channels only */
-		MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
-			      (eth_port_num), (reg_data << 8));
-
-		/* Wait for all Tx activity to terminate. */
-		do {
-			/* Check port cause register that all Tx queues are stopped */
-			reg_data =
-				MV_REG_READ
-				(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
-				 (eth_port_num));
-		}
-		while (reg_data & 0xFF);
-	}
-
-	/* Stop Rx port activity. Check port Rx activity. */
-	reg_data =
-		MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
-			     (eth_port_num));
-
-	if (reg_data & 0xFF) {
-		/* Issue stop command for active channels only */
-		MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
-			      (eth_port_num), (reg_data << 8));
-
-		/* Wait for all Rx activity to terminate. */
-		do {
-			/* Check port cause register that all Rx queues are stopped */
-			reg_data =
-				MV_REG_READ
-				(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
-				 (eth_port_num));
-		}
-		while (reg_data & 0xFF);
-	}
-
-
-	/* Clear all MIB counters */
-	eth_clear_mib_counters (eth_port_num);
-
-	/* Reset the Enable bit in the Configuration Register */
-	reg_data =
-		MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG
-			     (eth_port_num));
-	reg_data &= ~ETH_SERIAL_PORT_ENABLE;
-	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
-		      reg_data);
-
-	return;
-}
-
-#if 0				/* Not needed here */
-/*******************************************************************************
- * ethernet_set_config_reg - Set specified bits in configuration register.
- *
- * DESCRIPTION:
- *       This function sets specified bits in the given ethernet
- *       configuration register.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *      unsigned int    value   32 bit value.
- *
- * OUTPUT:
- *      The set bits in the value parameter are set in the configuration
- *      register.
- *
- * RETURN:
- *      None.
- *
- *******************************************************************************/
-static void ethernet_set_config_reg (ETH_PORT eth_port_num,
-				     unsigned int value)
-{
-	unsigned int eth_config_reg;
-
-	eth_config_reg =
-		MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num));
-	eth_config_reg |= value;
-	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
-		      eth_config_reg);
-
-	return;
-}
-#endif
-
-#if 0				/* FIXME */
-/*******************************************************************************
- * ethernet_reset_config_reg - Reset specified bits in configuration register.
- *
- * DESCRIPTION:
- *       This function resets specified bits in the given Ethernet
- *       configuration register.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *      unsigned int    value   32 bit value.
- *
- * OUTPUT:
- *      The set bits in the value parameter are reset in the configuration
- *      register.
- *
- * RETURN:
- *      None.
- *
- *******************************************************************************/
-static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
-				       unsigned int value)
-{
-	unsigned int eth_config_reg;
-
-	eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
-				      (eth_port_num));
-	eth_config_reg &= ~value;
-	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
-		      eth_config_reg);
-
-	return;
-}
-#endif
-
-#if 0				/* Not needed here */
-/*******************************************************************************
- * ethernet_get_config_reg - Get the port configuration register
- *
- * DESCRIPTION:
- *       This function returns the configuration register value of the given
- *       ethernet port.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- *       None.
- *
- * RETURN:
- *       Port configuration register value.
- *
- *******************************************************************************/
-static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
-{
-	unsigned int eth_config_reg;
-
-	eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
-				      (eth_port_num));
-	return eth_config_reg;
-}
-
-#endif
-
-/*******************************************************************************
- * eth_port_read_smi_reg - Read PHY registers
- *
- * DESCRIPTION:
- *       This routine utilize the SMI interface to interact with the PHY in
- *       order to perform PHY register read.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *       unsigned int   phy_reg   PHY register address offset.
- *       unsigned int   *value   Register value buffer.
- *
- * OUTPUT:
- *       Write the value of a specified PHY register into given buffer.
- *
- * RETURN:
- *       false if the PHY is busy or read data is not in valid state.
- *       true otherwise.
- *
- *******************************************************************************/
-static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
-				   unsigned int phy_reg, unsigned int *value)
-{
-	unsigned int reg_value;
-	unsigned int time_out = PHY_BUSY_TIMEOUT;
-	int phy_addr;
-
-	phy_addr = ethernet_phy_get (eth_port_num);
-/*    printf("     Phy-Port %d has addess %d  \n",eth_port_num, phy_addr );*/
-
-	/* first check that it is not busy */
-	do {
-		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
-		if (time_out-- == 0) {
-			return false;
-		}
-	}
-	while (reg_value & ETH_SMI_BUSY);
-
-	/* not busy */
-
-	MV_REG_WRITE (MV64460_ETH_SMI_REG,
-		      (phy_addr << 16) | (phy_reg << 21) |
-		      ETH_SMI_OPCODE_READ);
-
-	time_out = PHY_BUSY_TIMEOUT;	/* initialize the time out var again */
-
-	do {
-		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
-		if (time_out-- == 0) {
-			return false;
-		}
-	}
-	while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID);	/* Bit set equ operation done */
-
-	/* Wait for the data to update in the SMI register */
-#define PHY_UPDATE_TIMEOUT	10000
-	for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
-
-	reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
-
-	*value = reg_value & 0xffff;
-
-	return true;
-}
-
-/*******************************************************************************
- * eth_port_write_smi_reg - Write to PHY registers
- *
- * DESCRIPTION:
- *       This routine utilize the SMI interface to interact with the PHY in
- *       order to perform writes to PHY registers.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *      unsigned int   phy_reg   PHY register address offset.
- *      unsigned int    value   Register value.
- *
- * OUTPUT:
- *      Write the given value to the specified PHY register.
- *
- * RETURN:
- *      false if the PHY is busy.
- *      true otherwise.
- *
- *******************************************************************************/
-static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
-				    unsigned int phy_reg, unsigned int value)
-{
-	unsigned int reg_value;
-	unsigned int time_out = PHY_BUSY_TIMEOUT;
-	int phy_addr;
-
-	phy_addr = ethernet_phy_get (eth_port_num);
-
-	/* first check that it is not busy */
-	do {
-		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
-		if (time_out-- == 0) {
-			return false;
-		}
-	}
-	while (reg_value & ETH_SMI_BUSY);
-
-	/* not busy */
-	MV_REG_WRITE (MV64460_ETH_SMI_REG,
-		      (phy_addr << 16) | (phy_reg << 21) |
-		      ETH_SMI_OPCODE_WRITE | (value & 0xffff));
-	return true;
-}
-
-/*******************************************************************************
- * eth_set_access_control - Config address decode parameters for Ethernet unit
- *
- * DESCRIPTION:
- *       This function configures the address decode parameters for the Gigabit
- *       Ethernet Controller according the given parameters struct.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *       ETH_WIN_PARAM  *param   Address decode parameter struct.
- *
- * OUTPUT:
- *       An access window is opened using the given access parameters.
- *
- * RETURN:
- *       None.
- *
- *******************************************************************************/
-static void eth_set_access_control (ETH_PORT eth_port_num,
-				    ETH_WIN_PARAM * param)
-{
-	unsigned int access_prot_reg;
-
-	/* Set access control register */
-	access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG
-				       (eth_port_num));
-	access_prot_reg &= (~(3 << (param->win * 2)));	/* clear window permission */
-	access_prot_reg |= (param->access_ctrl << (param->win * 2));
-	MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num),
-		      access_prot_reg);
-
-	/* Set window Size reg (SR) */
-	MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 +
-		       (ETH_SIZE_REG_GAP * param->win)),
-		      (((param->size / 0x10000) - 1) << 16));
-
-	/* Set window Base address reg (BA) */
-	MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
-		      (param->target | param->attributes | param->base_addr));
-	/* High address remap reg (HARR) */
-	if (param->win < 4)
-		MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 +
-			       (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
-			      param->high_addr);
-
-	/* Base address enable reg (BARER) */
-	if (param->enable == 1)
-		MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
-				   (1 << param->win));
-	else
-		MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
-				 (1 << param->win));
-}
-
-/*******************************************************************************
- * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
- *
- * DESCRIPTION:
- *       This function prepares a Rx chained list of descriptors and packet
- *       buffers in a form of a ring. The routine must be called after port
- *       initialization routine and before port start routine.
- *       The Ethernet SDMA engine uses CPU bus addresses to access the various
- *       devices in the system (i.e. DRAM). This function uses the ethernet
- *       struct 'virtual to physical' routine (set by the user) to set the ring
- *       with physical addresses.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	rx_queue         Number of Rx queue.
- *      int			rx_desc_num       Number of Rx descriptors
- *      int			rx_buff_size      Size of Rx buffer
- *      unsigned int    rx_desc_base_addr  Rx descriptors memory area base addr.
- *      unsigned int    rx_buff_base_addr  Rx buffer memory area base addr.
- *
- * OUTPUT:
- *      The routine updates the Ethernet port control struct with information
- *      regarding the Rx descriptors and buffers.
- *
- * RETURN:
- *      false if the given descriptors memory area is not aligned according to
- *      Ethernet SDMA specifications.
- *      true otherwise.
- *
- *******************************************************************************/
-static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
-				     ETH_QUEUE rx_queue,
-				     int rx_desc_num,
-				     int rx_buff_size,
-				     unsigned int rx_desc_base_addr,
-				     unsigned int rx_buff_base_addr)
-{
-	ETH_RX_DESC *p_rx_desc;
-	ETH_RX_DESC *p_rx_prev_desc;	/* pointer to link with the last descriptor */
-	unsigned int buffer_addr;
-	int ix;			/* a counter */
-
-
-	p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
-	p_rx_prev_desc = p_rx_desc;
-	buffer_addr = rx_buff_base_addr;
-
-	/* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
-	if (rx_buff_base_addr & 0xF)
-		return false;
-
-	/* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
-	if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
-		return false;
-
-	/* Rx buffers must be 64-bit aligned.       */
-	if ((rx_buff_base_addr + rx_buff_size) & 0x7)
-		return false;
-
-	/* initialize the Rx descriptors ring */
-	for (ix = 0; ix < rx_desc_num; ix++) {
-		p_rx_desc->buf_size = rx_buff_size;
-		p_rx_desc->byte_cnt = 0x0000;
-		p_rx_desc->cmd_sts =
-			ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
-		p_rx_desc->next_desc_ptr =
-			((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
-		p_rx_desc->buf_ptr = buffer_addr;
-		p_rx_desc->return_info = 0x00000000;
-		D_CACHE_FLUSH_LINE (p_rx_desc, 0);
-		buffer_addr += rx_buff_size;
-		p_rx_prev_desc = p_rx_desc;
-		p_rx_desc = (ETH_RX_DESC *)
-			((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
-	}
-
-	/* Closing Rx descriptors ring */
-	p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
-	D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
-
-	/* Save Rx desc pointer to driver struct. */
-	CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
-	USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
-
-	p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
-		(ETH_RX_DESC *) rx_desc_base_addr;
-	p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
-		rx_desc_num * RX_DESC_ALIGNED_SIZE;
-
-	p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
-
-	return true;
-}
-
-/*******************************************************************************
- * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
- *
- * DESCRIPTION:
- *       This function prepares a Tx chained list of descriptors and packet
- *       buffers in a form of a ring. The routine must be called after port
- *       initialization routine and before port start routine.
- *       The Ethernet SDMA engine uses CPU bus addresses to access the various
- *       devices in the system (i.e. DRAM). This function uses the ethernet
- *       struct 'virtual to physical' routine (set by the user) to set the ring
- *       with physical addresses.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	tx_queue         Number of Tx queue.
- *      int			tx_desc_num       Number of Tx descriptors
- *      int			tx_buff_size      Size of Tx buffer
- *      unsigned int    tx_desc_base_addr  Tx descriptors memory area base addr.
- *      unsigned int    tx_buff_base_addr  Tx buffer memory area base addr.
- *
- * OUTPUT:
- *      The routine updates the Ethernet port control struct with information
- *      regarding the Tx descriptors and buffers.
- *
- * RETURN:
- *      false if the given descriptors memory area is not aligned according to
- *      Ethernet SDMA specifications.
- *      true otherwise.
- *
- *******************************************************************************/
-static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
-				     ETH_QUEUE tx_queue,
-				     int tx_desc_num,
-				     int tx_buff_size,
-				     unsigned int tx_desc_base_addr,
-				     unsigned int tx_buff_base_addr)
-{
-
-	ETH_TX_DESC *p_tx_desc;
-	ETH_TX_DESC *p_tx_prev_desc;
-	unsigned int buffer_addr;
-	int ix;			/* a counter */
-
-
-	/* save the first desc pointer to link with the last descriptor */
-	p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
-	p_tx_prev_desc = p_tx_desc;
-	buffer_addr = tx_buff_base_addr;
-
-	/* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
-	if (tx_buff_base_addr & 0xF)
-		return false;
-
-	/* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
-	if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
-	    || (tx_buff_size < TX_BUFFER_MIN_SIZE))
-		return false;
-
-	/* Initialize the Tx descriptors ring */
-	for (ix = 0; ix < tx_desc_num; ix++) {
-		p_tx_desc->byte_cnt = 0x0000;
-		p_tx_desc->l4i_chk = 0x0000;
-		p_tx_desc->cmd_sts = 0x00000000;
-		p_tx_desc->next_desc_ptr =
-			((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
-
-		p_tx_desc->buf_ptr = buffer_addr;
-		p_tx_desc->return_info = 0x00000000;
-		D_CACHE_FLUSH_LINE (p_tx_desc, 0);
-		buffer_addr += tx_buff_size;
-		p_tx_prev_desc = p_tx_desc;
-		p_tx_desc = (ETH_TX_DESC *)
-			((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
-
-	}
-	/* Closing Tx descriptors ring */
-	p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
-	D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
-	/* Set Tx desc pointer in driver struct. */
-	CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
-	USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
-
-	/* Init Tx ring base and size parameters */
-	p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
-		(ETH_TX_DESC *) tx_desc_base_addr;
-	p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
-		(tx_desc_num * TX_DESC_ALIGNED_SIZE);
-
-	/* Add the queue to the list of Tx queues of this port */
-	p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
-
-	return true;
-}
-
-/*******************************************************************************
- * eth_port_send - Send an Ethernet packet
- *
- * DESCRIPTION:
- *	This routine send a given packet described by p_pktinfo parameter. It
- *      supports transmitting of a packet spaned over multiple buffers. The
- *      routine updates 'curr' and 'first' indexes according to the packet
- *      segment passed to the routine. In case the packet segment is first,
- *      the 'first' index is update. In any case, the 'curr' index is updated.
- *      If the routine get into Tx resource error it assigns 'curr' index as
- *      'first'. This way the function can abort Tx process of multiple
- *      descriptors per packet.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	tx_queue         Number of Tx queue.
- *	PKT_INFO        *p_pkt_info       User packet buffer.
- *
- * OUTPUT:
- *	Tx ring 'curr' and 'first' indexes are updated.
- *
- * RETURN:
- *      ETH_QUEUE_FULL in case of Tx resource error.
- *	ETH_ERROR in case the routine can not access Tx desc ring.
- *	ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
- *      ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
-					  ETH_QUEUE tx_queue,
-					  PKT_INFO * p_pkt_info)
-{
-	volatile ETH_TX_DESC *p_tx_desc_first;
-	volatile ETH_TX_DESC *p_tx_desc_curr;
-	volatile ETH_TX_DESC *p_tx_next_desc_curr;
-	volatile ETH_TX_DESC *p_tx_desc_used;
-	unsigned int command_status;
-
-	/* Do not process Tx ring in case of Tx ring resource error */
-	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
-		return ETH_QUEUE_FULL;
-
-	/* Get the Tx Desc ring indexes */
-	CURR_TFD_GET (p_tx_desc_curr, tx_queue);
-	USED_TFD_GET (p_tx_desc_used, tx_queue);
-
-	if (p_tx_desc_curr == NULL)
-		return ETH_ERROR;
-
-	/* The following parameters are used to save readings from memory */
-	p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
-	command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
-
-	if (command_status & (ETH_TX_FIRST_DESC)) {
-		/* Update first desc */
-		FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
-		p_tx_desc_first = p_tx_desc_curr;
-	} else {
-		FIRST_TFD_GET (p_tx_desc_first, tx_queue);
-		command_status |= ETH_BUFFER_OWNED_BY_DMA;
-	}
-
-	/* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
-	/* boundary. We use the memory allocated for Tx descriptor. This memory  */
-	/* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
-	if (p_pkt_info->byte_cnt <= 8) {
-		printf ("You have failed in the < 8 bytes errata - fixme\n");	/* RABEEH - TBD */
-		return ETH_ERROR;
-
-		p_tx_desc_curr->buf_ptr =
-			(unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
-		eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
-			    p_pkt_info->byte_cnt);
-	} else
-		p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
-
-	p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
-	p_tx_desc_curr->return_info = p_pkt_info->return_info;
-
-	if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
-		/* Set last desc with DMA ownership and interrupt enable. */
-		p_tx_desc_curr->cmd_sts = command_status |
-			ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
-
-		if (p_tx_desc_curr != p_tx_desc_first)
-			p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
-
-		/* Flush CPU pipe */
-
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
-		CPU_PIPE_FLUSH;
-
-		/* Apply send command */
-		ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
-
-		/* Finish Tx packet. Update first desc in case of Tx resource error */
-		p_tx_desc_first = p_tx_next_desc_curr;
-		FIRST_TFD_SET (p_tx_desc_first, tx_queue);
-
-	} else {
-		p_tx_desc_curr->cmd_sts = command_status;
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
-	}
-
-	/* Check for ring index overlap in the Tx desc ring */
-	if (p_tx_next_desc_curr == p_tx_desc_used) {
-		/* Update the current descriptor */
-		CURR_TFD_SET (p_tx_desc_first, tx_queue);
-
-		p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
-		return ETH_QUEUE_LAST_RESOURCE;
-	} else {
-		/* Update the current descriptor */
-		CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
-		return ETH_OK;
-	}
-}
-
-/*******************************************************************************
- * eth_tx_return_desc - Free all used Tx descriptors
- *
- * DESCRIPTION:
- *	This routine returns the transmitted packet information to the caller.
- *      It uses the 'first' index to support Tx desc return in case a transmit
- *      of a packet spanned over multiple buffer still in process.
- *      In case the Tx queue was in "resource error" condition, where there are
- *      no available Tx resources, the function resets the resource error flag.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	tx_queue         Number of Tx queue.
- *	PKT_INFO        *p_pkt_info       User packet buffer.
- *
- * OUTPUT:
- *	Tx ring 'first' and 'used' indexes are updated.
- *
- * RETURN:
- *	ETH_ERROR in case the routine can not access Tx desc ring.
- *      ETH_RETRY in case there is transmission in process.
- *	ETH_END_OF_JOB if the routine has nothing to release.
- *      ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
-					       p_eth_port_ctrl,
-					       ETH_QUEUE tx_queue,
-					       PKT_INFO * p_pkt_info)
-{
-	volatile ETH_TX_DESC *p_tx_desc_used = NULL;
-	volatile ETH_TX_DESC *p_tx_desc_first = NULL;
-	unsigned int command_status;
-
-
-	/* Get the Tx Desc ring indexes */
-	USED_TFD_GET (p_tx_desc_used, tx_queue);
-	FIRST_TFD_GET (p_tx_desc_first, tx_queue);
-
-
-	/* Sanity check */
-	if (p_tx_desc_used == NULL)
-		return ETH_ERROR;
-
-	command_status = p_tx_desc_used->cmd_sts;
-
-	/* Still transmitting... */
-	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
-		return ETH_RETRY;
-	}
-
-	/* Stop release. About to overlap the current available Tx descriptor */
-	if ((p_tx_desc_used == p_tx_desc_first) &&
-	    (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
-		return ETH_END_OF_JOB;
-	}
-
-	/* Pass the packet information to the caller */
-	p_pkt_info->cmd_sts = command_status;
-	p_pkt_info->return_info = p_tx_desc_used->return_info;
-	p_tx_desc_used->return_info = 0;
-
-	/* Update the next descriptor to release. */
-	USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
-
-	/* Any Tx return cancels the Tx resource error status */
-	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
-		p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
-
-	D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
-
-	return ETH_OK;
-
-}
-
-/*******************************************************************************
- * eth_port_receive - Get received information from Rx ring.
- *
- * DESCRIPTION:
- *	This routine returns the received data to the caller. There is no
- *	data copying during routine operation. All information is returned
- *	using pointer to packet information struct passed from the caller.
- *      If the routine exhausts	Rx ring resources then the resource error flag
- *      is set.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	rx_queue         Number of Rx queue.
- *	PKT_INFO        *p_pkt_info       User packet buffer.
- *
- * OUTPUT:
- *	Rx ring current and used indexes are updated.
- *
- * RETURN:
- *	ETH_ERROR in case the routine can not access Rx desc ring.
- *	ETH_QUEUE_FULL if Rx ring resources are exhausted.
- *	ETH_END_OF_JOB if there is no received data.
- *      ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
-					     ETH_QUEUE rx_queue,
-					     PKT_INFO * p_pkt_info)
-{
-	volatile ETH_RX_DESC *p_rx_curr_desc;
-	volatile ETH_RX_DESC *p_rx_next_curr_desc;
-	volatile ETH_RX_DESC *p_rx_used_desc;
-	unsigned int command_status;
-
-	/* Do not process Rx ring in case of Rx ring resource error */
-	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
-		printf ("\nRx Queue is full ...\n");
-		return ETH_QUEUE_FULL;
-	}
-
-	/* Get the Rx Desc ring 'curr and 'used' indexes */
-	CURR_RFD_GET (p_rx_curr_desc, rx_queue);
-	USED_RFD_GET (p_rx_used_desc, rx_queue);
-
-	/* Sanity check */
-	if (p_rx_curr_desc == NULL)
-		return ETH_ERROR;
-
-	/* The following parameters are used to save readings from memory */
-	p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
-	command_status = p_rx_curr_desc->cmd_sts;
-
-	/* Nothing to receive... */
-	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
-/*	DP(printf("Rx: command_status: %08x\n", command_status)); */
-		D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
-/*	DP(printf("\nETH_END_OF_JOB ...\n"));*/
-		return ETH_END_OF_JOB;
-	}
-
-	p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
-	p_pkt_info->cmd_sts = command_status;
-	p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
-	p_pkt_info->return_info = p_rx_curr_desc->return_info;
-	p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size;	/* IP fragment indicator */
-
-	/* Clean the return info field to indicate that the packet has been */
-	/* moved to the upper layers                                        */
-	p_rx_curr_desc->return_info = 0;
-
-	/* Update 'curr' in data structure */
-	CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
-
-	/* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
-	if (p_rx_next_curr_desc == p_rx_used_desc)
-		p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
-
-	D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
-	CPU_PIPE_FLUSH;
-	return ETH_OK;
-}
-
-/*******************************************************************************
- * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
- *
- * DESCRIPTION:
- *	This routine returns a Rx buffer back to the Rx ring. It retrieves the
- *      next 'used' descriptor and attached the returned buffer to it.
- *      In case the Rx ring was in "resource error" condition, where there are
- *      no available Rx resources, the function resets the resource error flag.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	rx_queue         Number of Rx queue.
- *      PKT_INFO        *p_pkt_info       Information on the returned buffer.
- *
- * OUTPUT:
- *	New available Rx resource in Rx descriptor ring.
- *
- * RETURN:
- *	ETH_ERROR in case the routine can not access Rx desc ring.
- *      ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
-					       p_eth_port_ctrl,
-					       ETH_QUEUE rx_queue,
-					       PKT_INFO * p_pkt_info)
-{
-	volatile ETH_RX_DESC *p_used_rx_desc;	/* Where to return Rx resource */
-
-	/* Get 'used' Rx descriptor */
-	USED_RFD_GET (p_used_rx_desc, rx_queue);
-
-	/* Sanity check */
-	if (p_used_rx_desc == NULL)
-		return ETH_ERROR;
-
-	p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
-	p_used_rx_desc->return_info = p_pkt_info->return_info;
-	p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
-	p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE;	/* Reset Buffer size */
-
-	/* Flush the write pipe */
-	CPU_PIPE_FLUSH;
-
-	/* Return the descriptor to DMA ownership */
-	p_used_rx_desc->cmd_sts =
-		ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
-
-	/* Flush descriptor and CPU pipe */
-	D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
-	CPU_PIPE_FLUSH;
-
-	/* Move the used descriptor pointer to the next descriptor */
-	USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
-
-	/* Any Rx return cancels the Rx resource error status */
-	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
-		p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
-
-	return ETH_OK;
-}
-
-/*******************************************************************************
- * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
- *
- * DESCRIPTION:
- *	This routine sets the RX coalescing interrupt mechanism parameter.
- *	This parameter is a timeout counter, that counts in 64 t_clk
- *	chunks ; that when timeout event occurs a maskable interrupt
- *	occurs.
- *	The parameter is calculated using the tClk of the MV-643xx chip
- *	, and the required delay of the interrupt in usec.
- *
- * INPUT:
- *	ETH_PORT eth_port_num      Ethernet port number
- *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
- *	unsigned int delay       Delay in usec
- *
- * OUTPUT:
- *	Interrupt coalescing mechanism value is set in MV-643xx chip.
- *
- * RETURN:
- *	The interrupt coalescing value set in the gigE port.
- *
- *******************************************************************************/
-#if 0				/* FIXME */
-static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
-					  unsigned int t_clk,
-					  unsigned int delay)
-{
-	unsigned int coal;
-
-	coal = ((t_clk / 1000000) * delay) / 64;
-	/* Set RX Coalescing mechanism */
-	MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
-		      ((coal & 0x3fff) << 8) |
-		      (MV_REG_READ
-		       (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num))
-		       & 0xffc000ff));
-	return coal;
-}
-
-#endif
-/*******************************************************************************
- * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
- *
- * DESCRIPTION:
- *	This routine sets the TX coalescing interrupt mechanism parameter.
- *	This parameter is a timeout counter, that counts in 64 t_clk
- *	chunks ; that when timeout event occurs a maskable interrupt
- *	occurs.
- *	The parameter is calculated using the t_cLK frequency of the
- *	MV-643xx chip and the required delay in the interrupt in uSec
- *
- * INPUT:
- *	ETH_PORT eth_port_num      Ethernet port number
- *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
- *	unsigned int delay       Delay in uSeconds
- *
- * OUTPUT:
- *	Interrupt coalescing mechanism value is set in MV-643xx chip.
- *
- * RETURN:
- *	The interrupt coalescing value set in the gigE port.
- *
- *******************************************************************************/
-#if 0				/* FIXME */
-static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
-					  unsigned int t_clk,
-					  unsigned int delay)
-{
-	unsigned int coal;
-
-	coal = ((t_clk / 1000000) * delay) / 64;
-	/* Set TX Coalescing mechanism */
-	MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
-		      coal << 4);
-	return coal;
-}
-#endif
-
-/*******************************************************************************
- * eth_b_copy - Copy bytes from source to destination
- *
- * DESCRIPTION:
- *       This function supports the eight bytes limitation on Tx buffer size.
- *       The routine will zero eight bytes starting from the destination address
- *       followed by copying bytes from the source address to the destination.
- *
- * INPUT:
- *       unsigned int src_addr    32 bit source address.
- *       unsigned int dst_addr    32 bit destination address.
- *       int        byte_count    Number of bytes to copy.
- *
- * OUTPUT:
- *       See description.
- *
- * RETURN:
- *       None.
- *
- *******************************************************************************/
-static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
-			int byte_count)
-{
-	/* Zero the dst_addr area */
-	*(unsigned int *) dst_addr = 0x0;
-
-	while (byte_count != 0) {
-		*(char *) dst_addr = *(char *) src_addr;
-		dst_addr++;
-		src_addr++;
-		byte_count--;
-	}
-}
diff --git a/board/Marvell/db64460/mv_eth.h b/board/Marvell/db64460/mv_eth.h
deleted file mode 100644
index 4c95e3ec4c2..00000000000
--- a/board/Marvell/db64460/mv_eth.h
+++ /dev/null
@@ -1,815 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * mv_eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __DB64460_ETH_H__
-#define __DB64460_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-#include <net.h>
-#include "mv_regs.h"
-#include <asm/errno.h>
-
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The first part is the high level driver of the gigE ethernet ports.	 *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
-#ifndef MAX_SKB_FRAGS
-#define MAX_SKB_FRAGS 0
-#endif
-
-/* Port attributes */
-/*#define MAX_RX_QUEUE_NUM	8*/
-/*#define MAX_TX_QUEUE_NUM	8*/
-#define MAX_RX_QUEUE_NUM	1
-#define MAX_TX_QUEUE_NUM	1
-
-
-/* Use one TX queue and one RX queue */
-#define MV64460_TX_QUEUE_NUM 1
-#define MV64460_RX_QUEUE_NUM 1
-
-/*
- * Number of RX / TX descriptors on RX / TX rings.
- * Note that allocating RX descriptors is done by allocating the RX
- * ring AND a preallocated RX buffers (skb's) for each descriptor.
- * The TX descriptors only allocates the TX descriptors ring,
- * with no pre allocated TX buffers (skb's are allocated by higher layers.
- */
-
-/* Default TX ring size is 10 descriptors */
-#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
-#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
-#else
-#define MV64460_TX_QUEUE_SIZE 4
-#endif
-
-/* Default RX ring size is 4 descriptors */
-#ifdef	CONFIG_MV64460_ETH_RXQUEUE_SIZE
-#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
-#else
-#define MV64460_RX_QUEUE_SIZE 4
-#endif
-
-#ifdef CONFIG_RX_BUFFER_SIZE
-#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
-#else
-#define MV64460_RX_BUFFER_SIZE 1600
-#endif
-
-#ifdef CONFIG_TX_BUFFER_SIZE
-#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
-#else
-#define MV64460_TX_BUFFER_SIZE 1600
-#endif
-
-/*
- *	Network device statistics. Akin to the 2.0 ether stats but
- *	with byte counters.
- */
-
-struct net_device_stats
-{
-	unsigned long	rx_packets;		/* total packets received	*/
-	unsigned long	tx_packets;		/* total packets transmitted	*/
-	unsigned long	rx_bytes;		/* total bytes received		*/
-	unsigned long	tx_bytes;		/* total bytes transmitted	*/
-	unsigned long	rx_errors;		/* bad packets received		*/
-	unsigned long	tx_errors;		/* packet transmit problems	*/
-	unsigned long	rx_dropped;		/* no space in linux buffers	*/
-	unsigned long	tx_dropped;		/* no space available in linux	*/
-	unsigned long	multicast;		/* multicast packets received	*/
-	unsigned long	collisions;
-
-	/* detailed rx_errors: */
-	unsigned long	rx_length_errors;
-	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
-	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
-	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
-	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
-	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
-
-	/* detailed tx_errors */
-	unsigned long	tx_aborted_errors;
-	unsigned long	tx_carrier_errors;
-	unsigned long	tx_fifo_errors;
-	unsigned long	tx_heartbeat_errors;
-	unsigned long	tx_window_errors;
-
-	/* for cslip etc */
-	unsigned long	rx_compressed;
-	unsigned long	tx_compressed;
-};
-
-
-/* Private data structure used for ethernet device */
-struct mv64460_eth_priv {
-    unsigned int port_num;
-    struct net_device_stats *stats;
-
-/* to buffer area aligned */
-    char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
-    char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
-
-    /* Size of Tx Ring per queue */
-    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
-
-
-    /* Size of Rx Ring per queue */
-    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
-
-    /* Magic Number for Ethernet running */
-    unsigned int eth_running;
-
-};
-
-int mv64460_eth_init (struct eth_device *dev);
-int mv64460_eth_stop (struct eth_device *dev);
-int mv64460_eth_start_xmit(struct eth_device *dev, void *packet, int length);
-int mv64460_eth_open (struct eth_device *dev);
-
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The second part is the low level driver of the gigE ethernet ports.	 *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-
-
-/********************************************************************************
- * Header File for : MV-643xx network interface header
- *
- * DESCRIPTION:
- *	 This header file contains macros typedefs and function declaration for
- *	 the Marvell Gig Bit Ethernet Controller.
- *
- * DEPENDENCIES:
- *	 None.
- *
- *******************************************************************************/
-
-
-#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
-#ifdef CONFIG_MV64460_SRAM_CACHEABLE
-/* In case SRAM is cacheable but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset)       \
-{		    \
-  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case SRAM is cache coherent or non-cacheable */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif
-#else
-#ifdef CONFIG_NOT_COHERENT_CACHE
-/* In case of descriptors on DDR but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset)       \
-{		    \
-  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case of descriptors on DDR and cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif /* CONFIG_NOT_COHERENT_CACHE */
-#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
-
-
-#define CPU_PIPE_FLUSH		   \
-{		  \
-  __asm__ __volatile__ ("eieio");	  \
-}
-
-
-/* defines  */
-
-/* Default port configuration value */
-#define PORT_CONFIG_VALUE			\
-	     ETH_UNICAST_NORMAL_MODE		|   \
-	     ETH_DEFAULT_RX_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
-	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
-	     ETH_RECEIVE_BC_IF_IP		|   \
-	     ETH_RECEIVE_BC_IF_ARP		|   \
-	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
-	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
-	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_BPDU_QUEUE_0
-
-/* Default port extend configuration value */
-#define PORT_CONFIG_EXTEND_VALUE		\
-	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
-	     ETH_PARTITION_DISABLE
-
-
-/* Default sdma control value */
-#ifdef CONFIG_NOT_COHERENT_CACHE
-#define PORT_SDMA_CONFIG_VALUE				\
-			 ETH_RX_BURST_SIZE_16_64BIT	|	\
-			 GT_ETH_IPG_INT_RX(0)			|	\
-			 ETH_TX_BURST_SIZE_16_64BIT;
-#else
-#define PORT_SDMA_CONFIG_VALUE			\
-			 ETH_RX_BURST_SIZE_4_64BIT	|	\
-			 GT_ETH_IPG_INT_RX(0)			|	\
-			 ETH_TX_BURST_SIZE_4_64BIT;
-#endif
-
-#define GT_ETH_IPG_INT_RX(value)		\
-	    ((value & 0x3fff) << 8)
-
-/* Default port serial control value */
-#define PORT_SERIAL_CONTROL_VALUE			    \
-			ETH_FORCE_LINK_PASS			|	\
-			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
-			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
-			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
-			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
-			ETH_FORCE_BP_MODE_NO_JAM		|	\
-			BIT9					|	\
-			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
-			ETH_RETRANSMIT_16_ETTEMPTS		|	\
-			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
-			ETH_DTE_ADV_0				|	\
-			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
-			ETH_AUTO_NEG_NO_CHANGE			|	\
-			ETH_MAX_RX_PACKET_1552BYTE		|	\
-			ETH_CLR_EXT_LOOPBACK			|	\
-			ETH_SET_FULL_DUPLEX_MODE		|	\
-			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
-
-#define RX_BUFFER_MAX_SIZE  0xFFFF
-#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
-
-#define RX_BUFFER_MIN_SIZE  0x8
-#define TX_BUFFER_MIN_SIZE  0x8
-
-/* Tx WRR confoguration macros */
-#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
-#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
-#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
-
-/* MAC accepet/reject macros */
-#define ACCEPT_MAC_ADDR	    0
-#define REJECT_MAC_ADDR	    1
-
-/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define RX_DESC_ALIGNED_SIZE		0x20
-#define TX_DESC_ALIGNED_SIZE		0x20
-
-/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
-#define TX_BUF_OFFSET_IN_DESC	    0x18
-/* Buffer offset from buffer pointer */
-#define RX_BUF_OFFSET				0x2
-
-/* Gap define */
-#define ETH_BAR_GAP					0x8
-#define ETH_SIZE_REG_GAP				0x8
-#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
-#define ETH_PORT_ACCESS_CTRL_GAP			0x4
-
-/* Gigabit Ethernet Unit Global Registers */
-
-/* MIB Counters register definitions */
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
-#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
-#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
-#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
-#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
-#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
-#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
-#define ETH_MIB_FRAMES_64_OCTETS	   0x20
-#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
-#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
-#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
-#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
-#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
-#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
-#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
-#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
-#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
-#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
-#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
-#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
-#define ETH_MIB_FC_SENT			   0x54
-#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
-#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
-#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
-#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
-#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
-#define ETH_MIB_JABBER_RECEIVED		   0x6c
-#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
-#define ETH_MIB_BAD_CRC_EVENT		   0x74
-#define ETH_MIB_COLLISION		   0x78
-#define ETH_MIB_LATE_COLLISION		   0x7c
-
-/* Port serial status reg (PSR) */
-#define ETH_INTERFACE_GMII_MII				0
-#define ETH_INTERFACE_PCM				BIT0
-#define ETH_LINK_IS_DOWN				0
-#define ETH_LINK_IS_UP					BIT1
-#define ETH_PORT_AT_HALF_DUPLEX				0
-#define ETH_PORT_AT_FULL_DUPLEX				BIT2
-#define ETH_RX_FLOW_CTRL_DISABLED			0
-#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
-#define ETH_GMII_SPEED_100_10				0
-#define ETH_GMII_SPEED_1000				BIT4
-#define ETH_MII_SPEED_10				0
-#define ETH_MII_SPEED_100				BIT5
-#define ETH_NO_TX					0
-#define ETH_TX_IN_PROGRESS				BIT7
-#define ETH_BYPASS_NO_ACTIVE				0
-#define ETH_BYPASS_ACTIVE				BIT8
-#define ETH_PORT_NOT_AT_PARTITION_STATE			0
-#define ETH_PORT_AT_PARTITION_STATE			BIT9
-#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
-#define ETH_PORT_TX_FIFO_EMPTY				BIT10
-
-
-/* These macros describes the Port configuration reg (Px_cR) bits */
-#define ETH_UNICAST_NORMAL_MODE				0
-#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
-#define ETH_DEFAULT_RX_QUEUE_0				0
-#define ETH_DEFAULT_RX_QUEUE_1				BIT1
-#define ETH_DEFAULT_RX_QUEUE_2				BIT2
-#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_4				BIT3
-#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
-#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
-#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
-#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
-#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
-#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
-#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
-#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
-#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
-#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
-#define ETH_RECEIVE_BC_IF_IP				0
-#define ETH_REJECT_BC_IF_IP				BIT8
-#define ETH_RECEIVE_BC_IF_ARP				0
-#define ETH_REJECT_BC_IF_ARP				BIT9
-#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
-#define ETH_CAPTURE_TCP_FRAMES_DIS			0
-#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
-#define ETH_CAPTURE_UDP_FRAMES_DIS			0
-#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
-#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
-#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
-#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
-#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
-#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
-#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
-#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
-#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
-#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
-#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
-#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
-#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
-#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
-#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
-#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
-#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
-
-
-/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
-#define ETH_CLASSIFY_EN					BIT0
-#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
-#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
-#define ETH_PARTITION_DISABLE				0
-#define ETH_PARTITION_ENABLE				BIT2
-
-
-/* Tx/Rx queue command reg (RQCR/TQCR)*/
-#define ETH_QUEUE_0_ENABLE				BIT0
-#define ETH_QUEUE_1_ENABLE				BIT1
-#define ETH_QUEUE_2_ENABLE				BIT2
-#define ETH_QUEUE_3_ENABLE				BIT3
-#define ETH_QUEUE_4_ENABLE				BIT4
-#define ETH_QUEUE_5_ENABLE				BIT5
-#define ETH_QUEUE_6_ENABLE				BIT6
-#define ETH_QUEUE_7_ENABLE				BIT7
-#define ETH_QUEUE_0_DISABLE				BIT8
-#define ETH_QUEUE_1_DISABLE				BIT9
-#define ETH_QUEUE_2_DISABLE				BIT10
-#define ETH_QUEUE_3_DISABLE				BIT11
-#define ETH_QUEUE_4_DISABLE				BIT12
-#define ETH_QUEUE_5_DISABLE				BIT13
-#define ETH_QUEUE_6_DISABLE				BIT14
-#define ETH_QUEUE_7_DISABLE				BIT15
-
-/* These macros describes the Port Sdma configuration reg (SDCR) bits */
-#define ETH_RIFB					BIT0
-#define ETH_RX_BURST_SIZE_1_64BIT			0
-#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
-#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
-#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
-#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
-#define ETH_BLM_RX_NO_SWAP				BIT4
-#define ETH_BLM_RX_BYTE_SWAP				0
-#define ETH_BLM_TX_NO_SWAP				BIT5
-#define ETH_BLM_TX_BYTE_SWAP				0
-#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
-#define ETH_DESCRIPTORS_NO_SWAP				0
-#define ETH_TX_BURST_SIZE_1_64BIT			0
-#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
-#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
-#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
-#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
-
-/* These macros describes the Port serial control reg (PSCR) bits */
-#define ETH_SERIAL_PORT_DISABLE				0
-#define ETH_SERIAL_PORT_ENABLE				BIT0
-#define ETH_FORCE_LINK_PASS				BIT1
-#define ETH_DO_NOT_FORCE_LINK_PASS			0
-#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
-#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
-#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
-#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
-#define ETH_ADV_NO_FLOW_CTRL				0
-#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
-#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
-#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
-#define ETH_FORCE_BP_MODE_NO_JAM			0
-#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
-#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
-#define ETH_FORCE_LINK_FAIL				0
-#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
-#define ETH_RETRANSMIT_16_ETTEMPTS			0
-#define ETH_RETRANSMIT_FOREVER				BIT11
-#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
-#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
-#define ETH_DTE_ADV_0					0
-#define ETH_DTE_ADV_1					BIT14
-#define ETH_DISABLE_AUTO_NEG_BYPASS			0
-#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
-#define ETH_AUTO_NEG_NO_CHANGE				0
-#define ETH_RESTART_AUTO_NEG				BIT16
-#define ETH_MAX_RX_PACKET_1518BYTE			0
-#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
-#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
-#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
-#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
-#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
-#define ETH_SET_EXT_LOOPBACK				BIT20
-#define ETH_CLR_EXT_LOOPBACK				0
-#define ETH_SET_FULL_DUPLEX_MODE			BIT21
-#define ETH_SET_HALF_DUPLEX_MODE			0
-#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
-#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
-#define ETH_SET_GMII_SPEED_TO_10_100			0
-#define ETH_SET_GMII_SPEED_TO_1000			BIT23
-#define ETH_SET_MII_SPEED_TO_10				0
-#define ETH_SET_MII_SPEED_TO_100			BIT24
-
-
-/* SMI reg */
-#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
-#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
-#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
-#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
-
-/* SDMA command status fields macros */
-
-/* Tx & Rx descriptors status */
-#define ETH_ERROR_SUMMARY		    (BIT0)
-
-/* Tx & Rx descriptors command */
-#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
-
-/* Tx descriptors status */
-#define ETH_LC_ERROR			    (0	  )
-#define ETH_UR_ERROR			    (BIT1 )
-#define ETH_RL_ERROR			    (BIT2 )
-#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
-
-/* Rx descriptors status */
-#define ETH_CRC_ERROR			    (0	  )
-#define ETH_OVERRUN_ERROR		    (BIT1 )
-#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
-#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
-#define ETH_VLAN_TAGGED			    (BIT19)
-#define ETH_BPDU_FRAME			    (BIT20)
-#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
-#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
-#define ETH_OTHER_FRAME_TYPE		    (BIT22)
-#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
-#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
-#define ETH_FRAME_HEADER_OK		    (BIT25)
-#define ETH_RX_LAST_DESC		    (BIT26)
-#define ETH_RX_FIRST_DESC		    (BIT27)
-#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
-#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
-#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
-
-/* Rx descriptors byte count */
-#define ETH_FRAME_FRAGMENTED		    (BIT2)
-
-/* Tx descriptors command */
-#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
-#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
-#define ETH_TCP_FRAME			    (0	  )
-#define ETH_UDP_FRAME			    (BIT16)
-#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
-#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
-#define ETH_ZERO_PADDING		    (BIT19)
-#define ETH_TX_LAST_DESC		    (BIT20)
-#define ETH_TX_FIRST_DESC		    (BIT21)
-#define ETH_GEN_CRC			    (BIT22)
-#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
-#define ETH_AUTO_MODE			    (BIT30)
-
-/* Address decode parameters */
-/* Ethernet Base Address Register bits */
-#define EBAR_TARGET_DRAM					0x00000000
-#define EBAR_TARGET_DEVICE					0x00000001
-#define EBAR_TARGET_CBS						0x00000002
-#define EBAR_TARGET_PCI0					0x00000003
-#define EBAR_TARGET_PCI1					0x00000004
-#define EBAR_TARGET_CUNIT					0x00000005
-#define EBAR_TARGET_AUNIT					0x00000006
-#define EBAR_TARGET_GUNIT					0x00000007
-
-/* Window attributes */
-#define EBAR_ATTR_DRAM_CS0					0x00000E00
-#define EBAR_ATTR_DRAM_CS1					0x00000D00
-#define EBAR_ATTR_DRAM_CS2					0x00000B00
-#define EBAR_ATTR_DRAM_CS3					0x00000700
-
-/* DRAM Target interface */
-#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
-
-/* Device Bus Target interface */
-#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
-#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
-#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
-#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
-#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
-
-/* PCI Target interface */
-#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
-#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
-#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
-#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
-#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
-#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
-#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
-#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
-#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
-#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
-
-/* CPU 60x bus or internal SRAM interface */
-#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
-#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
-#define EBAR_ATTR_CBS_SRAM					0x00000000
-#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
-
-/* Window access control */
-#define EWIN_ACCESS_NOT_ALLOWED 0
-#define EWIN_ACCESS_READ_ONLY	BIT0
-#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
-#define EWIN0_ACCESS_MASK		0x0003
-#define EWIN1_ACCESS_MASK		0x000C
-#define EWIN2_ACCESS_MASK		0x0030
-#define EWIN3_ACCESS_MASK		0x00C0
-
-/* typedefs */
-
-typedef enum _eth_port
-{
-    ETH_0 = 0,
-	ETH_1 = 1,
-	ETH_2 = 2
-}ETH_PORT;
-
-typedef enum _eth_func_ret_status
-{
-    ETH_OK,			/* Returned as expected.		    */
-    ETH_ERROR,			/* Fundamental error.			    */
-    ETH_RETRY,			/* Could not process request. Try later.    */
-    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
-    ETH_QUEUE_FULL,		/* Ring resource error.			    */
-    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
-}ETH_FUNC_RET_STATUS;
-
-typedef enum _eth_queue
-{
-	ETH_Q0 = 0,
-	ETH_Q1 = 1,
-	ETH_Q2 = 2,
-	ETH_Q3 = 3,
-	ETH_Q4 = 4,
-	ETH_Q5 = 5,
-	ETH_Q6 = 6,
-    ETH_Q7 = 7
-} ETH_QUEUE;
-
-typedef enum _addr_win
-{
-	ETH_WIN0,
-	ETH_WIN1,
-	ETH_WIN2,
-	ETH_WIN3,
-	ETH_WIN4,
-    ETH_WIN5
-} ETH_ADDR_WIN;
-
-typedef enum _eth_target
-{
-	ETH_TARGET_DRAM	 ,
-	ETH_TARGET_DEVICE,
-	ETH_TARGET_CBS	 ,
-	ETH_TARGET_PCI0	 ,
-	ETH_TARGET_PCI1
-}ETH_TARGET;
-
-typedef struct _eth_rx_desc
-{
-	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
-	unsigned short	buf_size	   ;	/* Buffer size			    */
-	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
-	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
-	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} ETH_RX_DESC;
-
-
-typedef struct _eth_tx_desc
-{
-    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
-    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
-    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
-    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
-    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} ETH_TX_DESC;
-
-/* Unified struct for Rx and Tx operations. The user is not required to */
-/* be familier with neither Tx nor Rx descriptors.			 */
-typedef struct _pkt_info
-{
-	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
-	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
-	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
-	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} PKT_INFO;
-
-
-typedef struct _eth_win_param
-{
-    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
-    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
-    unsigned short attributes;	/* BAR attributes. See above macros. */
-    unsigned int base_addr; /* Window base address in unsigned int form */
-    unsigned int high_addr; /* Window high address in unsigned int form */
-    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
-    bool enable; /* Enable/disable access to the window. */
-    unsigned short access_ctrl; /* Access ctrl register. see above macros */
-} ETH_WIN_PARAM;
-
-
-/* Ethernet port specific infomation */
-
-typedef struct _eth_port_ctrl
-{
-    ETH_PORT  port_num; /* User Ethernet port number */
-    int port_phy_addr;	/* User phy address of Ethrnet port */
-    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
-    unsigned int  port_config; /* User port configuration value */
-    unsigned int  port_config_extend; /* User port config extend value */
-    unsigned int  port_sdma_config; /* User port SDMA config value */
-    unsigned int  port_serial_control; /* User port serial control value */
-    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
-    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
-
-    /* User function to cast virtual address to CPU bus address */
-    unsigned int  (*port_virt_to_phys)(unsigned int addr);
-    /* User scratch pad for user specific data structures */
-    void *port_private;
-
-    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
-    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
-
-    /* Tx/Rx rings managment indexes fields. For driver use */
-
-    /* Next available Rx resource */
-    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
-    /* Returning Rx resource */
-    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
-
-    /* Next available Tx resource */
-    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
-    /* Returning Tx resource */
-    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
-    /* An extra Tx index to support transmit of multiple buffers per packet */
-    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
-
-    /* Tx/Rx rings size and base variables fields. For driver use */
-
-    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
-    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
-    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
-
-    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
-    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
-    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
-
-} ETH_PORT_INFO;
-
-
-/* ethernet.h API list */
-
-/* Port operation control routines */
-static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
-static void eth_port_reset(ETH_PORT	eth_port_num);
-static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
-
-
-/* Port MAC address routines */
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
-				  unsigned char *p_addr,
-				  ETH_QUEUE queue);
-#if 0	/* FIXME */
-static void eth_port_mc_addr	(ETH_PORT eth_port_num,
-				 unsigned char *p_addr,
-				 ETH_QUEUE queue,
-				 int option);
-#endif
-
-/* PHY and MIB routines */
-static bool ethernet_phy_reset(ETH_PORT eth_port_num);
-
-static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
-				   unsigned int phy_reg,
-				   unsigned int value);
-
-static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
-				  unsigned int phy_reg,
-				  unsigned int* value);
-
-static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
-
-/* Port data flow control routines */
-static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
-					     ETH_QUEUE tx_queue,
-					     PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
-					      ETH_QUEUE tx_queue,
-					      PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
-					     ETH_QUEUE rx_queue,
-					     PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
-					      ETH_QUEUE rx_queue,
-					      PKT_INFO *p_pkt_info);
-
-
-static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
-				    ETH_QUEUE	tx_queue,
-				    int				tx_desc_num,
-				    int				tx_buff_size,
-				    unsigned int	tx_desc_base_addr,
-				    unsigned int	tx_buff_base_addr);
-
-static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
-				    ETH_QUEUE	rx_queue,
-				    int				rx_desc_num,
-				    int				rx_buff_size,
-				    unsigned int	rx_desc_base_addr,
-				    unsigned int	rx_buff_base_addr);
-
-#endif /* MV64460_ETH_ */
diff --git a/board/Marvell/db64460/mv_regs.h b/board/Marvell/db64460/mv_regs.h
deleted file mode 100644
index 70b6d2eeacc..00000000000
--- a/board/Marvell/db64460/mv_regs.h
+++ /dev/null
@@ -1,1108 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/********************************************************************************
-* gt64460r.h - GT-64460 Internal registers definition file.
-*
-* DESCRIPTION:
-*	None.
-*
-* DEPENDENCIES:
-*	None.
-*
-*******************************************************************************/
-
-#ifndef __INCmv_regsh
-#define __INCmv_regsh
-
-#define MV64460
-
-/* Supported by the Atlantis */
-#define MV64460_INCLUDE_PCI_1
-#define MV64460_INCLUDE_PCI_0_ARBITER
-#define MV64460_INCLUDE_PCI_1_ARBITER
-#define MV64460_INCLUDE_SNOOP_SUPPORT
-#define MV64460_INCLUDE_P2P
-#define MV64460_INCLUDE_ETH_PORT_2
-#define MV64460_INCLUDE_CPU_MAPPING
-#define MV64460_INCLUDE_MPSC
-
-/* Not supported features */
-#undef	INCLUDE_CNTMR_4_7
-#undef	INCLUDE_DMA_4_7
-
-/****************************************/
-/* Processor Address Space		*/
-/****************************************/
-
-/* DDR SDRAM BAR and size registers */
-
-#define MV64460_CS_0_BASE_ADDR					    0x008
-#define MV64460_CS_0_SIZE					    0x010
-#define MV64460_CS_1_BASE_ADDR					    0x208
-#define MV64460_CS_1_SIZE					    0x210
-#define MV64460_CS_2_BASE_ADDR					    0x018
-#define MV64460_CS_2_SIZE					    0x020
-#define MV64460_CS_3_BASE_ADDR					    0x218
-#define MV64460_CS_3_SIZE					    0x220
-
-/* Devices BAR and size registers */
-
-#define MV64460_DEV_CS0_BASE_ADDR				    0x028
-#define MV64460_DEV_CS0_SIZE					    0x030
-#define MV64460_DEV_CS1_BASE_ADDR				    0x228
-#define MV64460_DEV_CS1_SIZE					    0x230
-#define MV64460_DEV_CS2_BASE_ADDR				    0x248
-#define MV64460_DEV_CS2_SIZE					    0x250
-#define MV64460_DEV_CS3_BASE_ADDR				    0x038
-#define MV64460_DEV_CS3_SIZE					    0x040
-#define MV64460_BOOTCS_BASE_ADDR				    0x238
-#define MV64460_BOOTCS_SIZE					    0x240
-
-/* PCI 0 BAR and size registers */
-
-#define MV64460_PCI_0_IO_BASE_ADDR				    0x048
-#define MV64460_PCI_0_IO_SIZE					    0x050
-#define MV64460_PCI_0_MEMORY0_BASE_ADDR				    0x058
-#define MV64460_PCI_0_MEMORY0_SIZE				    0x060
-#define MV64460_PCI_0_MEMORY1_BASE_ADDR				    0x080
-#define MV64460_PCI_0_MEMORY1_SIZE				    0x088
-#define MV64460_PCI_0_MEMORY2_BASE_ADDR				    0x258
-#define MV64460_PCI_0_MEMORY2_SIZE				    0x260
-#define MV64460_PCI_0_MEMORY3_BASE_ADDR				    0x280
-#define MV64460_PCI_0_MEMORY3_SIZE				    0x288
-
-/* PCI 1 BAR and size registers */
-#define MV64460_PCI_1_IO_BASE_ADDR				    0x090
-#define MV64460_PCI_1_IO_SIZE					    0x098
-#define MV64460_PCI_1_MEMORY0_BASE_ADDR				    0x0a0
-#define MV64460_PCI_1_MEMORY0_SIZE				    0x0a8
-#define MV64460_PCI_1_MEMORY1_BASE_ADDR				    0x0b0
-#define MV64460_PCI_1_MEMORY1_SIZE				    0x0b8
-#define MV64460_PCI_1_MEMORY2_BASE_ADDR				    0x2a0
-#define MV64460_PCI_1_MEMORY2_SIZE				    0x2a8
-#define MV64460_PCI_1_MEMORY3_BASE_ADDR				    0x2b0
-#define MV64460_PCI_1_MEMORY3_SIZE				    0x2b8
-
-/* SRAM base address */
-#define MV64460_INTEGRATED_SRAM_BASE_ADDR			    0x268
-
-/* internal registers space base address */
-#define MV64460_INTERNAL_SPACE_BASE_ADDR			    0x068
-
-/* Enables the CS , DEV_CS , PCI 0 and PCI 1
-   windows above */
-#define MV64460_BASE_ADDR_ENABLE				    0x278
-
-/****************************************/
-/* PCI remap registers			*/
-/****************************************/
-      /* PCI 0 */
-#define MV64460_PCI_0_IO_ADDR_REMAP				    0x0f0
-#define MV64460_PCI_0_MEMORY0_LOW_ADDR_REMAP			    0x0f8
-#define MV64460_PCI_0_MEMORY0_HIGH_ADDR_REMAP			    0x320
-#define MV64460_PCI_0_MEMORY1_LOW_ADDR_REMAP			    0x100
-#define MV64460_PCI_0_MEMORY1_HIGH_ADDR_REMAP			    0x328
-#define MV64460_PCI_0_MEMORY2_LOW_ADDR_REMAP			    0x2f8
-#define MV64460_PCI_0_MEMORY2_HIGH_ADDR_REMAP			    0x330
-#define MV64460_PCI_0_MEMORY3_LOW_ADDR_REMAP			    0x300
-#define MV64460_PCI_0_MEMORY3_HIGH_ADDR_REMAP			    0x338
-      /* PCI 1 */
-#define MV64460_PCI_1_IO_ADDR_REMAP				    0x108
-#define MV64460_PCI_1_MEMORY0_LOW_ADDR_REMAP			    0x110
-#define MV64460_PCI_1_MEMORY0_HIGH_ADDR_REMAP			    0x340
-#define MV64460_PCI_1_MEMORY1_LOW_ADDR_REMAP			    0x118
-#define MV64460_PCI_1_MEMORY1_HIGH_ADDR_REMAP			    0x348
-#define MV64460_PCI_1_MEMORY2_LOW_ADDR_REMAP			    0x310
-#define MV64460_PCI_1_MEMORY2_HIGH_ADDR_REMAP			    0x350
-#define MV64460_PCI_1_MEMORY3_LOW_ADDR_REMAP			    0x318
-#define MV64460_PCI_1_MEMORY3_HIGH_ADDR_REMAP			    0x358
-
-#define MV64460_CPU_PCI_0_HEADERS_RETARGET_CONTROL		    0x3b0
-#define MV64460_CPU_PCI_0_HEADERS_RETARGET_BASE			    0x3b8
-#define MV64460_CPU_PCI_1_HEADERS_RETARGET_CONTROL		    0x3c0
-#define MV64460_CPU_PCI_1_HEADERS_RETARGET_BASE			    0x3c8
-#define MV64460_CPU_GE_HEADERS_RETARGET_CONTROL			    0x3d0
-#define MV64460_CPU_GE_HEADERS_RETARGET_BASE			    0x3d8
-#define MV64460_CPU_IDMA_HEADERS_RETARGET_CONTROL		    0x3e0
-#define MV64460_CPU_IDMA_HEADERS_RETARGET_BASE			    0x3e8
-
-/****************************************/
-/*	   CPU Control Registers	*/
-/****************************************/
-
-#define MV64460_CPU_CONFIG					    0x000
-#define MV64460_CPU_MODE					    0x120
-#define MV64460_CPU_MASTER_CONTROL				    0x160
-#define MV64460_CPU_CROSS_BAR_CONTROL_LOW			    0x150
-#define MV64460_CPU_CROSS_BAR_CONTROL_HIGH			    0x158
-#define MV64460_CPU_CROSS_BAR_TIMEOUT				    0x168
-
-/****************************************/
-/* SMP RegisterS			*/
-/****************************************/
-
-#define MV64460_SMP_WHO_AM_I					    0x200
-#define MV64460_SMP_CPU0_DOORBELL				    0x214
-#define MV64460_SMP_CPU0_DOORBELL_CLEAR				    0x21C
-#define MV64460_SMP_CPU1_DOORBELL				    0x224
-#define MV64460_SMP_CPU1_DOORBELL_CLEAR				    0x22C
-#define MV64460_SMP_CPU0_DOORBELL_MASK				    0x234
-#define MV64460_SMP_CPU1_DOORBELL_MASK				    0x23C
-#define MV64460_SMP_SEMAPHOR0					    0x244
-#define MV64460_SMP_SEMAPHOR1					    0x24c
-#define MV64460_SMP_SEMAPHOR2					    0x254
-#define MV64460_SMP_SEMAPHOR3					    0x25c
-#define MV64460_SMP_SEMAPHOR4					    0x264
-#define MV64460_SMP_SEMAPHOR5					    0x26c
-#define MV64460_SMP_SEMAPHOR6					    0x274
-#define MV64460_SMP_SEMAPHOR7					    0x27c
-
-/****************************************/
-/*  CPU Sync Barrier Register		*/
-/****************************************/
-
-#define MV64460_CPU_0_SYNC_BARRIER_TRIGGER			    0x0c0
-#define MV64460_CPU_0_SYNC_BARRIER_VIRTUAL			    0x0c8
-#define MV64460_CPU_1_SYNC_BARRIER_TRIGGER			    0x0d0
-#define MV64460_CPU_1_SYNC_BARRIER_VIRTUAL			    0x0d8
-
-/****************************************/
-/* CPU Access Protect			*/
-/****************************************/
-
-#define MV64460_CPU_PROTECT_WINDOW_0_BASE_ADDR			    0x180
-#define MV64460_CPU_PROTECT_WINDOW_0_SIZE			    0x188
-#define MV64460_CPU_PROTECT_WINDOW_1_BASE_ADDR			    0x190
-#define MV64460_CPU_PROTECT_WINDOW_1_SIZE			    0x198
-#define MV64460_CPU_PROTECT_WINDOW_2_BASE_ADDR			    0x1a0
-#define MV64460_CPU_PROTECT_WINDOW_2_SIZE			    0x1a8
-#define MV64460_CPU_PROTECT_WINDOW_3_BASE_ADDR			    0x1b0
-#define MV64460_CPU_PROTECT_WINDOW_3_SIZE			    0x1b8
-
-
-/****************************************/
-/*	    CPU Error Report		*/
-/****************************************/
-
-#define MV64460_CPU_ERROR_ADDR_LOW				    0x070
-#define MV64460_CPU_ERROR_ADDR_HIGH				    0x078
-#define MV64460_CPU_ERROR_DATA_LOW				    0x128
-#define MV64460_CPU_ERROR_DATA_HIGH				    0x130
-#define MV64460_CPU_ERROR_PARITY				    0x138
-#define MV64460_CPU_ERROR_CAUSE					    0x140
-#define MV64460_CPU_ERROR_MASK					    0x148
-
-/****************************************/
-/*	CPU Interface Debug Registers	*/
-/****************************************/
-
-#define MV64460_PUNIT_SLAVE_DEBUG_LOW				    0x360
-#define MV64460_PUNIT_SLAVE_DEBUG_HIGH				    0x368
-#define MV64460_PUNIT_MASTER_DEBUG_LOW				    0x370
-#define MV64460_PUNIT_MASTER_DEBUG_HIGH				    0x378
-#define MV64460_PUNIT_MMASK					    0x3e4
-
-/****************************************/
-/*  Integrated SRAM Registers		*/
-/****************************************/
-
-#define MV64460_SRAM_CONFIG					    0x380
-#define MV64460_SRAM_TEST_MODE					    0X3F4
-#define MV64460_SRAM_ERROR_CAUSE				    0x388
-#define MV64460_SRAM_ERROR_ADDR					    0x390
-#define MV64460_SRAM_ERROR_ADDR_HIGH				    0X3F8
-#define MV64460_SRAM_ERROR_DATA_LOW				    0x398
-#define MV64460_SRAM_ERROR_DATA_HIGH				    0x3a0
-#define MV64460_SRAM_ERROR_DATA_PARITY				    0x3a8
-
-/****************************************/
-/* SDRAM Configuration			*/
-/****************************************/
-
-#define MV64460_SDRAM_CONFIG					    0x1400
-#define MV64460_D_UNIT_CONTROL_LOW				    0x1404
-#define MV64460_D_UNIT_CONTROL_HIGH				    0x1424
-#define MV64460_SDRAM_TIMING_CONTROL_LOW			    0x1408
-#define MV64460_SDRAM_TIMING_CONTROL_HIGH			    0x140c
-#define MV64460_SDRAM_ADDR_CONTROL				    0x1410
-#define MV64460_SDRAM_OPEN_PAGES_CONTROL			    0x1414
-#define MV64460_SDRAM_OPERATION					    0x1418
-#define MV64460_SDRAM_MODE					    0x141c
-#define MV64460_EXTENDED_DRAM_MODE				    0x1420
-#define MV64460_SDRAM_CROSS_BAR_CONTROL_LOW			    0x1430
-#define MV64460_SDRAM_CROSS_BAR_CONTROL_HIGH			    0x1434
-#define MV64460_SDRAM_CROSS_BAR_TIMEOUT				    0x1438
-#define MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION		    0x14c0
-#define MV64460_SDRAM_DATA_PADS_CALIBRATION			    0x14c4
-
-/****************************************/
-/* SDRAM Error Report			*/
-/****************************************/
-
-#define MV64460_SDRAM_ERROR_DATA_LOW				    0x1444
-#define MV64460_SDRAM_ERROR_DATA_HIGH				    0x1440
-#define MV64460_SDRAM_ERROR_ADDR				    0x1450
-#define MV64460_SDRAM_RECEIVED_ECC				    0x1448
-#define MV64460_SDRAM_CALCULATED_ECC				    0x144c
-#define MV64460_SDRAM_ECC_CONTROL				    0x1454
-#define MV64460_SDRAM_ECC_ERROR_COUNTER				    0x1458
-
-/******************************************/
-/*  Controlled Delay Line (CDL) Registers */
-/******************************************/
-
-#define MV64460_DFCDL_CONFIG0					    0x1480
-#define MV64460_DFCDL_CONFIG1					    0x1484
-#define MV64460_DLL_WRITE					    0x1488
-#define MV64460_DLL_READ					    0x148c
-#define MV64460_SRAM_ADDR					    0x1490
-#define MV64460_SRAM_DATA0					    0x1494
-#define MV64460_SRAM_DATA1					    0x1498
-#define MV64460_SRAM_DATA2					    0x149c
-#define MV64460_DFCL_PROBE					    0x14a0
-
-/******************************************/
-/*   Debug Registers			  */
-/******************************************/
-
-#define MV64460_DUNIT_DEBUG_LOW					    0x1460
-#define MV64460_DUNIT_DEBUG_HIGH				    0x1464
-#define MV64460_DUNIT_MMASK					    0X1b40
-
-/****************************************/
-/* Device Parameters			*/
-/****************************************/
-
-#define MV64460_DEVICE_BANK0_PARAMETERS				    0x45c
-#define MV64460_DEVICE_BANK1_PARAMETERS				    0x460
-#define MV64460_DEVICE_BANK2_PARAMETERS				    0x464
-#define MV64460_DEVICE_BANK3_PARAMETERS				    0x468
-#define MV64460_DEVICE_BOOT_BANK_PARAMETERS			    0x46c
-#define MV64460_DEVICE_INTERFACE_CONTROL			    0x4c0
-#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		    0x4c8
-#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		    0x4cc
-#define MV64460_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT		    0x4c4
-
-/****************************************/
-/* Device interrupt registers		*/
-/****************************************/
-
-#define MV64460_DEVICE_INTERRUPT_CAUSE				    0x4d0
-#define MV64460_DEVICE_INTERRUPT_MASK				    0x4d4
-#define MV64460_DEVICE_ERROR_ADDR				    0x4d8
-#define MV64460_DEVICE_ERROR_DATA				    0x4dc
-#define MV64460_DEVICE_ERROR_PARITY				    0x4e0
-
-/****************************************/
-/* Device debug registers		*/
-/****************************************/
-
-#define MV64460_DEVICE_DEBUG_LOW				    0x4e4
-#define MV64460_DEVICE_DEBUG_HIGH				    0x4e8
-#define MV64460_RUNIT_MMASK					    0x4f0
-
-/****************************************/
-/* PCI Slave Address Decoding registers */
-/****************************************/
-
-#define MV64460_PCI_0_CS_0_BANK_SIZE				    0xc08
-#define MV64460_PCI_1_CS_0_BANK_SIZE				    0xc88
-#define MV64460_PCI_0_CS_1_BANK_SIZE				    0xd08
-#define MV64460_PCI_1_CS_1_BANK_SIZE				    0xd88
-#define MV64460_PCI_0_CS_2_BANK_SIZE				    0xc0c
-#define MV64460_PCI_1_CS_2_BANK_SIZE				    0xc8c
-#define MV64460_PCI_0_CS_3_BANK_SIZE				    0xd0c
-#define MV64460_PCI_1_CS_3_BANK_SIZE				    0xd8c
-#define MV64460_PCI_0_DEVCS_0_BANK_SIZE				    0xc10
-#define MV64460_PCI_1_DEVCS_0_BANK_SIZE				    0xc90
-#define MV64460_PCI_0_DEVCS_1_BANK_SIZE				    0xd10
-#define MV64460_PCI_1_DEVCS_1_BANK_SIZE				    0xd90
-#define MV64460_PCI_0_DEVCS_2_BANK_SIZE				    0xd18
-#define MV64460_PCI_1_DEVCS_2_BANK_SIZE				    0xd98
-#define MV64460_PCI_0_DEVCS_3_BANK_SIZE				    0xc14
-#define MV64460_PCI_1_DEVCS_3_BANK_SIZE				    0xc94
-#define MV64460_PCI_0_DEVCS_BOOT_BANK_SIZE			    0xd14
-#define MV64460_PCI_1_DEVCS_BOOT_BANK_SIZE			    0xd94
-#define MV64460_PCI_0_P2P_MEM0_BAR_SIZE				    0xd1c
-#define MV64460_PCI_1_P2P_MEM0_BAR_SIZE				    0xd9c
-#define MV64460_PCI_0_P2P_MEM1_BAR_SIZE				    0xd20
-#define MV64460_PCI_1_P2P_MEM1_BAR_SIZE				    0xda0
-#define MV64460_PCI_0_P2P_I_O_BAR_SIZE				    0xd24
-#define MV64460_PCI_1_P2P_I_O_BAR_SIZE				    0xda4
-#define MV64460_PCI_0_CPU_BAR_SIZE				    0xd28
-#define MV64460_PCI_1_CPU_BAR_SIZE				    0xda8
-#define MV64460_PCI_0_INTERNAL_SRAM_BAR_SIZE			    0xe00
-#define MV64460_PCI_1_INTERNAL_SRAM_BAR_SIZE			    0xe80
-#define MV64460_PCI_0_EXPANSION_ROM_BAR_SIZE			    0xd2c
-#define MV64460_PCI_1_EXPANSION_ROM_BAR_SIZE			    0xd9c
-#define MV64460_PCI_0_BASE_ADDR_REG_ENABLE			    0xc3c
-#define MV64460_PCI_1_BASE_ADDR_REG_ENABLE			    0xcbc
-#define MV64460_PCI_0_CS_0_BASE_ADDR_REMAP			    0xc48
-#define MV64460_PCI_1_CS_0_BASE_ADDR_REMAP			    0xcc8
-#define MV64460_PCI_0_CS_1_BASE_ADDR_REMAP			    0xd48
-#define MV64460_PCI_1_CS_1_BASE_ADDR_REMAP			    0xdc8
-#define MV64460_PCI_0_CS_2_BASE_ADDR_REMAP			    0xc4c
-#define MV64460_PCI_1_CS_2_BASE_ADDR_REMAP			    0xccc
-#define MV64460_PCI_0_CS_3_BASE_ADDR_REMAP			    0xd4c
-#define MV64460_PCI_1_CS_3_BASE_ADDR_REMAP			    0xdcc
-#define MV64460_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP			    0xF04
-#define MV64460_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP			    0xF84
-#define MV64460_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP			    0xF08
-#define MV64460_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP			    0xF88
-#define MV64460_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP			    0xF0C
-#define MV64460_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP			    0xF8C
-#define MV64460_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP			    0xF10
-#define MV64460_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP			    0xF90
-#define MV64460_PCI_0_DEVCS_0_BASE_ADDR_REMAP			    0xc50
-#define MV64460_PCI_1_DEVCS_0_BASE_ADDR_REMAP			    0xcd0
-#define MV64460_PCI_0_DEVCS_1_BASE_ADDR_REMAP			    0xd50
-#define MV64460_PCI_1_DEVCS_1_BASE_ADDR_REMAP			    0xdd0
-#define MV64460_PCI_0_DEVCS_2_BASE_ADDR_REMAP			    0xd58
-#define MV64460_PCI_1_DEVCS_2_BASE_ADDR_REMAP			    0xdd8
-#define MV64460_PCI_0_DEVCS_3_BASE_ADDR_REMAP			    0xc54
-#define MV64460_PCI_1_DEVCS_3_BASE_ADDR_REMAP			    0xcd4
-#define MV64460_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xd54
-#define MV64460_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xdd4
-#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xd5c
-#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xddc
-#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xd60
-#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xde0
-#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xd64
-#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xde4
-#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xd68
-#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xde8
-#define MV64460_PCI_0_P2P_I_O_BASE_ADDR_REMAP			    0xd6c
-#define MV64460_PCI_1_P2P_I_O_BASE_ADDR_REMAP			    0xdec
-#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_LOW			    0xd70
-#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_LOW			    0xdf0
-#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_HIGH			    0xd74
-#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_HIGH			    0xdf4
-#define MV64460_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf00
-#define MV64460_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf80
-#define MV64460_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		    0xf38
-#define MV64460_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		    0xfb8
-#define MV64460_PCI_0_ADDR_DECODE_CONTROL			    0xd3c
-#define MV64460_PCI_1_ADDR_DECODE_CONTROL			    0xdbc
-#define MV64460_PCI_0_HEADERS_RETARGET_CONTROL			    0xF40
-#define MV64460_PCI_1_HEADERS_RETARGET_CONTROL			    0xFc0
-#define MV64460_PCI_0_HEADERS_RETARGET_BASE			    0xF44
-#define MV64460_PCI_1_HEADERS_RETARGET_BASE			    0xFc4
-#define MV64460_PCI_0_HEADERS_RETARGET_HIGH			    0xF48
-#define MV64460_PCI_1_HEADERS_RETARGET_HIGH			    0xFc8
-
-/***********************************/
-/*   PCI Control Register Map	   */
-/***********************************/
-
-#define MV64460_PCI_0_DLL_STATUS_AND_COMMAND			    0x1d20
-#define MV64460_PCI_1_DLL_STATUS_AND_COMMAND			    0x1da0
-#define MV64460_PCI_0_MPP_PADS_DRIVE_CONTROL			    0x1d1C
-#define MV64460_PCI_1_MPP_PADS_DRIVE_CONTROL			    0x1d9C
-#define MV64460_PCI_0_COMMAND					    0xc00
-#define MV64460_PCI_1_COMMAND					    0xc80
-#define MV64460_PCI_0_MODE					    0xd00
-#define MV64460_PCI_1_MODE					    0xd80
-#define MV64460_PCI_0_RETRY					    0xc04
-#define MV64460_PCI_1_RETRY					    0xc84
-#define MV64460_PCI_0_READ_BUFFER_DISCARD_TIMER			    0xd04
-#define MV64460_PCI_1_READ_BUFFER_DISCARD_TIMER			    0xd84
-#define MV64460_PCI_0_MSI_TRIGGER_TIMER				    0xc38
-#define MV64460_PCI_1_MSI_TRIGGER_TIMER				    0xcb8
-#define MV64460_PCI_0_ARBITER_CONTROL				    0x1d00
-#define MV64460_PCI_1_ARBITER_CONTROL				    0x1d80
-#define MV64460_PCI_0_CROSS_BAR_CONTROL_LOW			    0x1d08
-#define MV64460_PCI_1_CROSS_BAR_CONTROL_LOW			    0x1d88
-#define MV64460_PCI_0_CROSS_BAR_CONTROL_HIGH			    0x1d0c
-#define MV64460_PCI_1_CROSS_BAR_CONTROL_HIGH			    0x1d8c
-#define MV64460_PCI_0_CROSS_BAR_TIMEOUT				    0x1d04
-#define MV64460_PCI_1_CROSS_BAR_TIMEOUT				    0x1d84
-#define MV64460_PCI_0_SYNC_BARRIER_TRIGGER_REG			    0x1D18
-#define MV64460_PCI_1_SYNC_BARRIER_TRIGGER_REG			    0x1D98
-#define MV64460_PCI_0_SYNC_BARRIER_VIRTUAL_REG			    0x1d10
-#define MV64460_PCI_1_SYNC_BARRIER_VIRTUAL_REG			    0x1d90
-#define MV64460_PCI_0_P2P_CONFIG				    0x1d14
-#define MV64460_PCI_1_P2P_CONFIG				    0x1d94
-
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_LOW			    0x1e00
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_HIGH		    0x1e04
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_0			    0x1e08
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_LOW			    0x1e10
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_HIGH		    0x1e14
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_1			    0x1e18
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_LOW			    0x1e20
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_HIGH		    0x1e24
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_2			    0x1e28
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_LOW			    0x1e30
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_HIGH		    0x1e34
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_3			    0x1e38
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_LOW			    0x1e40
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_HIGH		    0x1e44
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_4			    0x1e48
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_LOW			    0x1e50
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_HIGH		    0x1e54
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_5			    0x1e58
-
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_LOW			    0x1e80
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_HIGH		    0x1e84
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_0			    0x1e88
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_LOW			    0x1e90
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_HIGH		    0x1e94
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_1			    0x1e98
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_LOW			    0x1ea0
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_HIGH		    0x1ea4
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_2			    0x1ea8
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_LOW			    0x1eb0
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_HIGH		    0x1eb4
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_3			    0x1eb8
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_LOW			    0x1ec0
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_HIGH		    0x1ec4
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_4			    0x1ec8
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_LOW			    0x1ed0
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_HIGH		    0x1ed4
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_5			    0x1ed8
-
-/****************************************/
-/*   PCI Configuration Access Registers */
-/****************************************/
-
-#define MV64460_PCI_0_CONFIG_ADDR				    0xcf8
-#define MV64460_PCI_0_CONFIG_DATA_VIRTUAL_REG			    0xcfc
-#define MV64460_PCI_1_CONFIG_ADDR				    0xc78
-#define MV64460_PCI_1_CONFIG_DATA_VIRTUAL_REG			    0xc7c
-#define MV64460_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xc34
-#define MV64460_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xcb4
-
-/****************************************/
-/*   PCI Error Report Registers		*/
-/****************************************/
-
-#define MV64460_PCI_0_SERR_MASK					    0xc28
-#define MV64460_PCI_1_SERR_MASK					    0xca8
-#define MV64460_PCI_0_ERROR_ADDR_LOW				    0x1d40
-#define MV64460_PCI_1_ERROR_ADDR_LOW				    0x1dc0
-#define MV64460_PCI_0_ERROR_ADDR_HIGH				    0x1d44
-#define MV64460_PCI_1_ERROR_ADDR_HIGH				    0x1dc4
-#define MV64460_PCI_0_ERROR_ATTRIBUTE				    0x1d48
-#define MV64460_PCI_1_ERROR_ATTRIBUTE				    0x1dc8
-#define MV64460_PCI_0_ERROR_COMMAND				    0x1d50
-#define MV64460_PCI_1_ERROR_COMMAND				    0x1dd0
-#define MV64460_PCI_0_ERROR_CAUSE				    0x1d58
-#define MV64460_PCI_1_ERROR_CAUSE				    0x1dd8
-#define MV64460_PCI_0_ERROR_MASK				    0x1d5c
-#define MV64460_PCI_1_ERROR_MASK				    0x1ddc
-
-/****************************************/
-/*   PCI Debug Registers		*/
-/****************************************/
-
-#define MV64460_PCI_0_MMASK					    0X1D24
-#define MV64460_PCI_1_MMASK					    0X1DA4
-
-/*********************************************/
-/* PCI Configuration, Function 0, Registers  */
-/*********************************************/
-
-#define MV64460_PCI_DEVICE_AND_VENDOR_ID			    0x000
-#define MV64460_PCI_STATUS_AND_COMMAND				    0x004
-#define MV64460_PCI_CLASS_CODE_AND_REVISION_ID			    0x008
-#define MV64460_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	    0x00C
-
-#define MV64460_PCI_SCS_0_BASE_ADDR_LOW				    0x010
-#define MV64460_PCI_SCS_0_BASE_ADDR_HIGH			    0x014
-#define MV64460_PCI_SCS_1_BASE_ADDR_LOW				    0x018
-#define MV64460_PCI_SCS_1_BASE_ADDR_HIGH			    0x01C
-#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW	    0x020
-#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH	    0x024
-#define MV64460_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	    0x02c
-#define MV64460_PCI_EXPANSION_ROM_BASE_ADDR_REG			    0x030
-#define MV64460_PCI_CAPABILTY_LIST_POINTER			    0x034
-#define MV64460_PCI_INTERRUPT_PIN_AND_LINE			    0x03C
-       /* capability list */
-#define MV64460_PCI_POWER_MANAGEMENT_CAPABILITY			    0x040
-#define MV64460_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044
-#define MV64460_PCI_VPD_ADDR					    0x048
-#define MV64460_PCI_VPD_DATA					    0x04c
-#define MV64460_PCI_MSI_MESSAGE_CONTROL				    0x050
-#define MV64460_PCI_MSI_MESSAGE_ADDR				    0x054
-#define MV64460_PCI_MSI_MESSAGE_UPPER_ADDR			    0x058
-#define MV64460_PCI_MSI_MESSAGE_DATA				    0x05c
-#define MV64460_PCI_X_COMMAND					    0x060
-#define MV64460_PCI_X_STATUS					    0x064
-#define MV64460_PCI_COMPACT_PCI_HOT_SWAP			    0x068
-
-/***********************************************/
-/*   PCI Configuration, Function 1, Registers  */
-/***********************************************/
-
-#define MV64460_PCI_SCS_2_BASE_ADDR_LOW				    0x110
-#define MV64460_PCI_SCS_2_BASE_ADDR_HIGH			    0x114
-#define MV64460_PCI_SCS_3_BASE_ADDR_LOW				    0x118
-#define MV64460_PCI_SCS_3_BASE_ADDR_HIGH			    0x11c
-#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_LOW			    0x120
-#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH		    0x124
-
-/***********************************************/
-/*  PCI Configuration, Function 2, Registers   */
-/***********************************************/
-
-#define MV64460_PCI_DEVCS_0_BASE_ADDR_LOW			    0x210
-#define MV64460_PCI_DEVCS_0_BASE_ADDR_HIGH			    0x214
-#define MV64460_PCI_DEVCS_1_BASE_ADDR_LOW			    0x218
-#define MV64460_PCI_DEVCS_1_BASE_ADDR_HIGH			    0x21c
-#define MV64460_PCI_DEVCS_2_BASE_ADDR_LOW			    0x220
-#define MV64460_PCI_DEVCS_2_BASE_ADDR_HIGH			    0x224
-
-/***********************************************/
-/*  PCI Configuration, Function 3, Registers   */
-/***********************************************/
-
-#define MV64460_PCI_DEVCS_3_BASE_ADDR_LOW			    0x310
-#define MV64460_PCI_DEVCS_3_BASE_ADDR_HIGH			    0x314
-#define MV64460_PCI_BOOT_CS_BASE_ADDR_LOW			    0x318
-#define MV64460_PCI_BOOT_CS_BASE_ADDR_HIGH			    0x31c
-#define MV64460_PCI_CPU_BASE_ADDR_LOW				    0x220
-#define MV64460_PCI_CPU_BASE_ADDR_HIGH				    0x224
-
-/***********************************************/
-/*  PCI Configuration, Function 4, Registers   */
-/***********************************************/
-
-#define MV64460_PCI_P2P_MEM0_BASE_ADDR_LOW			    0x410
-#define MV64460_PCI_P2P_MEM0_BASE_ADDR_HIGH			    0x414
-#define MV64460_PCI_P2P_MEM1_BASE_ADDR_LOW			    0x418
-#define MV64460_PCI_P2P_MEM1_BASE_ADDR_HIGH			    0x41c
-#define MV64460_PCI_P2P_I_O_BASE_ADDR				    0x420
-#define MV64460_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR		    0x424
-
-/****************************************/
-/* Messaging Unit Registers (I20)	*/
-/****************************************/
-
-#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x010
-#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x014
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x018
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x01C
-#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE		    0x020
-#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x024
-#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x028
-#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE		    0x02C
-#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x030
-#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x034
-#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x040
-#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x044
-#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE		    0x050
-#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE		    0x054
-#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x060
-#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x064
-#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x068
-#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x06C
-#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x070
-#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x074
-#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x0F8
-#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x0FC
-
-#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x090
-#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x094
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x098
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x09C
-#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0A0
-#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0A4
-#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0A8
-#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0AC
-#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0B0
-#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0B4
-#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C0
-#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C4
-#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE		    0x0D0
-#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE		    0x0D4
-#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E0
-#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0E4
-#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E8
-#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x0EC
-#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0F0
-#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0F4
-#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x078
-#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x07C
-
-#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C10
-#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C14
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C18
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C1C
-#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C20
-#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C24
-#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C28
-#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C2C
-#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C30
-#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C34
-#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C40
-#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C44
-#define MV64460_I2O_QUEUE_CONTROL_REG_CPU0_SIDE			    0x1C50
-#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE		    0x1C54
-#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C60
-#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C64
-#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1C68
-#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1C6C
-#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C70
-#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C74
-#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1CF8
-#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1CFC
-#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C90
-#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C94
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C98
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C9C
-#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CA0
-#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CA4
-#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CA8
-#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CAC
-#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CB0
-#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CB4
-#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC0
-#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC4
-#define MV64460_I2O_QUEUE_CONTROL_REG_CPU1_SIDE			    0x1CD0
-#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE		    0x1CD4
-#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE0
-#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CE4
-#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE8
-#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1CEC
-#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CF0
-#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CF4
-#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1C78
-#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1C7C
-
-/****************************************/
-/*	  Ethernet Unit Registers		*/
-/****************************************/
-
-#define MV64460_ETH_PHY_ADDR_REG				    0x2000
-#define MV64460_ETH_SMI_REG					    0x2004
-#define MV64460_ETH_UNIT_DEFAULT_ADDR_REG			    0x2008
-#define MV64460_ETH_UNIT_DEFAULTID_REG				    0x200c
-#define MV64460_ETH_UNIT_INTERRUPT_CAUSE_REG			    0x2080
-#define MV64460_ETH_UNIT_INTERRUPT_MASK_REG			    0x2084
-#define MV64460_ETH_UNIT_INTERNAL_USE_REG			    0x24fc
-#define MV64460_ETH_UNIT_ERROR_ADDR_REG				    0x2094
-#define MV64460_ETH_BAR_0					    0x2200
-#define MV64460_ETH_BAR_1					    0x2208
-#define MV64460_ETH_BAR_2					    0x2210
-#define MV64460_ETH_BAR_3					    0x2218
-#define MV64460_ETH_BAR_4					    0x2220
-#define MV64460_ETH_BAR_5					    0x2228
-#define MV64460_ETH_SIZE_REG_0					    0x2204
-#define MV64460_ETH_SIZE_REG_1					    0x220c
-#define MV64460_ETH_SIZE_REG_2					    0x2214
-#define MV64460_ETH_SIZE_REG_3					    0x221c
-#define MV64460_ETH_SIZE_REG_4					    0x2224
-#define MV64460_ETH_SIZE_REG_5					    0x222c
-#define MV64460_ETH_HEADERS_RETARGET_BASE_REG			    0x2230
-#define MV64460_ETH_HEADERS_RETARGET_CONTROL_REG		    0x2234
-#define MV64460_ETH_HIGH_ADDR_REMAP_REG_0			    0x2280
-#define MV64460_ETH_HIGH_ADDR_REMAP_REG_1			    0x2284
-#define MV64460_ETH_HIGH_ADDR_REMAP_REG_2			    0x2288
-#define MV64460_ETH_HIGH_ADDR_REMAP_REG_3			    0x228c
-#define MV64460_ETH_BASE_ADDR_ENABLE_REG			    0x2290
-#define MV64460_ETH_ACCESS_PROTECTION_REG(port)			   (0x2294 + (port<<2))
-#define MV64460_ETH_MIB_COUNTERS_BASE(port)			   (0x3000 + (port<<7))
-#define MV64460_ETH_PORT_CONFIG_REG(port)			   (0x2400 + (port<<10))
-#define MV64460_ETH_PORT_CONFIG_EXTEND_REG(port)		   (0x2404 + (port<<10))
-#define MV64460_ETH_MII_SERIAL_PARAMETRS_REG(port)		   (0x2408 + (port<<10))
-#define MV64460_ETH_GMII_SERIAL_PARAMETRS_REG(port)		   (0x240c + (port<<10))
-#define MV64460_ETH_VLAN_ETHERTYPE_REG(port)			   (0x2410 + (port<<10))
-#define MV64460_ETH_MAC_ADDR_LOW(port)				   (0x2414 + (port<<10))
-#define MV64460_ETH_MAC_ADDR_HIGH(port)				   (0x2418 + (port<<10))
-#define MV64460_ETH_SDMA_CONFIG_REG(port)			   (0x241c + (port<<10))
-#define MV64460_ETH_DSCP_0(port)				   (0x2420 + (port<<10))
-#define MV64460_ETH_DSCP_1(port)				   (0x2424 + (port<<10))
-#define MV64460_ETH_DSCP_2(port)				   (0x2428 + (port<<10))
-#define MV64460_ETH_DSCP_3(port)				   (0x242c + (port<<10))
-#define MV64460_ETH_DSCP_4(port)				   (0x2430 + (port<<10))
-#define MV64460_ETH_DSCP_5(port)				   (0x2434 + (port<<10))
-#define MV64460_ETH_DSCP_6(port)				   (0x2438 + (port<<10))
-#define MV64460_ETH_PORT_SERIAL_CONTROL_REG(port)		   (0x243c + (port<<10))
-#define MV64460_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		   (0x2440 + (port<<10))
-#define MV64460_ETH_PORT_STATUS_REG(port)			   (0x2444 + (port<<10))
-#define MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(port)		   (0x2448 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_FIXED_PRIORITY(port)		   (0x244c + (port<<10))
-#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)	   (0x2450 + (port<<10))
-#define MV64460_ETH_MAXIMUM_TRANSMIT_UNIT(port)			   (0x2458 + (port<<10))
-#define MV64460_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)	   (0x245c + (port<<10))
-#define MV64460_ETH_INTERRUPT_CAUSE_REG(port)			   (0x2460 + (port<<10))
-#define MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG(port)		   (0x2464 + (port<<10))
-#define MV64460_ETH_INTERRUPT_MASK_REG(port)			   (0x2468 + (port<<10))
-#define MV64460_ETH_INTERRUPT_EXTEND_MASK_REG(port)		   (0x246c + (port<<10))
-#define MV64460_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2470 + (port<<10))
-#define MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2474 + (port<<10))
-#define MV64460_ETH_RX_MINIMAL_FRAME_SIZE_REG(port)		   (0x247c + (port<<10))
-#define MV64460_ETH_RX_DISCARDED_FRAMES_COUNTER(port)		   (0x2484 + (port<<10)
-#define MV64460_ETH_PORT_DEBUG_0_REG(port)			   (0x248c + (port<<10))
-#define MV64460_ETH_PORT_DEBUG_1_REG(port)			   (0x2490 + (port<<10))
-#define MV64460_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)		   (0x2494 + (port<<10))
-#define MV64460_ETH_INTERNAL_USE_REG(port)			   (0x24fc + (port<<10))
-#define MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(port)		   (0x2680 + (port<<10))
-#define MV64460_ETH_CURRENT_SERVED_TX_DESC_PTR(port)		   (0x2684 + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x260c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x261c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x262c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x263c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x264c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x265c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x266c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x267c + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x26c0 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x26c4 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x26c8 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x26cc + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x26d0 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x26d4 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x26d8 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x26dc + (port<<10))
-#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)		   (0x2700 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)		   (0x2710 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)		   (0x2720 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)		   (0x2730 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)		   (0x2740 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)		   (0x2750 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)		   (0x2760 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)		   (0x2770 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)	   (0x2704 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)	   (0x2714 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)	   (0x2724 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)	   (0x2734 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)	   (0x2744 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)	   (0x2754 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)	   (0x2764 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)	   (0x2774 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_0_ARBITER_CONFIG(port)		   (0x2708 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_1_ARBITER_CONFIG(port)		   (0x2718 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_2_ARBITER_CONFIG(port)		   (0x2728 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_3_ARBITER_CONFIG(port)		   (0x2738 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_4_ARBITER_CONFIG(port)		   (0x2748 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_5_ARBITER_CONFIG(port)		   (0x2758 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_6_ARBITER_CONFIG(port)		   (0x2768 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_7_ARBITER_CONFIG(port)		   (0x2778 + (port<<10))
-#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)		   (0x2780 + (port<<10))
-#define MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
-#define MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)	   (0x3500 + (port<<10))
-#define MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE(port)		   (0x3600 + (port<<10))
-
-/*******************************************/
-/*	    CUNIT  Registers		   */
-/*******************************************/
-
-	 /* Address Decoding Register Map */
-
-#define MV64460_CUNIT_BASE_ADDR_REG0				    0xf200
-#define MV64460_CUNIT_BASE_ADDR_REG1				    0xf208
-#define MV64460_CUNIT_BASE_ADDR_REG2				    0xf210
-#define MV64460_CUNIT_BASE_ADDR_REG3				    0xf218
-#define MV64460_CUNIT_SIZE0					    0xf204
-#define MV64460_CUNIT_SIZE1					    0xf20c
-#define MV64460_CUNIT_SIZE2					    0xf214
-#define MV64460_CUNIT_SIZE3					    0xf21c
-#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG0			    0xf240
-#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG1			    0xf244
-#define MV64460_CUNIT_BASE_ADDR_ENABLE_REG			    0xf250
-#define MV64460_MPSC0_ACCESS_PROTECTION_REG			    0xf254
-#define MV64460_MPSC1_ACCESS_PROTECTION_REG			    0xf258
-#define MV64460_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG		    0xf25C
-
-	/*  Error Report Registers  */
-
-#define MV64460_CUNIT_INTERRUPT_CAUSE_REG			    0xf310
-#define MV64460_CUNIT_INTERRUPT_MASK_REG			    0xf314
-#define MV64460_CUNIT_ERROR_ADDR				    0xf318
-
-	/*  Cunit Control Registers */
-
-#define MV64460_CUNIT_ARBITER_CONTROL_REG			    0xf300
-#define MV64460_CUNIT_CONFIG_REG				    0xb40c
-#define MV64460_CUNIT_CRROSBAR_TIMEOUT_REG			    0xf304
-
-	/*  Cunit Debug Registers   */
-
-#define MV64460_CUNIT_DEBUG_LOW					    0xf340
-#define MV64460_CUNIT_DEBUG_HIGH				    0xf344
-#define MV64460_CUNIT_MMASK					    0xf380
-
-	/*  Cunit Base Address Enable Window Bits*/
-#define MV64460_CUNIT_BASE_ADDR_WIN_0_BIT			 0x0
-#define MV64460_CUNIT_BASE_ADDR_WIN_1_BIT			 0x1
-#define MV64460_CUNIT_BASE_ADDR_WIN_2_BIT			 0x2
-#define MV64460_CUNIT_BASE_ADDR_WIN_3_BIT			 0x3
-
-	/*  MPSCs Clocks Routing Registers  */
-
-#define MV64460_MPSC_ROUTING_REG				    0xb400
-#define MV64460_MPSC_RX_CLOCK_ROUTING_REG			    0xb404
-#define MV64460_MPSC_TX_CLOCK_ROUTING_REG			    0xb408
-
-	/*  MPSCs Interrupts Registers	  */
-
-#define MV64460_MPSC_CAUSE_REG(port)				   (0xb804 + (port<<3))
-#define MV64460_MPSC_MASK_REG(port)				   (0xb884 + (port<<3))
-
-#define MV64460_MPSC_MAIN_CONFIG_LOW(port)			   (0x8000 + (port<<12))
-#define MV64460_MPSC_MAIN_CONFIG_HIGH(port)			   (0x8004 + (port<<12))
-#define MV64460_MPSC_PROTOCOL_CONFIG(port)			   (0x8008 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG1(port)				   (0x800c + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG2(port)				   (0x8010 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG3(port)				   (0x8014 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG4(port)				   (0x8018 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG5(port)				   (0x801c + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG6(port)				   (0x8020 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG7(port)				   (0x8024 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG8(port)				   (0x8028 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG9(port)				   (0x802c + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG10(port)			   (0x8030 + (port<<12))
-
-	/*  MPSC0 Registers	 */
-
-
-/***************************************/
-/*	    SDMA Registers	       */
-/***************************************/
-
-#define MV64460_SDMA_CONFIG_REG(channel)			(0x4000 + (channel<<13))
-#define MV64460_SDMA_COMMAND_REG(channel)			(0x4008 + (channel<<13))
-#define MV64460_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)	(0x4810 + (channel<<13))
-#define MV64460_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
-#define MV64460_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))
-
-#define MV64460_SDMA_CAUSE_REG					    0xb800
-#define MV64460_SDMA_MASK_REG					    0xb880
-
-
-/****************************************/
-/* SDMA Address Space Targets		*/
-/****************************************/
-
-#define MV64460_SDMA_DRAM_CS_0_TARGET				    0x0e00
-#define MV64460_SDMA_DRAM_CS_1_TARGET				    0x0d00
-#define MV64460_SDMA_DRAM_CS_2_TARGET				    0x0b00
-#define MV64460_SDMA_DRAM_CS_3_TARGET				    0x0700
-
-#define MV64460_SDMA_DEV_CS_0_TARGET				    0x1e01
-#define MV64460_SDMA_DEV_CS_1_TARGET				    0x1d01
-#define MV64460_SDMA_DEV_CS_2_TARGET				    0x1b01
-#define MV64460_SDMA_DEV_CS_3_TARGET				    0x1701
-
-#define MV64460_SDMA_BOOT_CS_TARGET				    0x0f00
-
-#define MV64460_SDMA_SRAM_TARGET				    0x0003
-#define MV64460_SDMA_60X_BUS_TARGET				    0x4003
-
-#define MV64460_PCI_0_TARGET					    0x0003
-#define MV64460_PCI_1_TARGET					    0x0004
-
-
-/* Devices BAR and size registers */
-
-#define MV64460_DEV_CS0_BASE_ADDR				    0x028
-#define MV64460_DEV_CS0_SIZE					    0x030
-#define MV64460_DEV_CS1_BASE_ADDR				    0x228
-#define MV64460_DEV_CS1_SIZE					    0x230
-#define MV64460_DEV_CS2_BASE_ADDR				    0x248
-#define MV64460_DEV_CS2_SIZE					    0x250
-#define MV64460_DEV_CS3_BASE_ADDR				    0x038
-#define MV64460_DEV_CS3_SIZE					    0x040
-#define MV64460_BOOTCS_BASE_ADDR				    0x238
-#define MV64460_BOOTCS_SIZE					    0x240
-
-/* SDMA Window access protection */
-#define MV64460_SDMA_WIN_ACCESS_NOT_ALLOWED 0
-#define MV64460_SDMA_WIN_ACCESS_READ_ONLY 1
-#define MV64460_SDMA_WIN_ACCESS_FULL 2
-
-/* BRG Interrupts */
-
-#define MV64460_BRG_CONFIG_REG(brg)				 (0xb200 + (brg<<3))
-#define MV64460_BRG_BAUDE_TUNING_REG(brg)			 (0xb204 + (brg<<3))
-#define MV64460_BRG_CAUSE_REG					    0xb834
-#define MV64460_BRG_MASK_REG					    0xb8b4
-
-/****************************************/
-/* DMA Channel Control			*/
-/****************************************/
-
-#define MV64460_DMA_CHANNEL0_CONTROL				    0x840
-#define MV64460_DMA_CHANNEL0_CONTROL_HIGH			    0x880
-#define MV64460_DMA_CHANNEL1_CONTROL				    0x844
-#define MV64460_DMA_CHANNEL1_CONTROL_HIGH			    0x884
-#define MV64460_DMA_CHANNEL2_CONTROL				    0x848
-#define MV64460_DMA_CHANNEL2_CONTROL_HIGH			    0x888
-#define MV64460_DMA_CHANNEL3_CONTROL				    0x84C
-#define MV64460_DMA_CHANNEL3_CONTROL_HIGH			    0x88C
-
-
-/****************************************/
-/*	     IDMA Registers		*/
-/****************************************/
-
-#define MV64460_DMA_CHANNEL0_BYTE_COUNT				    0x800
-#define MV64460_DMA_CHANNEL1_BYTE_COUNT				    0x804
-#define MV64460_DMA_CHANNEL2_BYTE_COUNT				    0x808
-#define MV64460_DMA_CHANNEL3_BYTE_COUNT				    0x80C
-#define MV64460_DMA_CHANNEL0_SOURCE_ADDR			    0x810
-#define MV64460_DMA_CHANNEL1_SOURCE_ADDR			    0x814
-#define MV64460_DMA_CHANNEL2_SOURCE_ADDR			    0x818
-#define MV64460_DMA_CHANNEL3_SOURCE_ADDR			    0x81c
-#define MV64460_DMA_CHANNEL0_DESTINATION_ADDR			    0x820
-#define MV64460_DMA_CHANNEL1_DESTINATION_ADDR			    0x824
-#define MV64460_DMA_CHANNEL2_DESTINATION_ADDR			    0x828
-#define MV64460_DMA_CHANNEL3_DESTINATION_ADDR			    0x82C
-#define MV64460_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		    0x830
-#define MV64460_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		    0x834
-#define MV64460_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		    0x838
-#define MV64460_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		    0x83C
-#define MV64460_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		    0x870
-#define MV64460_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		    0x874
-#define MV64460_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		    0x878
-#define MV64460_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		    0x87C
-
- /*  IDMA Address Decoding Base Address Registers  */
-
-#define MV64460_DMA_BASE_ADDR_REG0				    0xa00
-#define MV64460_DMA_BASE_ADDR_REG1				    0xa08
-#define MV64460_DMA_BASE_ADDR_REG2				    0xa10
-#define MV64460_DMA_BASE_ADDR_REG3				    0xa18
-#define MV64460_DMA_BASE_ADDR_REG4				    0xa20
-#define MV64460_DMA_BASE_ADDR_REG5				    0xa28
-#define MV64460_DMA_BASE_ADDR_REG6				    0xa30
-#define MV64460_DMA_BASE_ADDR_REG7				    0xa38
-
- /*  IDMA Address Decoding Size Address Register   */
-
-#define MV64460_DMA_SIZE_REG0					    0xa04
-#define MV64460_DMA_SIZE_REG1					    0xa0c
-#define MV64460_DMA_SIZE_REG2					    0xa14
-#define MV64460_DMA_SIZE_REG3					    0xa1c
-#define MV64460_DMA_SIZE_REG4					    0xa24
-#define MV64460_DMA_SIZE_REG5					    0xa2c
-#define MV64460_DMA_SIZE_REG6					    0xa34
-#define MV64460_DMA_SIZE_REG7					    0xa3C
-
- /* IDMA Address Decoding High Address Remap and Access
-		  Protection Registers			  */
-
-#define MV64460_DMA_HIGH_ADDR_REMAP_REG0			    0xa60
-#define MV64460_DMA_HIGH_ADDR_REMAP_REG1			    0xa64
-#define MV64460_DMA_HIGH_ADDR_REMAP_REG2			    0xa68
-#define MV64460_DMA_HIGH_ADDR_REMAP_REG3			    0xa6C
-#define MV64460_DMA_BASE_ADDR_ENABLE_REG			    0xa80
-#define MV64460_DMA_CHANNEL0_ACCESS_PROTECTION_REG		    0xa70
-#define MV64460_DMA_CHANNEL1_ACCESS_PROTECTION_REG		    0xa74
-#define MV64460_DMA_CHANNEL2_ACCESS_PROTECTION_REG		    0xa78
-#define MV64460_DMA_CHANNEL3_ACCESS_PROTECTION_REG		    0xa7c
-#define MV64460_DMA_ARBITER_CONTROL				    0x860
-#define MV64460_DMA_CROSS_BAR_TIMEOUT				    0x8d0
-
- /*  IDMA Headers Retarget Registers   */
-
-#define MV64460_DMA_HEADERS_RETARGET_CONTROL			    0xa84
-#define MV64460_DMA_HEADERS_RETARGET_BASE			    0xa88
-
- /*  IDMA Interrupt Register  */
-
-#define MV64460_DMA_INTERRUPT_CAUSE_REG				    0x8c0
-#define MV64460_DMA_INTERRUPT_CAUSE_MASK			    0x8c4
-#define MV64460_DMA_ERROR_ADDR					    0x8c8
-#define MV64460_DMA_ERROR_SELECT				    0x8cc
-
- /*  IDMA Debug Register ( for internal use )	 */
-
-#define MV64460_DMA_DEBUG_LOW					    0x8e0
-#define MV64460_DMA_DEBUG_HIGH					    0x8e4
-#define MV64460_DMA_SPARE					    0xA8C
-
-/****************************************/
-/* Timer_Counter			*/
-/****************************************/
-
-#define MV64460_TIMER_COUNTER0					    0x850
-#define MV64460_TIMER_COUNTER1					    0x854
-#define MV64460_TIMER_COUNTER2					    0x858
-#define MV64460_TIMER_COUNTER3					    0x85C
-#define MV64460_TIMER_COUNTER_0_3_CONTROL			    0x864
-#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_CAUSE		    0x868
-#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_MASK		    0x86c
-
-/****************************************/
-/*	   Watchdog registers		*/
-/****************************************/
-
-#define MV64460_WATCHDOG_CONFIG_REG				    0xb410
-#define MV64460_WATCHDOG_VALUE_REG				    0xb414
-
-/****************************************/
-/* I2C Registers			*/
-/****************************************/
-
-#define MV64460_I2C_SLAVE_ADDR					    0xc000
-#define MV64460_I2C_EXTENDED_SLAVE_ADDR				    0xc010
-#define MV64460_I2C_DATA					    0xc004
-#define MV64460_I2C_CONTROL					    0xc008
-#define MV64460_I2C_STATUS_BAUDE_RATE				    0xc00C
-#define MV64460_I2C_SOFT_RESET					    0xc01c
-
-/****************************************/
-/* GPP Interface Registers		*/
-/****************************************/
-
-#define MV64460_GPP_IO_CONTROL					    0xf100
-#define MV64460_GPP_LEVEL_CONTROL				    0xf110
-#define MV64460_GPP_VALUE					    0xf104
-#define MV64460_GPP_INTERRUPT_CAUSE				    0xf108
-#define MV64460_GPP_INTERRUPT_MASK0				    0xf10c
-#define MV64460_GPP_INTERRUPT_MASK1				    0xf114
-#define MV64460_GPP_VALUE_SET					    0xf118
-#define MV64460_GPP_VALUE_CLEAR					    0xf11c
-
-/****************************************/
-/* Interrupt Controller Registers	*/
-/****************************************/
-
-/****************************************/
-/* Interrupts				*/
-/****************************************/
-
-#define MV64460_MAIN_INTERRUPT_CAUSE_LOW			    0x004
-#define MV64460_MAIN_INTERRUPT_CAUSE_HIGH			    0x00c
-#define MV64460_CPU_INTERRUPT0_MASK_LOW				    0x014
-#define MV64460_CPU_INTERRUPT0_MASK_HIGH			    0x01c
-#define MV64460_CPU_INTERRUPT0_SELECT_CAUSE			    0x024
-#define MV64460_CPU_INTERRUPT1_MASK_LOW				    0x034
-#define MV64460_CPU_INTERRUPT1_MASK_HIGH			    0x03c
-#define MV64460_CPU_INTERRUPT1_SELECT_CAUSE			    0x044
-#define MV64460_INTERRUPT0_MASK_0_LOW				    0x054
-#define MV64460_INTERRUPT0_MASK_0_HIGH				    0x05c
-#define MV64460_INTERRUPT0_SELECT_CAUSE				    0x064
-#define MV64460_INTERRUPT1_MASK_0_LOW				    0x074
-#define MV64460_INTERRUPT1_MASK_0_HIGH				    0x07c
-#define MV64460_INTERRUPT1_SELECT_CAUSE				    0x084
-
-/****************************************/
-/*	MPP Interface Registers		*/
-/****************************************/
-
-#define MV64460_MPP_CONTROL0					    0xf000
-#define MV64460_MPP_CONTROL1					    0xf004
-#define MV64460_MPP_CONTROL2					    0xf008
-#define MV64460_MPP_CONTROL3					    0xf00c
-
-/****************************************/
-/*    Serial Initialization registers	*/
-/****************************************/
-
-#define MV64460_SERIAL_INIT_LAST_DATA				    0xf324
-#define MV64460_SERIAL_INIT_CONTROL				    0xf328
-#define MV64460_SERIAL_INIT_STATUS				    0xf32c
-
-
-#endif /* __INCgt64460rh */
diff --git a/board/Marvell/db64460/pci.c b/board/Marvell/db64460/pci.c
deleted file mode 100644
index 8c25198e3b2..00000000000
--- a/board/Marvell/db64460/pci.c
+++ /dev/null
@@ -1,923 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/* PCI.c - PCI functions */
-
-
-#include <common.h>
-#include <pci.h>
-
-#include "../include/pci.h"
-
-#undef DEBUG
-#undef IDE_SET_NATIVE_MODE
-static unsigned int local_buses[] = { 0, 0 };
-
-static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
-	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
-	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
-};
-
-
-#ifdef DEBUG
-static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
-static void gt_pci_bus_mode_display (PCI_HOST host)
-{
-	unsigned int mode;
-
-
-	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
-	switch (mode) {
-	case 0:
-		printf ("PCI %d bus mode: Conventional PCI\n", host);
-		break;
-	case 1:
-		printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
-		break;
-	case 2:
-		printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
-		break;
-	case 3:
-		printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
-		break;
-	default:
-		printf ("Unknown BUS %d\n", mode);
-	}
-}
-#endif
-
-static const unsigned int pci_p2p_configuration_reg[] = {
-	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-static const unsigned int pci_configuration_address[] = {
-	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
-};
-
-static const unsigned int pci_configuration_data[] = {
-	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
-	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
-};
-
-static const unsigned int pci_error_cause_reg[] = {
-	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
-};
-
-static const unsigned int pci_arbiter_control[] = {
-	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
-};
-
-static const unsigned int pci_address_space_en[] = {
-	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
-};
-
-static const unsigned int pci_snoop_control_base_0_low[] = {
-	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_snoop_control_top_0[] = {
-	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
-};
-
-static const unsigned int pci_access_control_base_0_low[] = {
-	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_access_control_top_0[] = {
-	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
-};
-
-static const unsigned int pci_scs_bank_size[2][4] = {
-	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
-	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
-	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
-	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
-};
-
-static const unsigned int pci_p2p_configuration[] = {
-	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-
-/********************************************************************
-* pciWriteConfigReg - Write to a PCI configuration register
-*                    - Make sure the GT is configured as a master before writing
-*                      to another device on the PCI.
-*                    - The function takes care of Big/Little endian conversion.
-*
-*
-* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
-*                   (or any other PCI device spec)
-*           pciDevNum: The device number needs to be addressed.
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|00|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*********************************************************************/
-void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
-			unsigned int pciDevNum, unsigned int data)
-{
-	volatile unsigned int DataForAddrReg;
-	unsigned int functionNum;
-	unsigned int busNum = 0;
-	unsigned int addr;
-
-	if (pciDevNum > 32)	/* illegal device Number */
-		return;
-	if (pciDevNum == SELF) {	/* configure our configuration space. */
-		pciDevNum =
-			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
-			0x1f;
-		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
-			0xff0000;
-	}
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xfc;
-	DataForAddrReg =
-		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
-	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
-	GT_REG_READ (pci_configuration_address[host], &addr);
-	if (addr != DataForAddrReg)
-		return;
-	GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-/********************************************************************
-* pciReadConfigReg  - Read from a PCI0 configuration register
-*                    - Make sure the GT is configured as a master before reading
-*                     from another device on the PCI.
-*                   - The function takes care of Big/Little endian conversion.
-* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
-*                        spec)
-*           pciDevNum: The device number needs to be addressed.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-*                 cause register to make sure the data is valid
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|00|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*********************************************************************/
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
-			       unsigned int pciDevNum)
-{
-	volatile unsigned int DataForAddrReg;
-	unsigned int data;
-	unsigned int functionNum;
-	unsigned int busNum = 0;
-
-	if (pciDevNum > 32)	/* illegal device Number */
-		return 0xffffffff;
-	if (pciDevNum == SELF) {	/* configure our configuration space. */
-		pciDevNum =
-			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
-			0x1f;
-		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
-			0xff0000;
-	}
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xfc;
-	DataForAddrReg =
-		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
-	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
-	GT_REG_READ (pci_configuration_address[host], &data);
-	if (data != DataForAddrReg)
-		return 0xffffffff;
-	GT_REG_READ (pci_configuration_data[host], &data);
-	return data;
-}
-
-/********************************************************************
-* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
-*                               the agent is placed on another Bus. For more
-*                               information read P2P in the PCI spec.
-*
-* Inputs:   unsigned int regOffset - The register offset as it apears in the
-*           GT spec (or any other PCI device spec).
-*           unsigned int pciDevNum - The device number needs to be addressed.
-*           unsigned int busNum - On which bus does the Target agent connect
-*                                 to.
-*           unsigned int data - data to be written.
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|01|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
-*   PCI spec referring to P2P.
-*
-*********************************************************************/
-void pciOverBridgeWriteConfigReg (PCI_HOST host,
-				  unsigned int regOffset,
-				  unsigned int pciDevNum,
-				  unsigned int busNum, unsigned int data)
-{
-	unsigned int DataForReg;
-	unsigned int functionNum;
-
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xff;
-	busNum = busNum << 16;
-	if (pciDevNum == SELF) {	/* This board */
-		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
-	} else {
-		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
-			BIT31 | BIT0;
-	}
-	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
-	GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-
-/********************************************************************
-* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
-*                               the agent target locate on another PCI bus.
-*                             - Make sure the GT is configured as a master
-*                               before reading from another device on the PCI.
-*                             - The function takes care of Big/Little endian
-*                               conversion.
-* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
-*                        spec). (configuration register offset.)
-*           pciDevNum: The device number needs to be addressed.
-*           busNum: the Bus number where the agent is place.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-*                 cause register to make sure the data is valid
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|01|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*********************************************************************/
-unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
-					 unsigned int regOffset,
-					 unsigned int pciDevNum,
-					 unsigned int busNum)
-{
-	unsigned int DataForReg;
-	unsigned int data;
-	unsigned int functionNum;
-
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xff;
-	busNum = busNum << 16;
-	if (pciDevNum == SELF) {	/* This board */
-		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
-	} else {		/* agent on another bus */
-
-		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
-			BIT0 | BIT31;
-	}
-	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
-	GT_REG_READ (pci_configuration_data[host], &data);
-	return data;
-}
-
-
-/********************************************************************
-* pciGetRegOffset - Gets the register offset for this region config.
-*
-* INPUT:   Bus, Region - The bus and region we ask for its base address.
-* OUTPUT:   N/A
-* RETURNS: PCI register base address
-*********************************************************************/
-static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
-{
-	switch (host) {
-	case PCI_HOST0:
-		switch (region) {
-		case PCI_IO:
-			return PCI_0I_O_LOW_DECODE_ADDRESS;
-		case PCI_REGION0:
-			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-		case PCI_REGION1:
-			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
-		case PCI_REGION2:
-			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
-		case PCI_REGION3:
-			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
-		}
-	case PCI_HOST1:
-		switch (region) {
-		case PCI_IO:
-			return PCI_1I_O_LOW_DECODE_ADDRESS;
-		case PCI_REGION0:
-			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
-		case PCI_REGION1:
-			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
-		case PCI_REGION2:
-			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
-		case PCI_REGION3:
-			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
-		}
-	}
-	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-}
-
-static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
-{
-	switch (host) {
-	case PCI_HOST0:
-		switch (region) {
-		case PCI_IO:
-			return PCI_0I_O_ADDRESS_REMAP;
-		case PCI_REGION0:
-			return PCI_0MEMORY0_ADDRESS_REMAP;
-		case PCI_REGION1:
-			return PCI_0MEMORY1_ADDRESS_REMAP;
-		case PCI_REGION2:
-			return PCI_0MEMORY2_ADDRESS_REMAP;
-		case PCI_REGION3:
-			return PCI_0MEMORY3_ADDRESS_REMAP;
-		}
-	case PCI_HOST1:
-		switch (region) {
-		case PCI_IO:
-			return PCI_1I_O_ADDRESS_REMAP;
-		case PCI_REGION0:
-			return PCI_1MEMORY0_ADDRESS_REMAP;
-		case PCI_REGION1:
-			return PCI_1MEMORY1_ADDRESS_REMAP;
-		case PCI_REGION2:
-			return PCI_1MEMORY2_ADDRESS_REMAP;
-		case PCI_REGION3:
-			return PCI_1MEMORY3_ADDRESS_REMAP;
-		}
-	}
-	return PCI_0MEMORY0_ADDRESS_REMAP;
-}
-
-/********************************************************************
-* pciGetBaseAddress - Gets the base address of a PCI.
-*           - If the PCI size is 0 then this base address has no meaning!!!
-*
-*
-* INPUT:   Bus, Region - The bus and region we ask for its base address.
-* OUTPUT:   N/A
-* RETURNS: PCI base address.
-*********************************************************************/
-unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int regBase;
-	unsigned int regEnd;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &regBase);
-	GT_REG_READ (regOffset + 8, &regEnd);
-
-	if (regEnd <= regBase)
-		return 0xffffffff;	/* ERROR !!! */
-
-	regBase = regBase << 16;
-	return regBase;
-}
-
-bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
-		  unsigned int bankBase, unsigned int bankLength)
-{
-	unsigned int low = 0xfff;
-	unsigned int high = 0x0;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-	unsigned int remapOffset = pciGetRemapOffset (host, region);
-
-	if (bankLength != 0) {
-		low = (bankBase >> 16) & 0xffff;
-		high = ((bankBase + bankLength) >> 16) - 1;
-	}
-
-	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
-	GT_REG_WRITE (regOffset + 8, high);
-
-	if (bankLength != 0) {	/* must do AFTER writing maps */
-		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
-								   dont support upper 32
-								   in this driver */
-	}
-	return true;
-}
-
-unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int low;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &low);
-	return (low & 0xffff) << 16;
-}
-
-unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int low, high;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &low);
-	GT_REG_READ (regOffset + 8, &high);
-	return ((high & 0xffff) + 1) << 16;
-}
-
-
-/* ronen - 7/Dec/03*/
-/********************************************************************
-* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
-* Inputs: one of the PCI BAR
-*********************************************************************/
-void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
-	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
-	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-/********************************************************************
-* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
-*
-* Inputs: base and size of PCI SCS
-*********************************************************************/
-void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
-		       unsigned int pciDramBase, unsigned int pciDramSize)
-{
-	/*ronen different function for 3rd bank. */
-	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
-
-	pciDramBase = pciDramBase & 0xfffff000;
-	pciDramBase = pciDramBase | (pciReadConfigReg (host,
-						       PCI_SCS_0_BASE_ADDRESS
-						       + offset,
-						       SELF) & 0x00000fff);
-	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
-			   pciDramBase);
-	if (pciDramSize == 0)
-		pciDramSize++;
-	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
-	gtPciEnableInternalBAR (host, bank);
-}
-
-/********************************************************************
-* pciSetRegionFeatures - This function modifys one of the 8 regions with
-*                         feature bits given as an input.
-*                       - Be advised to check the spec before modifying them.
-* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
-*         unsigned int features - See file: pci.h there are defintion for those
-*                                 region features.
-*         unsigned int baseAddress - The region base Address.
-*         unsigned int topAddress - The region top Address.
-* Returns: false if one of the parameters is erroneous true otherwise.
-*********************************************************************/
-bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
-			   unsigned int features, unsigned int baseAddress,
-			   unsigned int regionLength)
-{
-	unsigned int accessLow;
-	unsigned int accessHigh;
-	unsigned int accessTop = baseAddress + regionLength;
-
-	if (regionLength == 0) {	/* close the region. */
-		pciDisableAccessRegion (host, region);
-		return true;
-	}
-	/* base Address is store is bits [11:0] */
-	accessLow = (baseAddress & 0xfff00000) >> 20;
-	/* All the features are update according to the defines in pci.h (to be on
-	   the safe side we disable bits: [11:0] */
-	accessLow = accessLow | (features & 0xfffff000);
-	/* write to the Low Access Region register */
-	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
-		      accessLow);
-
-	accessHigh = (accessTop & 0xfff00000) >> 20;
-
-	/* write to the High Access Region register */
-	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
-		      accessHigh - 1);
-	return true;
-}
-
-/********************************************************************
-* pciDisableAccessRegion - Disable The given Region by writing MAX size
-*                           to its low Address and MIN size to its high Address.
-*
-* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
-* Returns:  N/A.
-*********************************************************************/
-void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
-{
-	/* writing back the registers default values. */
-	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
-		      0x01001fff);
-	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
-}
-
-/********************************************************************
-* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
-*
-* Inputs:   N/A
-* Returns:  true.
-*********************************************************************/
-bool pciArbiterEnable (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
-	return true;
-}
-
-/********************************************************************
-* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
-*
-* Inputs:   N/A
-* Returns:  true
-*********************************************************************/
-bool pciArbiterDisable (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
-	return true;
-}
-
-/********************************************************************
-* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
-*
-* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
-*           PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
-*           PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
-*           PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
-*           PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
-*           PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
-*           PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
-* Returns:  true
-*********************************************************************/
-bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
-				  PCI_AGENT_PRIO externalAgent0,
-				  PCI_AGENT_PRIO externalAgent1,
-				  PCI_AGENT_PRIO externalAgent2,
-				  PCI_AGENT_PRIO externalAgent3,
-				  PCI_AGENT_PRIO externalAgent4,
-				  PCI_AGENT_PRIO externalAgent5)
-{
-	unsigned int regData;
-	unsigned int writeData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
-		(externalAgent1 << 9) + (externalAgent2 << 10) +
-		(externalAgent3 << 11) + (externalAgent4 << 12) +
-		(externalAgent5 << 13);
-	regData = (regData & 0xffffc07f) | writeData;
-	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
-	return true;
-}
-
-/********************************************************************
-* pciParkingDisable - Park on last option disable, with this function you can
-*                      disable the park on last mechanism for each agent.
-*                      disabling this option for all agents results parking
-*                      on the internal master.
-*
-* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
-*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
-*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
-*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
-*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
-*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
-*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
-* Returns:  true
-*********************************************************************/
-bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
-			PCI_AGENT_PARK externalAgent0,
-			PCI_AGENT_PARK externalAgent1,
-			PCI_AGENT_PARK externalAgent2,
-			PCI_AGENT_PARK externalAgent3,
-			PCI_AGENT_PARK externalAgent4,
-			PCI_AGENT_PARK externalAgent5)
-{
-	unsigned int regData;
-	unsigned int writeData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
-		(externalAgent1 << 16) + (externalAgent2 << 17) +
-		(externalAgent3 << 18) + (externalAgent4 << 19) +
-		(externalAgent5 << 20);
-	regData = (regData & ~(0x7f << 14)) | writeData;
-	GT_REG_WRITE (pci_arbiter_control[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
-*                       respond to grant assertion within a window specified in
-*                       the input value: 'brokenValue'.
-*
-* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
-*                       grant without asserting frame.
-* Returns:  Error for illegal broken value otherwise true.
-*********************************************************************/
-bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
-{
-	unsigned int data;
-	unsigned int regData;
-
-	if (brokenValue > 0xf)
-		return false;	/* brokenValue must be 4 bit */
-	data = brokenValue << 3;
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	regData = (regData & 0xffffff87) | data;
-	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
-	return true;
-}
-
-/********************************************************************
-* pciDisableBrokenAgentDetection - This function disable the Broken agent
-*                           Detection mechanism.
-*                           NOTE: This operation may cause a dead lock on the
-*                           pci0 arbitration.
-*
-* Inputs:   N/A
-* Returns:  true.
-*********************************************************************/
-bool pciDisableBrokenAgentDetection (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	regData = regData & 0xfffffffd;
-	GT_REG_WRITE (pci_arbiter_control[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciP2PConfig - This function set the PCI_n P2P configurate.
-*                 For more information on the P2P read PCI spec.
-*
-* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
-*                                      Boundry.
-*          unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
-*                                      Boundry.
-*          unsigned int busNum - The CPI bus number to which the PCI interface
-*                                      is connected.
-*          unsigned int devNum - The PCI interface's device number.
-*
-* Returns:  true.
-*********************************************************************/
-bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
-		   unsigned int SecondBusHigh,
-		   unsigned int busNum, unsigned int devNum)
-{
-	unsigned int regData;
-
-	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
-		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
-	GT_REG_WRITE (pci_p2p_configuration[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
-*                          supports Cache Coherency in the PCI_n interface.
-* Inputs: region - One of the four regions.
-*         snoopType - There is four optional Types:
-*                        1. No Snoop.
-*                        2. Snoop to WT region.
-*                        3. Snoop to WB region.
-*                        4. Snoop & Invalidate to WB region.
-*         baseAddress - Base Address of this region.
-*         regionLength - Region length.
-* Returns: false if one of the parameters is wrong otherwise return true.
-*********************************************************************/
-bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
-			    PCI_SNOOP_TYPE snoopType,
-			    unsigned int baseAddress,
-			    unsigned int regionLength)
-{
-	unsigned int snoopXbaseAddress;
-	unsigned int snoopXtopAddress;
-	unsigned int data;
-	unsigned int snoopHigh = baseAddress + regionLength;
-
-	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
-		return false;
-	snoopXbaseAddress =
-		pci_snoop_control_base_0_low[host] + 0x10 * region;
-	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
-	if (regionLength == 0) {	/* closing the region */
-		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
-		GT_REG_WRITE (snoopXtopAddress, 0);
-		return true;
-	}
-	baseAddress = baseAddress & 0xfff00000;	/* Granularity of 1MByte */
-	data = (baseAddress >> 20) | snoopType << 12;
-	GT_REG_WRITE (snoopXbaseAddress, data);
-	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
-	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
-	return true;
-}
-
-static int gt_read_config_dword (struct pci_controller *hose,
-				 pci_dev_t dev, int offset, u32 * value)
-{
-	int bus = PCI_BUS (dev);
-
-	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
-		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
-					   PCI_DEV (dev));
-	} else {
-		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
-						     cfg_addr, offset,
-						     PCI_DEV (dev), bus);
-	}
-
-	return 0;
-}
-
-static int gt_write_config_dword (struct pci_controller *hose,
-				  pci_dev_t dev, int offset, u32 value)
-{
-	int bus = PCI_BUS (dev);
-
-	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
-		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
-				   PCI_DEV (dev), value);
-	} else {
-		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
-					     offset, PCI_DEV (dev), bus,
-					     value);
-	}
-	return 0;
-}
-
-
-static void gt_setup_ide (struct pci_controller *hose,
-			  pci_dev_t dev, struct pci_config_table *entry)
-{
-	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
-	u32 bar_response, bar_value;
-	int bar;
-
-	for (bar = 0; bar < 6; bar++) {
-		/*ronen different function for 3rd bank. */
-		unsigned int offset =
-			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
-
-		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
-					0x0);
-		pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
-				       &bar_response);
-
-		pciauto_region_allocate (bar_response &
-					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
-					 pci_io : hose->pci_mem, ide_bar[bar],
-					 &bar_value);
-
-		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
-					bar_value);
-	}
-}
-
-
-/* TODO BJW: Change this for DB64360. This was pulled from the EV64260  */
-/* and is curently not called *. */
-#if 0
-static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
-{
-	unsigned char pin, irq;
-
-	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
-
-	if (pin == 1) {		/* only allow INT A */
-		irq = pci_irq_swizzle[(PCI_HOST) hose->
-				      cfg_addr][PCI_DEV (dev)];
-		if (irq)
-			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
-	}
-}
-#endif
-
-struct pci_config_table gt_config_table[] = {
-	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
-	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
-
-	{}
-};
-
-struct pci_controller pci0_hose = {
-/*    fixup_irq: gt_fixup_irq, */
-	config_table:gt_config_table,
-};
-
-struct pci_controller pci1_hose = {
-/*    fixup_irq: gt_fixup_irq, */
-	config_table:gt_config_table,
-};
-
-void pci_init_board (void)
-{
-	unsigned int command;
-
-#ifdef DEBUG
-	gt_pci_bus_mode_display (PCI_HOST0);
-#endif
-
-	pci0_hose.first_busno = 0;
-	pci0_hose.last_busno = 0xff;
-	local_buses[0] = pci0_hose.first_busno;
-
-	/* PCI memory space */
-	pci_set_region (pci0_hose.regions + 0,
-			CONFIG_SYS_PCI0_0_MEM_SPACE,
-			CONFIG_SYS_PCI0_0_MEM_SPACE,
-			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region (pci0_hose.regions + 1,
-			CONFIG_SYS_PCI0_IO_SPACE_PCI,
-			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
-
-	pci_set_ops (&pci0_hose,
-		     pci_hose_read_config_byte_via_dword,
-		     pci_hose_read_config_word_via_dword,
-		     gt_read_config_dword,
-		     pci_hose_write_config_byte_via_dword,
-		     pci_hose_write_config_word_via_dword,
-		     gt_write_config_dword);
-	pci0_hose.region_count = 2;
-
-	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
-
-	pci_register_hose (&pci0_hose);
-	pciArbiterEnable (PCI_HOST0);
-	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
-	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MASTER;
-	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MEMORY;
-	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-
-	pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
-
-#ifdef DEBUG
-	gt_pci_bus_mode_display (PCI_HOST1);
-#endif
-	pci1_hose.first_busno = pci0_hose.last_busno + 1;
-	pci1_hose.last_busno = 0xff;
-	pci1_hose.current_busno = pci1_hose.first_busno;
-	local_buses[1] = pci1_hose.first_busno;
-
-	/* PCI memory space */
-	pci_set_region (pci1_hose.regions + 0,
-			CONFIG_SYS_PCI1_0_MEM_SPACE,
-			CONFIG_SYS_PCI1_0_MEM_SPACE,
-			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region (pci1_hose.regions + 1,
-			CONFIG_SYS_PCI1_IO_SPACE_PCI,
-			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
-
-	pci_set_ops (&pci1_hose,
-		     pci_hose_read_config_byte_via_dword,
-		     pci_hose_read_config_word_via_dword,
-		     gt_read_config_dword,
-		     pci_hose_write_config_byte_via_dword,
-		     pci_hose_write_config_word_via_dword,
-		     gt_write_config_dword);
-
-	pci1_hose.region_count = 2;
-
-	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
-
-	pci_register_hose (&pci1_hose);
-
-	pciArbiterEnable (PCI_HOST1);
-	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
-
-	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MASTER;
-	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-	pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
-
-	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MEMORY;
-	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-}
diff --git a/board/Marvell/db64460/sdram_init.c b/board/Marvell/db64460/sdram_init.c
deleted file mode 100644
index 71c2d9eb329..00000000000
--- a/board/Marvell/db64460/sdram_init.c
+++ /dev/null
@@ -1,1950 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*************************************************************************
- * adaption for the Marvell DB64460 Board
- * Ingo Assmus (ingo.assmus@keymile.com)
-  ************************************************************************/
-
-
-/* sdram_init.c - automatic memory sizing */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include "../include/memory.h"
-#include "../include/pci.h"
-#include "../include/mv_gen_reg.h"
-#include <net.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "../common/i2c.h"
-#include "64460.h"
-#include "mv_regs.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define	MAP_PCI
-
-int set_dfcdlInit (void);	/* setup delay line of Mv64460 */
-int mvDmaIsChannelActive (int);
-int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
-int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
-
-/* ------------------------------------------------------------------------- */
-
-int
-memory_map_bank (unsigned int bankNo,
-		 unsigned int bankBase, unsigned int bankLength)
-{
-#ifdef MAP_PCI
-	PCI_HOST host;
-#endif
-
-
-	if (bankLength > 0) {
-		debug("mapping bank %d at %08x - %08x\n",
-			bankNo, bankBase, bankBase + bankLength - 1);
-	} else {
-		debug("unmapping bank %d\n", bankNo);
-	}
-
-	memoryMapBank (bankNo, bankBase, bankLength);
-
-#ifdef MAP_PCI
-	for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
-		const int features =
-			PREFETCH_ENABLE |
-			DELAYED_READ_ENABLE |
-			AGGRESSIVE_PREFETCH |
-			READ_LINE_AGGRESSIVE_PREFETCH |
-			READ_MULTI_AGGRESSIVE_PREFETCH |
-			MAX_BURST_4 | PCI_NO_SWAP;
-
-		pciMapMemoryBank (host, bankNo, bankBase, bankLength);
-
-		pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
-				       bankLength);
-
-		pciSetRegionFeatures (host, bankNo, features, bankBase,
-				      bankLength);
-	}
-#endif
-	return 0;
-}
-
-#define GB         (1 << 30)
-
-/* much of this code is based on (or is) the code in the pip405 port */
-/* thanks go to the authors of said port - Josh */
-
-/* structure to store the relevant information about an sdram bank */
-typedef struct sdram_info {
-	uchar drb_size;
-	uchar registered, ecc;
-	uchar tpar;
-	uchar tras_clocks;
-	uchar burst_len;
-	uchar banks, slot;
-} sdram_info_t;
-
-/* Typedefs for 'gtAuxilGetDIMMinfo' function */
-
-typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE;
-
-typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
-	SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
-} VOLTAGE_INTERFACE;
-
-typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 =
-		4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 =
-		32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR;
-typedef enum _max_CL_supported_SD { SD_CL_1 =
-		1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7,
-		SD_FAULT } MAX_CL_SUPPORTED_SD;
-
-
-/* SDRAM/DDR information struct */
-typedef struct _gtMemoryDimmInfo {
-	MEMORY_TYPE memoryType;
-	unsigned int numOfRowAddresses;
-	unsigned int numOfColAddresses;
-	unsigned int numOfModuleBanks;
-	unsigned int dataWidth;
-	VOLTAGE_INTERFACE voltageInterface;
-	unsigned int errorCheckType;	/* ECC , PARITY.. */
-	unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
-	unsigned int errorCheckDataWidth;	/* 0 - no, 1 - Yes */
-	unsigned int minClkDelay;
-	unsigned int burstLengthSupported;
-	unsigned int numOfBanksOnEachDevice;
-	unsigned int suportedCasLatencies;
-	unsigned int RefreshInterval;
-	unsigned int maxCASlatencySupported_LoP;	/* LoP left of point (measured in ns) */
-	unsigned int maxCASlatencySupported_RoP;	/* RoP right of point (measured in ns) */
-	MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
-	MAX_CL_SUPPORTED_SD maxClSupported_SD;
-	unsigned int moduleBankDensity;
-	/* module attributes (true for yes) */
-	bool bufferedAddrAndControlInputs;
-	bool registeredAddrAndControlInputs;
-	bool onCardPLL;
-	bool bufferedDQMBinputs;
-	bool registeredDQMBinputs;
-	bool differentialClockInput;
-	bool redundantRowAddressing;
-
-	/* module general attributes */
-	bool suportedAutoPreCharge;
-	bool suportedPreChargeAll;
-	bool suportedEarlyRasPreCharge;
-	bool suportedWrite1ReadBurst;
-	bool suported5PercentLowVCC;
-	bool suported5PercentUpperVCC;
-	/* module timing parameters */
-	unsigned int minRasToCasDelay;
-	unsigned int minRowActiveRowActiveDelay;
-	unsigned int minRasPulseWidth;
-	unsigned int minRowPrechargeTime;	/* measured in ns */
-
-	int addrAndCommandHoldTime;	/* LoP left of point (measured in ns) */
-	int addrAndCommandSetupTime;	/* (measured in ns/100) */
-	int dataInputSetupTime;	/* LoP left of point (measured in ns) */
-	int dataInputHoldTime;	/* LoP left of point (measured in ns) */
-/* tAC times for highest 2nd and 3rd highest CAS Latency values */
-	unsigned int clockToDataOut_LoP;	/* LoP left of point (measured in ns) */
-	unsigned int clockToDataOut_RoP;	/* RoP right of point (measured in ns) */
-	unsigned int clockToDataOutMinus1_LoP;	/* LoP left of point (measured in ns) */
-	unsigned int clockToDataOutMinus1_RoP;	/* RoP right of point (measured in ns) */
-	unsigned int clockToDataOutMinus2_LoP;	/* LoP left of point (measured in ns) */
-	unsigned int clockToDataOutMinus2_RoP;	/* RoP right of point (measured in ns) */
-
-	unsigned int minimumCycleTimeAtMaxCasLatancy_LoP;	/* LoP left of point (measured in ns) */
-	unsigned int minimumCycleTimeAtMaxCasLatancy_RoP;	/* RoP right of point (measured in ns) */
-
-	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP;	/* LoP left of point (measured in ns) */
-	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP;	/* RoP right of point (measured in ns) */
-
-	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP;	/* LoP left of point (measured in ns) */
-	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP;	/* RoP right of point (measured in ns) */
-
-	/* Parameters calculated from
-	   the extracted DIMM information */
-	unsigned int size;
-	unsigned int deviceDensity;	/* 16,64,128,256 or 512 Mbit */
-	unsigned int numberOfDevices;
-	uchar drb_size;		/* DRAM size in n*64Mbit */
-	uchar slot;		/* Slot Number this module is inserted in */
-	uchar spd_raw_data[128];	/* Content of SPD-EEPROM copied 1:1 */
-#ifdef DEBUG
-	uchar manufactura[8];	/* Content of SPD-EEPROM Byte 64-71 */
-	uchar modul_id[18];	/* Content of SPD-EEPROM Byte 73-90 */
-	uchar vendor_data[27];	/* Content of SPD-EEPROM Byte 99-125 */
-	unsigned long modul_serial_no;	/* Content of SPD-EEPROM Byte 95-98 */
-	unsigned int manufac_date;	/* Content of SPD-EEPROM Byte 93-94 */
-	unsigned int modul_revision;	/* Content of SPD-EEPROM Byte 91-92 */
-	uchar manufac_place;	/* Content of SPD-EEPROM Byte 72 */
-
-#endif
-} AUX_MEM_DIMM_INFO;
-
-
-/*
- * translate ns.ns/10 coding of SPD timing values
- * into 10 ps unit values
- */
-static inline unsigned short NS10to10PS (unsigned char spd_byte)
-{
-	unsigned short ns, ns10;
-
-	/* isolate upper nibble */
-	ns = (spd_byte >> 4) & 0x0F;
-	/* isolate lower nibble */
-	ns10 = (spd_byte & 0x0F);
-
-	return (ns * 100 + ns10 * 10);
-}
-
-/*
- * translate ns coding of SPD timing values
- * into 10 ps unit values
- */
-static inline unsigned short NSto10PS (unsigned char spd_byte)
-{
-	return (spd_byte * 100);
-}
-
-/* This code reads the SPD chip on the sdram and populates
- * the array which is passed in with the relevant information */
-/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
-static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
-{
-	unsigned long spd_checksum;
-
-#ifdef ZUMA_NTL
-	/* zero all the values */
-	memset (info, 0, sizeof (*info));
-
-/*
-	if (!slot) {
-	    info->slot = 0;
-	    info->banks = 1;
-	    info->registered = 0;
-		    info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */
-/*	    info->tpar = 3;
-	    info->tras_clocks = 5;
-	    info->burst_len = 4;
-*/
-#ifdef CONFIG_MV64460_ECC
-	/* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
-	dimmInfo->errorCheckType = 2;
-/*	    info->ecc = 2;*/
-#endif
-}
-
-return 0;
-
-#else
-	uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
-	int ret;
-	unsigned int i, j, density = 1;
-
-#ifdef DEBUG
-	unsigned int k;
-#endif
-	unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
-	int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
-	uchar supp_cal, cal_val;
-	ulong memclk, tmemclk;
-	ulong tmp;
-	uchar trp_clocks = 0, tras_clocks;
-	uchar data[128];
-
-	memclk = gd->bus_clk;
-	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */
-
-	debug("before i2c read\n");
-
-	ret = i2c_read (addr, 0, 1, data, 128);
-
-	debug("after i2c read\n");
-
-	/* zero all the values */
-	memset (dimmInfo, 0, sizeof (*dimmInfo));
-
-	/* copy the SPD content 1:1 into the dimmInfo structure */
-	for (i = 0; i <= 127; i++) {
-		dimmInfo->spd_raw_data[i] = data[i];
-	}
-
-	if (ret) {
-		debug("No DIMM in slot %d [err = %x]\n", slot, ret);
-		return 0;
-	} else
-		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
-
-#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
-
-	for (i = 0; i <= 127; i++) {
-		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
-			data[i]);
-	}
-
-#endif
-#ifdef DEBUG
-/* find Manufactura of Dimm Module */
-	for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
-		dimmInfo->manufactura[i] = data[64 + i];
-	}
-	printf ("\nThis RAM-Module is produced by: 		%s\n",
-		dimmInfo->manufactura);
-
-/* find Manul-ID of Dimm Module */
-	for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
-		dimmInfo->modul_id[i] = data[73 + i];
-	}
-	printf ("The Module-ID of this RAM-Module is: 		%s\n",
-		dimmInfo->modul_id);
-
-/* find Vendor-Data of Dimm Module */
-	for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
-		dimmInfo->vendor_data[i] = data[99 + i];
-	}
-	printf ("Vendor Data of this RAM-Module is: 		%s\n",
-		dimmInfo->vendor_data);
-
-/* find modul_serial_no of Dimm Module */
-	dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
-	printf ("Serial No. of this RAM-Module is: 		%ld (%lx)\n",
-		dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
-
-/* find Manufac-Data of Dimm Module */
-	dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
-	printf ("Manufactoring Date of this RAM-Module is: 	%d.%d\n", data[93], data[94]);	/*dimmInfo->manufac_date */
-
-/* find modul_revision of Dimm Module */
-	dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
-	printf ("Module Revision of this RAM-Module is: 		%d.%d\n", data[91], data[92]);	/* dimmInfo->modul_revision */
-
-/* find manufac_place of Dimm Module */
-	dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
-	printf ("manufac_place of this RAM-Module is: 		%d\n",
-		dimmInfo->manufac_place);
-
-#endif
-
-/*------------------------------------------------------------------------------------------------------------------------------*/
-/* calculate SPD checksum */
-/*------------------------------------------------------------------------------------------------------------------------------*/
-	spd_checksum = 0;
-
-	for (i = 0; i <= 62; i++) {
-		spd_checksum += data[i];
-	}
-
-	if ((spd_checksum & 0xff) != data[63]) {
-		printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
-		hang ();
-	}
-
-	else
-		printf ("SPD Checksum ok!\n");
-
-
-/*------------------------------------------------------------------------------------------------------------------------------*/
-	for (i = 2; i <= 35; i++) {
-		switch (i) {
-		case 2:	/* Memory type (DDR / SDRAM) */
-			dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
-#ifdef DEBUG
-			if (dimmInfo->memoryType == 0)
-				debug
-				    ("Dram_type in slot %d is: 			SDRAM\n",
-				     dimmInfo->slot);
-			if (dimmInfo->memoryType == 1)
-				debug
-				    ("Dram_type in slot %d is: 			DDRAM\n",
-				     dimmInfo->slot);
-#endif
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 3:	/* Number Of Row Addresses */
-			dimmInfo->numOfRowAddresses = data[i];
-			debug
-			    ("Module Number of row addresses: 		%d\n",
-			     dimmInfo->numOfRowAddresses);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 4:	/* Number Of Column Addresses */
-			dimmInfo->numOfColAddresses = data[i];
-			debug
-			    ("Module Number of col addresses: 		%d\n",
-			     dimmInfo->numOfColAddresses);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 5:	/* Number Of Module Banks */
-			dimmInfo->numOfModuleBanks = data[i];
-			debug
-			    ("Number of Banks on Mod. : 				%d\n",
-			     dimmInfo->numOfModuleBanks);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 6:	/* Data Width */
-			dimmInfo->dataWidth = data[i];
-			debug
-			    ("Module Data Width: 				%d\n",
-			     dimmInfo->dataWidth);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 8:	/* Voltage Interface */
-			switch (data[i]) {
-			case 0x0:
-				dimmInfo->voltageInterface = TTL_5V_TOLERANT;
-				debug
-				    ("Module is 					TTL_5V_TOLERANT\n");
-				break;
-			case 0x1:
-				dimmInfo->voltageInterface = LVTTL;
-				debug
-				    ("Module is 					LVTTL\n");
-				break;
-			case 0x2:
-				dimmInfo->voltageInterface = HSTL_1_5V;
-				debug
-				    ("Module is 					TTL_5V_TOLERANT\n");
-				break;
-			case 0x3:
-				dimmInfo->voltageInterface = SSTL_3_3V;
-				debug
-				    ("Module is 					HSTL_1_5V\n");
-				break;
-			case 0x4:
-				dimmInfo->voltageInterface = SSTL_2_5V;
-				debug
-				    ("Module is 					SSTL_2_5V\n");
-				break;
-			default:
-				dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
-				debug
-				    ("Module is 					VOLTAGE_UNKNOWN\n");
-				break;
-			}
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 9:	/* Minimum Cycle Time At Max CasLatancy */
-			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
-			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
-			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
-			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
-				leftOfPoint;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
-				rightOfPoint;
-			debug
-			    ("Minimum Cycle Time At Max CasLatancy: 		%d.%d [ns]\n",
-			     leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 10:	/* Clock To Data Out */
-			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
-			time_tmp =
-				(((data[i] & 0xf0) >> 4) * 10) +
-				((data[i] & 0x0f));
-			leftOfPoint = time_tmp / div;
-			rightOfPoint = time_tmp % div;
-			dimmInfo->clockToDataOut_LoP = leftOfPoint;
-			dimmInfo->clockToDataOut_RoP = rightOfPoint;
-			debug("Clock To Data Out: 				%d.%2d [ns]\n", leftOfPoint, rightOfPoint);	/*dimmInfo->clockToDataOut */
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-/*#ifdef CONFIG_ECC */
-		case 11:	/* Error Check Type */
-			dimmInfo->errorCheckType = data[i];
-			debug
-			    ("Error Check Type (0=NONE): 			%d\n",
-			     dimmInfo->errorCheckType);
-			break;
-/* #endif */
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 12:	/* Refresh Interval */
-			dimmInfo->RefreshInterval = data[i];
-			debug
-			    ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
-			     dimmInfo->RefreshInterval);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 13:	/* Sdram Width */
-			dimmInfo->sdramWidth = data[i];
-			debug
-			    ("Sdram Width: 					%d\n",
-			     dimmInfo->sdramWidth);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 14:	/* Error Check Data Width */
-			dimmInfo->errorCheckDataWidth = data[i];
-			debug
-			    ("Error Check Data Width: 			%d\n",
-			     dimmInfo->errorCheckDataWidth);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 15:	/* Minimum Clock Delay */
-			dimmInfo->minClkDelay = data[i];
-			debug
-			    ("Minimum Clock Delay: 				%d\n",
-			     dimmInfo->minClkDelay);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 16:	/* Burst Length Supported */
-			   /******-******-******-*******
-			   * bit3 | bit2 | bit1 | bit0 *
-			   *******-******-******-*******
-	    burst length = *  8   |  4   |   2  |   1  *
-			   *****************************
-
-	    If for example bit0 and bit2 are set, the burst
-	    length supported are 1 and 4. */
-
-			dimmInfo->burstLengthSupported = data[i];
-#ifdef DEBUG
-			debug
-			    ("Burst Length Supported: 			");
-			if (dimmInfo->burstLengthSupported & 0x01)
-				debug("1, ");
-			if (dimmInfo->burstLengthSupported & 0x02)
-				debug("2, ");
-			if (dimmInfo->burstLengthSupported & 0x04)
-				debug("4, ");
-			if (dimmInfo->burstLengthSupported & 0x08)
-				debug("8, ");
-			debug(" Bit \n");
-#endif
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 17:	/* Number Of Banks On Each Device */
-			dimmInfo->numOfBanksOnEachDevice = data[i];
-			debug
-			    ("Number Of Banks On Each Chip: 			%d\n",
-			     dimmInfo->numOfBanksOnEachDevice);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 18:	/* Suported Cas Latencies */
-
-			/*     DDR:
-			 *******-******-******-******-******-******-******-*******
-			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
-			 *******-******-******-******-******-******-******-*******
-			 CAS =   * TBD  | TBD  | 3.5  |   3  | 2.5  |  2   | 1.5  |   1  *
-			 *********************************************************
-			 SDRAM:
-			 *******-******-******-******-******-******-******-*******
-			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
-			 *******-******-******-******-******-******-******-*******
-			 CAS =   * TBD  |  7   |  6   |  5   |  4   |  3   |   2  |   1  *
-			 ********************************************************/
-			dimmInfo->suportedCasLatencies = data[i];
-#ifdef DEBUG
-			debug
-			    ("Suported Cas Latencies: (CL) 			");
-			if (dimmInfo->memoryType == 0) {	/* SDRAM */
-				for (k = 0; k <= 7; k++) {
-					if (dimmInfo->
-					    suportedCasLatencies & (1 << k))
-						debug
-						    ("%d, 			",
-						     k + 1);
-				}
-
-			} else {	/* DDR-RAM */
-
-				if (dimmInfo->suportedCasLatencies & 1)
-					debug("1, ");
-				if (dimmInfo->suportedCasLatencies & 2)
-					debug("1.5, ");
-				if (dimmInfo->suportedCasLatencies & 4)
-					debug("2, ");
-				if (dimmInfo->suportedCasLatencies & 8)
-					debug("2.5, ");
-				if (dimmInfo->suportedCasLatencies & 16)
-					debug("3, ");
-				if (dimmInfo->suportedCasLatencies & 32)
-					debug("3.5, ");
-
-			}
-			debug("\n");
-#endif
-			/* Calculating MAX CAS latency */
-			for (j = 7; j > 0; j--) {
-				if (((dimmInfo->
-				      suportedCasLatencies >> j) & 0x1) ==
-				    1) {
-					switch (dimmInfo->memoryType) {
-					case DDR:
-						/* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
-						switch (j) {
-						case 7:
-							debug
-							    ("Max. Cas Latencies (DDR): 			ERROR !!!\n");
-							dimmInfo->
-								maxClSupported_DDR
-								=
-								DDR_CL_FAULT;
-							hang ();
-							break;
-						case 6:
-							debug
-							    ("Max. Cas Latencies (DDR): 			ERROR !!!\n");
-							dimmInfo->
-								maxClSupported_DDR
-								=
-								DDR_CL_FAULT;
-							hang ();
-							break;
-						case 5:
-							debug
-							    ("Max. Cas Latencies (DDR): 			3.5 clk's\n");
-							dimmInfo->
-								maxClSupported_DDR
-								= DDR_CL_3_5;
-							break;
-						case 4:
-							debug
-							    ("Max. Cas Latencies (DDR): 			3 clk's \n");
-							dimmInfo->
-								maxClSupported_DDR
-								= DDR_CL_3;
-							break;
-						case 3:
-							debug
-							    ("Max. Cas Latencies (DDR): 			2.5 clk's \n");
-							dimmInfo->
-								maxClSupported_DDR
-								= DDR_CL_2_5;
-							break;
-						case 2:
-							debug
-							    ("Max. Cas Latencies (DDR): 			2 clk's \n");
-							dimmInfo->
-								maxClSupported_DDR
-								= DDR_CL_2;
-							break;
-						case 1:
-							debug
-							    ("Max. Cas Latencies (DDR): 			1.5 clk's \n");
-							dimmInfo->
-								maxClSupported_DDR
-								= DDR_CL_1_5;
-							break;
-						}
-
-						/* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy
-						   lower then our SDRAM cycle count, we won't be able to support this CAL
-						   and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */
-						if ((dimmInfo->
-						     minimumCycleTimeAtMaxCasLatancy_LoP
-						     <
-						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
-						    ||
-						    ((dimmInfo->
-						      minimumCycleTimeAtMaxCasLatancy_LoP
-						      ==
-						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
-						     && (dimmInfo->
-							 minimumCycleTimeAtMaxCasLatancy_RoP
-							 <
-							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
-						{
-							dimmInfo->
-								maxClSupported_DDR
-								=
-								dimmInfo->
-								maxClSupported_DDR
-								>> 1;
-							debug
-							    ("*** Change actual Cas Latencies cause of minimumCycleTime n");
-						}
-						/* ronen - checkif the Dimm frequency compared to the Sysclock. */
-						if ((dimmInfo->
-						     minimumCycleTimeAtMaxCasLatancy_LoP
-						     >
-						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
-						    ||
-						    ((dimmInfo->
-						      minimumCycleTimeAtMaxCasLatancy_LoP
-						      ==
-						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
-						     && (dimmInfo->
-							 minimumCycleTimeAtMaxCasLatancy_RoP
-							 >
-							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
-						{
-							printf ("*********************************************************\n");
-							printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
-							printf ("*********************************************************\n");
-							hang ();
-						}
-
-						dimmInfo->
-							maxCASlatencySupported_LoP
-							=
-							1 +
-							(int) (5 * j / 10);
-						if (((5 * j) % 10) != 0)
-							dimmInfo->
-								maxCASlatencySupported_RoP
-								= 5;
-						else
-							dimmInfo->
-								maxCASlatencySupported_RoP
-								= 0;
-						debug
-						    ("Max. Cas Latencies (DDR LoP.RoP Notation): 	%d.%d \n",
-						     dimmInfo->
-						     maxCASlatencySupported_LoP,
-						     dimmInfo->
-						     maxCASlatencySupported_RoP);
-						break;
-					case SDRAM:
-						/* CAS latency 1, 2, 3, 4, 5, 6, 7 */
-						dimmInfo->maxClSupported_SD = j;	/*  Cas Latency DDR-RAM Coded                   */
-						debug
-						    ("Max. Cas Latencies (SD): %d\n",
-						     dimmInfo->
-						     maxClSupported_SD);
-						dimmInfo->
-							maxCASlatencySupported_LoP
-							= j;
-						dimmInfo->
-							maxCASlatencySupported_RoP
-							= 0;
-						debug
-						    ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
-						     dimmInfo->
-						     maxCASlatencySupported_LoP,
-						     dimmInfo->
-						     maxCASlatencySupported_RoP);
-						break;
-					}
-					break;
-				}
-			}
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 21:	/* Buffered Address And Control Inputs */
-			debug("\nModul Attributes (SPD Byte 21): \n");
-			dimmInfo->bufferedAddrAndControlInputs =
-				data[i] & BIT0;
-			dimmInfo->registeredAddrAndControlInputs =
-				(data[i] & BIT1) >> 1;
-			dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
-			dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
-			dimmInfo->registeredDQMBinputs =
-				(data[i] & BIT4) >> 4;
-			dimmInfo->differentialClockInput =
-				(data[i] & BIT5) >> 5;
-			dimmInfo->redundantRowAddressing =
-				(data[i] & BIT6) >> 6;
-#ifdef DEBUG
-			if (dimmInfo->bufferedAddrAndControlInputs == 1)
-				debug
-				    (" - Buffered Address/Control Input:		Yes \n");
-			else
-				debug
-				    (" - Buffered Address/Control Input:		No \n");
-
-			if (dimmInfo->registeredAddrAndControlInputs == 1)
-				debug
-				    (" - Registered Address/Control Input:		Yes \n");
-			else
-				debug
-				    (" - Registered Address/Control Input:		No \n");
-
-			if (dimmInfo->onCardPLL == 1)
-				debug
-				    (" - On-Card PLL (clock):				Yes \n");
-			else
-				debug
-				    (" - On-Card PLL (clock):				No \n");
-
-			if (dimmInfo->bufferedDQMBinputs == 1)
-				debug
-				    (" - Bufferd DQMB Inputs:				Yes \n");
-			else
-				debug
-				    (" - Bufferd DQMB Inputs:				No \n");
-
-			if (dimmInfo->registeredDQMBinputs == 1)
-				debug
-				    (" - Registered DQMB Inputs:			Yes \n");
-			else
-				debug
-				    (" - Registered DQMB Inputs:			No \n");
-
-			if (dimmInfo->differentialClockInput == 1)
-				debug
-				    (" - Differential Clock Input:			Yes \n");
-			else
-				debug
-				    (" - Differential Clock Input:			No \n");
-
-			if (dimmInfo->redundantRowAddressing == 1)
-				debug
-				    (" - redundant Row Addressing:			Yes \n");
-			else
-				debug
-				    (" - redundant Row Addressing:			No \n");
-
-#endif
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 22:	/* Suported AutoPreCharge */
-			debug("\nModul Attributes (SPD Byte 22): \n");
-			dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
-			dimmInfo->suportedAutoPreCharge =
-				(data[i] & BIT1) >> 1;
-			dimmInfo->suportedPreChargeAll =
-				(data[i] & BIT2) >> 2;
-			dimmInfo->suportedWrite1ReadBurst =
-				(data[i] & BIT3) >> 3;
-			dimmInfo->suported5PercentLowVCC =
-				(data[i] & BIT4) >> 4;
-			dimmInfo->suported5PercentUpperVCC =
-				(data[i] & BIT5) >> 5;
-#ifdef DEBUG
-			if (dimmInfo->suportedEarlyRasPreCharge == 1)
-				debug
-				    (" - Early Ras Precharge:			Yes \n");
-			else
-				debug
-				    (" -  Early Ras Precharge:			No \n");
-
-			if (dimmInfo->suportedAutoPreCharge == 1)
-				debug
-				    (" - AutoPreCharge:				Yes \n");
-			else
-				debug
-				    (" -  AutoPreCharge:				No \n");
-
-			if (dimmInfo->suportedPreChargeAll == 1)
-				debug
-				    (" - Precharge All:				Yes \n");
-			else
-				debug
-				    (" -  Precharge All:				No \n");
-
-			if (dimmInfo->suportedWrite1ReadBurst == 1)
-				debug
-				    (" - Write 1/ReadBurst:				Yes \n");
-			else
-				debug
-				    (" -  Write 1/ReadBurst:				No \n");
-
-			if (dimmInfo->suported5PercentLowVCC == 1)
-				debug
-				    (" - lower VCC tolerance:			5 Percent \n");
-			else
-				debug
-				    ("  - lower VCC tolerance:			10 Percent \n");
-
-			if (dimmInfo->suported5PercentUpperVCC == 1)
-				debug
-				    (" - upper VCC tolerance:			5 Percent \n");
-			else
-				debug
-				    (" -  upper VCC tolerance:			10 Percent \n");
-
-#endif
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 23:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
-			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
-			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
-			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
-			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
-				leftOfPoint;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
-				rightOfPoint;
-			debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint);	/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 24:	/* Clock To Data Out 2nd highest Cas Latency Value */
-			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
-			time_tmp =
-				(((data[i] & 0xf0) >> 4) * 10) +
-				((data[i] & 0x0f));
-			leftOfPoint = time_tmp / div;
-			rightOfPoint = time_tmp % div;
-			dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
-			dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
-			debug
-			    ("Clock To Data Out (2nd CL value): 		%d.%2d [ns]\n",
-			     leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 25:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
-			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
-			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
-			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
-			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
-				leftOfPoint;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
-				rightOfPoint;
-			debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint);	/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 26:	/* Clock To Data Out 3rd highest Cas Latency Value */
-			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
-			time_tmp =
-				(((data[i] & 0xf0) >> 4) * 10) +
-				((data[i] & 0x0f));
-			leftOfPoint = time_tmp / div;
-			rightOfPoint = time_tmp % div;
-			dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
-			dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
-			debug
-			    ("Clock To Data Out (3rd CL value): 		%d.%2d [ns]\n",
-			     leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 27:	/* Minimum Row Precharge Time */
-			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
-			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
-			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
-			dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint);	/* measured in n times 10ps Intervals */
-			trp_clocks =
-				(dimmInfo->minRowPrechargeTime +
-				 (tmemclk - 1)) / tmemclk;
-			debug
-			    ("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
-			     tmemclk, tmemclk / 100, tmemclk % 100);
-			debug
-			    ("Minimum Row Precharge Time [ns]: 		%d.%2d = in Clk cycles %d\n",
-			     leftOfPoint, rightOfPoint, trp_clocks);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 28:	/* Minimum Row Active to Row Active Time */
-			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
-			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
-			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
-			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
-			debug
-			    ("Minimum Row Active -To- Row Active Delay [ns]: 	%d.%2d = in Clk cycles %d\n",
-			     leftOfPoint, rightOfPoint, trp_clocks);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 29:	/* Minimum Ras-To-Cas Delay */
-			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
-			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
-			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
-			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
-			debug
-			    ("Minimum Ras-To-Cas Delay [ns]: 			%d.%2d = in Clk cycles %d\n",
-			     leftOfPoint, rightOfPoint, trp_clocks);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 30:	/* Minimum Ras Pulse Width */
-			dimmInfo->minRasPulseWidth = data[i];
-			tras_clocks =
-				(NSto10PS (data[i]) +
-				 (tmemclk - 1)) / tmemclk;
-			debug
-			    ("Minimum Ras Pulse Width [ns]: 			%d = in Clk cycles %d\n",
-			     dimmInfo->minRasPulseWidth, tras_clocks);
-
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 31:	/* Module Bank Density */
-			dimmInfo->moduleBankDensity = data[i];
-			debug
-			    ("Module Bank Density: 				%d\n",
-			     dimmInfo->moduleBankDensity);
-#ifdef DEBUG
-			debug
-			    ("*** Offered Densities (more than 1 = Multisize-Module): ");
-			{
-				if (dimmInfo->moduleBankDensity & 1)
-					debug("4MB, ");
-				if (dimmInfo->moduleBankDensity & 2)
-					debug("8MB, ");
-				if (dimmInfo->moduleBankDensity & 4)
-					debug("16MB, ");
-				if (dimmInfo->moduleBankDensity & 8)
-					debug("32MB, ");
-				if (dimmInfo->moduleBankDensity & 16)
-					debug("64MB, ");
-				if (dimmInfo->moduleBankDensity & 32)
-					debug("128MB, ");
-				if ((dimmInfo->moduleBankDensity & 64)
-				    || (dimmInfo->moduleBankDensity & 128)) {
-					debug("ERROR, ");
-					hang ();
-				}
-			}
-			debug("\n");
-#endif
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 32:	/* Address And Command Setup Time (measured in ns/1000) */
-			sign = 1;
-			switch (dimmInfo->memoryType) {
-			case DDR:
-				time_tmp =
-					(((data[i] & 0xf0) >> 4) * 10) +
-					((data[i] & 0x0f));
-				leftOfPoint = time_tmp / 100;
-				rightOfPoint = time_tmp % 100;
-				break;
-			case SDRAM:
-				leftOfPoint = (data[i] & 0xf0) >> 4;
-				if (leftOfPoint > 7) {
-					leftOfPoint = data[i] & 0x70 >> 4;
-					sign = -1;
-				}
-				rightOfPoint = (data[i] & 0x0f);
-				break;
-			}
-			dimmInfo->addrAndCommandSetupTime =
-				(leftOfPoint * 100 + rightOfPoint) * sign;
-			debug
-			    ("Address And Command Setup Time [ns]: 		%d.%d\n",
-			     sign * leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 33:	/* Address And Command Hold Time */
-			sign = 1;
-			switch (dimmInfo->memoryType) {
-			case DDR:
-				time_tmp =
-					(((data[i] & 0xf0) >> 4) * 10) +
-					((data[i] & 0x0f));
-				leftOfPoint = time_tmp / 100;
-				rightOfPoint = time_tmp % 100;
-				break;
-			case SDRAM:
-				leftOfPoint = (data[i] & 0xf0) >> 4;
-				if (leftOfPoint > 7) {
-					leftOfPoint = data[i] & 0x70 >> 4;
-					sign = -1;
-				}
-				rightOfPoint = (data[i] & 0x0f);
-				break;
-			}
-			dimmInfo->addrAndCommandHoldTime =
-				(leftOfPoint * 100 + rightOfPoint) * sign;
-			debug
-			    ("Address And Command Hold Time [ns]: 		%d.%d\n",
-			     sign * leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 34:	/* Data Input Setup Time */
-			sign = 1;
-			switch (dimmInfo->memoryType) {
-			case DDR:
-				time_tmp =
-					(((data[i] & 0xf0) >> 4) * 10) +
-					((data[i] & 0x0f));
-				leftOfPoint = time_tmp / 100;
-				rightOfPoint = time_tmp % 100;
-				break;
-			case SDRAM:
-				leftOfPoint = (data[i] & 0xf0) >> 4;
-				if (leftOfPoint > 7) {
-					leftOfPoint = data[i] & 0x70 >> 4;
-					sign = -1;
-				}
-				rightOfPoint = (data[i] & 0x0f);
-				break;
-			}
-			dimmInfo->dataInputSetupTime =
-				(leftOfPoint * 100 + rightOfPoint) * sign;
-			debug
-			    ("Data Input Setup Time [ns]: 			%d.%d\n",
-			     sign * leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 35:	/* Data Input Hold Time */
-			sign = 1;
-			switch (dimmInfo->memoryType) {
-			case DDR:
-				time_tmp =
-					(((data[i] & 0xf0) >> 4) * 10) +
-					((data[i] & 0x0f));
-				leftOfPoint = time_tmp / 100;
-				rightOfPoint = time_tmp % 100;
-				break;
-			case SDRAM:
-				leftOfPoint = (data[i] & 0xf0) >> 4;
-				if (leftOfPoint > 7) {
-					leftOfPoint = data[i] & 0x70 >> 4;
-					sign = -1;
-				}
-				rightOfPoint = (data[i] & 0x0f);
-				break;
-			}
-			dimmInfo->dataInputHoldTime =
-				(leftOfPoint * 100 + rightOfPoint) * sign;
-			debug
-			    ("Data Input Hold Time [ns]: 			%d.%d\n\n",
-			     sign * leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-		}
-	}
-	/* calculating the sdram density */
-	for (i = 0;
-	     i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
-	     i++) {
-		density = density * 2;
-	}
-	dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
-		dimmInfo->sdramWidth;
-	dimmInfo->numberOfDevices =
-		(dimmInfo->dataWidth / dimmInfo->sdramWidth) *
-		dimmInfo->numOfModuleBanks;
-	if ((dimmInfo->errorCheckType == 0x1)
-	    || (dimmInfo->errorCheckType == 0x2)
-	    || (dimmInfo->errorCheckType == 0x3)) {
-		dimmInfo->size =
-			(dimmInfo->deviceDensity / 8) *
-			(dimmInfo->numberOfDevices -
-			 /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */
-			 dimmInfo->numberOfDevices / 8);
-	} else {
-		dimmInfo->size =
-			(dimmInfo->deviceDensity / 8) *
-			dimmInfo->numberOfDevices;
-	}
-
-	/* compute the module DRB size */
-	tmp = (1 <<
-	       (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
-	tmp *= dimmInfo->numOfModuleBanks;
-	tmp *= dimmInfo->sdramWidth;
-	tmp = tmp >> 24;	/* div by 0x4000000 (64M)       */
-	dimmInfo->drb_size = (uchar) tmp;
-	debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
-
-	/* try a CAS latency of 3 first... */
-
-	/* bit 1 is CL2, bit 2 is CL3 */
-	supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1;
-
-	cal_val = 0;
-	if (supp_cal & 3) {
-		if (NS10to10PS (data[9]) <= tmemclk)
-			cal_val = 3;
-	}
-
-	/* then 2... */
-	if (supp_cal & 2) {
-		if (NS10to10PS (data[23]) <= tmemclk)
-			cal_val = 2;
-	}
-
-	debug("cal_val = %d\n", cal_val);
-
-	/* bummer, did't work... */
-	if (cal_val == 0) {
-		debug("Couldn't find a good CAS latency\n");
-		hang ();
-		return 0;
-	}
-
-	return true;
-#endif
-}
-
-/* sets up the GT properly with information passed in */
-int setup_sdram (AUX_MEM_DIMM_INFO * info)
-{
-	ulong tmp, check;
-	ulong tmp_sdram_mode = 0;	/* 0x141c */
-	ulong tmp_dunit_control_low = 0;	/* 0x1404 */
-	int i;
-
-	/* added 8/21/2003 P. Marchese */
-	unsigned int sdram_config_reg;
-
-	/* added 10/10/2003 P. Marchese */
-	ulong sdram_chip_size;
-
-	/* sanity checking */
-	if (!info->numOfModuleBanks) {
-		printf ("setup_sdram called with 0 banks\n");
-		return 1;
-	}
-
-	/* delay line */
-	set_dfcdlInit ();	/* may be its not needed */
-	debug("Delay line set done\n");
-
-	/* set SDRAM mode NOP */ /* To_do check it */
-	GT_REG_WRITE (SDRAM_OPERATION, 0x5);
-	while (GTREGREAD (SDRAM_OPERATION) != 0) {
-		debug
-		    ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
-	}
-
-	/* SDRAM configuration */
-/* added 8/21/2003 P. Marchese */
-/* code allows usage of registered DIMMS */
-
-	/* figure out the memory refresh internal */
-	switch (info->RefreshInterval) {
-	case 0x0:
-	case 0x80:		/* refresh period is 15.625 usec */
-		sdram_config_reg =
-			(unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_CLK)
-					/ (float) 1000000.0);
-		break;
-	case 0x1:
-	case 0x81:		/* refresh period is 3.9 usec */
-		sdram_config_reg =
-			(unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_CLK) /
-					(float) 1000000.0);
-		break;
-	case 0x2:
-	case 0x82:		/* refresh period is 7.8 usec */
-		sdram_config_reg =
-			(unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_CLK) /
-					(float) 1000000.0);
-		break;
-	case 0x3:
-	case 0x83:		/* refresh period is 31.3 usec */
-		sdram_config_reg =
-			(unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_CLK) /
-					(float) 1000000.0);
-		break;
-	case 0x4:
-	case 0x84:		/* refresh period is 62.5 usec */
-		sdram_config_reg =
-			(unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_CLK) /
-					(float) 1000000.0);
-		break;
-	case 0x5:
-	case 0x85:		/* refresh period is 125 usec */
-		sdram_config_reg =
-			(unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_CLK) /
-					(float) 1000000.0);
-		break;
-	default:		/* refresh period undefined */
-		printf ("DRAM refresh period is unknown!\n");
-		printf ("Aborting DRAM setup with an error\n");
-		hang ();
-		break;
-	}
-	debug("calculated refresh interval %0x\n", sdram_config_reg);
-
-	/* make sure the refresh value is only 14 bits */
-	if (sdram_config_reg > 0x1fff)
-		sdram_config_reg = 0x1fff;
-	debug("adjusted refresh interval %0x\n", sdram_config_reg);
-
-	/* we want physical bank interleaving and */
-	/* virtual bank interleaving enabled so do nothing */
-	/* since these bits need to be zero to enable the interleaving */
-
-	/*  registered DRAM ? */
-	if (info->registeredAddrAndControlInputs == 1) {
-		/* it's registered DRAM, so set the reg. DRAM bit */
-		sdram_config_reg = sdram_config_reg | BIT17;
-		debug("Enabling registered DRAM bit\n");
-	}
-	/* turn on DRAM ECC? */
-#ifdef CONFIG_MV64460_ECC
-	if (info->errorCheckType == 0x2) {
-		/* DRAM has ECC, so turn it on */
-		sdram_config_reg = sdram_config_reg | BIT18;
-		debug("Enabling ECC\n");
-	}
-#endif
-	/* set the data DQS pin configuration */
-	switch (info->sdramWidth) {
-	case 0x4:		/* memory is x4 */
-		sdram_config_reg = sdram_config_reg | BIT20 | BIT21;
-		debug("Data DQS pins set for 16 pins\n");
-		break;
-	case 0x8:		/* memory is x8 or x16 */
-	case 0x10:
-		sdram_config_reg = sdram_config_reg | BIT21;
-		debug("Data DQS pins set for 8 pins\n");
-		break;
-	case 0x20:		/* memory is x32 */
-		/* both bits are cleared for x32 so nothing to do */
-		debug("Data DQS pins set for 2 pins\n");
-		break;
-	default:		/* memory width unsupported */
-		printf ("DRAM chip width is unknown!\n");
-		printf ("Aborting DRAM setup with an error\n");
-		hang ();
-		break;
-	}
-
-	/*ronen db64460 */
-	/* perform read buffer assignments */
-	/* we are going to use the Power-up defaults */
-	/* bit 27 = PCI bus #0 = buffer 0 */
-	/* bit 28 = PCI bus #1 = buffer 0 */
-	/* bit 29 = MPSC = buffer 0 */
-	/* bit 30 = IDMA = buffer 0 */
-	/* bit 31 = Gigabit = buffer 0 */
-	sdram_config_reg = sdram_config_reg | 0x58000000;
-	sdram_config_reg = sdram_config_reg & 0xffffff00;
-	/* bit 14 FBSplit = FCRAM controller bsplit enable. */
-	/* bit 15 vw = FCRAM Variable write length enable.   */
-	/* bit 16 DType = Dram Type (0 = FCRAM,1 = Standard) */
-	sdram_config_reg = sdram_config_reg | BIT14 | BIT15;
-
-	/* write the value into the SDRAM configuration register */
-	GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg);
-	debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG));
-
-	/* SDRAM open pages control keep open as much as I can */
-	GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
-	debug
-	    ("sdram_open_pages_controll 0x1414: %08x\n",
-	     GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
-
-	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
-	tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);	/* Clock Domain Sync from power on reset */
-	if (tmp == 0)
-		debug("Core Signals are sync (by HW-Setting)!!!\n");
-	else
-		debug
-		    ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
-
-	/* SDRAM set CAS Latency according to SPD information */
-	switch (info->memoryType) {
-	case SDRAM:
-		printf ("### SD-RAM not supported !!!\n");
-		printf ("Aborting!!!\n");
-		hang ();
-		/* ToDo fill SD-RAM if needed !!!!! */
-		break;
-		/* Calculate the settings for SDRAM mode and Dunit control low registers */
-		/* Values set according to technical bulletin TB-92 rev. c */
-	case DDR:
-		debug("### SET-CL for DDR-RAM\n");
-		/* ronen db64460 - change the tmp_dunit_control_low setting!!! */
-		switch (info->maxClSupported_DDR) {
-		case DDR_CL_3:
-			tmp_sdram_mode = 0x32;	/* CL=3 Burstlength = 4 */
-			if (tmp == 1) {	/* clocks sync */
-				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
-					tmp_dunit_control_low = 0x05110051;
-				else
-					tmp_dunit_control_low = 0x24110051;
-				debug
-				    ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-				printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
-			} else {	/* clk sync. bypassed   */
-
-				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
-					tmp_dunit_control_low = 0xC5000540;
-				else
-					tmp_dunit_control_low = 0xC4000540;
-				debug
-				    ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			}
-			break;
-		case DDR_CL_2_5:
-			tmp_sdram_mode = 0x62;	/* CL=2.5 Burstlength = 4 */
-			if (tmp == 1) {	/* clocks sync */
-				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
-					tmp_dunit_control_low = 0x25110051;
-				else
-					tmp_dunit_control_low = 0x24110051;
-				debug
-				    ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-				printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
-			} else {	/* clk sync. bypassed   */
-
-				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
-					tmp_dunit_control_low = 0xC5000540;
-					/* printf("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
-					/* printf("Aborting!!!\n");1 */
-					/* hang();1 */
-				} else
-					tmp_dunit_control_low = 0xC4000540;
-				debug
-				    ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			}
-			break;
-		case DDR_CL_2:
-			tmp_sdram_mode = 0x22;	/* CL=2 Burstlength = 4 */
-			if (tmp == 1) {	/* clocks sync */
-				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
-					tmp_dunit_control_low = 0x04110051;
-				else
-					tmp_dunit_control_low = 0x03110051;
-				debug
-				    ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-				printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
-			} else {	/* clk sync. bypassed   */
-
-				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
-					/*printf("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
-					/*printf("Aborting!!!\n");1 */
-					/*hang();1 */
-					tmp_dunit_control_low = 0xC4000540;
-				} else
-					tmp_dunit_control_low = 0xC3000540;;
-				debug
-				    ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			}
-			break;
-		case DDR_CL_1_5:
-			tmp_sdram_mode = 0x52;	/* CL=1.5 Burstlength = 4 */
-			if (tmp == 1) {	/* clocks sync */
-				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
-					tmp_dunit_control_low = 0x24110051;
-				else
-					tmp_dunit_control_low = 0x23110051;
-				debug
-				    ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-				printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
-			} else {	/* clk sync. bypassed   */
-
-				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
-					/*printf("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
-					/*printf("Aborting!!!\n");1 */
-					/*hang();1 */
-					tmp_dunit_control_low = 0xC4000540;
-				} else
-					tmp_dunit_control_low = 0xC3000540;
-				debug
-				    ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			}
-			break;
-
-		default:
-			printf ("Max. CL is out of range %d\n",
-				info->maxClSupported_DDR);
-			hang ();
-			break;
-		}		/* end DDR switch */
-		break;
-	}			/* end CL switch */
-
-	/* Write results of CL detection procedure */
-	/* set SDRAM mode reg. 0x141c */
-	GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
-
-	/* set SDRAM mode SetCommand 0x1418 */
-	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
-	while (GTREGREAD (SDRAM_OPERATION) != 0) {
-		debug
-		    ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
-	}
-
-	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
-	GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low);
-
-	/* set SDRAM mode SetCommand 0x1418 */
-	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
-	while (GTREGREAD (SDRAM_OPERATION) != 0) {
-		debug
-		    ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
-	}
-
-/*------------------------------------------------------------------------------ */
-
-	/* bank parameters */
-	/* SDRAM address decode register 0x1410 */
-	/* program this with the default value */
-	tmp = 0x02;		/* power-up default address select decoding value */
-
-	debug("drb_size (n*64Mbit): %d\n", info->drb_size);
-/* figure out the DRAM chip size */
-	sdram_chip_size =
-		(1 << (info->numOfRowAddresses + info->numOfColAddresses));
-	sdram_chip_size *= info->sdramWidth;
-	sdram_chip_size *= 4;
-	debug("computed sdram chip size is %#lx\n", sdram_chip_size);
-	/* divide sdram chip size by 64 Mbits */
-	sdram_chip_size = sdram_chip_size / 0x4000000;
-	switch (sdram_chip_size) {
-	case 1:		/* 64 Mbit */
-	case 2:		/* 128 Mbit */
-		debug("RAM-Device_size 64Mbit or 128Mbit)\n");
-		tmp |= (0x00 << 4);
-		break;
-	case 4:		/* 256 Mbit */
-	case 8:		/* 512 Mbit */
-		debug("RAM-Device_size 256Mbit or 512Mbit)\n");
-		tmp |= (0x01 << 4);
-		break;
-	case 16:		/* 1 Gbit */
-	case 32:		/* 2 Gbit */
-		debug("RAM-Device_size 1Gbit or 2Gbit)\n");
-		tmp |= (0x02 << 4);
-		break;
-	default:
-		printf ("Error in dram size calculation\n");
-		printf ("RAM-Device_size is unsupported\n");
-		hang ();
-	}
-
-	/* SDRAM address control */
-	GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
-	debug
-	    ("setting up sdram address control (0x1410) with: %08lx \n",
-	     tmp);
-
-/* ------------------------------------------------------------------------------ */
-/* same settings for registerd & non-registerd DDR SDRAM */
-	debug
-	    ("setting up sdram_timing_control_low (0x1408) with: %08x \n",
-	     0x01501220);
-	/*ronen db64460 */
-	GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x01501220);
-
-
-/* ------------------------------------------------------------------------------ */
-
-	/* SDRAM configuration */
-	tmp = GTREGREAD (SDRAM_CONFIG);
-
-	if (info->registeredAddrAndControlInputs
-	    || info->registeredDQMBinputs) {
-		tmp |= (1 << 17);
-		debug
-		    ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
-		     info->registeredAddrAndControlInputs,
-		     info->registeredDQMBinputs);
-	}
-
-	/* Use buffer 1 to return read data to the CPU
-	 * Page 426 MV6indent: Standard input:1464: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
-
-indent: Standard input:1465: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
-
-4460 */
-	tmp |= (1 << 26);
-	debug
-	    ("Before Buffer assignment - sdram_conf (0x1400): %08x\n",
-	     GTREGREAD (SDRAM_CONFIG));
-	debug
-	    ("After Buffer assignment - sdram_conf (0x1400): %08x\n",
-	     GTREGREAD (SDRAM_CONFIG));
-
-	/* SDRAM timing To_do: */
-/* ------------------------------------------------------------------------------ */
-	/* ronen db64460 */
-	debug
-	    ("setting up sdram_timing_control_high (0x140c) with: %08x \n",
-	     0xc);
-	GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0xc);
-
-	debug
-	    ("setting up sdram address pads control (0x14c0) with: %08x \n",
-	     0x7d5014a);
-	GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a);
-
-	debug
-	    ("setting up sdram data pads control (0x14c4) with: %08x \n",
-	     0x7d5014a);
-	GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a);
-
-/* ------------------------------------------------------------------------------ */
-
-	/* set the SDRAM configuration for each bank */
-
-/*      for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
-	{
-		i = info->slot;
-		debug
-		    ("\n*** Running a MRS cycle for bank %d ***\n", i);
-
-		/* map the bank */
-		memory_map_bank (i, 0, GB / 4);
-
-		/* set SDRAM mode */ /* To_do check it */
-		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
-		check = GTREGREAD (SDRAM_OPERATION);
-		debug
-		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
-		     check);
-
-
-		/* switch back to normal operation mode */
-		GT_REG_WRITE (SDRAM_OPERATION, 0);
-		check = GTREGREAD (SDRAM_OPERATION);
-		debug
-		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
-		     check);
-
-		/* unmap the bank */
-		memory_map_bank (i, 0, 0);
-	}
-
-	return 0;
-
-}
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-long int dram_size (long int *base, long int maxsize)
-{
-	volatile long int *addr, *b = base;
-	long int cnt, val, save1, save2;
-
-#define STARTVAL (1<<20)	/* start test at 1M */
-	for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
-	     cnt <<= 1) {
-		addr = base + cnt;	/* pointer arith! */
-
-		save1 = *addr;	/* save contents of addr */
-		save2 = *b;	/* save contents of base */
-
-		*addr = cnt;	/* write cnt to addr */
-		*b = 0;		/* put null at base */
-
-		/* check at base address */
-		if ((*b) != 0) {
-			*addr = save1;	/* restore *addr */
-			*b = save2;	/* restore *b */
-			return (0);
-		}
-		val = *addr;	/* read *addr */
-		val = *addr;	/* read *addr */
-
-		*addr = save1;
-		*b = save2;
-
-		if (val != cnt) {
-			debug
-			    ("Found %08x  at Address %08x (failure)\n",
-			     (unsigned int) val, (unsigned int) addr);
-			/* fix boundary condition.. STARTVAL means zero */
-			if (cnt == STARTVAL / sizeof (long))
-				cnt = 0;
-			return (cnt * sizeof (long));
-		}
-	}
-	return maxsize;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* ppcboot interface function to SDRAM init - this is where all the
- * controlling logic happens */
-phys_size_t initdram (int board_type)
-{
-	int checkbank[4] = {[0 ... 3] = 0 };
-	ulong realsize, total;
-	AUX_MEM_DIMM_INFO dimmInfo1;
-	AUX_MEM_DIMM_INFO dimmInfo2;
-	int nhr, bank_no;
-	ulong dest, memSpaceAttr;
-
-	/* first, use the SPD to get info about the SDRAM/ DDRRAM */
-
-	/* check the NHR bit and skip mem init if it's already done */
-	nhr = get_hid0 () & (1 << 16);
-
-	if (nhr) {
-		printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n");
-	} else {
-		/* DIMM0 */
-		check_dimm (0, &dimmInfo1);
-
-		/* DIMM1 */
-		check_dimm (1, &dimmInfo2);
-
-		memory_map_bank (0, 0, 0);
-		memory_map_bank (1, 0, 0);
-		memory_map_bank (2, 0, 0);
-		memory_map_bank (3, 0, 0);
-
-		/* ronen check correct set of DIMMS */
-		if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) {
-			if (dimmInfo1.errorCheckType !=
-			    dimmInfo2.errorCheckType)
-				printf ("***WARNNING***!!!! different ECC support of the DIMMS\n");
-			if (dimmInfo1.maxClSupported_DDR !=
-			    dimmInfo2.maxClSupported_DDR)
-				printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n");
-			if (dimmInfo1.registeredAddrAndControlInputs !=
-			    dimmInfo2.registeredAddrAndControlInputs)
-				printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n");
-		}
-
-		if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) {
-			printf ("Setup for DIMM1 failed.\n");
-		}
-
-		if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) {
-			printf ("Setup for DIMM2 failed.\n");
-		}
-
-		/* set the NHR bit */
-		set_hid0 (get_hid0 () | (1 << 16));
-	}
-	/* next, size the SDRAM banks */
-
-	realsize = total = 0;
-	if (dimmInfo1.numOfModuleBanks > 0) {
-		checkbank[0] = 1;
-	}
-	if (dimmInfo1.numOfModuleBanks > 1) {
-		checkbank[1] = 1;
-	}
-	if (dimmInfo1.numOfModuleBanks > 2)
-		printf ("Error, SPD claims DIMM1 has >2 banks\n");
-
-	printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks);
-
-	if (dimmInfo2.numOfModuleBanks > 0) {
-		checkbank[2] = 1;
-	}
-	if (dimmInfo2.numOfModuleBanks > 1) {
-		checkbank[3] = 1;
-	}
-	if (dimmInfo2.numOfModuleBanks > 2)
-		printf ("Error, SPD claims DIMM2 has >2 banks\n");
-
-	printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
-
-	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
-		/* skip over banks that are not populated */
-		if (!checkbank[bank_no])
-			continue;
-
-		/* ronen - realsize = dram_size((long int *)total, check); */
-		if (bank_no == 0 || bank_no == 1) {
-			if (checkbank[1] == 1)
-				realsize = dimmInfo1.size / 2;
-			else
-				realsize = dimmInfo1.size;
-		}
-		if (bank_no == 2 || bank_no == 3) {
-			if (checkbank[3] == 1)
-				realsize = dimmInfo2.size / 2;
-			else
-				realsize = dimmInfo2.size;
-		}
-		memory_map_bank (bank_no, total, realsize);
-
-		/* ronen - initialize the DRAM for ECC */
-#ifdef CONFIG_MV64460_ECC
-		if ((dimmInfo1.errorCheckType != 0) &&
-		    ((dimmInfo2.errorCheckType != 0)
-		     || (dimmInfo2.numOfModuleBanks == 0))) {
-			printf ("ECC Initialization of Bank %d:", bank_no);
-			memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8;
-			mvDmaSetMemorySpace (0, 0, memSpaceAttr, total,
-					     realsize);
-			for (dest = total; dest < total + realsize;
-			     dest += _8M) {
-				mvDmaTransfer (0, total, dest, _8M,
-					       BIT8 /*DMA_DTL_128BYTES */  |
-					       BIT3 /*DMA_HOLD_SOURCE_ADDR */
-					       |
-					       BIT11
-					       /*DMA_BLOCK_TRANSFER_MODE */ );
-				while (mvDmaIsChannelActive (0));
-			}
-			printf (" PASS\n");
-		}
-#endif
-
-		total += realsize;
-	}
-
-	/* ronen */
-	switch ((GTREGREAD (0x141c) >> 4) & 0x7) {
-	case 0x2:
-		printf ("CAS Latency = 2");
-		break;
-	case 0x3:
-		printf ("CAS Latency = 3");
-		break;
-	case 0x5:
-		printf ("CAS Latency = 1.5");
-		break;
-	case 0x6:
-		printf ("CAS Latency = 2.5");
-		break;
-	}
-	printf (" tRP = %d tRAS = %d tRCD=%d\n",
-		((GTREGREAD (0x1408) >> 8) & 0xf) + 1,
-		((GTREGREAD (0x1408) >> 20) & 0xf) + 1,
-		((GTREGREAD (0x1408) >> 4) & 0xf) + 1);
-
-/*	Setup Ethernet DMA Adress window to DRAM Area */
-	if (total > _256M)
-		printf ("*** ONLY the first 256MB DRAM memory are used out of the ");
-	else
-		printf ("Total SDRAM memory is ");
-	/* (cause all the 4 BATS are taken) */
-	return (total);
-}
-
-
-/* ronen- add Idma functions for usage of the ecc dram init. */
-/*******************************************************************************
-* mvDmaIsChannelActive - Checks if a engine is busy.
-********************************************************************************/
-int mvDmaIsChannelActive (int engine)
-{
-	ulong data;
-
-	data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * engine);
-	if (data & BIT14 /*activity status */ ) {
-		return 1;
-	}
-	return 0;
-}
-
-/*******************************************************************************
-* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
-*                       map.
-*******************************************************************************/
-int mvDmaSetMemorySpace (ulong memSpace,
-			 ulong memSpaceTarget,
-			 ulong memSpaceAttr, ulong baseAddress, ulong size)
-{
-	ulong temp;
-
-	/* The base address must be aligned to the size.  */
-	if (baseAddress % size != 0) {
-		return 0;
-	}
-	if (size >= 0x10000 /*64K */ ) {
-		size &= 0xffff0000;
-		baseAddress = (baseAddress & 0xffff0000);
-		/* Set the new attributes */
-		GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8,
-			      (baseAddress | memSpaceTarget | memSpaceAttr));
-		GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8),
-			      (size - 1) & 0xffff0000);
-		temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG);
-		GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
-			      (temp & ~(BIT0 << memSpace)));
-		return 1;
-	}
-	return 0;
-}
-
-
-/*******************************************************************************
-* mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4
-*                 DMA channels.
-********************************************************************************/
-int mvDmaTransfer (int engine, ulong sourceAddr,
-		   ulong destAddr, ulong numOfBytes, ulong command)
-{
-	ulong engOffReg = 0;	/* Engine Offset Register */
-
-	if (numOfBytes > 0xffff) {
-		command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ;
-	}
-	command = command | ((command >> 6) & 0x7);
-	engOffReg = engine * 4;
-	GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg,
-		      numOfBytes);
-	GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg,
-		      sourceAddr);
-	GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg,
-		      destAddr);
-	command =
-		command | BIT12 /*DMA_CHANNEL_ENABLE */  | BIT9
-		/*DMA_NON_CHAIN_MODE */ ;
-	/* Activate DMA engine By writting to mvDmaControlRegister */
-	GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command);
-	return 1;
-}
-
-/****************************************************************************************
- *			       SDRAM INIT						*
- *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb	*
- *		 This procedure fits only the Atlantis					*
- *											*
- ***************************************************************************************/
-
-
-/****************************************************************************************
- *			       DFCDL initialize MV643xx Design Considerations		*
- *											*
- ***************************************************************************************/
-int set_dfcdlInit (void)
-{
-	/*ronen the dfcdl init are done by the I2C */
-	return (0);
-}
diff --git a/board/Marvell/dkb/Kconfig b/board/Marvell/dkb/Kconfig
index 33d5157bc3c..f6748941c69 100644
--- a/board/Marvell/dkb/Kconfig
+++ b/board/Marvell/dkb/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_DKB
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "dkb"
 
diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c
index b53c81080d1..0887d92c299 100644
--- a/board/Marvell/dreamplug/dreamplug.c
+++ b/board/Marvell/dreamplug/dreamplug.c
@@ -12,7 +12,7 @@
 #include <common.h>
 #include <miiphy.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include "dreamplug.h"
 
@@ -25,9 +25,9 @@ int board_early_init_f(void)
 	 * There are maximum 64 gpios controlled through 2 sets of registers
 	 * the  below configuration configures mainly initial LED status
 	 */
-	kw_config_gpio(DREAMPLUG_OE_VAL_LOW,
-			DREAMPLUG_OE_VAL_HIGH,
-			DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
+	mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
+			  DREAMPLUG_OE_VAL_HIGH,
+			  DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
 	static const u32 kwmpp_config[] = {
@@ -90,7 +90,7 @@ int board_early_init_f(void)
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
diff --git a/board/Marvell/gplugd/Kconfig b/board/Marvell/gplugd/Kconfig
index 102c18d30d4..d9448165096 100644
--- a/board/Marvell/gplugd/Kconfig
+++ b/board/Marvell/gplugd/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_GPLUGD
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "gplugd"
 
diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c
index 72bccc821ce..b0d5f1e10f4 100644
--- a/board/Marvell/guruplug/guruplug.c
+++ b/board/Marvell/guruplug/guruplug.c
@@ -9,7 +9,7 @@
 #include <common.h>
 #include <miiphy.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include "guruplug.h"
 
@@ -22,9 +22,9 @@ int board_early_init_f(void)
 	 * There are maximum 64 gpios controlled through 2 sets of registers
 	 * the  below configuration configures mainly initial LED status
 	 */
-	kw_config_gpio(GURUPLUG_OE_VAL_LOW,
-			GURUPLUG_OE_VAL_HIGH,
-			GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
+	mvebu_config_gpio(GURUPLUG_OE_VAL_LOW,
+			  GURUPLUG_OE_VAL_HIGH,
+			  GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
 	static const u32 kwmpp_config[] = {
@@ -92,7 +92,7 @@ int board_init(void)
 	gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
 
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
diff --git a/board/Marvell/include/core.h b/board/Marvell/include/core.h
deleted file mode 100644
index 3119d0a073e..00000000000
--- a/board/Marvell/include/core.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/* Core.h - Basic core logic functions and definitions */
-
-/* Copyright Galileo Technology. */
-
-/*
-DESCRIPTION
-This header file contains simple read/write macros for addressing
-the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
-space). The macros take care of Big/Little endian conversions.
-*/
-
-#ifndef __INCcoreh
-#define __INCcoreh
-
-#include "mv_gen_reg.h"
-
-extern unsigned int INTERNAL_REG_BASE_ADDR;
-
-/****************************************/
-/*	    GENERAL Definitions			*/
-/****************************************/
-
-#define NO_BIT		0x00000000
-#define BIT0		0x00000001
-#define BIT1		0x00000002
-#define BIT2		0x00000004
-#define BIT3		0x00000008
-#define BIT4		0x00000010
-#define BIT5		0x00000020
-#define BIT6		0x00000040
-#define BIT7		0x00000080
-#define BIT8		0x00000100
-#define BIT9		0x00000200
-#define BIT10		0x00000400
-#define BIT11		0x00000800
-#define BIT12		0x00001000
-#define BIT13		0x00002000
-#define BIT14		0x00004000
-#define BIT15		0x00008000
-#define BIT16		0x00010000
-#define BIT17		0x00020000
-#define BIT18		0x00040000
-#define BIT19		0x00080000
-#define BIT20		0x00100000
-#define BIT21		0x00200000
-#define BIT22		0x00400000
-#define BIT23		0x00800000
-#define BIT24		0x01000000
-#define BIT25		0x02000000
-#define BIT26		0x04000000
-#define BIT27		0x08000000
-#define BIT28		0x10000000
-#define BIT29		0x20000000
-#define BIT30		0x40000000
-#define BIT31		0x80000000
-
-#define _1K		0x00000400
-#define _2K		0x00000800
-#define _4K		0x00001000
-#define _8K		0x00002000
-#define _16K		0x00004000
-#define _32K		0x00008000
-#define _64K		0x00010000
-#define _128K		0x00020000
-#define _256K		0x00040000
-#define _512K		0x00080000
-
-#define _1M		0x00100000
-#define _2M		0x00200000
-#define _3M		0x00300000
-#define _4M		0x00400000
-#define _5M		0x00500000
-#define _6M		0x00600000
-#define _7M		0x00700000
-#define _8M		0x00800000
-#define _9M		0x00900000
-#define _10M		0x00a00000
-#define _11M		0x00b00000
-#define _12M		0x00c00000
-#define _13M		0x00d00000
-#define _14M		0x00e00000
-#define _15M		0x00f00000
-#define _16M		0x01000000
-
-#define _32M		0x02000000
-#define _64M		0x04000000
-#define _128M		0x08000000
-#define _256M		0x10000000
-#define _512M		0x20000000
-
-#define _1G		0x40000000
-#define _2G		0x80000000
-
-/* Little to Big endian conversion macros */
-
-#ifdef LE /* Little Endian */
-#define SHORT_SWAP(X) (X)
-#define WORD_SWAP(X) (X)
-#define LONG_SWAP(X) ((l64)(X))
-
-#else	 /* Big Endian */
-#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
-
-#define WORD_SWAP(X) (((X)&0xff)<<24)+	    \
-		    (((X)&0xff00)<<8)+	    \
-		    (((X)&0xff0000)>>8)+    \
-		    (((X)&0xff000000)>>24)
-
-#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+		\
-			    (((X)&0xff00ULL)<<40)+		\
-			    (((X)&0xff0000ULL)<<24)+		\
-			    (((X)&0xff000000ULL)<<8)+		\
-			    (((X)&0xff00000000ULL)>>8)+		\
-			    (((X)&0xff0000000000ULL)>>24)+	\
-			    (((X)&0xff000000000000ULL)>>40)+	\
-			    (((X)&0xff00000000000000ULL)>>56))
-
-#endif
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-/* Those two definitions were defined to be compatible with MIPS */
-#define NONE_CACHEABLE		0x00000000
-#define CACHEABLE			0x00000000
-
-/* 750 cache line */
-#define CACHE_LINE_SIZE 32
-#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
-#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
-
-/* Read/Write to/from GT`s internal registers */
-#define GT_REG_READ(offset, pData)					    \
-*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE |			    \
-		INTERNAL_REG_BASE_ADDR | (offset))) ) ;						     \
-*pData = WORD_SWAP(*pData)
-
-#define GTREGREAD(offset)						    \
-	 (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE |	     \
-		   INTERNAL_REG_BASE_ADDR | (offset))) ))
-
-#define GT_REG_WRITE(offset, data)					    \
-*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) =		    \
-		    WORD_SWAP(data)
-
-/* Write 32/16/8 bit */
-#define WRITE_CHAR(address, data)					    \
-	*((unsigned char *)(address)) = data
-#define WRITE_SHORT(address, data)					    \
-	*((unsigned short *)(address)) = data
-#define WRITE_WORD(address, data)					    \
-	*((unsigned int *)(address)) = data
-
-#define GT_WRITE_CHAR(address, data)	 WRITE_CHAR(address, data)
-
-/* Write 32/16/8 bit NonCacheable */
-/*
-#define GT_WRITE_CHAR(address, data)					       \
-	(*((unsigned char *)NONE_CACHEABLE(address))) = data
-#define GT_WRITE_SHORT(address, data)					       \
-	(*((unsigned short *)NONE_CACHEABLE(address))) = data
-#define GT_WRITE_WORD(address, data)					       \
-	(*((unsigned int *)NONE_CACHEABLE(address))) = data
-*/
- /*#define GT_WRITE_CHAR(address, data)	  ((*((volatile unsigned char *)NONE_CACHEABLE((address)))) = ((unsigned char)(data)))1 */
-
- /*#define GT_WRITE_SHORT(address, data)   ((*((volatile unsigned short *)NONE_CACHEABLE((address)))) = ((unsigned short)(data)))1 */
-
- /*#define GT_WRITE_WORD(address, data)	 ((*((volatile unsigned int *)NONE_CACHEABLE((address)))) = ((unsigned int)(data)))1 */
-
-
-/* Read 32/16/8 bits - returns data in variable. */
-#define READ_CHAR(address, pData)					    \
-	*pData = *((volatile unsigned char *)(address))
-
-#define READ_SHORT(address, pData)					    \
-	*pData = *((volatile unsigned short *)(address))
-
-#define READ_WORD(address, pData)					    \
-	*pData = *((volatile unsigned int *)(address))
-
-/* Read 32/16/8 bit - returns data direct. */
-#define READCHAR(address)						    \
-	*((volatile unsigned char *)((address) | NONE_CACHEABLE))
-
-#define READSHORT(address)						    \
-	*((volatile unsigned short *)((address) | NONE_CACHEABLE))
-
-#define READWORD(address)						    \
-	*((volatile unsigned int *)((address) | NONE_CACHEABLE))
-
-/* Those two Macros were defined to be compatible with MIPS */
-#define VIRTUAL_TO_PHY(x)    (((unsigned int)x) & 0xffffffff)
-#define PHY_TO_VIRTUAL(x)    (((unsigned int)x) | NONE_CACHEABLE)
-
-/*  SET_REG_BITS(regOffset,bits) -
-   gets register offset and bits: a 32bit value. It set to logic '1' in the
-   internal register the bits which given as an input example:
-   SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
-   '1' in register 0x840 while the other bits stays as is. */
-#define SET_REG_BITS(regOffset,bits) \
-	*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR |  \
-	regOffset) |= (unsigned int)WORD_SWAP(bits)
-
-/*  RESET_REG_BITS(regOffset,bits) -
-   gets register offset and bits: a 32bit value. It set to logic '0' in the
-   internal register the bits which given as an input example:
-   RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
-   '0' in register 0x840 while the other bits stays as is. */
-#define RESET_REG_BITS(regOffset,bits) \
-	*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR   \
-	| regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
-/* gets register offset and bits: a 32bit value. It set to logic '1' in the
-   internal register the bits which given as an input example:
-   GT_SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
-   '1' in register 0x840 while the other bits stays as is. */
- /*#define GT_SET_REG_BITS(regOffset,bits)	((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) |= ((unsigned int)WORD_SWAP(bits)))1 */
- /*#define GT_SET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)1 */
-#define GT_SET_REG_BITS(regOffset,bits) SET_REG_BITS(regOffset,bits)
-/* gets register offset and bits: a 32bit value. It set to logic '0' in the
-   internal register the bits which given as an input example:
-   GT_RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to
-   logic '0' in register 0x840 while the other bits stays as is. */
- /*#define GT_RESET_REG_BITS(regOffset,bits)	((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) |  (regOffset)))) &= ~((unsigned int)WORD_SWAP(bits)))1 */
-#define GT_RESET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)
-
-
-#define DEBUG_LED0_ON()	       WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x8000,0)
-#define DEBUG_LED1_ON()	       WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0xc000,0)
-#define DEBUG_LED2_ON()	       WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x10000,0)
-#define DEBUG_LED0_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x14000,0)
-#define DEBUG_LED1_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x18000,0)
-#define DEBUG_LED2_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x1c000,0)
-
-#endif /* __INCcoreh */
diff --git a/board/Marvell/include/mv_gen_reg.h b/board/Marvell/include/mv_gen_reg.h
deleted file mode 100644
index 008185ec78a..00000000000
--- a/board/Marvell/include/mv_gen_reg.h
+++ /dev/null
@@ -1,2296 +0,0 @@
-/* mv_gen_reg.h - Internal registers definition file */
-/* Copyright - Galileo technology. */
-
-
-/*******************************************************************************
-*		    Copyright 2002, GALILEO TECHNOLOGY, LTD.		       *
-* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL.		       *
-* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
-* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE	       *
-* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
-* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED,       *
-* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.   *
-*									       *
-* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
-* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL    *
-* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K.  *
-* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI).    *
-********************************************************************************
-* mv_gen_reg.h - Marvell 64360 and 64460 Internal registers definition file.
-*
-* DESCRIPTION:
-*	None.
-*
-* DEPENDENCIES:
-*	None.
-*
-*******************************************************************************/
-
-#ifndef __INCmv_gen_regh
-#define __INCmv_gen_regh
-
-
-/* Supported by the Atlantis */
-#define INCLUDE_PCI_1
-#define INCLUDE_PCI_0_ARBITER
-#define INCLUDE_PCI_1_ARBITER
-#define INCLUDE_SNOOP_SUPPORT
-#define INCLUDE_P2P
-#define INCLUDE_ETH_PORT_2
-#define INCLUDE_CPU_MAPPING
-#define INCLUDE_MPSC
-
-/* Not supported features */
-#undef	INCLUDE_CNTMR_4_7
-#undef	INCLUDE_DMA_4_7
-
-
-/****************************************/
-/* Processor Address Space				*/
-/****************************************/
-/* DDR SDRAM BAR and size registers */
-
-/* Sdram's BAR'S */
-#define SCS_0_LOW_DECODE_ADDRESS			0x008
-#define SCS_0_HIGH_DECODE_ADDRESS			0x010
-#define SCS_1_LOW_DECODE_ADDRESS			0x208
-#define SCS_1_HIGH_DECODE_ADDRESS			0x210
-#define SCS_2_LOW_DECODE_ADDRESS			0x018
-#define SCS_2_HIGH_DECODE_ADDRESS			0x020
-#define SCS_3_LOW_DECODE_ADDRESS			0x218
-#define SCS_3_HIGH_DECODE_ADDRESS			0x220
-
-/* Make it fit the MV64360 and MV64460 Lowlevel driver */
-#define CS_0_BASE_ADDR			SCS_0_LOW_DECODE_ADDRESS
-#define CS_0_SIZE			SCS_0_HIGH_DECODE_ADDRESS
-#define CS_1_BASE_ADDR		SCS_1_LOW_DECODE_ADDRESS
-#define CS_1_SIZE			SCS_1_HIGH_DECODE_ADDRESS
-#define CS_2_BASE_ADDR		SCS_2_LOW_DECODE_ADDRESS
-#define CS_2_SIZE			SCS_2_HIGH_DECODE_ADDRESS
-#define CS_3_BASE_ADDR		SCS_3_LOW_DECODE_ADDRESS
-#define CS_3_SIZE			SCS_3_HIGH_DECODE_ADDRESS
-
-/* Devices BAR'S */
-#define CS_0_LOW_DECODE_ADDRESS			0x028
-#define CS_0_HIGH_DECODE_ADDRESS			0x030
-#define CS_1_LOW_DECODE_ADDRESS			0x228
-#define CS_1_HIGH_DECODE_ADDRESS			0x230
-#define CS_2_LOW_DECODE_ADDRESS			0x248
-#define CS_2_HIGH_DECODE_ADDRESS			0x250
-#define CS_3_LOW_DECODE_ADDRESS			0x038
-#define CS_3_HIGH_DECODE_ADDRESS			0x040
-#define BOOTCS_LOW_DECODE_ADDRESS			0x238
-#define BOOTCS_HIGH_DECODE_ADDRESS			0x240
-
-/* Make it fit the MV64360 and MV64460 Lowlevel driver */
-/* Devices BAR and size registers */
-
-#define DEV_CS0_BASE_ADDR	CS_0_LOW_DECODE_ADDRESS
-#define DEV_CS0_SIZE			CS_0_HIGH_DECODE_ADDRESS
-#define DEV_CS1_BASE_ADDR	CS_1_LOW_DECODE_ADDRESS
-#define DEV_CS1_SIZE		CS_1_HIGH_DECODE_ADDRESS
-#define DEV_CS2_BASE_ADDR	CS_2_LOW_DECODE_ADDRESS
-#define DEV_CS2_SIZE			CS_2_HIGH_DECODE_ADDRESS
-#define DEV_CS3_BASE_ADDR		CS_3_LOW_DECODE_ADDRESS
-#define DEV_CS3_SIZE		CS_3_HIGH_DECODE_ADDRESS
-#define BOOTCS_BASE_ADDR	BOOTCS_LOW_DECODE_ADDRESS
-#define BOOTCS_SIZE		BOOTCS_HIGH_DECODE_ADDRESS
-
-/* PCI 0 BAR and size registers	 old names of evb64260*/
-
-#define PCI_0I_O_LOW_DECODE_ADDRESS			0x048
-#define PCI_0I_O_HIGH_DECODE_ADDRESS			0x050
-#define PCI_0MEMORY0_LOW_DECODE_ADDRESS		0x058
-#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS		0x060
-#define PCI_0MEMORY1_LOW_DECODE_ADDRESS		0x080
-#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS		0x088
-#define PCI_0MEMORY2_LOW_DECODE_ADDRESS		0x258
-#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS		0x260
-#define PCI_0MEMORY3_LOW_DECODE_ADDRESS		0x280
-#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS		0x288
-
-/* Make it fit the MV64360 and MV64460 Lowlevel driver */
-#define PCI_0_IO_BASE_ADDR						0x048
-#define PCI_0_IO_SIZE							0x050
-#define PCI_0_MEMORY0_BASE_ADDR					0x058
-#define PCI_0_MEMORY0_SIZE						0x060
-#define PCI_0_MEMORY1_BASE_ADDR					0x080
-#define PCI_0_MEMORY1_SIZE						0x088
-#define PCI_0_MEMORY2_BASE_ADDR					0x258
-#define PCI_0_MEMORY2_SIZE						0x260
-#define PCI_0_MEMORY3_BASE_ADDR					0x280
-#define PCI_0_MEMORY3_SIZE						0x288
-
-/* PCI 1 BAR and size registers	 old names of evb64260*/
-#define PCI_1I_O_LOW_DECODE_ADDRESS			0x090
-#define PCI_1I_O_HIGH_DECODE_ADDRESS			0x098
-#define PCI_1MEMORY0_LOW_DECODE_ADDRESS		0x0a0
-#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS		0x0a8
-#define PCI_1MEMORY1_LOW_DECODE_ADDRESS		0x0b0
-#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS		0x0b8
-#define PCI_1MEMORY2_LOW_DECODE_ADDRESS		0x2a0
-#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS		0x2a8
-#define PCI_1MEMORY3_LOW_DECODE_ADDRESS		0x2b0
-#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS		0x2b8
-
-/* Make it fit the MV64360 and MV64460 Lowlevel driver */
-#define PCI_1_IO_BASE_ADDR						0x090
-#define PCI_1_IO_SIZE							0x098
-#define PCI_1_MEMORY0_BASE_ADDR					0x0a0
-#define PCI_1_MEMORY0_SIZE						0x0a8
-#define PCI_1_MEMORY1_BASE_ADDR					0x0b0
-#define PCI_1_MEMORY1_SIZE						0x0b8
-#define PCI_1_MEMORY2_BASE_ADDR					0x2a0
-#define PCI_1_MEMORY2_SIZE						0x2a8
-#define PCI_1_MEMORY3_BASE_ADDR					0x2b0
-#define PCI_1_MEMORY3_SIZE						0x2b8
-
-/* internal registers space base address */
-#define INTERNAL_SPACE_DECODE				0x068
-#define INTERNAL_SPACE_BASE_ADDR				INTERNAL_SPACE_DECODE
-
-/* SRAM base address */
-#define INTEGRATED_SRAM_BASE_ADDR				0x268
-
-/* Enables the CS , DEV_CS , PCI 0 and PCI 1
-   windows above */
-#define BASE_ADDR_ENABLE						0x278
-
-
-#define CPU_0_LOW_DECODE_ADDRESS				0x290
-#define CPU_0_HIGH_DECODE_ADDRESS				0x298
-#define CPU_1_LOW_DECODE_ADDRESS				0x2c0
-#define CPU_1_HIGH_DECODE_ADDRESS				0x2c8
-
-/****************************************/
-/* PCI remap registers			*/
-/****************************************/
-/*****************************************************************************************/
-      /* PCI 0 */
-/* old fashion evb 64260 */
-#define PCI_0I_O_ADDRESS_REMAP				0x0f0
-#define PCI_0MEMORY0_ADDRESS_REMAP			0x0f8
-#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP		0x320
-#define PCI_0MEMORY1_ADDRESS_REMAP			0x100
-#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP		0x328
-#define PCI_0MEMORY2_ADDRESS_REMAP			0x2f8
-#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP		0x330
-#define PCI_0MEMORY3_ADDRESS_REMAP			0x300
-#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP		0x338
-
-#define PCI_0_IO_ADDR_REMAP						PCI_0I_O_ADDRESS_REMAP
-#define PCI_0_MEMORY0_LOW_ADDR_REMAP				PCI_0MEMORY0_ADDRESS_REMAP
-#define PCI_0_MEMORY0_HIGH_ADDR_REMAP				PCI_0MEMORY0_HIGH_ADDRESS_REMAP
-#define PCI_0_MEMORY1_LOW_ADDR_REMAP				PCI_0MEMORY1_ADDRESS_REMAP
-#define PCI_0_MEMORY1_HIGH_ADDR_REMAP				PCI_0MEMORY1_HIGH_ADDRESS_REMAP
-#define PCI_0_MEMORY2_LOW_ADDR_REMAP				PCI_0MEMORY2_ADDRESS_REMAP
-#define PCI_0_MEMORY2_HIGH_ADDR_REMAP				PCI_0MEMORY2_HIGH_ADDRESS_REMAP
-#define PCI_0_MEMORY3_LOW_ADDR_REMAP				PCI_0MEMORY3_ADDRESS_REMAP
-#define PCI_0_MEMORY3_HIGH_ADDR_REMAP				PCI_0MEMORY3_HIGH_ADDRESS_REMAP
-
-       /* PCI 1 */
-/* old fashion evb 64260 */
-#define PCI_1I_O_ADDRESS_REMAP				0x108
-#define PCI_1MEMORY0_ADDRESS_REMAP			0x110
-#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP		0x340
-#define PCI_1MEMORY1_ADDRESS_REMAP			0x118
-#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP		0x348
-#define PCI_1MEMORY2_ADDRESS_REMAP			0x310
-#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP		0x350
-#define PCI_1MEMORY3_ADDRESS_REMAP			0x318
-#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP		0x358
-
-#define PCI_1_IO_ADDR_REMAP						PCI_1I_O_ADDRESS_REMAP
-#define PCI_1_MEMORY0_LOW_ADDR_REMAP				PCI_1MEMORY0_ADDRESS_REMAP
-#define PCI_1_MEMORY0_HIGH_ADDR_REMAP				PCI_1MEMORY0_HIGH_ADDRESS_REMAP
-#define PCI_1_MEMORY1_LOW_ADDR_REMAP				PCI_1MEMORY1_ADDRESS_REMAP
-#define PCI_1_MEMORY1_HIGH_ADDR_REMAP				PCI_1MEMORY1_HIGH_ADDRESS_REMAP
-#define PCI_1_MEMORY2_LOW_ADDR_REMAP				PCI_1MEMORY2_ADDRESS_REMAP
-#define PCI_1_MEMORY2_HIGH_ADDR_REMAP				PCI_1MEMORY2_HIGH_ADDRESS_REMAP
-#define PCI_1_MEMORY3_LOW_ADDR_REMAP				PCI_1MEMORY3_ADDRESS_REMAP
-#define PCI_1_MEMORY3_HIGH_ADDR_REMAP				PCI_1MEMORY3_HIGH_ADDRESS_REMAP
-
-/* old fashion evb 64260 */
-#define CPU_PCI_0_HEADERS_RETARGET_CONTROL			0x3b0
-#define CPU_PCI_0_HEADERS_RETARGET_BASE				0x3b8
-#define CPU_PCI_1_HEADERS_RETARGET_CONTROL			0x3c0
-#define CPU_PCI_1_HEADERS_RETARGET_BASE				0x3c8
-#define CPU_GE_HEADERS_RETARGET_CONTROL				0x3d0
-#define CPU_GE_HEADERS_RETARGET_BASE				0x3d8
-
-/* MV64360 and MV64460 no changes needed*/
-/*****************************************************************************************/
-
-/****************************************/
-/*	   CPU Control Registers	*/
-/****************************************/
-/* CPU MASTER CONTROL REGISTER */
-#define CPU_CONFIGURATION				0x000
-#define CPU_MASTER_CONTROL				0x160
-
-#define CPU_CONFIG							0x000
-#define CPU_MODE							0x120
-#define CPU_MASTER_CONTROL						0x160
-/* new in MV64360 and MV64460 */
-#define CPU_CROSS_BAR_CONTROL_LOW				0x150
-#define CPU_CROSS_BAR_CONTROL_HIGH				0x158
-#define CPU_CROSS_BAR_TIMEOUT					0x168
-
-/****************************************/
-/* SMP RegisterS			*/
-/****************************************/
-
-#define SMP_WHO_AM_I							0x200
-#define SMP_CPU0_DOORBELL						0x214
-#define SMP_CPU0_DOORBELL_CLEAR					0x21C
-#define SMP_CPU1_DOORBELL						0x224
-#define SMP_CPU1_DOORBELL_CLEAR					0x22C
-#define SMP_CPU0_DOORBELL_MASK					0x234
-#define SMP_CPU1_DOORBELL_MASK					0x23C
-#define SMP_SEMAPHOR0							0x244
-#define SMP_SEMAPHOR1							0x24c
-#define SMP_SEMAPHOR2							0x254
-#define SMP_SEMAPHOR3							0x25c
-#define SMP_SEMAPHOR4							0x264
-#define SMP_SEMAPHOR5							0x26c
-#define SMP_SEMAPHOR6							0x274
-#define SMP_SEMAPHOR7							0x27c
-
-
-/****************************************/
-/* CPU Sync Barrier				*/
-/****************************************/
-#define CPU_0_SYNC_BARRIER_TRIGGER				0x0c0
-#define CPU_0_SYNC_BARRIER_VIRTUAL				0x0c8
-#define CPU_1_SYNC_BARRIER_TRIGGER				0x0d0
-#define CPU_1_SYNC_BARRIER_VIRTUAL				0x0d8
-
-
-/****************************************/
-/* CPU Access Protect			*/
-/****************************************/
-
-#define CPU_LOW_PROTECT_ADDRESS_0			    0x180
-#define CPU_HIGH_PROTECT_ADDRESS_0			    0x188
-#define CPU_LOW_PROTECT_ADDRESS_1			    0x190
-#define CPU_HIGH_PROTECT_ADDRESS_1			    0x198
-#define CPU_LOW_PROTECT_ADDRESS_2			    0x1a0
-#define CPU_HIGH_PROTECT_ADDRESS_2			    0x1a8
-#define CPU_LOW_PROTECT_ADDRESS_3			    0x1b0
-#define CPU_HIGH_PROTECT_ADDRESS_3			    0x1b8
-/*#define CPU_LOW_PROTECT_ADDRESS_4			      0x1c0
-#define CPU_HIGH_PROTECT_ADDRESS_4			    0x1c8
-#define CPU_LOW_PROTECT_ADDRESS_5			    0x1d0
-#define CPU_HIGH_PROTECT_ADDRESS_5			    0x1d8
-#define CPU_LOW_PROTECT_ADDRESS_6			    0x1e0
-#define CPU_HIGH_PROTECT_ADDRESS_6			    0x1e8
-#define CPU_LOW_PROTECT_ADDRESS_7			    0x1f0
-#define CPU_HIGH_PROTECT_ADDRESS_7			    0x1f8
-*/
-
-#define CPU_PROTECT_WINDOW_0_BASE_ADDR		     CPU_LOW_PROTECT_ADDRESS_0 /* 0x180 */
-#define CPU_PROTECT_WINDOW_0_SIZE			    CPU_HIGH_PROTECT_ADDRESS_0 /* 0x188 */
-#define CPU_PROTECT_WINDOW_1_BASE_ADDR		     CPU_LOW_PROTECT_ADDRESS_1 /* 0x190 */
-#define CPU_PROTECT_WINDOW_1_SIZE			    CPU_HIGH_PROTECT_ADDRESS_1 /* 0x198 */
-#define CPU_PROTECT_WINDOW_2_BASE_ADDR		     CPU_LOW_PROTECT_ADDRESS_2 /*0x1a0 */
-#define CPU_PROTECT_WINDOW_2_SIZE			    CPU_HIGH_PROTECT_ADDRESS_2 /* 0x1a8 */
-#define CPU_PROTECT_WINDOW_3_BASE_ADDR		     CPU_LOW_PROTECT_ADDRESS_3 /* 0x1b0 */
-#define CPU_PROTECT_WINDOW_3_SIZE			    CPU_HIGH_PROTECT_ADDRESS_3 /* 0x1b8 */
-
-
-/****************************************/
-/*	    Snoop Control			*/
-/****************************************/
-
-/*#define SNOOP_BASE_ADDRESS_0				      0x380
-#define SNOOP_TOP_ADDRESS_0				    0x388
-#define SNOOP_BASE_ADDRESS_1				    0x390
-#define SNOOP_TOP_ADDRESS_1				    0x398
-#define SNOOP_BASE_ADDRESS_2				    0x3a0
-#define SNOOP_TOP_ADDRESS_2				    0x3a8
-#define SNOOP_BASE_ADDRESS_3				    0x3b0
-#define SNOOP_TOP_ADDRESS_3				    0x3b8
-*/
-
-/****************************************/
-/*  Integrated SRAM Registers		*/
-/****************************************/
-
-#define SRAM_CONFIG						0x380
-#define SRAM_TEST_MODE						0x3F4
-#define SRAM_ERROR_CAUSE					0x388
-#define SRAM_ERROR_ADDR						0x390
-#define SRAM_ERROR_ADDR_HIGH					0x3F8
-#define SRAM_ERROR_DATA_LOW					0x398
-#define SRAM_ERROR_DATA_HIGH					0x3a0
-#define SRAM_ERROR_DATA_PARITY					0x3a8
-
-/****************************************/
-/*	    CPU Error Report			*/
-/****************************************/
-
-#define CPU_ERROR_ADDRESS_LOW		0x070
-#define CPU_ERROR_ADDRESS_HIGH		0x078
-#define CPU_ERROR_DATA_LOW					0x128
-#define CPU_ERROR_DATA_HIGH					0x130
-#define CPU_ERROR_PARITY					0x138
-#define CPU_ERROR_CAUSE						0x140
-#define CPU_ERROR_MASK						0x148
-
-#define CPU_ERROR_ADDR_LOW					CPU_ERROR_ADDRESS_LOW  /* 0x0701 */
-#define CPU_ERROR_ADDR_HIGH					CPU_ERROR_ADDRESS_HIGH	/* 0x0781 */
-
-/****************************************/
-/*	    Pslave Debug			*/
-/*	CPU Interface Debug Registers	*/
-/****************************************/
-
-#define X_0_ADDRESS						0x360
-#define X_0_COMMAND_ID						0x368
-#define X_1_ADDRESS						0x370
-#define X_1_COMMAND_ID						0x378
- /*#define WRITE_DATA_LOW					0x3c01 */
- /*#define WRITE_DATA_HIGH					0x3c81 */
- /*#define WRITE_BYTE_ENABLE					0x3e01 */
- /*#define READ_DATA_LOW					0x3d01 */
- /*#define READ_DATA_HIGH					0x3d81 */
- /*#define READ_ID						0x3e81 */
-
-#define PUNIT_SLAVE_DEBUG_LOW					X_0_ADDRESS  /* 0x3601 */
-#define PUNIT_SLAVE_DEBUG_HIGH					X_0_COMMAND_ID	/* 0x3681 */
-#define PUNIT_MASTER_DEBUG_LOW					X_1_ADDRESS  /* 0x3701 */
-#define PUNIT_MASTER_DEBUG_HIGH				   X_1_COMMAND_ID  /* 0x3781 */
-#define PUNIT_MMASK						0x3e4
-
-
-/****************************************/
-/* SDRAM and Device Address Space		*/
-/****************************************/
-
-/****************************************/
-/* SDRAM Configuration			*/
-/****************************************/
-#define SDRAM_CONFIG						0x1400	/* MV64260 0x448 some changes*/
-#define D_UNIT_CONTROL_LOW					0x1404	/* NEW in MV64360 and MV64460 */
-#define D_UNIT_CONTROL_HIGH					0x1424	/* NEW in MV64360 and MV64460 */
-#define SDRAM_TIMING_CONTROL_LOW			0x1408	/* MV64260 0x4b4 new SDRAM TIMING REGISTER */
-#define SDRAM_TIMING_CONTROL_HIGH			0x140c	/* MV64260 0x4b4 new SDRAM TIMING REGISTER */
-#define SDRAM_ADDR_CONTROL				    0x1410	/* MV64260 0x47c some changes*/
-#define SDRAM_OPEN_PAGES_CONTROL			0x1414	/* NEW in MV64360 and MV64460 */
-#define SDRAM_OPERATION						0x1418	/* MV64260 0x474 some changes*/
-#define SDRAM_MODE						0x141c	/* NEW in MV64360 and MV64460 */
-#define EXTENDED_DRAM_MODE					0x1420	/* NEW in MV64360 and MV64460 */
-#define SDRAM_CROSS_BAR_CONTROL_LOW			0x1430	/* MV64260 0x4a8 NO changes*/
-#define SDRAM_CROSS_BAR_CONTROL_HIGH			0x1434	/* MV64260 0x4ac NO changes*/
-#define SDRAM_CROSS_BAR_TIMEOUT				0x1438	/* MV64260 0x4b0 NO changes*/
-#define SDRAM_ADDR_CTRL_PADS_CALIBRATION	0x14c0	/* what is this ??? */
-#define SDRAM_DATA_PADS_CALIBRATION			0x14c4	/* what is this ??? */
-/****************************************/
-/* SDRAM Configuration MV64260			*/
-/****************************************/
- /*#define SDRAM_CONFIGURATION			0x4481 */
- /*#define SDRAM_OPERATION_MODE			0x4741 */
- /*#define SDRAM_ADDRESS_DECODE		0x47c1 */
- /*#define SDRAM_UMA_CONTROL			0x4a4	eliminated in MV64360 and MV64460 */
- /*#define SDRAM_CROSS_BAR_CONTROL_LOW	0x4a81 */
- /*#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac1 */
- /*#define SDRAM_CROSS_BAR_TIMEOUT		0x4b01 */
- /*#define SDRAM_TIMING				0x4b41 */
-
-
-/****************************************/
-/* SDRAM Error Report			*/
-/****************************************/
-#define SDRAM_ERROR_DATA_LOW				0x1444	/* MV64260 0x484 NO changes*/
-#define SDRAM_ERROR_DATA_HIGH					0x1440	/* MV64260 0x480 NO changes*/
-#define SDRAM_ERROR_ADDR					0x1450	/* MV64260 0x490 NO changes*/
-#define SDRAM_RECEIVED_ECC					0x1448	/* MV64260 0x488 NO changes*/
-#define SDRAM_CALCULATED_ECC					0x144c	/* MV64260 0x48c NO changes*/
-#define SDRAM_ECC_CONTROL					0x1454	/* MV64260 0x494 NO changes*/
-#define SDRAM_ECC_ERROR_COUNTER				0x1458	/* MV64260 0x498 NO changes*/
-#define SDRAM_MMASK					0x1B40	/* NEW Register in MV64360 and MV64460 DO NOT USE !!!*/
-/****************************************/
-/* SDRAM Error Report MV64260			*/
-/****************************************/
- /*#define SDRAM_ERROR_DATA_LOW					0x4841 */
- /*#define SDRAM_ERROR_DATA_HIGH				0x4801 */
- /*#define SDRAM_AND_DEVICE_ERROR_ADDRESS		0x4901 */
- /*#define SDRAM_RECEIVED_ECC				       0x4881 */
- /*#define SDRAM_CALCULATED_ECC					0x48c1 */
- /*#define SDRAM_ECC_CONTROL					0x4941 */
- /*#define SDRAM_ECC_ERROR_COUNTER			0x4981 */
-
-/******************************************/
-/*  Controlled Delay Line (CDL) Registers */
-/******************************************/
-#define DFCDL_CONFIG0						0x1480
-#define DFCDL_CONFIG1						0x1484
-#define DLL_WRITE						0x1488
-#define DLL_READ						0x148c
-#define SRAM_ADDR						0x1490
-#define SRAM_DATA0						0x1494
-#define SRAM_DATA1						0x1498
-#define SRAM_DATA2						0x149c
-#define DFCL_PROBE						0x14a0
-
-
-/****************************************/
-/* SDRAM Parameters only in MV64260			*/
-/****************************************/
-
- /*#define SDRAM_BANK0PARAMETERS				0x44C	eliminated in MV64360 and MV64460 */
- /*#define SDRAM_BANK1PARAMETERS				0x450	eliminated in MV64360 and MV64460 */
- /*#define SDRAM_BANK2PARAMETERS				0x454	eliminated in MV64360 and MV64460 */
- /*#define SDRAM_BANK3PARAMETERS				0x458	eliminated in MV64360 and MV64460 */
-
-/******************************************/
-/*   Debug Registers			  */
-/******************************************/
-
-#define DUNIT_DEBUG_LOW						0x1460
-#define DUNIT_DEBUG_HIGH					0x1464
-#define DUNIT_MMASK						0x1b40
-
-/****************************************/
-/* SDunit Debug (for internal use)	*/
-/****************************************/
-
-#define X0_ADDRESS					    0x500
-#define X0_COMMAND_AND_ID				    0x504
-#define X0_WRITE_DATA_LOW				    0x508
-#define X0_WRITE_DATA_HIGH				    0x50c
-#define X0_WRITE_BYTE_ENABLE				    0x518
-#define X0_READ_DATA_LOW				    0x510
-#define X0_READ_DATA_HIGH				    0x514
-#define X0_READ_ID					    0x51c
-#define X1_ADDRESS					    0x520
-#define X1_COMMAND_AND_ID				    0x524
-#define X1_WRITE_DATA_LOW				    0x528
-#define X1_WRITE_DATA_HIGH				    0x52c
-#define X1_WRITE_BYTE_ENABLE				    0x538
-#define X1_READ_DATA_LOW				    0x530
-#define X1_READ_DATA_HIGH				    0x534
-#define X1_READ_ID					    0x53c
-#define X0_SNOOP_ADDRESS				    0x540
-#define X0_SNOOP_COMMAND				    0x544
-#define X1_SNOOP_ADDRESS				    0x548
-#define X1_SNOOP_COMMAND				    0x54c
-
-/****************************************/
-/* Device Parameters					*/
-/****************************************/
-
-#define DEVICE_BANK0PARAMETERS				0x45c
-#define DEVICE_BANK1PARAMETERS				0x460
-#define DEVICE_BANK2PARAMETERS				0x464
-#define DEVICE_BANK3PARAMETERS				0x468
-#define DEVICE_BOOT_BANK_PARAMETERS			0x46c
-#define DEVICE_CONTROL							0x4c0
-#define DEVICE_CROSS_BAR_CONTROL_LOW				0x4c8
-#define DEVICE_CROSS_BAR_CONTROL_HIGH				0x4cc
-#define DEVICE_CROSS_BAR_TIMEOUT				0x4c4
-
-/****************************************/
-/* Device Parameters					*/
-/****************************************/
-
-#define DEVICE_BANK0_PARAMETERS			DEVICE_BANK0PARAMETERS	/* 0x45c1 */
-#define DEVICE_BANK1_PARAMETERS			DEVICE_BANK1PARAMETERS	/* 0x4601 */
-#define DEVICE_BANK2_PARAMETERS			DEVICE_BANK2PARAMETERS	/* 0x4641 */
-#define DEVICE_BANK3_PARAMETERS			DEVICE_BANK3PARAMETERS	/* 0x4681 */
-/*#define DEVICE_BOOT_BANK_PARAMETERS			 0x46c1 */
-#define DEVICE_INTERFACE_CONTROL				DEVICE_CONTROL	/* 0x4c01 */
-#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		DEVICE_CROSS_BAR_CONTROL_LOW  /* 0x4c81 */
-#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		DEVICE_CROSS_BAR_CONTROL_HIGH  /* 0x4cc1 */
-#define DEVICE_INTERFACE_CROSS_BAR_TIMEOUT			DEVICE_CROSS_BAR_TIMEOUT  /* 0x4c41 */
-
-
-/****************************************/
-/* Device Interrupt					*/
-/****************************************/
-
-#define DEVICE_INTERRUPT_CAUSE						0x4d0
-#define DEVICE_INTERRUPT_MASK						0x4d4
-#define DEVICE_ERROR_ADDRESS						0x4d8
- /*#define DEVICE_INTERRUPT_CAUSE				0x4d01 */
- /*#define DEVICE_INTERRUPT_MASK				0x4d41 */
-#define DEVICE_ERROR_ADDR				DEVICE_ERROR_ADDRESS  /*0x4d81 */
-#define DEVICE_ERROR_DATA				0x4dc
-#define DEVICE_ERROR_PARITY					0x4e0
-
-/****************************************/
-/* Device debug registers			*/
-/****************************************/
-
-#define DEVICE_DEBUG_LOW					0x4e4
-#define DEVICE_DEBUG_HIGH				0x4e8
-#define RUNIT_MMASK							0x4f0
-
-/****************************************/
-/* DMA Record							*/
-/****************************************/
-
- /*#define CHANNEL4_DMA_BYTE_COUNT			0x9001 */
- /*#define CHANNEL5_DMA_BYTE_COUNT			0x9041 */
- /*#define CHANNEL6_DMA_BYTE_COUNT			0x9081 */
- /*#define CHANNEL7_DMA_BYTE_COUNT			0x90C1 */
- /*#define CHANNEL4_DMA_SOURCE_ADDRESS		0x9101 */
- /*#define CHANNEL5_DMA_SOURCE_ADDRESS		0x9141 */
- /*#define CHANNEL6_DMA_SOURCE_ADDRESS		0x9181 */
- /*#define CHANNEL7_DMA_SOURCE_ADDRESS		0x91C1 */
- /*#define CHANNEL4_DMA_DESTINATION_ADDRESS		0x9201 */
- /*#define CHANNEL5_DMA_DESTINATION_ADDRESS		0x9241 */
- /*#define CHANNEL6_DMA_DESTINATION_ADDRESS		0x9281 */
- /*#define CHANNEL7_DMA_DESTINATION_ADDRESS		0x92C1 */
- /*#define CHANNEL4NEXT_RECORD_POINTER			0x9301 */
- /*#define CHANNEL5NEXT_RECORD_POINTER			0x9341 */
- /*#define CHANNEL6NEXT_RECORD_POINTER			0x9381 */
- /*#define CHANNEL7NEXT_RECORD_POINTER			0x93C1 */
- /*#define CHANNEL4CURRENT_DESCRIPTOR_POINTER		0x9701 */
- /*#define CHANNEL5CURRENT_DESCRIPTOR_POINTER		0x9741 */
- /*#define CHANNEL6CURRENT_DESCRIPTOR_POINTER		0x9781 */
- /*#define CHANNEL7CURRENT_DESCRIPTOR_POINTER		0x97C1 */
- /*#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x8901 */
- /*#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x8941 */
- /*#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x8981 */
- /*#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x89c1 */
- /*#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x9901 */
- /*#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x9941 */
- /*#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x9981 */
- /*#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x99c1 */
- /*#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x8a01 */
- /*#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x8a41 */
- /*#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x8a81 */
- /*#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x8ac1 */
- /*#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x9a01 */
- /*#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x9a41 */
- /*#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x9a81 */
- /*#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x9ac1 */
- /*#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b01 */
- /*#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b41 */
- /*#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b81 */
- /*#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8bc1 */
- /*#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b01 */
- /*#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b41 */
- /*#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b81 */
- /*#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9bc1 */
-
-/****************************************/
-/* DMA Channel Control					*/
-/****************************************/
-
-#define CHANNEL0CONTROL					0x840
-#define CHANNEL0CONTROL_HIGH				0x880
-#define CHANNEL1CONTROL					0x844
-#define CHANNEL1CONTROL_HIGH				0x884
-#define CHANNEL2CONTROL					0x848
-#define CHANNEL2CONTROL_HIGH				0x888
-#define CHANNEL3CONTROL					0x84C
-#define CHANNEL3CONTROL_HIGH				0x88C
-
-#define DMA_CHANNEL0_CONTROL				CHANNEL0CONTROL	 /*0x8401 */
-#define DMA_CHANNEL0_CONTROL_HIGH			CHANNEL0CONTROL_HIGH  /*0x8801 */
-#define DMA_CHANNEL1_CONTROL				CHANNEL1CONTROL	 /* 0x8441 */
-#define DMA_CHANNEL1_CONTROL_HIGH			CHANNEL1CONTROL_HIGH  /*0x8841 */
-#define DMA_CHANNEL2_CONTROL				CHANNEL2CONTROL	 /*0x8481 */
-#define DMA_CHANNEL2_CONTROL_HIGH			CHANNEL2CONTROL_HIGH  /*0x8881 */
-#define DMA_CHANNEL3_CONTROL				CHANNEL3CONTROL	 /*0x84C1 */
-#define DMA_CHANNEL3_CONTROL_HIGH			CHANNEL3CONTROL_HIGH  /*0x88C1 */
-
- /*#define CHANNEL4CONTROL				0x9401 */
- /*#define CHANNEL4CONTROL_HIGH				0x9801 */
- /*#define CHANNEL5CONTROL				0x9441 */
- /*#define CHANNEL5CONTROL_HIGH				0x9841 */
- /*#define CHANNEL6CONTROL				0x9481 */
- /*#define CHANNEL6CONTROL_HIGH				0x9881 */
- /*#define CHANNEL7CONTROL				0x94C1 */
- /*#define CHANNEL7CONTROL_HIGH				0x98C1 */
-
-
-/****************************************/
-/* DMA Arbiter							*/
-/****************************************/
-
- /*#define ARBITER_CONTROL_0_3				0x8601 */
-#define ARBITER_CONTROL_4_7				0x960
-/****************************************/
-/*	     IDMA Registers		*/
-/****************************************/
-
-#define DMA_CHANNEL0_BYTE_COUNT					CHANNEL0_DMA_BYTE_COUNT	 /*0x8001 */
-#define DMA_CHANNEL1_BYTE_COUNT					CHANNEL1_DMA_BYTE_COUNT	 /*0x8041 */
-#define DMA_CHANNEL2_BYTE_COUNT					CHANNEL2_DMA_BYTE_COUNT	 /*0x8081 */
-#define DMA_CHANNEL3_BYTE_COUNT					CHANNEL3_DMA_BYTE_COUNT	 /*0x80C1 */
-#define DMA_CHANNEL0_SOURCE_ADDR				CHANNEL0_DMA_SOURCE_ADDRESS  /*0x8101 */
-#define DMA_CHANNEL1_SOURCE_ADDR				CHANNEL1_DMA_SOURCE_ADDRESS  /*0x8141 */
-#define DMA_CHANNEL2_SOURCE_ADDR				CHANNEL2_DMA_SOURCE_ADDRESS  /*0x8181 */
-#define DMA_CHANNEL3_SOURCE_ADDR				CHANNEL3_DMA_SOURCE_ADDRESS  /*0x81c1 */
-#define DMA_CHANNEL0_DESTINATION_ADDR				CHANNEL0_DMA_DESTINATION_ADDRESS  /*0x8201 */
-#define DMA_CHANNEL1_DESTINATION_ADDR				CHANNEL1_DMA_DESTINATION_ADDRESS  /*0x8241 */
-#define DMA_CHANNEL2_DESTINATION_ADDR				CHANNEL2_DMA_DESTINATION_ADDRESS  /*0x8281 */
-#define DMA_CHANNEL3_DESTINATION_ADDR				CHANNEL3_DMA_DESTINATION_ADDRESS  /*0x82C1 */
-#define DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		CHANNEL0NEXT_RECORD_POINTER  /*0x8301 */
-#define DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		CHANNEL1NEXT_RECORD_POINTER  /*0x8341 */
-#define DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		CHANNEL2NEXT_RECORD_POINTER  /*0x8381 */
-#define DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		CHANNEL3NEXT_RECORD_POINTER  /*0x83C1 */
-#define DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		CHANNEL0CURRENT_DESCRIPTOR_POINTER  /*0x8701 */
-#define DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		CHANNEL1CURRENT_DESCRIPTOR_POINTER  /*0x8741 */
-#define DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		CHANNEL2CURRENT_DESCRIPTOR_POINTER  /*0x8781 */
-#define DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		CHANNEL3CURRENT_DESCRIPTOR_POINTER  /*0x87C1 */
-
-#define CHANNEL3CURRENT_DESCRIPTOR_POINTER		0x87C
-#define CHANNEL2CURRENT_DESCRIPTOR_POINTER		0x878
-#define CHANNEL1CURRENT_DESCRIPTOR_POINTER		0x874
-#define CHANNEL0CURRENT_DESCRIPTOR_POINTER		0x870
-#define CHANNEL0NEXT_RECORD_POINTER			0x830
-#define CHANNEL1NEXT_RECORD_POINTER			0x834
-#define CHANNEL2NEXT_RECORD_POINTER			0x838
-#define CHANNEL3NEXT_RECORD_POINTER			0x83C
-#define CHANNEL0_DMA_DESTINATION_ADDRESS		0x820
-#define CHANNEL1_DMA_DESTINATION_ADDRESS		0x824
-#define CHANNEL2_DMA_DESTINATION_ADDRESS		0x828
-#define CHANNEL3_DMA_DESTINATION_ADDRESS		0x82C
-#define CHANNEL0_DMA_SOURCE_ADDRESS			0x810
-#define CHANNEL1_DMA_SOURCE_ADDRESS			0x814
-#define CHANNEL2_DMA_SOURCE_ADDRESS			0x818
-#define CHANNEL3_DMA_SOURCE_ADDRESS			0x81C
-#define CHANNEL0_DMA_BYTE_COUNT			0x800
-#define CHANNEL1_DMA_BYTE_COUNT			0x804
-#define CHANNEL2_DMA_BYTE_COUNT			0x808
-#define CHANNEL3_DMA_BYTE_COUNT			0x80C
-
- /*  IDMA Address Decoding Base Address Registers  */
-
-#define DMA_BASE_ADDR_REG0						0xa00
-#define DMA_BASE_ADDR_REG1						0xa08
-#define DMA_BASE_ADDR_REG2						0xa10
-#define DMA_BASE_ADDR_REG3						0xa18
-#define DMA_BASE_ADDR_REG4						0xa20
-#define DMA_BASE_ADDR_REG5						0xa28
-#define DMA_BASE_ADDR_REG6						0xa30
-#define DMA_BASE_ADDR_REG7						0xa38
-
- /*  IDMA Address Decoding Size Address Register   */
-
-#define DMA_SIZE_REG0							0xa04
-#define DMA_SIZE_REG1							0xa0c
-#define DMA_SIZE_REG2							0xa14
-#define DMA_SIZE_REG3							0xa1c
-#define DMA_SIZE_REG4							0xa24
-#define DMA_SIZE_REG5							0xa2c
-#define DMA_SIZE_REG6							0xa34
-#define DMA_SIZE_REG7							0xa3C
-
-    /* IDMA Address Decoding High Address Remap and Access
-		  Protection Registers			  */
-
-#define DMA_HIGH_ADDR_REMAP_REG0				0xa60
-#define DMA_HIGH_ADDR_REMAP_REG1				0xa64
-#define DMA_HIGH_ADDR_REMAP_REG2				0xa68
-#define DMA_HIGH_ADDR_REMAP_REG3				0xa6C
-#define DMA_BASE_ADDR_ENABLE_REG				0xa80
-#define DMA_CHANNEL0_ACCESS_PROTECTION_REG		0xa70
-#define DMA_CHANNEL1_ACCESS_PROTECTION_REG		   0xa74
-#define DMA_CHANNEL2_ACCESS_PROTECTION_REG		   0xa78
-#define DMA_CHANNEL3_ACCESS_PROTECTION_REG		   0xa7c
-#define DMA_ARBITER_CONTROL						0x860
-#define DMA_CROSS_BAR_TIMEOUT					0x8d0
-
- /*  IDMA Headers Retarget Registers   */
-
- /*#define CPU_IDMA_HEADERS_RETARGET_CONTROL			0x3e01 */
- /*#define CPU_IDMA_HEADERS_RETARGET_BASE			 0x3e81 */
-
-#define DMA_HEADERS_RETARGET_CONTROL			0xa84
-#define DMA_HEADERS_RETARGET_BASE			0xa88
-
-/****************************************/
-/* DMA Interrupt						*/
-/****************************************/
-
-#define CHANELS0_3_INTERRUPT_CAUSE			0x8c0
-#define CHANELS0_3_INTERRUPT_MASK			0x8c4
-#define CHANELS0_3_ERROR_ADDRESS			0x8c8
-#define CHANELS0_3_ERROR_SELECT				0x8cc
- /*#define CHANELS4_7_INTERRUPT_CAUSE			0x9c01 */
- /*#define CHANELS4_7_INTERRUPT_MASK			0x9c41 */
- /*#define CHANELS4_7_ERROR_ADDRESS			0x9c81 */
- /*#define CHANELS4_7_ERROR_SELECT			0x9cc1 */
-
-#define DMA_INTERRUPT_CAUSE_REG				CHANELS0_3_INTERRUPT_CAUSE  /*0x8c01 */
-#define DMA_INTERRUPT_CAUSE_MASK			CHANELS0_3_INTERRUPT_MASK  /*0x8c41 */
-#define DMA_ERROR_ADDR						CHANELS0_3_ERROR_ADDRESS  /*0x8c81 */
-#define DMA_ERROR_SELECT					CHANELS0_3_ERROR_SELECT	 /*0x8cc1 */
-
-
-/****************************************/
-/* DMA Debug (for internal use)		*/
-/****************************************/
-
-#define DMA_X0_ADDRESS						0x8e0
-#define DMA_X0_COMMAND_AND_ID				0x8e4
- /*#define DMA_X0_WRITE_DATA_LOW				0x8e81 */
- /*#define DMA_X0_WRITE_DATA_HIGH				0x8ec1 */
- /*#define DMA_X0_WRITE_BYTE_ENABLE				0x8f81 */
- /*#define DMA_X0_READ_DATA_LOW					0x8f01 */
- /*#define DMA_X0_READ_DATA_HIGH				0x8f41 */
- /*#define DMA_X0_READ_ID					0x8fc1 */
- /*#define DMA_X1_ADDRESS					0x9e01 */
- /*#define DMA_X1_COMMAND_AND_ID			0x9e41 */
- /*#define DMA_X1_WRITE_DATA_LOW				0x9e81 */
- /*#define DMA_X1_WRITE_DATA_HIGH				0x9ec1 */
- /*#define DMA_X1_WRITE_BYTE_ENABLE				0x9f81 */
- /*#define DMA_X1_READ_DATA_LOW					0x9f01 */
- /*#define DMA_X1_READ_DATA_HIGH				0x9f41 */
- /*#define DMA_X1_READ_ID					0x9fc1 */
-
- /*  IDMA Debug Register ( for internal use )	 */
-
-#define DMA_DEBUG_LOW						DMA_X0_ADDRESS	/* 0x8e01 */
-#define DMA_DEBUG_HIGH						DMA_X0_COMMAND_AND_ID  /*0x8e41 */
-#define DMA_SPARE						0xA8C
-
-
-/****************************************/
-/* Timer_Counter						*/
-/****************************************/
-
-#define TIMER_COUNTER0					0x850
-#define TIMER_COUNTER1					0x854
-#define TIMER_COUNTER2					0x858
-#define TIMER_COUNTER3					0x85C
-#define TIMER_COUNTER_0_3_CONTROL			0x864
-#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE		0x868
-#define TIMER_COUNTER_0_3_INTERRUPT_MASK		0x86c
- /*#define TIMER_COUNTER4					0x9501 */
- /*#define TIMER_COUNTER5					0x9541 */
- /*#define TIMER_COUNTER6					0x9581 */
- /*#define TIMER_COUNTER7					0x95C1 */
- /*#define TIMER_COUNTER_4_7_CONTROL			0x9641 */
- /*#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE		0x9681 */
- /*#define TIMER_COUNTER_4_7_INTERRUPT_MASK			0x96c1 */
-
-/****************************************/
-/* PCI Slave Address Decoding		*/
-/****************************************/
-/****************************************/
-/* PCI Slave Address Decoding registers */
-/****************************************/
-#define PCI_0_CS_0_BANK_SIZE					PCI_0SCS_0_BANK_SIZE  /*0xc081 */
-#define PCI_1_CS_0_BANK_SIZE					PCI_1SCS_0_BANK_SIZE  /* 0xc881 */
-#define PCI_0_CS_1_BANK_SIZE					PCI_0SCS_1_BANK_SIZE  /*0xd081 */
-#define PCI_1_CS_1_BANK_SIZE					PCI_1SCS_1_BANK_SIZE  /* 0xd881 */
-#define PCI_0_CS_2_BANK_SIZE					PCI_0SCS_2_BANK_SIZE  /*0xc0c1 */
-#define PCI_1_CS_2_BANK_SIZE					PCI_1SCS_2_BANK_SIZE  /*0xc8c1 */
-#define PCI_0_CS_3_BANK_SIZE					PCI_0SCS_3_BANK_SIZE  /*0xd0c1 */
-#define PCI_1_CS_3_BANK_SIZE					PCI_1SCS_3_BANK_SIZE  /*0xd8c1 */
-#define PCI_0_DEVCS_0_BANK_SIZE					PCI_0CS_0_BANK_SIZE  /*0xc101 */
-#define PCI_1_DEVCS_0_BANK_SIZE				    PCI_1CS_0_BANK_SIZE	 /*0xc901 */
-#define PCI_0_DEVCS_1_BANK_SIZE				    PCI_0CS_1_BANK_SIZE	 /*0xd101 */
-#define PCI_1_DEVCS_1_BANK_SIZE				    PCI_1CS_1_BANK_SIZE	 /* 0xd901 */
-#define PCI_0_DEVCS_2_BANK_SIZE				    PCI_0CS_2_BANK_SIZE	 /* 0xd181 */
-#define PCI_1_DEVCS_2_BANK_SIZE				    PCI_1CS_2_BANK_SIZE	 /*0xd981 */
-#define PCI_0_DEVCS_3_BANK_SIZE				    PCI_0CS_3_BANK_SIZE	 /* 0xc141 */
-#define PCI_1_DEVCS_3_BANK_SIZE				    PCI_1CS_3_BANK_SIZE	 /*0xc941 */
-#define PCI_0_DEVCS_BOOT_BANK_SIZE			PCI_0CS_BOOT_BANK_SIZE	/*0xd141 */
-#define PCI_1_DEVCS_BOOT_BANK_SIZE			PCI_1CS_BOOT_BANK_SIZE	/* 0xd941 */
-#define PCI_0_P2P_MEM0_BAR_SIZE				    PCI_0P2P_MEM0_BAR_SIZE  /*0xd1c1 */
-#define PCI_1_P2P_MEM0_BAR_SIZE				    PCI_1P2P_MEM0_BAR_SIZE  /*0xd9c1 */
-#define PCI_0_P2P_MEM1_BAR_SIZE				    PCI_0P2P_MEM1_BAR_SIZE  /*0xd201 */
-#define PCI_1_P2P_MEM1_BAR_SIZE				    PCI_1P2P_MEM1_BAR_SIZE  /*0xda01 */
-#define PCI_0_P2P_I_O_BAR_SIZE					PCI_0P2P_I_O_BAR_SIZE  /*0xd241 */
-#define PCI_1_P2P_I_O_BAR_SIZE					PCI_1P2P_I_O_BAR_SIZE  /*0xda41 */
-#define PCI_0_CPU_BAR_SIZE					PCI_0CPU_BAR_SIZE  /*0xd281 */
-#define PCI_1_CPU_BAR_SIZE					PCI_1CPU_BAR_SIZE  /*0xda81 */
-#define PCI_0_INTERNAL_SRAM_BAR_SIZE			PCI_0DAC_SCS_0_BANK_SIZE  /*0xe001 */
-#define PCI_1_INTERNAL_SRAM_BAR_SIZE			PCI_1DAC_SCS_0_BANK_SIZE  /*0xe801 */
-#define PCI_0_EXPANSION_ROM_BAR_SIZE			PCI_0EXPANSION_ROM_BAR_SIZE  /*0xd2c1 */
-#define PCI_1_EXPANSION_ROM_BAR_SIZE		       PCI_1EXPANSION_ROM_BAR_SIZE  /*0xd9c1 */
-#define PCI_0_BASE_ADDR_REG_ENABLE			PCI_0BASE_ADDRESS_REGISTERS_ENABLE  /*0xc3c1 */
-#define PCI_1_BASE_ADDR_REG_ENABLE			PCI_1BASE_ADDRESS_REGISTERS_ENABLE  /*0xcbc1 */
-#define PCI_0_CS_0_BASE_ADDR_REMAP		PCI_0SCS_0_BASE_ADDRESS_REMAP  /*0xc481 */
-#define PCI_1_CS_0_BASE_ADDR_REMAP		PCI_1SCS_0_BASE_ADDRESS_REMAP  /*0xcc81 */
-#define PCI_0_CS_1_BASE_ADDR_REMAP		PCI_0SCS_1_BASE_ADDRESS_REMAP  /*0xd481 */
-#define PCI_1_CS_1_BASE_ADDR_REMAP		PCI_1SCS_1_BASE_ADDRESS_REMAP  /*0xdc81 */
-#define PCI_0_CS_2_BASE_ADDR_REMAP		PCI_0SCS_2_BASE_ADDRESS_REMAP  /*0xc4c1 */
-#define PCI_1_CS_2_BASE_ADDR_REMAP		PCI_1SCS_2_BASE_ADDRESS_REMAP  /*0xccc1 */
-#define PCI_0_CS_3_BASE_ADDR_REMAP		PCI_0SCS_3_BASE_ADDRESS_REMAP  /*0xd4c1 */
-#define PCI_1_CS_3_BASE_ADDR_REMAP		PCI_1SCS_3_BASE_ADDRESS_REMAP /* 0xdcc1 */
-#define PCI_0_CS_0_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP
-#define PCI_1_CS_0_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP
-#define PCI_0_CS_1_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP
-#define PCI_1_CS_1_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP
-#define PCI_0_CS_2_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP
-#define PCI_1_CS_2_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP
-#define PCI_0_CS_3_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP
-#define PCI_1_CS_3_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP
-#define PCI_0_DEVCS_0_BASE_ADDR_REMAP		PCI_0CS_0_BASE_ADDRESS_REMAP  /*0xc501 */
-#define PCI_1_DEVCS_0_BASE_ADDR_REMAP		PCI_1CS_0_BASE_ADDRESS_REMAP  /*0xcd01 */
-#define PCI_0_DEVCS_1_BASE_ADDR_REMAP		PCI_0CS_1_BASE_ADDRESS_REMAP  /*0xd501 */
-#define PCI_1_DEVCS_1_BASE_ADDR_REMAP		PCI_1CS_1_BASE_ADDRESS_REMAP  /*0xdd01 */
-#define PCI_0_DEVCS_2_BASE_ADDR_REMAP		PCI_0CS_2_BASE_ADDRESS_REMAP  /*0xd581 */
-#define PCI_1_DEVCS_2_BASE_ADDR_REMAP		PCI_1CS_2_BASE_ADDRESS_REMAP  /*0xdd81 */
-#define PCI_0_DEVCS_3_BASE_ADDR_REMAP			PCI_0CS_3_BASE_ADDRESS_REMAP  /*0xc541 */
-#define PCI_1_DEVCS_3_BASE_ADDR_REMAP			PCI_1CS_3_BASE_ADDRESS_REMAP  /*0xcd41 */
-#define PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP    PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP	 /*0xd541 */
-#define PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP    PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP	 /*0xdd41 */
-#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW    PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW  /*0xd5c1 */
-#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW    PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW  /*0xddc1 */
-#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH   PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH  /*0xd601 */
-#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH   PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH  /*0xde01 */
-#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW	PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW  /*0xd641 */
-#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW	PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW  /*0xde41 */
-#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH	PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH  /*0xd681 */
-#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH	PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH  /*0xde81 */
-#define PCI_0_P2P_I_O_BASE_ADDR_REMAP			PCI_0P2P_I_O_BASE_ADDRESS_REMAP	 /*0xd6c1 */
-#define PCI_1_P2P_I_O_BASE_ADDR_REMAP			PCI_1P2P_I_O_BASE_ADDRESS_REMAP	 /*0xdec 1 */
-#define PCI_0_CPU_BASE_ADDR_REMAP_LOW			PCI_0CPU_BASE_ADDRESS_REMAP  /*0xd701 */
-#define PCI_1_CPU_BASE_ADDR_REMAP_LOW			PCI_1CPU_BASE_ADDRESS_REMAP  /*0xdf01 */
-#define PCI_0_CPU_BASE_ADDR_REMAP_HIGH			0xd74
-#define PCI_1_CPU_BASE_ADDR_REMAP_HIGH			0xdf4
-#define PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		  PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP  /*0xf001 */
-#define PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		  0xf80
-#define PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		   PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP  /*0xf381 */
-#define PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		   PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP  /*0xfb81 */
-#define PCI_0_ADDR_DECODE_CONTROL				PCI_0ADDRESS_DECODE_CONTROL  /*0xd3c1 */
-#define PCI_1_ADDR_DECODE_CONTROL				PCI_1ADDRESS_DECODE_CONTROL  /*0xdbc1 */
-#define PCI_0_HEADERS_RETARGET_CONTROL			0xF40
-#define PCI_1_HEADERS_RETARGET_CONTROL				0xFc0
-#define PCI_0_HEADERS_RETARGET_BASE				0xF44
-#define PCI_1_HEADERS_RETARGET_BASE				0xFc4
-#define PCI_0_HEADERS_RETARGET_HIGH				0xF48
-#define PCI_1_HEADERS_RETARGET_HIGH				0xFc8
-
-#define PCI_0SCS_0_BANK_SIZE				0xc08
-#define PCI_1SCS_0_BANK_SIZE				0xc88
-#define PCI_0SCS_1_BANK_SIZE				0xd08
-#define PCI_1SCS_1_BANK_SIZE				0xd88
-#define PCI_0SCS_2_BANK_SIZE				0xc0c
-#define PCI_1SCS_2_BANK_SIZE				0xc8c
-#define PCI_0SCS_3_BANK_SIZE				0xd0c
-#define PCI_1SCS_3_BANK_SIZE				0xd8c
-#define PCI_0CS_0_BANK_SIZE				0xc10
-#define PCI_1CS_0_BANK_SIZE				0xc90
-#define PCI_0CS_1_BANK_SIZE				0xd10
-#define PCI_1CS_1_BANK_SIZE				0xd90
-#define PCI_0CS_2_BANK_SIZE				0xd18
-#define PCI_1CS_2_BANK_SIZE				0xd98
-#define PCI_0CS_3_BANK_SIZE				0xc14
-#define PCI_1CS_3_BANK_SIZE				0xc94
-#define PCI_0CS_BOOT_BANK_SIZE				0xd14
-#define PCI_1CS_BOOT_BANK_SIZE				0xd94
-#define PCI_0P2P_MEM0_BAR_SIZE						0xd1c
-#define PCI_1P2P_MEM0_BAR_SIZE						0xd9c
-#define PCI_0P2P_MEM1_BAR_SIZE						0xd20
-#define PCI_1P2P_MEM1_BAR_SIZE						0xda0
-#define PCI_0P2P_I_O_BAR_SIZE						0xd24
-#define PCI_1P2P_I_O_BAR_SIZE						0xda4
-#define PCI_0CPU_BAR_SIZE						0xd28
-#define PCI_1CPU_BAR_SIZE						0xda8
-#define PCI_0DAC_SCS_0_BANK_SIZE				0xe00
-#define PCI_1DAC_SCS_0_BANK_SIZE				0xe80
-#define PCI_0DAC_SCS_1_BANK_SIZE				0xe04
-#define PCI_1DAC_SCS_1_BANK_SIZE				0xe84
-#define PCI_0DAC_SCS_2_BANK_SIZE				0xe08
-#define PCI_1DAC_SCS_2_BANK_SIZE				0xe88
-#define PCI_0DAC_SCS_3_BANK_SIZE				0xe0c
-#define PCI_1DAC_SCS_3_BANK_SIZE				0xe8c
-#define PCI_0DAC_CS_0_BANK_SIZE					0xe10
-#define PCI_1DAC_CS_0_BANK_SIZE					0xe90
-#define PCI_0DAC_CS_1_BANK_SIZE					0xe14
-#define PCI_1DAC_CS_1_BANK_SIZE					0xe94
-#define PCI_0DAC_CS_2_BANK_SIZE					0xe18
-#define PCI_1DAC_CS_2_BANK_SIZE					0xe98
-#define PCI_0DAC_CS_3_BANK_SIZE					0xe1c
-#define PCI_1DAC_CS_3_BANK_SIZE					0xe9c
-#define PCI_0DAC_BOOTCS_BANK_SIZE				0xe20
-#define PCI_1DAC_BOOTCS_BANK_SIZE				0xea0
-
-#define PCI_0DAC_P2P_MEM0_BAR_SIZE				0xe24
-#define PCI_1DAC_P2P_MEM0_BAR_SIZE				0xea4
-#define PCI_0DAC_P2P_MEM1_BAR_SIZE				0xe28
-#define PCI_1DAC_P2P_MEM1_BAR_SIZE				0xea8
-#define PCI_0DAC_CPU_BAR_SIZE						0xe2c
-#define PCI_1DAC_CPU_BAR_SIZE						0xeac
-#define PCI_0EXPANSION_ROM_BAR_SIZE				0xd2c
-#define PCI_1EXPANSION_ROM_BAR_SIZE				0xdac
-#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE		0xc3c
-#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE		0xcbc
-#define PCI_0SCS_0_BASE_ADDRESS_REMAP			0xc48
-#define PCI_1SCS_0_BASE_ADDRESS_REMAP			0xcc8
-#define PCI_0SCS_1_BASE_ADDRESS_REMAP			0xd48
-#define PCI_1SCS_1_BASE_ADDRESS_REMAP			0xdc8
-#define PCI_0SCS_2_BASE_ADDRESS_REMAP			0xc4c
-#define PCI_1SCS_2_BASE_ADDRESS_REMAP			0xccc
-#define PCI_0SCS_3_BASE_ADDRESS_REMAP			0xd4c
-#define PCI_1SCS_3_BASE_ADDRESS_REMAP			0xdcc
-#define PCI_0CS_0_BASE_ADDRESS_REMAP			0xc50
-#define PCI_1CS_0_BASE_ADDRESS_REMAP			0xcd0
-#define PCI_0CS_1_BASE_ADDRESS_REMAP			0xd50
-#define PCI_1CS_1_BASE_ADDRESS_REMAP			0xdd0
-#define PCI_0CS_2_BASE_ADDRESS_REMAP			0xd58
-#define PCI_1CS_2_BASE_ADDRESS_REMAP			0xdd8
-#define PCI_0CS_3_BASE_ADDRESS_REMAP			0xc54
-#define PCI_1CS_3_BASE_ADDRESS_REMAP			0xcd4
-#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP	0xd54
-#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP	0xdd4
-#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW			0xd5c
-#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW		  0xddc
-#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		  0xd60
-#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		  0xde0
-#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW		 0xd64
-#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW		 0xde4
-#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		 0xd68
-#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		 0xde8
-#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP				0xd6c
-#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP				0xdec
-#define PCI_0CPU_BASE_ADDRESS_REMAP				0xd70
-#define PCI_1CPU_BASE_ADDRESS_REMAP				0xdf0
-#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP			0xf00
-#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP			0xff0
-#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP			0xf04
-#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP			0xf84
-#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP			0xf08
-#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP			0xf88
-#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP			0xf0c
-#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP			0xf8c
-#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP			0xf10
-#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP			0xf90
-#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP			0xf14
-#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP			0xf94
-#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP			0xf18
-#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP			0xf98
-#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP			0xf1c
-#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP			0xf9c
-#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP			0xf20
-#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP		    0xfa0
-#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW     0xf24
-#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW     0xfa4
-#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH    0xf28
-#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH    0xfa8
-#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW	0xf2c
-#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW     0xfac
-#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH    0xf30
-#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH    0xfb0
-#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP				0xf34
-#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP				0xfb4
-#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP			0xf38
-#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP			0xfb8
-#define PCI_0ADDRESS_DECODE_CONTROL				0xd3c
-#define PCI_1ADDRESS_DECODE_CONTROL				0xdbc
-
-/****************************************/
-/* PCI Control				*/
-/****************************************/
-
-#define PCI_0COMMAND										0xc00
-#define PCI_1COMMAND										0xc80
-#define PCI_0MODE					    0xd00
-#define PCI_1MODE					    0xd80
-#define PCI_0TIMEOUT_RETRY									0xc04
-#define PCI_1TIMEOUT_RETRY									0xc84
-#define PCI_0READ_BUFFER_DISCARD_TIMER			    0xd04
-#define PCI_1READ_BUFFER_DISCARD_TIMER			    0xd84
-#define MSI_0TRIGGER_TIMER				    0xc38
-#define MSI_1TRIGGER_TIMER				    0xcb8
-#define PCI_0ARBITER_CONTROL				    0x1d00
-#define PCI_1ARBITER_CONTROL				    0x1d80
-/* changing untill here */
-#define PCI_0CROSS_BAR_CONTROL_LOW			     0x1d08
-#define PCI_0CROSS_BAR_CONTROL_HIGH			     0x1d0c
-#define PCI_0CROSS_BAR_TIMEOUT				     0x1d04
-#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW	     0x1d18
-#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH	     0x1d1c
-#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER		     0x1d10
-#define PCI_0P2P_CONFIGURATION				     0x1d14
-#define PCI_0ACCESS_CONTROL_BASE_0_LOW			     0x1e00
-#define PCI_0ACCESS_CONTROL_BASE_0_HIGH			     0x1e04
-#define PCI_0ACCESS_CONTROL_TOP_0			     0x1e08
-#define PCI_0ACCESS_CONTROL_BASE_1_LOW			     0x1e10
-#define PCI_0ACCESS_CONTROL_BASE_1_HIGH			     0x1e14
-#define PCI_0ACCESS_CONTROL_TOP_1			     0x1e18
-#define PCI_0ACCESS_CONTROL_BASE_2_LOW			     0x1e20
-#define PCI_0ACCESS_CONTROL_BASE_2_HIGH			     0x1e24
-#define PCI_0ACCESS_CONTROL_TOP_2			     0x1e28
-#define PCI_0ACCESS_CONTROL_BASE_3_LOW			     0x1e30
-#define PCI_0ACCESS_CONTROL_BASE_3_HIGH			     0x1e34
-#define PCI_0ACCESS_CONTROL_TOP_3			     0x1e38
-#define PCI_0ACCESS_CONTROL_BASE_4_LOW			     0x1e40
-#define PCI_0ACCESS_CONTROL_BASE_4_HIGH			     0x1e44
-#define PCI_0ACCESS_CONTROL_TOP_4			     0x1e48
-#define PCI_0ACCESS_CONTROL_BASE_5_LOW			     0x1e50
-#define PCI_0ACCESS_CONTROL_BASE_5_HIGH			     0x1e54
-#define PCI_0ACCESS_CONTROL_TOP_5			     0x1e58
-#define PCI_0ACCESS_CONTROL_BASE_6_LOW			     0x1e60
-#define PCI_0ACCESS_CONTROL_BASE_6_HIGH			     0x1e64
-#define PCI_0ACCESS_CONTROL_TOP_6			     0x1e68
-#define PCI_0ACCESS_CONTROL_BASE_7_LOW			     0x1e70
-#define PCI_0ACCESS_CONTROL_BASE_7_HIGH			     0x1e74
-#define PCI_0ACCESS_CONTROL_TOP_7			     0x1e78
-#define PCI_1CROSS_BAR_CONTROL_LOW			     0x1d88
-#define PCI_1CROSS_BAR_CONTROL_HIGH			     0x1d8c
-#define PCI_1CROSS_BAR_TIMEOUT				     0x1d84
-#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW	     0x1d98
-#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH	     0x1d9c
-#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER		     0x1d90
-#define PCI_1P2P_CONFIGURATION				     0x1d94
-#define PCI_1ACCESS_CONTROL_BASE_0_LOW			     0x1e80
-#define PCI_1ACCESS_CONTROL_BASE_0_HIGH			     0x1e84
-#define PCI_1ACCESS_CONTROL_TOP_0			     0x1e88
-#define PCI_1ACCESS_CONTROL_BASE_1_LOW			     0x1e90
-#define PCI_1ACCESS_CONTROL_BASE_1_HIGH			     0x1e94
-#define PCI_1ACCESS_CONTROL_TOP_1			     0x1e98
-#define PCI_1ACCESS_CONTROL_BASE_2_LOW			     0x1ea0
-#define PCI_1ACCESS_CONTROL_BASE_2_HIGH			     0x1ea4
-#define PCI_1ACCESS_CONTROL_TOP_2			     0x1ea8
-#define PCI_1ACCESS_CONTROL_BASE_3_LOW			     0x1eb0
-#define PCI_1ACCESS_CONTROL_BASE_3_HIGH			     0x1eb4
-#define PCI_1ACCESS_CONTROL_TOP_3			     0x1eb8
-#define PCI_1ACCESS_CONTROL_BASE_4_LOW			     0x1ec0
-#define PCI_1ACCESS_CONTROL_BASE_4_HIGH			     0x1ec4
-#define PCI_1ACCESS_CONTROL_TOP_4			     0x1ec8
-#define PCI_1ACCESS_CONTROL_BASE_5_LOW			     0x1ed0
-#define PCI_1ACCESS_CONTROL_BASE_5_HIGH			     0x1ed4
-#define PCI_1ACCESS_CONTROL_TOP_5			     0x1ed8
-#define PCI_1ACCESS_CONTROL_BASE_6_LOW			     0x1ee0
-#define PCI_1ACCESS_CONTROL_BASE_6_HIGH			     0x1ee4
-#define PCI_1ACCESS_CONTROL_TOP_6			     0x1ee8
-#define PCI_1ACCESS_CONTROL_BASE_7_LOW			     0x1ef0
-#define PCI_1ACCESS_CONTROL_BASE_7_HIGH			     0x1ef4
-#define PCI_1ACCESS_CONTROL_TOP_7			     0x1ef8
-
-/****************************************/
-/* PCI Snoop Control			*/
-/****************************************/
-
-#define PCI_0SNOOP_CONTROL_BASE_0_LOW			     0x1f00
-#define PCI_0SNOOP_CONTROL_BASE_0_HIGH			     0x1f04
-#define PCI_0SNOOP_CONTROL_TOP_0			     0x1f08
-#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW			     0x1f10
-#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH		     0x1f14
-#define PCI_0SNOOP_CONTROL_TOP_1			     0x1f18
-#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW			     0x1f20
-#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH		     0x1f24
-#define PCI_0SNOOP_CONTROL_TOP_2			     0x1f28
-#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW			     0x1f30
-#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH		     0x1f34
-#define PCI_0SNOOP_CONTROL_TOP_3			     0x1f38
-#define PCI_1SNOOP_CONTROL_BASE_0_LOW			     0x1f80
-#define PCI_1SNOOP_CONTROL_BASE_0_HIGH			     0x1f84
-#define PCI_1SNOOP_CONTROL_TOP_0			     0x1f88
-#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW			     0x1f90
-#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH		     0x1f94
-#define PCI_1SNOOP_CONTROL_TOP_1			     0x1f98
-#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW			     0x1fa0
-#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH		     0x1fa4
-#define PCI_1SNOOP_CONTROL_TOP_2			     0x1fa8
-#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW			     0x1fb0
-#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH		     0x1fb4
-#define PCI_1SNOOP_CONTROL_TOP_3			     0x1fb8
-
-/****************************************/
-/* PCI Configuration Address		*/
-/****************************************/
-
-#define PCI_0CONFIGURATION_ADDRESS							0xcf8
-#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER		0xcfc
-#define PCI_1CONFIGURATION_ADDRESS							0xc78
-#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER		0xc7c
-#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER			0xc34
-#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER			0xcb4
-
-/****************************************/
-/* PCI Error Report			*/
-/****************************************/
-
-#define PCI_0SERR_MASK										 0xc28
-#define PCI_0ERROR_ADDRESS_LOW				     0x1d40
-#define PCI_0ERROR_ADDRESS_HIGH				     0x1d44
-#define PCI_0ERROR_DATA_LOW				     0x1d48
-#define PCI_0ERROR_DATA_HIGH				     0x1d4c
-#define PCI_0ERROR_COMMAND				     0x1d50
-#define PCI_0ERROR_CAUSE				     0x1d58
-#define PCI_0ERROR_MASK					     0x1d5c
-#define PCI_1SERR_MASK										 0xca8
-#define PCI_1ERROR_ADDRESS_LOW				     0x1dc0
-#define PCI_1ERROR_ADDRESS_HIGH				     0x1dc4
-#define PCI_1ERROR_DATA_LOW				     0x1dc8
-#define PCI_1ERROR_DATA_HIGH				     0x1dcc
-#define PCI_1ERROR_COMMAND				     0x1dd0
-#define PCI_1ERROR_CAUSE				     0x1dd8
-#define PCI_1ERROR_MASK					     0x1ddc
-
-
-/****************************************/
-/* Lslave Debug	 (for internal use)	*/
-/****************************************/
-
-#define L_SLAVE_X0_ADDRESS				    0x1d20
-#define L_SLAVE_X0_COMMAND_AND_ID			    0x1d24
-#define L_SLAVE_X1_ADDRESS				    0x1d28
-#define L_SLAVE_X1_COMMAND_AND_ID			    0x1d2c
-#define L_SLAVE_WRITE_DATA_LOW				    0x1d30
-#define L_SLAVE_WRITE_DATA_HIGH				    0x1d34
-#define L_SLAVE_WRITE_BYTE_ENABLE			    0x1d60
-#define L_SLAVE_READ_DATA_LOW				    0x1d38
-#define L_SLAVE_READ_DATA_HIGH				    0x1d3c
-#define L_SLAVE_READ_ID					    0x1d64
-
-/****************************************/
-/* PCI Configuration Function 0		*/
-/****************************************/
-
-#define PCI_DEVICE_AND_VENDOR_ID							0x000
-#define PCI_STATUS_AND_COMMAND								0x004
-#define PCI_CLASS_CODE_AND_REVISION_ID					0x008
-#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE		0x00C
-#define PCI_SCS_0_BASE_ADDRESS							0x010
-#define PCI_SCS_1_BASE_ADDRESS							    0x014
-#define PCI_SCS_2_BASE_ADDRESS							    0x018
-#define PCI_SCS_3_BASE_ADDRESS							0x01C
-#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS	0x020
-#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS		0x024
-#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID			0x02C
-#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER				0x030
-#define PCI_CAPABILTY_LIST_POINTER			    0x034
-#define PCI_INTERRUPT_PIN_AND_LINE						    0x03C
-#define PCI_POWER_MANAGEMENT_CAPABILITY			    0x040
-#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044
-#define PCI_VPD_ADDRESS					    0x048
-#define PCI_VPD_DATA					    0x04c
-#define PCI_MSI_MESSAGE_CONTROL				    0x050
-#define PCI_MSI_MESSAGE_ADDRESS				    0x054
-#define PCI_MSI_MESSAGE_UPPER_ADDRESS			    0x058
-#define PCI_MSI_MESSAGE_DATA				    0x05c
-#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY		    0x058
-
-/****************************************/
-/* PCI Configuration Function 1		*/
-/****************************************/
-
-#define PCI_CS_0_BASE_ADDRESS							0x110
-#define PCI_CS_1_BASE_ADDRESS							    0x114
-#define PCI_CS_2_BASE_ADDRESS							    0x118
-#define PCI_CS_3_BASE_ADDRESS							0x11c
-#define PCI_BOOTCS_BASE_ADDRESS				    0x120
-
-/****************************************/
-/* PCI Configuration Function 2		*/
-/****************************************/
-
-#define PCI_P2P_MEM0_BASE_ADDRESS						0x210
- /*#define PCI_P2P_MEM1_BASE_ADDRESS							0x2141 */
-#define PCI_P2P_I_O_BASE_ADDRESS							0x218
- /*#define PCI_CPU_BASE_ADDRESS							    0x21c1 */
-
-/****************************************/
-/* PCI Configuration Function 4		*/
-/****************************************/
-
-#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW						0x410
-#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH					    0x414
-#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW					    0x418
-#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH					    0x41c
-#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW		    0x420
-#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH		    0x424
-
-
-/****************************************/
-/* PCI Configuration Function 5		*/
-/****************************************/
-
-#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW						0x510
-#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH					    0x514
-#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW					    0x518
-#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH					    0x51c
-#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW		    0x520
-#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH		    0x524
-
-
-/****************************************/
-/* PCI Configuration Function 6		*/
-/****************************************/
-
-#define PCI_DAC_CS_0_BASE_ADDRESS_LOW						0x610
-#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH					    0x614
-#define PCI_DAC_CS_1_BASE_ADDRESS_LOW					    0x618
-#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH					    0x61c
-#define PCI_DAC_CS_2_BASE_ADDRESS_LOW				0x620
-#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH				0x624
-
-/****************************************/
-/* PCI Configuration Function 7		*/
-/****************************************/
-
-#define PCI_DAC_CS_3_BASE_ADDRESS_LOW						0x710
-#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH					    0x714
-#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW					    0x718
-#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH				    0x71c
-#define PCI_DAC_CPU_BASE_ADDRESS_LOW				0x720
-#define PCI_DAC_CPU_BASE_ADDRESS_HIGH				0x724
-
-/****************************** MV64360 and MV64460 PCI ***************************/
-/***********************************/
-/*   PCI Control Register Map	   */
-/***********************************/
-
-#define PCI_0_DLL_STATUS_AND_COMMAND				0x1d20
-#define PCI_1_DLL_STATUS_AND_COMMAND				0x1da0
-#define PCI_0_MPP_PADS_DRIVE_CONTROL				0x1d1C
-#define PCI_1_MPP_PADS_DRIVE_CONTROL				0x1d9C
-#define PCI_0_COMMAND					0xc00
-#define PCI_1_COMMAND					0xc80
-#define PCI_0_MODE							0xd00
-#define PCI_1_MODE							0xd80
-#define PCI_0_RETRY						0xc04
-#define PCI_1_RETRY						0xc84
-#define PCI_0_READ_BUFFER_DISCARD_TIMER				0xd04
-#define PCI_1_READ_BUFFER_DISCARD_TIMER				0xd84
-#define PCI_0_MSI_TRIGGER_TIMER						0xc38
-#define PCI_1_MSI_TRIGGER_TIMER						0xcb8
-#define PCI_0_ARBITER_CONTROL						0x1d00
-#define PCI_1_ARBITER_CONTROL						0x1d80
-#define PCI_0_CROSS_BAR_CONTROL_LOW				0x1d08
-#define PCI_1_CROSS_BAR_CONTROL_LOW				0x1d88
-#define PCI_0_CROSS_BAR_CONTROL_HIGH				0x1d0c
-#define PCI_1_CROSS_BAR_CONTROL_HIGH				0x1d8c
-#define PCI_0_CROSS_BAR_TIMEOUT					0x1d04
-#define PCI_1_CROSS_BAR_TIMEOUT					0x1d84
-#define PCI_0_SYNC_BARRIER_TRIGGER_REG				0x1D18
-#define PCI_1_SYNC_BARRIER_TRIGGER_REG				0x1D98
-#define PCI_0_SYNC_BARRIER_VIRTUAL_REG				0x1d10
-#define PCI_1_SYNC_BARRIER_VIRTUAL_REG				0x1d90
-#define PCI_0_P2P_CONFIG						0x1d14
-#define PCI_1_P2P_CONFIG						0x1d94
-
-#define PCI_0_ACCESS_CONTROL_BASE_0_LOW				0x1e00
-#define PCI_0_ACCESS_CONTROL_BASE_0_HIGH			0x1e04
-#define PCI_0_ACCESS_CONTROL_SIZE_0				0x1e08
-#define PCI_0_ACCESS_CONTROL_BASE_1_LOW				0x1e10
-#define PCI_0_ACCESS_CONTROL_BASE_1_HIGH			0x1e14
-#define PCI_0_ACCESS_CONTROL_SIZE_1				0x1e18
-#define PCI_0_ACCESS_CONTROL_BASE_2_LOW				0x1e20
-#define PCI_0_ACCESS_CONTROL_BASE_2_HIGH			0x1e24
-#define PCI_0_ACCESS_CONTROL_SIZE_2				0x1e28
-#define PCI_0_ACCESS_CONTROL_BASE_3_LOW				0x1e30
-#define PCI_0_ACCESS_CONTROL_BASE_3_HIGH			0x1e34
-#define PCI_0_ACCESS_CONTROL_SIZE_3				0x1e38
-#define PCI_0_ACCESS_CONTROL_BASE_4_LOW				0x1e40
-#define PCI_0_ACCESS_CONTROL_BASE_4_HIGH			0x1e44
-#define PCI_0_ACCESS_CONTROL_SIZE_4				0x1e48
-#define PCI_0_ACCESS_CONTROL_BASE_5_LOW				0x1e50
-#define PCI_0_ACCESS_CONTROL_BASE_5_HIGH			0x1e54
-#define PCI_0_ACCESS_CONTROL_SIZE_5				0x1e58
-
-#define PCI_1_ACCESS_CONTROL_BASE_0_LOW				0x1e80
-#define PCI_1_ACCESS_CONTROL_BASE_0_HIGH			0x1e84
-#define PCI_1_ACCESS_CONTROL_SIZE_0				0x1e88
-#define PCI_1_ACCESS_CONTROL_BASE_1_LOW				0x1e90
-#define PCI_1_ACCESS_CONTROL_BASE_1_HIGH			0x1e94
-#define PCI_1_ACCESS_CONTROL_SIZE_1				0x1e98
-#define PCI_1_ACCESS_CONTROL_BASE_2_LOW				0x1ea0
-#define PCI_1_ACCESS_CONTROL_BASE_2_HIGH			0x1ea4
-#define PCI_1_ACCESS_CONTROL_SIZE_2				0x1ea8
-#define PCI_1_ACCESS_CONTROL_BASE_3_LOW				0x1eb0
-#define PCI_1_ACCESS_CONTROL_BASE_3_HIGH			0x1eb4
-#define PCI_1_ACCESS_CONTROL_SIZE_3				0x1eb8
-#define PCI_1_ACCESS_CONTROL_BASE_4_LOW				0x1ec0
-#define PCI_1_ACCESS_CONTROL_BASE_4_HIGH			0x1ec4
-#define PCI_1_ACCESS_CONTROL_SIZE_4				0x1ec8
-#define PCI_1_ACCESS_CONTROL_BASE_5_LOW				0x1ed0
-#define PCI_1_ACCESS_CONTROL_BASE_5_HIGH			0x1ed4
-#define PCI_1_ACCESS_CONTROL_SIZE_5				0x1ed8
-
-/****************************************/
-/*   PCI Configuration Access Registers */
-/****************************************/
-
-#define PCI_0_CONFIG_ADDR				0xcf8
-#define PCI_0_CONFIG_DATA_VIRTUAL_REG				0xcfc
-#define PCI_1_CONFIG_ADDR				0xc78
-#define PCI_1_CONFIG_DATA_VIRTUAL_REG				0xc7c
-#define PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
-#define PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
-
-/****************************************/
-/*   PCI Error Report Registers		*/
-/****************************************/
-
-#define PCI_0_SERR_MASK					0xc28
-#define PCI_1_SERR_MASK					0xca8
-#define PCI_0_ERROR_ADDR_LOW						0x1d40
-#define PCI_1_ERROR_ADDR_LOW						0x1dc0
-#define PCI_0_ERROR_ADDR_HIGH						0x1d44
-#define PCI_1_ERROR_ADDR_HIGH						0x1dc4
-#define PCI_0_ERROR_ATTRIBUTE						0x1d48
-#define PCI_1_ERROR_ATTRIBUTE						0x1dc8
-#define PCI_0_ERROR_COMMAND						0x1d50
-#define PCI_1_ERROR_COMMAND						0x1dd0
-#define PCI_0_ERROR_CAUSE						0x1d58
-#define PCI_1_ERROR_CAUSE						0x1dd8
-#define PCI_0_ERROR_MASK						0x1d5c
-#define PCI_1_ERROR_MASK						0x1ddc
-
-/****************************************/
-/*   PCI Debug Registers		*/
-/****************************************/
-
-#define PCI_0_MMASK							0X1D24
-#define PCI_1_MMASK							0X1DA4
-
-/*********************************************/
-/* PCI Configuration, Function 0, Registers  */
-/*********************************************/
-
-#define PCI_DEVICE_AND_VENDOR_ID			0x000
-#define PCI_STATUS_AND_COMMAND			0x004
-#define PCI_CLASS_CODE_AND_REVISION_ID			0x008
-#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE		0x00C
-
-#define PCI_SCS_0_BASE_ADDR_LOW				0x010
-#define PCI_SCS_0_BASE_ADDR_HIGH			0x014
-#define PCI_SCS_1_BASE_ADDR_LOW				0x018
-#define PCI_SCS_1_BASE_ADDR_HIGH			0x01C
-#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW    0x020
-#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH   0x024
- /*#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	0x02c1 */
-#define PCI_EXPANSION_ROM_BASE_ADDR_REG		0x030
-#define PCI_CAPABILTY_LIST_POINTER				0x034
-#define PCI_INTERRUPT_PIN_AND_LINE			0x03C
-       /* capability list */
-#define PCI_POWER_MANAGEMENT_CAPABILITY				0x040
-#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL	     0x044
-#define PCI_VPD_ADDR							0x048
-#define PCI_VPD_DATA							0x04c
-#define PCI_MSI_MESSAGE_CONTROL					0x050
-#define PCI_MSI_MESSAGE_ADDR						0x054
-#define PCI_MSI_MESSAGE_UPPER_ADDR				0x058
-#define PCI_MSI_MESSAGE_DATA						0x05c
-#define PCI_X_COMMAND							0x060
-#define PCI_X_STATUS							0x064
-#define PCI_COMPACT_PCI_HOT_SWAP				0x068
-
-/***********************************************/
-/*   PCI Configuration, Function 1, Registers  */
-/***********************************************/
-
-#define PCI_SCS_2_BASE_ADDR_LOW				0x110
-#define PCI_SCS_2_BASE_ADDR_HIGH			0x114
-#define PCI_SCS_3_BASE_ADDR_LOW				0x118
-#define PCI_SCS_3_BASE_ADDR_HIGH			0x11c
-#define PCI_INTERNAL_SRAM_BASE_ADDR_LOW					0x120
-#define PCI_INTERNAL_SRAM_BASE_ADDR_HIGH				0x124
-
-/***********************************************/
-/*  PCI Configuration, Function 2, Registers   */
-/***********************************************/
-
-#define PCI_DEVCS_0_BASE_ADDR_LOW			0x210
-#define PCI_DEVCS_0_BASE_ADDR_HIGH			0x214
-#define PCI_DEVCS_1_BASE_ADDR_LOW			0x218
-#define PCI_DEVCS_1_BASE_ADDR_HIGH				0x21c
-#define PCI_DEVCS_2_BASE_ADDR_LOW			0x220
-#define PCI_DEVCS_2_BASE_ADDR_HIGH				0x224
-
-/***********************************************/
-/*  PCI Configuration, Function 3, Registers   */
-/***********************************************/
-
-#define PCI_DEVCS_3_BASE_ADDR_LOW			0x310
-#define PCI_DEVCS_3_BASE_ADDR_HIGH			0x314
-#define PCI_BOOT_CS_BASE_ADDR_LOW			0x318
-#define PCI_BOOT_CS_BASE_ADDR_HIGH				0x31c
-#define PCI_CPU_BASE_ADDR_LOW				0x220
-#define PCI_CPU_BASE_ADDR_HIGH				0x224
-
-/***********************************************/
-/*  PCI Configuration, Function 4, Registers   */
-/***********************************************/
-
-#define PCI_P2P_MEM0_BASE_ADDR_LOW			0x410
-#define PCI_P2P_MEM0_BASE_ADDR_HIGH			0x414
-#define PCI_P2P_MEM1_BASE_ADDR_LOW			0x418
-#define PCI_P2P_MEM1_BASE_ADDR_HIGH			0x41c
-#define PCI_P2P_I_O_BASE_ADDR						0x420
-#define PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR		  0x424
-
-/****************************** MV64360 and MV64460 PCI End ***************************/
-/****************************************/
-/* I20 Support registers				*/
-/****************************************/
-
-#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x010
-#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x014
-#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x018
-#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x01C
-#define INBOUND_DOORBELL_REGISTER_PCI_SIDE		0x020
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x024
-#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x028
-#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE		0x02C
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x030
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x034
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x040
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x044
-#define QUEUE_CONTROL_REGISTER_PCI_SIDE			0x050
-#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE		0x054
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x060
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x064
-#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x068
-#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x06C
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x070
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x074
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x078
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x07C
-
-#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1C10
-#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1C14
-#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1C18
-#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1C1C
-#define INBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1C20
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1C24
-#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1C28
-#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1C2C
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1C30
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1C34
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE		0x1C40
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE		0x1C44
-#define QUEUE_CONTROL_REGISTER_CPU_SIDE				0x1C50
-#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE			0x1C54
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE		0x1C60
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE		0x1C64
-#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE		0x1C68
-#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE		0x1C6C
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE		0x1C70
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE		0x1C74
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE		0x1C78
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE		0x1C7C
-
-
-/****************************************/
-/* Messaging Unit Registers (I20)	*/
-/****************************************/
-
-#define I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE			0x010
-#define I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE				0x014
-#define I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE				0x018
-#define I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE				0x01C
-#define I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE				0x020
-#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE		0x024
-#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE			0x028
-#define I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE				0x02C
-#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE		0x030
-#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE		0x034
-#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE		0x040
-#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE		0x044
-#define I2O_QUEUE_CONTROL_REG_PCI_0_SIDE			0x050
-#define I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE			0x054
-#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE		0x060
-#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE		0x064
-#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE		0x068
-#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE		0x06C
-#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE		0x070
-#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE		0x074
-#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE		0x0F8
-#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE		0x0FC
-
-#define I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE			0x090
-#define I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE				0x094
-#define I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE				0x098
-#define I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE				0x09C
-#define I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE				0x0A0
-#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE		0x0A4
-#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE			0x0A8
-#define I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE				0x0AC
-#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE		0x0B0
-#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE		0x0B4
-#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE		0x0C0
-#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE		0x0C4
-#define I2O_QUEUE_CONTROL_REG_PCI_1_SIDE			0x0D0
-#define I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE			0x0D4
-#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE		0x0E0
-#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE		0x0E4
-#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE		0x0E8
-#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE		0x0EC
-#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE		0x0F0
-#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE		0x0F4
-#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE		0x078
-#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE		0x07C
-
-#define I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE			0x1C10
-#define I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE				0x1C14
-#define I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE				0x1C18
-#define I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE				0x1C1C
-#define I2O_INBOUND_DOORBELL_REG_CPU0_SIDE				0x1C20
-#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE			0x1C24
-#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE			0x1C28
-#define I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE				0x1C2C
-#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE		0x1C30
-#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE		0x1C34
-#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE		0x1C40
-#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE		0x1C44
-#define I2O_QUEUE_CONTROL_REG_CPU0_SIDE				0x1C50
-#define I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE				0x1C54
-#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE		0x1C60
-#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE		0x1C64
-#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE		0x1C68
-#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE		0x1C6C
-#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE		0x1C70
-#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE		0x1C74
-#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE		0x1CF8
-#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE		0x1CFC
-#define I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE			0x1C90
-#define I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE				0x1C94
-#define I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE				0x1C98
-#define I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE				0x1C9C
-#define I2O_INBOUND_DOORBELL_REG_CPU1_SIDE				0x1CA0
-#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE			0x1CA4
-#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE			0x1CA8
-#define I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE				0x1CAC
-#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE		0x1CB0
-#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE		0x1CB4
-#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE		0x1CC0
-#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE		0x1CC4
-#define I2O_QUEUE_CONTROL_REG_CPU1_SIDE				0x1CD0
-#define I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE				0x1CD4
-#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE		0x1CE0
-#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE		0x1CE4
-#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE		0x1CE8
-#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE		0x1CEC
-#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE		0x1CF0
-#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE		0x1CF4
-#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE		0x1C78
-#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE		0x1C7C
-
-
-/****************************************/
-/* Communication Unit Registers		*/
-/****************************************/
-/*
-#define ETHERNET_0_ADDRESS_CONTROL_LOW						0xf200
-#define ETHERNET_0_ADDRESS_CONTROL_HIGH			    0xf204
-#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	    0xf208
-#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	    0xf20c
-#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf210
-#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf214
-#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS		    0xf218
-#define ETHERNET_1_ADDRESS_CONTROL_LOW			    0xf220
-#define ETHERNET_1_ADDRESS_CONTROL_HIGH			    0xf224
-#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	    0xf228
-#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	    0xf22c
-#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf230
-#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf234
-#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS		    0xf238
-#define ETHERNET_2_ADDRESS_CONTROL_LOW			    0xf240
-#define ETHERNET_2_ADDRESS_CONTROL_HIGH			    0xf244
-#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	    0xf248
-#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	    0xf24c
-#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf250
-#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf254
-#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS		    0xf258
- */
-#define MPSC_0_ADDRESS_CONTROL_LOW			    0xf280
-#define MPSC_0_ADDRESS_CONTROL_HIGH			    0xf284
-#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		    0xf288
-#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		    0xf28c
-#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf290
-#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf294
-#define MPSC_1_ADDRESS_CONTROL_LOW			    0xf2c0
-#define MPSC_1_ADDRESS_CONTROL_HIGH			    0xf2c4
-#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		    0xf2c8
-#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		    0xf2cc
-#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf2d0
-#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf2d4
- /*#define SERIAL_INIT_PCI_HIGH_ADDRESS			       0xf3201 */
-#define COMM_UNIT_ARBITER_CONTROL			    0xf300
-#define COMM_UNIT_CROSS_BAR_TIMEOUT			    0xf304
-#define COMM_UNIT_INTERRUPT_CAUSE			    0xf310
-#define COMM_UNIT_INTERRUPT_MASK			    0xf314
-#define COMM_UNIT_ERROR_ADDRESS				    0xf314
-/****************************************/
-/*    Serial Initialization registers	*/
-/****************************************/
-
- /*#define SERIAL_INIT_LAST_DATA					0xf3241 */
- /*#define SERIAL_INIT_STATUS_AND_CONTROL			0xf3281 */
-#define SERIAL_INIT_LAST_DATA						0xf324
-#define SERIAL_INIT_CONTROL						0xf328
-#define SERIAL_INIT_STATUS						0xf32c
-
-
-/****************************************/
-/*	  Ethernet Unit Registers		*/
-/****************************************/
-
-#define ETH_PHY_ADDR_REG			0x2000
-#define ETH_SMI_REG					0x2004
-#define ETH_UNIT_DEFAULT_ADDR_REG		0x2008
-#define ETH_UNIT_DEFAULTID_REG			0x200c
-#define ETH_UNIT_INTERRUPT_CAUSE_REG	0x2080
-#define ETH_UNIT_INTERRUPT_MASK_REG	0x2084
-#define ETH_UNIT_INTERNAL_USE_REG		0x24fc
-#define ETH_UNIT_ERROR_ADDR_REG			0x2094
-#define ETH_BAR_0					0x2200
-#define ETH_BAR_1					0x2208
-#define ETH_BAR_2					0x2210
-#define ETH_BAR_3					0x2218
-#define ETH_BAR_4					0x2220
-#define ETH_BAR_5					0x2228
-#define ETH_SIZE_REG_0				0x2204
-#define ETH_SIZE_REG_1				0x220c
-#define ETH_SIZE_REG_2				0x2214
-#define ETH_SIZE_REG_3				0x221c
-#define ETH_SIZE_REG_4				0x2224
-#define ETH_SIZE_REG_5					0x222c
-#define ETH_HEADERS_RETARGET_BASE_REG			0x2230
-#define ETH_HEADERS_RETARGET_CONTROL_REG	0x2234
-#define ETH_HIGH_ADDR_REMAP_REG_0		0x2280
-#define ETH_HIGH_ADDR_REMAP_REG_1		0x2284
-#define ETH_HIGH_ADDR_REMAP_REG_2		0x2288
-#define ETH_HIGH_ADDR_REMAP_REG_3			0x228c
-#define ETH_BASE_ADDR_ENABLE_REG			0x2290
-#define ETH_ACCESS_PROTECTION_REG(port)			(0x2294 + (port<<2))
-#define ETH_MIB_COUNTERS_BASE(port)			(0x3000 + (port<<7))
-#define ETH_PORT_CONFIG_REG(port)				(0x2400 + (port<<10))
-#define ETH_PORT_CONFIG_EXTEND_REG(port)		(0x2404 + (port<<10))
-#define ETH_MII_SERIAL_PARAMETRS_REG(port)		(0x2408 + (port<<10))
-#define ETH_GMII_SERIAL_PARAMETRS_REG(port)		(0x240c + (port<<10))
-#define ETH_VLAN_ETHERTYPE_REG(port)			(0x2410 + (port<<10))
-#define ETH_MAC_ADDR_LOW(port)					(0x2414 + (port<<10))
-#define ETH_MAC_ADDR_HIGH(port)					(0x2418 + (port<<10))
-#define ETH_SDMA_CONFIG_REG(port)				(0x241c + (port<<10))
-#define ETH_DSCP_0(port)					(0x2420 + (port<<10))
-#define ETH_DSCP_1(port)					(0x2424 + (port<<10))
-#define ETH_DSCP_2(port)					(0x2428 + (port<<10))
-#define ETH_DSCP_3(port)					(0x242c + (port<<10))
-#define ETH_DSCP_4(port)					(0x2430 + (port<<10))
-#define ETH_DSCP_5(port)					(0x2434 + (port<<10))
-#define ETH_DSCP_6(port)					(0x2438 + (port<<10))
-#define ETH_PORT_SERIAL_CONTROL_REG(port)		(0x243c + (port<<10))
-#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		(0x2440 + (port<<10))
-#define ETH_PORT_STATUS_REG(port)				(0x2444 + (port<<10))
-#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port)	(0x2448 + (port<<10))
-#define ETH_TX_QUEUE_FIXED_PRIORITY(port)		(0x244c + (port<<10))
-#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)		(0x2450 + (port<<10))
-#define ETH_MAXIMUM_TRANSMIT_UNIT(port)				(0x2458 + (port<<10))
-#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)		(0x245c + (port<<10))
-#define ETH_INTERRUPT_CAUSE_REG(port)				(0x2460 + (port<<10))
-#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port)			(0x2464 + (port<<10))
-#define ETH_INTERRUPT_MASK_REG(port)				(0x2468 + (port<<10))
-#define ETH_INTERRUPT_EXTEND_MASK_REG(port)			(0x246c + (port<<10))
-#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)			(0x2470 + (port<<10))
-#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)			(0x2474 + (port<<10))
-#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port)			(0x247c + (port<<10))
-#define ETH_RX_DISCARDED_FRAMES_COUNTER(port)			(0x2484 + (port<<10)
-#define ETH_PORT_DEBUG_0_REG(port)					(0x248c + (port<<10))
-#define ETH_PORT_DEBUG_1_REG(port)					(0x2490 + (port<<10))
-#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)			(0x2494 + (port<<10))
-#define ETH_INTERNAL_USE_REG(port)					(0x24fc + (port<<10))
-#define ETH_RECEIVE_QUEUE_COMMAND_REG(port)			(0x2680 + (port<<10))
-#define ETH_CURRENT_SERVED_TX_DESC_PTR(port)			(0x2684 + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)			(0x260c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)			(0x261c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)			(0x262c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)			(0x263c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)			(0x264c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)			(0x265c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)			(0x266c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)			(0x267c + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)			(0x26c0 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)			(0x26c4 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)			(0x26c8 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)			(0x26cc + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)			(0x26d0 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)			(0x26d4 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)			(0x26d8 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)			(0x26dc + (port<<10))
-#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)			(0x2700 + (port<<10))
-#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)			(0x2710 + (port<<10))
-#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)			(0x2720 + (port<<10))
-#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)			(0x2730 + (port<<10))
-#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)			(0x2740 + (port<<10))
-#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)			(0x2750 + (port<<10))
-#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)			(0x2760 + (port<<10))
-#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)			(0x2770 + (port<<10))
-#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)		(0x2704 + (port<<10))
-#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)		(0x2714 + (port<<10))
-#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)		(0x2724 + (port<<10))
-#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)		(0x2734 + (port<<10))
-#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)		(0x2744 + (port<<10))
-#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)		(0x2754 + (port<<10))
-#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)		(0x2764 + (port<<10))
-#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)		(0x2774 + (port<<10))
-#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port)			(0x2708 + (port<<10))
-#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port)			(0x2718 + (port<<10))
-#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port)			(0x2728 + (port<<10))
-#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port)			(0x2738 + (port<<10))
-#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port)			(0x2748 + (port<<10))
-#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port)			(0x2758 + (port<<10))
-#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port)			(0x2768 + (port<<10))
-#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port)			(0x2778 + (port<<10))
-#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)			(0x2780 + (port<<10))
-#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)	(0x3400 + (port<<10))
-#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)		(0x3500 + (port<<10))
-#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port)			(0x3600 + (port<<10))
-
-/****************************************/
-/* Cunit Debug	(for internal use)     */
-/****************************************/
-
-#define CUNIT_ADDRESS					    0xf340
-#define CUNIT_COMMAND_AND_ID				    0xf344
-#define CUNIT_WRITE_DATA_LOW				    0xf348
-#define CUNIT_WRITE_DATA_HIGH				    0xf34c
-#define CUNIT_WRITE_BYTE_ENABLE				    0xf358
-#define CUNIT_READ_DATA_LOW				    0xf350
-#define CUNIT_READ_DATA_HIGH				    0xf354
-#define CUNIT_READ_ID					    0xf35c
-
-/****************************************/
-/* Fast Ethernet Unit Registers		*/
-/****************************************/
-
-/****************************************/
-/*	  Ethernet Unit Registers		*/
-/****************************************/
-
-#define ETH_PHY_ADDR_REG				0x2000
-#define ETH_SMI_REG						0x2004
-#define ETH_UNIT_DEFAULT_ADDR_REG			0x2008
-#define ETH_UNIT_DEFAULTID_REG				0x200c
-#define ETH_UNIT_INTERRUPT_CAUSE_REG			0x2080
-#define ETH_UNIT_INTERRUPT_MASK_REG		0x2084
-#define ETH_UNIT_INTERNAL_USE_REG			0x24fc
-#define ETH_UNIT_ERROR_ADDR_REG				0x2094
-#define ETH_BAR_0						0x2200
-#define ETH_BAR_1						0x2208
-#define ETH_BAR_2						0x2210
-#define ETH_BAR_3						0x2218
-#define ETH_BAR_4						0x2220
-#define ETH_BAR_5						0x2228
-#define ETH_SIZE_REG_0						0x2204
-#define ETH_SIZE_REG_1						0x220c
-#define ETH_SIZE_REG_2						0x2214
-#define ETH_SIZE_REG_3						0x221c
-#define ETH_SIZE_REG_4						0x2224
-#define ETH_SIZE_REG_5						0x222c
-#define ETH_HEADERS_RETARGET_BASE_REG			0x2230
-#define ETH_HEADERS_RETARGET_CONTROL_REG	0x2234
-#define ETH_HIGH_ADDR_REMAP_REG_0			0x2280
-#define ETH_HIGH_ADDR_REMAP_REG_1		0x2284
-#define ETH_HIGH_ADDR_REMAP_REG_2		0x2288
-#define ETH_HIGH_ADDR_REMAP_REG_3			0x228c
-#define ETH_BASE_ADDR_ENABLE_REG			0x2290
-#define ETH_ACCESS_PROTECTION_REG(port)			(0x2294 + (port<<2))
-#define ETH_MIB_COUNTERS_BASE(port)			(0x3000 + (port<<7))
-#define ETH_PORT_CONFIG_REG(port)			(0x2400 + (port<<10))
-#define ETH_PORT_CONFIG_EXTEND_REG(port)		(0x2404 + (port<<10))
-#define ETH_MII_SERIAL_PARAMETRS_REG(port)		(0x2408 + (port<<10))
-#define ETH_GMII_SERIAL_PARAMETRS_REG(port)		(0x240c + (port<<10))
-#define ETH_VLAN_ETHERTYPE_REG(port)			(0x2410 + (port<<10))
-#define ETH_MAC_ADDR_LOW(port)					(0x2414 + (port<<10))
-#define ETH_MAC_ADDR_HIGH(port)					(0x2418 + (port<<10))
-#define ETH_SDMA_CONFIG_REG(port)			(0x241c + (port<<10))
-#define ETH_DSCP_0(port)					(0x2420 + (port<<10))
-#define ETH_DSCP_1(port)					(0x2424 + (port<<10))
-#define ETH_DSCP_2(port)					(0x2428 + (port<<10))
-#define ETH_DSCP_3(port)					(0x242c + (port<<10))
-#define ETH_DSCP_4(port)					(0x2430 + (port<<10))
-#define ETH_DSCP_5(port)					(0x2434 + (port<<10))
-#define ETH_DSCP_6(port)					(0x2438 + (port<<10))
-#define ETH_PORT_SERIAL_CONTROL_REG(port)	(0x243c + (port<<10))
-#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		(0x2440 + (port<<10))
-#define ETH_PORT_STATUS_REG(port)				(0x2444 + (port<<10))
-#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port)	(0x2448 + (port<<10))
-#define ETH_TX_QUEUE_FIXED_PRIORITY(port)		(0x244c + (port<<10))
-#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)	   (0x2450 + (port<<10))
-#define ETH_MAXIMUM_TRANSMIT_UNIT(port)			(0x2458 + (port<<10))
-#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)	   (0x245c + (port<<10))
-#define ETH_INTERRUPT_CAUSE_REG(port)			(0x2460 + (port<<10))
-#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port)		(0x2464 + (port<<10))
-#define ETH_INTERRUPT_MASK_REG(port)			(0x2468 + (port<<10))
-#define ETH_INTERRUPT_EXTEND_MASK_REG(port)		(0x246c + (port<<10))
-#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)	(0x2470 + (port<<10))
-#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)	(0x2474 + (port<<10))
-#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port)		(0x247c + (port<<10))
-#define ETH_RX_DISCARDED_FRAMES_COUNTER(port)	(0x2484 + (port<<10)
-#define ETH_PORT_DEBUG_0_REG(port)				(0x248c + (port<<10))
-#define ETH_PORT_DEBUG_1_REG(port)				(0x2490 + (port<<10))
-#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)	(0x2494 + (port<<10))
-#define ETH_INTERNAL_USE_REG(port)				(0x24fc + (port<<10))
-#define ETH_RECEIVE_QUEUE_COMMAND_REG(port)	(0x2680 + (port<<10))
-#define ETH_CURRENT_SERVED_TX_DESC_PTR(port)		(0x2684 + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)		(0x260c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)	(0x261c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)		(0x262c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)		(0x263c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)		(0x264c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)		(0x265c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)		(0x266c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)		(0x267c + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)	(0x26c0 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)	(0x26c4 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)	(0x26c8 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)		(0x26cc + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)		(0x26d0 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)		(0x26d4 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)		(0x26d8 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)		(0x26dc + (port<<10))
-#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)		   (0x2700 + (port<<10))
-#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)		   (0x2710 + (port<<10))
-#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)		   (0x2720 + (port<<10))
-#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)		   (0x2730 + (port<<10))
-#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)		   (0x2740 + (port<<10))
-#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)		   (0x2750 + (port<<10))
-#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)		   (0x2760 + (port<<10))
-#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)		   (0x2770 + (port<<10))
-#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)	   (0x2704 + (port<<10))
-#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)	   (0x2714 + (port<<10))
-#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)	   (0x2724 + (port<<10))
-#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)	   (0x2734 + (port<<10))
-#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)	   (0x2744 + (port<<10))
-#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)	   (0x2754 + (port<<10))
-#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)	   (0x2764 + (port<<10))
-#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)	   (0x2774 + (port<<10))
-#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port)		(0x2708 + (port<<10))
-#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port)		(0x2718 + (port<<10))
-#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port)		(0x2728 + (port<<10))
-#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port)		(0x2738 + (port<<10))
-#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port)		(0x2748 + (port<<10))
-#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port)		(0x2758 + (port<<10))
-#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port)		(0x2768 + (port<<10))
-#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port)		(0x2778 + (port<<10))
-#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)		(0x2780 + (port<<10))
-#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
-#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)	   (0x3500 + (port<<10))
-#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port)		(0x3600 + (port<<10))
-
-/* Compat with interrupts.c */
-#define ETHERNET0_INTERRUPT_CAUSE_REGISTER      ETH_INTERRUPT_CAUSE_REG(0)
-#define ETHERNET1_INTERRUPT_CAUSE_REGISTER      ETH_INTERRUPT_CAUSE_REG(1)
-#define ETHERNET2_INTERRUPT_CAUSE_REGISTER      ETH_INTERRUPT_CAUSE_REG(2)
-
-#define ETHERNET0_INTERRUPT_MASK_REGISTER       ETH_INTERRUPT_MASK_REG(0)
-#define ETHERNET1_INTERRUPT_MASK_REGISTER       ETH_INTERRUPT_MASK_REG(1)
-#define ETHERNET2_INTERRUPT_MASK_REGISTER       ETH_INTERRUPT_MASK_REG(2)
-
-/* Ethernet GT64260 */
-/*
-#define ETHERNET_PHY_ADDRESS_REGISTER					0x2000
-#define ETHERNET_SMI_REGISTER							0x2010
-*/
-/* Ethernet 0 */
-/*
-#define ETHERNET0_PORT_CONFIGURATION_REGISTER				0x2400
-#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER		0x2408
-#define ETHERNET0_PORT_COMMAND_REGISTER					0x2410
-#define ETHERNET0_PORT_STATUS_REGISTER					0x2418
-#define ETHERNET0_SERIAL_PARAMETRS_REGISTER				0x2420
-#define ETHERNET0_HASH_TABLE_POINTER_REGISTER				0x2428
-#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW		0x2430
-#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH		0x2438
-#define ETHERNET0_SDMA_CONFIGURATION_REGISTER			0x2440
-#define ETHERNET0_SDMA_COMMAND_REGISTER					0x2448
-#define ETHERNET0_INTERRUPT_CAUSE_REGISTER				0x2450
-#define ETHERNET0_INTERRUPT_MASK_REGISTER				0x2458
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0				0x2480
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1				0x2484
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2				0x2488
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3				0x248c
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0		0x24a0
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1		0x24a4
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2		0x24a8
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3		0x24ac
-#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0		0x24e0
-#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1		0x24e4
-#define ETHERNET0_MIB_COUNTER_BASE					0x2500
-*/
-/* Ethernet 1 */
-/*
-#define ETHERNET1_PORT_CONFIGURATION_REGISTER				0x2800
-#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER		0x2808
-#define ETHERNET1_PORT_COMMAND_REGISTER					0x2810
-#define ETHERNET1_PORT_STATUS_REGISTER					0x2818
-#define ETHERNET1_SERIAL_PARAMETRS_REGISTER				0x2820
-#define ETHERNET1_HASH_TABLE_POINTER_REGISTER				0x2828
-#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW		0x2830
-#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH		0x2838
-#define ETHERNET1_SDMA_CONFIGURATION_REGISTER			0x2840
-#define ETHERNET1_SDMA_COMMAND_REGISTER					0x2848
-#define ETHERNET1_INTERRUPT_CAUSE_REGISTER				0x2850
-#define ETHERNET1_INTERRUPT_MASK_REGISTER				0x2858
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0				0x2880
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1				0x2884
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2				0x2888
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3				0x288c
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0		0x28a0
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1		0x28a4
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2		0x28a8
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3		0x28ac
-#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0		0x28e0
-#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1		0x28e4
-#define ETHERNET1_MIB_COUNTER_BASE					0x2900
-*/
-/* Ethernet 2 */
-/*
-#define ETHERNET2_PORT_CONFIGURATION_REGISTER				0x2c00
-#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER		0x2c08
-#define ETHERNET2_PORT_COMMAND_REGISTER					0x2c10
-#define ETHERNET2_PORT_STATUS_REGISTER					0x2c18
-#define ETHERNET2_SERIAL_PARAMETRS_REGISTER				0x2c20
-#define ETHERNET2_HASH_TABLE_POINTER_REGISTER				0x2c28
-#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW		0x2c30
-#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH		0x2c38
-#define ETHERNET2_SDMA_CONFIGURATION_REGISTER			0x2c40
-#define ETHERNET2_SDMA_COMMAND_REGISTER					0x2c48
-#define ETHERNET2_INTERRUPT_CAUSE_REGISTER				0x2c50
-#define ETHERNET2_INTERRUPT_MASK_REGISTER				0x2c58
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0				0x2c80
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1				0x2c84
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2				0x2c88
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3				0x2c8c
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0		0x2ca0
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1		0x2ca4
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2		0x2ca8
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3		0x2cac
-#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0		0x2ce0
-#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1		0x2ce4
-#define ETHERNET2_MIB_COUNTER_BASE					0x2d00
-*/
-
-/****************************************/
-/* SDMA Registers			*/
-/****************************************/
-
-#define SDMA_GROUP_CONFIGURATION_REGISTER			0xb1f0
-#define CHANNEL0_CONFIGURATION_REGISTER				0x4000
-#define CHANNEL0_COMMAND_REGISTER				0x4008
-#define CHANNEL0_RX_CMD_STATUS					0x4800
-#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES		    0x4804
-#define CHANNEL0_RX_BUFFER_POINTER				0x4808
-#define CHANNEL0_RX_NEXT_POINTER				0x480c
-#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER		0x4810
-#define CHANNEL0_TX_CMD_STATUS					0x4C00
-#define CHANNEL0_TX_PACKET_SIZE					0x4C04
-#define CHANNEL0_TX_BUFFER_POINTER				0x4C08
-#define CHANNEL0_TX_NEXT_POINTER				0x4C0c
-#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER		0x4c10
-#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER			0x4c14
-/*
-#define CHANNEL1_CONFIGURATION_REGISTER				0x5000
-#define CHANNEL1_COMMAND_REGISTER				0x5008
-#define CHANNEL1_RX_CMD_STATUS					0x5800
-#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES		    0x5804
-#define CHANNEL1_RX_BUFFER_POINTER				0x5808
-#define CHANNEL1_RX_NEXT_POINTER				0x580c
-#define CHANNEL1_TX_CMD_STATUS					0x5C00
-#define CHANNEL1_TX_PACKET_SIZE					0x5C04
-#define CHANNEL1_TX_BUFFER_POINTER				0x5C08
-#define CHANNEL1_TX_NEXT_POINTER				0x5C0c
-#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER		0x5810
-#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER		0x5c10
-#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER			0x5c14
-#define CHANNEL2_CONFIGURATION_REGISTER				0x6000
-#define CHANNEL2_COMMAND_REGISTER				0x6008
-#define CHANNEL2_RX_CMD_STATUS					0x6800
-#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES		    0x6804
-#define CHANNEL2_RX_BUFFER_POINTER				0x6808
-#define CHANNEL2_RX_NEXT_POINTER				0x680c
-#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER		0x6810
-#define CHANNEL2_TX_CMD_STATUS					0x6C00
-#define CHANNEL2_TX_PACKET_SIZE					0x6C04
-#define CHANNEL2_TX_BUFFER_POINTER				0x6C08
-#define CHANNEL2_TX_NEXT_POINTER				0x6C0c
-#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER		0x6810
-#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER			0x6c10
-#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER			0x6c14
-*/
-/* SDMA Interrupt */
-/*
-#define SDMA_CAUSE							0xb820
-#define SDMA_MASK							0xb8a0
-*/
-/***************************************/
-/*	    SDMA Registers	       */
-/***************************************/
-
-#define SDMA_CONFIG_REG(channel)					(0x4000 + (channel<<13))
-#define SDMA_COMMAND_REG(channel)					(0x4008 + (channel<<13))
-#define SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)		(0x4810 + (channel<<13))
-#define SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
-#define SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))
-
-#define SDMA_CAUSE_REG							0xb800
-#define SDMA_MASK_REG							0xb880
-
-/****************************************/
-/* Baude Rate Generators Registers	*/
-/****************************************/
-
-/* BRG 0 */
-#define BRG0_CONFIGURATION_REGISTER		0xb200
-#define BRG0_BAUDE_TUNING_REGISTER			 0xb204
-
-/* BRG 1 */
-#define BRG1_CONFIGURATION_REGISTER			0xb208
-#define BRG1_BAUDE_TUNING_REGISTER			 0xb20c
-
-/* BRG 2 */
-#define BRG2_CONFIGURATION_REGISTER			0xb210
-#define BRG2_BAUDE_TUNING_REGISTER			 0xb214
-
-/* BRG Interrupts */
-#define BRG_CAUSE_REGISTER					0xb834
-#define BRG_MASK_REGISTER					0xb8b4
-#define BRG_CONFIG_REG(brg)					(0xb200 + (brg<<3))
-#define BRG_BAUDE_TUNING_REG(brg)				(0xb208 + (brg<<3))
-#define BRG_CAUSE_REG						BRG_CAUSE_REGISTER  /*0xb8341 */
-#define BRG_MASK_REG						BRG_MASK_REGISTER  /*0xb8b41 */
-
-/* MISC */
-
-#define MAIN_ROUTING_REGISTER						0xb400
-#define RECEIVE_CLOCK_ROUTING_REGISTER				0xb404
-#define TRANSMIT_CLOCK_ROUTING_REGISTER				0xb408
-#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER	0xb40c
-
-/****************************************/
-/*	   Watchdog registers			*/
-/****************************************/
-#define WATCHDOG_CONFIGURATION_REGISTER			0xb410
-#define WATCHDOG_VALUE_REGISTER					0xb414
-#define WATCHDOG_CONFIG_REG					WATCHDOG_CONFIGURATION_REGISTER	 /*0xb4101 */
-#define WATCHDOG_VALUE_REG						WATCHDOG_VALUE_REGISTER	 /*0xb4141 */
-
-
-/****************************************/
-/* Flex TDM Registers			*/
-/****************************************/
-
-/* FTDM Port */
-
-#define FLEXTDM_TRANSMIT_READ_POINTER			    0xa800
-#define FLEXTDM_RECEIVE_READ_POINTER			    0xa804
-#define FLEXTDM_CONFIGURATION_REGISTER			    0xa808
-#define FLEXTDM_AUX_CHANNELA_TX_REGISTER		    0xa80c
-#define FLEXTDM_AUX_CHANNELA_RX_REGISTER		    0xa810
-#define FLEXTDM_AUX_CHANNELB_TX_REGISTER		    0xa814
-#define FLEXTDM_AUX_CHANNELB_RX_REGISTER		    0xa818
-
-/* FTDM Interrupts */
-
-#define FTDM_CAUSE_REGISTER				    0xb830
-#define FTDM_MASK_REGISTER				    0xb8b0
-
-
-/****************************************/
-/* GPP Interface Registers		*/
-/****************************************/
-
-#define GPP_IO_CONTROL						0xf100
-#define GPP_LEVEL_CONTROL					0xf110
-#define GPP_VALUE						0xf104
-#define GPP_INTERRUPT_CAUSE					0xf108
-#define GPP_INTERRUPT_MASK					0xf10c
-#define GPP_INTERRUPT_MASK0					GPP_INTERRUPT_MASK  /* 0xf10c1 */
-#define GPP_INTERRUPT_MASK1					0xf114
-#define GPP_VALUE_SET						0xf118
-#define GPP_VALUE_CLEAR						0xf11c
-
-/****************************************/
-/*	MPP Interface Registers		*/
-/****************************************/
-#define MPP_CONTROL0						0xf000
-#define MPP_CONTROL1						0xf004
-#define MPP_CONTROL2						0xf008
-#define MPP_CONTROL3						0xf00c
-#define DEBUG_PORT_MULTIPLEX					0xf014
- /*#define SERIAL_PORT_MULTIPLEX			       0xf0101 */
-
-/****************************************/
-/* Interrupt Controller Registers	*/
-/****************************************/
-
-/****************************************/
-/* Interrupts							*/
-/****************************************/
-/****************************************/
-/* Interrupts (checked I.A. 14.10.02)				*/
-/****************************************/
-
-#define LOW_INTERRUPT_CAUSE_REGISTER			0x004  /* gt64260: 0xc181 */
-#define HIGH_INTERRUPT_CAUSE_REGISTER			0x00c  /* gt64260: 0xc681 */
-#define CPU_INTERRUPT_MASK_REGISTER_LOW		0x014  /* gt64260: 0xc1c1 */
-#define CPU_INTERRUPT_MASK_REGISTER_HIGH		0x01c  /* gt64260: 0xc6c1 */
-#define CPU_SELECT_CAUSE_REGISTER			0x024  /* gt64260: 0xc701 */
-#define CPU_INTERRUPT_1_MASK_REGISTER_LOW		0x034  /* new in the MV64360 and MV64460 */
-#define CPU_INTERRUPT_1_MASK_REGISTER_HIGH		0x03c  /* new in the MV64360 and MV64460 */
-#define CPU_SELECT_1_CAUSE_REGISTER			0x044  /* new in the MV64360 and MV64460 */
-#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW	0x054  /* gt64260: 0xc241 */
-#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x05c  /* gt64260: 0xc641 */
-#define PCI_0SELECT_CAUSE						0x064  /* gt64260: 0xc741 */
-#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW	0x074  /* gt64260: 0xca41 */
-#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x07c  /* gt64260: 0xce41 */
-#define PCI_1SELECT_CAUSE						0x084  /* gt64260: 0xcf41 */
-/*#define CPU_INT_0_MASK						0xe60 signal is not multiplexed on MPP in the MV64360 and MV64460 */
-/*#define CPU_INT_1_MASK						0xe64 signal is not multiplexed on MPP in the MV64360 and MV64460 */
-/*#define CPU_INT_2_MASK						0xe68 signal is not multiplexed on MPP in the MV64360 and MV64460 */
-/*#define CPU_INT_3_MASK						0xe6c signal is not multiplexed on MPP in the MV64360 and MV64460 */
-
-#define MAIN_INTERRUPT_CAUSE_LOW				LOW_INTERRUPT_CAUSE_REGISTER  /* 0x0041 */
-#define MAIN_INTERRUPT_CAUSE_HIGH				HIGH_INTERRUPT_CAUSE_REGISTER  /* 0x00c1 */
-#define CPU_INTERRUPT0_MASK_LOW				CPU_INTERRUPT_MASK_REGISTER_LOW	 /* 0x0141 */
-#define CPU_INTERRUPT0_MASK_HIGH			CPU_INTERRUPT_MASK_REGISTER_HIGH  /*0x01c1 */
-#define CPU_INTERRUPT0_SELECT_CAUSE			CPU_SELECT_CAUSE_REGISTER  /* 0x0241 */
-#define CPU_INTERRUPT1_MASK_LOW				CPU_INTERRUPT_1_MASK_REGISTER_LOW  /* 0x0341 */
-#define CPU_INTERRUPT1_MASK_HIGH			CPU_INTERRUPT_1_MASK_REGISTER_HIGH  /* 0x03c1 */
-#define CPU_INTERRUPT1_SELECT_CAUSE			CPU_SELECT_1_CAUSE_REGISTER  /* 0x0441 */
-#define INTERRUPT0_MASK_0_LOW				PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW /* 0x0541 */
-#define INTERRUPT0_MASK_0_HIGH					PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH	 /* 0x05c1 */
-#define INTERRUPT0_SELECT_CAUSE				PCI_0SELECT_CAUSE  /* 0x0641 */
-#define INTERRUPT1_MASK_0_LOW					PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW	/* 0x0741 */
-#define INTERRUPT1_MASK_0_HIGH					PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH	 /* 0x07c1 */
-#define INTERRUPT1_SELECT_CAUSE				PCI_1SELECT_CAUSE  /* 0x0841 */
-
-/****************************************/
-/* I2C Registers			*/
-/****************************************/
-
-#define I2C_SLAVE_ADDRESS					0xc000
-#define I2C_EXTENDED_SLAVE_ADDRESS			0xc040
-#define I2C_DATA						0xc004
-#define I2C_CONTROL						0xc008
-#define I2C_STATUS_BAUDE_RATE					0xc00C
-#define I2C_SOFT_RESET						0xc01c
-#define I2C_SLAVE_ADDR						I2C_SLAVE_ADDRESS  /* 0xc0001 */
-#define I2C_EXTENDED_SLAVE_ADDR					I2C_EXTENDED_SLAVE_ADDRESS  /*0xc0101 */
-
-/****************************************/
-/* MPSC Registers			*/
-/****************************************/
-
-	/*  MPSCs Clocks Routing Registers  */
-
-#define MPSC_ROUTING_REG					0xb400
-#define MPSC_RX_CLOCK_ROUTING_REG			0xb404
-#define MPSC_TX_CLOCK_ROUTING_REG			0xb408
-
-	/*  MPSCs Interrupts Registers	  */
-
-#define MPSC_CAUSE_REG(port)					(0xb804 + (port<<3))
-#define MPSC_MASK_REG(port)					(0xb884 + (port<<3))
-
-#define MPSC_MAIN_CONFIG_LOW(port)			(0x8000 + (port<<12))
-#define MPSC_MAIN_CONFIG_HIGH(port)			(0x8004 + (port<<12))
-#define MPSC_PROTOCOL_CONFIG(port)			(0x8008 + (port<<12))
-#define MPSC_CHANNEL_REG1(port)					(0x800c + (port<<12))
-#define MPSC_CHANNEL_REG2(port)					(0x8010 + (port<<12))
-#define MPSC_CHANNEL_REG3(port)					(0x8014 + (port<<12))
-#define MPSC_CHANNEL_REG4(port)					(0x8018 + (port<<12))
-#define MPSC_CHANNEL_REG5(port)					(0x801c + (port<<12))
-#define MPSC_CHANNEL_REG6(port)					(0x8020 + (port<<12))
-#define MPSC_CHANNEL_REG7(port)					(0x8024 + (port<<12))
-#define MPSC_CHANNEL_REG8(port)					(0x8028 + (port<<12))
-#define MPSC_CHANNEL_REG9(port)					(0x802c + (port<<12))
-#define MPSC_CHANNEL_REG10(port)				(0x8030 + (port<<12))
-
-
-/* MPSC0  */
-
-#define MPSC0_MAIN_CONFIGURATION_LOW			    0x8000
-#define MPSC0_MAIN_CONFIGURATION_HIGH			    0x8004
-#define MPSC0_PROTOCOL_CONFIGURATION			    0x8008
-#define CHANNEL0_REGISTER1				    0x800c
-#define CHANNEL0_REGISTER2				    0x8010
-#define CHANNEL0_REGISTER3				    0x8014
-#define CHANNEL0_REGISTER4				    0x8018
-#define CHANNEL0_REGISTER5				    0x801c
-#define CHANNEL0_REGISTER6				    0x8020
-#define CHANNEL0_REGISTER7				    0x8024
-#define CHANNEL0_REGISTER8				    0x8028
-#define CHANNEL0_REGISTER9				    0x802c
-#define CHANNEL0_REGISTER10				    0x8030
-#define CHANNEL0_REGISTER11				    0x8034
-
-/* MPSC1  */
-
-#define MPSC1_MAIN_CONFIGURATION_LOW			    0x8840
-#define MPSC1_MAIN_CONFIGURATION_HIGH			    0x8844
-#define MPSC1_PROTOCOL_CONFIGURATION			    0x8848
-#define CHANNEL1_REGISTER1				    0x884c
-#define CHANNEL1_REGISTER2				    0x8850
-#define CHANNEL1_REGISTER3				    0x8854
-#define CHANNEL1_REGISTER4				    0x8858
-#define CHANNEL1_REGISTER5				    0x885c
-#define CHANNEL1_REGISTER6				    0x8860
-#define CHANNEL1_REGISTER7				    0x8864
-#define CHANNEL1_REGISTER8				    0x8868
-#define CHANNEL1_REGISTER9				    0x886c
-#define CHANNEL1_REGISTER10				    0x8870
-#define CHANNEL1_REGISTER11				    0x8874
-
-/* MPSC2  */
-
-#define MPSC2_MAIN_CONFIGURATION_LOW			    0x9040
-#define MPSC2_MAIN_CONFIGURATION_HIGH			    0x9044
-#define MPSC2_PROTOCOL_CONFIGURATION			    0x9048
-#define CHANNEL2_REGISTER1				    0x904c
-#define CHANNEL2_REGISTER2				    0x9050
-#define CHANNEL2_REGISTER3				    0x9054
-#define CHANNEL2_REGISTER4				    0x9058
-#define CHANNEL2_REGISTER5				    0x905c
-#define CHANNEL2_REGISTER6				    0x9060
-#define CHANNEL2_REGISTER7				    0x9064
-#define CHANNEL2_REGISTER8				    0x9068
-#define CHANNEL2_REGISTER9				    0x906c
-#define CHANNEL2_REGISTER10				    0x9070
-#define CHANNEL2_REGISTER11				    0x9074
-
-/* MPSCs Interrupts  */
-
-#define MPSC0_CAUSE						0xb824
-#define MPSC0_MASK						0xb8a4
-#define MPSC1_CAUSE						0xb828
-#define MPSC1_MASK						0xb8a8
-#define MPSC2_CAUSE						0xb82c
-#define MPSC2_MASK						 0xb8ac
-
-/*******************************************/
-/*	    CUNIT  Registers		   */
-/*******************************************/
-
-	 /* Address Decoding Register Map */
-
-#define CUNIT_BASE_ADDR_REG0					0xf200
-#define CUNIT_BASE_ADDR_REG1					0xf208
-#define CUNIT_BASE_ADDR_REG2					0xf210
-#define CUNIT_BASE_ADDR_REG3					0xf218
-#define CUNIT_SIZE0						0xf204
-#define CUNIT_SIZE1						0xf20c
-#define CUNIT_SIZE2						0xf214
-#define CUNIT_SIZE3						0xf21c
-#define CUNIT_HIGH_ADDR_REMAP_REG0			0xf240
-#define CUNIT_HIGH_ADDR_REMAP_REG1			0xf244
-#define CUNIT_BASE_ADDR_ENABLE_REG			0xf250
-#define MPSC0_ACCESS_PROTECTION_REG			0xf254
-#define MPSC1_ACCESS_PROTECTION_REG			0xf258
-#define CUNIT_INTERNAL_SPACE_BASE_ADDR_REG	0xf25C
-
-	/*  Error Report Registers  */
-
-#define CUNIT_INTERRUPT_CAUSE_REG			0xf310
-#define CUNIT_INTERRUPT_MASK_REG			0xf314
-#define CUNIT_ERROR_ADDR					0xf318
-
-	/*  Cunit Control Registers */
-
-#define CUNIT_ARBITER_CONTROL_REG			0xf300
-#define CUNIT_CONFIG_REG					0xb40c
-#define CUNIT_CRROSBAR_TIMEOUT_REG			0xf304
-
-	/*  Cunit Debug Registers   */
-
-#define CUNIT_DEBUG_LOW						0xf340
-#define CUNIT_DEBUG_HIGH					0xf344
-#define CUNIT_MMASK						0xf380
-
-#endif /* __INCmv_gen_regh */
diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
index e1652c08317..ef08ad8928d 100644
--- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
+++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
@@ -11,7 +11,7 @@
 #include <common.h>
 #include <netdev.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include "mv88f6281gtw_ge.h"
 
@@ -24,9 +24,9 @@ int board_early_init_f(void)
 	 * There are maximum 64 gpios controlled through 2 sets of registers
 	 * the  below configuration configures mainly initial LED status
 	 */
-	kw_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW,
-			MV88F6281GTW_GE_OE_VAL_HIGH,
-			MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
+	mvebu_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW,
+			  MV88F6281GTW_GE_OE_VAL_HIGH,
+			  MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
 	static const u32 kwmpp_config[] = {
@@ -94,7 +94,7 @@ int board_init(void)
 	gd->bd->bi_arch_number = MACH_TYPE_MV88F6281GTW_GE;
 
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c
index a005a2f79dd..55cf525cf8a 100644
--- a/board/Marvell/openrd/openrd.c
+++ b/board/Marvell/openrd/openrd.c
@@ -14,7 +14,7 @@
 #include <common.h>
 #include <miiphy.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include "openrd.h"
 
@@ -27,9 +27,9 @@ int board_early_init_f(void)
 	 * There are maximum 64 gpios controlled through 2 sets of registers
 	 * the  below configuration configures mainly initial LED status
 	 */
-	kw_config_gpio(OPENRD_OE_VAL_LOW,
-			OPENRD_OE_VAL_HIGH,
-			OPENRD_OE_LOW, OPENRD_OE_HIGH);
+	mvebu_config_gpio(OPENRD_OE_VAL_LOW,
+			  OPENRD_OE_VAL_HIGH,
+			  OPENRD_OE_LOW, OPENRD_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
 	static const u32 kwmpp_config[] = {
@@ -104,7 +104,7 @@ int board_init(void)
 #endif
 
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 	return 0;
 }
 
diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c
index 33ef0c78e5b..b0020c95a5b 100644
--- a/board/Marvell/rd6281a/rd6281a.c
+++ b/board/Marvell/rd6281a/rd6281a.c
@@ -10,7 +10,7 @@
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include "rd6281a.h"
 
@@ -23,9 +23,9 @@ int board_early_init_f(void)
 	 * There are maximum 64 gpios controlled through 2 sets of registers
 	 * the  below configuration configures mainly initial LED status
 	 */
-	kw_config_gpio(RD6281A_OE_VAL_LOW,
-			RD6281A_OE_VAL_HIGH,
-			RD6281A_OE_LOW, RD6281A_OE_HIGH);
+	mvebu_config_gpio(RD6281A_OE_VAL_LOW,
+			  RD6281A_OE_VAL_HIGH,
+			  RD6281A_OE_LOW, RD6281A_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
 	static const u32 kwmpp_config[] = {
@@ -93,7 +93,7 @@ int board_init(void)
 	gd->bd->bi_arch_number = MACH_TYPE_RD88F6281;
 
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c
index 87e49f417bb..8907fb58ff8 100644
--- a/board/Marvell/sheevaplug/sheevaplug.c
+++ b/board/Marvell/sheevaplug/sheevaplug.c
@@ -9,7 +9,7 @@
 #include <common.h>
 #include <miiphy.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include "sheevaplug.h"
 
@@ -22,9 +22,9 @@ int board_early_init_f(void)
 	 * There are maximum 64 gpios controlled through 2 sets of registers
 	 * the  below configuration configures mainly initial LED status
 	 */
-	kw_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
-			SHEEVAPLUG_OE_VAL_HIGH,
-			SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
+	mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
+			  SHEEVAPLUG_OE_VAL_HIGH,
+			  SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
 	static const u32 kwmpp_config[] = {
@@ -92,7 +92,7 @@ int board_init(void)
 	gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
 
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c
index ff6a6a09ed7..83ab1bc32d3 100644
--- a/board/Seagate/dockstar/dockstar.c
+++ b/board/Seagate/dockstar/dockstar.c
@@ -11,7 +11,7 @@
 
 #include <common.h>
 #include <miiphy.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include <asm/arch/cpu.h>
 #include <asm/io.h>
@@ -26,9 +26,9 @@ int board_early_init_f(void)
 	 * There are maximum 64 gpios controlled through 2 sets of registers
 	 * the  below configuration configures mainly initial LED status
 	 */
-	kw_config_gpio(DOCKSTAR_OE_VAL_LOW,
-			DOCKSTAR_OE_VAL_HIGH,
-			DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
+	mvebu_config_gpio(DOCKSTAR_OE_VAL_LOW,
+			  DOCKSTAR_OE_VAL_HIGH,
+			  DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
 	static const u32 kwmpp_config[] = {
@@ -96,7 +96,7 @@ int board_init(void)
 	gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR;
 
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
@@ -143,7 +143,7 @@ void reset_phy(void)
 
 static void set_leds(u32 leds, u32 blinking)
 {
-	struct kwgpio_registers *r = (struct kwgpio_registers *)KW_GPIO1_BASE;
+	struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
 	u32 oe = readl(&r->oe) | BOTH_LEDS;
 	writel(oe & ~leds, &r->oe);	/* active low */
 	u32 bl = readl(&r->blink_en) & ~BOTH_LEDS;
diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c
index a6598e9c81e..1f4fb924942 100644
--- a/board/Seagate/goflexhome/goflexhome.c
+++ b/board/Seagate/goflexhome/goflexhome.c
@@ -14,7 +14,7 @@
 
 #include <common.h>
 #include <miiphy.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include <asm/arch/cpu.h>
 #include <asm/io.h>
@@ -83,9 +83,9 @@ int board_early_init_f(void)
 	 * There are maximum 64 gpios controlled through 2 sets of registers
 	 * the  below configuration configures mainly initial LED status
 	 */
-	kw_config_gpio(GOFLEXHOME_OE_VAL_LOW,
-		       GOFLEXHOME_OE_VAL_HIGH,
-		       GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
+	mvebu_config_gpio(GOFLEXHOME_OE_VAL_LOW,
+			  GOFLEXHOME_OE_VAL_HIGH,
+			  GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
 	kirkwood_mpp_conf(kwmpp_config, NULL);
 	return 0;
 }
@@ -98,7 +98,7 @@ int board_init(void)
 	gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME;
 
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
@@ -149,7 +149,7 @@ static void set_leds(u32 leds, u32 blinking)
 	u32 oe;
 	u32 bl;
 
-	r = (struct kwgpio_registers *)KW_GPIO1_BASE;
+	r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
 	oe = readl(&r->oe) | BOTH_LEDS;
 	writel(oe & ~leds, &r->oe);	/* active low */
 	bl = readl(&r->blink_en) & ~BOTH_LEDS;
diff --git a/board/afeb9260/Kconfig b/board/afeb9260/Kconfig
index ff191811ba0..6a5a93139de 100644
--- a/board/afeb9260/Kconfig
+++ b/board/afeb9260/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_AFEB9260
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "afeb9260"
 
diff --git a/board/altera/socfpga/Kconfig b/board/altera/socfpga/Kconfig
index f8595781d9b..fc42185a83b 100644
--- a/board/altera/socfpga/Kconfig
+++ b/board/altera/socfpga/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_SOCFPGA_CYCLONE5
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "socfpga"
 
diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig
index ac35d6de6fe..b8e380eb848 100644
--- a/board/aristainetos/Kconfig
+++ b/board/aristainetos/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_ARISTAINETOS
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "aristainetos"
 
diff --git a/board/armadeus/apf27/Kconfig b/board/armadeus/apf27/Kconfig
index 53532bba58f..65544a84483 100644
--- a/board/armadeus/apf27/Kconfig
+++ b/board/armadeus/apf27/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_APF27
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "apf27"
 
diff --git a/board/armltd/integrator/Kconfig b/board/armltd/integrator/Kconfig
index 49553131b9d..6153b5dd7d4 100644
--- a/board/armltd/integrator/Kconfig
+++ b/board/armltd/integrator/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_INTEGRATORAP_CM720T
 
-config SYS_CPU
-	default "arm720t"
-
 config SYS_BOARD
 	default "integrator"
 
@@ -16,9 +13,6 @@ endif
 
 if TARGET_INTEGRATORAP_CM920T
 
-config SYS_CPU
-	default "arm920t"
-
 config SYS_BOARD
 	default "integrator"
 
@@ -32,9 +26,6 @@ endif
 
 if TARGET_INTEGRATORCP_CM920T
 
-config SYS_CPU
-	default "arm920t"
-
 config SYS_BOARD
 	default "integrator"
 
@@ -48,9 +39,6 @@ endif
 
 if TARGET_INTEGRATORAP_CM926EJS
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "integrator"
 
@@ -64,9 +52,6 @@ endif
 
 if TARGET_INTEGRATORCP_CM926EJS
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "integrator"
 
@@ -80,9 +65,6 @@ endif
 
 if TARGET_INTEGRATORCP_CM1136
 
-config SYS_CPU
-	default "arm1136"
-
 config SYS_BOARD
 	default "integrator"
 
@@ -96,9 +78,6 @@ endif
 
 if TARGET_INTEGRATORAP_CM946ES
 
-config SYS_CPU
-	default "arm946es"
-
 config SYS_BOARD
 	default "integrator"
 
@@ -112,9 +91,6 @@ endif
 
 if TARGET_INTEGRATORCP_CM946ES
 
-config SYS_CPU
-	default "arm946es"
-
 config SYS_BOARD
 	default "integrator"
 
diff --git a/board/armltd/vexpress/Kconfig b/board/armltd/vexpress/Kconfig
index 7fa30c65f9e..2e15e0d4975 100644
--- a/board/armltd/vexpress/Kconfig
+++ b/board/armltd/vexpress/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_VEXPRESS_CA15_TC2
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "vexpress"
 
@@ -16,9 +13,6 @@ endif
 
 if TARGET_VEXPRESS_CA5X2
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "vexpress"
 
@@ -32,9 +26,6 @@ endif
 
 if TARGET_VEXPRESS_CA9X4
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "vexpress"
 
diff --git a/board/atmel/at91rm9200ek/Kconfig b/board/atmel/at91rm9200ek/Kconfig
index 61db2e2d405..bad4a37da03 100644
--- a/board/atmel/at91rm9200ek/Kconfig
+++ b/board/atmel/at91rm9200ek/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_AT91RM9200EK
 
-config SYS_CPU
-	default "arm920t"
-
 config SYS_BOARD
 	default "at91rm9200ek"
 
diff --git a/board/atmel/at91rm9200ek/led.c b/board/atmel/at91rm9200ek/led.c
index 2298e3619c4..6761b141fb8 100644
--- a/board/atmel/at91rm9200ek/led.c
+++ b/board/atmel/at91rm9200ek/led.c
@@ -14,6 +14,7 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_pio.h>
+#include <status_led.h>
 
 /* bit mask in PIO port B */
 #define	GREEN_LED	(1<<0)
diff --git a/board/atmel/at91sam9260ek/Kconfig b/board/atmel/at91sam9260ek/Kconfig
index 24a645bc94d..fe00ed5e60c 100644
--- a/board/atmel/at91sam9260ek/Kconfig
+++ b/board/atmel/at91sam9260ek/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_AT91SAM9260EK
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "at91sam9260ek"
 
diff --git a/board/atmel/at91sam9260ek/led.c b/board/atmel/at91sam9260ek/led.c
index 56d811ca425..fbe15afd281 100644
--- a/board/atmel/at91sam9260ek/led.c
+++ b/board/atmel/at91sam9260ek/led.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/gpio.h>
+#include <status_led.h>
 
 void coloured_LED_init(void)
 {
diff --git a/board/atmel/at91sam9261ek/Kconfig b/board/atmel/at91sam9261ek/Kconfig
index 301bf1a61c6..d839c1a6329 100644
--- a/board/atmel/at91sam9261ek/Kconfig
+++ b/board/atmel/at91sam9261ek/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_AT91SAM9261EK
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "at91sam9261ek"
 
diff --git a/board/atmel/at91sam9263ek/Kconfig b/board/atmel/at91sam9263ek/Kconfig
index f8e2b481495..311c504da28 100644
--- a/board/atmel/at91sam9263ek/Kconfig
+++ b/board/atmel/at91sam9263ek/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_AT91SAM9263EK
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "at91sam9263ek"
 
diff --git a/board/atmel/at91sam9m10g45ek/Kconfig b/board/atmel/at91sam9m10g45ek/Kconfig
index d2e191c141b..1bc086a4832 100644
--- a/board/atmel/at91sam9m10g45ek/Kconfig
+++ b/board/atmel/at91sam9m10g45ek/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_AT91SAM9M10G45EK
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "at91sam9m10g45ek"
 
diff --git a/board/atmel/at91sam9n12ek/Kconfig b/board/atmel/at91sam9n12ek/Kconfig
index 845cd36442d..cf1d1a3670c 100644
--- a/board/atmel/at91sam9n12ek/Kconfig
+++ b/board/atmel/at91sam9n12ek/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_AT91SAM9N12EK
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "at91sam9n12ek"
 
diff --git a/board/atmel/at91sam9rlek/Kconfig b/board/atmel/at91sam9rlek/Kconfig
index 517f22a8a96..438d300421d 100644
--- a/board/atmel/at91sam9rlek/Kconfig
+++ b/board/atmel/at91sam9rlek/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_AT91SAM9RLEK
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "at91sam9rlek"
 
diff --git a/board/atmel/at91sam9x5ek/Kconfig b/board/atmel/at91sam9x5ek/Kconfig
index d236b1ad66d..5c5ec615779 100644
--- a/board/atmel/at91sam9x5ek/Kconfig
+++ b/board/atmel/at91sam9x5ek/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_AT91SAM9X5EK
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "at91sam9x5ek"
 
diff --git a/board/atmel/sama5d3_xplained/Kconfig b/board/atmel/sama5d3_xplained/Kconfig
index 0ca1ec006ab..0ba8a7bf93b 100644
--- a/board/atmel/sama5d3_xplained/Kconfig
+++ b/board/atmel/sama5d3_xplained/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_SAMA5D3_XPLAINED
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "sama5d3_xplained"
 
diff --git a/board/atmel/sama5d3xek/Kconfig b/board/atmel/sama5d3xek/Kconfig
index f0dd04a06ed..2a9ed23ecf6 100644
--- a/board/atmel/sama5d3xek/Kconfig
+++ b/board/atmel/sama5d3xek/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_SAMA5D3XEK
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "sama5d3xek"
 
diff --git a/board/bachmann/ot1200/Kconfig b/board/bachmann/ot1200/Kconfig
index 6cf25732210..7f8a6a1abc3 100644
--- a/board/bachmann/ot1200/Kconfig
+++ b/board/bachmann/ot1200/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_OT1200
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "ot1200"
 
diff --git a/board/balloon3/Kconfig b/board/balloon3/Kconfig
index fb1cf3f0ef9..53b7a9a5c7e 100644
--- a/board/balloon3/Kconfig
+++ b/board/balloon3/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_BALLOON3
 
-config SYS_CPU
-	default "pxa"
-
 config SYS_BOARD
 	default "balloon3"
 
diff --git a/board/barco/titanium/Kconfig b/board/barco/titanium/Kconfig
index 56ed7d670bb..b6f7c855b51 100644
--- a/board/barco/titanium/Kconfig
+++ b/board/barco/titanium/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_TITANIUM
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "titanium"
 
diff --git a/board/bluegiga/apx4devkit/Kconfig b/board/bluegiga/apx4devkit/Kconfig
index 7d1534a647c..f327fa15cf0 100644
--- a/board/bluegiga/apx4devkit/Kconfig
+++ b/board/bluegiga/apx4devkit/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_APX4DEVKIT
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "apx4devkit"
 
diff --git a/board/bluewater/snapper9260/Kconfig b/board/bluewater/snapper9260/Kconfig
index 1c8f78dee2c..c896c46895b 100644
--- a/board/bluewater/snapper9260/Kconfig
+++ b/board/bluewater/snapper9260/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_SNAPPER9260
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "snapper9260"
 
diff --git a/board/boundary/nitrogen6x/Kconfig b/board/boundary/nitrogen6x/Kconfig
index 298c9fdb8cf..03b0f6f2783 100644
--- a/board/boundary/nitrogen6x/Kconfig
+++ b/board/boundary/nitrogen6x/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_NITROGEN6X
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "nitrogen6x"
 
diff --git a/board/broadcom/bcm28155_ap/Kconfig b/board/broadcom/bcm28155_ap/Kconfig
index 2e779f0174b..f1b4e089411 100644
--- a/board/broadcom/bcm28155_ap/Kconfig
+++ b/board/broadcom/bcm28155_ap/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_BCM28155_AP
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "bcm28155_ap"
 
diff --git a/board/broadcom/bcm958300k/Kconfig b/board/broadcom/bcm958300k/Kconfig
index d627a3885f0..92892881afe 100644
--- a/board/broadcom/bcm958300k/Kconfig
+++ b/board/broadcom/bcm958300k/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_BCM958300K
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "bcm_ep"
 
diff --git a/board/broadcom/bcm958622hr/Kconfig b/board/broadcom/bcm958622hr/Kconfig
index 9038f5b0a39..861c55909bf 100644
--- a/board/broadcom/bcm958622hr/Kconfig
+++ b/board/broadcom/bcm958622hr/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_BCM958622HR
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "bcm_ep"
 
diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c
index 659a124b227..b0d49c4ee6b 100644
--- a/board/buffalo/lsxl/lsxl.c
+++ b/board/buffalo/lsxl/lsxl.c
@@ -13,11 +13,12 @@
 #include <malloc.h>
 #include <netdev.h>
 #include <miiphy.h>
-#include <asm/arch/kirkwood.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/mpp.h>
 #include <asm/arch/gpio.h>
-#include <spi_flash.h>
 
 #include "lsxl.h"
 
@@ -51,9 +52,9 @@ int board_early_init_f(void)
 	 * There are maximum 64 gpios controlled through 2 sets of registers
 	 * the below configuration configures mainly initial LED status
 	 */
-	kw_config_gpio(LSXL_OE_VAL_LOW,
-			LSXL_OE_VAL_HIGH,
-			LSXL_OE_LOW, LSXL_OE_HIGH);
+	mvebu_config_gpio(LSXL_OE_VAL_LOW,
+			  LSXL_OE_VAL_HIGH,
+			  LSXL_OE_LOW, LSXL_OE_HIGH);
 
 	/*
 	 * Multi-Purpose Pins Functionality configuration
@@ -167,7 +168,7 @@ static void set_led(int state)
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	set_led(LED_POWER_BLINKING);
 
diff --git a/board/calao/sbc35_a9g20/Kconfig b/board/calao/sbc35_a9g20/Kconfig
index b2528dcd260..fb5a1a3f42c 100644
--- a/board/calao/sbc35_a9g20/Kconfig
+++ b/board/calao/sbc35_a9g20/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_SBC35_A9G20
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "sbc35_a9g20"
 
diff --git a/board/calao/tny_a9260/Kconfig b/board/calao/tny_a9260/Kconfig
index 7fad578d5c6..b1de8f8ba86 100644
--- a/board/calao/tny_a9260/Kconfig
+++ b/board/calao/tny_a9260/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_TNY_A9260
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "tny_a9260"
 
diff --git a/board/calao/usb_a9263/Kconfig b/board/calao/usb_a9263/Kconfig
index 4209b361364..7a159dc3ba5 100644
--- a/board/calao/usb_a9263/Kconfig
+++ b/board/calao/usb_a9263/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_USB_A9263
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "usb_a9263"
 
diff --git a/board/chromebook-x86/coreboot/Makefile b/board/chromebook-x86/coreboot/Makefile
index 4f2ac898ebc..27ebe78eb13 100644
--- a/board/chromebook-x86/coreboot/Makefile
+++ b/board/chromebook-x86/coreboot/Makefile
@@ -12,4 +12,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	+= coreboot_start.o
+obj-y	+= coreboot_start.o coreboot.o
diff --git a/board/chromebook-x86/coreboot/coreboot.c b/board/chromebook-x86/coreboot/coreboot.c
new file mode 100644
index 00000000000..0240c345810
--- /dev/null
+++ b/board/chromebook-x86/coreboot/coreboot.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+
+int arch_early_init_r(void)
+{
+	if (cros_ec_board_init())
+		return -1;
+
+	return 0;
+}
diff --git a/board/cirrus/edb93xx/Kconfig b/board/cirrus/edb93xx/Kconfig
index f063d557083..c5f4897f8ae 100644
--- a/board/cirrus/edb93xx/Kconfig
+++ b/board/cirrus/edb93xx/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_EDB93XX
 
-config SYS_CPU
-	default "arm920t"
-
 config SYS_BOARD
 	default "edb93xx"
 
diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c
index 0e632582d3d..8309d06882e 100644
--- a/board/cloudengines/pogo_e02/pogo_e02.c
+++ b/board/cloudengines/pogo_e02/pogo_e02.c
@@ -13,7 +13,7 @@
 #include <common.h>
 #include <miiphy.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include "pogo_e02.h"
 
@@ -26,9 +26,9 @@ int board_early_init_f(void)
 	 * There are maximum 64 gpios controlled through 2 sets of registers
 	 * the  below configuration configures mainly initial LED status
 	 */
-	kw_config_gpio(POGO_E02_OE_VAL_LOW,
-			POGO_E02_OE_VAL_HIGH,
-			POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
+	mvebu_config_gpio(POGO_E02_OE_VAL_LOW,
+			  POGO_E02_OE_VAL_HIGH,
+			  POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
 	static const u32 kwmpp_config[] = {
@@ -64,7 +64,7 @@ int board_early_init_f(void)
 int board_init(void)
 {
 	/* Boot parameters address */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
diff --git a/board/cm4008/Kconfig b/board/cm4008/Kconfig
index a7f3b2f8120..de87d5bc12d 100644
--- a/board/cm4008/Kconfig
+++ b/board/cm4008/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_CM4008
 
-config SYS_CPU
-	default "arm920t"
-
 config SYS_BOARD
 	default "cm4008"
 
diff --git a/board/cm41xx/Kconfig b/board/cm41xx/Kconfig
index b537e2674c8..99e675b12d9 100644
--- a/board/cm41xx/Kconfig
+++ b/board/cm41xx/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_CM41XX
 
-config SYS_CPU
-	default "arm920t"
-
 config SYS_BOARD
 	default "cm41xx"
 
diff --git a/board/compulab/cm_fx6/Kconfig b/board/compulab/cm_fx6/Kconfig
index 42a84380f24..508c21f58b1 100644
--- a/board/compulab/cm_fx6/Kconfig
+++ b/board/compulab/cm_fx6/Kconfig
@@ -1,23 +1,15 @@
 if TARGET_CM_FX6
 
-config SYS_CPU
-	string
-	default "armv7"
-
 config SYS_BOARD
-	string
 	default "cm_fx6"
 
 config SYS_VENDOR
-	string
 	default "compulab"
 
 config SYS_SOC
-	string
 	default "mx6"
 
 config SYS_CONFIG_NAME
-	string
 	default "cm_fx6"
 
 endif
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index 090f784cd9f..0206ae81fca 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -9,6 +9,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
 #include <netdev.h>
@@ -21,6 +22,7 @@
 #include <asm/imx-common/sata.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
+#include <dm/platform_data/serial_mxc.h>
 #include "common.h"
 #include "../common/eeprom.h"
 
@@ -69,16 +71,23 @@ static iomux_v3_cfg_t const sata_pads[] = {
 	IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
-static void cm_fx6_setup_issd(void)
+static int cm_fx6_setup_issd(void)
 {
+	int ret, i;
+
 	SETUP_IOMUX_PADS(sata_pads);
-	/* Make sure this gpio has logical 0 value */
-	gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
-	udelay(100);
 
-	cm_fx6_sata_power(0);
-	mdelay(250);
-	cm_fx6_sata_power(1);
+	for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
+		ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
+		if (ret)
+			return ret;
+	}
+
+	ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
+	if (ret)
+		return ret;
+
+	return 0;
 }
 
 #define CM_FX6_SATA_INIT_RETRIES	10
@@ -86,7 +95,14 @@ int sata_initialize(void)
 {
 	int err, i;
 
-	cm_fx6_setup_issd();
+	/* Make sure this gpio has logical 0 value */
+	gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
+	udelay(100);
+
+	cm_fx6_sata_power(0);
+	mdelay(250);
+	cm_fx6_sata_power(1);
+
 	for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
 		err = setup_sata();
 		if (err) {
@@ -109,6 +125,8 @@ int sata_initialize(void)
 
 	return err;
 }
+#else
+static int cm_fx6_setup_issd(void) { return 0; }
 #endif
 
 #ifdef CONFIG_SYS_I2C_MXC
@@ -141,49 +159,68 @@ I2C_PADS(i2c2_pads,
 	 IMX_GPIO_NR(1, 6));
 
 
-static void cm_fx6_setup_i2c(void)
+static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
+{
+	int ret;
+
+	ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
+	if (ret)
+		printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
+
+	return ret;
+}
+
+static int cm_fx6_setup_i2c(void)
 {
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c0_pads));
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c1_pads));
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c2_pads));
+	int ret = 0, err;
+
+	/* i2c<x>_pads are wierd macro variables; we can't use an array */
+	err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
+	if (err)
+		ret = err;
+	err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
+	if (err)
+		ret = err;
+	err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
+	if (err)
+		ret = err;
+
+	return ret;
 }
 #else
-static void cm_fx6_setup_i2c(void) { }
+static int cm_fx6_setup_i2c(void) { return 0; }
 #endif
 
 #ifdef CONFIG_USB_EHCI_MX6
 #define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
 			PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
 			PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
+#define MX6_USBNC_BASEADDR	0x2184800
+#define USBNC_USB_H1_PWR_POL	(1 << 9)
 
-static int cm_fx6_usb_hub_reset(void)
+static int cm_fx6_setup_usb_host(void)
 {
 	int err;
 
 	err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
-	if (err) {
-		printf("USB hub rst gpio request failed: %d\n", err);
-		return -1;
-	}
+	if (err)
+		return err;
 
+	SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
 	SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
-	gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
-	udelay(10);
-	gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
-	mdelay(1);
 
 	return 0;
 }
 
-static int cm_fx6_init_usb_otg(void)
+static int cm_fx6_setup_usb_otg(void)
 {
-	int ret;
+	int err;
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 
-	ret = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
-	if (ret) {
-		printf("USB OTG pwr gpio request failed: %d\n", ret);
-		return ret;
+	err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
+	if (err) {
+		printf("USB OTG pwr gpio request failed: %d\n", err);
+		return err;
 	}
 
 	SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
@@ -194,25 +231,27 @@ static int cm_fx6_init_usb_otg(void)
 	return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
 }
 
-#define MX6_USBNC_BASEADDR	0x2184800
-#define USBNC_USB_H1_PWR_POL	(1 << 9)
 int board_ehci_hcd_init(int port)
 {
+	int ret;
 	u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
 
-	switch (port) {
-	case 0:
-		return cm_fx6_init_usb_otg();
-	case 1:
-		SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR |
-				MUX_PAD_CTRL(NO_PAD_CTRL));
+	/* Only 1 host controller in use. port 0 is OTG & needs no attention */
+	if (port != 1)
+		return 0;
 
-		/* Set PWR polarity to match power switch's enable polarity */
-		setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
-		return cm_fx6_usb_hub_reset();
-	default:
-		break;
-	}
+	/* Set PWR polarity to match power switch's enable polarity */
+	setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
+	ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
+	if (ret)
+		return ret;
+
+	udelay(10);
+	ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
+	if (ret)
+		return ret;
+
+	mdelay(1);
 
 	return 0;
 }
@@ -224,6 +263,9 @@ int board_ehci_power(int port, int on)
 
 	return 0;
 }
+#else
+static int cm_fx6_setup_usb_otg(void) { return 0; }
+static int cm_fx6_setup_usb_host(void) { return 0; }
 #endif
 
 #ifdef CONFIG_FEC_MXC
@@ -318,12 +360,17 @@ static int handle_mac_address(void)
 
 int board_eth_init(bd_t *bis)
 {
-	int res = handle_mac_address();
-	if (res)
+	int err;
+
+	err = handle_mac_address();
+	if (err)
 		puts("No MAC address found\n");
 
 	SETUP_IOMUX_PADS(enet_pads);
 	/* phy reset */
+	err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
+	if (err)
+		printf("Etnernet NRST gpio request failed: %d\n", err);
 	gpio_direction_output(CM_FX6_ENET_NRST, 0);
 	udelay(500);
 	gpio_set_value(CM_FX6_ENET_NRST, 1);
@@ -394,6 +441,16 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_MXC_SPI
+int cm_fx6_setup_ecspi(void)
+{
+	cm_fx6_set_ecspi_iomux();
+	return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
+}
+#else
+int cm_fx6_setup_ecspi(void) { return 0; }
+#endif
+
 #ifdef CONFIG_OF_BOARD_SETUP
 void ft_board_setup(void *blob, bd_t *bd)
 {
@@ -409,9 +466,37 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 int board_init(void)
 {
+	int ret;
+
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 	cm_fx6_setup_gpmi_nand();
-	cm_fx6_setup_i2c();
+
+	ret = cm_fx6_setup_ecspi();
+	if (ret)
+		printf("Warning: ECSPI setup failed: %d\n", ret);
+
+	ret = cm_fx6_setup_usb_otg();
+	if (ret)
+		printf("Warning: USB OTG setup failed: %d\n", ret);
+
+	ret = cm_fx6_setup_usb_host();
+	if (ret)
+		printf("Warning: USB host setup failed: %d\n", ret);
+
+	/*
+	 * cm-fx6 may have iSSD not assembled and in this case it has
+	 * bypasses for a (m)SATA socket on the baseboard. The socketed
+	 * device is not controlled by those GPIOs. So just print a warning
+	 * if the setup fails.
+	 */
+	ret = cm_fx6_setup_issd();
+	if (ret)
+		printf("Warning: iSSD setup failed: %d\n", ret);
+
+	/* Warn on failure but do not abort boot */
+	ret = cm_fx6_setup_i2c();
+	if (ret)
+		printf("Warning: I2C setup failed: %d\n", ret);
 
 	return 0;
 }
@@ -481,3 +566,11 @@ u32 get_board_rev(void)
 	return cl_eeprom_get_board_rev();
 }
 
+static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
+	.reg = (struct mxc_uart *)UART4_BASE,
+};
+
+U_BOOT_DEVICE(cm_fx6_serial) = {
+	.name	= "serial_mxc",
+	.platdata = &cm_fx6_mxc_serial_plat,
+};
diff --git a/board/compulab/cm_t335/Kconfig b/board/compulab/cm_t335/Kconfig
index 61159765ab1..683efde7644 100644
--- a/board/compulab/cm_t335/Kconfig
+++ b/board/compulab/cm_t335/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_CM_T335
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "cm_t335"
 
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index 0944903ec88..d0b0930f423 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -53,16 +53,6 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = {
 	0
 };
 
-static u32 gpmc_nand_config[GPMC_MAX_REG] = {
-	M_NAND_GPMC_CONFIG1,
-	M_NAND_GPMC_CONFIG2,
-	M_NAND_GPMC_CONFIG3,
-	M_NAND_GPMC_CONFIG4,
-	M_NAND_GPMC_CONFIG5,
-	M_NAND_GPMC_CONFIG6,
-	0,
-};
-
 #ifdef CONFIG_LCD
 #ifdef CONFIG_CMD_NAND
 static int splash_load_from_nand(u32 bmp_load_addr)
@@ -148,9 +138,6 @@ int board_init(void)
 {
 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
 
-	enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
-			      CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
-
 	/* board id for Linux */
 	if (get_cpu_family() == CPU_OMAP34XX)
 		gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
@@ -381,7 +368,7 @@ static void cm_t3x_set_common_muxconf(void)
 	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)); /*OFF_MODE*/
 	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)); /*CLKOUT1*/
 	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTU | DIS | M4)); /*green LED*/
-	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)); /*JTAG_nTRST*/
+	MUX_VAL(CP(JTAG_NTRST),		(IEN  | PTD | DIS | M0)); /*JTAG_NTRST*/
 	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)); /*JTAG_TCK*/
 	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)); /*JTAG_TMS*/
 	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)); /*JTAG_TDI*/
@@ -457,6 +444,8 @@ void set_muxconf_regs(void)
 }
 
 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#define SB_T35_WP_GPIO 59
+
 int board_mmc_getcd(struct mmc *mmc)
 {
 	u8 val;
@@ -469,7 +458,7 @@ int board_mmc_getcd(struct mmc *mmc)
 
 int board_mmc_init(bd_t *bis)
 {
-	return omap_mmc_init(0, 0, 0, -1, 59);
+	return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO);
 }
 #endif
 
diff --git a/board/congatec/cgtqmx6eval/Kconfig b/board/congatec/cgtqmx6eval/Kconfig
index 0774784f788..0a837bde0e7 100644
--- a/board/congatec/cgtqmx6eval/Kconfig
+++ b/board/congatec/cgtqmx6eval/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_CGTQMX6EVAL
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "cgtqmx6eval"
 
diff --git a/board/creative/xfi3/Kconfig b/board/creative/xfi3/Kconfig
index 2255cc98bcc..7b681cd81b0 100644
--- a/board/creative/xfi3/Kconfig
+++ b/board/creative/xfi3/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_XFI3
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "xfi3"
 
diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c
index ff70e9415f0..a022daf71e4 100644
--- a/board/d-link/dns325/dns325.c
+++ b/board/d-link/dns325/dns325.c
@@ -14,7 +14,7 @@
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include <asm/arch/gpio.h>
 #include "dns325.h"
@@ -24,8 +24,8 @@ DECLARE_GLOBAL_DATA_PTR;
 int board_early_init_f(void)
 {
 	/* Gpio configuration */
-	kw_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
-			DNS325_OE_LOW, DNS325_OE_HIGH);
+	mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
+			  DNS325_OE_LOW, DNS325_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
 	static const u32 kwmpp_config[] = {
@@ -92,7 +92,7 @@ int board_early_init_f(void)
 int board_init(void)
 {
 	/* Boot parameters address */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
diff --git a/board/davedenx/qong/Kconfig b/board/davedenx/qong/Kconfig
index 54cb4502f05..76cf343dede 100644
--- a/board/davedenx/qong/Kconfig
+++ b/board/davedenx/qong/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_QONG
 
-config SYS_CPU
-	default "arm1136"
-
 config SYS_BOARD
 	default "qong"
 
diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig
index 1a8946d06ca..1286e4509f4 100644
--- a/board/dbau1x00/Kconfig
+++ b/board/dbau1x00/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_DBAU1X00
 
-config SYS_CPU
-	default "mips32"
-
 config SYS_BOARD
 	default "dbau1x00"
 
@@ -12,4 +9,22 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "dbau1x00"
 
+menu "dbau1x00 board options"
+
+choice
+	prompt "Select au1x00 SoC type"
+
+config DBAU1100
+	bool "Select AU1100"
+
+config DBAU1500
+	bool "Select AU1500"
+
+config DBAU1550
+	bool "Select AU1550"
+
+endchoice
+
+endmenu
+
 endif
diff --git a/board/denx/m28evk/Kconfig b/board/denx/m28evk/Kconfig
index b1c16c702b6..dd4dc4d096d 100644
--- a/board/denx/m28evk/Kconfig
+++ b/board/denx/m28evk/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_M28EVK
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "m28evk"
 
diff --git a/board/denx/m53evk/Kconfig b/board/denx/m53evk/Kconfig
index 5dbb7f8d5f6..0696ad7ffb7 100644
--- a/board/denx/m53evk/Kconfig
+++ b/board/denx/m53evk/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_M53EVK
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "m53evk"
 
diff --git a/board/egnite/ethernut5/Kconfig b/board/egnite/ethernut5/Kconfig
index 281e43a17f1..c42c734f1ff 100644
--- a/board/egnite/ethernut5/Kconfig
+++ b/board/egnite/ethernut5/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_ETHERNUT5
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "ethernut5"
 
diff --git a/board/eltec/mhpc/Kconfig b/board/eltec/mhpc/Kconfig
deleted file mode 100644
index 5a4c8844f04..00000000000
--- a/board/eltec/mhpc/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MHPC
-
-config SYS_BOARD
-	default "mhpc"
-
-config SYS_VENDOR
-	default "eltec"
-
-config SYS_CONFIG_NAME
-	default "MHPC"
-
-endif
diff --git a/board/eltec/mhpc/MAINTAINERS b/board/eltec/mhpc/MAINTAINERS
deleted file mode 100644
index 4d84a3533c0..00000000000
--- a/board/eltec/mhpc/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MHPC BOARD
-M:	Frank Gottschling <fgottschling@eltec.de>
-S:	Maintained
-F:	board/eltec/mhpc/
-F:	include/configs/MHPC.h
-F:	configs/MHPC_defconfig
diff --git a/board/eltec/mhpc/Makefile b/board/eltec/mhpc/Makefile
deleted file mode 100644
index f3fcc2f370e..00000000000
--- a/board/eltec/mhpc/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= mhpc.o flash.o
diff --git a/board/eltec/mhpc/flash.c b/board/eltec/mhpc/flash.c
deleted file mode 100644
index ad89df92cf0..00000000000
--- a/board/eltec/mhpc/flash.c
+++ /dev/null
@@ -1,414 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <linux/byteorder/swab.h>
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/*-----------------------------------------------------------------------
- * Protection Flags:
- */
-#define FLAG_PROTECT_SET	0x01
-#define FLAG_PROTECT_CLEAR	0x02
-
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH		ushort
-#define FLASH_PORT_WIDTHV		vu_short
-#define SWAP(x)                         __swab16(x)
-#else
-#define FLASH_PORT_WIDTH		ulong
-#define FLASH_PORT_WIDTHV		vu_long
-#define SWAP(x)                         __swab32(x)
-#endif
-
-#define FPW	FLASH_PORT_WIDTH
-#define FPWV	FLASH_PORT_WIDTHV
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (FPW *addr, flash_info_t *info);
-static int   write_data (flash_info_t *info, ulong dest, FPW data);
-static void  flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	unsigned long size_b0;
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-	size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
-	}
-
-	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
-
-	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-	/* monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    CONFIG_SYS_FLASH_BASE,
-			    CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
-			    &flash_info[0]);
-
-	flash_info[0].size = size_b0;
-
-	return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return;
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000);
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-		case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
-		default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-   case FLASH_28F640J5 :
-				printf ("28F640J5 \n"); break;
-	default:		printf ("Unknown Chip Type=0x%lXh\n",
-					info->flash_id & FLASH_TYPEMASK); break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (FPW *addr, flash_info_t *info)
-{
-	FPW value;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x5555] = (FPW)0xAA00AA00;
-	addr[0x2AAA] = (FPW)0x55005500;
-	addr[0x5555] = (FPW)0x90009000;
-
-	value = SWAP(addr[0]);
-
-   switch (value) {
-   case (FPW)INTEL_MANUFACT:
-      info->flash_id = FLASH_MAN_INTEL;
-      break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		addr[0] = (FPW)0xFF00FF00;      /* restore read mode */
-		return (0);			      /* no or unknown flash	*/
-	}
-
-   value = SWAP(addr[1]);			        /* device ID no swap !*/
-
-   switch (value) {
-   case (FPW)INTEL_ID_28F640J5 :
-	info->flash_id += FLASH_28F640J5 ;
-	info->sector_count = 64;
-	info->size = 0x00800000;
-	break;            /* => 8 MB     */
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		break;
-	}
-
-	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
-		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	}
-
-	addr[0] = (FPW)0xFF00FF00;      /* restore read mode */
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	int flag, prot, sect;
-	ulong type, start, now, last;
-	int rc = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	type = (info->flash_id & FLASH_VENDMASK);
-	if ((type != FLASH_MAN_INTEL)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	start = get_timer (0);
-	last  = start;
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			FPWV *addr = (FPWV *)(info->start[sect]);
-			FPW status;
-
-			/* Disable interrupts which might cause a timeout here */
-			flag = disable_interrupts();
-
-			*addr = (FPW)0x50005000;	/* clear status register */
-			*addr = (FPW)0x20002000;	/* erase setup */
-			*addr = (FPW)0xD000D000;	/* erase confirm */
-
-			/* re-enable interrupts if necessary */
-			if (flag)
-				enable_interrupts();
-
-			/* wait at least 80us - let's wait 1 ms */
-			udelay (1000);
-
-			while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
-				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-					printf ("Timeout\n");
-					*addr = (FPW)0xB000B000; /* suspend erase */
-					*addr = (FPW)0xFF00FF00; /* reset to read mode */
-					rc = 1;
-					break;
-				}
-
-				/* show that we're waiting */
-			if ((now - last) > 1000) {	/* every second */
-					putc ('.');
-					last = now;
-				}
-			}
-
-			*addr = (FPW)0xFF00FF00;	/* reset to read mode */
-			printf (" done\n");
-		}
-	}
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp;
-	FPW data;
-	int i, l, rc, port_width;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return 4;
-	}
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
-	wp = (addr & ~1);
-	port_width = 2;
-#else
-	wp = (addr & ~3);
-	port_width = 4;
-#endif
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp)
-			data = (data << 8) | (*(uchar *)cp);
-
-		for (; i<port_width && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<port_width; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_data(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += port_width;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= port_width) {
-		data = 0;
-		for (i=0; i<port_width; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_data(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += port_width;
-		cnt -= port_width;
-		if ((wp & 0xfff) == 0)
-		{
-			printf("%08lX",wp);
-			printf("\x1b[8D");
-		}
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<port_width; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_data(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, ulong dest, FPW data)
-{
-	FPWV *addr = (FPWV *)dest;
-	ulong status;
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) {
-		printf("not erased at %08lx (%x)\n",(ulong)addr,*addr);
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	*addr = (FPW)0x40004000;		/* write setup */
-	*addr = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	start = get_timer (0);
-
-	while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			*addr = (FPW)0xFF00FF00;	/* restore read mode */
-			return (1);
-		}
-	}
-
-	*addr = (FPW)0xFF00FF00;	/* restore read mode */
-
-	return (0);
-}
diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c
deleted file mode 100644
index 5781b2a54f3..00000000000
--- a/board/eltec/mhpc/mhpc.c
+++ /dev/null
@@ -1,465 +0,0 @@
-/*
- * (C) Copyright 2001
- * ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * Board specific routines for the miniHiPerCam
- *
- * - initialisation (eeprom)
- * - memory controller
- * - serial io initialisation
- * - ethernet io initialisation
- *
- * -----------------------------------------------------------------
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <cli.h>
-#include <linux/ctype.h>
-#include <commproc.h>
-#include "mpc8xx.h"
-#include <video_fb.h>
-
-extern void eeprom_init (void);
-extern int eeprom_read (unsigned dev_addr, unsigned offset,
-			unsigned char *buffer, unsigned cnt);
-extern int eeprom_write (unsigned dev_addr, unsigned offset,
-			 unsigned char *buffer, unsigned cnt);
-
-/* globals */
-void *video_hw_init (void);
-void video_set_lut (unsigned int index,	/* color number */
-		    unsigned char r,	/* red */
-		    unsigned char g,	/* green */
-		    unsigned char b	/* blue */
-	);
-
-GraphicDevice gdev;
-
-/* locals */
-static void video_circle (char *center, int radius, int color, int pitch);
-static void video_test_image (void);
-static void video_default_lut (unsigned int clut_type);
-
-/* revision info foer MHPC EEPROM offset 480 */
-typedef struct {
-	char board[12];		/* 000 - Board Revision information */
-	char sensor;		/* 012 - Sensor Type information */
-	char serial[8];		/* 013 - Board serial number */
-	char etheraddr[6];	/* 021 - Ethernet node addresse */
-	char revision[2];	/* 027 - Revision code */
-	char option[3];		/* 029 - resevered for options */
-} revinfo;
-
-/* ------------------------------------------------------------------------- */
-
-static const unsigned int sdram_table[] = {
-	/* read single beat cycle */
-	0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00,
-	0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35,
-
-	/* read burst cycle */
-	0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00,
-	0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05,
-	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* write single beat cycle */
-	0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05,
-	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* write burst cycle */
-	0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440,
-	0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04,
-	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* periodic timer expired */
-	0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84,
-	0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05,
-	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* exception */
-	0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04
-};
-
-/* ------------------------------------------------------------------------- */
-
-int board_early_init_f (void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile cpm8xx_t *cp = &(im->im_cpm);
-	volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport);
-
-	/* reset the port A s.a. cpm-routines */
-	ip->iop_padat = 0x0000;
-	ip->iop_papar = 0x0000;
-	ip->iop_padir = 0x0800;
-	ip->iop_paodr = 0x0000;
-
-	/* reset the port B for digital and LCD output */
-	cp->cp_pbdat = 0x0300;
-	cp->cp_pbpar = 0x5001;
-	cp->cp_pbdir = 0x5301;
-	cp->cp_pbodr = 0x0000;
-
-	/* reset the port C configured for SMC1 serial port and aqc. control */
-	ip->iop_pcdat = 0x0800;
-	ip->iop_pcpar = 0x0000;
-	ip->iop_pcdir = 0x0e30;
-	ip->iop_pcso = 0x0000;
-
-	/* Config port D for LCD output */
-	ip->iop_pdpar = 0x1fff;
-	ip->iop_pddir = 0x1fff;
-
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity
- */
-int checkboard (void)
-{
-	puts ("Board: ELTEC miniHiperCam\n");
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_r (void)
-{
-	revinfo mhpcRevInfo;
-	char nid[32];
-	char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color",
-		"OMNIVISON OV7110 b&w", NULL
-	};
-	char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
-		0, 0, 0, 0, 10, 11, 12, 13, 14, 15
-	};
-	int i;
-
-	/* check revision data */
-	eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32);
-
-	if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) {
-		printf ("Enter revision number (0-9): %c  ",
-			mhpcRevInfo.revision[0]);
-		if (0 != cli_readline(NULL)) {
-			mhpcRevInfo.revision[0] =
-				(char) toupper (console_buffer[0]);
-		}
-
-		printf ("Enter revision character (A-Z): %c  ",
-			mhpcRevInfo.revision[1]);
-		if (1 == cli_readline(NULL)) {
-			mhpcRevInfo.revision[1] =
-				(char) toupper (console_buffer[0]);
-		}
-
-		printf ("Enter board name (V-XXXX-XXXX): %s  ",
-			(char *) &mhpcRevInfo.board);
-		if (11 == cli_readline(NULL)) {
-			for (i = 0; i < 11; i++) {
-				mhpcRevInfo.board[i] =
-					(char) toupper (console_buffer[i]);
-				mhpcRevInfo.board[11] = '\0';
-			}
-		}
-
-		printf ("Supported sensor types:\n");
-		i = 0;
-		do {
-			printf ("\n    \'%d\' : %s\n", i, mhpcSensorTypes[i]);
-		} while (mhpcSensorTypes[++i] != NULL);
-
-		do {
-			printf ("\nEnter sensor number (0-255): %d  ",
-				(int) mhpcRevInfo.sensor);
-			if (0 != cli_readline(NULL)) {
-				mhpcRevInfo.sensor =
-					(unsigned char)
-					simple_strtoul (console_buffer, NULL,
-							10);
-			}
-		} while (mhpcRevInfo.sensor >= i);
-
-		printf ("Enter serial number: %s ",
-			(char *) &mhpcRevInfo.serial);
-		if (6 == cli_readline(NULL)) {
-			for (i = 0; i < 6; i++) {
-				mhpcRevInfo.serial[i] = console_buffer[i];
-			}
-			mhpcRevInfo.serial[6] = '\0';
-		}
-
-		printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
-		if (12 == cli_readline(NULL)) {
-			for (i = 0; i < 12; i += 2) {
-				mhpcRevInfo.etheraddr[i >> 1] =
-					(char) (16 *
-						hex[toupper
-						    (console_buffer[i]) -
-						    '0'] +
-						hex[toupper
-						    (console_buffer[i + 1]) -
-						    '0']);
-			}
-		}
-
-		/* setup new revision data */
-		eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo,
-			      32);
-	}
-
-	/* set environment */
-	sprintf (nid, "%02x:%02x:%02x:%02x:%02x:%02x",
-		 mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
-		 mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
-		 mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
-	setenv ("ethaddr", nid);
-
-	/* print actual board identification */
-	printf ("Ident: %s %s Ser %s Rev %c%c\n",
-		mhpcRevInfo.board,
-		(mhpcRevInfo.sensor == 0 ? "color" : "b&w"),
-		(char *) &mhpcRevInfo.serial, mhpcRevInfo.revision[0],
-		mhpcRevInfo.revision[1]);
-
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	upmconfig (UPMA, (uint *) sdram_table,
-		   sizeof (sdram_table) / sizeof (uint));
-
-	memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
-	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* should this be mamr? - NTL */
-	memctl->memc_mptpr = MPTPR_PTP_DIV64;
-	memctl->memc_mar = 0x00008800;
-
-	/*
-	 * Map controller SDRAM bank 0
-	 */
-	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
-	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
-	udelay (200);
-
-	/*
-	 * Map controller SDRAM bank 1
-	 */
-	memctl->memc_or2 = CONFIG_SYS_OR2;
-	memctl->memc_br2 = CONFIG_SYS_BR2;
-
-	/*
-	 * Perform SDRAM initializsation sequence
-	 */
-	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
-	udelay (1);
-	memctl->memc_mcr = 0x80002730;	/* SDRAM bank 0 - execute twice */
-	udelay (1);
-	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
-
-	udelay (10000);
-
-	/* leave place for framebuffers */
-	return (SDRAM_MAX_SIZE - SDRAM_RES_SIZE);
-}
-
-/* ------------------------------------------------------------------------- */
-
-static void video_circle (char *center, int radius, int color, int pitch)
-{
-	int x, y, d, dE, dSE;
-
-	x = 0;
-	y = radius;
-	d = 1 - radius;
-	dE = 3;
-	dSE = -2 * radius + 5;
-
-	*(center + x + y * pitch) = color;
-	*(center + y + x * pitch) = color;
-	*(center + y - x * pitch) = color;
-	*(center + x - y * pitch) = color;
-	*(center - x - y * pitch) = color;
-	*(center - y - x * pitch) = color;
-	*(center - y + x * pitch) = color;
-	*(center - x + y * pitch) = color;
-	while (y > x) {
-		if (d < 0) {
-			d += dE;
-			dE += 2;
-			dSE += 2;
-			x++;
-		} else {
-			d += dSE;
-			dE += 2;
-			dSE += 4;
-			x++;
-			y--;
-		}
-		*(center + x + y * pitch) = color;
-		*(center + y + x * pitch) = color;
-		*(center + y - x * pitch) = color;
-		*(center + x - y * pitch) = color;
-		*(center - x - y * pitch) = color;
-		*(center - y - x * pitch) = color;
-		*(center - y + x * pitch) = color;
-		*(center - x + y * pitch) = color;
-	}
-}
-
-/* ------------------------------------------------------------------------- */
-
-static void video_test_image (void)
-{
-	char *di;
-	int i, n;
-
-	/* draw raster */
-	for (i = 0; i < LCD_VIDEO_ROWS; i += 32) {
-		memset ((char *) (LCD_VIDEO_ADDR + i * LCD_VIDEO_COLS),
-			LCD_VIDEO_FG, LCD_VIDEO_COLS);
-		for (n = i + 1; n < i + 32; n++)
-			memset ((char *) (LCD_VIDEO_ADDR +
-					  n * LCD_VIDEO_COLS), LCD_VIDEO_BG,
-				LCD_VIDEO_COLS);
-	}
-
-	for (i = 0; i < LCD_VIDEO_COLS; i += 32) {
-		for (n = 0; n < LCD_VIDEO_ROWS; n++)
-			*(char *) (LCD_VIDEO_ADDR + n * LCD_VIDEO_COLS + i) =
-				LCD_VIDEO_FG;
-	}
-
-	/* draw gray bar */
-	di = (char *) (LCD_VIDEO_ADDR + (LCD_VIDEO_COLS - 256) / 64 * 32 +
-		       97 * LCD_VIDEO_COLS);
-	for (n = 0; n < 63; n++) {
-		for (i = 0; i < 256; i++) {
-			*di++ = (char) i;
-			*(di + LCD_VIDEO_COLS * 64) = (i & 1) * 255;
-		}
-		di += LCD_VIDEO_COLS - 256;
-	}
-
-	video_circle ((char *) LCD_VIDEO_ADDR + LCD_VIDEO_COLS / 2 +
-		      LCD_VIDEO_ROWS / 2 * LCD_VIDEO_COLS, LCD_VIDEO_ROWS / 2,
-		      LCD_VIDEO_FG, LCD_VIDEO_COLS);
-}
-
-/* ------------------------------------------------------------------------- */
-
-static void video_default_lut (unsigned int clut_type)
-{
-	unsigned int i;
-	unsigned char RGB[] = {
-		0x00, 0x00, 0x00,	/* black */
-		0x80, 0x80, 0x80,	/* gray */
-		0xff, 0x00, 0x00,	/* red */
-		0x00, 0xff, 0x00,	/* green */
-		0x00, 0x00, 0xff,	/* blue */
-		0x00, 0xff, 0xff,	/* cyan */
-		0xff, 0x00, 0xff,	/* magenta */
-		0xff, 0xff, 0x00,	/* yellow */
-		0x80, 0x00, 0x00,	/* dark red */
-		0x00, 0x80, 0x00,	/* dark green */
-		0x00, 0x00, 0x80,	/* dark blue */
-		0x00, 0x80, 0x80,	/* dark cyan */
-		0x80, 0x00, 0x80,	/* dark magenta */
-		0x80, 0x80, 0x00,	/* dark yellow */
-		0xc0, 0xc0, 0xc0,	/* light gray */
-		0xff, 0xff, 0xff,	/* white */
-	};
-
-	switch (clut_type) {
-	case 1:
-		for (i = 0; i < 240; i++)
-			video_set_lut (i, i, i, i);
-		for (i = 0; i < 16; i++)
-			video_set_lut (i + 240, RGB[i * 3], RGB[i * 3 + 1],
-				       RGB[i * 3 + 2]);
-		break;
-	default:
-		for (i = 0; i < 256; i++)
-			video_set_lut (i, i, i, i);
-	}
-}
-
-/* ------------------------------------------------------------------------- */
-
-void *video_hw_init (void)
-{
-	unsigned int clut = 0;
-	unsigned char *penv;
-	immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
-	/* enable video only on CLUT value */
-	if ((penv = (uchar *)getenv ("clut")) != NULL)
-		clut = (u_int) simple_strtoul ((char *)penv, NULL, 10);
-	else
-		return NULL;
-
-	/* disable graphic before write LCD regs. */
-	immr->im_lcd.lcd_lccr = 0x96000866;
-
-	/* config LCD regs. */
-	immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR;
-	immr->im_lcd.lcd_lchcr = 0x010a0093;
-	immr->im_lcd.lcd_lcvcr = 0x900f0024;
-
-	printf ("Video: 640x480 8Bit Index Lut %s\n",
-		(clut == 1 ? "240/16 (gray/vga)" : "256(gray)"));
-
-	video_default_lut (clut);
-
-	/* clear framebuffer */
-	memset ((char *) (LCD_VIDEO_ADDR), LCD_VIDEO_BG,
-		LCD_VIDEO_ROWS * LCD_VIDEO_COLS);
-
-	/* enable graphic */
-	immr->im_lcd.lcd_lccr = 0x96000867;
-
-	/* fill in Graphic Device */
-	gdev.frameAdrs = LCD_VIDEO_ADDR;
-	gdev.winSizeX = LCD_VIDEO_COLS;
-	gdev.winSizeY = LCD_VIDEO_ROWS;
-	gdev.gdfBytesPP = 1;
-	gdev.gdfIndex = GDF__8BIT_INDEX;
-
-	if (clut > 1)
-		/* return Graphic Device for console */
-		return (void *) &gdev;
-	else
-		/* just graphic enabled - draw something beautiful */
-		video_test_image ();
-
-	return NULL;		/* this disabels cfb - console */
-}
-
-/* ------------------------------------------------------------------------- */
-
-void video_set_lut (unsigned int index,
-		    unsigned char r, unsigned char g, unsigned char b)
-{
-	unsigned int lum;
-	unsigned short *pLut = (unsigned short *) (CONFIG_SYS_IMMR + 0x0e00);
-
-	/* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */
-	/* y = 0.299*R + 0.587*G + 0.114*B */
-	lum = (2990 * r + 5870 * g + 1140 * b) / 10000;
-	pLut[index] =
-		((b & 0xc0) << 4) | ((g & 0xc0) << 2) | (r & 0xc0) | (lum &
-								      0x3f);
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug
deleted file mode 100644
index b0091db0c6b..00000000000
--- a/board/eltec/mhpc/u-boot.lds.debug
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib/vsprintf.o	(.text)
-    lib/crc32.o		(.text)
-
-    . = env_offset;
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/embest/mx6boards/Kconfig b/board/embest/mx6boards/Kconfig
index 8e39fce6fec..53a39d31dd1 100644
--- a/board/embest/mx6boards/Kconfig
+++ b/board/embest/mx6boards/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_EMBESTMX6BOARDS
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "mx6boards"
 
diff --git a/board/emk/common/am79c874.c b/board/emk/common/am79c874.c
deleted file mode 100644
index b3840a22229..00000000000
--- a/board/emk/common/am79c874.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * (C) Copyright 2003
- * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-/*****************************************************************************
- * check fiber optic link present, and then copper link present. do auto switch
- * between both
- *****************************************************************************/
diff --git a/board/emk/common/flash.c b/board/emk/common/flash.c
deleted file mode 100644
index ae5777c796f..00000000000
--- a/board/emk/common/flash.c
+++ /dev/null
@@ -1,575 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003
- * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined (CONFIG_TOP860)
-  typedef unsigned short FLASH_PORT_WIDTH;
-  typedef volatile unsigned short FLASH_PORT_WIDTHV;
-  #define	FLASH_ID_MASK	0xFF
-
-  #define FPW	FLASH_PORT_WIDTH
-  #define FPWV	FLASH_PORT_WIDTHV
-
-  #define FLASH_CYCLE1	0x0555
-  #define FLASH_CYCLE2	0x02aa
-  #define FLASH_ID1		0
-  #define FLASH_ID2		1
-  #define FLASH_ID3		0x0e
-  #define FLASH_ID4		0x0F
-#endif
-
-#if defined (CONFIG_TOP5200) && !defined (CONFIG_LITE5200)
-  typedef unsigned char FLASH_PORT_WIDTH;
-  typedef volatile unsigned char FLASH_PORT_WIDTHV;
-  #define	FLASH_ID_MASK	0xFF
-
-  #define FPW	FLASH_PORT_WIDTH
-  #define FPWV	FLASH_PORT_WIDTHV
-
-  #define FLASH_CYCLE1	0x0aaa
-  #define FLASH_CYCLE2	0x0555
-  #define FLASH_ID1		0
-  #define FLASH_ID2		2
-  #define FLASH_ID3		0x1c
-  #define FLASH_ID4		0x1E
-#endif
-
-#if defined (CONFIG_TOP5200) && defined (CONFIG_LITE5200)
-  typedef unsigned char FLASH_PORT_WIDTH;
-  typedef volatile unsigned char FLASH_PORT_WIDTHV;
-  #define	FLASH_ID_MASK	0xFF
-
-  #define FPW	FLASH_PORT_WIDTH
-  #define FPWV	FLASH_PORT_WIDTHV
-
-  #define FLASH_CYCLE1	0x0555
-  #define FLASH_CYCLE2	0x02aa
-  #define FLASH_ID1		0
-  #define FLASH_ID2		1
-  #define FLASH_ID3		0x0E
-  #define FLASH_ID4		0x0F
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV *addr, flash_info_t *info);
-static void flash_reset(flash_info_t *info);
-static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
-flash_info_t *flash_get_info(ulong base);
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
-	unsigned long size = 0;
-	int i = 0;
-	extern void flash_preinit(void);
-	extern void flash_afterinit(uint, ulong, ulong);
-	ulong flashbase = CONFIG_SYS_FLASH_BASE;
-
-	flash_preinit();
-
-	/* There is only ONE FLASH device */
-	memset(&flash_info[i], 0, sizeof(flash_info_t));
-	flash_info[i].size =
-			flash_get_size((FPW *)flashbase, &flash_info[i]);
-	size += flash_info[i].size;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
-		      flash_get_info(CONFIG_ENV_ADDR));
-#endif
-
-
-	flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
-	return size ? size : 1;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t *info)
-{
-	FPWV *base = (FPWV *)(info->start[0]);
-
-	/* Put FLASH back in read mode */
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
-		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
-	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
-		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
-}
-
-/*-----------------------------------------------------------------------
- */
-
-flash_info_t *flash_get_info(ulong base)
-{
-	int i;
-	flash_info_t * info;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
-		info = & flash_info[i];
-		if (info->size &&
-			info->start[0] <= base && base <= info->start[0] + info->size - 1)
-			break;
-	}
-
-	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
-	int i;
-	uchar *boottype;
-	uchar *bootletter;
-	char *fmt;
-	uchar botbootletter[] = "B";
-	uchar topbootletter[] = "T";
-	uchar botboottype[] = "bottom boot sector";
-	uchar topboottype[] = "top boot sector";
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-#if 0
-	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	case FLASH_MAN_SST:	printf ("SST ");		break;
-	case FLASH_MAN_STM:	printf ("STM ");		break;
-	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
-#endif
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	/* check for top or bottom boot, if it applies */
-	if (info->flash_id & FLASH_BTYPE) {
-		boottype = botboottype;
-		bootletter = botbootletter;
-	}
-	else {
-		boottype = topboottype;
-		bootletter = topbootletter;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM160T:
-	case FLASH_AM160B:
-		fmt = "29LV160%s (16 Mbit, %s)\n";
-		break;
-	case FLASH_AMLV640U:
-		fmt = "29LV640M (64 Mbit)\n";
-		break;
-	case FLASH_AMDLV065D:
-		fmt = "29LV065D (64 Mbit)\n";
-		break;
-	case FLASH_AMLV256U:
-		fmt = "29LV256M (256 Mbit)\n";
-		break;
-	default:
-		fmt = "Unknown Chip Type\n";
-		break;
-	}
-
-	printf (fmt, bootletter, boottype);
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20,
-		info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-
-	for (i=0; i<info->sector_count; ++i) {
-		ulong	size;
-		int		erased;
-		ulong	*flash = (unsigned long *) info->start[i];
-
-		if ((i % 5) == 0) {
-			printf ("\n   ");
-		}
-
-		/*
-		 * Check if whole sector is erased
-		 */
-		size =
-			(i != (info->sector_count - 1)) ?
-			(info->start[i + 1] - info->start[i]) >> 2 :
-		(info->start[0] + info->size - info->start[i]) >> 2;
-
-		for (
-			flash = (unsigned long *) info->start[i], erased = 1;
-				(flash != (unsigned long *) info->start[i] + size) && erased;
-					flash++
-			)
-			erased = *flash == ~0x0UL;
-
-		printf (" %08lX %s %s",
-			info->start[i],
-			erased ? "E": " ",
-			info->protect[i] ? "(RO)" : "    ");
-	}
-
-	printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size (FPWV *addr, flash_info_t *info)
-{
-	int		i;
-
-	/* Write auto select command: read Manufacturer ID */
-	/* Write auto select command sequence and test FLASH answer */
-	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
-	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
-	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
-
-	/* The manufacturer codes are only 1 byte, so just use 1 byte.
-	 * This works for any bus width and any FLASH device width.
-	 */
-	udelay(100);
-	switch (addr[FLASH_ID1] & 0xff) {
-
-	case (uchar)AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-
-#if 0
-	case (uchar)INTEL_MANUFACT:
-		info->flash_id = FLASH_MAN_INTEL;
-		break;
-#endif
-
-	default:
-		printf ("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		break;
-	}
-
-	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
-	if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[FLASH_ID2]) {
-
-	case (FPW)AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00200000;
-		info->start[0] = (ulong)addr;
-		info->start[1] = (ulong)addr + 0x4000;
-		info->start[2] = (ulong)addr + 0x6000;
-		info->start[3] = (ulong)addr + 0x8000;
-		for (i = 4; i < info->sector_count; i++)
-		{
-			info->start[i] = (ulong)addr + 0x10000 * (i-3);
-		}
-		break;
-
-	case (FPW)AMD_ID_LV065D:
-		info->flash_id += FLASH_AMDLV065D;
-		info->sector_count = 128;
-		info->size = 0x00800000;
-		for (i = 0; i < info->sector_count; i++)
-		{
-			info->start[i] = (ulong)addr + 0x10000 * i;
-		}
-		break;
-
-	case (FPW)AMD_ID_MIRROR:
-		/* MIRROR BIT FLASH, read more ID bytes */
-		if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV640U_2 &&
-			(FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV640U_3)
-		{
-			info->flash_id += FLASH_AMLV640U;
-			info->sector_count = 128;
-			info->size = 0x00800000;
-			for (i = 0; i < info->sector_count; i++)
-			{
-				info->start[i] = (ulong)addr + 0x10000 * i;
-			}
-			break;
-		}
-		if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV256U_2 &&
-			(FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV256U_3)
-		{
-			/* attention: only the first 16 MB will be used in u-boot */
-			info->flash_id += FLASH_AMLV256U;
-			info->sector_count = 256;
-			info->size = 0x01000000;
-			for (i = 0; i < info->sector_count; i++)
-			{
-				info->start[i] = (ulong)addr + 0x10000 * i;
-			}
-			break;
-		}
-
-		/* fall thru to here ! */
-	default:
-		printf ("unknown AMD device=%x %x %x",
-			(FPW)addr[FLASH_ID2],
-			(FPW)addr[FLASH_ID3],
-			(FPW)addr[FLASH_ID4]);
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0x800000;
-		break;
-	}
-
-	/* Put FLASH back in read mode */
-	flash_reset(info);
-
-	return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	FPWV *addr;
-	int flag, prot, sect;
-	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
-	ulong start, now, last;
-	int rcode = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM160B:
-	case FLASH_AMLV640U:
-		break;
-	case FLASH_UNKNOWN:
-	default:
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	last  = get_timer(0);
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
-
-		if (info->protect[sect] != 0)	/* protected, skip it */
-			continue;
-
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr = (FPWV *)(info->start[sect]);
-		if (intel) {
-			*addr = (FPW)0x00500050; /* clear status register */
-			*addr = (FPW)0x00200020; /* erase setup */
-			*addr = (FPW)0x00D000D0; /* erase confirm */
-		}
-		else {
-			/* must be AMD style if not Intel */
-			FPWV *base;		/* first address in bank */
-
-			base = (FPWV *)(info->start[0]);
-			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
-			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
-			base[FLASH_CYCLE1] = (FPW)0x00800080;	/* erase mode */
-			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
-			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
-			*addr = (FPW)0x00300030;	/* erase sector */
-		}
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		start = get_timer(0);
-
-		/* wait at least 50us for AMD, 80us for Intel.
-		 * Let's wait 1 ms.
-		 */
-		udelay (1000);
-
-		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
-			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-				printf ("Timeout\n");
-
-				if (intel) {
-					/* suspend erase	*/
-					*addr = (FPW)0x00B000B0;
-				}
-
-				flash_reset(info);	/* reset to read mode */
-				rcode = 1;		/* failed */
-				break;
-			}
-
-			/* show that we're waiting */
-			if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
-				putc ('.');
-				last = get_timer(0);
-			}
-		}
-
-		/* show that we're waiting */
-		if ((get_timer(last)) > CONFIG_SYS_HZ) {	/* every second */
-			putc ('.');
-			last = get_timer(0);
-		}
-
-		flash_reset(info);	/* reset to read mode */
-	}
-
-	printf (" done\n");
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
-	int bytes;	  /* number of bytes to program in current word		*/
-	int left;	  /* number of bytes left to program			*/
-	int i, res;
-
-	for (left = cnt, res = 0;
-		 left > 0 && res == 0;
-		 addr += sizeof(data), left -= sizeof(data) - bytes) {
-
-		bytes = addr & (sizeof(data) - 1);
-		addr &= ~(sizeof(data) - 1);
-
-		/* combine source and destination data so can program
-		 * an entire word of 16 or 32 bits
-		 */
-		for (i = 0; i < sizeof(data); i++) {
-			data <<= 8;
-			if (i < bytes || i - bytes >= left )
-				data += *((uchar *)addr + i);
-			else
-				data += *src++;
-		}
-
-		/* write one word to the flash */
-		switch (info->flash_id & FLASH_VENDMASK) {
-		case FLASH_MAN_AMD:
-			res = write_word_amd(info, (FPWV *)addr, data);
-			break;
-		default:
-			/* unknown flash type, error! */
-			printf ("missing or unknown FLASH type\n");
-			res = 1;	/* not really a timeout, but gives error */
-			break;
-		}
-	}
-
-	return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
-{
-	ulong start;
-	int flag;
-	int res = 0;	/* result, assume success	*/
-	FPWV *base;		/* first address in flash bank	*/
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*dest & data) != data) {
-		return (2);
-	}
-
-
-	base = (FPWV *)(info->start[0]);
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
-	base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
-	base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
-
-	*dest = data;		/* start programming the data	*/
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	start = get_timer (0);
-
-	/* data polling for D7 */
-	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			*dest = (FPW)0x00F000F0;	/* reset bank */
-			res = 1;
-		}
-	}
-
-	return (res);
-}
diff --git a/board/emk/common/vpd.c b/board/emk/common/vpd.c
deleted file mode 100644
index d9af92a528b..00000000000
--- a/board/emk/common/vpd.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2003
- * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-/*****************************************************************************
- * read "factory" part of EEPROM and set some environment variables
- *****************************************************************************/
-void read_factory_r (void)
-{
-	/* read 'factory' part of EEPROM */
-	uchar buf[81];
-	uchar *p;
-	uint length;
-	uint addr;
-	uint len;
-
-	/* get length first */
-	addr = CONFIG_SYS_FACT_OFFSET;
-	if (eeprom_read (CONFIG_SYS_I2C_FACT_ADDR, addr, buf, 2)) {
-	  bailout:
-		printf ("cannot read factory configuration\n");
-		printf ("be sure to set ethaddr	yourself!\n");
-		return;
-	}
-	length = buf[0] + (buf[1] << 8);
-	addr += 2;
-
-	/* sanity check */
-	if (length < 20 || length > CONFIG_SYS_FACT_SIZE - 2)
-		goto bailout;
-
-	/* read lines */
-	while (length > 0) {
-		/* read one line */
-		len = length > 80 ? 80 : length;
-		if (eeprom_read (CONFIG_SYS_I2C_FACT_ADDR, addr, buf, len))
-			goto bailout;
-		/* mark end of buffer */
-		buf[len] = 0;
-		/* search end of line */
-		for (p = buf; *p && *p != 0x0a; p++);
-		if (!*p)
-			goto bailout;
-		*p++ = 0;
-		/* advance to next line start */
-		length -= p - buf;
-		addr += p - buf;
-		/*printf ("%s\n", buf); */
-		/* search for our specific entry */
-		if (!strncmp ((char *) buf, "[RLA/lan/Ethernet] ", 19)) {
-			setenv ("ethaddr", (char *)(buf + 19));
-		} else if (!strncmp ((char *) buf, "[BOARD/SERIAL] ", 15)) {
-			setenv ("serial#", (char *)(buf + 15));
-		} else if (!strncmp ((char *) buf, "[BOARD/TYPE] ", 13)) {
-			setenv ("board_id", (char *)(buf + 13));
-		}
-	}
-}
diff --git a/board/emk/top5200/Kconfig b/board/emk/top5200/Kconfig
deleted file mode 100644
index bba1fd4d9bc..00000000000
--- a/board/emk/top5200/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_TOP5200
-
-config SYS_BOARD
-	default "top5200"
-
-config SYS_VENDOR
-	default "emk"
-
-config SYS_CONFIG_NAME
-	default "TOP5200"
-
-endif
diff --git a/board/emk/top5200/MAINTAINERS b/board/emk/top5200/MAINTAINERS
deleted file mode 100644
index 72fea41969b..00000000000
--- a/board/emk/top5200/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-TOP5200 BOARD
-M:	Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-S:	Maintained
-F:	board/emk/top5200/
-F:	include/configs/TOP5200.h
-F:	configs/EVAL5200_defconfig
-F:	configs/MINI5200_defconfig
-F:	configs/TOP5200_defconfig
diff --git a/board/emk/top5200/Makefile b/board/emk/top5200/Makefile
deleted file mode 100644
index b455c26e17d..00000000000
--- a/board/emk/top5200/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= top5200.o ../common/flash.o ../common/vpd.o ../common/am79c874.o
diff --git a/board/emk/top5200/top5200.c b/board/emk/top5200/top5200.c
deleted file mode 100644
index 8eaf7cbde30..00000000000
--- a/board/emk/top5200/top5200.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003
- * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-
-/*****************************************************************************
- * initialize SDRAM/DDRAM controller.
- * TBD: get data from I2C EEPROM
- *****************************************************************************/
-phys_size_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-#if 0
-	ulong	t;
-	ulong	tap_del;
-#endif
-
-	#define	MODE_EN		0x80000000
-	#define	SOFT_PRE	2
-	#define	SOFT_REF	4
-
-	/* configure SDRAM start/end */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | CONFIG_SYS_DRAM_RAM_SIZE;
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CONFIG_SYS_DRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CONFIG_SYS_DRAM_CONFIG2;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN;
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE;
-#ifdef CONFIG_SYS_DRAM_DDR
-	/* set extended mode register */
-	*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_EMODE;
-#endif
-	/* set mode register */
-	*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE | 0x0400;
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE;
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_REF;
-	/* set mode register */
-	*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE;
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL;
-	/* write default TAP delay */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = CONFIG_SYS_DRAM_TAP_DEL << 24;
-
-#if 0
-	for (tap_del = 0; tap_del < 32; tap_del++)
-	{
-		*(vu_long *)MPC5XXX_CDM_PORCFG = tap_del << 24;
-
-		printf ("\nTAP Delay:%x Filling DRAM...", *(vu_long *)MPC5XXX_CDM_PORCFG);
-		for (t = 0; t < 0x04000000; t+=4)
-			*(vu_long *) t = t;
-		printf ("Checking DRAM...\n");
-		for (t = 0; t < 0x04000000; t+=4)
-		{
-			ulong	rval = *(vu_long *) t;
-			if (rval != t)
-			{
-				printf ("mismatch at %x: ", t);
-				printf (" 1.read %x", rval);
-				printf (" 2.read %x", *(vu_long *) t);
-				printf (" 3.read %x", *(vu_long *) t);
-				break;
-			}
-		}
-	}
-#endif
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
-
-	/* return total ram size */
-	return dramsize;
-}
-
-/*****************************************************************************
- * print board identification
- *****************************************************************************/
-int checkboard (void)
-{
-#if defined (CONFIG_EVAL5200)
-	puts ("Board: EMK TOP5200 on EVAL5200\n");
-#else
-#if defined (CONFIG_LITE5200)
-	puts ("Board: LITE5200\n");
-#else
-#if defined (CONFIG_MINI5200)
-	puts ("Board: EMK TOP5200 on MINI5200\n");
-#else
-	puts ("Board: EMK TOP5200\n");
-#endif
-#endif
-#endif
-	return 0;
-}
-
-/*****************************************************************************
- * prepare for FLASH detection
- *****************************************************************************/
-void flash_preinit(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-/*****************************************************************************
- * finalize FLASH setup
- *****************************************************************************/
-void flash_afterinit(uint bank, ulong start, ulong size)
-{
-	if (bank == 0) { /* adjust mapping */
-		*(vu_long *)MPC5XXX_BOOTCS_START =
-		*(vu_long *)MPC5XXX_CS0_START =	START_REG(start);
-		*(vu_long *)MPC5XXX_BOOTCS_STOP =
-		*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(start, size);
-	}
-}
-
-/*****************************************************************************
- * otherinits after RAM is there and we are relocated to RAM
- * note: though this is an int function, nobody cares for the result!
- *****************************************************************************/
-int misc_init_r (void)
-{
-#if !defined (CONFIG_LITE5200)
-	/* read 'factory' part of EEPROM */
-	extern void read_factory_r (void);
-	read_factory_r ();
-#endif
-	return (0);
-}
-
-/*****************************************************************************
- * initialize the PCI system
- *****************************************************************************/
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-/*****************************************************************************
- * provide the IDE Reset Function
- *****************************************************************************/
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
-	debug ("init_ide_reset\n");
-
-	/* Configure PSC1_4 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
-}
-
-void ide_set_reset (int idereset)
-{
-	debug ("ide_reset(%d)\n", idereset);
-
-	if (idereset) {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
-	} else {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
-	}
-}
-#endif
diff --git a/board/emk/top860/Kconfig b/board/emk/top860/Kconfig
deleted file mode 100644
index 7b5afdadfc3..00000000000
--- a/board/emk/top860/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_TOP860
-
-config SYS_BOARD
-	default "top860"
-
-config SYS_VENDOR
-	default "emk"
-
-config SYS_CONFIG_NAME
-	default "TOP860"
-
-endif
diff --git a/board/emk/top860/MAINTAINERS b/board/emk/top860/MAINTAINERS
deleted file mode 100644
index 3676acab9b7..00000000000
--- a/board/emk/top860/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TOP860 BOARD
-M:	Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-S:	Maintained
-F:	board/emk/top860/
-F:	include/configs/TOP860.h
-F:	configs/TOP860_defconfig
diff --git a/board/emk/top860/Makefile b/board/emk/top860/Makefile
deleted file mode 100644
index 0401639ce37..00000000000
--- a/board/emk/top860/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= top860.o ../common/flash.o ../common/vpd.o ../common/am79c874.o
diff --git a/board/emk/top860/top860.c b/board/emk/top860/top860.c
deleted file mode 100644
index 32c77f84e74..00000000000
--- a/board/emk/top860/top860.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * (C) Copyright 2003
- * EMK Elektronik GmbH <www.emk-elektronik.de>
- * Reinhard Meyer <r.meyer@emk-elektronik.de>
- *
- * Board specific routines for the TOP860
- *
- * - initialisation
- * - interface to VPD data (mac address, clock speeds)
- * - memory controller
- * - serial io initialisation
- * - ethernet io initialisation
- *
- * -----------------------------------------------------------------
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <commproc.h>
-#include <mpc8xx.h>
-#include <asm/io.h>
-
-/*****************************************************************************
- * UPM table for 60ns EDO RAM at 25 MHz bus/external clock
- *****************************************************************************/
-static const uint edo_60ns_25MHz_tbl[] = {
-
-/* single read   (offset 0x00 in upm ram) */
-    0x0ff3fc04,0x08f3fc04,0x00f3fc04,0x00f3fc00,
-    0x33f7fc07,0xfffffc05,0xfffffc05,0xfffffc05,
-/* burst read    (offset 0x08 in upm ram) */
-    0x0ff3fc04,0x08f3fc04,0x00f3fc0c,0x0ff3fc40,
-    0x0cf3fc04,0x03f3fc48,0x0cf3fc04,0x03f3fc48,
-    0x0cf3fc04,0x03f3fc00,0x3ff7fc07,0xfffffc05,
-    0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
-/* single write  (offset 0x18 in upm ram) */
-    0x0ffffc04,0x08fffc04,0x30fffc00,0xf1fffc07,
-    0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
-/* burst write   (offset 0x20 in upm ram) */
-    0x0ffffc04,0x08fffc00,0x00fffc04,0x03fffc4c,
-    0x00fffc00,0x07fffc4c,0x00fffc00,0x0ffffc4c,
-    0x00fffc00,0x3ffffc07,0xfffffc05,0xfffffc05,
-    0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
-/* refresh       (offset 0x30 in upm ram) */
-    0xc0fffc04,0x07fffc04,0x0ffffc04,0x0ffffc04,
-    0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
-    0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
-/* exception     (offset 0x3C in upm ram) */
-    0xfffffc07,0xfffffc03,0xfffffc05,0xfffffc05,
-};
-
-/*****************************************************************************
- * Print Board Identity
- *****************************************************************************/
-int checkboard (void)
-{
-	puts ("Board:"CONFIG_IDENT_STRING"\n");
-	return (0);
-}
-
-/*****************************************************************************
- * Initialize DRAM controller
- *****************************************************************************/
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	/*
-	 * Only initialize memory controller when running from FLASH.
-	 * When running from RAM, don't touch it.
-	 */
-	if ((ulong) initdram & 0xff000000) {
-		volatile uint *addr1, *addr2;
-		uint i;
-
-		upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl,
-			   sizeof (edo_60ns_25MHz_tbl) / sizeof (uint));
-		memctl->memc_mptpr = 0x0200;
-		memctl->memc_mamr = 0x0ca20330;
-		memctl->memc_or2 = -CONFIG_SYS_DRAM_MAX | OR_CSNT_SAM;
-		memctl->memc_br2 = CONFIG_SYS_DRAM_BASE | BR_MS_UPMA | BR_V;
-		/*
-		 * Do 8 read accesses to DRAM
-		 */
-		addr1 = (volatile uint *) 0;
-		addr2 = (volatile uint *) 0x00400000;
-		for (i = 0; i < 8; i++)
-			in_be32(addr1);
-
-		/*
-		 * Now check whether we got 4MB or 16MB populated
-		 */
-		addr1[0] = 0x12345678;
-		addr1[1] = 0x9abcdef0;
-		addr2[0] = 0xfeedc0de;
-		addr2[1] = 0x47110815;
-		if (addr1[0] == 0xfeedc0de && addr1[1] == 0x47110815) {
-			/* only 4MB populated */
-			memctl->memc_or2 = -(CONFIG_SYS_DRAM_MAX / 4) | OR_CSNT_SAM;
-		}
-	}
-
-	return -(memctl->memc_or2 & 0xffff0000);
-}
-
-/*****************************************************************************
- * prepare for FLASH detection
- *****************************************************************************/
-void flash_preinit(void)
-{
-}
-
-/*****************************************************************************
- * finalize FLASH setup
- *****************************************************************************/
-void flash_afterinit(uint bank, ulong start, ulong size)
-{
-}
-
-/*****************************************************************************
- * otherinits after RAM is there and we are relocated to RAM
- * note: though this is an int function, nobody cares for the result!
- *****************************************************************************/
-int misc_init_r (void)
-{
-	/* read 'factory' part of EEPROM */
-	extern void read_factory_r (void);
-	read_factory_r ();
-
-	return (0);
-}
diff --git a/board/emk/top860/u-boot.lds.debug b/board/emk/top860/u-boot.lds.debug
deleted file mode 100644
index eec132d38c8..00000000000
--- a/board/emk/top860/u-boot.lds.debug
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib/vsprintf.o	(.text)
-    lib/crc32.o		(.text)
-    arch/powerpc/lib/extable.o	(.text)
-
-    . = env_offset;
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/emk/top9000/Kconfig b/board/emk/top9000/Kconfig
deleted file mode 100644
index 2dbe0603b77..00000000000
--- a/board/emk/top9000/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-if TARGET_TOP9000
-
-config SYS_CPU
-	default "arm926ejs"
-
-config SYS_BOARD
-	default "top9000"
-
-config SYS_VENDOR
-	default "emk"
-
-config SYS_SOC
-	default "at91"
-
-config SYS_CONFIG_NAME
-	default "top9000"
-
-endif
diff --git a/board/emk/top9000/MAINTAINERS b/board/emk/top9000/MAINTAINERS
deleted file mode 100644
index 890359fcbd0..00000000000
--- a/board/emk/top9000/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-TOP9000 BOARD
-M:	Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-S:	Maintained
-F:	board/emk/top9000/
-F:	include/configs/top9000.h
-F:	configs/top9000eval_xe_defconfig
-F:	configs/top9000su_xe_defconfig
diff --git a/board/emk/top9000/Makefile b/board/emk/top9000/Makefile
deleted file mode 100644
index 8725a6cf0d6..00000000000
--- a/board/emk/top9000/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2010
-# Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= top9000.o
-obj-$(CONFIG_ATMEL_SPI)	+= spi.o
diff --git a/board/emk/top9000/spi.c b/board/emk/top9000/spi.c
deleted file mode 100644
index afcd00bd514..00000000000
--- a/board/emk/top9000/spi.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_spi.h>
-#include <asm/arch/gpio.h>
-#include <spi.h>
-
-static const struct {
-	u32	port;
-	u32	bit;
-} cs_to_portbit[2][4] = {
-	{{AT91_PIO_PORTA,  3}, {AT91_PIO_PORTC, 11},
-			{AT91_PIO_PORTC, 16}, {AT91_PIO_PORTC, 17} },
-	{{AT91_PIO_PORTB,  3}, {AT91_PIO_PORTC,  5},
-			{AT91_PIO_PORTC,  4}, {AT91_PIO_PORTC,  3} }
-};
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	debug("spi_cs_is_valid: bus=%u cs=%u\n", bus, cs);
-	if (bus < 2 && cs < 4)
-		return 1;
-	return 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	debug("spi_cs_activate: bus=%u cs=%u\n", slave->bus, slave->cs);
-	at91_set_pio_output(cs_to_portbit[slave->bus][slave->cs].port,
-		cs_to_portbit[slave->bus][slave->cs].bit, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	debug("spi_cs_deactivate: bus=%u cs=%u\n", slave->bus, slave->cs);
-	at91_set_pio_output(cs_to_portbit[slave->bus][slave->cs].port,
-		cs_to_portbit[slave->bus][slave->cs].bit, 1);
-}
diff --git a/board/emk/top9000/top9000.c b/board/emk/top9000/top9000.c
deleted file mode 100644
index 6e2ffddb0a4..00000000000
--- a/board/emk/top9000/top9000.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <mmc.h>
-#include <atmel_mci.h>
-#include <i2c.h>
-#include <spi.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91sam9260_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/at91_shdwn.h>
-#include <asm/arch/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_CMD_NAND
-static void nand_hw_init(void)
-{
-	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
-	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
-	unsigned long csa;
-
-	/* Assign CS3 to NAND/SmartMedia Interface */
-	csa = readl(&matrix->ebicsa);
-	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
-	writel(csa, &matrix->ebicsa);
-
-	/* Configure SMC CS3 for NAND/SmartMedia */
-	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
-		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
-		&smc->cs[3].setup);
-	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
-		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
-		&smc->cs[3].pulse);
-	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
-		&smc->cs[3].cycle);
-	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
-		AT91_SMC_MODE_EXNW_DISABLE |
-		AT91_SMC_MODE_DBW_8 |
-		AT91_SMC_MODE_TDF_CYCLE(2),
-		&smc->cs[3].mode);
-
-	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
-
-	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-}
-#endif
-
-#ifdef CONFIG_MACB
-static void macb_hw_init(void)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-	/* Enable EMAC clock */
-	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
-
-	/* Initialize EMAC=MACB hardware */
-	at91_macb_hw_init();
-}
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-	/* Enable MCI clock */
-	writel(1 << ATMEL_ID_MCI, &pmc->pcer);
-
-	/* Initialize MCI hardware */
-	at91_mci_hw_init();
-
-	/* This calls the atmel_mmc_init in gen_atmel_mci.c */
-	return atmel_mci_init((void *)ATMEL_BASE_MCI);
-}
-
-/* this is a weak define that we are overriding */
-int board_mmc_getcd(struct mmc *mmc)
-{
-	return !at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN);
-}
-
-#endif
-
-int board_early_init_f(void)
-{
-	struct at91_shdwn *shdwn = (struct at91_shdwn *)ATMEL_BASE_SHDWN;
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-	/*
-	 * make sure the board can be powered on by
-	 * any transition on WKUP
-	 */
-	writel(AT91_SHDW_MR_WKMODE0H2L | AT91_SHDW_MR_WKMODE0L2H,
-		&shdwn->mr);
-
-	/* Enable clocks for all PIOs */
-	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
-		(1 << ATMEL_ID_PIOC),
-		&pmc->pcer);
-
-	/* set SCL0 and SDA0 to open drain */
-	at91_set_pio_output(I2C0_PORT, SCL0_PIN, 1);
-	at91_set_pio_multi_drive(I2C0_PORT, SCL0_PIN, 1);
-	at91_set_pio_pullup(I2C0_PORT, SCL0_PIN, 1);
-	at91_set_pio_output(I2C0_PORT, SDA0_PIN, 1);
-	at91_set_pio_multi_drive(I2C0_PORT, SDA0_PIN, 1);
-	at91_set_pio_pullup(I2C0_PORT, SDA0_PIN, 1);
-
-	/* set SCL1 and SDA1 to open drain */
-	at91_set_pio_output(I2C1_PORT, SCL1_PIN, 1);
-	at91_set_pio_multi_drive(I2C1_PORT, SCL1_PIN, 1);
-	at91_set_pio_pullup(I2C1_PORT, SCL1_PIN, 1);
-	at91_set_pio_output(I2C1_PORT, SDA1_PIN, 1);
-	at91_set_pio_multi_drive(I2C1_PORT, SDA1_PIN, 1);
-	at91_set_pio_pullup(I2C1_PORT, SDA1_PIN, 1);
-	return 0;
-}
-
-int board_init(void)
-{
-	/* arch number of TOP9000 Board */
-	gd->bd->bi_arch_number = MACH_TYPE_TOP9000;
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	at91_seriald_hw_init();
-#ifdef CONFIG_CMD_NAND
-	nand_hw_init();
-#endif
-#ifdef CONFIG_MACB
-	macb_hw_init();
-#endif
-#ifdef CONFIG_ATMEL_SPI0
-	/* (n+4) denotes to use nSPISEL(0) in GPIO mode! */
-	at91_spi0_hw_init(1 << (FRAM_CS_NUM + 4));
-#endif
-#ifdef CONFIG_ATMEL_SPI1
-	at91_spi1_hw_init(1 << (ENC_CS_NUM + 4));
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
-	/* read 'factory' part of EEPROM */
-	read_factory_r();
-	return 0;
-}
-#endif
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size(
-		(void *)CONFIG_SYS_SDRAM_BASE,
-		CONFIG_SYS_SDRAM_SIZE);
-	return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-void reset_phy(void)
-{
-	/*
-	 * Initialize ethernet HW addresses prior to starting Linux,
-	 * needed for nfsroot.
-	 * TODO: We need to investigate if that is really necessary.
-	 */
-	eth_init(gd->bd);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-	int num = 0;
-#ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0,
-		(void *)ATMEL_BASE_EMAC0,
-		CONFIG_SYS_PHY_ID);
-	if (!rc)
-		num++;
-#endif
-#ifdef CONFIG_ENC28J60
-	rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM,
-		ENC_SPI_CLOCK, SPI_MODE_0);
-	if (!rc)
-		num++;
-# ifdef CONFIG_ENC28J60_2
-	rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM+1,
-		ENC_SPI_CLOCK, SPI_MODE_0);
-	if (!rc)
-		num++;
-#  ifdef CONFIG_ENC28J60_3
-	rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM+2,
-		ENC_SPI_CLOCK, SPI_MODE_0);
-	if (!rc)
-		num++;
-#  endif
-# endif
-#endif
-	return num;
-}
-
-/*
- * I2C access functions
- *
- * Note:
- * We need to access Bus 0 before relocation to access the
- * environment settings.
- * However i2c_get_bus_num() cannot be called before
- * relocation.
- */
-#ifdef CONFIG_SYS_I2C_SOFT
-void iic_init(void)
-{
-	/* ports are now initialized in board_early_init_f() */
-}
-
-int iic_read(void)
-{
-	switch (I2C_ADAP_HWNR) {
-	case 0:
-		return at91_get_pio_value(I2C0_PORT, SDA0_PIN);
-	case 1:
-		return at91_get_pio_value(I2C1_PORT, SDA1_PIN);
-	}
-	return 1;
-}
-
-void iic_sda(int bit)
-{
-	switch (I2C_ADAP_HWNR) {
-	case 0:
-		at91_set_pio_value(I2C0_PORT, SDA0_PIN, bit);
-		break;
-	case 1:
-		at91_set_pio_value(I2C1_PORT, SDA1_PIN, bit);
-		break;
-	}
-}
-
-void iic_scl(int bit)
-{
-	switch (I2C_ADAP_HWNR) {
-	case 0:
-		at91_set_pio_value(I2C0_PORT, SCL0_PIN, bit);
-		break;
-	case 1:
-		at91_set_pio_value(I2C1_PORT, SCL1_PIN, bit);
-		break;
-	}
-}
-
-#endif
diff --git a/board/esd/cpci750/64360.h b/board/esd/cpci750/64360.h
deleted file mode 100644
index 92133f0bafe..00000000000
--- a/board/esd/cpci750/64360.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- * for cpci750 Reinhard Arlt
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * main board support/init for the cpci750.
- */
-
-#ifndef __64360_H__
-#define __64360_H__
-
-/* CPU Configuration bits */
-#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
-#define	CPU_CONF_SINGLE_CPU	(1 << 11)
-#define	CPU_CONF_ENDIANESS	(1 << 12)
-#define CPU_CONF_PIPELINE	(1 << 13)
-#define CPU_CONF_STOP_RETRY	(1 << 17)
-#define CPU_CONF_MULTI_DECODE	(1 << 18)
-#define CPU_CONF_DP_VALID	(1 << 19)
-#define CPU_CONF_PERR_PROP	(1 << 22)
-#define CPU_CONF_AACK_DELAY_2	(1 << 25)
-#define CPU_CONF_AP_VALID	(1 << 26)
-#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
-
-/* CPU Master Control bits */
-#define CPU_MAST_CTL_ARB_EN	(1 << 8)
-#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
-#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
-#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
-#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
-#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
-
-#endif /* __64360_H__ */
diff --git a/board/esd/cpci750/Kconfig b/board/esd/cpci750/Kconfig
deleted file mode 100644
index 32d4ee60b70..00000000000
--- a/board/esd/cpci750/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_CPCI750
-
-config SYS_BOARD
-	default "cpci750"
-
-config SYS_VENDOR
-	default "esd"
-
-config SYS_CONFIG_NAME
-	default "CPCI750"
-
-endif
diff --git a/board/esd/cpci750/MAINTAINERS b/board/esd/cpci750/MAINTAINERS
deleted file mode 100644
index 4a46457e520..00000000000
--- a/board/esd/cpci750/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CPCI750 BOARD
-M:	Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S:	Maintained
-F:	board/esd/cpci750/
-F:	include/configs/CPCI750.h
-F:	configs/CPCI750_defconfig
diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile
deleted file mode 100644
index a3300c9f4ac..00000000000
--- a/board/esd/cpci750/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2001
-# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= misc.o
-obj-y	+= cpci750.o serial.o ../../Marvell/common/memory.o pci.o \
-	  mv_eth.o  mpsc.o i2c.o \
-	  sdram_init.o ide.o
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
deleted file mode 100644
index fcaf3e67c75..00000000000
--- a/board/esd/cpci750/cpci750.c
+++ /dev/null
@@ -1,1088 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
- * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
- */
-
-/*
- * cpci750.c - main board support/init for the esd cpci750.
- */
-
-#include <common.h>
-#include <command.h>
-#include <74xx_7xx.h>
-#include "../../Marvell/include/memory.h"
-#include "../../Marvell/include/pci.h"
-#include "../../Marvell/include/mv_gen_reg.h"
-#include <net.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "i2c.h"
-#include "64360.h"
-#include "mv_regs.h"
-
-#undef	DEBUG
-/*#define	DEBUG */
-
-#ifdef CONFIG_PCI
-#define	MAP_PCI
-#endif /* of CONFIG_PCI */
-
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-static char show_config_tab[][15] = {{"PCI0DLL_2     "},  /* 31 */
-				     {"PCI0DLL_1     "},  /* 30 */
-				     {"PCI0DLL_0     "},  /* 29 */
-				     {"PCI1DLL_2     "},  /* 28 */
-				     {"PCI1DLL_1     "},  /* 27 */
-				     {"PCI1DLL_0     "},  /* 26 */
-				     {"BbEP2En       "},  /* 25 */
-				     {"SDRAMRdDataDel"},  /* 24 */
-				     {"SDRAMRdDel    "},  /* 23 */
-				     {"SDRAMSync     "},  /* 22 */
-				     {"SDRAMPipeSel_1"},  /* 21 */
-				     {"SDRAMPipeSel_0"},  /* 20 */
-				     {"SDRAMAddDel   "},  /* 19 */
-				     {"SDRAMClkSel   "},  /* 18 */
-				     {"Reserved(1!)  "},  /* 17 */
-				     {"PCIRty        "},  /* 16 */
-				     {"BootCSWidth_1 "},  /* 15 */
-				     {"BootCSWidth_0 "},  /* 14 */
-				     {"PCI1PadsCal   "},  /* 13 */
-				     {"PCI0PadsCal   "},  /* 12 */
-				     {"MultiMVId_1   "},  /* 11 */
-				     {"MultiMVId_0   "},  /* 10 */
-				     {"MultiGTEn     "},  /* 09 */
-				     {"Int60xArb     "},  /* 08 */
-				     {"CPUBusConfig_1"},  /* 07 */
-				     {"CPUBusConfig_0"},  /* 06 */
-				     {"DefIntSpc     "},  /* 05 */
-				     {0               },  /* 04 */
-				     {"SROMAdd_1     "},  /* 03 */
-				     {"SROMAdd_0     "},  /* 02 */
-				     {"DRAMPadCal    "},  /* 01 */
-				     {"SInitEn       "},  /* 00 */
-				     {0               },  /* 31 */
-				     {0               },  /* 30 */
-				     {0               },  /* 29 */
-				     {0               },  /* 28 */
-				     {0               },  /* 27 */
-				     {0               },  /* 26 */
-				     {0               },  /* 25 */
-				     {0               },  /* 24 */
-				     {0               },  /* 23 */
-				     {0               },  /* 22 */
-				     {"JTAGCalBy     "},  /* 21 */
-				     {"GB2Sel        "},  /* 20 */
-				     {"GB1Sel        "},  /* 19 */
-				     {"DRAMPLL_MDiv_5"},  /* 18 */
-				     {"DRAMPLL_MDiv_4"},  /* 17 */
-				     {"DRAMPLL_MDiv_3"},  /* 16 */
-				     {"DRAMPLL_MDiv_2"},  /* 15 */
-				     {"DRAMPLL_MDiv_1"},  /* 14 */
-				     {"DRAMPLL_MDiv_0"},  /* 13 */
-				     {"GB0Sel        "},  /* 12 */
-				     {"DRAMPLLPU     "},  /* 11 */
-				     {"DRAMPLL_HIKVCO"},  /* 10 */
-				     {"DRAMPLLNP     "},  /* 09 */
-				     {"DRAMPLL_NDiv_7"},  /* 08 */
-				     {"DRAMPLL_NDiv_6"},  /* 07 */
-				     {"CPUPadCal     "},  /* 06 */
-				     {"DRAMPLL_NDiv_5"},  /* 05 */
-				     {"DRAMPLL_NDiv_4"},  /* 04 */
-				     {"DRAMPLL_NDiv_3"},  /* 03 */
-				     {"DRAMPLL_NDiv_2"},  /* 02 */
-				     {"DRAMPLL_NDiv_1"},  /* 01 */
-				     {"DRAMPLL_NDiv_0"}}; /* 00 */
-
-extern flash_info_t flash_info[];
-
-extern int do_bootvx (cmd_tbl_t *, int, int, char *[]);
-
-/* ------------------------------------------------------------------------- */
-
-/* this is the current GT register space location */
-/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
-
-/* Unfortunately, we cant change it while we are in flash, so we initialize it
- * to the "final" value. This means that any debug_led calls before
- * board_early_init_f wont work right (like in cpu_init_f).
- * See also my_remap_gt_regs below. (NTL)
- */
-
-void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
-int display_mem_map (void);
-
-/*
- * Skip video initialization on slave variant.
- * This function will overwrite the weak default in cfb_console.c
- */
-int board_video_skip(void)
-{
-	return CPCI750_SLAVE_TEST;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * This is a version of the GT register space remapping function that
- * doesn't touch globals (meaning, it's ok to run from flash.)
- *
- * Unfortunately, this has the side effect that a writable
- * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
- */
-
-void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
-{
-	u32 temp;
-
-	/* check and see if it's already moved */
-
-/* original ppcboot 1.1.6 source
-
-	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 20)
-		return;
-
-	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 20);
-
-	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
-original ppcboot 1.1.6 source end */
-
-	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 16)
-		return;
-
-	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 16);
-
-	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
-}
-
-#ifdef CONFIG_PCI
-
-static void gt_pci_config (void)
-{
-	unsigned int stat;
-	unsigned int data;
-	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
-
-	/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
-	 * config registers by writing ones to the bus and device.
-	 * We then update the Virtual register with the correct value for the bus and device.
-	 */
-	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
-		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
-
-		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
-
-		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
-		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
-
-	}
-	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
-		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
-		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
-
-		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
-		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
-	}
-
-	/* Enable master */
-	PCI_MASTER_ENABLE (0, SELF);
-	PCI_MASTER_ENABLE (1, SELF);
-
-	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
-	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
-	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
-									     <<
-									     18);
-	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
-	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
-
-	/* ronen- add write to pci remap registers for 64460.
-	   in 64360 when writing to pci base go and overide remap automaticaly,
-	   in 64460 it doesn't */
-	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
-	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
-	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
-	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
-	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
-
-	/* PCI interface settings */
-	/* Timeout set to retry forever */
-	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
-	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
-
-	/* ronen - enable only CS0 and Internal reg!! */
-	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-
-/*ronen update the pci internal registers base address.*/
-#ifdef MAP_PCI
-	for (stat = 0; stat <= PCI_HOST1; stat++) {
-		data = pciReadConfigReg(stat,
-					PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
-					SELF);
-		data = (data & 0x0f) | CONFIG_SYS_GT_REGS;
-		pciWriteConfigReg (stat,
-				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
-				   SELF, data);
-	}
-#endif
-
-}
-#endif
-
-/* Setup CPU interface paramaters */
-static void gt_cpu_config (void)
-{
-	cpu_t cpu = get_cpu_type ();
-	ulong tmp;
-
-	/* cpu configuration register */
-	tmp = GTREGREAD (CPU_CONFIGURATION);
-
-	/* set the SINGLE_CPU bit  see MV64360 P.399 */
-#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
-	tmp |= CPU_CONF_SINGLE_CPU;
-#endif
-
-	tmp &= ~CPU_CONF_AACK_DELAY_2;
-
-	tmp |= CPU_CONF_DP_VALID;
-	tmp |= CPU_CONF_AP_VALID;
-
-	tmp |= CPU_CONF_PIPELINE;
-
-	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
-
-	/* CPU master control register */
-	tmp = GTREGREAD (CPU_MASTER_CONTROL);
-
-	tmp |= CPU_MAST_CTL_ARB_EN;
-
-	if ((cpu == CPU_7400) ||
-	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
-
-		tmp |= CPU_MAST_CTL_CLEAN_BLK;
-		tmp |= CPU_MAST_CTL_FLUSH_BLK;
-
-	} else {
-		/* cleanblock must be cleared for CPUs
-		 * that do not support this command (603e, 750)
-		 * see Res#1 */
-		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
-		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
-	}
-	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
-}
-
-/*
- * board_early_init_f.
- *
- * set up gal. device mappings, etc.
- */
-int board_early_init_f (void)
-{
-
-	/*
-	 * set up the GT the way the kernel wants it
-	 * the call to move the GT register space will obviously
-	 * fail if it has already been done, but we're going to assume
-	 * that if it's not at the power-on location, it's where we put
-	 * it last time. (huber)
-	 */
-
-	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
-
-	/* No PCI in first release of Port To_do: enable it. */
-#ifdef CONFIG_PCI
-	gt_pci_config ();
-#endif
-	/* mask all external interrupt sources */
-	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
-	/* new in MV6436x */
-	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
-	/* --------------------- */
-	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
-	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
-	/* does not exist in MV6436x
-	   GT_REG_WRITE(CPU_INT_0_MASK, 0);
-	   GT_REG_WRITE(CPU_INT_1_MASK, 0);
-	   GT_REG_WRITE(CPU_INT_2_MASK, 0);
-	   GT_REG_WRITE(CPU_INT_3_MASK, 0);
-	   --------------------- */
-
-
-	/* ----- DEVICE BUS SETTINGS ------ */
-
-	/*
-	 * EVB
-	 * 0 - SRAM   ????
-	 * 1 - RTC      ????
-	 * 2 - UART     ????
-	 * 3 - Flash    checked 32Bit Intel Strata
-	 * boot - BootCS checked 8Bit 29LV040B
-	 *
-	 */
-
-	/*
-	 * the dual 7450 module requires burst access to the boot
-	 * device, so the serial rom copies the boot device to the
-	 * on-board sram on the eval board, and updates the correct
-	 * registers to boot from the sram. (device0)
-	 */
-
-	memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
-	memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
-	memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
-	memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
-
-
-	/* configure device timing */
-	GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
-	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
-	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
-	GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_DEV3_PAR);
-
-#ifdef CONFIG_SYS_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
-	/* detect if we are booting from the 32 bit flash */
-	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
-		/* 32 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
-			      CONFIG_SYS_32BIT_BOOT_PAR);
-	} else {
-		/* 8 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
-	}
-#else
-	/* 8 bit boot flash only */
-/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
-#endif
-
-
-	gt_cpu_config ();
-
-	/* MPP setup */
-	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
-	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
-	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
-	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
-
-	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
-	DEBUG_LED0_ON ();
-	DEBUG_LED1_ON ();
-	DEBUG_LED2_ON ();
-
-	return 0;
-}
-
-/* various things to do after relocation */
-
-int misc_init_r ()
-{
-	icache_enable ();
-#ifdef CONFIG_SYS_L2
-	l2cache_enable ();
-#endif
-#ifdef CONFIG_MPSC
-
-	mpsc_sdma_init ();
-	mpsc_init2 ();
-#endif
-
-#if 0
-	/* disable the dcache and MMU */
-	dcache_lock ();
-#endif
-	if (flash_info[3].size < CONFIG_SYS_FLASH_INCREMENT) {
-		unsigned int flash_offset;
-		unsigned int l;
-
-		flash_offset =  CONFIG_SYS_FLASH_INCREMENT - flash_info[3].size;
-		for (l = 0; l < CONFIG_SYS_MAX_FLASH_SECT; l++) {
-			if (flash_info[3].start[l] != 0) {
-			      flash_info[3].start[l] += flash_offset;
-			}
-		}
-		flash_protect (FLAG_PROTECT_SET,
-			       CONFIG_SYS_MONITOR_BASE,
-			       CONFIG_SYS_MONITOR_BASE + monitor_flash_len  - 1,
-			       &flash_info[3]);
-	}
-	return 0;
-}
-
-void after_reloc (ulong dest_addr, gd_t * gd)
-{
-	memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE,
-			      CONFIG_SYS_BOOT_SIZE);
-
-	display_mem_map ();
-	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-
-	/* now, jump to the main ppcboot board init code */
-	board_init_r (gd, dest_addr);
-	/* NOTREACHED */
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- *
- * right now, assume borad type. (there is just one...after all)
- */
-
-int checkboard (void)
-{
-	int l_type = 0;
-
-	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
-	return (l_type);
-}
-
-/* utility functions */
-void debug_led (int led, int mode)
-{
-}
-
-int display_mem_map (void)
-{
-	int i, j;
-	unsigned int base, size, width;
-
-	/* SDRAM */
-	printf ("SD (DDR) RAM\n");
-	for (i = 0; i <= BANK3; i++) {
-		base = memoryGetBankBaseAddress (i);
-		size = memoryGetBankSize (i);
-		if (size != 0) {
-			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
-				i, base, size >> 20);
-		}
-	}
-#ifdef CONFIG_PCI
-	/* CPU's PCI windows */
-	for (i = 0; i <= PCI_HOST1; i++) {
-		printf ("\nCPU's PCI %d windows\n", i);
-		base = pciGetSpaceBase (i, PCI_IO);
-		size = pciGetSpaceSize (i, PCI_IO);
-		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
-			size >> 20);
-		for (j = 0;
-		     j <=
-		     PCI_REGION0
-		     /*ronen currently only first PCI MEM is used 3 */ ;
-		     j++) {
-			base = pciGetSpaceBase (i, j);
-			size = pciGetSpaceSize (i, j);
-			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
-		}
-	}
-#endif /* of CONFIG_PCI */
-	/* Devices */
-	printf ("\nDEVICES\n");
-	for (i = 0; i <= DEVICE3; i++) {
-		base = memoryGetDeviceBaseAddress (i);
-		size = memoryGetDeviceSize (i);
-		width = memoryGetDeviceWidth (i) * 8;
-		printf ("DEV %d:  base - 0x%08x  size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
-		if (i == 0)
-			printf ("\t- FLASH\n");
-		else if (i == 1)
-			printf ("\t- FLASH\n");
-		else if (i == 2)
-			printf ("\t- FLASH\n");
-		else
-			printf ("\t- RTC/REGS/CAN\n");
-	}
-
-	/* Bootrom */
-	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
-	size = memoryGetDeviceSize (BOOT_DEVICE);
-	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
-	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\t- FLASH\n",
-		base, size >> 20, width);
-	return (0);
-}
-
-/*
- * Command loadpci: wait for signal from host and boot image.
- */
-int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	volatile unsigned int *ptr;
-	int count = 0;
-	int count2 = 0;
-	int status = 0;
-	char addr[16];
-	char str[] = "\\|/-";
-	char *local_args[2];
-
-	/*
-	 * Mark sync address
-	 */
-	ptr = 0;
-	ptr[0] = 0xffffffff;
-	ptr[1] = 0xffffffff;
-	puts("\nWaiting for image from pci host -");
-
-	/*
-	 * Wait for host to write the start address
-	 */
-	while (*ptr == 0xffffffff) {
-		count++;
-		if (!(count % 100)) {
-			count2++;
-			putc(0x08); /* backspace */
-			putc(str[count2 % 4]);
-		}
-
-		/* Abort if ctrl-c was pressed */
-		if (ctrlc()) {
-			puts("\nAbort\n");
-			return 0;
-		}
-
-		udelay(1000);
-	}
-
-	sprintf(addr, "%08x", *ptr);
-	printf("\nBooting Image at addr 0x%s ...\n", addr);
-	setenv("loadaddr", addr);
-
-	switch (ptr[1] == 0) {
-	case 0:
-		/*
-		 * Boot image via bootm
-		 */
-		local_args[0] = argv[0];
-		local_args[1] = NULL;
-		status = do_bootm (cmdtp, 0, 1, local_args);
-		break;
-	case 1:
-		/*
-		 * Boot image via bootvx
-		 */
-		local_args[0] = argv[0];
-		local_args[1] = NULL;
-		status = do_bootvx (cmdtp, 0, 1, local_args);
-		break;
-	}
-
-	return status;
-}
-
-U_BOOT_CMD(
-	loadpci,	1,	1,	do_loadpci,
-	"loadpci - Wait for pci-image and boot it\n",
-	NULL
-	);
-
-/* DRAM check routines copied from gw8260 */
-
-#if defined (CONFIG_SYS_DRAM_TEST)
-
-/*********************************************************************/
-/* NAME:  move64() -  moves a double word (64-bit)		     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   this function performs a double word move from the data at	     */
-/*   the source pointer to the location at the destination pointer.  */
-/*								     */
-/* INPUTS:							     */
-/*   unsigned long long *src  - pointer to data to move		     */
-/*								     */
-/* OUTPUTS:							     */
-/*   unsigned long long *dest - pointer to locate to move data	     */
-/*								     */
-/* RETURNS:							     */
-/*   None							     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*   May cloober fr0.						     */
-/*								     */
-/*********************************************************************/
-static void move64 (unsigned long long *src, unsigned long long *dest)
-{
-	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
-	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
-      : : : "fr0");		/* Clobbers fr0		*/
-	return;
-}
-
-
-#if defined (CONFIG_SYS_DRAM_TEST_DATA)
-
-unsigned long long pattern[] = {
-	0xaaaaaaaaaaaaaaaaLL,
-	0xccccccccccccccccLL,
-	0xf0f0f0f0f0f0f0f0LL,
-	0xff00ff00ff00ff00LL,
-	0xffff0000ffff0000LL,
-	0xffffffff00000000LL,
-	0x00000000ffffffffLL,
-	0x0000ffff0000ffffLL,
-	0x00ff00ff00ff00ffLL,
-	0x0f0f0f0f0f0f0f0fLL,
-	0x3333333333333333LL,
-	0x5555555555555555LL,
-};
-
-/*********************************************************************/
-/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Tests data lines for shorts and opens by forcing adjacent data  */
-/*   to opposite states. Because the data lines could be routed in   */
-/*   an arbitrary manner the must ensure test patterns ensure that   */
-/*   every case is tested. By using the following series of binary   */
-/*   patterns every combination of adjacent bits is test regardless  */
-/*   of routing.						     */
-/*								     */
-/*     ...101010101010101010101010				     */
-/*     ...110011001100110011001100				     */
-/*     ...111100001111000011110000				     */
-/*     ...111111110000000011111111				     */
-/*								     */
-/*   Carrying this out, gives us six hex patterns as follows:	     */
-/*								     */
-/*     0xaaaaaaaaaaaaaaaa					     */
-/*     0xcccccccccccccccc					     */
-/*     0xf0f0f0f0f0f0f0f0					     */
-/*     0xff00ff00ff00ff00					     */
-/*     0xffff0000ffff0000					     */
-/*     0xffffffff00000000					     */
-/*								     */
-/*   The number test patterns will always be given by:		     */
-/*								     */
-/*   log(base 2)(number data bits) = log2 (64) = 6		     */
-/*								     */
-/*   To test for short and opens to other signals on our boards. we  */
-/*   simply							     */
-/*   test with the 1's complemnt of the paterns as well.	     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern				     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*  Assumes only one one SDRAM bank				     */
-/*								     */
-/*********************************************************************/
-int mem_test_data (void)
-{
-	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
-	unsigned long long temp64 = 0;
-	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
-	int i;
-	unsigned int hi, lo;
-
-	for (i = 0; i < num_patterns; i++) {
-		move64 (&(pattern[i]), pmem);
-		move64 (pmem, &temp64);
-
-		/* hi = (temp64>>32) & 0xffffffff;		*/
-		/* lo = temp64 & 0xffffffff;			*/
-		/* printf("\ntemp64 = 0x%08x%08x", hi, lo);	*/
-
-		hi = (pattern[i] >> 32) & 0xffffffff;
-		lo = pattern[i] & 0xffffffff;
-		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
-
-		if (temp64 != pattern[i]) {
-			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
-				hi, lo);
-			return 1;
-		}
-	}
-
-	return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_DATA */
-
-#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
-/*********************************************************************/
-/* NAME:  mem_test_address() -	test address lines		     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   This function performs a test to verify that each word im	     */
-/*   memory is uniquly addressable. The test sequence is as follows: */
-/*								     */
-/*   1) write the address of each word to each word.		     */
-/*   2) verify that each location equals its address		     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern and address			     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_test_address (void)
-{
-	volatile unsigned int *pmem =
-		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
-	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
-	unsigned int i;
-
-	/* write address to each location */
-	for (i = 0; i < size; i++) {
-		pmem[i] = i;
-	}
-
-	/* verify each loaction */
-	for (i = 0; i < size; i++) {
-		if (pmem[i] != i) {
-			printf ("\n   Address Test Failed at 0x%x", i);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
-
-#if defined (CONFIG_SYS_DRAM_TEST_WALK)
-/*********************************************************************/
-/* NAME:   mem_march() -  memory march				     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Marches up through memory. At each location verifies rmask if   */
-/*   read = 1. At each location write wmask if	write = 1. Displays  */
-/*   failing address and pattern.				     */
-/*								     */
-/* INPUTS:							     */
-/*   volatile unsigned long long * base - start address of test	     */
-/*   unsigned int size - number of dwords(64-bit) to test	     */
-/*   unsigned long long rmask - read verify mask		     */
-/*   unsigned long long wmask - wrtie verify mask		     */
-/*   short read - verifies rmask if read = 1			     */
-/*   short write  - writes wmask if write = 1			     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern and address			     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_march (volatile unsigned long long *base,
-	       unsigned int size,
-	       unsigned long long rmask,
-	       unsigned long long wmask, short read, short write)
-{
-	unsigned int i;
-	unsigned long long temp = 0;
-	unsigned int hitemp, lotemp, himask, lomask;
-
-	for (i = 0; i < size; i++) {
-		if (read != 0) {
-			/* temp = base[i]; */
-			move64 ((unsigned long long *) &(base[i]), &temp);
-			if (rmask != temp) {
-				hitemp = (temp >> 32) & 0xffffffff;
-				lotemp = temp & 0xffffffff;
-				himask = (rmask >> 32) & 0xffffffff;
-				lomask = rmask & 0xffffffff;
-
-				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
-				return 1;
-			}
-		}
-		if (write != 0) {
-			/*  base[i] = wmask; */
-			move64 (&wmask, (unsigned long long *) &(base[i]));
-		}
-	}
-	return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_WALK */
-
-/*********************************************************************/
-/* NAME:   mem_test_walk() -  a simple walking ones test	     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Performs a walking ones through entire physical memory. The     */
-/*   test uses as series of memory marches, mem_march(), to verify   */
-/*   and write the test patterns to memory. The test sequence is as  */
-/*   follows:							     */
-/*     1) march writing 0000...0001				     */
-/*     2) march verifying 0000...0001  , writing  0000...0010	     */
-/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
-/*	   the write mask equals 1000...0000			     */
-/*     4) march verifying 1000...0000				     */
-/*   The test fails if any of the memory marches return a failure.   */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays which pass on the memory test is executing	     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_test_walk (void)
-{
-	unsigned long long mask;
-	volatile unsigned long long *pmem =
-		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
-	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
-
-	unsigned int i;
-
-	mask = 0x01;
-
-	printf ("Initial Pass");
-	mem_march (pmem, size, 0x0, 0x1, 0, 1);
-
-	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-	printf ("		");
-	printf ("         ");
-	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-
-	for (i = 0; i < 63; i++) {
-		printf ("Pass %2d", i + 2);
-		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
-			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
-			return 1;
-		}
-		mask = mask << 1;
-		printf ("\b\b\b\b\b\b\b");
-	}
-
-	printf ("Last Pass");
-	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
-		/* printf("mask: 0x%x", mask); */
-		return 1;
-	}
-	printf ("\b\b\b\b\b\b\b\b\b");
-	printf ("	     ");
-	printf ("\b\b\b\b\b\b\b\b\b");
-
-	return 0;
-}
-
-/*********************************************************************/
-/* NAME:    testdram() -  calls any enabled memory tests	     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Runs memory tests if the environment test variables are set to  */
-/*   'y'.							     */
-/*								     */
-/* INPUTS:							     */
-/*   testdramdata    - If set to 'y', data test is run.		     */
-/*   testdramaddress - If set to 'y', address test is run.	     */
-/*   testdramwalk    - If set to 'y', walking ones test is run	     */
-/*								     */
-/* OUTPUTS:							     */
-/*   None							     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int testdram (void)
-{
-	int rundata    = 0;
-	int runaddress = 0;
-	int runwalk    = 0;
-
-#ifdef CONFIG_SYS_DRAM_TEST_DATA
-	rundata = getenv_yesno("testdramdata") == 1;
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
-	runaddress = getenv_yesno("testdramaddress") == 1;
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_WALK
-	runwalk = getenv_yesno("testdramwalk") == 1;
-#endif
-
-	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
-	}
-#ifdef CONFIG_SYS_DRAM_TEST_DATA
-	if (rundata == 1) {
-		printf ("Test DATA ...  ");
-		if (mem_test_data () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
-	if (runaddress == 1) {
-		printf ("Test ADDRESS ...  ");
-		if (mem_test_address () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_WALK
-	if (runwalk == 1) {
-		printf ("Test WALKING ONEs ...  ");
-		if (mem_test_walk () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("passed\n");
-	}
-	return 0;
-
-}
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-/* ronen - the below functions are used by the bootm function		*/
-/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
-/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
-/*    the kernel data areas.						*/
-/*  - we diable and invalidate the icache and dcache.			*/
-void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
-{
-	u32 temp;
-
-	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 16)
-		return;
-
-	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 16);
-
-	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
-							new_loc |
-							(INTERNAL_SPACE_DECODE)))))
-	       != temp);
-
-}
-
-void board_prebootm_init ()
-{
-
-/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
-		GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
-
-/* Stop GigE Rx DMA engines */
-	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
-/*	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */
-/*      GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */
-
-/* Relocate MV64360 internal regs */
-	my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, CONFIG_SYS_DFL_GT_REGS);
-
-	icache_disable ();
-	dcache_disable ();
-}
-
-int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	unsigned int reset_sample_low;
-	unsigned int reset_sample_high;
-	unsigned int l, l1, l2;
-
-	GT_REG_READ(0x3c4, &reset_sample_low);
-	GT_REG_READ(0x3d4, &reset_sample_high);
-	printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
-
-	l2 = 0;
-	for (l=0; l<63; l++) {
-		if (show_config_tab[l][0] != 0) {
-			printf("%14s:%1x ", show_config_tab[l],
-			       ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01);
-			l2++;
-			if ((l2 % 4) == 0)
-				printf("\n");
-		} else {
-			l1++;
-		}
-		if (l == 32)
-			reset_sample_low = reset_sample_high;
-	}
-	printf("\n");
-
-	return(0);
-}
-
-U_BOOT_CMD(
-	show_config,	1,	1,	do_show_config,
-	"Show Marvell strapping register",
-	"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)"
-);
-
-int do_pldver(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	printf("PLD version:0x%02x\n", in_8((void *)CONFIG_SYS_PLD_VER));
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	pldver, 1, 1, do_pldver,
-	"Show PLD version",
-	"Show PLD version)");
-
-int board_eth_init(bd_t *bis)
-{
-	return mv6436x_eth_initialize(bis);
-}
diff --git a/board/esd/cpci750/eth.h b/board/esd/cpci750/eth.h
deleted file mode 100644
index 4e427683b41..00000000000
--- a/board/esd/cpci750/eth.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __EVB64360_ETH_H__
-#define __EVB64360_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-
-
-int db64360_eth0_poll(void);
-int db64360_eth0_transmit(unsigned int s, volatile char *p);
-void db64360_eth0_disable(void);
-bool network_start(bd_t *bis);
-
-int mv6436x_eth_initialize(bd_t *);
-
-#endif /* __EVB64360_ETH_H__ */
diff --git a/board/esd/cpci750/i2c.c b/board/esd/cpci750/i2c.c
deleted file mode 100644
index bad0dac05d4..00000000000
--- a/board/esd/cpci750/i2c.c
+++ /dev/null
@@ -1,475 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
- * extra improvments by Brain Waite
- * for cpci750 by reinhard.arlt@esd-electronics.com
- */
-#include <common.h>
-#include <mpc8xx.h>
-#include <malloc.h>
-#include <i2c.h>
-#include "../../Marvell/include/mv_gen_reg.h"
-#include "../../Marvell/include/core.h"
-
-#define I2C_DELAY	    100
-#undef	DEBUG_I2C
-
-#ifdef DEBUG_I2C
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-/* Assuming that there is only one master on the bus (us) */
-
-void i2c_init (int speed, int slaveaddr)
-{
-	unsigned int n, m, freq, margin, power;
-	unsigned int actualN = 0, actualM = 0;
-	unsigned int minMargin = 0xffffffff;
-	unsigned int tclk = CONFIG_SYS_TCLK;
-	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
-
-	DP (puts ("i2c_init\n"));
-/* gtI2cMasterInit */
-	for (n = 0; n < 8; n++) {
-		for (m = 0; m < 16; m++) {
-			power = 2 << n;	/* power = 2^(n+1) */
-			freq = tclk / (10 * (m + 1) * power);
-			if (i2cFreq > freq)
-				margin = i2cFreq - freq;
-			else
-				margin = freq - i2cFreq;
-			if (margin < minMargin) {
-				minMargin = margin;
-				actualN = n;
-				actualM = m;
-			}
-		}
-	}
-
-	DP (puts ("setup i2c bus\n"));
-
-	/* Setup bus */
-	/* gtI2cReset */
-	GT_REG_WRITE (I2C_SOFT_RESET, 0);
-	asm(" sync");
-	GT_REG_WRITE (I2C_CONTROL, 0);
-	asm(" sync");
-
-	DP (puts ("set baudrate\n"));
-
-	GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
-	asm(" sync");
-
-	DP (puts ("udelay...\n"));
-
-	udelay (I2C_DELAY);
-
-	GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
-	asm(" sync");
-}
-
-
-static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
-{
-	unsigned int status, data, bits = 7;
-	unsigned int control;
-	int count = 0;
-
-	DP (puts ("i2c_select_device\n"));
-
-	/* Output slave address */
-
-	if (ten_bit) {
-		bits = 10;
-	}
-
-	GT_REG_READ (I2C_CONTROL, &control);
-	control |=  (0x1 << 2);
-	GT_REG_WRITE (I2C_CONTROL, control);
-	asm(" sync");
-
-	GT_REG_READ (I2C_CONTROL, &control);
-	control |= (0x1 << 5);	/* generate the I2C_START_BIT */
-	GT_REG_WRITE (I2C_CONTROL, control);
-	asm(" sync");
-	RESET_REG_BITS (I2C_CONTROL, (0x01 << 3));
-	asm(" sync");
-
-	GT_REG_READ (I2C_CONTROL, &status);
-	while ((status & 0x08) != 0x08) {
-		GT_REG_READ (I2C_CONTROL, &status);
-		}
-
-
-	count = 0;
-
-	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-	while (((status & 0xff) != 0x08) && ((status & 0xff) != 0x10)){
-		if (count > 200) {
-#ifdef DEBUG_I2C
-			printf ("Failed to set startbit: 0x%02x\n", status);
-#endif
-			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-			asm(" sync");
-			return (status);
-		}
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-	}
-
-	DP (puts ("i2c_select_device:write addr byte\n"));
-
-	/* assert the address */
-
-	data = (dev_addr << 1);
-	/* set the read bit */
-	data |= read;
-	GT_REG_WRITE (I2C_DATA, data);
-	asm(" sync");
-	RESET_REG_BITS (I2C_CONTROL, BIT3);
-	asm(" sync");
-
-	GT_REG_READ (I2C_CONTROL, &status);
-	while ((status & 0x08) != 0x08) {
-		GT_REG_READ (I2C_CONTROL, &status);
-		}
-
-	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-	count = 0;
-	while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
-		if (count > 200) {
-#ifdef DEBUG_I2C
-			printf ("Failed to write address: 0x%02x\n", status);
-#endif
-			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-			return (status);
-		}
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		asm(" sync");
-		count++;
-	}
-
-	if (bits == 10) {
-		printf ("10 bit I2C addressing not yet implemented\n");
-		return (0xff);
-	}
-
-	return (0);
-}
-
-static uchar i2c_get_data (uchar * return_data, int len)
-{
-
-	unsigned int data, status;
-	int count = 0;
-
-	DP (puts ("i2c_get_data\n"));
-
-	while (len) {
-
-		RESET_REG_BITS (I2C_CONTROL, BIT3);
-		asm(" sync");
-
-		/* Get and return the data */
-
-		GT_REG_READ (I2C_CONTROL, &status);
-		while ((status & 0x08) != 0x08) {
-			GT_REG_READ (I2C_CONTROL, &status);
-			}
-
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-		while ((status & 0xff) != 0x50) {
-			if (count > 20) {
-#ifdef DEBUG_I2C
-				printf ("Failed to get data len status: 0x%02x\n", status);
-#endif
-				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-				asm(" sync");
-				return 0;
-			}
-			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-			count++;
-		}
-		GT_REG_READ (I2C_DATA, &data);
-		len--;
-		*return_data = (uchar) data;
-		return_data++;
-
-	}
-	RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
-	asm(" sync");
-	count = 0;
-
-	GT_REG_READ (I2C_CONTROL, &status);
-	while ((status & 0x08) != 0x08) {
-		GT_REG_READ (I2C_CONTROL, &status);
-		}
-
-	while ((status & 0xff) != 0x58) {
-		if (count > 2000) {
-			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-			return (status);
-		}
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-	}
-	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/* stop */
-	asm(" sync");
-	RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
-	asm(" sync");
-
-	return (0);
-}
-
-
-static uchar i2c_write_data (unsigned int *data, int len)
-{
-	unsigned int status;
-	int count;
-	unsigned int temp;
-	unsigned int *temp_ptr = data;
-
-	DP (puts ("i2c_write_data\n"));
-
-	while (len) {
-		count = 0;
-		temp = (unsigned int) (*temp_ptr);
-		GT_REG_WRITE (I2C_DATA, temp);
-		asm(" sync");
-		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
-		asm(" sync");
-
-		GT_REG_READ (I2C_CONTROL, &status);
-		while ((status & 0x08) != 0x08) {
-			GT_REG_READ (I2C_CONTROL, &status);
-			}
-
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-		while ((status & 0xff) != 0x28) {
-			if (count > 200) {
-				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-				asm(" sync");
-				return (status);
-			}
-			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-			count++;
-		}
-		len--;
-		temp_ptr++;
-	}
-	return (0);
-}
-
-
-static uchar i2c_write_byte (unsigned char *data, int len)
-{
-	unsigned int status;
-	int count;
-	unsigned int temp;
-	unsigned char *temp_ptr = data;
-
-	DP (puts ("i2c_write_byte\n"));
-
-	while (len) {
-		count = 0;
-		/* Set and assert the data */
-		temp = *temp_ptr;
-		GT_REG_WRITE (I2C_DATA, temp);
-		asm(" sync");
-		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
-		asm(" sync");
-
-
-		GT_REG_READ (I2C_CONTROL, &status);
-		while ((status & 0x08) != 0x08) {
-			GT_REG_READ (I2C_CONTROL, &status);
-			}
-
-		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-		count++;
-		while ((status & 0xff) != 0x28) {
-			if (count > 200) {
-				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
-				asm(" sync");
-				return (status);
-			}
-			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-			count++;
-		}
-		len--;
-		temp_ptr++;
-	}
-	return (0);
-}
-
-static uchar
-i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
-		    int alen)
-{
-	uchar status;
-	unsigned int table[2];
-
-	table[1] = (offset     ) & 0x0ff;	/* low byte */
-	table[0] = (offset >> 8) & 0x0ff;	/* high byte */
-
-	DP (puts ("i2c_set_dev_offset\n"));
-
-	status = i2c_select_device (dev_addr, 0, ten_bit);
-	if (status) {
-#ifdef DEBUG_I2C
-22		printf ("Failed to select device setting offset: 0x%02x\n",
-			status);
-#endif
-		return status;
-	}
-/* check the address offset length */
-	if (alen == 0)
-		/* no address offset */
-		return (0);
-	else if (alen == 1) {
-		/* 1 byte address offset */
-		status = i2c_write_data (&offset, 1);
-		if (status) {
-#ifdef DEBUG_I2C
-			printf ("Failed to write data: 0x%02x\n", status);
-#endif
-			return status;
-		}
-	} else if (alen == 2) {
-		/* 2 bytes address offset */
-		status = i2c_write_data (table, 2);
-		if (status) {
-#ifdef DEBUG_I2C
-			printf ("Failed to write data: 0x%02x\n", status);
-#endif
-			return status;
-		}
-	} else {
-		/* address offset unknown or not supported */
-		printf ("Address length offset %d is not supported\n", alen);
-		return 1;
-	}
-	return 0;		/* sucessful completion */
-}
-
-int
-i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
-	  int len)
-{
-	uchar status = 0;
-	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
-
-	DP (puts ("i2c_read\n"));
-
-	/* set the i2c frequency */
-	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
-
-	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Failed to set slave address & offset: 0x%02x\n",
-			status);
-#endif
-		return status;
-	}
-
-	status = i2c_select_device (dev_addr, 1, 0);
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Failed to select device for data read: 0x%02x\n",
-			status);
-#endif
-		return status;
-	}
-
-	status = i2c_get_data (data, len);
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Data not read: 0x%02x\n", status);
-#endif
-		return status;
-	}
-
-	return 0;
-}
-
-
-void i2c_stop (void)
-{
-	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
-	asm(" sync");
-}
-
-
-int
-i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
-	   int len)
-{
-	uchar status = 0;
-	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
-
-	DP (puts ("i2c_write\n"));
-
-	/* set the i2c frequency */
-	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
-
-	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Failed to set slave address & offset: 0x%02x\n",
-			status);
-#endif
-		return status;
-		}
-
-
-	status = i2c_write_byte (data, len);	/* write the data */
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Data not written: 0x%02x\n", status);
-#endif
-		return status;
-		}
-	/* issue a stop bit */
-	i2c_stop ();
-	return 0;
-}
-
-
-int i2c_probe (uchar chip)
-{
-
-#ifdef DEBUG_I2C
-	unsigned int i2c_status;
-#endif
-	uchar status = 0;
-	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
-
-	DP (puts ("i2c_probe\n"));
-
-	/* set the i2c frequency */
-	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
-
-	status = i2c_set_dev_offset (chip, 0, 0, 0);	/* send the slave address + no offset */
-	if (status) {
-#ifdef DEBUG_I2C
-		printf ("Failed to set slave address: 0x%02x\n", status);
-#endif
-		return (int) status;
-	}
-#ifdef DEBUG_I2C
-	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
-	printf ("address %#x returned %#x\n", chip, i2c_status);
-#endif
-	/* issue a stop bit */
-	i2c_stop ();
-	return 0;		/* successful completion */
-}
diff --git a/board/esd/cpci750/i2c.h b/board/esd/cpci750/i2c.h
deleted file mode 100644
index a879ea93c84..00000000000
--- a/board/esd/cpci750/i2c.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
- */
-
-#ifndef __I2C_H__
-#define __I2C_H__
-
-/* function declarations */
-uchar i2c_read(uchar, unsigned int, int, uchar*, int);
-
-#endif
diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c
deleted file mode 100644
index f555c08427a..00000000000
--- a/board/esd/cpci750/ide.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/* ide.c - ide support functions */
-
-
-#include <common.h>
-#if defined(CONFIG_CMD_IDE)
-#include <ata.h>
-#include <ide.h>
-#include <pci.h>
-
-int cpci_hd_type;
-
-int ata_device(int dev)
-{
-	int retval;
-
-	retval = (dev & 1) << 4;
-	if (cpci_hd_type == 2)
-		retval ^= 1 << 4;
-	return retval;
-}
-
-
-int ide_preinit (void)
-{
-	int status;
-	pci_dev_t devbusfn;
-	int l;
-
-	status = 1;
-	cpci_hd_type = 0;
-	if (CPCI750_SLAVE_TEST != 0)
-		return status;
-	for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
-		ide_bus_offset[l] = -ATA_STATUS;
-	}
-	devbusfn = pci_find_device (0x1103, 0x0004, 0);
-	if (devbusfn != -1) {
-		cpci_hd_type = 1;
-	} else {
-		devbusfn = pci_find_device (0x1095, 0x3114, 0);
-		if (devbusfn != -1) {
-			cpci_hd_type = 2;
-		}
-	}
-	if (devbusfn != -1) {
-		ulong *ide_bus_offset_ptr;
-
-		status = 0;
-
-		ide_bus_offset_ptr = &ide_bus_offset[0];
-		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
-				       (u32 *)ide_bus_offset_ptr);
-		ide_bus_offset[0] &= 0xfffffffe;
-		ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE;
-		ide_bus_offset_ptr = &ide_bus_offset[1];
-		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
-				       (u32 *)ide_bus_offset_ptr);
-		ide_bus_offset[1] &= 0xfffffffe;
-		ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;
-	}
-	return status;
-}
-
-void ide_set_reset (int flag) {
-	return;
-}
-
-#endif /* of CONFIG_CMDS_IDE */
diff --git a/board/esd/cpci750/local.h b/board/esd/cpci750/local.h
deleted file mode 100644
index 084f99f7171..00000000000
--- a/board/esd/cpci750/local.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * include/local.h - local configuration options, board specific
- */
-
-#ifndef __LOCAL_H
-#define __LOCAL_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/* This tells PPCBoot that the config options are compiled in */
-/* #undef ENV_IS_EMBEDDED */
-/* Don't touch this! PPCBOOT figures this out  based on other
- * magic. */
-
-/* Uncomment and define any of the below options */
-
-/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */
-#define CONFIG_750FX       /* The 750FX doesn't support as many things in L2CR like 750CX*/
-
-/* These want string arguments */
-/* #define CONFIG_BOOTARGS */
-/* #define CONFIG_BOOTCOMMAND */
-/* #define CONFIG_RAMBOOTCOMMAND */
-/* #define CONFIG_NFSBOOTCOMMAND */
-/* #define CONFIG_SYS_AUTOLOAD */
-/* #define CONFIG_PREBOOT */
-
-/* These don't */
-
-/* #define CONFIG_BOOTDELAY  */
-/* #define CONFIG_BAUDRATE */
-/* #define CONFIG_LOADS_ECHO */
-/* #define CONFIG_ETHADDR */
-/* #define CONFIG_ETH2ADDR */
-/* #define CONFIG_ETH3ADDR */
-/* #define CONFIG_IPADDR */
-/* #define CONFIG_SERVERIP */
-/* #define CONFIG_ROOTPATH */
-/* #define CONFIG_GATEWAYIP */
-/* #define CONFIG_NETMASK */
-/* #define CONFIG_HOSTNAME */
-/* #define CONFIG_BOOTFILE */
-/* #define CONFIG_LOADADDR */
-
-/* these hardware addresses are pretty bogus, please change them to
-   suit your needs */
-
-/* first ethernet */
-/* #define CONFIG_ETHADDR          86:06:2d:7e:c6:53 */
-#define CONFIG_ETHADDR          64:36:00:00:00:01
-
-/* next two ethernet hwaddrs */
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		86:06:2d:7e:c6:54
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR		86:06:2d:7e:c6:55
-
-#define CONFIG_ENV_OVERWRITE
-#endif	/* __CONFIG_H */
diff --git a/board/esd/cpci750/misc.S b/board/esd/cpci750/misc.S
deleted file mode 100644
index 233fd83bcca..00000000000
--- a/board/esd/cpci750/misc.S
+++ /dev/null
@@ -1,245 +0,0 @@
-#include <config.h>
-#include <74xx_7xx.h>
-#include "version.h"
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#include "../../Marvell/include/mv_gen_reg.h"
-
-#ifdef CONFIG_ECC
-	/* Galileo specific asm code for initializing ECC */
-	.globl board_relocate_rom
-board_relocate_rom:
-	mflr	r7
-	/* update the location of the GT registers */
-	lis	r11, CONFIG_SYS_GT_REGS@h
-	/* if we're using ECC, we must use the DMA engine to copy ourselves */
-	bl	start_idma_transfer_0
-	bl	wait_for_idma_0
-	bl	stop_idma_engine_0
-
-	mtlr	r7
-	blr
-
-	.globl board_init_ecc
-board_init_ecc:
-	mflr	r7
-	/* NOTE: r10 still contains the location we've been relocated to
-	 * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
-
-	/* now that we're running from ram, init the rest of main memory
-	 * for ECC use */
-	lis	r8, CONFIG_SYS_MONITOR_LEN@h
-	ori	r8, r8, CONFIG_SYS_MONITOR_LEN@l
-
-	divw	r3, r10, r8
-
-	/* set up the counter, and init the starting address */
-	mtctr	r3
-	li	r12, 0
-
-	/* bytes per transfer */
-	mr	r5, r8
-about_to_init_ecc:
-1:	mr	r3, r12
-	mr	r4, r12
-	bl	start_idma_transfer_0
-	bl	wait_for_idma_0
-	bl	stop_idma_engine_0
-	add	r12, r12, r8
-	bdnz	1b
-
-	mtlr	r7
-	blr
-
-	/* r3:	dest addr
-	 * r4:	source addr
-	 * r5:	byte count
-	 * r11: gt regbase
-	 * trashes:	 r6, r5
-	 */
-start_idma_transfer_0:
-	/* set the byte count, including the OWN bit */
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0_DMA_BYTE_COUNT
-	stwbrx	r5, 0, (r6)
-
-	/* set the source address */
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
-	stwbrx	r4, 0, (r6)
-
-	/* set the dest address */
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
-	stwbrx	r3, 0, (r6)
-
-	/* set the next record pointer */
-	li	r5, 0
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0NEXT_RECORD_POINTER
-	stwbrx	r5, 0, (r6)
-
-	/* set the low control register */
-	/* bit 9 is NON chained mode, bit 31 is new style descriptors.
-	   bit 12 is channel enable */
-	ori	r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
-	/* 15 shifted by 16 (oris) == bit 31 */
-	oris	r5, r5, (1 << 15)
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0CONTROL
-	stwbrx	r5, 0, (r6)
-
-	blr
-
-	/* this waits for the bytecount to return to zero, indicating
-	 * that the trasfer is complete */
-wait_for_idma_0:
-	mr	r5, r11
-	lis	r6, 0xff
-	ori	r6, r6, 0xffff
-	ori	r5, r5, CHANNEL0_DMA_BYTE_COUNT
-1:	lwbrx	r4, 0, (r5)
-	and.	r4, r4, r6
-	bne	1b
-
-	blr
-
-	/* this turns off channel 0 of the idma engine */
-stop_idma_engine_0:
-	/* shut off the DMA engine */
-	li	r5, 0
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0CONTROL
-	stwbrx	r5, 0, (r6)
-
-	blr
-#endif
-
-#ifdef CONFIG_SYS_BOARD_ASM_INIT
-	/* NOTE: trashes r3-r7 */
-	.globl board_asm_init
-board_asm_init:
-	/* just move the GT registers to where they belong */
-	lis	r3, CONFIG_SYS_DFL_GT_REGS@h
-	ori	r3, r3, CONFIG_SYS_DFL_GT_REGS@l
-	lis	r4, CONFIG_SYS_GT_REGS@h
-	ori	r4, r4, CONFIG_SYS_GT_REGS@l
-	li	r5, INTERNAL_SPACE_DECODE
-
-	/* test to see if we've already moved */
-	lwbrx	r6, r5, r4
-	andi.	r6, r6, 0xffff
-	/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
-/*	rlwinm	r7, r4, 8, 16, 31
-	rlwinm	r7, r4, 12, 16, 31	*/ /* original */
-	rlwinm	r7, r4, 16, 16, 31
-	/* -----------------------------------------------------*/
-	cmp	cr0, r7, r6
-	beqlr
-
-	/* nope, have to move the registers */
-	lwbrx	r6, r5, r3
-	andis.	r6, r6, 0xffff
-	or	r6, r6, r7
-	stwbrx	r6, r5, r3
-
-	/* now, poll for the change */
-1:	lwbrx	r7, r5, r4
-	cmp	cr0, r7, r6
-	bne	1b
-
-	lis	r3, CONFIG_SYS_INT_SRAM_BASE@h
-	ori	r3, r3, CONFIG_SYS_INT_SRAM_BASE@l
-	rlwinm  r3, r3, 16, 16, 31
-	lis	r4, CONFIG_SYS_GT_REGS@h
-	ori	r4, r4, CONFIG_SYS_GT_REGS@l
-	li	r5, INTEGRATED_SRAM_BASE_ADDR
-	stwbrx  r3, r5, r4
-
-2:	lwbrx	r6, r5, r4
-	cmp	cr0, r3, r6
-	bne	2b
-
-	/* done! */
-	blr
-#endif
-
-/* For use of the debug LEDs */
-	.global led_on0_relocated
-led_on0_relocated:
-	xor	r21, r21, r21
-	xor	r18, r18, r18
-	lis	r18, 0xFC80
-	ori	r18, r18, 0x8000
-/*	stw	r21, 0x0(r18)   */
-	sync
-	blr
-
-	.global led_off0_relocated
-led_off0_relocated:
-	xor	r21, r21, r21
-	xor	r18, r18, r18
-	lis	r18, 0xFC81
-	ori	r18, r18, 0x4000
-/*	stw	r21, 0x0(r18)   */
-	sync
-	blr
-
-	.global led_on0
-led_on0:
-	xor	r18, r18, r18
-	lis	r18, 0x1c80
-	ori	r18, r18, 0x8000
-/*	stw	r18, 0x0(r18)  */
-	sync
-	blr
-
-	.global led_off0
-led_off0:
-	xor	r18, r18, r18
-	lis	r18, 0x1c81
-	ori	r18, r18, 0x4000
-/*	stw	r18, 0x0(r18)  */
-	sync
-	blr
-
-	.global led_on1
-led_on1:
-	xor	r18, r18, r18
-	lis	r18, 0x1c80
-	ori	r18, r18, 0xc000
-/*	stw	r18, 0x0(r18)  */
-	sync
-	blr
-
-	.global led_off1
-led_off1:
-	xor	r18, r18, r18
-	lis	r18, 0x1c81
-	ori	r18, r18, 0x8000
-/*	stw	r18, 0x0(r18)  */
-	sync
-	blr
-
-	.global led_on2
-led_on2:
-	xor	r18, r18, r18
-	lis	r18, 0x1c81
-	ori	r18, r18, 0x0000
-/*	stw	r18, 0x0(r18)  */
-	sync
-	blr
-
-	.global led_off2
-led_off2:
-	xor	r18, r18, r18
-	lis	r18, 0x1c81
-	ori	r18, r18, 0xc000
-/*	stw	r18, 0x0(r18)  */
-	sync
-	blr
diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c
deleted file mode 100644
index a15877457df..00000000000
--- a/board/esd/cpci750/mpsc.c
+++ /dev/null
@@ -1,1002 +0,0 @@
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*************************************************************************
- * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
-  ************************************************************************/
-
-/*
- * mpsc.c - driver for console over the MPSC.
- */
-
-
-#include <common.h>
-#include <config.h>
-#include <asm/cache.h>
-
-#include <malloc.h>
-#include "mpsc.h"
-
-#include "mv_regs.h"
-
-#include "../../Marvell/include/memory.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Define this if you wish to use the MPSC as a register based UART.
- * This will force the serial port to not use the SDMA engine at all.
- */
-
-#undef CONFIG_MPSC_DEBUG_PORT
-
-
-int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
-char (*mpsc_getchar) (void) = mpsc_getchar_debug;
-int (*mpsc_test_char) (void) = mpsc_test_char_debug;
-
-
-static volatile unsigned int *rx_desc_base = NULL;
-static unsigned int rx_desc_index = 0;
-static volatile unsigned int *tx_desc_base = NULL;
-static unsigned int tx_desc_index = 0;
-
-/* local function declarations */
-static int galmpsc_connect (int channel, int connect);
-static int galmpsc_route_rx_clock (int channel, int brg);
-static int galmpsc_route_tx_clock (int channel, int brg);
-static int galmpsc_write_config_regs (int mpsc, int mode);
-static int galmpsc_config_channel_regs (int mpsc);
-static int galmpsc_set_char_length (int mpsc, int value);
-static int galmpsc_set_stop_bit_length (int mpsc, int value);
-static int galmpsc_set_parity (int mpsc, int value);
-static int galmpsc_enter_hunt (int mpsc);
-static int galmpsc_set_brkcnt (int mpsc, int value);
-static int galmpsc_set_tcschar (int mpsc, int value);
-static int galmpsc_set_snoop (int mpsc, int value);
-static int galmpsc_shutdown (int mpsc);
-
-static int galsdma_set_RFT (int channel);
-static int galsdma_set_SFM (int channel);
-static int galsdma_set_rxle (int channel);
-static int galsdma_set_txle (int channel);
-static int galsdma_set_burstsize (int channel, unsigned int value);
-static int galsdma_set_RC (int channel, unsigned int value);
-
-static int galbrg_set_CDV (int channel, int value);
-static int galbrg_enable (int channel);
-static int galbrg_disable (int channel);
-static int galbrg_set_clksrc (int channel, int value);
-static int galbrg_set_CUV (int channel, int value);
-
-static void galsdma_enable_rx (void);
-static int galsdma_set_mem_space (unsigned int memSpace,
-				  unsigned int memSpaceTarget,
-				  unsigned int memSpaceAttr,
-				  unsigned int baseAddress,
-				  unsigned int size);
-
-
-#define SOFTWARE_CACHE_MANAGEMENT
-
-#ifdef SOFTWARE_CACHE_MANAGEMENT
-#define FLUSH_DCACHE(a,b)		 if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
-#define INVALIDATE_DCACHE(a,b)		 if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
-#else
-#define FLUSH_DCACHE(a,b)
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
-#define INVALIDATE_DCACHE(a,b)
-#endif
-
-#ifdef CONFIG_MPSC_DEBUG_PORT
-static void mpsc_debug_init (void)
-{
-
-	volatile unsigned int temp;
-
-	/* Clear the CFR  (CHR4) */
-	/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
-	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
-	temp &= 0xffffff00;
-	temp |= BIT29;
-	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
-		      temp);
-
-	/* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
-	temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
-	temp |= (BIT12 | BIT15);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
-		      temp);
-
-	/* Set int mask */
-	temp = GTREGREAD (GALMPSC_0_INT_MASK);
-	temp |= BIT6;
-	GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
-}
-#endif
-
-char mpsc_getchar_debug (void)
-{
-	volatile int temp;
-	volatile unsigned int cause;
-
-	cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
-	while ((cause & BIT6) == 0) {
-		cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
-	}
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
-			  (CHANNEL * GALMPSC_REG_GAP));
-	/* By writing 1's to the set bits, the register is cleared */
-	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
-		      temp);
-	GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
-	return (temp >> 16) & 0xff;
-}
-
-/* special function for running out of flash.  doesn't modify any
- * global variables [josh] */
-int mpsc_putchar_early (char ch)
-{
-	int mpsc = CHANNEL;
-	int temp =
-		GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
-	galmpsc_set_tcschar (mpsc, ch);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
-		      temp | 0x200);
-
-#define MAGIC_FACTOR	(10*1000000)
-
-	udelay (MAGIC_FACTOR / gd->baudrate);
-	return 0;
-}
-
-/* This is used after relocation, see serial.c and mpsc_init2 */
-static int mpsc_putchar_sdma (char ch)
-{
-	volatile unsigned int *p;
-	unsigned int temp;
-
-
-	/* align the descriptor */
-	p = tx_desc_base;
-	memset ((void *) p, 0, 8 * sizeof (unsigned int));
-
-	/* fill one 64 bit buffer */
-	/* word swap, pad with 0 */
-	p[4] = 0;		/* x */
-	p[5] = (unsigned int) ch;	/* x */
-
-	/* CHANGED completely according to GT64260A dox - NTL */
-	p[0] = 0x00010001;	/* 0 */
-	p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* 4 */
-	p[2] = 0;		/* 8 */
-	p[3] = (unsigned int) &p[4];	/* c */
-
-#if 0
-	p[9] = DESC_FIRST | DESC_LAST;
-	p[10] = (unsigned int) &p[0];
-	p[11] = (unsigned int) &p[12];
-#endif
-
-	FLUSH_DCACHE (&p[0], &p[8]);
-
-	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
-		      (unsigned int) &p[0]);
-	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
-		      (unsigned int) &p[0]);
-
-	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
-	temp |= (TX_DEMAND | TX_STOP);
-	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
-
-	INVALIDATE_DCACHE (&p[1], &p[2]);
-
-	while (p[1] & DESC_OWNER_BIT) {
-		udelay (100);
-		INVALIDATE_DCACHE (&p[1], &p[2]);
-	}
-	return 0;
-}
-
-char mpsc_getchar_sdma (void)
-{
-	static unsigned int done = 0;
-	volatile char ch;
-	unsigned int len = 0, idx = 0, temp;
-
-	volatile unsigned int *p;
-
-
-	do {
-		p = &rx_desc_base[rx_desc_index * 8];
-
-		INVALIDATE_DCACHE (&p[0], &p[1]);
-		/* Wait for character */
-		while (p[1] & DESC_OWNER_BIT) {
-			udelay (100);
-			INVALIDATE_DCACHE (&p[0], &p[1]);
-		}
-
-		/* Handle error case */
-		if (p[1] & (1 << 15)) {
-			printf ("oops, error: %08x\n", p[1]);
-
-			temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
-					  (CHANNEL * GALMPSC_REG_GAP));
-			temp |= (1 << 23);
-			GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
-				      (CHANNEL * GALMPSC_REG_GAP), temp);
-
-			/* Can't poll on abort bit, so we just wait. */
-			udelay (100);
-
-			galsdma_enable_rx ();
-		}
-
-		/* Number of bytes left in this descriptor */
-		len = p[0] & 0xffff;
-
-		if (len) {
-			/* Where to look */
-			idx = 5;
-			if (done > 3)
-				idx = 4;
-			if (done > 7)
-				idx = 7;
-			if (done > 11)
-				idx = 6;
-
-			INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
-			ch = p[idx] & 0xff;
-			done++;
-		}
-
-		if (done < len) {
-			/* this descriptor has more bytes still
-			 * shift down the char we just read, and leave the
-			 * buffer in place for the next time around
-			 */
-			p[idx] = p[idx] >> 8;
-			FLUSH_DCACHE (&p[idx], &p[idx + 1]);
-		}
-
-		if (done == len) {
-			/* nothing left in this descriptor.
-			 * go to next one
-			 */
-			p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
-			p[0] = 0x00100000;
-			FLUSH_DCACHE (&p[0], &p[1]);
-			/* Next descriptor */
-			rx_desc_index = (rx_desc_index + 1) % RX_DESC;
-			done = 0;
-		}
-	} while (len == 0);	/* galileo bug.. len might be zero */
-
-	return ch;
-}
-
-
-int mpsc_test_char_debug (void)
-{
-	if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
-		return 0;
-	else {
-		return 1;
-	}
-}
-
-
-int mpsc_test_char_sdma (void)
-{
-	volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
-
-	INVALIDATE_DCACHE (&p[1], &p[2]);
-
-	if (p[1] & DESC_OWNER_BIT)
-		return 0;
-	else
-		return 1;
-}
-
-int mpsc_init (int baud)
-{
-	/* BRG CONFIG */
-	galbrg_set_baudrate (CHANNEL, baud);
-	galbrg_set_clksrc (CHANNEL, 8);	/* set source=Tclk */
-	galbrg_set_CUV (CHANNEL, 0);	/* set up CountUpValue */
-	galbrg_enable (CHANNEL);	/* Enable BRG */
-
-	/* Set up clock routing */
-	galmpsc_connect (CHANNEL, GALMPSC_CONNECT);	/* connect it */
-
-	galmpsc_route_rx_clock (CHANNEL, CHANNEL);	/* chosse BRG0 for Rx */
-	galmpsc_route_tx_clock (CHANNEL, CHANNEL);	/* chose BRG0 for Tx */
-
-	/* reset MPSC state */
-	galmpsc_shutdown (CHANNEL);
-
-	/* SDMA CONFIG */
-	galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8);	/* in 64 bit words (8 bytes) */
-	galsdma_set_txle (CHANNEL);
-	galsdma_set_rxle (CHANNEL);
-	galsdma_set_RC (CHANNEL, 0xf);
-	galsdma_set_SFM (CHANNEL);
-	galsdma_set_RFT (CHANNEL);
-
-	/* MPSC CONFIG */
-	galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
-	galmpsc_config_channel_regs (CHANNEL);
-	galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8);	/* 8 */
-	galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE);	/* N */
-	galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1);	/* 1 */
-
-#ifdef CONFIG_MPSC_DEBUG_PORT
-	mpsc_debug_init ();
-#endif
-
-	/* COMM_MPSC CONFIG */
-#ifdef SOFTWARE_CACHE_MANAGEMENT
-	galmpsc_set_snoop (CHANNEL, 0);	/* disable snoop */
-#else
-	galmpsc_set_snoop (CHANNEL, 1);	/* enable snoop */
-#endif
-
-	return 0;
-}
-
-
-void mpsc_sdma_init (void)
-{
-/* Setup SDMA channel0 SDMA_CONFIG_REG*/
-	GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
-
-/*  Enable MPSC-Window0 for DRAM Bank0   */
-	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT,
-				   MV64360_SDMA_DRAM_CS_0_TARGET,
-				   0,
-				   memoryGetBankBaseAddress
-				   (CS_0_LOW_DECODE_ADDRESS),
-				   memoryGetBankSize (BANK0)) != true)
-		printf ("%s: SDMA_Window0 memory setup failed !!! \n",
-			__FUNCTION__);
-
-
-/*  Disable MPSC-Window1    */
-	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT,
-				   MV64360_SDMA_DRAM_CS_0_TARGET,
-				   0,
-				   memoryGetBankBaseAddress
-				   (CS_1_LOW_DECODE_ADDRESS),
-				   memoryGetBankSize (BANK3)) != true)
-		printf ("%s: SDMA_Window1 memory setup failed !!! \n",
-			__FUNCTION__);
-
-
-/*  Disable MPSC-Window2 */
-	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT,
-				   MV64360_SDMA_DRAM_CS_0_TARGET,
-				   0,
-				   memoryGetBankBaseAddress
-				   (CS_2_LOW_DECODE_ADDRESS),
-				   memoryGetBankSize (BANK3)) != true)
-		printf ("%s: SDMA_Window2 memory setup failed !!! \n",
-			__FUNCTION__);
-
-
-/*  Disable MPSC-Window3 */
-	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT,
-				   MV64360_SDMA_DRAM_CS_0_TARGET,
-				   0,
-				   memoryGetBankBaseAddress
-				   (CS_3_LOW_DECODE_ADDRESS),
-				   memoryGetBankSize (BANK3)) != true)
-		printf ("%s: SDMA_Window3 memory setup failed !!! \n",
-			__FUNCTION__);
-
-/*  Setup MPSC0 access mode Window0 full access */
-	GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
-			 (MV64360_SDMA_WIN_ACCESS_FULL <<
-			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
-
-/*  Setup MPSC1 access mode Window1 full access */
-	GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
-			 (MV64360_SDMA_WIN_ACCESS_FULL <<
-			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
-
-/* Setup MPSC internal address space base address	*/
-	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
-
-/* no high address remap*/
-	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
-	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
-
-/* clear interrupt cause register for MPSC (fault register)*/
-	GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
-}
-
-
-void mpsc_init2 (void)
-{
-	int i;
-
-#ifndef CONFIG_MPSC_DEBUG_PORT
-	mpsc_putchar = mpsc_putchar_sdma;
-	mpsc_getchar = mpsc_getchar_sdma;
-	mpsc_test_char = mpsc_test_char_sdma;
-#endif
-	/* RX descriptors */
-	rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
-						sizeof (unsigned int));
-
-	/* align descriptors */
-	rx_desc_base = (unsigned int *)
-		(((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
-
-	rx_desc_index = 0;
-
-	memset ((void *) rx_desc_base, 0,
-		(RX_DESC * 8) * sizeof (unsigned int));
-
-	for (i = 0; i < RX_DESC; i++) {
-		rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4];	/* Buffer */
-		rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8];	/* Next descriptor */
-		rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* Command & control */
-		rx_desc_base[i * 8] = 0x00100000;
-	}
-	rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
-
-	FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
-	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
-		      (unsigned int) &rx_desc_base[0]);
-
-	/* TX descriptors */
-	tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
-						sizeof (unsigned int));
-
-	/* align descriptors */
-	tx_desc_base = (unsigned int *)
-		(((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
-
-	tx_desc_index = -1;
-
-	memset ((void *) tx_desc_base, 0,
-		(TX_DESC * 8) * sizeof (unsigned int));
-
-	for (i = 0; i < TX_DESC; i++) {
-		tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
-		tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
-		tx_desc_base[i * 8 + 3] =
-			(unsigned int) &tx_desc_base[i * 8 + 4];
-		tx_desc_base[i * 8 + 2] =
-			(unsigned int) &tx_desc_base[(i + 1) * 8];
-		tx_desc_base[i * 8 + 1] =
-			DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
-
-		/* set sbytecnt and shadow byte cnt to 1 */
-		tx_desc_base[i * 8] = 0x00010001;
-	}
-	tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
-
-	FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
-
-	udelay (100);
-
-	galsdma_enable_rx ();
-
-	return;
-}
-
-int galbrg_set_baudrate (int channel, int rate)
-{
-	int clock;
-
-	galbrg_disable (channel);	/*ok */
-
-#ifdef ZUMA_NTL
-	/* from tclk */
-	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
-#else
-	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
-#endif
-
-	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
-
-	galbrg_enable (channel);
-
-	gd->baudrate = rate;
-
-	return 0;
-}
-
-/* ------------------------------------------------------------------ */
-
-/* Below are all the private functions that no one else needs */
-
-static int galbrg_set_CDV (int channel, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp &= 0xFFFF0000;
-	temp |= (value & 0x0000FFFF);
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galbrg_enable (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp |= 0x00010000;
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galbrg_disable (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp &= 0xFFFEFFFF;
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galbrg_set_clksrc (int channel, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp &= 0xFFC3FFFF;	/* Bit 18 - 21 (MV 64260 18-22) */
-	temp |= (value << 18);
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-	return 0;
-}
-
-static int galbrg_set_CUV (int channel, int value)
-{
-	/* set CountUpValue */
-	GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
-
-	return 0;
-}
-
-#if 0
-static int galbrg_reset (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp |= 0x20000;
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
-	return 0;
-}
-#endif
-
-static int galsdma_set_RFT (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp |= 0x00000001;
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_SFM (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp |= 0x00000002;
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_rxle (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp |= 0x00000040;
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_txle (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp |= 0x00000080;
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_RC (int channel, unsigned int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp &= ~0x0000003c;
-	temp |= (value << 2);
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_burstsize (int channel, unsigned int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp &= 0xFFFFCFFF;
-	switch (value) {
-	case 8:
-		GT_REG_WRITE (GALSDMA_0_CONF_REG +
-			      (channel * GALSDMA_REG_DIFF),
-			      (temp | (0x3 << 12)));
-		break;
-
-	case 4:
-		GT_REG_WRITE (GALSDMA_0_CONF_REG +
-			      (channel * GALSDMA_REG_DIFF),
-			      (temp | (0x2 << 12)));
-		break;
-
-	case 2:
-		GT_REG_WRITE (GALSDMA_0_CONF_REG +
-			      (channel * GALSDMA_REG_DIFF),
-			      (temp | (0x1 << 12)));
-		break;
-
-	case 1:
-		GT_REG_WRITE (GALSDMA_0_CONF_REG +
-			      (channel * GALSDMA_REG_DIFF),
-			      (temp | (0x0 << 12)));
-		break;
-
-	default:
-		return -1;
-		break;
-	}
-
-	return 0;
-}
-
-static int galmpsc_connect (int channel, int connect)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
-
-	if ((channel == 0) && connect)
-		temp &= ~0x00000007;
-	else if ((channel == 1) && connect)
-		temp &= ~(0x00000007 << 6);
-	else if ((channel == 0) && !connect)
-		temp |= 0x00000007;
-	else
-		temp |= (0x00000007 << 6);
-
-	/* Just in case... */
-	temp &= 0x3fffffff;
-
-	GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
-
-	return 0;
-}
-
-static int galmpsc_route_rx_clock (int channel, int brg)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_RxC_ROUTE);
-
-	if (channel == 0) {
-		temp &= ~0x0000000F;
-		temp |= brg;
-	} else {
-		temp &= ~0x00000F00;
-		temp |= (brg << 8);
-	}
-
-	GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
-
-	return 0;
-}
-
-static int galmpsc_route_tx_clock (int channel, int brg)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_TxC_ROUTE);
-
-	if (channel == 0) {
-		temp &= ~0x0000000F;
-		temp |= brg;
-	} else {
-		temp &= ~0x00000F00;
-		temp |= (brg << 8);
-	}
-
-	GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
-
-	return 0;
-}
-
-static int galmpsc_write_config_regs (int mpsc, int mode)
-{
-	if (mode == GALMPSC_UART) {
-		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
-		GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
-			      0x000004c4);
-
-		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
-		GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
-			      0x024003f8);
-		/*        22 2222 1111 */
-		/*        54 3210 9876 */
-		/* 0000 0010 0000 0000 */
-		/*       1 */
-		/*       098 7654 3210 */
-		/* 0000 0011 1111 1000 */
-	} else
-		return -1;
-
-	return 0;
-}
-
-static int galmpsc_config_channel_regs (int mpsc)
-{
-	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
-
-	galmpsc_set_brkcnt (mpsc, 0x3);
-	galmpsc_set_tcschar (mpsc, 0xab);
-
-	return 0;
-}
-
-static int galmpsc_set_brkcnt (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
-	temp &= 0x0000FFFF;
-	temp |= (value << 16);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_set_tcschar (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
-	temp &= 0xFFFF0000;
-	temp |= value;
-	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_set_char_length (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
-	temp &= 0xFFFFCFFF;
-	temp |= (value << 12);
-	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_set_stop_bit_length (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
-	temp &= 0xFFFFBFFF;
-	temp |= (value << 14);
-	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_set_parity (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
-	if (value != -1) {
-		temp &= 0xFFF3FFF3;
-		temp |= ((value << 18) | (value << 2));
-		temp |= ((value << 17) | (value << 1));
-	} else {
-		temp &= 0xFFF1FFF1;
-	}
-
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_enter_hunt (int mpsc)
-{
-	int temp;
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
-	temp |= 0x80000000;
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
-	       MPSC_ENTER_HUNT) {
-		udelay (1);
-	}
-	return 0;
-}
-
-
-static int galmpsc_shutdown (int mpsc)
-{
-	unsigned int temp;
-
-	/* cause RX abort (clears RX) */
-	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
-	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
-	temp &= ~MPSC_ENTER_HUNT;
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
-	GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
-
-	/* shut down the MPSC */
-	GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
-	GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
-	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
-
-	udelay (100);
-
-	/* shut down the sdma engines. */
-	/* reset config to default */
-	GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
-
-	udelay (100);
-
-	/* clear the SDMA current and first TX and RX pointers */
-	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
-	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
-	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
-
-	udelay (100);
-
-	return 0;
-}
-
-static void galsdma_enable_rx (void)
-{
-	int temp;
-
-	/* Enable RX processing */
-	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
-	temp |= RX_ENABLE;
-	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
-
-	galmpsc_enter_hunt (CHANNEL);
-}
-
-static int galmpsc_set_snoop (int mpsc, int value)
-{
-	int reg =
-		mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
-		MPSC_0_ADDRESS_CONTROL_LOW;
-	int temp = GTREGREAD (reg);
-
-	if (value)
-		temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
-	else
-		temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
-	GT_REG_WRITE (reg, temp);
-	return 0;
-}
-
-/*******************************************************************************
-* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map.
-*
-* DESCRIPTION:
-*       the MV64360 SDMA has its own address decoding map that is de-coupled
-*       from the CPU interface address decoding windows. The SDMA channels
-*       share four address windows. Each region can be individually configured
-*       by this function by associating it to a target interface and setting
-*       base and size values.
-*
-*      NOTE!!!
-*       The size must be in 64Kbyte granularity.
-*       The base address must be aligned to the size.
-*       The size must be a series of 1s followed by a series of zeros
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       true for success, false otherwise.
-*
-*******************************************************************************/
-
-static int galsdma_set_mem_space (unsigned int memSpace,
-				  unsigned int memSpaceTarget,
-				  unsigned int memSpaceAttr,
-				  unsigned int baseAddress, unsigned int size)
-{
-	unsigned int temp;
-
-	if (size == 0) {
-		GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
-				   1 << memSpace);
-		return true;
-	}
-
-	/* The base address must be aligned to the size.  */
-	if (baseAddress % size != 0) {
-		return false;
-	}
-	if (size < 0x10000) {
-		return false;
-	}
-
-	/* Align size and base to 64K */
-	baseAddress &= 0xffff0000;
-	size &= 0xffff0000;
-	temp = size >> 16;
-
-	/* Checking that the size is a sequence of '1' followed by a
-	   sequence of '0' starting from LSB to MSB. */
-	while ((temp > 0) && (temp & 0x1)) {
-		temp = temp >> 1;
-	}
-
-	if (temp != 0) {
-		GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
-			      (baseAddress | memSpaceTarget | memSpaceAttr));
-		GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8),
-			      (size - 1) & 0xffff0000);
-		GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
-				   1 << memSpace);
-	} else {
-		/* An invalid size was specified */
-		return false;
-	}
-	return true;
-}
diff --git a/board/esd/cpci750/mpsc.h b/board/esd/cpci750/mpsc.h
deleted file mode 100644
index 241f28a31ab..00000000000
--- a/board/esd/cpci750/mpsc.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*************************************************************************
- * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
-  ************************************************************************/
-
-
-/*
- * mpsc.h - header file for MPSC in uart mode (console driver)
- */
-
-#ifndef __MPSC_H__
-#define __MPSC_H__
-
-/* include actual Galileo defines */
-#include "../../Marvell/include/mv_gen_reg.h"
-
-/* driver related defines */
-
-int mpsc_init(int baud);
-void mpsc_sdma_init(void);
-void mpsc_init2(void);
-int galbrg_set_baudrate(int channel, int rate);
-
-int mpsc_putchar_early(char ch);
-char mpsc_getchar_debug(void);
-int mpsc_test_char_debug(void);
-
-int mpsc_test_char_sdma(void);
-
-extern int (*mpsc_putchar)(char ch);
-extern char (*mpsc_getchar)(void);
-extern int (*mpsc_test_char)(void);
-
-#define CHANNEL CONFIG_MPSC_PORT
-
-#define TX_DESC     5
-#define RX_DESC     20
-
-#define DESC_FIRST  0x00010000
-#define DESC_LAST   0x00020000
-#define DESC_OWNER_BIT  0x80000000
-
-#define TX_DEMAND   0x00800000
-#define TX_STOP     0x00010000
-#define RX_ENABLE   0x00000080
-
-#define SDMA_RX_ABORT		  (1 << 15)
-#define SDMA_TX_ABORT		  (1 << 31)
-#define MPSC_TX_ABORT		  (1 << 7)
-#define MPSC_RX_ABORT             (1 << 23)
-#define MPSC_ENTER_HUNT           (1 << 31)
-
-/* MPSC defines */
-
-#define GALMPSC_CONNECT            0x1
-#define GALMPSC_DISCONNECT         0x0
-
-#define GALMPSC_UART               0x1
-
-#define GALMPSC_STOP_BITS_1        0x0
-#define GALMPSC_STOP_BITS_2        0x1
-#define GALMPSC_CHAR_LENGTH_8      0x3
-#define GALMPSC_CHAR_LENGTH_7      0x2
-
-#define GALMPSC_PARITY_ODD         0x0
-#define GALMPSC_PARITY_EVEN        0x2
-#define GALMPSC_PARITY_MARK        0x3
-#define GALMPSC_PARITY_SPACE       0x1
-#define GALMPSC_PARITY_NONE        -1
-
-#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
-#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
-#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
-#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
-#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
-#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
-#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
-
-#define GALMPSC_REG_GAP            0x1000
-
-#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
-#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
-#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
-#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
-#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
-#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
-#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
-#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
-#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
-#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
-#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
-#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
-
-#define GALSDMA_COMMAND_FIRST     (1 << 16)
-#define GALSDMA_COMMAND_LAST      (1 << 17)
-#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
-#define GALSDMA_COMMAND_AUTO      (1 << 30)
-#define GALSDMA_COMMAND_OWNER     (1 << 31)
-
-#define GALSDMA_RX                 0
-#define GALSDMA_TX                 1
-
-/* CHANNEL2 should be CHANNEL1, according to documentation,
- * but to work with the current GTREGS file...
- */
-#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
-#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
-#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
-#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
-#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
-#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
-#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
-#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
-#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
-#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
-#define GALSDMA_REG_DIFF           0x2000
-
-/* WRONG in gt64260R.h */
-#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
-#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
-#define GALMPSC_0_INT_CAUSE        0xb804
-#define GALMPSC_0_INT_MASK         0xb884
-
-#define GALSDMA_MODE_UART          0
-#define GALSDMA_MODE_BISYNC        1
-#define GALSDMA_MODE_HDLC          2
-#define GALSDMA_MODE_TRANSPARENT   3
-
-#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
-#define GALBRG_REG_GAP             0x0008
-#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
-
-#endif /* __MPSC_H__ */
diff --git a/board/esd/cpci750/mv_eth.c b/board/esd/cpci750/mv_eth.c
deleted file mode 100644
index cbdcfe33c5c..00000000000
--- a/board/esd/cpci750/mv_eth.c
+++ /dev/null
@@ -1,3131 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-/*
- * mv_eth.c - header file for the polled mode GT ethernet driver
- */
-#include <common.h>
-#include <net.h>
-#include <malloc.h>
-
-#include "mv_eth.h"
-
-/* enable Debug outputs */
-
-#undef DEBUG_MV_ETH
-
-#ifdef DEBUG_MV_ETH
-#define DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-#undef MV64360_CHECKSUM_OFFLOAD
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The first part is the high level driver of the gigE ethernet ports.   *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-
-/* Definition for configuring driver */
-/* #define UPDATE_STATS_BY_SOFTWARE */
-#undef MV64360_RX_QUEUE_FILL_ON_TASK
-
-
-/* Constants */
-#define MAGIC_ETH_RUNNING		8031971
-#define MV64360_INTERNAL_SRAM_SIZE                      _256K
-#define EXTRA_BYTES 32
-#define WRAP       ETH_HLEN + 2 + 4 + 16
-#define BUFFER_MTU dev->mtu + WRAP
-#define INT_CAUSE_UNMASK_ALL		0x0007ffff
-#define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
-#ifdef MV64360_RX_FILL_ON_TASK
-#define INT_CAUSE_MASK_ALL		0x00000000
-#define INT_CAUSE_CHECK_BITS		INT_CAUSE_UNMASK_ALL
-#define INT_CAUSE_CHECK_BITS_EXT	INT_CAUSE_UNMASK_ALL_EXT
-#endif
-
-/* Read/Write to/from MV64360 internal registers */
-#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
-#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
-#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
-#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
-
-/* Static function declarations */
-static int mv64360_eth_real_open (struct eth_device *eth);
-static int mv64360_eth_real_stop (struct eth_device *eth);
-static struct net_device_stats *mv64360_eth_get_stats (struct eth_device
-						       *dev);
-static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
-static void mv64360_eth_update_stat (struct eth_device *dev);
-bool db64360_eth_start (struct eth_device *eth);
-unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
-				   unsigned int mib_offset);
-int mv64360_eth_receive (struct eth_device *dev);
-
-int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
-
-#ifndef  UPDATE_STATS_BY_SOFTWARE
-static void mv64360_eth_print_stat (struct eth_device *dev);
-#endif
-
-extern unsigned int INTERNAL_REG_BASE_ADDR;
-
-/*************************************************
- *Helper functions - used inside the driver only *
- *************************************************/
-#ifdef DEBUG_MV_ETH
-void print_globals (struct eth_device *dev)
-{
-	printf ("Ethernet PRINT_Globals-Debug function\n");
-	printf ("Base Address for ETH_PORT_INFO:	%08x\n",
-		(unsigned int) dev->priv);
-	printf ("Base Address for mv64360_eth_priv:	%08x\n",
-		(unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
-				 port_private));
-
-	printf ("GT Internal Base Address:	%08x\n",
-		INTERNAL_REG_BASE_ADDR);
-	printf ("Base Address for TX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE);
-	printf ("Base Address for RX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE);
-	printf ("Base Address for RX-Buffer:	%08x	allocated Bytes %d\n",
-		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
-		p_rx_buffer_base[0],
-		(MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32);
-	printf ("Base Address for TX-Buffer:	%08x	allocated Bytes %d\n",
-		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
-		p_tx_buffer_base[0],
-		(MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32);
-}
-#endif
-
-#define my_cpu_to_le32(x) my_le32_to_cpu((x))
-
-unsigned long my_le32_to_cpu (unsigned long x)
-{
-	return (((x & 0x000000ffU) << 24) |
-		((x & 0x0000ff00U) << 8) |
-		((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
-}
-
-
-/**********************************************************************
- * mv64360_eth_print_phy_status
- *
- * Prints gigabit ethenret phy status
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64360_eth_print_phy_status (struct eth_device *dev)
-{
-	struct mv64360_eth_priv *port_private;
-	unsigned int port_num;
-	ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	unsigned int port_status, phy_reg_data;
-
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-	/* Check Link status on phy */
-	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
-	if (!(phy_reg_data & 0x20)) {
-		printf ("Ethernet port changed link status to DOWN\n");
-	} else {
-		port_status =
-			MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
-		printf ("Ethernet status port %d: Link up", port_num);
-		printf (", %s",
-			(port_status & BIT2) ? "Full Duplex" : "Half Duplex");
-		if (port_status & BIT4)
-			printf (", Speed 1 Gbps");
-		else
-			printf (", %s",
-				(port_status & BIT5) ? "Speed 100 Mbps" :
-				"Speed 10 Mbps");
-		printf ("\n");
-	}
-}
-
-/**********************************************************************
- * u-boot entry functions for mv64360_eth
- *
- **********************************************************************/
-int db64360_eth_probe (struct eth_device *dev)
-{
-	return ((int) db64360_eth_start (dev));
-}
-
-int db64360_eth_poll (struct eth_device *dev)
-{
-	return mv64360_eth_receive (dev);
-}
-
-int db64360_eth_transmit(struct eth_device *dev, void *packet, int length)
-{
-	mv64360_eth_xmit (dev, packet, length);
-	return 0;
-}
-
-void db64360_eth_disable (struct eth_device *dev)
-{
-	mv64360_eth_stop (dev);
-}
-
-
-void mv6436x_eth_initialize (bd_t * bis)
-{
-	struct eth_device *dev;
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	int devnum, x, temp;
-	char *s, *e, buf[64];
-
-	for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
-		dev = calloc (sizeof (*dev), 1);
-		if (!dev) {
-			printf ("%s: mv_enet%d allocation failure, %s\n",
-				__FUNCTION__, devnum, "eth_device structure");
-			return;
-		}
-
-		/* must be less than sizeof(dev->name) */
-		sprintf (dev->name, "mv_enet%d", devnum);
-
-#ifdef DEBUG
-		printf ("Initializing %s\n", dev->name);
-#endif
-
-		/* Extract the MAC address from the environment */
-		switch (devnum) {
-		case 0:
-			s = "ethaddr";
-			break;
-
-		case 1:
-			s = "eth1addr";
-			break;
-
-		case 2:
-			s = "eth2addr";
-			break;
-
-		default:	/* this should never happen */
-			printf ("%s: Invalid device number %d\n",
-				__FUNCTION__, devnum);
-			return;
-		}
-
-		temp = getenv_f(s, buf, sizeof (buf));
-		s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
-		printf ("Setting MAC %d to %s\n", devnum, s);
-#endif
-		for (x = 0; x < 6; ++x) {
-			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
-			if (s)
-				s = (*e) ? e + 1 : e;
-		}
-		/* ronen - set the MAC addr in the HW */
-		eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
-
-		dev->init = (void *) db64360_eth_probe;
-		dev->halt = (void *) ethernet_phy_reset;
-		dev->send = (void *) db64360_eth_transmit;
-		dev->recv = (void *) db64360_eth_poll;
-
-		ethernet_private =
-			calloc (sizeof (*ethernet_private), 1);
-		dev->priv = (void *) ethernet_private;
-		if (!ethernet_private) {
-			printf ("%s: %s allocation failure, %s\n",
-				__FUNCTION__, dev->name,
-				"Private Device Structure");
-			free (dev);
-			return;
-		}
-		/* start with an zeroed ETH_PORT_INFO */
-		memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
-		memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
-
-		/* set pointer to memory for stats data structure etc... */
-		port_private =
-			calloc (sizeof (*ethernet_private), 1);
-		ethernet_private->port_private = (void *)port_private;
-		if (!port_private) {
-			printf ("%s: %s allocation failure, %s\n",
-				__FUNCTION__, dev->name,
-				"Port Private Device Structure");
-
-			free (ethernet_private);
-			free (dev);
-			return;
-		}
-
-		port_private->stats =
-			calloc (sizeof (struct net_device_stats), 1);
-		if (!port_private->stats) {
-			printf ("%s: %s allocation failure, %s\n",
-				__FUNCTION__, dev->name,
-				"Net stat Structure");
-
-			free (port_private);
-			free (ethernet_private);
-			free (dev);
-			return;
-		}
-		memset (ethernet_private->port_private, 0,
-			sizeof (struct mv64360_eth_priv));
-		switch (devnum) {
-		case 0:
-			ethernet_private->port_num = ETH_0;
-			break;
-		case 1:
-			ethernet_private->port_num = ETH_1;
-			break;
-		case 2:
-			ethernet_private->port_num = ETH_2;
-			break;
-		default:
-			printf ("Invalid device number %d\n", devnum);
-			break;
-		};
-
-		port_private->port_num = devnum;
-		/*
-		 * Read MIB counter on the GT in order to reset them,
-		 * then zero all the stats fields in memory
-		 */
-		mv64360_eth_update_stat (dev);
-		memset (port_private->stats, 0,
-			sizeof (struct net_device_stats));
-		/* Extract the MAC address from the environment */
-		switch (devnum) {
-		case 0:
-			s = "ethaddr";
-			break;
-
-		case 1:
-			s = "eth1addr";
-			break;
-
-		case 2:
-			s = "eth2addr";
-			break;
-
-		default:	/* this should never happen */
-			printf ("%s: Invalid device number %d\n",
-				__FUNCTION__, devnum);
-			return;
-		}
-
-		temp = getenv_f(s, buf, sizeof (buf));
-		s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
-		printf ("Setting MAC %d to %s\n", devnum, s);
-#endif
-		for (x = 0; x < 6; ++x) {
-			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
-			if (s)
-				s = (*e) ? e + 1 : e;
-		}
-
-		DP (printf ("Allocating descriptor and buffer rings\n"));
-
-		ethernet_private->p_rx_desc_area_base[0] =
-			(ETH_RX_DESC *) memalign (16,
-						  RX_DESC_ALIGNED_SIZE *
-						  MV64360_RX_QUEUE_SIZE + 1);
-		ethernet_private->p_tx_desc_area_base[0] =
-			(ETH_TX_DESC *) memalign (16,
-						  TX_DESC_ALIGNED_SIZE *
-						  MV64360_TX_QUEUE_SIZE + 1);
-
-		ethernet_private->p_rx_buffer_base[0] =
-			(char *) memalign (16,
-					   MV64360_RX_QUEUE_SIZE *
-					   MV64360_TX_BUFFER_SIZE + 1);
-		ethernet_private->p_tx_buffer_base[0] =
-			(char *) memalign (16,
-					   MV64360_RX_QUEUE_SIZE *
-					   MV64360_TX_BUFFER_SIZE + 1);
-
-#ifdef DEBUG_MV_ETH
-		/* DEBUG OUTPUT prints adresses of globals */
-		print_globals (dev);
-#endif
-		eth_register (dev);
-
-	}
-	DP (printf ("%s: exit\n", __FUNCTION__));
-
-}
-
-/**********************************************************************
- * mv64360_eth_open
- *
- * This function is called when openning the network device. The function
- * should initialize all the hardware, initialize cyclic Rx/Tx
- * descriptors chain and buffers and allocate an IRQ to the network
- * device.
- *
- * Input : a pointer to the network device structure
- * / / ronen - changed the output to match  net/eth.c needs
- * Output : nonzero of success , zero if fails.
- * under construction
- **********************************************************************/
-
-int mv64360_eth_open (struct eth_device *dev)
-{
-	return (mv64360_eth_real_open (dev));
-}
-
-/* Helper function for mv64360_eth_open */
-static int mv64360_eth_real_open (struct eth_device *dev)
-{
-
-	unsigned int queue;
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	unsigned int port_num;
-	u32 phy_reg_data;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	/* ronen - when we update the MAC env params we only update dev->enetaddr
-	   see ./net/eth.c eth_set_enetaddr() */
-	memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
-
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-	/* Stop RX Queues */
-	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
-		      0x0000ff00);
-
-	/* Clear the ethernet port interrupts */
-	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
-	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
-
-	/* Unmask RX buffer and TX end interrupt */
-	MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num),
-		      INT_CAUSE_UNMASK_ALL);
-
-	/* Unmask phy and link status changes interrupts */
-	MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
-		      INT_CAUSE_UNMASK_ALL_EXT);
-
-	/* Set phy address of the port */
-	ethernet_private->port_phy_addr = 0x8 + port_num;
-
-	/* Activate the DMA channels etc */
-	eth_port_init (ethernet_private);
-
-
-	/* "Allocate" setup TX rings */
-
-	for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
-		unsigned int size;
-
-		port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE;
-		size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE);	/*size = no of DESCs times DESC-size */
-		ethernet_private->tx_desc_area_size[queue] = size;
-
-		/* first clear desc area completely */
-		memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
-			0, ethernet_private->tx_desc_area_size[queue]);
-
-		/* initialize tx desc ring with low level driver */
-		if (ether_init_tx_desc_ring
-		    (ethernet_private, ETH_Q0,
-		     port_private->tx_ring_size[queue],
-		     MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
-		     (unsigned int) ethernet_private->
-		     p_tx_desc_area_base[queue],
-		     (unsigned int) ethernet_private->
-		     p_tx_buffer_base[queue]) == false)
-			printf ("### Error initializing TX Ring\n");
-	}
-
-	/* "Allocate" setup RX rings */
-	for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
-		unsigned int size;
-
-		/* Meantime RX Ring are fixed - but must be configurable by user */
-		port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE;
-		size = (port_private->rx_ring_size[queue] *
-			RX_DESC_ALIGNED_SIZE);
-		ethernet_private->rx_desc_area_size[queue] = size;
-
-		/* first clear desc area completely */
-		memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
-			0, ethernet_private->rx_desc_area_size[queue]);
-		if ((ether_init_rx_desc_ring
-		     (ethernet_private, ETH_Q0,
-		      port_private->rx_ring_size[queue],
-		      MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
-		      (unsigned int) ethernet_private->
-		      p_rx_desc_area_base[queue],
-		      (unsigned int) ethernet_private->
-		      p_rx_buffer_base[queue])) == false)
-			printf ("### Error initializing RX Ring\n");
-	}
-
-	eth_port_start (ethernet_private);
-
-	/* Set maximum receive buffer to 9700 bytes */
-	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num),
-		      (0x5 << 17) |
-		      (MV_REG_READ
-		       (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num))
-		       & 0xfff1ffff));
-
-	/*
-	 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
-	 * disable the leaky bucket mechanism .
-	 */
-
-	MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
-	MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
-
-	/* Check Link status on phy */
-	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
-	if (!(phy_reg_data & 0x20)) {
-		/* Reset PHY */
-		if ((ethernet_phy_reset (port_num)) != true) {
-			printf ("$$ Warnning: No link on port %d \n",
-				port_num);
-			return 0;
-		} else {
-			eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
-			if (!(phy_reg_data & 0x20)) {
-				printf ("### Error: Phy is not active\n");
-				return 0;
-			}
-		}
-	} else {
-		mv64360_eth_print_phy_status (dev);
-	}
-	port_private->eth_running = MAGIC_ETH_RUNNING;
-	return 1;
-}
-
-
-static int mv64360_eth_free_tx_rings (struct eth_device *dev)
-{
-	unsigned int queue;
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	unsigned int port_num;
-	volatile ETH_TX_DESC *p_tx_curr_desc;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-	/* Stop Tx Queues */
-	MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
-		      0x0000ff00);
-
-	/* Free TX rings */
-	DP (printf ("Clearing previously allocated TX queues... "));
-	for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
-		/* Free on TX rings */
-		for (p_tx_curr_desc =
-		     ethernet_private->p_tx_desc_area_base[queue];
-		     ((unsigned int) p_tx_curr_desc <= (unsigned int)
-		      ethernet_private->p_tx_desc_area_base[queue] +
-		      ethernet_private->tx_desc_area_size[queue]);
-		     p_tx_curr_desc =
-		     (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
-				      TX_DESC_ALIGNED_SIZE)) {
-			/* this is inside for loop */
-			if (p_tx_curr_desc->return_info != 0) {
-				p_tx_curr_desc->return_info = 0;
-				DP (printf ("freed\n"));
-			}
-		}
-		DP (printf ("Done\n"));
-	}
-	return 0;
-}
-
-static int mv64360_eth_free_rx_rings (struct eth_device *dev)
-{
-	unsigned int queue;
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	unsigned int port_num;
-	volatile ETH_RX_DESC *p_rx_curr_desc;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-
-	/* Stop RX Queues */
-	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
-		      0x0000ff00);
-
-	/* Free RX rings */
-	DP (printf ("Clearing previously allocated RX queues... "));
-	for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
-		/* Free preallocated skb's on RX rings */
-		for (p_rx_curr_desc =
-		     ethernet_private->p_rx_desc_area_base[queue];
-		     (((unsigned int) p_rx_curr_desc <
-		       ((unsigned int) ethernet_private->
-			p_rx_desc_area_base[queue] +
-			ethernet_private->rx_desc_area_size[queue])));
-		     p_rx_curr_desc =
-		     (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
-				      RX_DESC_ALIGNED_SIZE)) {
-			if (p_rx_curr_desc->return_info != 0) {
-				p_rx_curr_desc->return_info = 0;
-				DP (printf ("freed\n"));
-			}
-		}
-		DP (printf ("Done\n"));
-	}
-	return 0;
-}
-
-/**********************************************************************
- * mv64360_eth_stop
- *
- * This function is used when closing the network device.
- * It updates the hardware,
- * release all memory that holds buffers and descriptors and release the IRQ.
- * Input : a pointer to the device structure
- * Output : zero if success , nonzero if fails
- *********************************************************************/
-
-int mv64360_eth_stop (struct eth_device *dev)
-{
-	/* Disable all gigE address decoder */
-	MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
-	DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
-	mv64360_eth_real_stop (dev);
-
-	return 0;
-};
-
-/* Helper function for mv64360_eth_stop */
-
-static int mv64360_eth_real_stop (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	unsigned int port_num;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-
-	mv64360_eth_free_tx_rings (dev);
-	mv64360_eth_free_rx_rings (dev);
-
-	eth_port_reset (ethernet_private->port_num);
-	/* Disable ethernet port interrupts */
-	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
-	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
-	/* Mask RX buffer and TX end interrupt */
-	MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0);
-	/* Mask phy and link status changes interrupts */
-	MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
-	MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH,
-			   BIT0 << port_num);
-	/* Print Network statistics */
-#ifndef  UPDATE_STATS_BY_SOFTWARE
-	/*
-	 * Print statistics (only if ethernet is running),
-	 * then zero all the stats fields in memory
-	 */
-	if (port_private->eth_running == MAGIC_ETH_RUNNING) {
-		port_private->eth_running = 0;
-		mv64360_eth_print_stat (dev);
-	}
-	memset (port_private->stats, 0, sizeof (struct net_device_stats));
-#endif
-	DP (printf ("\nEthernet stopped ... \n"));
-	return 0;
-}
-
-
-/**********************************************************************
- * mv64360_eth_start_xmit
- *
- * This function is queues a packet in the Tx descriptor for
- * required port.
- *
- * Input : skb - a pointer to socket buffer
- *         dev - a pointer to the required port
- *
- * Output : zero upon success
- **********************************************************************/
-
-int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
-		      int dataSize)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	PKT_INFO pkt_info;
-	ETH_FUNC_RET_STATUS status;
-	struct net_device_stats *stats;
-	ETH_FUNC_RET_STATUS release_result;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-
-	stats = port_private->stats;
-
-	/* Update packet info data structure */
-	pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;	/* DMA owned, first last */
-	pkt_info.byte_cnt = dataSize;
-	pkt_info.buf_ptr = (unsigned int) dataPtr;
-	pkt_info.return_info = 0;
-
-	status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
-	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
-		printf ("Error on transmitting packet ..");
-		if (status == ETH_QUEUE_FULL)
-			printf ("ETH Queue is full. \n");
-		if (status == ETH_QUEUE_LAST_RESOURCE)
-			printf ("ETH Queue: using last available resource. \n");
-		goto error;
-	}
-
-	/* Update statistics and start of transmittion time */
-	stats->tx_bytes += dataSize;
-	stats->tx_packets++;
-
-	/* Check if packet(s) is(are) transmitted correctly (release everything) */
-	do {
-		release_result =
-			eth_tx_return_desc (ethernet_private, ETH_Q0,
-					    &pkt_info);
-		switch (release_result) {
-		case ETH_OK:
-			DP (printf ("descriptor released\n"));
-			if (pkt_info.cmd_sts & BIT0) {
-				printf ("Error in TX\n");
-				stats->tx_errors++;
-
-			}
-			break;
-		case ETH_RETRY:
-			DP (printf ("transmission still in process\n"));
-			break;
-
-		case ETH_ERROR:
-			printf ("routine can not access Tx desc ring\n");
-			break;
-
-		case ETH_END_OF_JOB:
-			DP (printf ("the routine has nothing to release\n"));
-			break;
-		default:	/* should not happen */
-			break;
-		}
-	} while (release_result == ETH_OK);
-
-
-	return 0;		/* success */
-      error:
-	return 1;		/* Failed - higher layers will free the skb */
-}
-
-/**********************************************************************
- * mv64360_eth_receive
- *
- * This function is forward packets that are received from the port's
- * queues toward kernel core or FastRoute them to another interface.
- *
- * Input : dev - a pointer to the required interface
- *         max - maximum number to receive (0 means unlimted)
- *
- * Output : number of served packets
- **********************************************************************/
-
-int mv64360_eth_receive (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	PKT_INFO pkt_info;
-	struct net_device_stats *stats;
-
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-	stats = port_private->stats;
-
-	while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
-		ETH_OK)) {
-
-#ifdef DEBUG_MV_ETH
-		if (pkt_info.byte_cnt != 0) {
-			printf ("%s: Received %d byte Packet @ 0x%x\n",
-				__FUNCTION__, pkt_info.byte_cnt,
-				pkt_info.buf_ptr);
-		}
-#endif
-		/* Update statistics. Note byte count includes 4 byte CRC count */
-		stats->rx_packets++;
-		stats->rx_bytes += pkt_info.byte_cnt;
-
-		/*
-		 * In case received a packet without first / last bits on OR the error
-		 * summary bit is on, the packets needs to be dropeed.
-		 */
-		if (((pkt_info.
-		      cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
-		     (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
-		    || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
-			stats->rx_dropped++;
-
-			printf ("Received packet spread on multiple descriptors\n");
-
-			/* Is this caused by an error ? */
-			if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
-				stats->rx_errors++;
-			}
-
-			/* free these descriptors again without forwarding them to the higher layers */
-			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
-			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
-
-			if (eth_rx_return_buff
-			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
-				printf ("Error while returning the RX Desc to Ring\n");
-			} else {
-				DP (printf ("RX Desc returned to Ring\n"));
-			}
-			/* /free these descriptors again */
-		} else {
-
-/* !!! call higher layer processing */
-#ifdef DEBUG_MV_ETH
-			printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
-#endif
-			/* let the upper layer handle the packet */
-			NetReceive ((uchar *) pkt_info.buf_ptr,
-				    (int) pkt_info.byte_cnt);
-
-/* **************************************************************** */
-/* free descriptor  */
-			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
-			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
-			DP (printf
-			    ("RX: pkt_info.buf_ptr =	%x\n",
-			     pkt_info.buf_ptr));
-			if (eth_rx_return_buff
-			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
-				printf ("Error while returning the RX Desc to Ring\n");
-			} else {
-				DP (printf ("RX Desc returned to Ring\n"));
-			}
-
-/* **************************************************************** */
-
-		}
-	}
-	mv64360_eth_get_stats (dev);	/* update statistics */
-	return 1;
-}
-
-/**********************************************************************
- * mv64360_eth_get_stats
- *
- * Returns a pointer to the interface statistics.
- *
- * Input : dev - a pointer to the required interface
- *
- * Output : a pointer to the interface's statistics
- **********************************************************************/
-
-static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-
-	mv64360_eth_update_stat (dev);
-
-	return port_private->stats;
-}
-
-
-/**********************************************************************
- * mv64360_eth_update_stat
- *
- * Update the statistics structure in the private data structure
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64360_eth_update_stat (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	struct net_device_stats *stats;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-	stats = port_private->stats;
-
-	/* These are false updates */
-	stats->rx_packets += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_FRAMES_RECEIVED);
-	stats->tx_packets += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_FRAMES_SENT);
-	stats->rx_bytes += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
-	/*
-	 * Ideally this should be as follows -
-	 *
-	 *   stats->rx_bytes   += stats->rx_bytes +
-	 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
-	 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
-	 *
-	 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
-	 * is just a dummy read for proper work of the GigE port
-	 */
-	(void)eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
-	stats->tx_bytes += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_OCTETS_SENT_LOW);
-	(void)eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_OCTETS_SENT_HIGH);
-	stats->rx_errors += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_MAC_RECEIVE_ERROR);
-
-	/* Rx dropped is for received packet with CRC error */
-	stats->rx_dropped +=
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_BAD_CRC_EVENT);
-	stats->multicast += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_MULTICAST_FRAMES_RECEIVED);
-	stats->collisions +=
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_COLLISION) +
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_LATE_COLLISION);
-	/* detailed rx errors */
-	stats->rx_length_errors +=
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_UNDERSIZE_RECEIVED)
-		+
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_OVERSIZE_RECEIVED);
-	/* detailed tx errors */
-}
-
-#ifndef  UPDATE_STATS_BY_SOFTWARE
-/**********************************************************************
- * mv64360_eth_print_stat
- *
- * Update the statistics structure in the private data structure
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64360_eth_print_stat (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64360_eth_priv *port_private;
-	struct net_device_stats *stats;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64360_eth_priv *) ethernet_private->port_private;
-	stats = port_private->stats;
-
-	/* These are false updates */
-	printf ("\n### Network statistics: ###\n");
-	printf ("--------------------------\n");
-	printf (" Packets received:		%ld\n", stats->rx_packets);
-	printf (" Packets send:			%ld\n", stats->tx_packets);
-	printf (" Received bytes:		%ld\n", stats->rx_bytes);
-	printf (" Send bytes:			%ld\n", stats->tx_bytes);
-	if (stats->rx_errors != 0)
-		printf (" Rx Errors:			%ld\n",
-			stats->rx_errors);
-	if (stats->rx_dropped != 0)
-		printf (" Rx dropped (CRC Errors):	%ld\n",
-			stats->rx_dropped);
-	if (stats->multicast != 0)
-		printf (" Rx mulicast frames:		%ld\n",
-			stats->multicast);
-	if (stats->collisions != 0)
-		printf (" No. of collisions:		%ld\n",
-			stats->collisions);
-	if (stats->rx_length_errors != 0)
-		printf (" Rx length errors:		%ld\n",
-			stats->rx_length_errors);
-}
-#endif
-
-/**************************************************************************
- *network_start - Network Kick Off Routine UBoot
- *Inputs :
- *Outputs :
- **************************************************************************/
-
-bool db64360_eth_start (struct eth_device *dev)
-{
-	return (mv64360_eth_open (dev));	/* calls real open */
-}
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The second part is the low level driver of the gigE ethernet ports.   *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-/*
- * based on Linux code
- * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- */
-
-/********************************************************************************
- * Marvell's Gigabit Ethernet controller low level driver
- *
- * DESCRIPTION:
- *       This file introduce low level API to Marvell's Gigabit Ethernet
- *		controller. This Gigabit Ethernet Controller driver API controls
- *		1) Operations (i.e. port init, start, reset etc').
- *		2) Data flow (i.e. port send, receive etc').
- *		Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
- *		struct.
- *		This struct includes user configuration information as well as
- *		driver internal data needed for its operations.
- *
- *		Supported Features:
- *		- This low level driver is OS independent. Allocating memory for
- *		  the descriptor rings and buffers are not within the scope of
- *		  this driver.
- *		- The user is free from Rx/Tx queue managing.
- *		- This low level driver introduce functionality API that enable
- *		  the to operate Marvell's Gigabit Ethernet Controller in a
- *		  convenient way.
- *		- Simple Gigabit Ethernet port operation API.
- *		- Simple Gigabit Ethernet port data flow API.
- *		- Data flow and operation API support per queue functionality.
- *		- Support cached descriptors for better performance.
- *		- Enable access to all four DRAM banks and internal SRAM memory
- *		  spaces.
- *		- PHY access and control API.
- *		- Port control register configuration API.
- *		- Full control over Unicast and Multicast MAC configurations.
- *
- *		Operation flow:
- *
- *		Initialization phase
- *		This phase complete the initialization of the ETH_PORT_INFO
- *		struct.
- *		User information regarding port configuration has to be set
- *		prior to calling the port initialization routine. For example,
- *		the user has to assign the port_phy_addr field which is board
- *		depended parameter.
- *		In this phase any port Tx/Rx activity is halted, MIB counters
- *		are cleared, PHY address is set according to user parameter and
- *		access to DRAM and internal SRAM memory spaces.
- *
- *		Driver ring initialization
- *		Allocating memory for the descriptor rings and buffers is not
- *		within the scope of this driver. Thus, the user is required to
- *		allocate memory for the descriptors ring and buffers. Those
- *		memory parameters are used by the Rx and Tx ring initialization
- *		routines in order to curve the descriptor linked list in a form
- *		of a ring.
- *		Note: Pay special attention to alignment issues when using
- *		cached descriptors/buffers. In this phase the driver store
- *		information in the ETH_PORT_INFO struct regarding each queue
- *		ring.
- *
- *		Driver start
- *		This phase prepares the Ethernet port for Rx and Tx activity.
- *		It uses the information stored in the ETH_PORT_INFO struct to
- *		initialize the various port registers.
- *
- *		Data flow:
- *		All packet references to/from the driver are done using PKT_INFO
- *		struct.
- *		This struct is a unified struct used with Rx and Tx operations.
- *		This way the user is not required to be familiar with neither
- *		Tx nor Rx descriptors structures.
- *		The driver's descriptors rings are management by indexes.
- *		Those indexes controls the ring resources and used to indicate
- *		a SW resource error:
- *		'current'
- *		This index points to the current available resource for use. For
- *		example in Rx process this index will point to the descriptor
- *		that will be passed to the user upon calling the receive routine.
- *		In Tx process, this index will point to the descriptor
- *		that will be assigned with the user packet info and transmitted.
- *		'used'
- *		This index points to the descriptor that need to restore its
- *		resources. For example in Rx process, using the Rx buffer return
- *		API will attach the buffer returned in packet info to the
- *		descriptor pointed by 'used'. In Tx process, using the Tx
- *		descriptor return will merely return the user packet info with
- *		the command status of  the transmitted buffer pointed by the
- *		'used' index. Nevertheless, it is essential to use this routine
- *		to update the 'used' index.
- *		'first'
- *		This index supports Tx Scatter-Gather. It points to the first
- *		descriptor of a packet assembled of multiple buffers. For example
- *		when in middle of Such packet we have a Tx resource error the
- *		'curr' index get the value of 'first' to indicate that the ring
- *		returned to its state before trying to transmit this packet.
- *
- *		Receive operation:
- *		The eth_port_receive API set the packet information struct,
- *		passed by the caller, with received information from the
- *		'current' SDMA descriptor.
- *		It is the user responsibility to return this resource back
- *		to the Rx descriptor ring to enable the reuse of this source.
- *		Return Rx resource is done using the eth_rx_return_buff API.
- *
- *		Transmit operation:
- *		The eth_port_send API supports Scatter-Gather which enables to
- *		send a packet spanned over multiple buffers. This means that
- *		for each packet info structure given by the user and put into
- *		the Tx descriptors ring, will be transmitted only if the 'LAST'
- *		bit will be set in the packet info command status field. This
- *		API also consider restriction regarding buffer alignments and
- *		sizes.
- *		The user must return a Tx resource after ensuring the buffer
- *		has been transmitted to enable the Tx ring indexes to update.
- *
- *		BOARD LAYOUT
- *		This device is on-board.  No jumper diagram is necessary.
- *
- *		EXTERNAL INTERFACE
- *
- *       Prior to calling the initialization routine eth_port_init() the user
- *	 must set the following fields under ETH_PORT_INFO struct:
- *       port_num             User Ethernet port number.
- *       port_phy_addr		    User PHY address of Ethernet port.
- *       port_mac_addr[6]	    User defined port MAC address.
- *       port_config          User port configuration value.
- *       port_config_extend    User port config extend value.
- *       port_sdma_config      User port SDMA config value.
- *       port_serial_control   User port serial control value.
- *       *port_virt_to_phys ()  User function to cast virtual addr to CPU bus addr.
- *       *port_private        User scratch pad for user specific data structures.
- *
- *       This driver introduce a set of default values:
- *       PORT_CONFIG_VALUE           Default port configuration value
- *       PORT_CONFIG_EXTEND_VALUE    Default port extend configuration value
- *       PORT_SDMA_CONFIG_VALUE      Default sdma control value
- *       PORT_SERIAL_CONTROL_VALUE   Default port serial control value
- *
- *		This driver data flow is done using the PKT_INFO struct which is
- *		a unified struct for Rx and Tx operations:
- *		byte_cnt	Tx/Rx descriptor buffer byte count.
- *		l4i_chk		CPU provided TCP Checksum. For Tx operation only.
- *		cmd_sts		Tx/Rx descriptor command status.
- *		buf_ptr		Tx/Rx descriptor buffer pointer.
- *		return_info	Tx/Rx user resource return information.
- *
- *
- *		EXTERNAL SUPPORT REQUIREMENTS
- *
- *		This driver requires the following external support:
- *
- *		D_CACHE_FLUSH_LINE (address, address offset)
- *
- *		This macro applies assembly code to flush and invalidate cache
- *		line.
- *		address        - address base.
- *		address offset - address offset
- *
- *
- *		CPU_PIPE_FLUSH
- *
- *		This macro applies assembly code to flush the CPU pipeline.
- *
- *******************************************************************************/
-/* includes */
-
-/* defines */
-/* SDMA command macros */
-#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
- MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
-
-#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
- MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
- (1 << (8 + tx_queue)))
-
-#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
-MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
-
-#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
-MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
-
-#define CURR_RFD_GET(p_curr_desc, queue) \
- ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
-
-#define CURR_RFD_SET(p_curr_desc, queue) \
- (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
-
-#define USED_RFD_GET(p_used_desc, queue) \
- ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
-
-#define USED_RFD_SET(p_used_desc, queue)\
-(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
-
-
-#define CURR_TFD_GET(p_curr_desc, queue) \
- ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
-
-#define CURR_TFD_SET(p_curr_desc, queue) \
- (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
-
-#define USED_TFD_GET(p_used_desc, queue) \
- ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
-
-#define USED_TFD_SET(p_used_desc, queue) \
- (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
-
-#define FIRST_TFD_GET(p_first_desc, queue) \
- ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
-
-#define FIRST_TFD_SET(p_first_desc, queue) \
- (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
-
-
-/* Macros that save access to desc in order to find next desc pointer  */
-#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
-
-#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
-
-#define LINK_UP_TIMEOUT		100000
-#define PHY_BUSY_TIMEOUT    10000000
-
-/* locals */
-
-/* PHY routines */
-static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
-static int ethernet_phy_get (ETH_PORT eth_port_num);
-
-/* Ethernet Port routines */
-static void eth_set_access_control (ETH_PORT eth_port_num,
-				    ETH_WIN_PARAM * param);
-static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
-			      ETH_QUEUE queue, int option);
-#if 0				/* FIXME */
-static bool eth_port_smc_addr (ETH_PORT eth_port_num,
-			       unsigned char mc_byte,
-			       ETH_QUEUE queue, int option);
-static bool eth_port_omc_addr (ETH_PORT eth_port_num,
-			       unsigned char crc8,
-			       ETH_QUEUE queue, int option);
-#endif
-
-static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
-			int byte_count);
-
-void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
-
-
-typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
-u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
-{
-	u32 result = 0;
-	u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
-
-	if (enable & (1 << bank))
-		return 0;
-	if (bank == BANK0)
-		result = MV_REG_READ (MV64360_CS_0_BASE_ADDR);
-	if (bank == BANK1)
-		result = MV_REG_READ (MV64360_CS_1_BASE_ADDR);
-	if (bank == BANK2)
-		result = MV_REG_READ (MV64360_CS_2_BASE_ADDR);
-	if (bank == BANK3)
-		result = MV_REG_READ (MV64360_CS_3_BASE_ADDR);
-	result &= 0x0000ffff;
-	result = result << 16;
-	return result;
-}
-
-u32 mv_get_dram_bank_size (MEMORY_BANK bank)
-{
-	u32 result = 0;
-	u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
-
-	if (enable & (1 << bank))
-		return 0;
-	if (bank == BANK0)
-		result = MV_REG_READ (MV64360_CS_0_SIZE);
-	if (bank == BANK1)
-		result = MV_REG_READ (MV64360_CS_1_SIZE);
-	if (bank == BANK2)
-		result = MV_REG_READ (MV64360_CS_2_SIZE);
-	if (bank == BANK3)
-		result = MV_REG_READ (MV64360_CS_3_SIZE);
-	result += 1;
-	result &= 0x0000ffff;
-	result = result << 16;
-	return result;
-}
-
-u32 mv_get_internal_sram_base (void)
-{
-	u32 result;
-
-	result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR);
-	result &= 0x0000ffff;
-	result = result << 16;
-	return result;
-}
-
-/*******************************************************************************
-* eth_port_init - Initialize the Ethernet port driver
-*
-* DESCRIPTION:
-*       This function prepares the ethernet port to start its activity:
-*       1) Completes the ethernet port driver struct initialization toward port
-*           start routine.
-*       2) Resets the device to a quiescent state in case of warm reboot.
-*       3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
-*       4) Clean MAC tables. The reset status of those tables is unknown.
-*       5) Set PHY address.
-*       Note: Call this routine prior to eth_port_start routine and after setting
-*       user values in the user fields of Ethernet port control struct (i.e.
-*       port_phy_addr).
-*
-* INPUT:
-*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
-*
-* OUTPUT:
-*       See description.
-*
-* RETURN:
-*       None.
-*
-*******************************************************************************/
-static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
-{
-	int queue;
-	ETH_WIN_PARAM win_param;
-
-	p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
-	p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
-	p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
-	p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
-
-	p_eth_port_ctrl->port_rx_queue_command = 0;
-	p_eth_port_ctrl->port_tx_queue_command = 0;
-
-	/* Zero out SW structs */
-	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
-		CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
-		USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
-		p_eth_port_ctrl->rx_resource_err[queue] = false;
-	}
-
-	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
-		CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
-		USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
-		FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
-		p_eth_port_ctrl->tx_resource_err[queue] = false;
-	}
-
-	eth_port_reset (p_eth_port_ctrl->port_num);
-
-	/* Set access parameters for DRAM bank 0 */
-	win_param.win = ETH_WIN0;	/* Use Ethernet window 0 */
-	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR  */
-	win_param.attributes = EBAR_ATTR_DRAM_CS0;	/* Enable DRAM bank   */
-#ifndef CONFIG_NOT_COHERENT_CACHE
-	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
-	win_param.high_addr = 0;
-	/* Get bank base */
-	win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
-	win_param.size = mv_get_dram_bank_size (BANK0);	/* Get bank size */
-	if (win_param.size == 0)
-		win_param.enable = 0;
-	else
-		win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	/* Set access parameters for DRAM bank 1 */
-	win_param.win = ETH_WIN1;	/* Use Ethernet window 1 */
-	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
-	win_param.attributes = EBAR_ATTR_DRAM_CS1;	/* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
-	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
-	win_param.high_addr = 0;
-	/* Get bank base */
-	win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
-	win_param.size = mv_get_dram_bank_size (BANK1);	/* Get bank size */
-	if (win_param.size == 0)
-		win_param.enable = 0;
-	else
-		win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	/* Set access parameters for DRAM bank 2 */
-	win_param.win = ETH_WIN2;	/* Use Ethernet window 2 */
-	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
-	win_param.attributes = EBAR_ATTR_DRAM_CS2;	/* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
-	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
-	win_param.high_addr = 0;
-	/* Get bank base */
-	win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
-	win_param.size = mv_get_dram_bank_size (BANK2);	/* Get bank size */
-	if (win_param.size == 0)
-		win_param.enable = 0;
-	else
-		win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	/* Set access parameters for DRAM bank 3 */
-	win_param.win = ETH_WIN3;	/* Use Ethernet window 3 */
-	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
-	win_param.attributes = EBAR_ATTR_DRAM_CS3;	/* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
-	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
-	win_param.high_addr = 0;
-	/* Get bank base */
-	win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
-	win_param.size = mv_get_dram_bank_size (BANK3);	/* Get bank size */
-	if (win_param.size == 0)
-		win_param.enable = 0;
-	else
-		win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	/* Set access parameters for Internal SRAM */
-	win_param.win = ETH_WIN4;	/* Use Ethernet window 0 */
-	win_param.target = EBAR_TARGET_CBS;	/* Target - Internal SRAM */
-	win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
-	win_param.high_addr = 0;
-	win_param.base_addr = mv_get_internal_sram_base ();	/* Get base addr */
-	win_param.size = MV64360_INTERNAL_SRAM_SIZE;	/* Get bank size */
-	win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
-
-	ethernet_phy_set (p_eth_port_ctrl->port_num,
-			  p_eth_port_ctrl->port_phy_addr);
-
-	return;
-
-}
-
-/*******************************************************************************
-* eth_port_start - Start the Ethernet port activity.
-*
-* DESCRIPTION:
-*       This routine prepares the Ethernet port for Rx and Tx activity:
-*       1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
-*           has been initialized a descriptor's ring (using ether_init_tx_desc_ring
-*           for Tx and ether_init_rx_desc_ring for Rx)
-*       2. Initialize and enable the Ethernet configuration port by writing to
-*           the port's configuration and command registers.
-*       3. Initialize and enable the SDMA by writing to the SDMA's
-*    configuration and command registers.
-*       After completing these steps, the ethernet port SDMA can starts to
-*       perform Rx and Tx activities.
-*
-*       Note: Each Rx and Tx queue descriptor's list must be initialized prior
-*       to calling this function (use ether_init_tx_desc_ring for Tx queues and
-*       ether_init_rx_desc_ring for Rx queues).
-*
-* INPUT:
-*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
-*
-* OUTPUT:
-*       Ethernet port is ready to receive and transmit.
-*
-* RETURN:
-*       false if the port PHY is not up.
-*       true otherwise.
-*
-*******************************************************************************/
-static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
-{
-	int queue;
-	volatile ETH_TX_DESC *p_tx_curr_desc;
-	volatile ETH_RX_DESC *p_rx_curr_desc;
-	unsigned int phy_reg_data;
-	ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
-
-
-	/* Assignment of Tx CTRP of given queue */
-	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
-		CURR_TFD_GET (p_tx_curr_desc, queue);
-		MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
-			       (eth_port_num)
-			       + (4 * queue)),
-			      ((unsigned int) p_tx_curr_desc));
-
-	}
-
-	/* Assignment of Rx CRDP of given queue */
-	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
-		CURR_RFD_GET (p_rx_curr_desc, queue);
-		MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
-			       (eth_port_num)
-			       + (4 * queue)),
-			      ((unsigned int) p_rx_curr_desc));
-
-		if (p_rx_curr_desc != NULL)
-			/* Add the assigned Ethernet address to the port's address table */
-			eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
-					      p_eth_port_ctrl->port_mac_addr,
-					      queue);
-	}
-
-	/* Assign port configuration and command. */
-	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
-		      p_eth_port_ctrl->port_config);
-
-	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
-		      p_eth_port_ctrl->port_config_extend);
-
-	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
-		      p_eth_port_ctrl->port_serial_control);
-
-	MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
-			 ETH_SERIAL_PORT_ENABLE);
-
-	/* Assign port SDMA configuration */
-	MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
-		      p_eth_port_ctrl->port_sdma_config);
-
-	MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
-		      (eth_port_num), 0x3fffffff);
-	MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
-		      (eth_port_num), 0x03fffcff);
-	/* Turn off the port/queue bandwidth limitation */
-	MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
-
-	/* Enable port Rx. */
-	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
-		      p_eth_port_ctrl->port_rx_queue_command);
-
-	/* Check if link is up */
-	eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
-
-	if (!(phy_reg_data & 0x20))
-		return false;
-
-	return true;
-}
-
-/*******************************************************************************
-* eth_port_uc_addr_set - This function Set the port Unicast address.
-*
-* DESCRIPTION:
-*		This function Set the port Ethernet MAC address.
-*
-* INPUT:
-*	ETH_PORT eth_port_num     Port number.
-*	char *        p_addr		Address to be set
-*	ETH_QUEUE	  queue		Rx queue number for this MAC address.
-*
-* OUTPUT:
-*	Set MAC address low and high registers. also calls eth_port_uc_addr()
-*       To set the unicast table with the proper information.
-*
-* RETURN:
-*	N/A.
-*
-*******************************************************************************/
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
-				  unsigned char *p_addr, ETH_QUEUE queue)
-{
-	unsigned int mac_h;
-	unsigned int mac_l;
-
-	mac_l = (p_addr[4] << 8) | (p_addr[5]);
-	mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
-		(p_addr[2] << 8) | (p_addr[3] << 0);
-
-	MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
-	MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
-
-	/* Accept frames of this address */
-	eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
-
-	return;
-}
-
-/*******************************************************************************
-* eth_port_uc_addr - This function Set the port unicast address table
-*
-* DESCRIPTION:
-*	This function locates the proper entry in the Unicast table for the
-*	specified MAC nibble and sets its properties according to function
-*	parameters.
-*
-* INPUT:
-*	ETH_PORT	eth_port_num      Port number.
-*	unsigned char uc_nibble		Unicast MAC Address last nibble.
-*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
-*	int			option      0 = Add, 1 = remove address.
-*
-* OUTPUT:
-*	This function add/removes MAC addresses from the port unicast address
-*	table.
-*
-* RETURN:
-*	true is output succeeded.
-*	false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_uc_addr (ETH_PORT eth_port_num,
-			      unsigned char uc_nibble,
-			      ETH_QUEUE queue, int option)
-{
-	unsigned int unicast_reg;
-	unsigned int tbl_offset;
-	unsigned int reg_offset;
-
-	/* Locate the Unicast table entry */
-	uc_nibble = (0xf & uc_nibble);
-	tbl_offset = (uc_nibble / 4) * 4;	/* Register offset from unicast table base */
-	reg_offset = uc_nibble % 4;	/* Entry offset within the above register */
-
-	switch (option) {
-	case REJECT_MAC_ADDR:
-		/* Clear accepts frame bit at specified unicast DA table entry */
-		unicast_reg =
-			MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
-				      (eth_port_num)
-				      + tbl_offset));
-
-		unicast_reg &= (0x0E << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
-			       (eth_port_num)
-			       + tbl_offset), unicast_reg);
-		break;
-
-	case ACCEPT_MAC_ADDR:
-		/* Set accepts frame bit at unicast DA filter table entry */
-		unicast_reg =
-			MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
-				      (eth_port_num)
-				      + tbl_offset));
-
-		unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
-			       (eth_port_num)
-			       + tbl_offset), unicast_reg);
-
-		break;
-
-	default:
-		return false;
-	}
-	return true;
-}
-
-#if 0				/* FIXME */
-/*******************************************************************************
-* eth_port_mc_addr - Multicast address settings.
-*
-* DESCRIPTION:
-*	This API controls the MV device MAC multicast support.
-*	The MV device supports multicast using two tables:
-*	1) Special Multicast Table for MAC addresses of the form
-*	   0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
-*	   The MAC DA[7:0] bits are used as a pointer to the Special Multicast
-*	   Table entries in the DA-Filter table.
-*	   In this case, the function calls eth_port_smc_addr() routine to set the
-*	   Special Multicast Table.
-*	2) Other Multicast Table for multicast of another type. A CRC-8bit
-*	   is used as an index to the Other Multicast Table entries in the
-*	   DA-Filter table.
-*	   In this case, the function calculates the CRC-8bit value and calls
-*	   eth_port_omc_addr() routine to set the Other Multicast Table.
-* INPUT:
-*	ETH_PORT	eth_port_num      Port number.
-*	unsigned char	*p_addr		Unicast MAC Address.
-*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
-*	int			option      0 = Add, 1 = remove address.
-*
-* OUTPUT:
-*	See description.
-*
-* RETURN:
-*	true is output succeeded.
-*	false if add_address_table_entry( ) failed.
-*
-*******************************************************************************/
-static void eth_port_mc_addr (ETH_PORT eth_port_num,
-			      unsigned char *p_addr,
-			      ETH_QUEUE queue, int option)
-{
-	unsigned int mac_h;
-	unsigned int mac_l;
-	unsigned char crc_result = 0;
-	int mac_array[48];
-	int crc[8];
-	int i;
-
-
-	if ((p_addr[0] == 0x01) &&
-	    (p_addr[1] == 0x00) &&
-	    (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
-
-		eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
-	else {
-		/* Calculate CRC-8 out of the given address */
-		mac_h = (p_addr[0] << 8) | (p_addr[1]);
-		mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
-			(p_addr[4] << 8) | (p_addr[5] << 0);
-
-		for (i = 0; i < 32; i++)
-			mac_array[i] = (mac_l >> i) & 0x1;
-		for (i = 32; i < 48; i++)
-			mac_array[i] = (mac_h >> (i - 32)) & 0x1;
-
-
-		crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
-			mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
-			mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
-			mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
-			mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
-			mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
-			mac_array[6] ^ mac_array[0];
-
-		crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
-			mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
-			mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
-			mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
-			mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
-			mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
-			mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
-			mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
-			mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
-			mac_array[0];
-
-		crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
-			mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
-			mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
-			mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
-			mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
-			mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
-			mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
-			mac_array[2] ^ mac_array[1] ^ mac_array[0];
-
-		crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
-			mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
-			mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
-			mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
-			mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
-			mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
-			mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
-			mac_array[2] ^ mac_array[1];
-
-		crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
-			mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
-			mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
-			mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
-			mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
-			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
-			mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
-			mac_array[2];
-
-		crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
-			mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
-			mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
-			mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
-			mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
-			mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
-			mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
-			mac_array[3];
-
-		crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
-			mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
-			mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
-			mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
-			mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
-			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
-			mac_array[6] ^ mac_array[5] ^ mac_array[4];
-
-		crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
-			mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
-			mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
-			mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
-			mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
-			mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
-			mac_array[6] ^ mac_array[5];
-
-		for (i = 0; i < 8; i++)
-			crc_result = crc_result | (crc[i] << i);
-
-		eth_port_omc_addr (eth_port_num, crc_result, queue, option);
-	}
-	return;
-}
-
-/*******************************************************************************
-* eth_port_smc_addr - Special Multicast address settings.
-*
-* DESCRIPTION:
-*	This routine controls the MV device special MAC multicast support.
-*	The Special Multicast Table for MAC addresses supports MAC of the form
-*	0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
-*	The MAC DA[7:0] bits are used as a pointer to the Special Multicast
-*	Table entries in the DA-Filter table.
-*	This function set the Special Multicast Table appropriate entry
-*	according to the argument given.
-*
-* INPUT:
-*	ETH_PORT	eth_port_num      Port number.
-*	unsigned char	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
-*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
-*	int			option      0 = Add, 1 = remove address.
-*
-* OUTPUT:
-*	See description.
-*
-* RETURN:
-*	true is output succeeded.
-*	false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_smc_addr (ETH_PORT eth_port_num,
-			       unsigned char mc_byte,
-			       ETH_QUEUE queue, int option)
-{
-	unsigned int smc_table_reg;
-	unsigned int tbl_offset;
-	unsigned int reg_offset;
-
-	/* Locate the SMC table entry */
-	tbl_offset = (mc_byte / 4) * 4;	/* Register offset from SMC table base */
-	reg_offset = mc_byte % 4;	/* Entry offset within the above register */
-	queue &= 0x7;
-
-	switch (option) {
-	case REJECT_MAC_ADDR:
-		/* Clear accepts frame bit at specified Special DA table entry */
-		smc_table_reg =
-			MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
-		smc_table_reg &= (0x0E << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
-		break;
-
-	case ACCEPT_MAC_ADDR:
-		/* Set accepts frame bit at specified Special DA table entry */
-		smc_table_reg =
-			MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
-		smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
-		break;
-
-	default:
-		return false;
-	}
-	return true;
-}
-
-/*******************************************************************************
-* eth_port_omc_addr - Multicast address settings.
-*
-* DESCRIPTION:
-*	This routine controls the MV device Other MAC multicast support.
-*	The Other Multicast Table is used for multicast of another type.
-*	A CRC-8bit is used as an index to the Other Multicast Table entries
-*	in the DA-Filter table.
-*	The function gets the CRC-8bit value from the calling routine and
-*      set the Other Multicast Table appropriate entry according to the
-*	CRC-8 argument given.
-*
-* INPUT:
-*	ETH_PORT	eth_port_num      Port number.
-*	unsigned char	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
-*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
-*	int			option      0 = Add, 1 = remove address.
-*
-* OUTPUT:
-*	See description.
-*
-* RETURN:
-*	true is output succeeded.
-*	false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_omc_addr (ETH_PORT eth_port_num,
-			       unsigned char crc8,
-			       ETH_QUEUE queue, int option)
-{
-	unsigned int omc_table_reg;
-	unsigned int tbl_offset;
-	unsigned int reg_offset;
-
-	/* Locate the OMC table entry */
-	tbl_offset = (crc8 / 4) * 4;	/* Register offset from OMC table base */
-	reg_offset = crc8 % 4;	/* Entry offset within the above register */
-	queue &= 0x7;
-
-	switch (option) {
-	case REJECT_MAC_ADDR:
-		/* Clear accepts frame bit at specified Other DA table entry */
-		omc_table_reg =
-			MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
-		omc_table_reg &= (0x0E << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
-		break;
-
-	case ACCEPT_MAC_ADDR:
-		/* Set accepts frame bit at specified Other DA table entry */
-		omc_table_reg =
-			MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
-		omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
-		break;
-
-	default:
-		return false;
-	}
-	return true;
-}
-#endif
-
-/*******************************************************************************
-* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
-*
-* DESCRIPTION:
-*       Go through all the DA filter tables (Unicast, Special Multicast & Other
-*       Multicast) and set each entry to 0.
-*
-* INPUT:
-*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-*       Multicast and Unicast packets are rejected.
-*
-* RETURN:
-*       None.
-*
-*******************************************************************************/
-static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
-{
-	int table_index;
-
-	/* Clear DA filter unicast table (Ex_dFUT) */
-	for (table_index = 0; table_index <= 0xC; table_index += 4)
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
-			       (eth_port_num) + table_index), 0);
-
-	for (table_index = 0; table_index <= 0xFC; table_index += 4) {
-		/* Clear DA filter special multicast table (Ex_dFSMT) */
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
-		/* Clear DA filter other multicast table (Ex_dFOMT) */
-		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
-	}
-}
-
-/*******************************************************************************
-* eth_clear_mib_counters - Clear all MIB counters
-*
-* DESCRIPTION:
-*       This function clears all MIB counters of a specific ethernet port.
-*       A read from the MIB counter will reset the counter.
-*
-* INPUT:
-*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-*       After reading all MIB counters, the counters resets.
-*
-* RETURN:
-*       MIB counter value.
-*
-*******************************************************************************/
-static void eth_clear_mib_counters (ETH_PORT eth_port_num)
-{
-	int i;
-
-	/* Perform dummy reads from MIB counters */
-	for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
-	     i += 4) {
-		(void)MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE
-				      (eth_port_num) + i));
-	}
-
-	return;
-}
-
-/*******************************************************************************
-* eth_read_mib_counter - Read a MIB counter
-*
-* DESCRIPTION:
-*       This function reads a MIB counter of a specific ethernet port.
-*       NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
-*       following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
-*       register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
-*       ETH_MIB_GOOD_OCTETS_SENT_HIGH
-*
-* INPUT:
-*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
-*       unsigned int mib_offset   MIB counter offset (use ETH_MIB_... macros).
-*
-* OUTPUT:
-*       After reading the MIB counter, the counter resets.
-*
-* RETURN:
-*       MIB counter value.
-*
-*******************************************************************************/
-unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
-				   unsigned int mib_offset)
-{
-	return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num)
-			     + mib_offset));
-}
-
-/*******************************************************************************
-* ethernet_phy_set - Set the ethernet port PHY address.
-*
-* DESCRIPTION:
-*       This routine set the ethernet port PHY address according to given
-*       parameter.
-*
-* INPUT:
-*		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-*       Set PHY Address Register with given PHY address parameter.
-*
-* RETURN:
-*       None.
-*
-*******************************************************************************/
-static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
-{
-	unsigned int reg_data;
-
-	reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
-
-	reg_data &= ~(0x1F << (5 * eth_port_num));
-	reg_data |= (phy_addr << (5 * eth_port_num));
-
-	MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data);
-
-	return;
-}
-
-/*******************************************************************************
- * ethernet_phy_get - Get the ethernet port PHY address.
- *
- * DESCRIPTION:
- *       This routine returns the given ethernet port PHY address.
- *
- * INPUT:
- *		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- *       None.
- *
- * RETURN:
- *       PHY address.
- *
- *******************************************************************************/
-static int ethernet_phy_get (ETH_PORT eth_port_num)
-{
-	unsigned int reg_data;
-
-	reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
-
-	return ((reg_data >> (5 * eth_port_num)) & 0x1f);
-}
-
-/*******************************************************************************
- * ethernet_phy_reset - Reset Ethernet port PHY.
- *
- * DESCRIPTION:
- *       This routine utilize the SMI interface to reset the ethernet port PHY.
- *       The routine waits until the link is up again or link up is timeout.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- *       The ethernet port PHY renew its link.
- *
- * RETURN:
- *       None.
- *
-*******************************************************************************/
-static bool ethernet_phy_reset (ETH_PORT eth_port_num)
-{
-	unsigned int time_out = 50;
-	unsigned int phy_reg_data;
-
-	/* Reset the PHY */
-	eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
-	phy_reg_data |= 0x8000;	/* Set bit 15 to reset the PHY */
-	eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
-
-	/* Poll on the PHY LINK */
-	do {
-		eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
-
-		if (time_out-- == 0)
-			return false;
-	}
-	while (!(phy_reg_data & 0x20));
-
-	return true;
-}
-
-/*******************************************************************************
- * eth_port_reset - Reset Ethernet port
- *
- * DESCRIPTION:
- *	This routine resets the chip by aborting any SDMA engine activity and
- *      clearing the MIB counters. The Receiver and the Transmit unit are in
- *      idle state after this command is performed and the port is disabled.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- *       Channel activity is halted.
- *
- * RETURN:
- *       None.
- *
- *******************************************************************************/
-static void eth_port_reset (ETH_PORT eth_port_num)
-{
-	unsigned int reg_data;
-
-	/* Stop Tx port activity. Check port Tx activity. */
-	reg_data =
-		MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
-			     (eth_port_num));
-
-	if (reg_data & 0xFF) {
-		/* Issue stop command for active channels only */
-		MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
-			      (eth_port_num), (reg_data << 8));
-
-		/* Wait for all Tx activity to terminate. */
-		do {
-			/* Check port cause register that all Tx queues are stopped */
-			reg_data =
-				MV_REG_READ
-				(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
-				 (eth_port_num));
-		}
-		while (reg_data & 0xFF);
-	}
-
-	/* Stop Rx port activity. Check port Rx activity. */
-	reg_data =
-		MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
-			     (eth_port_num));
-
-	if (reg_data & 0xFF) {
-		/* Issue stop command for active channels only */
-		MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
-			      (eth_port_num), (reg_data << 8));
-
-		/* Wait for all Rx activity to terminate. */
-		do {
-			/* Check port cause register that all Rx queues are stopped */
-			reg_data =
-				MV_REG_READ
-				(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
-				 (eth_port_num));
-		}
-		while (reg_data & 0xFF);
-	}
-
-
-	/* Clear all MIB counters */
-	eth_clear_mib_counters (eth_port_num);
-
-	/* Reset the Enable bit in the Configuration Register */
-	reg_data =
-		MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG
-			     (eth_port_num));
-	reg_data &= ~ETH_SERIAL_PORT_ENABLE;
-	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
-		      reg_data);
-
-	return;
-}
-
-#if 0				/* Not needed here */
-/*******************************************************************************
- * ethernet_set_config_reg - Set specified bits in configuration register.
- *
- * DESCRIPTION:
- *       This function sets specified bits in the given ethernet
- *       configuration register.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *      unsigned int    value   32 bit value.
- *
- * OUTPUT:
- *      The set bits in the value parameter are set in the configuration
- *      register.
- *
- * RETURN:
- *      None.
- *
- *******************************************************************************/
-static void ethernet_set_config_reg (ETH_PORT eth_port_num,
-				     unsigned int value)
-{
-	unsigned int eth_config_reg;
-
-	eth_config_reg =
-		MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num));
-	eth_config_reg |= value;
-	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
-		      eth_config_reg);
-
-	return;
-}
-#endif
-
-#if 0				/* FIXME */
-/*******************************************************************************
- * ethernet_reset_config_reg - Reset specified bits in configuration register.
- *
- * DESCRIPTION:
- *       This function resets specified bits in the given Ethernet
- *       configuration register.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *      unsigned int    value   32 bit value.
- *
- * OUTPUT:
- *      The set bits in the value parameter are reset in the configuration
- *      register.
- *
- * RETURN:
- *      None.
- *
- *******************************************************************************/
-static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
-				       unsigned int value)
-{
-	unsigned int eth_config_reg;
-
-	eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
-				      (eth_port_num));
-	eth_config_reg &= ~value;
-	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
-		      eth_config_reg);
-
-	return;
-}
-#endif
-
-#if 0				/* Not needed here */
-/*******************************************************************************
- * ethernet_get_config_reg - Get the port configuration register
- *
- * DESCRIPTION:
- *       This function returns the configuration register value of the given
- *       ethernet port.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- *       None.
- *
- * RETURN:
- *       Port configuration register value.
- *
- *******************************************************************************/
-static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
-{
-	unsigned int eth_config_reg;
-
-	eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
-				      (eth_port_num));
-	return eth_config_reg;
-}
-
-#endif
-
-/*******************************************************************************
- * eth_port_read_smi_reg - Read PHY registers
- *
- * DESCRIPTION:
- *       This routine utilize the SMI interface to interact with the PHY in
- *       order to perform PHY register read.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *       unsigned int   phy_reg   PHY register address offset.
- *       unsigned int   *value   Register value buffer.
- *
- * OUTPUT:
- *       Write the value of a specified PHY register into given buffer.
- *
- * RETURN:
- *       false if the PHY is busy or read data is not in valid state.
- *       true otherwise.
- *
- *******************************************************************************/
-static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
-				   unsigned int phy_reg, unsigned int *value)
-{
-	unsigned int reg_value;
-	unsigned int time_out = PHY_BUSY_TIMEOUT;
-	int phy_addr;
-
-	phy_addr = ethernet_phy_get (eth_port_num);
-/*    printf("     Phy-Port %d has addess %d  \n",eth_port_num, phy_addr );*/
-
-	/* first check that it is not busy */
-	do {
-		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
-		if (time_out-- == 0) {
-			return false;
-		}
-	}
-	while (reg_value & ETH_SMI_BUSY);
-
-	/* not busy */
-
-	MV_REG_WRITE (MV64360_ETH_SMI_REG,
-		      (phy_addr << 16) | (phy_reg << 21) |
-		      ETH_SMI_OPCODE_READ);
-
-	time_out = PHY_BUSY_TIMEOUT;	/* initialize the time out var again */
-
-	do {
-		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
-		if (time_out-- == 0) {
-			return false;
-		}
-	}
-	while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID);	/* Bit set equ operation done */
-
-	/* Wait for the data to update in the SMI register */
-#define PHY_UPDATE_TIMEOUT	10000
-	for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
-
-	reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
-
-	*value = reg_value & 0xffff;
-
-	return true;
-}
-
-/*******************************************************************************
- * eth_port_write_smi_reg - Write to PHY registers
- *
- * DESCRIPTION:
- *       This routine utilize the SMI interface to interact with the PHY in
- *       order to perform writes to PHY registers.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *      unsigned int   phy_reg   PHY register address offset.
- *      unsigned int    value   Register value.
- *
- * OUTPUT:
- *      Write the given value to the specified PHY register.
- *
- * RETURN:
- *      false if the PHY is busy.
- *      true otherwise.
- *
- *******************************************************************************/
-static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
-				    unsigned int phy_reg, unsigned int value)
-{
-	unsigned int reg_value;
-	unsigned int time_out = PHY_BUSY_TIMEOUT;
-	int phy_addr;
-
-	phy_addr = ethernet_phy_get (eth_port_num);
-
-	/* first check that it is not busy */
-	do {
-		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
-		if (time_out-- == 0) {
-			return false;
-		}
-	}
-	while (reg_value & ETH_SMI_BUSY);
-
-	/* not busy */
-	MV_REG_WRITE (MV64360_ETH_SMI_REG,
-		      (phy_addr << 16) | (phy_reg << 21) |
-		      ETH_SMI_OPCODE_WRITE | (value & 0xffff));
-	return true;
-}
-
-/*******************************************************************************
- * eth_set_access_control - Config address decode parameters for Ethernet unit
- *
- * DESCRIPTION:
- *       This function configures the address decode parameters for the Gigabit
- *       Ethernet Controller according the given parameters struct.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
- *       ETH_WIN_PARAM  *param   Address decode parameter struct.
- *
- * OUTPUT:
- *       An access window is opened using the given access parameters.
- *
- * RETURN:
- *       None.
- *
- *******************************************************************************/
-static void eth_set_access_control (ETH_PORT eth_port_num,
-				    ETH_WIN_PARAM * param)
-{
-	unsigned int access_prot_reg;
-
-	/* Set access control register */
-	access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG
-				       (eth_port_num));
-	access_prot_reg &= (~(3 << (param->win * 2)));	/* clear window permission */
-	access_prot_reg |= (param->access_ctrl << (param->win * 2));
-	MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num),
-		      access_prot_reg);
-
-	/* Set window Size reg (SR) */
-	MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 +
-		       (ETH_SIZE_REG_GAP * param->win)),
-		      (((param->size / 0x10000) - 1) << 16));
-
-	/* Set window Base address reg (BA) */
-	MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
-		      (param->target | param->attributes | param->base_addr));
-	/* High address remap reg (HARR) */
-	if (param->win < 4)
-		MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 +
-			       (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
-			      param->high_addr);
-
-	/* Base address enable reg (BARER) */
-	if (param->enable == 1)
-		MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
-				   (1 << param->win));
-	else
-		MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
-				 (1 << param->win));
-}
-
-/*******************************************************************************
- * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
- *
- * DESCRIPTION:
- *       This function prepares a Rx chained list of descriptors and packet
- *       buffers in a form of a ring. The routine must be called after port
- *       initialization routine and before port start routine.
- *       The Ethernet SDMA engine uses CPU bus addresses to access the various
- *       devices in the system (i.e. DRAM). This function uses the ethernet
- *       struct 'virtual to physical' routine (set by the user) to set the ring
- *       with physical addresses.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	rx_queue         Number of Rx queue.
- *      int			rx_desc_num       Number of Rx descriptors
- *      int			rx_buff_size      Size of Rx buffer
- *      unsigned int    rx_desc_base_addr  Rx descriptors memory area base addr.
- *      unsigned int    rx_buff_base_addr  Rx buffer memory area base addr.
- *
- * OUTPUT:
- *      The routine updates the Ethernet port control struct with information
- *      regarding the Rx descriptors and buffers.
- *
- * RETURN:
- *      false if the given descriptors memory area is not aligned according to
- *      Ethernet SDMA specifications.
- *      true otherwise.
- *
- *******************************************************************************/
-static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
-				     ETH_QUEUE rx_queue,
-				     int rx_desc_num,
-				     int rx_buff_size,
-				     unsigned int rx_desc_base_addr,
-				     unsigned int rx_buff_base_addr)
-{
-	ETH_RX_DESC *p_rx_desc;
-	ETH_RX_DESC *p_rx_prev_desc;	/* pointer to link with the last descriptor */
-	unsigned int buffer_addr;
-	int ix;			/* a counter */
-
-
-	p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
-	p_rx_prev_desc = p_rx_desc;
-	buffer_addr = rx_buff_base_addr;
-
-	/* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
-	if (rx_buff_base_addr & 0xF)
-		return false;
-
-	/* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
-	if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
-		return false;
-
-	/* Rx buffers must be 64-bit aligned.       */
-	if ((rx_buff_base_addr + rx_buff_size) & 0x7)
-		return false;
-
-	/* initialize the Rx descriptors ring */
-	for (ix = 0; ix < rx_desc_num; ix++) {
-		p_rx_desc->buf_size = rx_buff_size;
-		p_rx_desc->byte_cnt = 0x0000;
-		p_rx_desc->cmd_sts =
-			ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
-		p_rx_desc->next_desc_ptr =
-			((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
-		p_rx_desc->buf_ptr = buffer_addr;
-		p_rx_desc->return_info = 0x00000000;
-		D_CACHE_FLUSH_LINE (p_rx_desc, 0);
-		buffer_addr += rx_buff_size;
-		p_rx_prev_desc = p_rx_desc;
-		p_rx_desc = (ETH_RX_DESC *)
-			((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
-	}
-
-	/* Closing Rx descriptors ring */
-	p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
-	D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
-
-	/* Save Rx desc pointer to driver struct. */
-	CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
-	USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
-
-	p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
-		(ETH_RX_DESC *) rx_desc_base_addr;
-	p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
-		rx_desc_num * RX_DESC_ALIGNED_SIZE;
-
-	p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
-
-	return true;
-}
-
-/*******************************************************************************
- * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
- *
- * DESCRIPTION:
- *       This function prepares a Tx chained list of descriptors and packet
- *       buffers in a form of a ring. The routine must be called after port
- *       initialization routine and before port start routine.
- *       The Ethernet SDMA engine uses CPU bus addresses to access the various
- *       devices in the system (i.e. DRAM). This function uses the ethernet
- *       struct 'virtual to physical' routine (set by the user) to set the ring
- *       with physical addresses.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	tx_queue         Number of Tx queue.
- *      int			tx_desc_num       Number of Tx descriptors
- *      int			tx_buff_size      Size of Tx buffer
- *      unsigned int    tx_desc_base_addr  Tx descriptors memory area base addr.
- *      unsigned int    tx_buff_base_addr  Tx buffer memory area base addr.
- *
- * OUTPUT:
- *      The routine updates the Ethernet port control struct with information
- *      regarding the Tx descriptors and buffers.
- *
- * RETURN:
- *      false if the given descriptors memory area is not aligned according to
- *      Ethernet SDMA specifications.
- *      true otherwise.
- *
- *******************************************************************************/
-static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
-				     ETH_QUEUE tx_queue,
-				     int tx_desc_num,
-				     int tx_buff_size,
-				     unsigned int tx_desc_base_addr,
-				     unsigned int tx_buff_base_addr)
-{
-
-	ETH_TX_DESC *p_tx_desc;
-	ETH_TX_DESC *p_tx_prev_desc;
-	unsigned int buffer_addr;
-	int ix;			/* a counter */
-
-
-	/* save the first desc pointer to link with the last descriptor */
-	p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
-	p_tx_prev_desc = p_tx_desc;
-	buffer_addr = tx_buff_base_addr;
-
-	/* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
-	if (tx_buff_base_addr & 0xF)
-		return false;
-
-	/* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
-	if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
-	    || (tx_buff_size < TX_BUFFER_MIN_SIZE))
-		return false;
-
-	/* Initialize the Tx descriptors ring */
-	for (ix = 0; ix < tx_desc_num; ix++) {
-		p_tx_desc->byte_cnt = 0x0000;
-		p_tx_desc->l4i_chk = 0x0000;
-		p_tx_desc->cmd_sts = 0x00000000;
-		p_tx_desc->next_desc_ptr =
-			((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
-
-		p_tx_desc->buf_ptr = buffer_addr;
-		p_tx_desc->return_info = 0x00000000;
-		D_CACHE_FLUSH_LINE (p_tx_desc, 0);
-		buffer_addr += tx_buff_size;
-		p_tx_prev_desc = p_tx_desc;
-		p_tx_desc = (ETH_TX_DESC *)
-			((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
-
-	}
-	/* Closing Tx descriptors ring */
-	p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
-	D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
-	/* Set Tx desc pointer in driver struct. */
-	CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
-	USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
-
-	/* Init Tx ring base and size parameters */
-	p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
-		(ETH_TX_DESC *) tx_desc_base_addr;
-	p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
-		(tx_desc_num * TX_DESC_ALIGNED_SIZE);
-
-	/* Add the queue to the list of Tx queues of this port */
-	p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
-
-	return true;
-}
-
-/*******************************************************************************
- * eth_port_send - Send an Ethernet packet
- *
- * DESCRIPTION:
- *	This routine send a given packet described by p_pktinfo parameter. It
- *      supports transmitting of a packet spaned over multiple buffers. The
- *      routine updates 'curr' and 'first' indexes according to the packet
- *      segment passed to the routine. In case the packet segment is first,
- *      the 'first' index is update. In any case, the 'curr' index is updated.
- *      If the routine get into Tx resource error it assigns 'curr' index as
- *      'first'. This way the function can abort Tx process of multiple
- *      descriptors per packet.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	tx_queue         Number of Tx queue.
- *	PKT_INFO        *p_pkt_info       User packet buffer.
- *
- * OUTPUT:
- *	Tx ring 'curr' and 'first' indexes are updated.
- *
- * RETURN:
- *      ETH_QUEUE_FULL in case of Tx resource error.
- *	ETH_ERROR in case the routine can not access Tx desc ring.
- *	ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
- *      ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
-					  ETH_QUEUE tx_queue,
-					  PKT_INFO * p_pkt_info)
-{
-	volatile ETH_TX_DESC *p_tx_desc_first;
-	volatile ETH_TX_DESC *p_tx_desc_curr;
-	volatile ETH_TX_DESC *p_tx_next_desc_curr;
-	volatile ETH_TX_DESC *p_tx_desc_used;
-	unsigned int command_status;
-
-	/* Do not process Tx ring in case of Tx ring resource error */
-	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
-		return ETH_QUEUE_FULL;
-
-	/* Get the Tx Desc ring indexes */
-	CURR_TFD_GET (p_tx_desc_curr, tx_queue);
-	USED_TFD_GET (p_tx_desc_used, tx_queue);
-
-	if (p_tx_desc_curr == NULL)
-		return ETH_ERROR;
-
-	/* The following parameters are used to save readings from memory */
-	p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
-	command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
-
-	if (command_status & (ETH_TX_FIRST_DESC)) {
-		/* Update first desc */
-		FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
-		p_tx_desc_first = p_tx_desc_curr;
-	} else {
-		FIRST_TFD_GET (p_tx_desc_first, tx_queue);
-		command_status |= ETH_BUFFER_OWNED_BY_DMA;
-	}
-
-	/* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
-	/* boundary. We use the memory allocated for Tx descriptor. This memory  */
-	/* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
-	if (p_pkt_info->byte_cnt <= 8) {
-		printf ("You have failed in the < 8 bytes errata - fixme\n");	/* RABEEH - TBD */
-		return ETH_ERROR;
-
-		p_tx_desc_curr->buf_ptr =
-			(unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
-		eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
-			    p_pkt_info->byte_cnt);
-	} else
-		p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
-
-	p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
-	p_tx_desc_curr->return_info = p_pkt_info->return_info;
-
-	if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
-		/* Set last desc with DMA ownership and interrupt enable. */
-		p_tx_desc_curr->cmd_sts = command_status |
-			ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
-
-		if (p_tx_desc_curr != p_tx_desc_first)
-			p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
-
-		/* Flush CPU pipe */
-
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
-		CPU_PIPE_FLUSH;
-
-		/* Apply send command */
-		ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
-
-		/* Finish Tx packet. Update first desc in case of Tx resource error */
-		p_tx_desc_first = p_tx_next_desc_curr;
-		FIRST_TFD_SET (p_tx_desc_first, tx_queue);
-
-	} else {
-		p_tx_desc_curr->cmd_sts = command_status;
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
-	}
-
-	/* Check for ring index overlap in the Tx desc ring */
-	if (p_tx_next_desc_curr == p_tx_desc_used) {
-		/* Update the current descriptor */
-		CURR_TFD_SET (p_tx_desc_first, tx_queue);
-
-		p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
-		return ETH_QUEUE_LAST_RESOURCE;
-	} else {
-		/* Update the current descriptor */
-		CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
-		return ETH_OK;
-	}
-}
-
-/*******************************************************************************
- * eth_tx_return_desc - Free all used Tx descriptors
- *
- * DESCRIPTION:
- *	This routine returns the transmitted packet information to the caller.
- *      It uses the 'first' index to support Tx desc return in case a transmit
- *      of a packet spanned over multiple buffer still in process.
- *      In case the Tx queue was in "resource error" condition, where there are
- *      no available Tx resources, the function resets the resource error flag.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	tx_queue         Number of Tx queue.
- *	PKT_INFO        *p_pkt_info       User packet buffer.
- *
- * OUTPUT:
- *	Tx ring 'first' and 'used' indexes are updated.
- *
- * RETURN:
- *	ETH_ERROR in case the routine can not access Tx desc ring.
- *      ETH_RETRY in case there is transmission in process.
- *	ETH_END_OF_JOB if the routine has nothing to release.
- *      ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
-					       p_eth_port_ctrl,
-					       ETH_QUEUE tx_queue,
-					       PKT_INFO * p_pkt_info)
-{
-	volatile ETH_TX_DESC *p_tx_desc_used = NULL;
-	volatile ETH_TX_DESC *p_tx_desc_first = NULL;
-	unsigned int command_status;
-
-
-	/* Get the Tx Desc ring indexes */
-	USED_TFD_GET (p_tx_desc_used, tx_queue);
-	FIRST_TFD_GET (p_tx_desc_first, tx_queue);
-
-
-	/* Sanity check */
-	if (p_tx_desc_used == NULL)
-		return ETH_ERROR;
-
-	command_status = p_tx_desc_used->cmd_sts;
-
-	/* Still transmitting... */
-	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
-		return ETH_RETRY;
-	}
-
-	/* Stop release. About to overlap the current available Tx descriptor */
-	if ((p_tx_desc_used == p_tx_desc_first) &&
-	    (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
-		return ETH_END_OF_JOB;
-	}
-
-	/* Pass the packet information to the caller */
-	p_pkt_info->cmd_sts = command_status;
-	p_pkt_info->return_info = p_tx_desc_used->return_info;
-	p_tx_desc_used->return_info = 0;
-
-	/* Update the next descriptor to release. */
-	USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
-
-	/* Any Tx return cancels the Tx resource error status */
-	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
-		p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
-
-	D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
-
-	return ETH_OK;
-
-}
-
-/*******************************************************************************
- * eth_port_receive - Get received information from Rx ring.
- *
- * DESCRIPTION:
- *	This routine returns the received data to the caller. There is no
- *	data copying during routine operation. All information is returned
- *	using pointer to packet information struct passed from the caller.
- *      If the routine exhausts	Rx ring resources then the resource error flag
- *      is set.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	rx_queue         Number of Rx queue.
- *	PKT_INFO        *p_pkt_info       User packet buffer.
- *
- * OUTPUT:
- *	Rx ring current and used indexes are updated.
- *
- * RETURN:
- *	ETH_ERROR in case the routine can not access Rx desc ring.
- *	ETH_QUEUE_FULL if Rx ring resources are exhausted.
- *	ETH_END_OF_JOB if there is no received data.
- *      ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
-					     ETH_QUEUE rx_queue,
-					     PKT_INFO * p_pkt_info)
-{
-	volatile ETH_RX_DESC *p_rx_curr_desc;
-	volatile ETH_RX_DESC *p_rx_next_curr_desc;
-	volatile ETH_RX_DESC *p_rx_used_desc;
-	unsigned int command_status;
-
-	/* Do not process Rx ring in case of Rx ring resource error */
-	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
-		printf ("\nRx Queue is full ...\n");
-		return ETH_QUEUE_FULL;
-	}
-
-	/* Get the Rx Desc ring 'curr and 'used' indexes */
-	CURR_RFD_GET (p_rx_curr_desc, rx_queue);
-	USED_RFD_GET (p_rx_used_desc, rx_queue);
-
-	/* Sanity check */
-	if (p_rx_curr_desc == NULL)
-		return ETH_ERROR;
-
-	/* The following parameters are used to save readings from memory */
-	p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
-	command_status = p_rx_curr_desc->cmd_sts;
-
-	/* Nothing to receive... */
-	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
-/*	DP(printf("Rx: command_status: %08x\n", command_status)); */
-		D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
-/*	DP(printf("\nETH_END_OF_JOB ...\n"));*/
-		return ETH_END_OF_JOB;
-	}
-
-	p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
-	p_pkt_info->cmd_sts = command_status;
-	p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
-	p_pkt_info->return_info = p_rx_curr_desc->return_info;
-	p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size;	/* IP fragment indicator */
-
-	/* Clean the return info field to indicate that the packet has been */
-	/* moved to the upper layers                                        */
-	p_rx_curr_desc->return_info = 0;
-
-	/* Update 'curr' in data structure */
-	CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
-
-	/* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
-	if (p_rx_next_curr_desc == p_rx_used_desc)
-		p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
-
-	D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
-	CPU_PIPE_FLUSH;
-	return ETH_OK;
-}
-
-/*******************************************************************************
- * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
- *
- * DESCRIPTION:
- *	This routine returns a Rx buffer back to the Rx ring. It retrieves the
- *      next 'used' descriptor and attached the returned buffer to it.
- *      In case the Rx ring was in "resource error" condition, where there are
- *      no available Rx resources, the function resets the resource error flag.
- *
- * INPUT:
- *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	rx_queue         Number of Rx queue.
- *      PKT_INFO        *p_pkt_info       Information on the returned buffer.
- *
- * OUTPUT:
- *	New available Rx resource in Rx descriptor ring.
- *
- * RETURN:
- *	ETH_ERROR in case the routine can not access Rx desc ring.
- *      ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
-					       p_eth_port_ctrl,
-					       ETH_QUEUE rx_queue,
-					       PKT_INFO * p_pkt_info)
-{
-	volatile ETH_RX_DESC *p_used_rx_desc;	/* Where to return Rx resource */
-
-	/* Get 'used' Rx descriptor */
-	USED_RFD_GET (p_used_rx_desc, rx_queue);
-
-	/* Sanity check */
-	if (p_used_rx_desc == NULL)
-		return ETH_ERROR;
-
-	p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
-	p_used_rx_desc->return_info = p_pkt_info->return_info;
-	p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
-	p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE;	/* Reset Buffer size */
-
-	/* Flush the write pipe */
-	CPU_PIPE_FLUSH;
-
-	/* Return the descriptor to DMA ownership */
-	p_used_rx_desc->cmd_sts =
-		ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
-
-	/* Flush descriptor and CPU pipe */
-	D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
-	CPU_PIPE_FLUSH;
-
-	/* Move the used descriptor pointer to the next descriptor */
-	USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
-
-	/* Any Rx return cancels the Rx resource error status */
-	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
-		p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
-
-	return ETH_OK;
-}
-
-/*******************************************************************************
- * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
- *
- * DESCRIPTION:
- *	This routine sets the RX coalescing interrupt mechanism parameter.
- *	This parameter is a timeout counter, that counts in 64 t_clk
- *	chunks ; that when timeout event occurs a maskable interrupt
- *	occurs.
- *	The parameter is calculated using the tClk of the MV-643xx chip
- *	, and the required delay of the interrupt in usec.
- *
- * INPUT:
- *	ETH_PORT eth_port_num      Ethernet port number
- *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
- *	unsigned int delay       Delay in usec
- *
- * OUTPUT:
- *	Interrupt coalescing mechanism value is set in MV-643xx chip.
- *
- * RETURN:
- *	The interrupt coalescing value set in the gigE port.
- *
- *******************************************************************************/
-#if 0				/* FIXME */
-static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
-					  unsigned int t_clk,
-					  unsigned int delay)
-{
-	unsigned int coal;
-
-	coal = ((t_clk / 1000000) * delay) / 64;
-	/* Set RX Coalescing mechanism */
-	MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
-		      ((coal & 0x3fff) << 8) |
-		      (MV_REG_READ
-		       (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num))
-		       & 0xffc000ff));
-	return coal;
-}
-
-#endif
-/*******************************************************************************
- * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
- *
- * DESCRIPTION:
- *	This routine sets the TX coalescing interrupt mechanism parameter.
- *	This parameter is a timeout counter, that counts in 64 t_clk
- *	chunks ; that when timeout event occurs a maskable interrupt
- *	occurs.
- *	The parameter is calculated using the t_cLK frequency of the
- *	MV-643xx chip and the required delay in the interrupt in uSec
- *
- * INPUT:
- *	ETH_PORT eth_port_num      Ethernet port number
- *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
- *	unsigned int delay       Delay in uSeconds
- *
- * OUTPUT:
- *	Interrupt coalescing mechanism value is set in MV-643xx chip.
- *
- * RETURN:
- *	The interrupt coalescing value set in the gigE port.
- *
- *******************************************************************************/
-#if 0				/* FIXME */
-static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
-					  unsigned int t_clk,
-					  unsigned int delay)
-{
-	unsigned int coal;
-
-	coal = ((t_clk / 1000000) * delay) / 64;
-	/* Set TX Coalescing mechanism */
-	MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
-		      coal << 4);
-	return coal;
-}
-#endif
-
-/*******************************************************************************
- * eth_b_copy - Copy bytes from source to destination
- *
- * DESCRIPTION:
- *       This function supports the eight bytes limitation on Tx buffer size.
- *       The routine will zero eight bytes starting from the destination address
- *       followed by copying bytes from the source address to the destination.
- *
- * INPUT:
- *       unsigned int src_addr    32 bit source address.
- *       unsigned int dst_addr    32 bit destination address.
- *       int        byte_count    Number of bytes to copy.
- *
- * OUTPUT:
- *       See description.
- *
- * RETURN:
- *       None.
- *
- *******************************************************************************/
-static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
-			int byte_count)
-{
-	/* Zero the dst_addr area */
-	*(unsigned int *) dst_addr = 0x0;
-
-	while (byte_count != 0) {
-		*(char *) dst_addr = *(char *) src_addr;
-		dst_addr++;
-		src_addr++;
-		byte_count--;
-	}
-}
diff --git a/board/esd/cpci750/mv_eth.h b/board/esd/cpci750/mv_eth.h
deleted file mode 100644
index c04fb58afd8..00000000000
--- a/board/esd/cpci750/mv_eth.h
+++ /dev/null
@@ -1,819 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * mv_eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __DB64360_ETH_H__
-#define __DB64360_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-#include <net.h>
-#include "mv_regs.h"
-#include <asm/errno.h>
-
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The first part is the high level driver of the gigE ethernet ports.	 *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
-#ifndef MAX_SKB_FRAGS
-#define MAX_SKB_FRAGS 0
-#endif
-
-/* Port attributes */
-/*#define MAX_RX_QUEUE_NUM	8*/
-/*#define MAX_TX_QUEUE_NUM	8*/
-#define MAX_RX_QUEUE_NUM	1
-#define MAX_TX_QUEUE_NUM	1
-
-
-/* Use one TX queue and one RX queue */
-#define MV64360_TX_QUEUE_NUM 1
-#define MV64360_RX_QUEUE_NUM 1
-
-/*
- * Number of RX / TX descriptors on RX / TX rings.
- * Note that allocating RX descriptors is done by allocating the RX
- * ring AND a preallocated RX buffers (skb's) for each descriptor.
- * The TX descriptors only allocates the TX descriptors ring,
- * with no pre allocated TX buffers (skb's are allocated by higher layers.
- */
-
-/* Default TX ring size is 10 descriptors */
-#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
-#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
-#else
-#define MV64360_TX_QUEUE_SIZE 4
-#endif
-
-/* Default RX ring size is 4 descriptors */
-#ifdef	CONFIG_MV64360_ETH_RXQUEUE_SIZE
-#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
-#else
-#define MV64360_RX_QUEUE_SIZE 4
-#endif
-
-#ifdef CONFIG_RX_BUFFER_SIZE
-#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
-#else
-#define MV64360_RX_BUFFER_SIZE 1600
-#endif
-
-#ifdef CONFIG_TX_BUFFER_SIZE
-#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
-#else
-#define MV64360_TX_BUFFER_SIZE 1600
-#endif
-
-
-/*
- *	Network device statistics. Akin to the 2.0 ether stats but
- *	with byte counters.
- */
-
-struct net_device_stats
-{
-	unsigned long	rx_packets;		/* total packets received	*/
-	unsigned long	tx_packets;		/* total packets transmitted	*/
-	unsigned long	rx_bytes;		/* total bytes received		*/
-	unsigned long	tx_bytes;		/* total bytes transmitted	*/
-	unsigned long	rx_errors;		/* bad packets received		*/
-	unsigned long	tx_errors;		/* packet transmit problems	*/
-	unsigned long	rx_dropped;		/* no space in linux buffers	*/
-	unsigned long	tx_dropped;		/* no space available in linux	*/
-	unsigned long	multicast;		/* multicast packets received	*/
-	unsigned long	collisions;
-
-	/* detailed rx_errors: */
-	unsigned long	rx_length_errors;
-	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
-	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
-	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
-	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
-	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
-
-	/* detailed tx_errors */
-	unsigned long	tx_aborted_errors;
-	unsigned long	tx_carrier_errors;
-	unsigned long	tx_fifo_errors;
-	unsigned long	tx_heartbeat_errors;
-	unsigned long	tx_window_errors;
-
-	/* for cslip etc */
-	unsigned long	rx_compressed;
-	unsigned long	tx_compressed;
-};
-
-
-/* Private data structure used for ethernet device */
-struct mv64360_eth_priv {
-    unsigned int port_num;
-    struct net_device_stats *stats;
-
-/* to buffer area aligned */
-    char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
-    char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
-
-    /* Size of Tx Ring per queue */
-    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
-
-
-    /* Size of Rx Ring per queue */
-    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
-
-    /* Magic Number for Ethernet running */
-    unsigned int eth_running;
-
-};
-
-
-int mv64360_eth_init (struct eth_device *dev);
-int mv64360_eth_stop (struct eth_device *dev);
-int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length);
-int mv64360_eth_open (struct eth_device *dev);
-
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The second part is the low level driver of the gigE ethernet ports.	 *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-
-
-/********************************************************************************
- * Header File for : MV-643xx network interface header
- *
- * DESCRIPTION:
- *	 This header file contains macros typedefs and function declaration for
- *	 the Marvell Gig Bit Ethernet Controller.
- *
- * DEPENDENCIES:
- *	 None.
- *
- *******************************************************************************/
-
-
-#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
-#ifdef CONFIG_MV64360_SRAM_CACHEABLE
-/* In case SRAM is cacheable but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset)       \
-{		    \
-  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case SRAM is cache coherent or non-cacheable */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif
-#else
-#ifdef CONFIG_NOT_COHERENT_CACHE
-/* In case of descriptors on DDR but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset)       \
-{		    \
-  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case of descriptors on DDR and cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif /* CONFIG_NOT_COHERENT_CACHE */
-#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
-
-
-#define CPU_PIPE_FLUSH		   \
-{		  \
-  __asm__ __volatile__ ("eieio");	  \
-}
-
-
-/* defines  */
-
-/* Default port configuration value */
-#define PORT_CONFIG_VALUE			\
-	     ETH_UNICAST_NORMAL_MODE		|   \
-	     ETH_DEFAULT_RX_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
-	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
-	     ETH_RECEIVE_BC_IF_IP		|   \
-	     ETH_RECEIVE_BC_IF_ARP		|   \
-	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
-	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
-	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_BPDU_QUEUE_0
-
-/* Default port extend configuration value */
-#define PORT_CONFIG_EXTEND_VALUE		\
-	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
-	     ETH_PARTITION_DISABLE
-
-
-/* Default sdma control value */
-#ifdef CONFIG_NOT_COHERENT_CACHE
-#define PORT_SDMA_CONFIG_VALUE				\
-			 ETH_RX_BURST_SIZE_16_64BIT	|	\
-			 GT_ETH_IPG_INT_RX(0)			|	\
-			 ETH_TX_BURST_SIZE_16_64BIT;
-#else
-#define PORT_SDMA_CONFIG_VALUE			\
-			 ETH_RX_BURST_SIZE_4_64BIT	|	\
-			 GT_ETH_IPG_INT_RX(0)			|	\
-			 ETH_TX_BURST_SIZE_4_64BIT;
-#endif
-
-#define GT_ETH_IPG_INT_RX(value)		\
-	    ((value & 0x3fff) << 8)
-
-/* Default port serial control value */
-#define PORT_SERIAL_CONTROL_VALUE			    \
-			ETH_FORCE_LINK_PASS			|	\
-			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
-			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
-			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
-			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
-			ETH_FORCE_BP_MODE_NO_JAM		|	\
-			BIT9					|	\
-			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
-			ETH_RETRANSMIT_16_ETTEMPTS		|	\
-			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
-			ETH_DTE_ADV_0				|	\
-			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
-			ETH_AUTO_NEG_NO_CHANGE			|	\
-			ETH_MAX_RX_PACKET_1552BYTE		|	\
-			ETH_CLR_EXT_LOOPBACK			|	\
-			ETH_SET_FULL_DUPLEX_MODE		|	\
-			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
-
-#define RX_BUFFER_MAX_SIZE  0xFFFF
-#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
-
-#define RX_BUFFER_MIN_SIZE  0x8
-#define TX_BUFFER_MIN_SIZE  0x8
-
-/* Tx WRR confoguration macros */
-#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
-#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
-#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
-
-/* MAC accepet/reject macros */
-#define ACCEPT_MAC_ADDR	    0
-#define REJECT_MAC_ADDR	    1
-
-/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define RX_DESC_ALIGNED_SIZE		0x20
-#define TX_DESC_ALIGNED_SIZE		0x20
-
-/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
-#define TX_BUF_OFFSET_IN_DESC	    0x18
-/* Buffer offset from buffer pointer */
-#define RX_BUF_OFFSET				0x2
-
-/* Gap define */
-#define ETH_BAR_GAP					0x8
-#define ETH_SIZE_REG_GAP				0x8
-#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
-#define ETH_PORT_ACCESS_CTRL_GAP			0x4
-
-/* Gigabit Ethernet Unit Global Registers */
-
-/* MIB Counters register definitions */
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
-#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
-#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
-#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
-#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
-#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
-#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
-#define ETH_MIB_FRAMES_64_OCTETS	   0x20
-#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
-#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
-#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
-#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
-#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
-#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
-#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
-#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
-#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
-#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
-#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
-#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
-#define ETH_MIB_FC_SENT			   0x54
-#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
-#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
-#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
-#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
-#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
-#define ETH_MIB_JABBER_RECEIVED		   0x6c
-#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
-#define ETH_MIB_BAD_CRC_EVENT		   0x74
-#define ETH_MIB_COLLISION		   0x78
-#define ETH_MIB_LATE_COLLISION		   0x7c
-
-/* Port serial status reg (PSR) */
-#define ETH_INTERFACE_GMII_MII				0
-#define ETH_INTERFACE_PCM				BIT0
-#define ETH_LINK_IS_DOWN				0
-#define ETH_LINK_IS_UP					BIT1
-#define ETH_PORT_AT_HALF_DUPLEX				0
-#define ETH_PORT_AT_FULL_DUPLEX				BIT2
-#define ETH_RX_FLOW_CTRL_DISABLED			0
-#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
-#define ETH_GMII_SPEED_100_10				0
-#define ETH_GMII_SPEED_1000				BIT4
-#define ETH_MII_SPEED_10				0
-#define ETH_MII_SPEED_100				BIT5
-#define ETH_NO_TX					0
-#define ETH_TX_IN_PROGRESS				BIT7
-#define ETH_BYPASS_NO_ACTIVE				0
-#define ETH_BYPASS_ACTIVE				BIT8
-#define ETH_PORT_NOT_AT_PARTITION_STATE			0
-#define ETH_PORT_AT_PARTITION_STATE			BIT9
-#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
-#define ETH_PORT_TX_FIFO_EMPTY				BIT10
-
-
-/* These macros describes the Port configuration reg (Px_cR) bits */
-#define ETH_UNICAST_NORMAL_MODE				0
-#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
-#define ETH_DEFAULT_RX_QUEUE_0				0
-#define ETH_DEFAULT_RX_QUEUE_1				BIT1
-#define ETH_DEFAULT_RX_QUEUE_2				BIT2
-#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_4				BIT3
-#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
-#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
-#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
-#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
-#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
-#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
-#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
-#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
-#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
-#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
-#define ETH_RECEIVE_BC_IF_IP				0
-#define ETH_REJECT_BC_IF_IP				BIT8
-#define ETH_RECEIVE_BC_IF_ARP				0
-#define ETH_REJECT_BC_IF_ARP				BIT9
-#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
-#define ETH_CAPTURE_TCP_FRAMES_DIS			0
-#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
-#define ETH_CAPTURE_UDP_FRAMES_DIS			0
-#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
-#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
-#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
-#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
-#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
-#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
-#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
-#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
-#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
-#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
-#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
-#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
-#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
-#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
-#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
-#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
-#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
-
-
-/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
-#define ETH_CLASSIFY_EN					BIT0
-#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
-#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
-#define ETH_PARTITION_DISABLE				0
-#define ETH_PARTITION_ENABLE				BIT2
-
-
-/* Tx/Rx queue command reg (RQCR/TQCR)*/
-#define ETH_QUEUE_0_ENABLE				BIT0
-#define ETH_QUEUE_1_ENABLE				BIT1
-#define ETH_QUEUE_2_ENABLE				BIT2
-#define ETH_QUEUE_3_ENABLE				BIT3
-#define ETH_QUEUE_4_ENABLE				BIT4
-#define ETH_QUEUE_5_ENABLE				BIT5
-#define ETH_QUEUE_6_ENABLE				BIT6
-#define ETH_QUEUE_7_ENABLE				BIT7
-#define ETH_QUEUE_0_DISABLE				BIT8
-#define ETH_QUEUE_1_DISABLE				BIT9
-#define ETH_QUEUE_2_DISABLE				BIT10
-#define ETH_QUEUE_3_DISABLE				BIT11
-#define ETH_QUEUE_4_DISABLE				BIT12
-#define ETH_QUEUE_5_DISABLE				BIT13
-#define ETH_QUEUE_6_DISABLE				BIT14
-#define ETH_QUEUE_7_DISABLE				BIT15
-
-
-/* These macros describes the Port Sdma configuration reg (SDCR) bits */
-#define ETH_RIFB					BIT0
-#define ETH_RX_BURST_SIZE_1_64BIT			0
-#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
-#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
-#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
-#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
-#define ETH_BLM_RX_NO_SWAP				BIT4
-#define ETH_BLM_RX_BYTE_SWAP				0
-#define ETH_BLM_TX_NO_SWAP				BIT5
-#define ETH_BLM_TX_BYTE_SWAP				0
-#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
-#define ETH_DESCRIPTORS_NO_SWAP				0
-#define ETH_TX_BURST_SIZE_1_64BIT			0
-#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
-#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
-#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
-#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
-
-
-/* These macros describes the Port serial control reg (PSCR) bits */
-#define ETH_SERIAL_PORT_DISABLE				0
-#define ETH_SERIAL_PORT_ENABLE				BIT0
-#define ETH_FORCE_LINK_PASS				BIT1
-#define ETH_DO_NOT_FORCE_LINK_PASS			0
-#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
-#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
-#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
-#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
-#define ETH_ADV_NO_FLOW_CTRL				0
-#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
-#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
-#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
-#define ETH_FORCE_BP_MODE_NO_JAM			0
-#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
-#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
-#define ETH_FORCE_LINK_FAIL				0
-#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
-#define ETH_RETRANSMIT_16_ETTEMPTS			0
-#define ETH_RETRANSMIT_FOREVER				BIT11
-#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
-#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
-#define ETH_DTE_ADV_0					0
-#define ETH_DTE_ADV_1					BIT14
-#define ETH_DISABLE_AUTO_NEG_BYPASS			0
-#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
-#define ETH_AUTO_NEG_NO_CHANGE				0
-#define ETH_RESTART_AUTO_NEG				BIT16
-#define ETH_MAX_RX_PACKET_1518BYTE			0
-#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
-#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
-#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
-#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
-#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
-#define ETH_SET_EXT_LOOPBACK				BIT20
-#define ETH_CLR_EXT_LOOPBACK				0
-#define ETH_SET_FULL_DUPLEX_MODE			BIT21
-#define ETH_SET_HALF_DUPLEX_MODE			0
-#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
-#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
-#define ETH_SET_GMII_SPEED_TO_10_100			0
-#define ETH_SET_GMII_SPEED_TO_1000			BIT23
-#define ETH_SET_MII_SPEED_TO_10				0
-#define ETH_SET_MII_SPEED_TO_100			BIT24
-
-
-/* SMI reg */
-#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
-#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
-#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
-#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
-
-/* SDMA command status fields macros */
-
-/* Tx & Rx descriptors status */
-#define ETH_ERROR_SUMMARY		    (BIT0)
-
-/* Tx & Rx descriptors command */
-#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
-
-/* Tx descriptors status */
-#define ETH_LC_ERROR			    (0	  )
-#define ETH_UR_ERROR			    (BIT1 )
-#define ETH_RL_ERROR			    (BIT2 )
-#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
-
-/* Rx descriptors status */
-#define ETH_CRC_ERROR			    (0	  )
-#define ETH_OVERRUN_ERROR		    (BIT1 )
-#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
-#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
-#define ETH_VLAN_TAGGED			    (BIT19)
-#define ETH_BPDU_FRAME			    (BIT20)
-#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
-#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
-#define ETH_OTHER_FRAME_TYPE		    (BIT22)
-#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
-#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
-#define ETH_FRAME_HEADER_OK		    (BIT25)
-#define ETH_RX_LAST_DESC		    (BIT26)
-#define ETH_RX_FIRST_DESC		    (BIT27)
-#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
-#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
-#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
-
-/* Rx descriptors byte count */
-#define ETH_FRAME_FRAGMENTED		    (BIT2)
-
-/* Tx descriptors command */
-#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
-#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
-#define ETH_TCP_FRAME			    (0	  )
-#define ETH_UDP_FRAME			    (BIT16)
-#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
-#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
-#define ETH_ZERO_PADDING		    (BIT19)
-#define ETH_TX_LAST_DESC		    (BIT20)
-#define ETH_TX_FIRST_DESC		    (BIT21)
-#define ETH_GEN_CRC			    (BIT22)
-#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
-#define ETH_AUTO_MODE			    (BIT30)
-
-/* Address decode parameters */
-/* Ethernet Base Address Register bits */
-#define EBAR_TARGET_DRAM					0x00000000
-#define EBAR_TARGET_DEVICE					0x00000001
-#define EBAR_TARGET_CBS						0x00000002
-#define EBAR_TARGET_PCI0					0x00000003
-#define EBAR_TARGET_PCI1					0x00000004
-#define EBAR_TARGET_CUNIT					0x00000005
-#define EBAR_TARGET_AUNIT					0x00000006
-#define EBAR_TARGET_GUNIT					0x00000007
-
-/* Window attributes */
-#define EBAR_ATTR_DRAM_CS0					0x00000E00
-#define EBAR_ATTR_DRAM_CS1					0x00000D00
-#define EBAR_ATTR_DRAM_CS2					0x00000B00
-#define EBAR_ATTR_DRAM_CS3					0x00000700
-
-/* DRAM Target interface */
-#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
-
-/* Device Bus Target interface */
-#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
-#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
-#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
-#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
-#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
-
-/* PCI Target interface */
-#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
-#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
-#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
-#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
-#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
-#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
-#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
-#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
-#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
-#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
-
-/* CPU 60x bus or internal SRAM interface */
-#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
-#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
-#define EBAR_ATTR_CBS_SRAM					0x00000000
-#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
-
-/* Window access control */
-#define EWIN_ACCESS_NOT_ALLOWED 0
-#define EWIN_ACCESS_READ_ONLY	BIT0
-#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
-#define EWIN0_ACCESS_MASK		0x0003
-#define EWIN1_ACCESS_MASK		0x000C
-#define EWIN2_ACCESS_MASK		0x0030
-#define EWIN3_ACCESS_MASK		0x00C0
-
-/* typedefs */
-
-typedef enum _eth_port
-{
-    ETH_0 = 0,
-	ETH_1 = 1,
-	ETH_2 = 2
-}ETH_PORT;
-
-typedef enum _eth_func_ret_status
-{
-    ETH_OK,			/* Returned as expected.		    */
-    ETH_ERROR,			/* Fundamental error.			    */
-    ETH_RETRY,			/* Could not process request. Try later.    */
-    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
-    ETH_QUEUE_FULL,		/* Ring resource error.			    */
-    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
-}ETH_FUNC_RET_STATUS;
-
-typedef enum _eth_queue
-{
-	ETH_Q0 = 0,
-	ETH_Q1 = 1,
-	ETH_Q2 = 2,
-	ETH_Q3 = 3,
-	ETH_Q4 = 4,
-	ETH_Q5 = 5,
-	ETH_Q6 = 6,
-    ETH_Q7 = 7
-} ETH_QUEUE;
-
-typedef enum _addr_win
-{
-	ETH_WIN0,
-	ETH_WIN1,
-	ETH_WIN2,
-	ETH_WIN3,
-	ETH_WIN4,
-    ETH_WIN5
-} ETH_ADDR_WIN;
-
-typedef enum _eth_target
-{
-	ETH_TARGET_DRAM	 ,
-	ETH_TARGET_DEVICE,
-	ETH_TARGET_CBS	 ,
-	ETH_TARGET_PCI0	 ,
-	ETH_TARGET_PCI1
-}ETH_TARGET;
-
-typedef struct _eth_rx_desc
-{
-	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
-	unsigned short	buf_size	   ;	/* Buffer size			    */
-	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
-	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
-	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} ETH_RX_DESC;
-
-
-typedef struct _eth_tx_desc
-{
-    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
-    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
-    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
-    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
-    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} ETH_TX_DESC;
-
-/* Unified struct for Rx and Tx operations. The user is not required to */
-/* be familier with neither Tx nor Rx descriptors.			 */
-typedef struct _pkt_info
-{
-	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
-	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
-	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
-	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} PKT_INFO;
-
-
-typedef struct _eth_win_param
-{
-    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
-    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
-    unsigned short attributes;	/* BAR attributes. See above macros. */
-    unsigned int base_addr; /* Window base address in unsigned int form */
-    unsigned int high_addr; /* Window high address in unsigned int form */
-    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
-    bool enable; /* Enable/disable access to the window. */
-    unsigned short access_ctrl; /* Access ctrl register. see above macros */
-} ETH_WIN_PARAM;
-
-
-/* Ethernet port specific infomation */
-
-typedef struct _eth_port_ctrl
-{
-    ETH_PORT  port_num; /* User Ethernet port number */
-    int port_phy_addr;	/* User phy address of Ethrnet port */
-    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
-    unsigned int  port_config; /* User port configuration value */
-    unsigned int  port_config_extend; /* User port config extend value */
-    unsigned int  port_sdma_config; /* User port SDMA config value */
-    unsigned int  port_serial_control; /* User port serial control value */
-    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
-    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
-
-    /* User function to cast virtual address to CPU bus address */
-    unsigned int  (*port_virt_to_phys)(unsigned int addr);
-    /* User scratch pad for user specific data structures */
-    void *port_private;
-
-    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
-    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
-
-    /* Tx/Rx rings managment indexes fields. For driver use */
-
-    /* Next available Rx resource */
-    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
-    /* Returning Rx resource */
-    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
-
-    /* Next available Tx resource */
-    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
-    /* Returning Tx resource */
-    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
-    /* An extra Tx index to support transmit of multiple buffers per packet */
-    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
-
-    /* Tx/Rx rings size and base variables fields. For driver use */
-
-    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
-    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
-    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
-
-    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
-    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
-    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
-
-} ETH_PORT_INFO;
-
-
-/* ethernet.h API list */
-
-/* Port operation control routines */
-static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
-static void eth_port_reset(ETH_PORT	eth_port_num);
-static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
-
-
-/* Port MAC address routines */
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
-				  unsigned char *p_addr,
-				  ETH_QUEUE queue);
-#if 0	/* FIXME */
-static void eth_port_mc_addr	(ETH_PORT eth_port_num,
-				 unsigned char *p_addr,
-				 ETH_QUEUE queue,
-				 int option);
-#endif
-
-/* PHY and MIB routines */
-static bool ethernet_phy_reset(ETH_PORT eth_port_num);
-
-static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
-				   unsigned int phy_reg,
-				   unsigned int value);
-
-static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
-				  unsigned int phy_reg,
-				  unsigned int* value);
-
-static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
-
-/* Port data flow control routines */
-static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
-					     ETH_QUEUE tx_queue,
-					     PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
-					      ETH_QUEUE tx_queue,
-					      PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
-					     ETH_QUEUE rx_queue,
-					     PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
-					      ETH_QUEUE rx_queue,
-					      PKT_INFO *p_pkt_info);
-
-
-static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
-				    ETH_QUEUE	tx_queue,
-				    int				tx_desc_num,
-				    int				tx_buff_size,
-				    unsigned int	tx_desc_base_addr,
-				    unsigned int	tx_buff_base_addr);
-
-static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
-				    ETH_QUEUE	rx_queue,
-				    int				rx_desc_num,
-				    int				rx_buff_size,
-				    unsigned int	rx_desc_base_addr,
-				    unsigned int	rx_buff_base_addr);
-
-#endif /* MV64360_ETH_ */
diff --git a/board/esd/cpci750/mv_regs.h b/board/esd/cpci750/mv_regs.h
deleted file mode 100644
index 9a54a976d93..00000000000
--- a/board/esd/cpci750/mv_regs.h
+++ /dev/null
@@ -1,1108 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/********************************************************************************
-* gt64360r.h - GT-64360 Internal registers definition file.
-*
-* DESCRIPTION:
-*	None.
-*
-* DEPENDENCIES:
-*	None.
-*
-*******************************************************************************/
-
-#ifndef __INCmv_regsh
-#define __INCmv_regsh
-
-#define MV64360
-
-/* Supported by the Atlantis */
-#define MV64360_INCLUDE_PCI_1
-#define MV64360_INCLUDE_PCI_0_ARBITER
-#define MV64360_INCLUDE_PCI_1_ARBITER
-#define MV64360_INCLUDE_SNOOP_SUPPORT
-#define MV64360_INCLUDE_P2P
-#define MV64360_INCLUDE_ETH_PORT_2
-#define MV64360_INCLUDE_CPU_MAPPING
-#define MV64360_INCLUDE_MPSC
-
-/* Not supported features */
-#undef	INCLUDE_CNTMR_4_7
-#undef	INCLUDE_DMA_4_7
-
-/****************************************/
-/* Processor Address Space		*/
-/****************************************/
-
-/* DDR SDRAM BAR and size registers */
-
-#define MV64360_CS_0_BASE_ADDR					    0x008
-#define MV64360_CS_0_SIZE					    0x010
-#define MV64360_CS_1_BASE_ADDR					    0x208
-#define MV64360_CS_1_SIZE					    0x210
-#define MV64360_CS_2_BASE_ADDR					    0x018
-#define MV64360_CS_2_SIZE					    0x020
-#define MV64360_CS_3_BASE_ADDR					    0x218
-#define MV64360_CS_3_SIZE					    0x220
-
-/* Devices BAR and size registers */
-
-#define MV64360_DEV_CS0_BASE_ADDR				    0x028
-#define MV64360_DEV_CS0_SIZE					    0x030
-#define MV64360_DEV_CS1_BASE_ADDR				    0x228
-#define MV64360_DEV_CS1_SIZE					    0x230
-#define MV64360_DEV_CS2_BASE_ADDR				    0x248
-#define MV64360_DEV_CS2_SIZE					    0x250
-#define MV64360_DEV_CS3_BASE_ADDR				    0x038
-#define MV64360_DEV_CS3_SIZE					    0x040
-#define MV64360_BOOTCS_BASE_ADDR				    0x238
-#define MV64360_BOOTCS_SIZE					    0x240
-
-/* PCI 0 BAR and size registers */
-
-#define MV64360_PCI_0_IO_BASE_ADDR				    0x048
-#define MV64360_PCI_0_IO_SIZE					    0x050
-#define MV64360_PCI_0_MEMORY0_BASE_ADDR				    0x058
-#define MV64360_PCI_0_MEMORY0_SIZE				    0x060
-#define MV64360_PCI_0_MEMORY1_BASE_ADDR				    0x080
-#define MV64360_PCI_0_MEMORY1_SIZE				    0x088
-#define MV64360_PCI_0_MEMORY2_BASE_ADDR				    0x258
-#define MV64360_PCI_0_MEMORY2_SIZE				    0x260
-#define MV64360_PCI_0_MEMORY3_BASE_ADDR				    0x280
-#define MV64360_PCI_0_MEMORY3_SIZE				    0x288
-
-/* PCI 1 BAR and size registers */
-#define MV64360_PCI_1_IO_BASE_ADDR				    0x090
-#define MV64360_PCI_1_IO_SIZE					    0x098
-#define MV64360_PCI_1_MEMORY0_BASE_ADDR				    0x0a0
-#define MV64360_PCI_1_MEMORY0_SIZE				    0x0a8
-#define MV64360_PCI_1_MEMORY1_BASE_ADDR				    0x0b0
-#define MV64360_PCI_1_MEMORY1_SIZE				    0x0b8
-#define MV64360_PCI_1_MEMORY2_BASE_ADDR				    0x2a0
-#define MV64360_PCI_1_MEMORY2_SIZE				    0x2a8
-#define MV64360_PCI_1_MEMORY3_BASE_ADDR				    0x2b0
-#define MV64360_PCI_1_MEMORY3_SIZE				    0x2b8
-
-/* SRAM base address */
-#define MV64360_INTEGRATED_SRAM_BASE_ADDR			    0x268
-
-/* internal registers space base address */
-#define MV64360_INTERNAL_SPACE_BASE_ADDR			    0x068
-
-/* Enables the CS , DEV_CS , PCI 0 and PCI 1
-   windows above */
-#define MV64360_BASE_ADDR_ENABLE				    0x278
-
-/****************************************/
-/* PCI remap registers			*/
-/****************************************/
-      /* PCI 0 */
-#define MV64360_PCI_0_IO_ADDR_REMAP				    0x0f0
-#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP			    0x0f8
-#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP			    0x320
-#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP			    0x100
-#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP			    0x328
-#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP			    0x2f8
-#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP			    0x330
-#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP			    0x300
-#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP			    0x338
-      /* PCI 1 */
-#define MV64360_PCI_1_IO_ADDR_REMAP				    0x108
-#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP			    0x110
-#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP			    0x340
-#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP			    0x118
-#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP			    0x348
-#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP			    0x310
-#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP			    0x350
-#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP			    0x318
-#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP			    0x358
-
-#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL		    0x3b0
-#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE			    0x3b8
-#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL		    0x3c0
-#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE			    0x3c8
-#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL			    0x3d0
-#define MV64360_CPU_GE_HEADERS_RETARGET_BASE			    0x3d8
-#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL		    0x3e0
-#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE			    0x3e8
-
-/****************************************/
-/*	   CPU Control Registers	*/
-/****************************************/
-
-#define MV64360_CPU_CONFIG					    0x000
-#define MV64360_CPU_MODE					    0x120
-#define MV64360_CPU_MASTER_CONTROL				    0x160
-#define MV64360_CPU_CROSS_BAR_CONTROL_LOW			    0x150
-#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH			    0x158
-#define MV64360_CPU_CROSS_BAR_TIMEOUT				    0x168
-
-/****************************************/
-/* SMP RegisterS			*/
-/****************************************/
-
-#define MV64360_SMP_WHO_AM_I					    0x200
-#define MV64360_SMP_CPU0_DOORBELL				    0x214
-#define MV64360_SMP_CPU0_DOORBELL_CLEAR				    0x21C
-#define MV64360_SMP_CPU1_DOORBELL				    0x224
-#define MV64360_SMP_CPU1_DOORBELL_CLEAR				    0x22C
-#define MV64360_SMP_CPU0_DOORBELL_MASK				    0x234
-#define MV64360_SMP_CPU1_DOORBELL_MASK				    0x23C
-#define MV64360_SMP_SEMAPHOR0					    0x244
-#define MV64360_SMP_SEMAPHOR1					    0x24c
-#define MV64360_SMP_SEMAPHOR2					    0x254
-#define MV64360_SMP_SEMAPHOR3					    0x25c
-#define MV64360_SMP_SEMAPHOR4					    0x264
-#define MV64360_SMP_SEMAPHOR5					    0x26c
-#define MV64360_SMP_SEMAPHOR6					    0x274
-#define MV64360_SMP_SEMAPHOR7					    0x27c
-
-/****************************************/
-/*  CPU Sync Barrier Register		*/
-/****************************************/
-
-#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER			    0x0c0
-#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL			    0x0c8
-#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER			    0x0d0
-#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL			    0x0d8
-
-/****************************************/
-/* CPU Access Protect			*/
-/****************************************/
-
-#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR			    0x180
-#define MV64360_CPU_PROTECT_WINDOW_0_SIZE			    0x188
-#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR			    0x190
-#define MV64360_CPU_PROTECT_WINDOW_1_SIZE			    0x198
-#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR			    0x1a0
-#define MV64360_CPU_PROTECT_WINDOW_2_SIZE			    0x1a8
-#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR			    0x1b0
-#define MV64360_CPU_PROTECT_WINDOW_3_SIZE			    0x1b8
-
-
-/****************************************/
-/*	    CPU Error Report		*/
-/****************************************/
-
-#define MV64360_CPU_ERROR_ADDR_LOW				    0x070
-#define MV64360_CPU_ERROR_ADDR_HIGH				    0x078
-#define MV64360_CPU_ERROR_DATA_LOW				    0x128
-#define MV64360_CPU_ERROR_DATA_HIGH				    0x130
-#define MV64360_CPU_ERROR_PARITY				    0x138
-#define MV64360_CPU_ERROR_CAUSE					    0x140
-#define MV64360_CPU_ERROR_MASK					    0x148
-
-/****************************************/
-/*	CPU Interface Debug Registers	*/
-/****************************************/
-
-#define MV64360_PUNIT_SLAVE_DEBUG_LOW				    0x360
-#define MV64360_PUNIT_SLAVE_DEBUG_HIGH				    0x368
-#define MV64360_PUNIT_MASTER_DEBUG_LOW				    0x370
-#define MV64360_PUNIT_MASTER_DEBUG_HIGH				    0x378
-#define MV64360_PUNIT_MMASK					    0x3e4
-
-/****************************************/
-/*  Integrated SRAM Registers		*/
-/****************************************/
-
-#define MV64360_SRAM_CONFIG					    0x380
-#define MV64360_SRAM_TEST_MODE					    0X3F4
-#define MV64360_SRAM_ERROR_CAUSE				    0x388
-#define MV64360_SRAM_ERROR_ADDR					    0x390
-#define MV64360_SRAM_ERROR_ADDR_HIGH				    0X3F8
-#define MV64360_SRAM_ERROR_DATA_LOW				    0x398
-#define MV64360_SRAM_ERROR_DATA_HIGH				    0x3a0
-#define MV64360_SRAM_ERROR_DATA_PARITY				    0x3a8
-
-/****************************************/
-/* SDRAM Configuration			*/
-/****************************************/
-
-#define MV64360_SDRAM_CONFIG					    0x1400
-#define MV64360_D_UNIT_CONTROL_LOW				    0x1404
-#define MV64360_D_UNIT_CONTROL_HIGH				    0x1424
-#define MV64360_SDRAM_TIMING_CONTROL_LOW			    0x1408
-#define MV64360_SDRAM_TIMING_CONTROL_HIGH			    0x140c
-#define MV64360_SDRAM_ADDR_CONTROL				    0x1410
-#define MV64360_SDRAM_OPEN_PAGES_CONTROL			    0x1414
-#define MV64360_SDRAM_OPERATION					    0x1418
-#define MV64360_SDRAM_MODE					    0x141c
-#define MV64360_EXTENDED_DRAM_MODE				    0x1420
-#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW			    0x1430
-#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH			    0x1434
-#define MV64360_SDRAM_CROSS_BAR_TIMEOUT				    0x1438
-#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION		    0x14c0
-#define MV64360_SDRAM_DATA_PADS_CALIBRATION			    0x14c4
-
-/****************************************/
-/* SDRAM Error Report			*/
-/****************************************/
-
-#define MV64360_SDRAM_ERROR_DATA_LOW				    0x1444
-#define MV64360_SDRAM_ERROR_DATA_HIGH				    0x1440
-#define MV64360_SDRAM_ERROR_ADDR				    0x1450
-#define MV64360_SDRAM_RECEIVED_ECC				    0x1448
-#define MV64360_SDRAM_CALCULATED_ECC				    0x144c
-#define MV64360_SDRAM_ECC_CONTROL				    0x1454
-#define MV64360_SDRAM_ECC_ERROR_COUNTER				    0x1458
-
-/******************************************/
-/*  Controlled Delay Line (CDL) Registers */
-/******************************************/
-
-#define MV64360_DFCDL_CONFIG0					    0x1480
-#define MV64360_DFCDL_CONFIG1					    0x1484
-#define MV64360_DLL_WRITE					    0x1488
-#define MV64360_DLL_READ					    0x148c
-#define MV64360_SRAM_ADDR					    0x1490
-#define MV64360_SRAM_DATA0					    0x1494
-#define MV64360_SRAM_DATA1					    0x1498
-#define MV64360_SRAM_DATA2					    0x149c
-#define MV64360_DFCL_PROBE					    0x14a0
-
-/******************************************/
-/*   Debug Registers			  */
-/******************************************/
-
-#define MV64360_DUNIT_DEBUG_LOW					    0x1460
-#define MV64360_DUNIT_DEBUG_HIGH				    0x1464
-#define MV64360_DUNIT_MMASK					    0X1b40
-
-/****************************************/
-/* Device Parameters			*/
-/****************************************/
-
-#define MV64360_DEVICE_BANK0_PARAMETERS				    0x45c
-#define MV64360_DEVICE_BANK1_PARAMETERS				    0x460
-#define MV64360_DEVICE_BANK2_PARAMETERS				    0x464
-#define MV64360_DEVICE_BANK3_PARAMETERS				    0x468
-#define MV64360_DEVICE_BOOT_BANK_PARAMETERS			    0x46c
-#define MV64360_DEVICE_INTERFACE_CONTROL			    0x4c0
-#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		    0x4c8
-#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		    0x4cc
-#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT		    0x4c4
-
-/****************************************/
-/* Device interrupt registers		*/
-/****************************************/
-
-#define MV64360_DEVICE_INTERRUPT_CAUSE				    0x4d0
-#define MV64360_DEVICE_INTERRUPT_MASK				    0x4d4
-#define MV64360_DEVICE_ERROR_ADDR				    0x4d8
-#define MV64360_DEVICE_ERROR_DATA				    0x4dc
-#define MV64360_DEVICE_ERROR_PARITY				    0x4e0
-
-/****************************************/
-/* Device debug registers		*/
-/****************************************/
-
-#define MV64360_DEVICE_DEBUG_LOW				    0x4e4
-#define MV64360_DEVICE_DEBUG_HIGH				    0x4e8
-#define MV64360_RUNIT_MMASK					    0x4f0
-
-/****************************************/
-/* PCI Slave Address Decoding registers */
-/****************************************/
-
-#define MV64360_PCI_0_CS_0_BANK_SIZE				    0xc08
-#define MV64360_PCI_1_CS_0_BANK_SIZE				    0xc88
-#define MV64360_PCI_0_CS_1_BANK_SIZE				    0xd08
-#define MV64360_PCI_1_CS_1_BANK_SIZE				    0xd88
-#define MV64360_PCI_0_CS_2_BANK_SIZE				    0xc0c
-#define MV64360_PCI_1_CS_2_BANK_SIZE				    0xc8c
-#define MV64360_PCI_0_CS_3_BANK_SIZE				    0xd0c
-#define MV64360_PCI_1_CS_3_BANK_SIZE				    0xd8c
-#define MV64360_PCI_0_DEVCS_0_BANK_SIZE				    0xc10
-#define MV64360_PCI_1_DEVCS_0_BANK_SIZE				    0xc90
-#define MV64360_PCI_0_DEVCS_1_BANK_SIZE				    0xd10
-#define MV64360_PCI_1_DEVCS_1_BANK_SIZE				    0xd90
-#define MV64360_PCI_0_DEVCS_2_BANK_SIZE				    0xd18
-#define MV64360_PCI_1_DEVCS_2_BANK_SIZE				    0xd98
-#define MV64360_PCI_0_DEVCS_3_BANK_SIZE				    0xc14
-#define MV64360_PCI_1_DEVCS_3_BANK_SIZE				    0xc94
-#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE			    0xd14
-#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE			    0xd94
-#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE				    0xd1c
-#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE				    0xd9c
-#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE				    0xd20
-#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE				    0xda0
-#define MV64360_PCI_0_P2P_I_O_BAR_SIZE				    0xd24
-#define MV64360_PCI_1_P2P_I_O_BAR_SIZE				    0xda4
-#define MV64360_PCI_0_CPU_BAR_SIZE				    0xd28
-#define MV64360_PCI_1_CPU_BAR_SIZE				    0xda8
-#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE			    0xe00
-#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE			    0xe80
-#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE			    0xd2c
-#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE			    0xd9c
-#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE			    0xc3c
-#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE			    0xcbc
-#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP			    0xc48
-#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP			    0xcc8
-#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP			    0xd48
-#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP			    0xdc8
-#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP			    0xc4c
-#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP			    0xccc
-#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP			    0xd4c
-#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP			    0xdcc
-#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP			    0xF04
-#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP			    0xF84
-#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP			    0xF08
-#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP			    0xF88
-#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP			    0xF0C
-#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP			    0xF8C
-#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP			    0xF10
-#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP			    0xF90
-#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP			    0xc50
-#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP			    0xcd0
-#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP			    0xd50
-#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP			    0xdd0
-#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP			    0xd58
-#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP			    0xdd8
-#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP			    0xc54
-#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP			    0xcd4
-#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xd54
-#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xdd4
-#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xd5c
-#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xddc
-#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xd60
-#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xde0
-#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xd64
-#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xde4
-#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xd68
-#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xde8
-#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP			    0xd6c
-#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP			    0xdec
-#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW			    0xd70
-#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW			    0xdf0
-#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH			    0xd74
-#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH			    0xdf4
-#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf00
-#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf80
-#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		    0xf38
-#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		    0xfb8
-#define MV64360_PCI_0_ADDR_DECODE_CONTROL			    0xd3c
-#define MV64360_PCI_1_ADDR_DECODE_CONTROL			    0xdbc
-#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL			    0xF40
-#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL			    0xFc0
-#define MV64360_PCI_0_HEADERS_RETARGET_BASE			    0xF44
-#define MV64360_PCI_1_HEADERS_RETARGET_BASE			    0xFc4
-#define MV64360_PCI_0_HEADERS_RETARGET_HIGH			    0xF48
-#define MV64360_PCI_1_HEADERS_RETARGET_HIGH			    0xFc8
-
-/***********************************/
-/*   PCI Control Register Map	   */
-/***********************************/
-
-#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND			    0x1d20
-#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND			    0x1da0
-#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL			    0x1d1C
-#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL			    0x1d9C
-#define MV64360_PCI_0_COMMAND					    0xc00
-#define MV64360_PCI_1_COMMAND					    0xc80
-#define MV64360_PCI_0_MODE					    0xd00
-#define MV64360_PCI_1_MODE					    0xd80
-#define MV64360_PCI_0_RETRY					    0xc04
-#define MV64360_PCI_1_RETRY					    0xc84
-#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER			    0xd04
-#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER			    0xd84
-#define MV64360_PCI_0_MSI_TRIGGER_TIMER				    0xc38
-#define MV64360_PCI_1_MSI_TRIGGER_TIMER				    0xcb8
-#define MV64360_PCI_0_ARBITER_CONTROL				    0x1d00
-#define MV64360_PCI_1_ARBITER_CONTROL				    0x1d80
-#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW			    0x1d08
-#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW			    0x1d88
-#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH			    0x1d0c
-#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH			    0x1d8c
-#define MV64360_PCI_0_CROSS_BAR_TIMEOUT				    0x1d04
-#define MV64360_PCI_1_CROSS_BAR_TIMEOUT				    0x1d84
-#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG			    0x1D18
-#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG			    0x1D98
-#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG			    0x1d10
-#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG			    0x1d90
-#define MV64360_PCI_0_P2P_CONFIG				    0x1d14
-#define MV64360_PCI_1_P2P_CONFIG				    0x1d94
-
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW			    0x1e00
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH		    0x1e04
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0			    0x1e08
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW			    0x1e10
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH		    0x1e14
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1			    0x1e18
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW			    0x1e20
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH		    0x1e24
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2			    0x1e28
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW			    0x1e30
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH		    0x1e34
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3			    0x1e38
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW			    0x1e40
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH		    0x1e44
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4			    0x1e48
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW			    0x1e50
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH		    0x1e54
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5			    0x1e58
-
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW			    0x1e80
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH		    0x1e84
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0			    0x1e88
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW			    0x1e90
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH		    0x1e94
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1			    0x1e98
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW			    0x1ea0
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH		    0x1ea4
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2			    0x1ea8
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW			    0x1eb0
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH		    0x1eb4
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3			    0x1eb8
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW			    0x1ec0
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH		    0x1ec4
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4			    0x1ec8
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW			    0x1ed0
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH		    0x1ed4
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5			    0x1ed8
-
-/****************************************/
-/*   PCI Configuration Access Registers */
-/****************************************/
-
-#define MV64360_PCI_0_CONFIG_ADDR				    0xcf8
-#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG			    0xcfc
-#define MV64360_PCI_1_CONFIG_ADDR				    0xc78
-#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG			    0xc7c
-#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xc34
-#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xcb4
-
-/****************************************/
-/*   PCI Error Report Registers		*/
-/****************************************/
-
-#define MV64360_PCI_0_SERR_MASK					    0xc28
-#define MV64360_PCI_1_SERR_MASK					    0xca8
-#define MV64360_PCI_0_ERROR_ADDR_LOW				    0x1d40
-#define MV64360_PCI_1_ERROR_ADDR_LOW				    0x1dc0
-#define MV64360_PCI_0_ERROR_ADDR_HIGH				    0x1d44
-#define MV64360_PCI_1_ERROR_ADDR_HIGH				    0x1dc4
-#define MV64360_PCI_0_ERROR_ATTRIBUTE				    0x1d48
-#define MV64360_PCI_1_ERROR_ATTRIBUTE				    0x1dc8
-#define MV64360_PCI_0_ERROR_COMMAND				    0x1d50
-#define MV64360_PCI_1_ERROR_COMMAND				    0x1dd0
-#define MV64360_PCI_0_ERROR_CAUSE				    0x1d58
-#define MV64360_PCI_1_ERROR_CAUSE				    0x1dd8
-#define MV64360_PCI_0_ERROR_MASK				    0x1d5c
-#define MV64360_PCI_1_ERROR_MASK				    0x1ddc
-
-/****************************************/
-/*   PCI Debug Registers		*/
-/****************************************/
-
-#define MV64360_PCI_0_MMASK					    0X1D24
-#define MV64360_PCI_1_MMASK					    0X1DA4
-
-/*********************************************/
-/* PCI Configuration, Function 0, Registers  */
-/*********************************************/
-
-#define MV64360_PCI_DEVICE_AND_VENDOR_ID			    0x000
-#define MV64360_PCI_STATUS_AND_COMMAND				    0x004
-#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID			    0x008
-#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	    0x00C
-
-#define MV64360_PCI_SCS_0_BASE_ADDR_LOW				    0x010
-#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH			    0x014
-#define MV64360_PCI_SCS_1_BASE_ADDR_LOW				    0x018
-#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH			    0x01C
-#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW	    0x020
-#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH	    0x024
-#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	    0x02c
-#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG			    0x030
-#define MV64360_PCI_CAPABILTY_LIST_POINTER			    0x034
-#define MV64360_PCI_INTERRUPT_PIN_AND_LINE			    0x03C
-       /* capability list */
-#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY			    0x040
-#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044
-#define MV64360_PCI_VPD_ADDR					    0x048
-#define MV64360_PCI_VPD_DATA					    0x04c
-#define MV64360_PCI_MSI_MESSAGE_CONTROL				    0x050
-#define MV64360_PCI_MSI_MESSAGE_ADDR				    0x054
-#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR			    0x058
-#define MV64360_PCI_MSI_MESSAGE_DATA				    0x05c
-#define MV64360_PCI_X_COMMAND					    0x060
-#define MV64360_PCI_X_STATUS					    0x064
-#define MV64360_PCI_COMPACT_PCI_HOT_SWAP			    0x068
-
-/***********************************************/
-/*   PCI Configuration, Function 1, Registers  */
-/***********************************************/
-
-#define MV64360_PCI_SCS_2_BASE_ADDR_LOW				    0x110
-#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH			    0x114
-#define MV64360_PCI_SCS_3_BASE_ADDR_LOW				    0x118
-#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH			    0x11c
-#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW			    0x120
-#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH		    0x124
-
-/***********************************************/
-/*  PCI Configuration, Function 2, Registers   */
-/***********************************************/
-
-#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW			    0x210
-#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH			    0x214
-#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW			    0x218
-#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH			    0x21c
-#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW			    0x220
-#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH			    0x224
-
-/***********************************************/
-/*  PCI Configuration, Function 3, Registers   */
-/***********************************************/
-
-#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW			    0x310
-#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH			    0x314
-#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW			    0x318
-#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH			    0x31c
-#define MV64360_PCI_CPU_BASE_ADDR_LOW				    0x220
-#define MV64360_PCI_CPU_BASE_ADDR_HIGH				    0x224
-
-/***********************************************/
-/*  PCI Configuration, Function 4, Registers   */
-/***********************************************/
-
-#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW			    0x410
-#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH			    0x414
-#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW			    0x418
-#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH			    0x41c
-#define MV64360_PCI_P2P_I_O_BASE_ADDR				    0x420
-#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR		    0x424
-
-/****************************************/
-/* Messaging Unit Registers (I20)	*/
-/****************************************/
-
-#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x010
-#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x014
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x018
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x01C
-#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE		    0x020
-#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x024
-#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x028
-#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE		    0x02C
-#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x030
-#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x034
-#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x040
-#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x044
-#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE		    0x050
-#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE		    0x054
-#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x060
-#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x064
-#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x068
-#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x06C
-#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x070
-#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x074
-#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x0F8
-#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x0FC
-
-#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x090
-#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x094
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x098
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x09C
-#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0A0
-#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0A4
-#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0A8
-#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0AC
-#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0B0
-#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0B4
-#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C0
-#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C4
-#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE		    0x0D0
-#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE		    0x0D4
-#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E0
-#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0E4
-#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E8
-#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x0EC
-#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0F0
-#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0F4
-#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x078
-#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x07C
-
-#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C10
-#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C14
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C18
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C1C
-#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C20
-#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C24
-#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C28
-#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C2C
-#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C30
-#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C34
-#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C40
-#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C44
-#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE			    0x1C50
-#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE		    0x1C54
-#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C60
-#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C64
-#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1C68
-#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1C6C
-#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C70
-#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C74
-#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1CF8
-#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1CFC
-#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C90
-#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C94
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C98
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C9C
-#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CA0
-#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CA4
-#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CA8
-#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CAC
-#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CB0
-#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CB4
-#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC0
-#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC4
-#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE			    0x1CD0
-#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE		    0x1CD4
-#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE0
-#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CE4
-#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE8
-#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1CEC
-#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CF0
-#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CF4
-#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1C78
-#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1C7C
-
-/****************************************/
-/*	  Ethernet Unit Registers		*/
-/****************************************/
-
-#define MV64360_ETH_PHY_ADDR_REG				    0x2000
-#define MV64360_ETH_SMI_REG					    0x2004
-#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG			    0x2008
-#define MV64360_ETH_UNIT_DEFAULTID_REG				    0x200c
-#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG			    0x2080
-#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG			    0x2084
-#define MV64360_ETH_UNIT_INTERNAL_USE_REG			    0x24fc
-#define MV64360_ETH_UNIT_ERROR_ADDR_REG				    0x2094
-#define MV64360_ETH_BAR_0					    0x2200
-#define MV64360_ETH_BAR_1					    0x2208
-#define MV64360_ETH_BAR_2					    0x2210
-#define MV64360_ETH_BAR_3					    0x2218
-#define MV64360_ETH_BAR_4					    0x2220
-#define MV64360_ETH_BAR_5					    0x2228
-#define MV64360_ETH_SIZE_REG_0					    0x2204
-#define MV64360_ETH_SIZE_REG_1					    0x220c
-#define MV64360_ETH_SIZE_REG_2					    0x2214
-#define MV64360_ETH_SIZE_REG_3					    0x221c
-#define MV64360_ETH_SIZE_REG_4					    0x2224
-#define MV64360_ETH_SIZE_REG_5					    0x222c
-#define MV64360_ETH_HEADERS_RETARGET_BASE_REG			    0x2230
-#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG		    0x2234
-#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0			    0x2280
-#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1			    0x2284
-#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2			    0x2288
-#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3			    0x228c
-#define MV64360_ETH_BASE_ADDR_ENABLE_REG			    0x2290
-#define MV64360_ETH_ACCESS_PROTECTION_REG(port)			   (0x2294 + (port<<2))
-#define MV64360_ETH_MIB_COUNTERS_BASE(port)			   (0x3000 + (port<<7))
-#define MV64360_ETH_PORT_CONFIG_REG(port)			   (0x2400 + (port<<10))
-#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port)		   (0x2404 + (port<<10))
-#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port)		   (0x2408 + (port<<10))
-#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port)		   (0x240c + (port<<10))
-#define MV64360_ETH_VLAN_ETHERTYPE_REG(port)			   (0x2410 + (port<<10))
-#define MV64360_ETH_MAC_ADDR_LOW(port)				   (0x2414 + (port<<10))
-#define MV64360_ETH_MAC_ADDR_HIGH(port)				   (0x2418 + (port<<10))
-#define MV64360_ETH_SDMA_CONFIG_REG(port)			   (0x241c + (port<<10))
-#define MV64360_ETH_DSCP_0(port)				   (0x2420 + (port<<10))
-#define MV64360_ETH_DSCP_1(port)				   (0x2424 + (port<<10))
-#define MV64360_ETH_DSCP_2(port)				   (0x2428 + (port<<10))
-#define MV64360_ETH_DSCP_3(port)				   (0x242c + (port<<10))
-#define MV64360_ETH_DSCP_4(port)				   (0x2430 + (port<<10))
-#define MV64360_ETH_DSCP_5(port)				   (0x2434 + (port<<10))
-#define MV64360_ETH_DSCP_6(port)				   (0x2438 + (port<<10))
-#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port)		   (0x243c + (port<<10))
-#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		   (0x2440 + (port<<10))
-#define MV64360_ETH_PORT_STATUS_REG(port)			   (0x2444 + (port<<10))
-#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port)		   (0x2448 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port)		   (0x244c + (port<<10))
-#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)	   (0x2450 + (port<<10))
-#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port)			   (0x2458 + (port<<10))
-#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)	   (0x245c + (port<<10))
-#define MV64360_ETH_INTERRUPT_CAUSE_REG(port)			   (0x2460 + (port<<10))
-#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port)		   (0x2464 + (port<<10))
-#define MV64360_ETH_INTERRUPT_MASK_REG(port)			   (0x2468 + (port<<10))
-#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port)		   (0x246c + (port<<10))
-#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2470 + (port<<10))
-#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2474 + (port<<10))
-#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port)		   (0x247c + (port<<10))
-#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port)		   (0x2484 + (port<<10)
-#define MV64360_ETH_PORT_DEBUG_0_REG(port)			   (0x248c + (port<<10))
-#define MV64360_ETH_PORT_DEBUG_1_REG(port)			   (0x2490 + (port<<10))
-#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)		   (0x2494 + (port<<10))
-#define MV64360_ETH_INTERNAL_USE_REG(port)			   (0x24fc + (port<<10))
-#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port)		   (0x2680 + (port<<10))
-#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port)		   (0x2684 + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x260c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x261c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x262c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x263c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x264c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x265c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x266c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x267c + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x26c0 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x26c4 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x26c8 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x26cc + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x26d0 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x26d4 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x26d8 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x26dc + (port<<10))
-#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)		   (0x2700 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)		   (0x2710 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)		   (0x2720 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)		   (0x2730 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)		   (0x2740 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)		   (0x2750 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)		   (0x2760 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)		   (0x2770 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)	   (0x2704 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)	   (0x2714 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)	   (0x2724 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)	   (0x2734 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)	   (0x2744 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)	   (0x2754 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)	   (0x2764 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)	   (0x2774 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port)		   (0x2708 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port)		   (0x2718 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port)		   (0x2728 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port)		   (0x2738 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port)		   (0x2748 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port)		   (0x2758 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port)		   (0x2768 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port)		   (0x2778 + (port<<10))
-#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)		   (0x2780 + (port<<10))
-#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
-#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)	   (0x3500 + (port<<10))
-#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port)		   (0x3600 + (port<<10))
-
-/*******************************************/
-/*	    CUNIT  Registers		   */
-/*******************************************/
-
-	 /* Address Decoding Register Map */
-
-#define MV64360_CUNIT_BASE_ADDR_REG0				    0xf200
-#define MV64360_CUNIT_BASE_ADDR_REG1				    0xf208
-#define MV64360_CUNIT_BASE_ADDR_REG2				    0xf210
-#define MV64360_CUNIT_BASE_ADDR_REG3				    0xf218
-#define MV64360_CUNIT_SIZE0					    0xf204
-#define MV64360_CUNIT_SIZE1					    0xf20c
-#define MV64360_CUNIT_SIZE2					    0xf214
-#define MV64360_CUNIT_SIZE3					    0xf21c
-#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0			    0xf240
-#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1			    0xf244
-#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG			    0xf250
-#define MV64360_MPSC0_ACCESS_PROTECTION_REG			    0xf254
-#define MV64360_MPSC1_ACCESS_PROTECTION_REG			    0xf258
-#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG		    0xf25C
-
-	/*  Error Report Registers  */
-
-#define MV64360_CUNIT_INTERRUPT_CAUSE_REG			    0xf310
-#define MV64360_CUNIT_INTERRUPT_MASK_REG			    0xf314
-#define MV64360_CUNIT_ERROR_ADDR				    0xf318
-
-	/*  Cunit Control Registers */
-
-#define MV64360_CUNIT_ARBITER_CONTROL_REG			    0xf300
-#define MV64360_CUNIT_CONFIG_REG				    0xb40c
-#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG			    0xf304
-
-	/*  Cunit Debug Registers   */
-
-#define MV64360_CUNIT_DEBUG_LOW					    0xf340
-#define MV64360_CUNIT_DEBUG_HIGH				    0xf344
-#define MV64360_CUNIT_MMASK					    0xf380
-
-	/*  Cunit Base Address Enable Window Bits*/
-#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT			 0x0
-#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT			 0x1
-#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT			 0x2
-#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT			 0x3
-
-	/*  MPSCs Clocks Routing Registers  */
-
-#define MV64360_MPSC_ROUTING_REG				    0xb400
-#define MV64360_MPSC_RX_CLOCK_ROUTING_REG			    0xb404
-#define MV64360_MPSC_TX_CLOCK_ROUTING_REG			    0xb408
-
-	/*  MPSCs Interrupts Registers	  */
-
-#define MV64360_MPSC_CAUSE_REG(port)				   (0xb804 + (port<<3))
-#define MV64360_MPSC_MASK_REG(port)				   (0xb884 + (port<<3))
-
-#define MV64360_MPSC_MAIN_CONFIG_LOW(port)			   (0x8000 + (port<<12))
-#define MV64360_MPSC_MAIN_CONFIG_HIGH(port)			   (0x8004 + (port<<12))
-#define MV64360_MPSC_PROTOCOL_CONFIG(port)			   (0x8008 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG1(port)				   (0x800c + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG2(port)				   (0x8010 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG3(port)				   (0x8014 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG4(port)				   (0x8018 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG5(port)				   (0x801c + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG6(port)				   (0x8020 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG7(port)				   (0x8024 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG8(port)				   (0x8028 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG9(port)				   (0x802c + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG10(port)			   (0x8030 + (port<<12))
-
-	/*  MPSC0 Registers	 */
-
-
-/***************************************/
-/*	    SDMA Registers	       */
-/***************************************/
-
-#define MV64360_SDMA_CONFIG_REG(channel)			(0x4000 + (channel<<13))
-#define MV64360_SDMA_COMMAND_REG(channel)			(0x4008 + (channel<<13))
-#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)	(0x4810 + (channel<<13))
-#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
-#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))
-
-#define MV64360_SDMA_CAUSE_REG					    0xb800
-#define MV64360_SDMA_MASK_REG					    0xb880
-
-
-/****************************************/
-/* SDMA Address Space Targets		*/
-/****************************************/
-
-#define MV64360_SDMA_DRAM_CS_0_TARGET				    0x0e00
-#define MV64360_SDMA_DRAM_CS_1_TARGET				    0x0d00
-#define MV64360_SDMA_DRAM_CS_2_TARGET				    0x0b00
-#define MV64360_SDMA_DRAM_CS_3_TARGET				    0x0700
-
-#define MV64360_SDMA_DEV_CS_0_TARGET				    0x1e01
-#define MV64360_SDMA_DEV_CS_1_TARGET				    0x1d01
-#define MV64360_SDMA_DEV_CS_2_TARGET				    0x1b01
-#define MV64360_SDMA_DEV_CS_3_TARGET				    0x1701
-
-#define MV64360_SDMA_BOOT_CS_TARGET				    0x0f00
-
-#define MV64360_SDMA_SRAM_TARGET				    0x0003
-#define MV64360_SDMA_60X_BUS_TARGET				    0x4003
-
-#define MV64360_PCI_0_TARGET					    0x0003
-#define MV64360_PCI_1_TARGET					    0x0004
-
-
-/* Devices BAR and size registers */
-
-#define MV64360_DEV_CS0_BASE_ADDR				    0x028
-#define MV64360_DEV_CS0_SIZE					    0x030
-#define MV64360_DEV_CS1_BASE_ADDR				    0x228
-#define MV64360_DEV_CS1_SIZE					    0x230
-#define MV64360_DEV_CS2_BASE_ADDR				    0x248
-#define MV64360_DEV_CS2_SIZE					    0x250
-#define MV64360_DEV_CS3_BASE_ADDR				    0x038
-#define MV64360_DEV_CS3_SIZE					    0x040
-#define MV64360_BOOTCS_BASE_ADDR				    0x238
-#define MV64360_BOOTCS_SIZE					    0x240
-
-/* SDMA Window access protection */
-#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0
-#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1
-#define MV64360_SDMA_WIN_ACCESS_FULL 2
-
-/* BRG Interrupts */
-
-#define MV64360_BRG_CONFIG_REG(brg)				 (0xb200 + (brg<<3))
-#define MV64360_BRG_BAUDE_TUNING_REG(brg)			 (0xb204 + (brg<<3))
-#define MV64360_BRG_CAUSE_REG					    0xb834
-#define MV64360_BRG_MASK_REG					    0xb8b4
-
-/****************************************/
-/* DMA Channel Control			*/
-/****************************************/
-
-#define MV64360_DMA_CHANNEL0_CONTROL				    0x840
-#define MV64360_DMA_CHANNEL0_CONTROL_HIGH			    0x880
-#define MV64360_DMA_CHANNEL1_CONTROL				    0x844
-#define MV64360_DMA_CHANNEL1_CONTROL_HIGH			    0x884
-#define MV64360_DMA_CHANNEL2_CONTROL				    0x848
-#define MV64360_DMA_CHANNEL2_CONTROL_HIGH			    0x888
-#define MV64360_DMA_CHANNEL3_CONTROL				    0x84C
-#define MV64360_DMA_CHANNEL3_CONTROL_HIGH			    0x88C
-
-
-/****************************************/
-/*	     IDMA Registers		*/
-/****************************************/
-
-#define MV64360_DMA_CHANNEL0_BYTE_COUNT				    0x800
-#define MV64360_DMA_CHANNEL1_BYTE_COUNT				    0x804
-#define MV64360_DMA_CHANNEL2_BYTE_COUNT				    0x808
-#define MV64360_DMA_CHANNEL3_BYTE_COUNT				    0x80C
-#define MV64360_DMA_CHANNEL0_SOURCE_ADDR			    0x810
-#define MV64360_DMA_CHANNEL1_SOURCE_ADDR			    0x814
-#define MV64360_DMA_CHANNEL2_SOURCE_ADDR			    0x818
-#define MV64360_DMA_CHANNEL3_SOURCE_ADDR			    0x81c
-#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR			    0x820
-#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR			    0x824
-#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR			    0x828
-#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR			    0x82C
-#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		    0x830
-#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		    0x834
-#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		    0x838
-#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		    0x83C
-#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		    0x870
-#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		    0x874
-#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		    0x878
-#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		    0x87C
-
- /*  IDMA Address Decoding Base Address Registers  */
-
-#define MV64360_DMA_BASE_ADDR_REG0				    0xa00
-#define MV64360_DMA_BASE_ADDR_REG1				    0xa08
-#define MV64360_DMA_BASE_ADDR_REG2				    0xa10
-#define MV64360_DMA_BASE_ADDR_REG3				    0xa18
-#define MV64360_DMA_BASE_ADDR_REG4				    0xa20
-#define MV64360_DMA_BASE_ADDR_REG5				    0xa28
-#define MV64360_DMA_BASE_ADDR_REG6				    0xa30
-#define MV64360_DMA_BASE_ADDR_REG7				    0xa38
-
- /*  IDMA Address Decoding Size Address Register   */
-
-#define MV64360_DMA_SIZE_REG0					    0xa04
-#define MV64360_DMA_SIZE_REG1					    0xa0c
-#define MV64360_DMA_SIZE_REG2					    0xa14
-#define MV64360_DMA_SIZE_REG3					    0xa1c
-#define MV64360_DMA_SIZE_REG4					    0xa24
-#define MV64360_DMA_SIZE_REG5					    0xa2c
-#define MV64360_DMA_SIZE_REG6					    0xa34
-#define MV64360_DMA_SIZE_REG7					    0xa3C
-
- /* IDMA Address Decoding High Address Remap and Access
-		  Protection Registers			  */
-
-#define MV64360_DMA_HIGH_ADDR_REMAP_REG0			    0xa60
-#define MV64360_DMA_HIGH_ADDR_REMAP_REG1			    0xa64
-#define MV64360_DMA_HIGH_ADDR_REMAP_REG2			    0xa68
-#define MV64360_DMA_HIGH_ADDR_REMAP_REG3			    0xa6C
-#define MV64360_DMA_BASE_ADDR_ENABLE_REG			    0xa80
-#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG		    0xa70
-#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG		    0xa74
-#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG		    0xa78
-#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG		    0xa7c
-#define MV64360_DMA_ARBITER_CONTROL				    0x860
-#define MV64360_DMA_CROSS_BAR_TIMEOUT				    0x8d0
-
- /*  IDMA Headers Retarget Registers   */
-
-#define MV64360_DMA_HEADERS_RETARGET_CONTROL			    0xa84
-#define MV64360_DMA_HEADERS_RETARGET_BASE			    0xa88
-
- /*  IDMA Interrupt Register  */
-
-#define MV64360_DMA_INTERRUPT_CAUSE_REG				    0x8c0
-#define MV64360_DMA_INTERRUPT_CAUSE_MASK			    0x8c4
-#define MV64360_DMA_ERROR_ADDR					    0x8c8
-#define MV64360_DMA_ERROR_SELECT				    0x8cc
-
- /*  IDMA Debug Register ( for internal use )	 */
-
-#define MV64360_DMA_DEBUG_LOW					    0x8e0
-#define MV64360_DMA_DEBUG_HIGH					    0x8e4
-#define MV64360_DMA_SPARE					    0xA8C
-
-/****************************************/
-/* Timer_Counter			*/
-/****************************************/
-
-#define MV64360_TIMER_COUNTER0					    0x850
-#define MV64360_TIMER_COUNTER1					    0x854
-#define MV64360_TIMER_COUNTER2					    0x858
-#define MV64360_TIMER_COUNTER3					    0x85C
-#define MV64360_TIMER_COUNTER_0_3_CONTROL			    0x864
-#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE		    0x868
-#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK		    0x86c
-
-/****************************************/
-/*	   Watchdog registers		*/
-/****************************************/
-
-#define MV64360_WATCHDOG_CONFIG_REG				    0xb410
-#define MV64360_WATCHDOG_VALUE_REG				    0xb414
-
-/****************************************/
-/* I2C Registers			*/
-/****************************************/
-
-#define MV64360_I2C_SLAVE_ADDR					    0xc000
-#define MV64360_I2C_EXTENDED_SLAVE_ADDR				    0xc010
-#define MV64360_I2C_DATA					    0xc004
-#define MV64360_I2C_CONTROL					    0xc008
-#define MV64360_I2C_STATUS_BAUDE_RATE				    0xc00C
-#define MV64360_I2C_SOFT_RESET					    0xc01c
-
-/****************************************/
-/* GPP Interface Registers		*/
-/****************************************/
-
-#define MV64360_GPP_IO_CONTROL					    0xf100
-#define MV64360_GPP_LEVEL_CONTROL				    0xf110
-#define MV64360_GPP_VALUE					    0xf104
-#define MV64360_GPP_INTERRUPT_CAUSE				    0xf108
-#define MV64360_GPP_INTERRUPT_MASK0				    0xf10c
-#define MV64360_GPP_INTERRUPT_MASK1				    0xf114
-#define MV64360_GPP_VALUE_SET					    0xf118
-#define MV64360_GPP_VALUE_CLEAR					    0xf11c
-
-/****************************************/
-/* Interrupt Controller Registers	*/
-/****************************************/
-
-/****************************************/
-/* Interrupts				*/
-/****************************************/
-
-#define MV64360_MAIN_INTERRUPT_CAUSE_LOW			    0x004
-#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH			    0x00c
-#define MV64360_CPU_INTERRUPT0_MASK_LOW				    0x014
-#define MV64360_CPU_INTERRUPT0_MASK_HIGH			    0x01c
-#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE			    0x024
-#define MV64360_CPU_INTERRUPT1_MASK_LOW				    0x034
-#define MV64360_CPU_INTERRUPT1_MASK_HIGH			    0x03c
-#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE			    0x044
-#define MV64360_INTERRUPT0_MASK_0_LOW				    0x054
-#define MV64360_INTERRUPT0_MASK_0_HIGH				    0x05c
-#define MV64360_INTERRUPT0_SELECT_CAUSE				    0x064
-#define MV64360_INTERRUPT1_MASK_0_LOW				    0x074
-#define MV64360_INTERRUPT1_MASK_0_HIGH				    0x07c
-#define MV64360_INTERRUPT1_SELECT_CAUSE				    0x084
-
-/****************************************/
-/*	MPP Interface Registers		*/
-/****************************************/
-
-#define MV64360_MPP_CONTROL0					    0xf000
-#define MV64360_MPP_CONTROL1					    0xf004
-#define MV64360_MPP_CONTROL2					    0xf008
-#define MV64360_MPP_CONTROL3					    0xf00c
-
-/****************************************/
-/*    Serial Initialization registers	*/
-/****************************************/
-
-#define MV64360_SERIAL_INIT_LAST_DATA				    0xf324
-#define MV64360_SERIAL_INIT_CONTROL				    0xf328
-#define MV64360_SERIAL_INIT_STATUS				    0xf32c
-
-
-#endif /* __INCgt64360rh */
diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c
deleted file mode 100644
index 59f170a0df7..00000000000
--- a/board/esd/cpci750/pci.c
+++ /dev/null
@@ -1,1028 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/* PCI.c - PCI functions */
-
-
-#include <common.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-
-#include "../../Marvell/include/pci.h"
-
-#undef DEBUG
-#undef IDE_SET_NATIVE_MODE
-static unsigned int local_buses[] = { 0, 0 };
-
-static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
-	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
-	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
-};
-
-#ifdef CONFIG_USE_CPCIDVI
-typedef struct {
-	unsigned int base;
-	unsigned int init;
-} GT_CPCIDVI_ROM_T;
-
-static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
-#endif
-
-#ifdef DEBUG
-static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
-static void gt_pci_bus_mode_display (PCI_HOST host)
-{
-	unsigned int mode;
-
-
-	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
-	switch (mode) {
-	case 0:
-		printf ("PCI %d bus mode: Conventional PCI\n", host);
-		break;
-	case 1:
-		printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
-		break;
-	case 2:
-		printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
-		break;
-	case 3:
-		printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
-		break;
-	default:
-		printf ("Unknown BUS %d\n", mode);
-	}
-}
-#endif
-
-static const unsigned int pci_p2p_configuration_reg[] = {
-	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-static const unsigned int pci_configuration_address[] = {
-	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
-};
-
-static const unsigned int pci_configuration_data[] = {
-	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
-	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
-};
-
-static const unsigned int pci_error_cause_reg[] = {
-	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
-};
-
-static const unsigned int pci_arbiter_control[] = {
-	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
-};
-
-static const unsigned int pci_address_space_en[] = {
-	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
-};
-
-static const unsigned int pci_snoop_control_base_0_low[] = {
-	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_snoop_control_top_0[] = {
-	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
-};
-
-static const unsigned int pci_access_control_base_0_low[] = {
-	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_access_control_top_0[] = {
-	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
-};
-
-static const unsigned int pci_scs_bank_size[2][4] = {
-	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
-	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
-	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
-	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
-};
-
-static const unsigned int pci_p2p_configuration[] = {
-	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-
-/********************************************************************
-* pciWriteConfigReg - Write to a PCI configuration register
-*		    - Make sure the GT is configured as a master before writing
-*		      to another device on the PCI.
-*		    - The function takes care of Big/Little endian conversion.
-*
-*
-* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
-*		   (or any other PCI device spec)
-*	    pciDevNum: The device number needs to be addressed.
-*
-*  Configuration Address 0xCF8:
-*
-*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|00|
-*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
-*
-*********************************************************************/
-void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
-			unsigned int pciDevNum, unsigned int data)
-{
-	volatile unsigned int DataForAddrReg;
-	unsigned int functionNum;
-	unsigned int busNum = 0;
-	unsigned int addr;
-
-	if (pciDevNum > 32)	/* illegal device Number */
-		return;
-	if (pciDevNum == SELF) {	/* configure our configuration space. */
-		pciDevNum =
-			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
-			0x1f;
-		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
-			0xff0000;
-	}
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xfc;
-	DataForAddrReg =
-		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
-	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
-	GT_REG_READ (pci_configuration_address[host], &addr);
-	if (addr != DataForAddrReg)
-		return;
-	GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-/********************************************************************
-* pciReadConfigReg  - Read from a PCI0 configuration register
-*		    - Make sure the GT is configured as a master before reading
-*		      from another device on the PCI.
-*		    - The function takes care of Big/Little endian conversion.
-* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
-*			spec)
-*	    pciDevNum: The device number needs to be addressed.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-*		  cause register to make sure the data is valid
-*
-*  Configuration Address 0xCF8:
-*
-*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|00|
-*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
-*
-*********************************************************************/
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
-			       unsigned int pciDevNum)
-{
-	volatile unsigned int DataForAddrReg;
-	unsigned int data;
-	unsigned int functionNum;
-	unsigned int busNum = 0;
-
-	if (pciDevNum > 32)	/* illegal device Number */
-		return 0xffffffff;
-	if (pciDevNum == SELF) {	/* configure our configuration space. */
-		pciDevNum =
-			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
-			0x1f;
-		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
-			0xff0000;
-	}
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xfc;
-	DataForAddrReg =
-		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
-	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
-	GT_REG_READ (pci_configuration_address[host], &data);
-	if (data != DataForAddrReg)
-		return 0xffffffff;
-	GT_REG_READ (pci_configuration_data[host], &data);
-	return data;
-}
-
-/********************************************************************
-* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
-*				the agent is placed on another Bus. For more
-*				information read P2P in the PCI spec.
-*
-* Inputs:   unsigned int regOffset - The register offset as it apears in the
-*	    GT spec (or any other PCI device spec).
-*	    unsigned int pciDevNum - The device number needs to be addressed.
-*	    unsigned int busNum - On which bus does the Target agent connect
-*				  to.
-*	    unsigned int data - data to be written.
-*
-*  Configuration Address 0xCF8:
-*
-*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|01|
-*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
-*
-*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
-*   PCI spec referring to P2P.
-*
-*********************************************************************/
-void pciOverBridgeWriteConfigReg (PCI_HOST host,
-				  unsigned int regOffset,
-				  unsigned int pciDevNum,
-				  unsigned int busNum, unsigned int data)
-{
-	unsigned int DataForReg;
-	unsigned int functionNum;
-
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xff;
-	busNum = busNum << 16;
-	if (pciDevNum == SELF) {	/* This board */
-		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
-	} else {
-		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
-			BIT31 | BIT0;
-	}
-	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
-	GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-
-/********************************************************************
-* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
-*				the agent target locate on another PCI bus.
-*			      - Make sure the GT is configured as a master
-*				before reading from another device on the PCI.
-*			      - The function takes care of Big/Little endian
-*				conversion.
-* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
-*			 spec). (configuration register offset.)
-*	    pciDevNum: The device number needs to be addressed.
-*	    busNum: the Bus number where the agent is place.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-*		  cause register to make sure the data is valid
-*
-*  Configuration Address 0xCF8:
-*
-*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|01|
-*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
-*
-*********************************************************************/
-unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
-					 unsigned int regOffset,
-					 unsigned int pciDevNum,
-					 unsigned int busNum)
-{
-	unsigned int DataForReg;
-	unsigned int data;
-	unsigned int functionNum;
-
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xff;
-	busNum = busNum << 16;
-	if (pciDevNum == SELF) {	/* This board */
-		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
-	} else {		/* agent on another bus */
-
-		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
-			BIT0 | BIT31;
-	}
-	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
-	GT_REG_READ (pci_configuration_data[host], &data);
-	return data;
-}
-
-
-/********************************************************************
-* pciGetRegOffset - Gets the register offset for this region config.
-*
-* INPUT:   Bus, Region - The bus and region we ask for its base address.
-* OUTPUT:   N/A
-* RETURNS: PCI register base address
-*********************************************************************/
-static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
-{
-	switch (host) {
-	case PCI_HOST0:
-		switch (region) {
-		case PCI_IO:
-			return PCI_0I_O_LOW_DECODE_ADDRESS;
-		case PCI_REGION0:
-			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-		case PCI_REGION1:
-			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
-		case PCI_REGION2:
-			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
-		case PCI_REGION3:
-			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
-		}
-	case PCI_HOST1:
-		switch (region) {
-		case PCI_IO:
-			return PCI_1I_O_LOW_DECODE_ADDRESS;
-		case PCI_REGION0:
-			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
-		case PCI_REGION1:
-			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
-		case PCI_REGION2:
-			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
-		case PCI_REGION3:
-			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
-		}
-	}
-	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-}
-
-static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
-{
-	switch (host) {
-	case PCI_HOST0:
-		switch (region) {
-		case PCI_IO:
-			return PCI_0I_O_ADDRESS_REMAP;
-		case PCI_REGION0:
-			return PCI_0MEMORY0_ADDRESS_REMAP;
-		case PCI_REGION1:
-			return PCI_0MEMORY1_ADDRESS_REMAP;
-		case PCI_REGION2:
-			return PCI_0MEMORY2_ADDRESS_REMAP;
-		case PCI_REGION3:
-			return PCI_0MEMORY3_ADDRESS_REMAP;
-		}
-	case PCI_HOST1:
-		switch (region) {
-		case PCI_IO:
-			return PCI_1I_O_ADDRESS_REMAP;
-		case PCI_REGION0:
-			return PCI_1MEMORY0_ADDRESS_REMAP;
-		case PCI_REGION1:
-			return PCI_1MEMORY1_ADDRESS_REMAP;
-		case PCI_REGION2:
-			return PCI_1MEMORY2_ADDRESS_REMAP;
-		case PCI_REGION3:
-			return PCI_1MEMORY3_ADDRESS_REMAP;
-		}
-	}
-	return PCI_0MEMORY0_ADDRESS_REMAP;
-}
-
-/********************************************************************
-* pciGetBaseAddress - Gets the base address of a PCI.
-*	    - If the PCI size is 0 then this base address has no meaning!!!
-*
-*
-* INPUT:   Bus, Region - The bus and region we ask for its base address.
-* OUTPUT:   N/A
-* RETURNS: PCI base address.
-*********************************************************************/
-unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int regBase;
-	unsigned int regEnd;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &regBase);
-	GT_REG_READ (regOffset + 8, &regEnd);
-
-	if (regEnd <= regBase)
-		return 0xffffffff;	/* ERROR !!! */
-
-	regBase = regBase << 16;
-	return regBase;
-}
-
-bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
-		  unsigned int bankBase, unsigned int bankLength)
-{
-	unsigned int low = 0xfff;
-	unsigned int high = 0x0;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-	unsigned int remapOffset = pciGetRemapOffset (host, region);
-
-	if (bankLength != 0) {
-		low = (bankBase >> 16) & 0xffff;
-		high = ((bankBase + bankLength) >> 16) - 1;
-	}
-
-	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
-	GT_REG_WRITE (regOffset + 8, high);
-
-	if (bankLength != 0) {	/* must do AFTER writing maps */
-		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
-								   dont support upper 32
-								   in this driver */
-	}
-	return true;
-}
-
-unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int low;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &low);
-	return (low & 0xffff) << 16;
-}
-
-unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int low, high;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &low);
-	GT_REG_READ (regOffset + 8, &high);
-	return ((high & 0xffff) + 1) << 16;
-}
-
-
-/* ronen - 7/Dec/03*/
-/********************************************************************
-* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
-* Inputs: one of the PCI BAR
-*********************************************************************/
-void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
-	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
-	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-/********************************************************************
-* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
-*
-* Inputs: base and size of PCI SCS
-*********************************************************************/
-void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
-		       unsigned int pciDramBase, unsigned int pciDramSize)
-{
-	/*ronen different function for 3rd bank. */
-	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
-
-	pciDramBase = pciDramBase & 0xfffff000;
-	pciDramBase = pciDramBase | (pciReadConfigReg (host,
-						       PCI_SCS_0_BASE_ADDRESS
-						       + offset,
-						       SELF) & 0x00000fff);
-	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
-			   pciDramBase);
-	if (pciDramSize == 0)
-		pciDramSize++;
-	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
-	gtPciEnableInternalBAR (host, bank);
-}
-
-/********************************************************************
-* pciSetRegionFeatures - This function modifys one of the 8 regions with
-*			  feature bits given as an input.
-*			- Be advised to check the spec before modifying them.
-* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
-*	  unsigned int features - See file: pci.h there are defintion for those
-*				  region features.
-*	  unsigned int baseAddress - The region base Address.
-*	  unsigned int topAddress - The region top Address.
-* Returns: false if one of the parameters is erroneous true otherwise.
-*********************************************************************/
-bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
-			   unsigned int features, unsigned int baseAddress,
-			   unsigned int regionLength)
-{
-	unsigned int accessLow;
-	unsigned int accessHigh;
-	unsigned int accessTop = baseAddress + regionLength;
-
-	if (regionLength == 0) {	/* close the region. */
-		pciDisableAccessRegion (host, region);
-		return true;
-	}
-	/* base Address is store is bits [11:0] */
-	accessLow = (baseAddress & 0xfff00000) >> 20;
-	/* All the features are update according to the defines in pci.h (to be on
-	   the safe side we disable bits: [11:0] */
-	accessLow = accessLow | (features & 0xfffff000);
-	/* write to the Low Access Region register */
-	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
-		      accessLow);
-
-	accessHigh = (accessTop & 0xfff00000) >> 20;
-
-	/* write to the High Access Region register */
-	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
-		      accessHigh - 1);
-	return true;
-}
-
-/********************************************************************
-* pciDisableAccessRegion - Disable The given Region by writing MAX size
-*			    to its low Address and MIN size to its high Address.
-*
-* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
-* Returns:  N/A.
-*********************************************************************/
-void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
-{
-	/* writing back the registers default values. */
-	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
-		      0x01001fff);
-	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
-}
-
-/********************************************************************
-* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
-*
-* Inputs:   N/A
-* Returns:  true.
-*********************************************************************/
-bool pciArbiterEnable (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
-	return true;
-}
-
-/********************************************************************
-* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
-*
-* Inputs:   N/A
-* Returns:  true
-*********************************************************************/
-bool pciArbiterDisable (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
-	return true;
-}
-
-/********************************************************************
-* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
-*
-* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
-*	    PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
-*	    PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
-*	    PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
-*	    PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
-*	    PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
-*	    PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
-* Returns:  true
-*********************************************************************/
-bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
-				  PCI_AGENT_PRIO externalAgent0,
-				  PCI_AGENT_PRIO externalAgent1,
-				  PCI_AGENT_PRIO externalAgent2,
-				  PCI_AGENT_PRIO externalAgent3,
-				  PCI_AGENT_PRIO externalAgent4,
-				  PCI_AGENT_PRIO externalAgent5)
-{
-	unsigned int regData;
-	unsigned int writeData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
-		(externalAgent1 << 9) + (externalAgent2 << 10) +
-		(externalAgent3 << 11) + (externalAgent4 << 12) +
-		(externalAgent5 << 13);
-	regData = (regData & 0xffffc07f) | writeData;
-	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
-	return true;
-}
-
-/********************************************************************
-* pciParkingDisable - Park on last option disable, with this function you can
-*		       disable the park on last mechanism for each agent.
-*		       disabling this option for all agents results parking
-*		       on the internal master.
-*
-* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
-*	  PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
-*	  PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
-*	  PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
-*	  PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
-*	  PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
-*	  PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
-* Returns:  true
-*********************************************************************/
-bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
-			PCI_AGENT_PARK externalAgent0,
-			PCI_AGENT_PARK externalAgent1,
-			PCI_AGENT_PARK externalAgent2,
-			PCI_AGENT_PARK externalAgent3,
-			PCI_AGENT_PARK externalAgent4,
-			PCI_AGENT_PARK externalAgent5)
-{
-	unsigned int regData;
-	unsigned int writeData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
-		(externalAgent1 << 16) + (externalAgent2 << 17) +
-		(externalAgent3 << 18) + (externalAgent4 << 19) +
-		(externalAgent5 << 20);
-	regData = (regData & ~(0x7f << 14)) | writeData;
-	GT_REG_WRITE (pci_arbiter_control[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
-*			respond to grant assertion within a window specified in
-*			the input value: 'brokenValue'.
-*
-* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
-*			grant without asserting frame.
-* Returns:  Error for illegal broken value otherwise true.
-*********************************************************************/
-bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
-{
-	unsigned int data;
-	unsigned int regData;
-
-	if (brokenValue > 0xf)
-		return false;	/* brokenValue must be 4 bit */
-	data = brokenValue << 3;
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	regData = (regData & 0xffffff87) | data;
-	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
-	return true;
-}
-
-/********************************************************************
-* pciDisableBrokenAgentDetection - This function disable the Broken agent
-*			    Detection mechanism.
-*			    NOTE: This operation may cause a dead lock on the
-*			    pci0 arbitration.
-*
-* Inputs:   N/A
-* Returns:  true.
-*********************************************************************/
-bool pciDisableBrokenAgentDetection (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	regData = regData & 0xfffffffd;
-	GT_REG_WRITE (pci_arbiter_control[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciP2PConfig - This function set the PCI_n P2P configurate.
-*		  For more information on the P2P read PCI spec.
-*
-* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
-*				       Boundry.
-*	   unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
-*				       Boundry.
-*	   unsigned int busNum - The CPI bus number to which the PCI interface
-*				       is connected.
-*	   unsigned int devNum - The PCI interface's device number.
-*
-* Returns:  true.
-*********************************************************************/
-bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
-		   unsigned int SecondBusHigh,
-		   unsigned int busNum, unsigned int devNum)
-{
-	unsigned int regData;
-
-	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
-		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
-	GT_REG_WRITE (pci_p2p_configuration[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
-*			   supports Cache Coherency in the PCI_n interface.
-* Inputs: region - One of the four regions.
-*	  snoopType - There is four optional Types:
-*			 1. No Snoop.
-*			 2. Snoop to WT region.
-*			 3. Snoop to WB region.
-*			 4. Snoop & Invalidate to WB region.
-*	  baseAddress - Base Address of this region.
-*	  regionLength - Region length.
-* Returns: false if one of the parameters is wrong otherwise return true.
-*********************************************************************/
-bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
-			    PCI_SNOOP_TYPE snoopType,
-			    unsigned int baseAddress,
-			    unsigned int regionLength)
-{
-	unsigned int snoopXbaseAddress;
-	unsigned int snoopXtopAddress;
-	unsigned int data;
-	unsigned int snoopHigh = baseAddress + regionLength;
-
-	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
-		return false;
-	snoopXbaseAddress =
-		pci_snoop_control_base_0_low[host] + 0x10 * region;
-	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
-	if (regionLength == 0) {	/* closing the region */
-		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
-		GT_REG_WRITE (snoopXtopAddress, 0);
-		return true;
-	}
-	baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
-	data = (baseAddress >> 20) | snoopType << 12;
-	GT_REG_WRITE (snoopXbaseAddress, data);
-	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
-	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
-	return true;
-}
-
-static int gt_read_config_dword (struct pci_controller *hose,
-				 pci_dev_t dev, int offset, u32 * value)
-{
-	int bus = PCI_BUS (dev);
-
-	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
-		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr,
-					   offset | (PCI_FUNC(dev) << 8),
-					   PCI_DEV (dev));
-	} else {
-		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->cfg_addr,
-						     offset | (PCI_FUNC(dev) << 8),
-						     PCI_DEV (dev), bus);
-	}
-
-	return 0;
-}
-
-static int gt_write_config_dword (struct pci_controller *hose,
-				  pci_dev_t dev, int offset, u32 value)
-{
-	int bus = PCI_BUS (dev);
-
-	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
-		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr,
-				   offset | (PCI_FUNC(dev) << 8),
-				   PCI_DEV (dev), value);
-	} else {
-		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
-					     offset | (PCI_FUNC(dev) << 8),
-					     PCI_DEV (dev), bus,
-					     value);
-	}
-	return 0;
-}
-
-
-static void gt_setup_ide (struct pci_controller *hose,
-			  pci_dev_t dev, struct pci_config_table *entry)
-{
-	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
-	u32 bar_response, bar_value;
-	int bar;
-
-	if (CPCI750_SLAVE_TEST != 0)
-		return;
-
-	for (bar = 0; bar < 6; bar++) {
-		/*ronen different function for 3rd bank. */
-		unsigned int offset =
-			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
-
-		pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
-					     0x0);
-		pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
-					    &bar_response);
-
-		pciauto_region_allocate (bar_response &
-					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
-					 pci_io : hose->pci_mem, ide_bar[bar],
-					 &bar_value);
-
-		pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
-					     bar_value);
-	}
-}
-
-#ifdef CONFIG_USE_CPCIDVI
-static void gt_setup_cpcidvi (struct pci_controller *hose,
-			      pci_dev_t dev, struct pci_config_table *entry)
-{
-	u32		  bar_value, pci_response;
-
-	if (CPCI750_SLAVE_TEST != 0)
-		return;
-
-	pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
-	pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
-	pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
-	pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
-	pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
-	pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
-	pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
-	pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
-	gt_cpcidvi_rom.base = bar_value & 0xffffff00;
-	gt_cpcidvi_rom.init = 1;
-}
-
-unsigned char gt_cpcidvi_in8(unsigned int offset)
-{
-	unsigned char	  data;
-
-	if (gt_cpcidvi_rom.init == 0) {
-		return(0);
-		}
-	data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
-	return(data);
-}
-
-void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
-{
-	unsigned int	  off;
-
-	if (gt_cpcidvi_rom.init == 0) {
-		return;
-	}
-	off = data;
-	off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
-	in8(off);
-	return;
-}
-#endif
-
-/* TODO BJW: Change this for DB64360. This was pulled from the EV64260	*/
-/* and is curently not called *. */
-#if 0
-static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
-{
-	unsigned char pin, irq;
-
-	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
-
-	if (pin == 1) {		/* only allow INT A */
-		irq = pci_irq_swizzle[(PCI_HOST) hose->
-				      cfg_addr][PCI_DEV (dev)];
-		if (irq)
-			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
-	}
-}
-#endif
-
-struct pci_config_table gt_config_table[] = {
-#ifdef CONFIG_USE_CPCIDVI
-	{PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
-	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
-#endif
-	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
-	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
-	{}
-};
-
-struct pci_controller pci0_hose = {
-/*    fixup_irq: gt_fixup_irq, */
-	config_table:gt_config_table,
-};
-
-struct pci_controller pci1_hose = {
-/*    fixup_irq: gt_fixup_irq, */
-	config_table:gt_config_table,
-};
-
-void pci_init_board (void)
-{
-	unsigned int command;
-	unsigned int slave;
-#ifdef CONFIG_PCI_PNP
-	unsigned int bar;
-#endif
-#ifdef DEBUG
-	gt_pci_bus_mode_display (PCI_HOST0);
-#endif
-#ifdef CONFIG_USE_CPCIDVI
-	gt_cpcidvi_rom.init = 0;
-	gt_cpcidvi_rom.base = 0;
-#endif
-
-	slave = CPCI750_SLAVE_TEST;
-
-	pci0_hose.config_table = gt_config_table;
-	pci1_hose.config_table = gt_config_table;
-
-#ifdef CONFIG_USE_CPCIDVI
-	gt_config_table[0].config_device =  gt_setup_cpcidvi;
-#endif
-	gt_config_table[1].config_device =  gt_setup_ide;
-
-	pci0_hose.first_busno = 0;
-	pci0_hose.last_busno = 0xff;
-	local_buses[0] = pci0_hose.first_busno;
-
-	/* PCI memory space */
-	pci_set_region (pci0_hose.regions + 0,
-			CONFIG_SYS_PCI0_0_MEM_SPACE,
-			CONFIG_SYS_PCI0_0_MEM_SPACE,
-			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region (pci0_hose.regions + 1,
-			CONFIG_SYS_PCI0_IO_SPACE_PCI,
-			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
-
-	pci_set_ops (&pci0_hose,
-		     pci_hose_read_config_byte_via_dword,
-		     pci_hose_read_config_word_via_dword,
-		     gt_read_config_dword,
-		     pci_hose_write_config_byte_via_dword,
-		     pci_hose_write_config_word_via_dword,
-		     gt_write_config_dword);
-	pci0_hose.region_count = 2;
-
-	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
-
-	pci_register_hose (&pci0_hose);
-	if (slave == 0) {
-		pciArbiterEnable (PCI_HOST0);
-		pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
-		command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
-		command |= PCI_COMMAND_MASTER;
-		pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-		command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
-		command |= PCI_COMMAND_MEMORY;
-		pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-
-#ifdef CONFIG_PCI_PNP
-		pciauto_config_init(&pci0_hose);
-		pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
-#endif
-#ifdef CONFIG_PCI_SCAN_SHOW
-		printf("PCI:   Bus Dev VenId DevId Class Int\n");
-#endif
-		pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose,
-							  pci0_hose.first_busno);
-
-#ifdef DEBUG
-		gt_pci_bus_mode_display (PCI_HOST1);
-#endif
-	} else {
-		pciArbiterDisable (PCI_HOST0);
-		pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
-		command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
-		command |= PCI_COMMAND_MASTER;
-		pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-		command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
-		command |= PCI_COMMAND_MEMORY;
-		pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-		pci0_hose.last_busno = pci0_hose.first_busno;
-	}
-	pci1_hose.first_busno = pci0_hose.last_busno + 1;
-	pci1_hose.last_busno = 0xff;
-	pci1_hose.current_busno = pci1_hose.first_busno;
-	local_buses[1] = pci1_hose.first_busno;
-
-	/* PCI memory space */
-	pci_set_region (pci1_hose.regions + 0,
-			CONFIG_SYS_PCI1_0_MEM_SPACE,
-			CONFIG_SYS_PCI1_0_MEM_SPACE,
-			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region (pci1_hose.regions + 1,
-			CONFIG_SYS_PCI1_IO_SPACE_PCI,
-			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
-
-	pci_set_ops (&pci1_hose,
-		     pci_hose_read_config_byte_via_dword,
-		     pci_hose_read_config_word_via_dword,
-		     gt_read_config_dword,
-		     pci_hose_write_config_byte_via_dword,
-		     pci_hose_write_config_word_via_dword,
-		     gt_write_config_dword);
-
-	pci1_hose.region_count = 2;
-
-	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
-
-	pci_register_hose (&pci1_hose);
-
-	pciArbiterEnable (PCI_HOST1);
-	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
-
-	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MASTER;
-	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-#ifdef CONFIG_PCI_PNP
-	pciauto_config_init(&pci1_hose);
-	pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar);
-#endif
-	pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno);
-
-	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MEMORY;
-	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-}
-#endif /* of CONFIG_PCI */
diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c
deleted file mode 100644
index 89f94aa6aa8..00000000000
--- a/board/esd/cpci750/sdram_init.c
+++ /dev/null
@@ -1,1702 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*************************************************************************
- * adaption for the Marvell DB64360 Board
- * Ingo Assmus (ingo.assmus@keymile.com)
- *
- * adaption for the cpci750 Board
- * Reinhard Arlt (reinhard.arlt@esd-electronics.com)
- *************************************************************************/
-
-
-/* sdram_init.c - automatic memory sizing */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include "../../Marvell/include/memory.h"
-#include "../../Marvell/include/pci.h"
-#include "../../Marvell/include/mv_gen_reg.h"
-#include <net.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "../../Marvell/common/i2c.h"
-#include "64360.h"
-#include "mv_regs.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int set_dfcdlInit(void);	/* setup delay line of Mv64360 */
-
-/* ------------------------------------------------------------------------- */
-
-int
-memory_map_bank(unsigned int bankNo,
-		unsigned int bankBase,
-		unsigned int bankLength)
-{
-#ifdef MAP_PCI
-	PCI_HOST host;
-#endif
-
-
-#ifdef DEBUG
-	if (bankLength > 0) {
-		printf("mapping bank %d at %08x - %08x\n",
-		       bankNo, bankBase, bankBase + bankLength - 1);
-	} else {
-		printf("unmapping bank %d\n", bankNo);
-	}
-#endif
-
-	memoryMapBank(bankNo, bankBase, bankLength);
-
-#ifdef MAP_PCI
-	for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
-		const int features=
-			PREFETCH_ENABLE |
-			DELAYED_READ_ENABLE |
-			AGGRESSIVE_PREFETCH |
-			READ_LINE_AGGRESSIVE_PREFETCH |
-			READ_MULTI_AGGRESSIVE_PREFETCH |
-			MAX_BURST_4 |
-			PCI_NO_SWAP;
-
-		pciMapMemoryBank(host, bankNo, bankBase, bankLength);
-
-		pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
-				bankLength);
-
-		pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
-	}
-#endif
-	return 0;
-}
-
-#define GB	   (1 << 30)
-
-/* much of this code is based on (or is) the code in the pip405 port */
-/* thanks go to the authors of said port - Josh */
-
-/* structure to store the relevant information about an sdram bank */
-typedef struct sdram_info {
-	uchar drb_size;
-	uchar registered, ecc;
-	uchar tpar;
-	uchar tras_clocks;
-	uchar burst_len;
-	uchar banks, slot;
-} sdram_info_t;
-
-/* Typedefs for 'gtAuxilGetDIMMinfo' function */
-
-typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE;
-
-typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
-				SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
-			       } VOLTAGE_INTERFACE;
-
-typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR;
-typedef enum _max_CL_supported_SD {SD_CL_1=1,  SD_CL_2,  SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD;
-
-
-/* SDRAM/DDR information struct */
-typedef struct _gtMemoryDimmInfo {
-	MEMORY_TYPE memoryType;
-	unsigned int numOfRowAddresses;
-	unsigned int numOfColAddresses;
-	unsigned int numOfModuleBanks;
-	unsigned int dataWidth;
-	VOLTAGE_INTERFACE voltageInterface;
-	unsigned int errorCheckType;			/* ECC , PARITY.. */
-	unsigned int sdramWidth;			/* 4,8,16 or 32 */ ;
-	unsigned int errorCheckDataWidth;		/* 0 - no, 1 - Yes */
-	unsigned int minClkDelay;
-	unsigned int burstLengthSupported;
-	unsigned int numOfBanksOnEachDevice;
-	unsigned int suportedCasLatencies;
-	unsigned int RefreshInterval;
-	unsigned int maxCASlatencySupported_LoP;	/* LoP left of point (measured in ns) */
-	unsigned int maxCASlatencySupported_RoP;	/* RoP right of point (measured in ns) */
-	MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
-	MAX_CL_SUPPORTED_SD maxClSupported_SD;
-	unsigned int moduleBankDensity;
-	/* module attributes (true for yes) */
-	bool bufferedAddrAndControlInputs;
-	bool registeredAddrAndControlInputs;
-	bool onCardPLL;
-	bool bufferedDQMBinputs;
-	bool registeredDQMBinputs;
-	bool differentialClockInput;
-	bool redundantRowAddressing;
-
-	/* module general attributes */
-	bool suportedAutoPreCharge;
-	bool suportedPreChargeAll;
-	bool suportedEarlyRasPreCharge;
-	bool suportedWrite1ReadBurst;
-	bool suported5PercentLowVCC;
-	bool suported5PercentUpperVCC;
-	/* module timing parameters */
-	unsigned int minRasToCasDelay;
-	unsigned int minRowActiveRowActiveDelay;
-	unsigned int minRasPulseWidth;
-	unsigned int minRowPrechargeTime;		/* measured in ns */
-
-	int addrAndCommandHoldTime;			/* LoP left of point (measured in ns) */
-	int addrAndCommandSetupTime;			/* (measured in ns/100) */
-	int dataInputSetupTime;				/* LoP left of point (measured in ns) */
-	int dataInputHoldTime;				/* LoP left of point (measured in ns) */
-/* tAC times for highest 2nd and 3rd highest CAS Latency values */
-	unsigned int clockToDataOut_LoP;		/* LoP left of point (measured in ns) */
-	unsigned int clockToDataOut_RoP;		/* RoP right of point (measured in ns) */
-	unsigned int clockToDataOutMinus1_LoP;		/* LoP left of point (measured in ns) */
-	unsigned int clockToDataOutMinus1_RoP;		/* RoP right of point (measured in ns) */
-	unsigned int clockToDataOutMinus2_LoP;		/* LoP left of point (measured in ns) */
-	unsigned int clockToDataOutMinus2_RoP;		/* RoP right of point (measured in ns) */
-
-	unsigned int minimumCycleTimeAtMaxCasLatancy_LoP;	/* LoP left of point (measured in ns) */
-	unsigned int minimumCycleTimeAtMaxCasLatancy_RoP;	/* RoP right of point (measured in ns) */
-
-	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP;	/* LoP left of point (measured in ns) */
-	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP;	/* RoP right of point (measured in ns) */
-
-	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP;	/* LoP left of point (measured in ns) */
-	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP;	/* RoP right of point (measured in ns) */
-
-	/* Parameters calculated from
-	   the extracted DIMM information */
-	unsigned int size;
-	unsigned int deviceDensity;			/* 16,64,128,256 or 512 Mbit */
-	unsigned int numberOfDevices;
-	uchar drb_size;					/* DRAM size in n*64Mbit */
-	uchar slot;					/* Slot Number this module is inserted in */
-	uchar spd_raw_data[128];			/* Content of SPD-EEPROM copied 1:1 */
-#ifdef DEBUG
-	uchar manufactura[8];				/* Content of SPD-EEPROM Byte 64-71 */
-	uchar modul_id[18];				/* Content of SPD-EEPROM Byte 73-90 */
-	uchar vendor_data[27];				/* Content of SPD-EEPROM Byte 99-125 */
-	unsigned long modul_serial_no;			/* Content of SPD-EEPROM Byte 95-98 */
-	unsigned int manufac_date;			/* Content of SPD-EEPROM Byte 93-94 */
-	unsigned int modul_revision;			/* Content of SPD-EEPROM Byte 91-92 */
-	uchar manufac_place;				/* Content of SPD-EEPROM Byte 72 */
-
-#endif
-} AUX_MEM_DIMM_INFO;
-
-
-/*
- * translate ns.ns/10 coding of SPD timing values
- * into 10 ps unit values
- */
-static inline unsigned short
-NS10to10PS(unsigned char spd_byte)
-{
-	unsigned short ns, ns10;
-
-	/* isolate upper nibble */
-	ns = (spd_byte >> 4) & 0x0F;
-	/* isolate lower nibble */
-	ns10 = (spd_byte & 0x0F);
-
-	return(ns*100 + ns10*10);
-}
-
-/*
- * translate ns coding of SPD timing values
- * into 10 ps unit values
- */
-static inline unsigned short
-NSto10PS(unsigned char spd_byte)
-{
-	return(spd_byte*100);
-}
-
-/* This code reads the SPD chip on the sdram and populates
- * the array which is passed in with the relevant information */
-/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
-static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
-{
-	uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
-	int ret;
-	unsigned int i, j, density = 1, devicesForErrCheck = 0;
-
-#ifdef DEBUG
-	unsigned int k;
-#endif
-	unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
-	int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
-	uchar supp_cal, cal_val;
-	ulong memclk, tmemclk;
-	ulong tmp;
-	uchar trp_clocks = 0, tras_clocks;
-	uchar data[128];
-
-	memclk = gd->bus_clk;
-	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */
-
-	memset (data, 0, sizeof (data));
-
-
-	ret = 0;
-
-	debug("before i2c read\n");
-
-	ret = i2c_read (addr, 0, 2, data, 128);
-
-	debug("after i2c read\n");
-
-	if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd')
-	    || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm')
-	    || (data[70] != 'b') || (data[71] != 'h')) {
-		ret = -1;
-	}
-
-	if ((ret != 0) && (slot == 0)) {
-		memset (data, 0, sizeof (data));
-		data[0] = 0x80;
-		data[1] = 0x08;
-		data[2] = 0x07;
-		data[3] = 0x0c;
-		data[4] = 0x09;
-		data[5] = 0x01;
-		data[6] = 0x48;
-		data[7] = 0x00;
-		data[8] = 0x04;
-		data[9] = 0x75;
-		data[10] = 0x80;
-		data[11] = 0x02;
-		data[12] = 0x80;
-		data[13] = 0x10;
-		data[14] = 0x08;
-		data[15] = 0x01;
-		data[16] = 0x0e;
-		data[17] = 0x04;
-		data[18] = 0x0c;
-		data[19] = 0x01;
-		data[20] = 0x02;
-		data[21] = 0x20;
-		data[22] = 0x00;
-		data[23] = 0xa0;
-		data[24] = 0x80;
-		data[25] = 0x00;
-		data[26] = 0x00;
-		data[27] = 0x50;
-		data[28] = 0x3c;
-		data[29] = 0x50;
-		data[30] = 0x32;
-		data[31] = 0x10;
-		data[32] = 0xb0;
-		data[33] = 0xb0;
-		data[34] = 0x60;
-		data[35] = 0x60;
-		data[64] = 'e';
-		data[65] = 's';
-		data[66] = 'd';
-		data[67] = '-';
-		data[68] = 'g';
-		data[69] = 'm';
-		data[70] = 'b';
-		data[71] = 'h';
-		ret = 0;
-	}
-
-	/* zero all the values */
-	memset (dimmInfo, 0, sizeof (*dimmInfo));
-
-	/* copy the SPD content 1:1 into the dimmInfo structure */
-	for (i = 0; i <= 127; i++) {
-		dimmInfo->spd_raw_data[i] = data[i];
-	}
-
-	if (ret) {
-		debug("No DIMM in slot %d [err = %x]\n", slot, ret);
-		return 0;
-	} else
-		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
-
-#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
-
-	for (i = 0; i <= 127; i++) {
-		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
-			data[i]);
-	}
-
-#endif
-#ifdef DEBUG
-	/* find Manufacturer of Dimm Module */
-	for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
-		dimmInfo->manufactura[i] = data[64 + i];
-	}
-	printf ("\nThis RAM-Module is produced by:		%s\n",
-		dimmInfo->manufactura);
-
-	/* find Manul-ID of Dimm Module */
-	for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
-		dimmInfo->modul_id[i] = data[73 + i];
-	}
-	printf ("The Module-ID of this RAM-Module is:		%s\n",
-		dimmInfo->modul_id);
-
-	/* find Vendor-Data of Dimm Module */
-	for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
-		dimmInfo->vendor_data[i] = data[99 + i];
-	}
-	printf ("Vendor Data of this RAM-Module is:		%s\n",
-		dimmInfo->vendor_data);
-
-	/* find modul_serial_no of Dimm Module */
-	dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
-	printf ("Serial No. of this RAM-Module is:		%ld (%lx)\n",
-		dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
-
-	/* find Manufac-Data of Dimm Module */
-	dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
-	printf ("Manufactoring Date of this RAM-Module is:	%d.%d\n", data[93], data[94]);	/*dimmInfo->manufac_date */
-
-	/* find modul_revision of Dimm Module */
-	dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
-	printf ("Module Revision of this RAM-Module is: 		%d.%d\n", data[91], data[92]);	/* dimmInfo->modul_revision */
-
-	/* find manufac_place of Dimm Module */
-	dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
-	printf ("manufac_place of this RAM-Module is:		%d\n",
-		dimmInfo->manufac_place);
-
-#endif
-/*------------------------------------------------------------------------------------------------------------------------------*/
-/* calculate SPD checksum */
-/*------------------------------------------------------------------------------------------------------------------------------*/
-#if 0				/* test-only */
-	spd_checksum = 0;
-
-	for (i = 0; i <= 62; i++) {
-		spd_checksum += data[i];
-	}
-
-	if ((spd_checksum & 0xff) != data[63]) {
-		printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
-		hang ();
-	}
-
-	else
-		printf ("SPD Checksum ok!\n");
-#endif /* test-only */
-
-/*------------------------------------------------------------------------------------------------------------------------------*/
-	for (i = 2; i <= 35; i++) {
-		switch (i) {
-		case 2:	/* Memory type (DDR / SDRAM) */
-			dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
-#ifdef DEBUG
-			if (dimmInfo->memoryType == 0)
-				debug("Dram_type in slot %d is:			SDRAM\n",
-				     dimmInfo->slot);
-			if (dimmInfo->memoryType == 1)
-				debug("Dram_type in slot %d is:			DDRAM\n",
-				     dimmInfo->slot);
-#endif
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 3:	/* Number Of Row Addresses */
-			dimmInfo->numOfRowAddresses = data[i];
-			debug("Module Number of row addresses:		%d\n",
-			     dimmInfo->numOfRowAddresses);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 4:	/* Number Of Column Addresses */
-			dimmInfo->numOfColAddresses = data[i];
-			debug("Module Number of col addresses:		%d\n",
-			     dimmInfo->numOfColAddresses);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 5:	/* Number Of Module Banks */
-			dimmInfo->numOfModuleBanks = data[i];
-			debug("Number of Banks on Mod. : 				%d\n",
-			     dimmInfo->numOfModuleBanks);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 6:	/* Data Width */
-			dimmInfo->dataWidth = data[i];
-			debug("Module Data Width:				%d\n",
-			     dimmInfo->dataWidth);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 8:	/* Voltage Interface */
-			switch (data[i]) {
-			case 0x0:
-				dimmInfo->voltageInterface = TTL_5V_TOLERANT;
-				debug("Module is 					TTL_5V_TOLERANT\n");
-				break;
-			case 0x1:
-				dimmInfo->voltageInterface = LVTTL;
-				debug("Module is 					LVTTL\n");
-				break;
-			case 0x2:
-				dimmInfo->voltageInterface = HSTL_1_5V;
-				debug("Module is 					TTL_5V_TOLERANT\n");
-				break;
-			case 0x3:
-				dimmInfo->voltageInterface = SSTL_3_3V;
-				debug("Module is 					HSTL_1_5V\n");
-				break;
-			case 0x4:
-				dimmInfo->voltageInterface = SSTL_2_5V;
-				debug("Module is 					SSTL_2_5V\n");
-				break;
-			default:
-				dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
-				debug("Module is 					VOLTAGE_UNKNOWN\n");
-				break;
-			}
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 9:	/* Minimum Cycle Time At Max CasLatancy */
-			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
-			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
-			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
-			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
-				leftOfPoint;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
-				rightOfPoint;
-			debug("Minimum Cycle Time At Max CasLatancy:		%d.%d [ns]\n",
-			     leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 10:	/* Clock To Data Out */
-			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
-			time_tmp =
-				(((data[i] & 0xf0) >> 4) * 10) +
-				((data[i] & 0x0f));
-			leftOfPoint = time_tmp / div;
-			rightOfPoint = time_tmp % div;
-			dimmInfo->clockToDataOut_LoP = leftOfPoint;
-			dimmInfo->clockToDataOut_RoP = rightOfPoint;
-			debug("Clock To Data Out:				%d.%2d [ns]\n",
-			     leftOfPoint, rightOfPoint);
-			/*dimmInfo->clockToDataOut */
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-#ifdef CONFIG_MV64360_ECC
-		case 11:	/* Error Check Type */
-			dimmInfo->errorCheckType = data[i];
-			debug("Error Check Type (0=NONE):			%d\n",
-			     dimmInfo->errorCheckType);
-			break;
-#endif /* of ifdef CONFIG_MV64360_ECC */
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 12:	/* Refresh Interval */
-			dimmInfo->RefreshInterval = data[i];
-			debug("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
-			     dimmInfo->RefreshInterval);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 13:	/* Sdram Width */
-			dimmInfo->sdramWidth = data[i];
-			debug("Sdram Width:					%d\n",
-			     dimmInfo->sdramWidth);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 14:	/* Error Check Data Width */
-			dimmInfo->errorCheckDataWidth = data[i];
-			debug("Error Check Data Width:			%d\n",
-			     dimmInfo->errorCheckDataWidth);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 15:	/* Minimum Clock Delay */
-			dimmInfo->minClkDelay = data[i];
-			debug("Minimum Clock Delay:				%d\n",
-			     dimmInfo->minClkDelay);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 16:	/* Burst Length Supported */
-			   /******-******-******-*******
-			   * bit3 | bit2 | bit1 | bit0 *
-			   *******-******-******-*******
-	    burst length = *  8   |  4	 |   2	|   1  *
-			   *****************************
-
-	    If for example bit0 and bit2 are set, the burst
-	    length supported are 1 and 4. */
-
-			dimmInfo->burstLengthSupported = data[i];
-#ifdef DEBUG
-			debug("Burst Length Supported:			");
-			if (dimmInfo->burstLengthSupported & 0x01)
-				debug("1, ");
-			if (dimmInfo->burstLengthSupported & 0x02)
-				debug("2, ");
-			if (dimmInfo->burstLengthSupported & 0x04)
-				debug("4, ");
-			if (dimmInfo->burstLengthSupported & 0x08)
-				debug("8, ");
-			debug(" Bit \n");
-#endif
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 17:	/* Number Of Banks On Each Device */
-			dimmInfo->numOfBanksOnEachDevice = data[i];
-			debug("Number Of Banks On Each Chip:			%d\n",
-			     dimmInfo->numOfBanksOnEachDevice);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 18:	/* Suported Cas Latencies */
-
-			/*     DDR:
-			 *******-******-******-******-******-******-******-*******
-			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
-			 *******-******-******-******-******-******-******-*******
-			 CAS =	 * TBD	| TBD  | 3.5  |   3  | 2.5  |  2   | 1.5  |   1  *
-			 *********************************************************
-			 SDRAM:
-			 *******-******-******-******-******-******-******-*******
-			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
-			 *******-******-******-******-******-******-******-*******
-			 CAS =	 * TBD	|  7   |  6   |  5   |	4   |  3   |   2  |   1  *
-			 ********************************************************/
-			dimmInfo->suportedCasLatencies = data[i];
-#ifdef DEBUG
-			debug("Suported Cas Latencies: (CL)			");
-			if (dimmInfo->memoryType == 0) {	/* SDRAM */
-				for (k = 0; k <= 7; k++) {
-					if (dimmInfo->
-					    suportedCasLatencies & (1 << k))
-						debug("%d,			",
-						     k + 1);
-				}
-
-			} else {	/* DDR-RAM */
-
-				if (dimmInfo->suportedCasLatencies & 1)
-					debug("1, ");
-				if (dimmInfo->suportedCasLatencies & 2)
-					debug("1.5, ");
-				if (dimmInfo->suportedCasLatencies & 4)
-					debug("2, ");
-				if (dimmInfo->suportedCasLatencies & 8)
-					debug("2.5, ");
-				if (dimmInfo->suportedCasLatencies & 16)
-					debug("3, ");
-				if (dimmInfo->suportedCasLatencies & 32)
-					debug("3.5, ");
-
-			}
-			debug("\n");
-#endif
-			/* Calculating MAX CAS latency */
-			for (j = 7; j > 0; j--) {
-				if (((dimmInfo->
-				      suportedCasLatencies >> j) & 0x1) ==
-				    1) {
-					switch (dimmInfo->memoryType) {
-					case DDR:
-						/* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
-						switch (j) {
-						case 7:
-							debug("Max. Cas Latencies (DDR): 			ERROR !!!\n");
-							dimmInfo->
-								maxClSupported_DDR
-								=
-								DDR_CL_FAULT;
-							hang ();
-							break;
-						case 6:
-							debug("Max. Cas Latencies (DDR): 			ERROR !!!\n");
-							dimmInfo->
-								maxClSupported_DDR
-								=
-								DDR_CL_FAULT;
-							hang ();
-							break;
-						case 5:
-							debug("Max. Cas Latencies (DDR): 			3.5 clk's\n");
-							dimmInfo->
-								maxClSupported_DDR
-								= DDR_CL_3_5;
-							break;
-						case 4:
-							debug("Max. Cas Latencies (DDR): 			3 clk's \n");
-							dimmInfo->
-								maxClSupported_DDR
-								= DDR_CL_3;
-							break;
-						case 3:
-							debug("Max. Cas Latencies (DDR): 			2.5 clk's \n");
-							dimmInfo->
-								maxClSupported_DDR
-								= DDR_CL_2_5;
-							break;
-						case 2:
-							debug("Max. Cas Latencies (DDR): 			2 clk's \n");
-							dimmInfo->
-								maxClSupported_DDR
-								= DDR_CL_2;
-							break;
-						case 1:
-							debug("Max. Cas Latencies (DDR): 			1.5 clk's \n");
-							dimmInfo->
-								maxClSupported_DDR
-								= DDR_CL_1_5;
-							break;
-						}
-						dimmInfo->
-							maxCASlatencySupported_LoP
-							=
-							1 +
-							(int) (5 * j / 10);
-						if (((5 * j) % 10) != 0)
-							dimmInfo->
-								maxCASlatencySupported_RoP
-								= 5;
-						else
-							dimmInfo->
-								maxCASlatencySupported_RoP
-								= 0;
-						debug("Max. Cas Latencies (DDR LoP.RoP Notation):	%d.%d \n",
-						     dimmInfo->
-						     maxCASlatencySupported_LoP,
-						     dimmInfo->
-						     maxCASlatencySupported_RoP);
-						break;
-					case SDRAM:
-						/* CAS latency 1, 2, 3, 4, 5, 6, 7 */
-						dimmInfo->maxClSupported_SD = j;	/*  Cas Latency DDR-RAM Coded			*/
-						debug("Max. Cas Latencies (SD): %d\n",
-						     dimmInfo->
-						     maxClSupported_SD);
-						dimmInfo->
-							maxCASlatencySupported_LoP
-							= j;
-						dimmInfo->
-							maxCASlatencySupported_RoP
-							= 0;
-						debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
-						     dimmInfo->
-						     maxCASlatencySupported_LoP,
-						     dimmInfo->
-						     maxCASlatencySupported_RoP);
-						break;
-					}
-					break;
-				}
-			}
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 21:	/* Buffered Address And Control Inputs */
-			debug("\nModul Attributes (SPD Byte 21): \n");
-			dimmInfo->bufferedAddrAndControlInputs =
-				data[i] & BIT0;
-			dimmInfo->registeredAddrAndControlInputs =
-				(data[i] & BIT1) >> 1;
-			dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
-			dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
-			dimmInfo->registeredDQMBinputs =
-				(data[i] & BIT4) >> 4;
-			dimmInfo->differentialClockInput =
-				(data[i] & BIT5) >> 5;
-			dimmInfo->redundantRowAddressing =
-				(data[i] & BIT6) >> 6;
-
-			if (dimmInfo->bufferedAddrAndControlInputs == 1)
-				debug(" - Buffered Address/Control Input:		Yes \n");
-			else
-				debug(" - Buffered Address/Control Input:		No \n");
-
-			if (dimmInfo->registeredAddrAndControlInputs == 1)
-				debug(" - Registered Address/Control Input:		Yes \n");
-			else
-				debug(" - Registered Address/Control Input:		No \n");
-
-			if (dimmInfo->onCardPLL == 1)
-				debug(" - On-Card PLL (clock):				Yes \n");
-			else
-				debug(" - On-Card PLL (clock):				No \n");
-
-			if (dimmInfo->bufferedDQMBinputs == 1)
-				debug(" - Bufferd DQMB Inputs:				Yes \n");
-			else
-				debug(" - Bufferd DQMB Inputs:				No \n");
-
-			if (dimmInfo->registeredDQMBinputs == 1)
-				debug(" - Registered DQMB Inputs:			Yes \n");
-			else
-				debug(" - Registered DQMB Inputs:			No \n");
-
-			if (dimmInfo->differentialClockInput == 1)
-				debug(" - Differential Clock Input:			Yes \n");
-			else
-				debug(" - Differential Clock Input:			No \n");
-
-			if (dimmInfo->redundantRowAddressing == 1)
-				debug(" - redundant Row Addressing:			Yes \n");
-			else
-				debug(" - redundant Row Addressing:			No \n");
-
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 22:	/* Suported AutoPreCharge */
-			debug("\nModul Attributes (SPD Byte 22): \n");
-			dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
-			dimmInfo->suportedAutoPreCharge =
-				(data[i] & BIT1) >> 1;
-			dimmInfo->suportedPreChargeAll =
-				(data[i] & BIT2) >> 2;
-			dimmInfo->suportedWrite1ReadBurst =
-				(data[i] & BIT3) >> 3;
-			dimmInfo->suported5PercentLowVCC =
-				(data[i] & BIT4) >> 4;
-			dimmInfo->suported5PercentUpperVCC =
-				(data[i] & BIT5) >> 5;
-
-			if (dimmInfo->suportedEarlyRasPreCharge == 1)
-				debug(" - Early Ras Precharge:			Yes \n");
-			else
-				debug(" -  Early Ras Precharge:			No \n");
-
-			if (dimmInfo->suportedAutoPreCharge == 1)
-				debug(" - AutoPreCharge:				Yes \n");
-			else
-				debug(" -  AutoPreCharge:				No \n");
-
-			if (dimmInfo->suportedPreChargeAll == 1)
-				debug(" - Precharge All:				Yes \n");
-			else
-				debug(" -  Precharge All:				No \n");
-
-			if (dimmInfo->suportedWrite1ReadBurst == 1)
-				debug(" - Write 1/ReadBurst:				Yes \n");
-			else
-				debug(" -  Write 1/ReadBurst:				No \n");
-
-			if (dimmInfo->suported5PercentLowVCC == 1)
-				debug(" - lower VCC tolerance:			5 Percent \n");
-			else
-				debug("	- lower VCC tolerance:			10 Percent \n");
-
-			if (dimmInfo->suported5PercentUpperVCC == 1)
-				debug(" - upper VCC tolerance:			5 Percent \n");
-			else
-				debug(" -  upper VCC tolerance:			10 Percent \n");
-
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 23:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
-			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
-			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
-			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
-			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
-				leftOfPoint;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
-				rightOfPoint;
-			debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
-			     leftOfPoint, rightOfPoint);
-			/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 24:	/* Clock To Data Out 2nd highest Cas Latency Value */
-			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
-			time_tmp =
-				(((data[i] & 0xf0) >> 4) * 10) +
-				((data[i] & 0x0f));
-			leftOfPoint = time_tmp / div;
-			rightOfPoint = time_tmp % div;
-			dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
-			dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
-			debug("Clock To Data Out (2nd CL value): 		%d.%2d [ns]\n",
-			     leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 25:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
-			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
-			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
-			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
-			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
-				leftOfPoint;
-			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
-				rightOfPoint;
-			debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
-			     leftOfPoint, rightOfPoint);
-			/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 26:	/* Clock To Data Out 3rd highest Cas Latency Value */
-			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
-			time_tmp =
-				(((data[i] & 0xf0) >> 4) * 10) +
-				((data[i] & 0x0f));
-			leftOfPoint = time_tmp / div;
-			rightOfPoint = time_tmp % div;
-			dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
-			dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
-			debug("Clock To Data Out (3rd CL value): 		%d.%2d [ns]\n",
-			     leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 27:	/* Minimum Row Precharge Time */
-			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
-			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
-			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
-			dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint);	/* measured in n times 10ps Intervals */
-			trp_clocks =
-				(dimmInfo->minRowPrechargeTime +
-				 (tmemclk - 1)) / tmemclk;
-			debug("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
-			     tmemclk, tmemclk / 100, tmemclk % 100);
-			debug("Minimum Row Precharge Time [ns]:		%d.%2d = in Clk cycles %d\n",
-			     leftOfPoint, rightOfPoint, trp_clocks);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 28:	/* Minimum Row Active to Row Active Time */
-			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
-			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
-			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
-			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
-			debug("Minimum Row Active -To- Row Active Delay [ns]:	%d.%2d = in Clk cycles %d\n",
-			     leftOfPoint, rightOfPoint, trp_clocks);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 29:	/* Minimum Ras-To-Cas Delay */
-			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
-			maskLeftOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
-			maskRightOfPoint =
-				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
-			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
-			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
-			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
-			debug("Minimum Ras-To-Cas Delay [ns]:			%d.%2d = in Clk cycles %d\n",
-			     leftOfPoint, rightOfPoint, trp_clocks);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 30:	/* Minimum Ras Pulse Width */
-			dimmInfo->minRasPulseWidth = data[i];
-			tras_clocks =
-				(NSto10PS (data[i]) +
-				 (tmemclk - 1)) / tmemclk;
-			debug("Minimum Ras Pulse Width [ns]:			%d = in Clk cycles %d\n",
-			     dimmInfo->minRasPulseWidth, tras_clocks);
-
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 31:	/* Module Bank Density */
-			dimmInfo->moduleBankDensity = data[i];
-			debug("Module Bank Density:				%d\n",
-			     dimmInfo->moduleBankDensity);
-#ifdef DEBUG
-			debug("*** Offered Densities (more than 1 = Multisize-Module): ");
-			{
-				if (dimmInfo->moduleBankDensity & 1)
-					debug("4MB, ");
-				if (dimmInfo->moduleBankDensity & 2)
-					debug("8MB, ");
-				if (dimmInfo->moduleBankDensity & 4)
-					debug("16MB, ");
-				if (dimmInfo->moduleBankDensity & 8)
-					debug("32MB, ");
-				if (dimmInfo->moduleBankDensity & 16)
-					debug("64MB, ");
-				if (dimmInfo->moduleBankDensity & 32)
-					debug("128MB, ");
-				if ((dimmInfo->moduleBankDensity & 64)
-				    || (dimmInfo->moduleBankDensity & 128)) {
-					debug("ERROR, ");
-					hang ();
-				}
-			}
-			debug("\n");
-#endif
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 32:	/* Address And Command Setup Time (measured in ns/1000) */
-			sign = 1;
-			switch (dimmInfo->memoryType) {
-			case DDR:
-				time_tmp =
-					(((data[i] & 0xf0) >> 4) * 10) +
-					((data[i] & 0x0f));
-				leftOfPoint = time_tmp / 100;
-				rightOfPoint = time_tmp % 100;
-				break;
-			case SDRAM:
-				leftOfPoint = (data[i] & 0xf0) >> 4;
-				if (leftOfPoint > 7) {
-					leftOfPoint = data[i] & 0x70 >> 4;
-					sign = -1;
-				}
-				rightOfPoint = (data[i] & 0x0f);
-				break;
-			}
-			dimmInfo->addrAndCommandSetupTime =
-				(leftOfPoint * 100 + rightOfPoint) * sign;
-			debug("Address And Command Setup Time [ns]:		%d.%d\n",
-			     sign * leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 33:	/* Address And Command Hold Time */
-			sign = 1;
-			switch (dimmInfo->memoryType) {
-			case DDR:
-				time_tmp =
-					(((data[i] & 0xf0) >> 4) * 10) +
-					((data[i] & 0x0f));
-				leftOfPoint = time_tmp / 100;
-				rightOfPoint = time_tmp % 100;
-				break;
-			case SDRAM:
-				leftOfPoint = (data[i] & 0xf0) >> 4;
-				if (leftOfPoint > 7) {
-					leftOfPoint = data[i] & 0x70 >> 4;
-					sign = -1;
-				}
-				rightOfPoint = (data[i] & 0x0f);
-				break;
-			}
-			dimmInfo->addrAndCommandHoldTime =
-				(leftOfPoint * 100 + rightOfPoint) * sign;
-			debug("Address And Command Hold Time [ns]:		%d.%d\n",
-			     sign * leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 34:	/* Data Input Setup Time */
-			sign = 1;
-			switch (dimmInfo->memoryType) {
-			case DDR:
-				time_tmp =
-					(((data[i] & 0xf0) >> 4) * 10) +
-					((data[i] & 0x0f));
-				leftOfPoint = time_tmp / 100;
-				rightOfPoint = time_tmp % 100;
-				break;
-			case SDRAM:
-				leftOfPoint = (data[i] & 0xf0) >> 4;
-				if (leftOfPoint > 7) {
-					leftOfPoint = data[i] & 0x70 >> 4;
-					sign = -1;
-				}
-				rightOfPoint = (data[i] & 0x0f);
-				break;
-			}
-			dimmInfo->dataInputSetupTime =
-				(leftOfPoint * 100 + rightOfPoint) * sign;
-			debug("Data Input Setup Time [ns]:			%d.%d\n",
-			     sign * leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-		case 35:	/* Data Input Hold Time */
-			sign = 1;
-			switch (dimmInfo->memoryType) {
-			case DDR:
-				time_tmp =
-					(((data[i] & 0xf0) >> 4) * 10) +
-					((data[i] & 0x0f));
-				leftOfPoint = time_tmp / 100;
-				rightOfPoint = time_tmp % 100;
-				break;
-			case SDRAM:
-				leftOfPoint = (data[i] & 0xf0) >> 4;
-				if (leftOfPoint > 7) {
-					leftOfPoint = data[i] & 0x70 >> 4;
-					sign = -1;
-				}
-				rightOfPoint = (data[i] & 0x0f);
-				break;
-			}
-			dimmInfo->dataInputHoldTime =
-				(leftOfPoint * 100 + rightOfPoint) * sign;
-			debug("Data Input Hold Time [ns]:			%d.%d\n\n",
-			     sign * leftOfPoint, rightOfPoint);
-			break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-		}
-	}
-	/* calculating the sdram density */
-	for (i = 0;
-	     i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
-	     i++) {
-		density = density * 2;
-	}
-	dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
-		dimmInfo->sdramWidth;
-	dimmInfo->numberOfDevices =
-		(dimmInfo->dataWidth / dimmInfo->sdramWidth) *
-		dimmInfo->numOfModuleBanks;
-	devicesForErrCheck =
-		(dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
-	if ((dimmInfo->errorCheckType == 0x1)
-	    || (dimmInfo->errorCheckType == 0x2)
-	    || (dimmInfo->errorCheckType == 0x3)) {
-		dimmInfo->size =
-			(dimmInfo->deviceDensity / 8) *
-			(dimmInfo->numberOfDevices - devicesForErrCheck);
-	} else {
-		dimmInfo->size =
-			(dimmInfo->deviceDensity / 8) *
-			dimmInfo->numberOfDevices;
-	}
-
-	/* compute the module DRB size */
-	tmp = (1 <<
-	       (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
-	tmp *= dimmInfo->numOfModuleBanks;
-	tmp *= dimmInfo->sdramWidth;
-	tmp = tmp >> 24;	/* div by 0x4000000 (64M)	*/
-	dimmInfo->drb_size = (uchar) tmp;
-	debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
-
-	/* try a CAS latency of 3 first... */
-
-	/* bit 1 is CL2, bit 2 is CL3 */
-	supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1;
-
-	cal_val = 0;
-	if (supp_cal & 8) {
-		if (NS10to10PS (data[9]) <= tmemclk)
-			cal_val = 6;
-	}
-	if (supp_cal & 4) {
-		if (NS10to10PS (data[9]) <= tmemclk)
-			cal_val = 5;
-	}
-
-	/* then 2... */
-	if (supp_cal & 2) {
-		if (NS10to10PS (data[23]) <= tmemclk)
-			cal_val = 4;
-	}
-
-	debug("cal_val = %d\n", cal_val * 5);
-
-	/* bummer, did't work... */
-	if (cal_val == 0) {
-		debug("Couldn't find a good CAS latency\n");
-		hang ();
-		return 0;
-	}
-
-	return true;
-}
-
-/* sets up the GT properly with information passed in */
-int setup_sdram (AUX_MEM_DIMM_INFO * info)
-{
-	ulong tmp;
-	ulong tmp_sdram_mode = 0;	/* 0x141c */
-	ulong tmp_dunit_control_low = 0;	/* 0x1404 */
-	uint sdram_config_reg = CONFIG_SYS_SDRAM_CONFIG;
-	int i;
-
-	/* sanity checking */
-	if (!info->numOfModuleBanks) {
-		printf ("setup_sdram called with 0 banks\n");
-		return 1;
-	}
-
-	/* delay line */
-
-	/* Program the GT with the discovered data */
-	if (info->registeredAddrAndControlInputs == true)
-		debug("Module is registered, but we do not support registered Modules !!!\n");
-
-	/* delay line */
-	set_dfcdlInit ();	/* may be its not needed */
-	debug("Delay line set done\n");
-
-	/* set SDRAM mode NOP */ /* To_do check it */
-	GT_REG_WRITE (SDRAM_OPERATION, 0x5);
-	while (GTREGREAD (SDRAM_OPERATION) != 0) {
-		debug("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
-	}
-
-#ifdef CONFIG_MV64360_ECC
-	if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) {
-		/* DRAM has ECC, so turn it on */
-		sdram_config_reg |= BIT18;
-		debug("Enabling ECC\n");
-	}
-#endif /* of ifdef CONFIG_MV64360_ECC */
-
-	/* SDRAM configuration */
-	GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg);
-	debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG));
-
-	/* SDRAM open pages controll keep open as much as I can */
-	GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
-	debug("sdram_open_pages_controll 0x1414: %08x\n",
-	     GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
-
-
-	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
-	tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);	/* Clock Domain Sync from power on reset */
-	if (tmp == 0)
-		debug("Core Signals are sync (by HW-Setting)!!!\n");
-	else
-		debug("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
-
-	/* SDRAM set CAS Lentency according to SPD information */
-	switch (info->memoryType) {
-	case SDRAM:
-		debug("### SD-RAM not supported yet !!!\n");
-		hang ();
-		/* ToDo fill SD-RAM if needed !!!!! */
-		break;
-
-	case DDR:
-		debug("### SET-CL for DDR-RAM\n");
-
-		switch (info->maxClSupported_DDR) {
-		case DDR_CL_3:
-			tmp_dunit_control_low = 0x3c000000;	/* Read-Data sampled on falling edge of Clk */
-			tmp_sdram_mode = 0x32;	/* CL=3 Burstlength = 4 */
-			debug("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-			     tmp_sdram_mode, tmp_dunit_control_low);
-			break;
-
-		case DDR_CL_2_5:
-			if (tmp == 1) {	/* clocks sync */
-				tmp_dunit_control_low = 0x24000000;	/* Read-Data sampled on falling edge of Clk */
-				tmp_sdram_mode = 0x62;	/* CL=2,5 Burstlength = 4 */
-				debug("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			} else {	/* clk sync. bypassed	  */
-
-				tmp_dunit_control_low = 0x03000000;	/* Read-Data sampled on rising edge of Clk */
-				tmp_sdram_mode = 0x62;	/* CL=2,5 Burstlength = 4 */
-				debug("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			}
-			break;
-
-		case DDR_CL_2:
-			if (tmp == 1) {	/* Sync */
-				tmp_dunit_control_low = 0x03000000;	/* Read-Data sampled on rising edge of Clk */
-				tmp_sdram_mode = 0x22;	/* CL=2 Burstlength = 4 */
-				debug("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			} else {	/* Not sync.	  */
-
-				tmp_dunit_control_low = 0x3b000000;	/* Read-Data sampled on rising edge of Clk */
-				tmp_sdram_mode = 0x22;	/* CL=2 Burstlength = 4 */
-				debug("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			}
-			break;
-
-		case DDR_CL_1_5:
-			if (tmp == 1) {	/* Sync */
-				tmp_dunit_control_low = 0x23000000;	/* Read-Data sampled on falling edge of Clk */
-				tmp_sdram_mode = 0x52;	/* CL=1,5 Burstlength = 4 */
-				debug("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			} else {	/* not sync */
-
-				tmp_dunit_control_low = 0x1a000000;	/* Read-Data sampled on rising edge of Clk */
-				tmp_sdram_mode = 0x52;	/* CL=1,5 Burstlength = 4 */
-				debug("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
-				     tmp_sdram_mode, tmp_dunit_control_low);
-			}
-			break;
-
-		default:
-			printf ("Max. CL is out of range %d\n",
-				info->maxClSupported_DDR);
-			hang ();
-			break;
-		}
-		break;
-	}
-
-	/* Write results of CL detection procedure */
-	GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
-	/* set SDRAM mode SetCommand 0x1418 */
-	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
-	while (GTREGREAD (SDRAM_OPERATION) != 0) {
-		debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
-	}
-
-
-	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
-	tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);	/* Clock Domain Sync from power on reset */
-	if (tmp != 1) {		/*clocks are not sync */
-		/* asyncmode */
-		GT_REG_WRITE (D_UNIT_CONTROL_LOW,
-			      (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
-			      0x18110780 | tmp_dunit_control_low);
-	} else {
-		/* syncmode */
-		GT_REG_WRITE (D_UNIT_CONTROL_LOW,
-			      (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
-			      0x00110000 | tmp_dunit_control_low);
-	}
-
-	/* set SDRAM mode SetCommand 0x1418 */
-	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
-	while (GTREGREAD (SDRAM_OPERATION) != 0) {
-		debug("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
-	}
-
-/*------------------------------------------------------------------------------ */
-
-
-	/* bank parameters */
-	/* SDRAM address decode register */
-	/* program this with the default value */
-	tmp = 0x02;
-
-
-	debug("drb_size (n*64Mbit): %d\n", info->drb_size);
-	switch (info->drb_size) {
-	case 1:		/* 64 Mbit */
-	case 2:		/* 128 Mbit */
-		debug("RAM-Device_size 64Mbit or 128Mbit)\n");
-		tmp |= (0x00 << 4);
-		break;
-	case 4:		/* 256 Mbit */
-	case 8:		/* 512 Mbit */
-		debug("RAM-Device_size 256Mbit or 512Mbit)\n");
-		tmp |= (0x01 << 4);
-		break;
-	case 16:		/* 1 Gbit */
-	case 32:		/* 2 Gbit */
-		debug("RAM-Device_size 1Gbit or 2Gbit)\n");
-		tmp |= (0x02 << 4);
-		break;
-	default:
-		printf ("Error in dram size calculation\n");
-		debug("Assume: RAM-Device_size 1Gbit or 2Gbit)\n");
-		tmp |= (0x02 << 4);
-		return 1;
-	}
-
-	/* SDRAM bank parameters */
-	/* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
-	debug("setting up slot %d config with: %08lx \n", info->slot, tmp);
-	GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
-
-/* ------------------------------------------------------------------------------ */
-
-	debug("setting up sdram_timing_control_low with: %08x \n",
-	     0x11511220);
-	GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
-
-
-/* ------------------------------------------------------------------------------ */
-
-	/* SDRAM configuration */
-	tmp = GTREGREAD (SDRAM_CONFIG);
-
-	if (info->registeredAddrAndControlInputs
-	    || info->registeredDQMBinputs) {
-		tmp |= (1 << 17);
-		debug("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
-		     info->registeredAddrAndControlInputs,
-		     info->registeredDQMBinputs);
-	}
-
-	/* Use buffer 1 to return read data to the CPU
-	 * Page 426 MV64360 */
-	tmp |= (1 << 26);
-	debug("Before Buffer assignment - sdram_conf: %08x\n",
-	     GTREGREAD (SDRAM_CONFIG));
-	debug("After Buffer assignment - sdram_conf: %08x\n",
-	     GTREGREAD (SDRAM_CONFIG));
-
-	/* SDRAM timing To_do: */
-
-
-	tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH);
-	debug("# sdram_timing_control_high is : %08lx \n", tmp);
-
-	/* SDRAM address decode register */
-	/* program this with the default value */
-	tmp = GTREGREAD (SDRAM_ADDR_CONTROL);
-	debug("SDRAM address control (before: decode): %08x  ",
-	     GTREGREAD (SDRAM_ADDR_CONTROL));
-	GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2));
-	debug("SDRAM address control (after: decode): %08x\n",
-	     GTREGREAD (SDRAM_ADDR_CONTROL));
-
-	/* set the SDRAM configuration for each bank */
-
-/*	for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
-	{
-		int l, l1;
-
-		i = info->slot;
-		debug("\n*** Running a MRS cycle for bank %d ***\n", i);
-
-		/* map the bank */
-		memory_map_bank (i, 0, GB / 4);
-#if 1				/* test only */
-
-		tmp = GTREGREAD (SDRAM_MODE);
-		GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0);
-		GT_REG_WRITE (SDRAM_OPERATION, 0x4);
-		while (GTREGREAD (SDRAM_OPERATION) != 0) {
-			debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
-		}
-
-		GT_REG_WRITE (SDRAM_MODE, tmp | 0x80);
-		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
-		while (GTREGREAD (SDRAM_OPERATION) != 0) {
-			debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
-		}
-		l1 = 0;
-		for (l=0;l<200;l++)
-			l1 += GTREGREAD (SDRAM_OPERATION);
-
-		GT_REG_WRITE (SDRAM_MODE, tmp);
-		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
-		while (GTREGREAD (SDRAM_OPERATION) != 0) {
-			debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
-		}
-
-		/* switch back to normal operation mode */
-		GT_REG_WRITE (SDRAM_OPERATION, 0x5);
-		while (GTREGREAD (SDRAM_OPERATION) != 0) {
-			debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
-		}
-
-#endif /* test only */
-		/* unmap the bank */
-		memory_map_bank (i, 0, 0);
-	}
-
-	return 0;
-}
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-long int
-dram_size(long int *base, long int maxsize)
-{
-    volatile long int	 *addr, *b=base;
-    long int	 cnt, val, save1, save2;
-
-#define STARTVAL (1<<20)	/* start test at 1M */
-    for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
-	    addr = base + cnt;	/* pointer arith! */
-
-	    save1 = *addr;		/* save contents of addr */
-	    save2 = *b;		/* save contents of base */
-
-	    *addr=cnt;		/* write cnt to addr */
-	    *b=0;			/* put null at base */
-
-	    /* check at base address */
-	    if ((*b) != 0) {
-		*addr=save1;	/* restore *addr */
-		*b=save2;	/* restore *b */
-		return (0);
-	    }
-	    val = *addr;		/* read *addr */
-	    val = *addr;		/* read *addr */
-
-	    *addr=save1;
-	    *b=save2;
-
-	    if (val != cnt) {
-		    debug("Found %08x  at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr);
-		    /* fix boundary condition.. STARTVAL means zero */
-		    if(cnt==STARTVAL/sizeof(long)) cnt=0;
-		    return (cnt * sizeof(long));
-	    }
-    }
-    return maxsize;
-}
-
-#ifdef CONFIG_MV64360_ECC
-/*
- * mv_dma_is_channel_active:
- * Checks if a engine is busy.
- */
-int mv_dma_is_channel_active(int engine)
-{
-	ulong data;
-
-	data = GTREGREAD(MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
-	if (data & BIT14)	/* activity status */
-		return 1;
-
-	return 0;
-}
-
-/*
- * mv_dma_set_memory_space:
- * Set a DMA memory window for the DMA's address decoding map.
- */
-int mv_dma_set_memory_space(ulong mem_space, ulong mem_space_target,
-			    ulong mem_space_attr, ulong base_address,
-			    ulong size)
-{
-	ulong temp;
-
-	/* The base address must be aligned to the size.  */
-	if (base_address % size != 0)
-		return 0;
-
-	if (size >= 0x10000) {
-		size &= 0xffff0000;
-		base_address = (base_address & 0xffff0000);
-		/* Set the new attributes */
-		GT_REG_WRITE(MV64360_DMA_BASE_ADDR_REG0 + mem_space * 8,
-			     (base_address | mem_space_target |
-			      mem_space_attr));
-		GT_REG_WRITE((MV64360_DMA_SIZE_REG0 + mem_space * 8),
-			     (size - 1) & 0xffff0000);
-		temp = GTREGREAD(MV64360_DMA_BASE_ADDR_ENABLE_REG);
-		GT_REG_WRITE(DMA_BASE_ADDR_ENABLE_REG,
-			     (temp & ~(BIT0 << mem_space)));
-		return 1;
-	}
-
-	return 0;
-}
-
-
-/*
- * mv_dma_transfer:
- * Transfer data from source_addr to dest_addr on one of the 4 DMA channels.
- */
-int mv_dma_transfer(int engine, ulong source_addr,
-		    ulong dest_addr, ulong bytes, ulong command)
-{
-	ulong eng_off_reg;	/* Engine Offset Register */
-
-	if (bytes > 0xffff)
-		command = command | BIT31;	 /* DMA_16M_DESCRIPTOR_MODE */
-
-	command = command | ((command >> 6) & 0x7);
-	eng_off_reg = engine * 4;
-	GT_REG_WRITE(MV64360_DMA_CHANNEL0_BYTE_COUNT + eng_off_reg,
-		     bytes);
-	GT_REG_WRITE(MV64360_DMA_CHANNEL0_SOURCE_ADDR + eng_off_reg,
-		     source_addr);
-	GT_REG_WRITE(MV64360_DMA_CHANNEL0_DESTINATION_ADDR + eng_off_reg,
-		     dest_addr);
-	command |= BIT12	/* DMA_CHANNEL_ENABLE */
-		| BIT9;		/* DMA_NON_CHAIN_MODE */
-
-	/* Activate DMA engine By writting to mv_dma_control_register */
-	GT_REG_WRITE(MV64360_DMA_CHANNEL0_CONTROL + eng_off_reg, command);
-
-	return 1;
-}
-#endif /* of ifdef CONFIG_MV64360_ECC */
-
-/* ppcboot interface function to SDRAM init - this is where all the
- * controlling logic happens */
-phys_size_t
-initdram(int board_type)
-{
-	int checkbank[4] = { [0 ... 3] = 0 };
-	ulong realsize, total, check;
-	AUX_MEM_DIMM_INFO dimmInfo1;
-	AUX_MEM_DIMM_INFO dimmInfo2;
-	int bank_no, nhr;
-#ifdef CONFIG_MV64360_ECC
-	ulong dest, mem_space_attr;
-#endif /* of ifdef CONFIG_MV64360_ECC */
-
-	/* first, use the SPD to get info about the SDRAM/ DDRRAM */
-
-	/* check the NHR bit and skip mem init if it's already done */
-	nhr = get_hid0() & (1 << 16);
-
-	if (nhr) {
-		printf("Skipping SD- DDRRAM setup due to NHR bit being set\n");
-	} else {
-		/* DIMM0 */
-		(void)check_dimm(0, &dimmInfo1);
-
-		/* DIMM1 */
-		(void)check_dimm(1, &dimmInfo2);
-
-		memory_map_bank(0, 0, 0);
-		memory_map_bank(1, 0, 0);
-		memory_map_bank(2, 0, 0);
-		memory_map_bank(3, 0, 0);
-
-		if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) {
-			printf("Setup for DIMM1 failed.\n");
-		}
-
-		if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) {
-			printf("Setup for DIMM2 failed.\n");
-		}
-
-		/* set the NHR bit */
-		set_hid0(get_hid0() | (1 << 16));
-	}
-	/* next, size the SDRAM banks */
-
-	realsize = total = 0;
-	check = GB/4;
-	if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");}
-	if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");}
-	if (dimmInfo1.numOfModuleBanks > 2)
-		printf("Error, SPD claims DIMM1 has >2 banks\n");
-
-	if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");}
-	if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");}
-	if (dimmInfo2.numOfModuleBanks > 2)
-		printf("Error, SPD claims DIMM2 has >2 banks\n");
-
-	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
-		/* skip over banks that are not populated */
-		if (! checkbank[bank_no])
-			continue;
-
-		if ((total + check) > CONFIG_SYS_GT_REGS)
-			check = CONFIG_SYS_GT_REGS - total;
-
-		memory_map_bank(bank_no, total, check);
-		realsize = dram_size((long int *)total, check);
-		memory_map_bank(bank_no, total, realsize);
-
-#ifdef CONFIG_MV64360_ECC
-		if (((dimmInfo1.errorCheckType != 0) &&
-		     ((dimmInfo2.errorCheckType != 0) ||
-		      (dimmInfo2.numOfModuleBanks == 0))) &&
-		    (CPCI750_ECC_TEST)) {
-			printf("ECC Initialization of Bank %d:", bank_no);
-			mem_space_attr = ((~(BIT0 << bank_no)) & 0xf) << 8;
-			mv_dma_set_memory_space(0, 0, mem_space_attr, total,
-						realsize);
-			for (dest = total; dest < total + realsize;
-			     dest += _8M) {
-				mv_dma_transfer(0, total, dest, _8M,
-						BIT8 |	/* DMA_DTL_128BYTES */
-						BIT3 |	/* DMA_HOLD_SOURCE_ADDR */
-						BIT11);	/* DMA_BLOCK_TRANSFER_MODE */
-				while (mv_dma_is_channel_active(0))
-					;
-			}
-			printf(" PASS\n");
-		}
-#endif /* of ifdef CONFIG_MV64360_ECC */
-
-		total += realsize;
-	}
-
-/*	Setup Ethernet DMA Adress window to DRAM Area */
-	return(total);
-}
-
-/* ***************************************************************************************
-! *				SDRAM INIT						*
-! *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb	*
-! *		  This procedure fits only the Atlantis				       *
-! *											*
-! *************************************************************************************** */
-
-
-/* ***************************************************************************************
-! *				DFCDL initialize MV643xx Design Considerations		   *
-! *											*
-! *************************************************************************************** */
-int set_dfcdlInit (void)
-{
-	int i;
-	unsigned int dfcdl_word = 0x0000014f;
-
-	for (i = 0; i < 64; i++) {
-		GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
-	}
-	GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000);	/* enable dynamic delay line updating */
-
-
-	return (0);
-}
-
-int do_show_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	unsigned int ecc_counter;
-	unsigned int ecc_addr;
-
-	GT_REG_READ(0x1458, &ecc_counter);
-	GT_REG_READ(0x1450, &ecc_addr);
-	GT_REG_WRITE(0x1450, 0);
-
-	printf("Error Counter since Reset:  %8d\n", ecc_counter);
-	printf("Last error address       :0x%08x (" , ecc_addr & 0xfffffff8);
-	if (ecc_addr & 0x01)
-		printf("double");
-	else
-		printf("single");
-	printf(" bit) at DDR-RAM CS#%d\n", ((ecc_addr & 0x6) >> 1));
-
-	return 0;
-}
-
-
-U_BOOT_CMD(
-	show_ecc, 1, 1, do_show_ecc,
-	"Show Marvell MV64360 ECC Info",
-	"Show Marvell MV64360 ECC Counter and last error."
-);
diff --git a/board/esd/cpci750/serial.c b/board/esd/cpci750/serial.c
deleted file mode 100644
index 6c2cf215acf..00000000000
--- a/board/esd/cpci750/serial.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * modified for cpci750 board by
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * serial.c - serial support for esd cpci750 board
- */
-
-/* supports the MPSC */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-#include "../../Marvell/include/memory.h"
-
-#include "mpsc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int cpci750_serial_init(void)
-{
-	mpsc_init (gd->baudrate);
-
-	return (0);
-}
-
-static void cpci750_serial_putc(const char c)
-{
-	if (c == '\n')
-		mpsc_putchar ('\r');
-
-	mpsc_putchar (c);
-}
-
-static int cpci750_serial_getc(void)
-{
-	return mpsc_getchar ();
-}
-
-static int cpci750_serial_tstc(void)
-{
-	return mpsc_test_char ();
-}
-
-static void cpci750_serial_setbrg(void)
-{
-	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
-}
-
-static struct serial_device cpci750_serial_drv = {
-	.name	= "cpci750_serial",
-	.start	= cpci750_serial_init,
-	.stop	= NULL,
-	.setbrg	= cpci750_serial_setbrg,
-	.putc	= cpci750_serial_putc,
-	.puts	= default_serial_puts,
-	.getc	= cpci750_serial_getc,
-	.tstc	= cpci750_serial_tstc,
-};
-
-void cpci750_serial_initialize(void)
-{
-	serial_register(&cpci750_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &cpci750_serial_drv;
-}
-
-#if defined(CONFIG_CMD_KGDB)
-void kgdb_serial_init (void)
-{
-}
-
-void putDebugChar (int c)
-{
-	serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
-	serial_puts (str);
-}
-
-int getDebugChar (void)
-{
-	return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
-	return;
-}
-#endif
diff --git a/board/esd/meesc/Kconfig b/board/esd/meesc/Kconfig
index 7d5c3ca9800..5041041dd26 100644
--- a/board/esd/meesc/Kconfig
+++ b/board/esd/meesc/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MEESC
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "meesc"
 
diff --git a/board/esd/otc570/Kconfig b/board/esd/otc570/Kconfig
index 7c5ce90a7df..55a2f70f402 100644
--- a/board/esd/otc570/Kconfig
+++ b/board/esd/otc570/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_OTC570
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "otc570"
 
diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c
index 3481e46436a..40b135f2ba0 100644
--- a/board/esd/pmc440/cmd_pmc440.c
+++ b/board/esd/pmc440/cmd_pmc440.c
@@ -347,16 +347,16 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		return 1;
 	}
 
-	base = gd->bd->bi_memsize;
+	base = (u32)gd->ram_size;
 #if defined(CONFIG_LOGBUFFER)
 	base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
 #endif
 	/*
-	 * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
+	 * gd->ram_size == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
 	 */
 	param = base - (pram << 10);
 	printf("PARAM: @%08x\n", param);
-	debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base);
+	debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->ram_size, base);
 
 	/* clear entire PA ram */
 	memset((void*)param, 0, (pram << 10));
diff --git a/board/esg/ima3-mx53/Kconfig b/board/esg/ima3-mx53/Kconfig
index 5593689e724..d73238f9a90 100644
--- a/board/esg/ima3-mx53/Kconfig
+++ b/board/esg/ima3-mx53/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_IMA3_MX53
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "ima3-mx53"
 
diff --git a/board/eukrea/cpu9260/Kconfig b/board/eukrea/cpu9260/Kconfig
index 53ae917c767..9bd077b1ff1 100644
--- a/board/eukrea/cpu9260/Kconfig
+++ b/board/eukrea/cpu9260/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_CPU9260
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "cpu9260"
 
diff --git a/board/eukrea/cpuat91/Kconfig b/board/eukrea/cpuat91/Kconfig
index f2b02dc1c22..b69e4c3f82b 100644
--- a/board/eukrea/cpuat91/Kconfig
+++ b/board/eukrea/cpuat91/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_CPUAT91
 
-config SYS_CPU
-	default "arm920t"
-
 config SYS_BOARD
 	default "cpuat91"
 
diff --git a/board/exmeritus/hww1u1a/Kconfig b/board/exmeritus/hww1u1a/Kconfig
deleted file mode 100644
index 7a76b4358e9..00000000000
--- a/board/exmeritus/hww1u1a/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_HWW1U1A
-
-config SYS_BOARD
-	default "hww1u1a"
-
-config SYS_VENDOR
-	default "exmeritus"
-
-config SYS_CONFIG_NAME
-	default "HWW1U1A"
-
-endif
diff --git a/board/exmeritus/hww1u1a/MAINTAINERS b/board/exmeritus/hww1u1a/MAINTAINERS
deleted file mode 100644
index b37f10b17ae..00000000000
--- a/board/exmeritus/hww1u1a/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-HWW1U1A BOARD
-#M:	Kyle Moffett <Kyle.D.Moffett@boeing.com>
-S:	Orphan (since 2014-06)
-F:	board/exmeritus/hww1u1a/
-F:	include/configs/HWW1U1A.h
-F:	configs/HWW1U1A_defconfig
diff --git a/board/exmeritus/hww1u1a/Makefile b/board/exmeritus/hww1u1a/Makefile
deleted file mode 100644
index d0cd87828ef..00000000000
--- a/board/exmeritus/hww1u1a/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright 2007-2009 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= hww1u1a.o
-obj-y	+= law.o
-obj-y	+= tlb.o
-obj-$(CONFIG_DDR_SPD) += ddr.o
diff --git a/board/exmeritus/hww1u1a/ddr.c b/board/exmeritus/hww1u1a/ddr.c
deleted file mode 100644
index e1f6865f42c..00000000000
--- a/board/exmeritus/hww1u1a/ddr.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2009-2010 eXMeritus, A Boeing Company
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * We only support one DIMM, so according to the P2020 docs we should
-	 * set the options as follows:
-	 */
-	popts->cs_local_opts[0].odt_rd_cfg = 0;
-	popts->cs_local_opts[0].odt_wr_cfg = 4;
-	popts->cs_local_opts[1].odt_rd_cfg = 0;
-	popts->cs_local_opts[1].odt_wr_cfg = 0;
-	popts->half_strength_driver_enable = 0;
-
-	/* Manually configured for our static clock rate */
-	popts->clk_adjust = 4;
-	popts->cpo_override = 4;
-	popts->write_data_delay = 2;
-	popts->twot_en = 0;
-}
diff --git a/board/exmeritus/hww1u1a/gpios.h b/board/exmeritus/hww1u1a/gpios.h
deleted file mode 100644
index 499880f1a02..00000000000
--- a/board/exmeritus/hww1u1a/gpios.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2010 eXMeritus, A Boeing Company
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/mpc85xx_gpio.h>
-
-/* Common CPU A/B GPIOs (GPIO8-GPIO15 and IRQ4-IRQ6) */
-#define GPIO_CPU_ID		(1UL << (31 -  8))
-#define GPIO_BLUE_LED		(1UL << (31 -  9))
-#define GPIO_DIMM_RESET		(1UL << (31 - 10))
-#define GPIO_USB_RESET		(1UL << (31 - 11))
-#define GPIO_UNUSED_12		(1UL << (31 - 12))
-#define GPIO_GETH0_RESET	(1UL << (31 - 13))
-#define GPIO_RS422_RE		(1UL << (31 - 14))
-#define GPIO_RS422_DE		(1UL << (31 - 15))
-#define IRQ_I2CINT		(1UL << (31 - 20))
-#define IRQ_FANINT		(1UL << (31 - 21))
-#define IRQ_DIMM_EVENT		(1UL << (31 - 22))
-
-#define GPIO_RESETS (GPIO_DIMM_RESET|GPIO_USB_RESET|GPIO_GETH0_RESET)
-
-/* CPU A GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
-#define GPIO_CPUA_UNUSED_0	(1UL << (31 -  0))
-#define GPIO_CPUA_CPU_READY	(1UL << (31 -  1))
-#define GPIO_CPUA_DEBUG_LED2	(1UL << (31 -  2))
-#define GPIO_CPUA_DEBUG_LED1	(1UL << (31 -  3))
-#define GPIO_CPUA_TDIS2B	(1UL << (31 -  4)) /* MAC 2 TX B */
-#define GPIO_CPUA_TDIS2A	(1UL << (31 -  5)) /* MAC 2 TX A */
-#define GPIO_CPUA_TDIS1B	(1UL << (31 -  6)) /* MAC 1 TX B */
-#define GPIO_CPUA_TDIS1A	(1UL << (31 -  7)) /* MAC 1 TX A */
-#define IRQ_CPUA_UNUSED_0	(1UL << (31 - 16))
-#define IRQ_CPUA_UNUSED_1	(1UL << (31 - 17))
-#define IRQ_CPUA_UNUSED_2	(1UL << (31 - 18))
-#define IRQ_CPUA_UNUSED_3	(1UL << (31 - 19))
-
-/* CPU B GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
-#define GPIO_CPUB_RMUX_SEL1B	(1UL << (31 -  0))
-#define GPIO_CPUB_RMUX_SEL0B	(1UL << (31 -  1))
-#define GPIO_CPUB_RMUX_SEL1A	(1UL << (31 -  2))
-#define GPIO_CPUB_RMUX_SEL0A	(1UL << (31 -  3))
-#define GPIO_CPUB_UNUSED_4	(1UL << (31 -  4))
-#define GPIO_CPUB_CPU_READY	(1UL << (31 -  5))
-#define GPIO_CPUB_DEBUG_LED2	(1UL << (31 -  6))
-#define GPIO_CPUB_DEBUG_LED1	(1UL << (31 -  7))
-#define IRQ_CPUB_SD_1A		(1UL << (31 - 16))
-#define IRQ_CPUB_SD_2B		(1UL << (31 - 17))
-#define IRQ_CPUB_SD_2A		(1UL << (31 - 18))
-#define IRQ_CPUB_SD_1B		(1UL << (31 - 19))
-
-/* If it isn't CPU A then it's CPU B */
-static inline unsigned int hww1u1a_is_cpu_a(void)
-{
-	return !mpc85xx_gpio_get(GPIO_CPU_ID);
-}
diff --git a/board/exmeritus/hww1u1a/hww1u1a.c b/board/exmeritus/hww1u1a/hww1u1a.c
deleted file mode 100644
index 643ece1ae65..00000000000
--- a/board/exmeritus/hww1u1a/hww1u1a.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Copyright 2009-2011 eXMeritus, A Boeing Company
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <linux/ctype.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <asm/fsl_law.h>
-#include <netdev.h>
-#include <malloc.h>
-#include <i2c.h>
-#include <pca953x.h>
-
-#include "gpios.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	unsigned int gpio_high = 0;
-	unsigned int gpio_low  = 0;
-	unsigned int gpio_in   = 0;
-	unsigned int i;
-	struct ccsr_ddr __iomem *ddr;
-
-	puts("Board: HWW-1U-1A ");
-
-	/*
-	 * First just figure out which CPU we're on, then use that to
-	 * configure the lists of other GPIOs to be programmed.
-	 */
-	mpc85xx_gpio_set_in(GPIO_CPU_ID);
-	if (hww1u1a_is_cpu_a()) {
-		puts("CPU A\n");
-
-		/* We want to turn on some LEDs */
-		gpio_high |= GPIO_CPUA_CPU_READY;
-		gpio_low  |= GPIO_CPUA_DEBUG_LED1;
-		gpio_low  |= GPIO_CPUA_DEBUG_LED2;
-
-		/* Disable the unused transmitters */
-		gpio_low  |= GPIO_CPUA_TDIS1A;
-		gpio_high |= GPIO_CPUA_TDIS1B;
-		gpio_low  |= GPIO_CPUA_TDIS2A;
-		gpio_high |= GPIO_CPUA_TDIS2B;
-	} else {
-		puts("CPU B\n");
-
-		/* We want to turn on some LEDs */
-		gpio_high |= GPIO_CPUB_CPU_READY;
-		gpio_low  |= GPIO_CPUB_DEBUG_LED1;
-		gpio_low  |= GPIO_CPUB_DEBUG_LED2;
-
-		/* Enable the appropriate receivers */
-		gpio_high |= GPIO_CPUB_RMUX_SEL0A;
-		gpio_high |= GPIO_CPUB_RMUX_SEL0B;
-		gpio_low  |= GPIO_CPUB_RMUX_SEL1A;
-		gpio_low  |= GPIO_CPUB_RMUX_SEL1B;
-	}
-
-	/* These GPIOs are common */
-	gpio_in   |= IRQ_I2CINT | IRQ_FANINT | IRQ_DIMM_EVENT;
-	gpio_low  |= GPIO_RS422_RE;
-	gpio_high |= GPIO_RS422_DE;
-
-	/* Ok, now go ahead and program all of those in one go */
-	mpc85xx_gpio_set(gpio_high|gpio_low|gpio_in,
-			 gpio_high|gpio_low,
-			 gpio_high);
-
-	/*
-	 * If things have been taken out of reset early (for example, by one
-	 * of the BDI3000 debuggers), then we need to put them back in reset
-	 * and delay a while before we continue.
-	 */
-	if (mpc85xx_gpio_get(GPIO_RESETS)) {
-		ddr = (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
-
-		puts("Debugger detected... extra device reset enabled!\n");
-
-		/* Put stuff into reset and disable the DDR controller */
-		mpc85xx_gpio_set_low(GPIO_RESETS);
-		out_be32(&ddr->sdram_cfg, 0x00000000);
-
-		puts("    Waiting 1 sec for reset...");
-		for (i = 0; i < 10; i++) {
-			udelay(100000);
-			puts(".");
-		}
-		puts("\n");
-	}
-
-	/* Now bring everything back out of reset again */
-	mpc85xx_gpio_set_high(GPIO_RESETS);
-	return 0;
-}
-
-/*
- * This little shell function just returns whether or not it's CPU A.
- * It can be used to select the right device-tree when booting, etc.
- */
-int do_hww1u1a_test_cpu_a(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
-{
-	if (argc > 1)
-		cmd_usage(cmdtp);
-
-	if (hww1u1a_is_cpu_a())
-		return 0;
-	else
-		return 1;
-}
-U_BOOT_CMD(
-	test_cpu_a, 1, 0, do_hww1u1a_test_cpu_a,
-	"Test if this is CPU A (versus B) on the eXMeritus HWW-1U-1A board",
-	""
-);
-
-/* Create a prompt-like string: "uboot@HOSTNAME% " */
-#define PROMPT_PREFIX "uboot@exm"
-#define PROMPT_SUFFIX "% "
-
-/* This function returns a PS1 prompt based on the serial number */
-static char *hww1u1a_prompt;
-const char *hww1u1a_get_ps1(void)
-{
-	unsigned long len, i, j;
-	const char *serialnr;
-
-	/* If our prompt was already set, just use that */
-	if (hww1u1a_prompt)
-		return hww1u1a_prompt;
-
-	/* Use our serial number if present, otherwise a default */
-	serialnr = getenv("serial#");
-	if (!serialnr || !serialnr[0])
-		serialnr = "999999-X";
-
-	/*
-	 * We will turn the serial number into a hostname by:
-	 *   (A) Delete all non-alphanumerics.
-	 *   (B) Lowercase all letters.
-	 *   (C) Prefix "exm".
-	 *   (D) Suffix "a" for CPU A and "b" for CPU B.
-	 */
-	for (i = 0, len = 0; serialnr[i]; i++) {
-		if (isalnum(serialnr[i]))
-			len++;
-	}
-
-	len += sizeof(PROMPT_PREFIX PROMPT_SUFFIX) + 1; /* Includes NUL */
-	hww1u1a_prompt = malloc(len);
-	if (!hww1u1a_prompt)
-		return PROMPT_PREFIX "UNKNOWN(ENOMEM)" PROMPT_SUFFIX;
-
-	/* Now actually fill it in */
-	i = 0;
-
-	/* Handle the prefix */
-	for (j = 0; j < sizeof(PROMPT_PREFIX) - 1; j++)
-		hww1u1a_prompt[i++] = PROMPT_PREFIX[j];
-
-	/* Now the serial# part of the hostname */
-	for (j = 0; serialnr[j]; j++)
-		if (isalnum(serialnr[j]))
-			hww1u1a_prompt[i++] = tolower(serialnr[j]);
-
-	/* Now the CPU id ("a" or "b") */
-	hww1u1a_prompt[i++] = hww1u1a_is_cpu_a() ? 'a' : 'b';
-
-	/* Finally the suffix */
-	for (j = 0; j < sizeof(PROMPT_SUFFIX); j++)
-		hww1u1a_prompt[i++] = PROMPT_SUFFIX[j];
-
-	/* This should all have added up, but just in case */
-	hww1u1a_prompt[len - 1] = '\0';
-
-	/* Now we're done */
-	return hww1u1a_prompt;
-}
-
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap bootflash region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for FLASH */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	struct tsec_info_struct tsec_info[4];
-	struct fsl_pq_mdio_info mdio_info;
-
-	SET_STD_TSEC_INFO(tsec_info[0], 1);
-	SET_STD_TSEC_INFO(tsec_info[1], 2);
-	SET_STD_TSEC_INFO(tsec_info[2], 3);
-
-	if (hww1u1a_is_cpu_a())
-		tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUA;
-	else
-		tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUB;
-
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-	fsl_pq_mdio_init(bis, &mdio_info);
-
-	tsec_eth_init(bis, tsec_info, 3);
-	return pci_eth_init(bis);
-}
-
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = getenv_bootm_low();
-	size = getenv_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-	FT_FSL_PCI_SETUP;
-}
diff --git a/board/exmeritus/hww1u1a/law.c b/board/exmeritus/hww1u1a/law.c
deleted file mode 100644
index c7dc58d5968..00000000000
--- a/board/exmeritus/hww1u1a/law.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/exmeritus/hww1u1a/tlb.c b/board/exmeritus/hww1u1a/tlb.c
deleted file mode 100644
index 7f5a36f1ebf..00000000000
--- a/board/exmeritus/hww1u1a/tlb.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright 2009-2010 eXMeritus, A Boeing Company
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0,	CONFIG_SYS_INIT_RAM_ADDR      +  0 * 1024,
-				CONFIG_SYS_INIT_RAM_ADDR_PHYS +  0 * 1024,
-				MAS3_SX|MAS3_SW|MAS3_SR, 0,
-				0, 0, BOOKE_PAGESZ_4K, 0),
-
-	SET_TLB_ENTRY(0,	CONFIG_SYS_INIT_RAM_ADDR      +  4 * 1024,
-				CONFIG_SYS_INIT_RAM_ADDR_PHYS +  4 * 1024,
-				MAS3_SX|MAS3_SW|MAS3_SR, 0,
-				0, 0, BOOKE_PAGESZ_4K, 0),
-
-	SET_TLB_ENTRY(0,	CONFIG_SYS_INIT_RAM_ADDR      +  8 * 1024,
-				CONFIG_SYS_INIT_RAM_ADDR_PHYS +  8 * 1024,
-				MAS3_SX|MAS3_SW|MAS3_SR, 0,
-				0, 0, BOOKE_PAGESZ_4K, 0),
-
-	SET_TLB_ENTRY(0,	CONFIG_SYS_INIT_RAM_ADDR      + 12 * 1024,
-				CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
-				MAS3_SX|MAS3_SW|MAS3_SR, 0,
-				0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Boot page */
-	SET_TLB_ENTRY(1,	CONFIG_BPTR_VIRT_ADDR,
-				CONFIG_BPTR_VIRT_ADDR,
-				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-				0, 0, BOOKE_PAGESZ_4K, 1),
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1,	CONFIG_SYS_CCSRBAR,
-				CONFIG_SYS_CCSRBAR_PHYS,
-				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-				0, 1, BOOKE_PAGESZ_1M, 1),
-
-	/*
-	 * W**G* - FLASH (Will be *I*G* after relocation to RAM)
-	 *
-	 * This maps both SPI FLASH chips (128MByte per chip)
-	 */
-	SET_TLB_ENTRY(1,	CONFIG_SYS_FLASH_BASE,
-				CONFIG_SYS_FLASH_BASE_PHYS,
-				MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-				0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * *I*G* - PCI memory
-	 *
-	 * We have 1.5GB total PCI-E memory space to map and we want to use
-	 * the minimum possible number of TLB entries.  Since Book-E TLB
-	 * entries are sized in powers of 4, we use 1GB + 256MB + 256MB.
-	 */
-	SET_TLB_ENTRY(1,	CONFIG_SYS_PCIE3_MEM_VIRT,
-				CONFIG_SYS_PCIE3_MEM_PHYS,
-				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-				0, 3, BOOKE_PAGESZ_1G, 1),
-	SET_TLB_ENTRY(1,	CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
-				CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
-				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-				0, 4, BOOKE_PAGESZ_256M, 1),
-	SET_TLB_ENTRY(1,	CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
-				CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
-				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-				0, 5, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * *I*G* - PCI I/O
-	 *
-	 * This one entry covers all 3 64k PCI-E I/O windows
-	 */
-	SET_TLB_ENTRY(1,	CONFIG_SYS_PCIE3_IO_VIRT,
-				CONFIG_SYS_PCIE3_IO_PHYS,
-				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-				0, 6, BOOKE_PAGESZ_256K, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/faraday/a320evb/Kconfig b/board/faraday/a320evb/Kconfig
index bfa620708d4..02c42cb0a29 100644
--- a/board/faraday/a320evb/Kconfig
+++ b/board/faraday/a320evb/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_A320EVB
 
-config SYS_CPU
-	default "arm920t"
-
 config SYS_BOARD
 	default "a320evb"
 
diff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig
index 3cee468a3dd..119b9550410 100644
--- a/board/freescale/ls1021aqds/Kconfig
+++ b/board/freescale/ls1021aqds/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_LS1021AQDS
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "ls1021aqds"
 
diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS
index ccf45131b87..e30e94471b1 100644
--- a/board/freescale/ls1021aqds/MAINTAINERS
+++ b/board/freescale/ls1021aqds/MAINTAINERS
@@ -5,3 +5,4 @@ F:	board/freescale/ls1021aqds/
 F:	include/configs/ls1021aqds.h
 F:	configs/ls1021aqds_nor_defconfig
 F:	configs/ls1021aqds_ddr4_nor_defconfig
+F:	configs/ls1021aqds_nor_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 12e83f76454..5fafc856720 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -13,6 +13,7 @@
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
+#include <fsl_sec.h>
 
 #include "../common/qixis.h"
 #include "ls1021aqds_qixis.h"
@@ -213,6 +214,15 @@ int config_serdes_mux(void)
 	return 0;
 }
 
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#ifdef CONFIG_FSL_CAAM
+	return sec_init();
+#endif
+}
+#endif
+
 int board_init(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
diff --git a/board/freescale/ls1021atwr/Kconfig b/board/freescale/ls1021atwr/Kconfig
index 312f9388fc0..bc50b8d9668 100644
--- a/board/freescale/ls1021atwr/Kconfig
+++ b/board/freescale/ls1021atwr/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_LS1021ATWR
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "ls1021atwr"
 
diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS
index 4e5bc15a0d6..8def0e5ac4b 100644
--- a/board/freescale/ls1021atwr/MAINTAINERS
+++ b/board/freescale/ls1021atwr/MAINTAINERS
@@ -4,3 +4,4 @@ S:	Maintained
 F:	board/freescale/ls1021atwr/
 F:	include/configs/ls1021atwr.h
 F:	configs/ls1021atwr_nor_defconfig
+F:	configs/ls1021atwr_nor_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index b522ff28e5e..50d564055b1 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -16,6 +16,7 @@
 #include <netdev.h>
 #include <fsl_mdio.h>
 #include <tsec.h>
+#include <fsl_sec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -280,6 +281,15 @@ int board_init(void)
 	return 0;
 }
 
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#ifdef CONFIG_FSL_CAAM
+	return sec_init();
+#endif
+}
+#endif
+
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
diff --git a/board/freescale/mpc5121ads/README b/board/freescale/mpc5121ads/README
index defcd6b469a..741bc40382e 100644
--- a/board/freescale/mpc5121ads/README
+++ b/board/freescale/mpc5121ads/README
@@ -1,7 +1,7 @@
 To configure for the current (Rev 3.x) ADS5121
-	make ads5121_config
+	make mpc5121ads_config
 This will automatically include PCI, the Real Time CLock, add backup flash
 ability and set the correct frequency and memory configuration.
 
 To configure for the older Rev 2 ADS5121 type (this will not have PCI)
-	make ads5121_rev2_config
+	make mpc5121ads_rev2_config
diff --git a/board/freescale/mx23evk/Kconfig b/board/freescale/mx23evk/Kconfig
index 1bbbe2d5f51..51a8f9f773c 100644
--- a/board/freescale/mx23evk/Kconfig
+++ b/board/freescale/mx23evk/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX23EVK
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "mx23evk"
 
diff --git a/board/freescale/mx25pdk/Kconfig b/board/freescale/mx25pdk/Kconfig
index a693239701b..af06b4c827e 100644
--- a/board/freescale/mx25pdk/Kconfig
+++ b/board/freescale/mx25pdk/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX25PDK
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "mx25pdk"
 
diff --git a/board/freescale/mx28evk/Kconfig b/board/freescale/mx28evk/Kconfig
index cc654bcfa5a..39777bd70fa 100644
--- a/board/freescale/mx28evk/Kconfig
+++ b/board/freescale/mx28evk/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX28EVK
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "mx28evk"
 
diff --git a/board/freescale/mx31ads/Kconfig b/board/freescale/mx31ads/Kconfig
index b4ea64b4051..eeeb6f490fd 100644
--- a/board/freescale/mx31ads/Kconfig
+++ b/board/freescale/mx31ads/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX31ADS
 
-config SYS_CPU
-	default "arm1136"
-
 config SYS_BOARD
 	default "mx31ads"
 
diff --git a/board/freescale/mx31pdk/Kconfig b/board/freescale/mx31pdk/Kconfig
index 68c3880638c..055545c9306 100644
--- a/board/freescale/mx31pdk/Kconfig
+++ b/board/freescale/mx31pdk/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX31PDK
 
-config SYS_CPU
-	default "arm1136"
-
 config SYS_BOARD
 	default "mx31pdk"
 
diff --git a/board/freescale/mx35pdk/Kconfig b/board/freescale/mx35pdk/Kconfig
index ca5b40f07d1..021d19e5511 100644
--- a/board/freescale/mx35pdk/Kconfig
+++ b/board/freescale/mx35pdk/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX35PDK
 
-config SYS_CPU
-	default "arm1136"
-
 config SYS_BOARD
 	default "mx35pdk"
 
diff --git a/board/freescale/mx51evk/Kconfig b/board/freescale/mx51evk/Kconfig
index 07861a97063..f9b69cbd661 100644
--- a/board/freescale/mx51evk/Kconfig
+++ b/board/freescale/mx51evk/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX51EVK
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "mx51evk"
 
diff --git a/board/freescale/mx53ard/Kconfig b/board/freescale/mx53ard/Kconfig
index 566df859856..41f46a04ac7 100644
--- a/board/freescale/mx53ard/Kconfig
+++ b/board/freescale/mx53ard/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX53ARD
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "mx53ard"
 
diff --git a/board/freescale/mx53evk/Kconfig b/board/freescale/mx53evk/Kconfig
index d064b104dc1..c226c1ca060 100644
--- a/board/freescale/mx53evk/Kconfig
+++ b/board/freescale/mx53evk/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX53EVK
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "mx53evk"
 
diff --git a/board/freescale/mx53loco/Kconfig b/board/freescale/mx53loco/Kconfig
index bc44e59bfcc..5ca1672bf7a 100644
--- a/board/freescale/mx53loco/Kconfig
+++ b/board/freescale/mx53loco/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX53LOCO
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "mx53loco"
 
diff --git a/board/freescale/mx53smd/Kconfig b/board/freescale/mx53smd/Kconfig
index 62c37d4e0ce..1195d33d067 100644
--- a/board/freescale/mx53smd/Kconfig
+++ b/board/freescale/mx53smd/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX53SMD
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "mx53smd"
 
diff --git a/board/freescale/mx6qarm2/Kconfig b/board/freescale/mx6qarm2/Kconfig
index f7f18db9fca..4af33af1852 100644
--- a/board/freescale/mx6qarm2/Kconfig
+++ b/board/freescale/mx6qarm2/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX6QARM2
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "mx6qarm2"
 
diff --git a/board/freescale/mx6qsabreauto/Kconfig b/board/freescale/mx6qsabreauto/Kconfig
index d0cf355bc11..cc2a140c52e 100644
--- a/board/freescale/mx6qsabreauto/Kconfig
+++ b/board/freescale/mx6qsabreauto/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX6QSABREAUTO
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "mx6qsabreauto"
 
diff --git a/board/freescale/mx6sabresd/Kconfig b/board/freescale/mx6sabresd/Kconfig
index 15b65c09f16..fa6ddb22921 100644
--- a/board/freescale/mx6sabresd/Kconfig
+++ b/board/freescale/mx6sabresd/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX6SABRESD
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "mx6sabresd"
 
diff --git a/board/freescale/mx6slevk/Kconfig b/board/freescale/mx6slevk/Kconfig
index 558aeab0e3d..d32da900a39 100644
--- a/board/freescale/mx6slevk/Kconfig
+++ b/board/freescale/mx6slevk/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX6SLEVK
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "mx6slevk"
 
diff --git a/board/freescale/mx6sxsabresd/Kconfig b/board/freescale/mx6sxsabresd/Kconfig
index 2a86b68afc8..940983e932c 100644
--- a/board/freescale/mx6sxsabresd/Kconfig
+++ b/board/freescale/mx6sxsabresd/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX6SXSABRESD
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "mx6sxsabresd"
 
diff --git a/board/freescale/vf610twr/Kconfig b/board/freescale/vf610twr/Kconfig
index 684ef279c3b..ef091d6b2bf 100644
--- a/board/freescale/vf610twr/Kconfig
+++ b/board/freescale/vf610twr/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_VF610TWR
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "vf610twr"
 
diff --git a/board/gaisler/gr_cpci_ax2000/Kconfig b/board/gaisler/gr_cpci_ax2000/Kconfig
index 8da050404cf..c12a002179a 100644
--- a/board/gaisler/gr_cpci_ax2000/Kconfig
+++ b/board/gaisler/gr_cpci_ax2000/Kconfig
@@ -1,14 +1,8 @@
 if TARGET_GR_CPCI_AX2000
 
-config SYS_CPU
-	default "leon3"
-
 config SYS_BOARD
 	default "gr_cpci_ax2000"
 
-config SYS_VENDOR
-	default "gaisler"
-
 config SYS_CONFIG_NAME
 	default "gr_cpci_ax2000"
 
diff --git a/board/gaisler/gr_cpci_ax2000/config.mk b/board/gaisler/gr_cpci_ax2000/config.mk
deleted file mode 100644
index 731a53905f8..00000000000
--- a/board/gaisler/gr_cpci_ax2000/config.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# (C) Copyright 2008
-# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# GR-CPCI-AX2000 board
-#
-
-# U-BOOT IN FLASH
-CONFIG_SYS_TEXT_BASE = 0x00000000
-
-# U-BOOT IN RAM or SDRAM with -nosram flag set when starting GRMON
-#CONFIG_SYS_TEXT_BASE = 0x40000000
-
-# U-BOOT IN SDRAM
-#CONFIG_SYS_TEXT_BASE = 0x60000000
diff --git a/board/gaisler/gr_ep2s60/Kconfig b/board/gaisler/gr_ep2s60/Kconfig
index 00b2097cf43..f49937c55a6 100644
--- a/board/gaisler/gr_ep2s60/Kconfig
+++ b/board/gaisler/gr_ep2s60/Kconfig
@@ -1,14 +1,8 @@
 if TARGET_GR_EP2S60
 
-config SYS_CPU
-	default "leon3"
-
 config SYS_BOARD
 	default "gr_ep2s60"
 
-config SYS_VENDOR
-	default "gaisler"
-
 config SYS_CONFIG_NAME
 	default "gr_ep2s60"
 
diff --git a/board/gaisler/gr_ep2s60/config.mk b/board/gaisler/gr_ep2s60/config.mk
deleted file mode 100644
index 6e01f07c0ce..00000000000
--- a/board/gaisler/gr_ep2s60/config.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2008
-# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# Altera NIOS delopment board Stratix II edition, FPGA device EP2S60,
-# with GRLIB Template design (GPL Open Source SPARC/LEON3)
-#
-
-# U-BOOT IN FLASH
-CONFIG_SYS_TEXT_BASE = 0x00000000
-
-# U-BOOT IN SDRAM
-#CONFIG_SYS_TEXT_BASE = 0x40000000
diff --git a/board/gaisler/gr_xc3s_1500/Kconfig b/board/gaisler/gr_xc3s_1500/Kconfig
index 765e028b51e..e695ba2cddb 100644
--- a/board/gaisler/gr_xc3s_1500/Kconfig
+++ b/board/gaisler/gr_xc3s_1500/Kconfig
@@ -1,14 +1,8 @@
 if TARGET_GR_XC3S_1500
 
-config SYS_CPU
-	default "leon3"
-
 config SYS_BOARD
 	default "gr_xc3s_1500"
 
-config SYS_VENDOR
-	default "gaisler"
-
 config SYS_CONFIG_NAME
 	default "gr_xc3s_1500"
 
diff --git a/board/gaisler/gr_xc3s_1500/config.mk b/board/gaisler/gr_xc3s_1500/config.mk
deleted file mode 100644
index e4a66cbcf1e..00000000000
--- a/board/gaisler/gr_xc3s_1500/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2007
-# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# GR-XC3S-1500 board
-#
-
-# U-BOOT IN FLASH
-CONFIG_SYS_TEXT_BASE = 0x00000000
-
-# U-BOOT IN RAM
-#CONFIG_SYS_TEXT_BASE = 0x40000000
diff --git a/board/gaisler/grsim/Kconfig b/board/gaisler/grsim/Kconfig
index 751fa03be4d..18598d3c2a7 100644
--- a/board/gaisler/grsim/Kconfig
+++ b/board/gaisler/grsim/Kconfig
@@ -1,14 +1,8 @@
 if TARGET_GRSIM
 
-config SYS_CPU
-	default "leon3"
-
 config SYS_BOARD
 	default "grsim"
 
-config SYS_VENDOR
-	default "gaisler"
-
 config SYS_CONFIG_NAME
 	default "grsim"
 
diff --git a/board/gaisler/grsim/config.mk b/board/gaisler/grsim/config.mk
deleted file mode 100644
index d1f61dac76d..00000000000
--- a/board/gaisler/grsim/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2007
-# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# GRSIM simulating a LEON3 GR-XC3S-1500 board
-#
-
-# U-BOOT IN FLASH
-CONFIG_SYS_TEXT_BASE = 0x00000000
-
-# U-BOOT IN RAM
-#CONFIG_SYS_TEXT_BASE = 0x40000000
diff --git a/board/gaisler/grsim_leon2/Kconfig b/board/gaisler/grsim_leon2/Kconfig
index 0907f3af891..0d21a0a985e 100644
--- a/board/gaisler/grsim_leon2/Kconfig
+++ b/board/gaisler/grsim_leon2/Kconfig
@@ -1,14 +1,8 @@
 if TARGET_GRSIM_LEON2
 
-config SYS_CPU
-	default "leon2"
-
 config SYS_BOARD
 	default "grsim_leon2"
 
-config SYS_VENDOR
-	default "gaisler"
-
 config SYS_CONFIG_NAME
 	default "grsim_leon2"
 
diff --git a/board/gaisler/grsim_leon2/config.mk b/board/gaisler/grsim_leon2/config.mk
deleted file mode 100644
index f98b23b8005..00000000000
--- a/board/gaisler/grsim_leon2/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2007
-# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# GRSIM simulating a LEON2 board
-#
-
-# RUN U-BOOT FROM PROM
-CONFIG_SYS_TEXT_BASE = 0x00000000
-
-# RUN U-BOOT FROM RAM
-#CONFIG_SYS_TEXT_BASE = 0x40000000
diff --git a/board/gateworks/gw_ventana/Kconfig b/board/gateworks/gw_ventana/Kconfig
index 82909a80a31..c233e90c658 100644
--- a/board/gateworks/gw_ventana/Kconfig
+++ b/board/gateworks/gw_ventana/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_GW_VENTANA
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "gw_ventana"
 
diff --git a/board/genesi/mx51_efikamx/Kconfig b/board/genesi/mx51_efikamx/Kconfig
index 87d15a59d49..355702a4b6d 100644
--- a/board/genesi/mx51_efikamx/Kconfig
+++ b/board/genesi/mx51_efikamx/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX51_EFIKAMX
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "mx51_efikamx"
 
diff --git a/board/gumstix/pepper/Kconfig b/board/gumstix/pepper/Kconfig
index 0b739551671..6f94612fe21 100644
--- a/board/gumstix/pepper/Kconfig
+++ b/board/gumstix/pepper/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_PEPPER
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "pepper"
 
diff --git a/board/h2200/Kconfig b/board/h2200/Kconfig
index 75956be823d..c0e0c1e7639 100644
--- a/board/h2200/Kconfig
+++ b/board/h2200/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_H2200
 
-config SYS_CPU
-	default "pxa"
-
 config SYS_BOARD
 	default "h2200"
 
diff --git a/board/hale/tt01/Kconfig b/board/hale/tt01/Kconfig
index 40e56cb11f5..af9828a4bf0 100644
--- a/board/hale/tt01/Kconfig
+++ b/board/hale/tt01/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_TT01
 
-config SYS_CPU
-	default "arm1136"
-
 config SYS_BOARD
 	default "tt01"
 
diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h
index 17c122cf509..d6c5df203e6 100644
--- a/board/htkw/mcx/mcx.h
+++ b/board/htkw/mcx/mcx.h
@@ -339,7 +339,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M4))\
 	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTU | DIS | M4))\
 	/* JTAG */\
-	MUX_VAL(CP(JTAG_nTRST),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(JTAG_NTRST),		(IEN | PTU | EN  | M4)) \
 	MUX_VAL(CP(JTAG_TCK),		(IEN | PTU | EN  | M4)) \
 	MUX_VAL(CP(JTAG_TMS),		(IEN | PTU | EN  | M4)) \
 	MUX_VAL(CP(JTAG_TDI),		(IEN | PTU | EN  | M4)) \
diff --git a/board/hymod/Kconfig b/board/hymod/Kconfig
deleted file mode 100644
index fa162ebc96b..00000000000
--- a/board/hymod/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_HYMOD
-
-config SYS_BOARD
-	default "hymod"
-
-config SYS_CONFIG_NAME
-	default "hymod"
-
-endif
diff --git a/board/hymod/MAINTAINERS b/board/hymod/MAINTAINERS
deleted file mode 100644
index e27fe974c8f..00000000000
--- a/board/hymod/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-HYMOD BOARD
-M:	Murray Jensen <Murray.Jensen@csiro.au>
-S:	Maintained
-F:	board/hymod/
-F:	include/configs/hymod.h
-F:	configs/hymod_defconfig
diff --git a/board/hymod/Makefile b/board/hymod/Makefile
deleted file mode 100644
index b9080b0a96c..00000000000
--- a/board/hymod/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= hymod.o flash.o bsp.o eeprom.o fetch.o input.o env.o
diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c
deleted file mode 100644
index e54640f2d2d..00000000000
--- a/board/hymod/bsp.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * hacked for Hymod FPGA support by Murray.Jensen@csiro.au, 29-Jan-01
- */
-
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include <asm/iopin_8260.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*-----------------------------------------------------------------------
- * Board Special Commands: FPGA load/store, EEPROM erase
- */
-
-#if defined(CONFIG_CMD_BSP)
-
-#define LOAD_SUCCESS		0
-#define LOAD_FAIL_NOCONF	1
-#define LOAD_FAIL_NOINIT	2
-#define LOAD_FAIL_NODONE	3
-
-#define STORE_SUCCESS		0
-
-/*
- * Programming the Hymod FPGAs
- *
- * The 8260 io port config table is set up so that the INIT pin is
- * held Low (Open Drain output 0) - this will delay the automatic
- * Power-On config until INIT is released (by making it an input).
- *
- * If the FPGA has been programmed before, then the assertion of PROGRAM
- * will initiate configuration (i.e. it begins clearing the RAM).
- *
- * When the FPGA is ready to receive configuration data (either after
- * releasing INIT after Power-On, or after asserting PROGRAM), it will
- * pull INIT high.
- *
- * Notes from Paul Dunn:
- *
- *  1. program pin should be forced low for >= 300ns
- *     (about 20 bus clock cycles minimum).
- *
- *  2. then wait for init to go high, which signals
- *     that the FPGA has cleared its internal memory
- *     and is ready to load
- *
- *  3. perform load writes of entire config file
- *
- *  4. wait for done to go high, which should be
- *     within a few bus clock cycles. If done has not
- *     gone high after reasonable period, then load
- *     has not worked (wait several ms?)
- */
-
-int
-fpga_load(int mezz, const uchar *addr, ulong size)
-{
-	hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
-	xlx_info_t *fp;
-	xlx_iopins_t *fpgaio;
-	volatile uchar *fpgabase;
-	volatile uint cnt;
-	const uchar *eaddr = addr + size;
-	int result;
-
-	if (mezz)
-		fp = &cp->mezz.xlx[0];
-	else
-		fp = &cp->main.xlx[0];
-
-	if (!fp->mmap.prog.exists)
-		return (LOAD_FAIL_NOCONF);
-
-	fpgabase = (uchar *)fp->mmap.prog.base;
-	fpgaio = &fp->iopins;
-
-	/* set enable HIGH if required */
-	if (fpgaio->enable_pin.flag)
-		iopin_set_high (&fpgaio->enable_pin);
-
-	/* ensure INIT is released (set it to be an input) */
-	iopin_set_in (&fpgaio->init_pin);
-
-	/* toggle PROG Low then High (will already be Low after Power-On) */
-	iopin_set_low (&fpgaio->prog_pin);
-	udelay (1);	/* minimum 300ns - 1usec should do it */
-	iopin_set_high (&fpgaio->prog_pin);
-
-	/* wait for INIT High */
-	cnt = 0;
-	while (!iopin_is_high (&fpgaio->init_pin))
-		if (++cnt == 10000000) {
-			result = LOAD_FAIL_NOINIT;
-			goto done;
-		}
-
-	/* write configuration data */
-	while (addr < eaddr)
-		*fpgabase = *addr++;
-
-	/* wait for DONE High */
-	cnt = 0;
-	while (!iopin_is_high (&fpgaio->done_pin))
-		if (++cnt == 100000000) {
-			result = LOAD_FAIL_NODONE;
-			goto done;
-		}
-
-	/* success */
-	result = LOAD_SUCCESS;
-
-  done:
-
-	if (fpgaio->enable_pin.flag)
-		iopin_set_low (&fpgaio->enable_pin);
-
-	return (result);
-}
-
-/* ------------------------------------------------------------------------- */
-int
-do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	uchar *addr, *save_addr;
-	ulong size;
-	int mezz, arg, result;
-
-	switch (argc) {
-
-	case 0:
-	case 1:
-		break;
-
-	case 2:
-		if (strcmp (argv[1], "info") == 0) {
-			printf ("\nHymod FPGA Info...\n");
-			printf ("\t\t\t\tAddress\t\tSize\n");
-			printf ("\tMain Configuration:\t0x%08x\t%d\n",
-				FPGA_MAIN_CFG_BASE, FPGA_MAIN_CFG_SIZE);
-			printf ("\tMain Register:\t\t0x%08x\t%d\n",
-				FPGA_MAIN_REG_BASE, FPGA_MAIN_REG_SIZE);
-			printf ("\tMain Port:\t\t0x%08x\t%d\n",
-				FPGA_MAIN_PORT_BASE, FPGA_MAIN_PORT_SIZE);
-			printf ("\tMezz Configuration:\t0x%08x\t%d\n",
-				FPGA_MEZZ_CFG_BASE, FPGA_MEZZ_CFG_SIZE);
-			return 0;
-		}
-		break;
-
-	case 3:
-		if (strcmp (argv[1], "store") == 0) {
-			addr = (uchar *) simple_strtoul (argv[2], NULL, 16);
-
-			save_addr = addr;
-#if 0
-			/* fpga readback unimplemented */
-			while (more readback data)
-				*addr++ = *fpga;
-			result = error ? STORE_FAIL_XXX : STORE_SUCCESS;
-#else
-			result = STORE_SUCCESS;
-#endif
-
-			if (result == STORE_SUCCESS) {
-				printf ("SUCCEEDED (%d bytes)\n",
-					addr - save_addr);
-				return 0;
-			} else
-				printf ("FAILED (%d bytes)\n",
-					addr - save_addr);
-			return 1;
-		}
-		break;
-
-	case 4:
-		if (strcmp (argv[1], "tftp") == 0) {
-			copy_filename (BootFile, argv[2], sizeof (BootFile));
-			load_addr = simple_strtoul (argv[3], NULL, 16);
-			NetBootFileXferSize = 0;
-
-			if (NetLoop(TFTPGET) <= 0) {
-				printf ("tftp transfer failed - aborting "
-					"fgpa load\n");
-				return 1;
-			}
-
-			if (NetBootFileXferSize == 0) {
-				printf ("can't determine file size - "
-					"aborting fpga load\n");
-				return 1;
-			}
-
-			printf ("File transfer succeeded - "
-				"beginning fpga load...");
-
-			result = fpga_load (0, (uchar *) load_addr,
-				NetBootFileXferSize);
-
-			if (result == LOAD_SUCCESS) {
-				printf ("SUCCEEDED\n");
-				return 0;
-			} else if (result == LOAD_FAIL_NOCONF)
-				printf ("FAILED (no CONF)\n");
-			else if (result == LOAD_FAIL_NOINIT)
-				printf ("FAILED (no INIT)\n");
-			else
-				printf ("FAILED (no DONE)\n");
-			return 1;
-
-		}
-		/* fall through ... */
-
-	case 5:
-		if (strcmp (argv[1], "load") == 0) {
-			if (argc == 5) {
-				if (strcmp (argv[2], "main") == 0)
-					mezz = 0;
-				else if (strcmp (argv[2], "mezz") == 0)
-					mezz = 1;
-				else {
-					printf ("FPGA type must be either "
-						"`main' or `mezz'\n");
-					return 1;
-				}
-				arg = 3;
-			} else {
-				mezz = 0;
-				arg = 2;
-			}
-
-			addr = (uchar *) simple_strtoul (argv[arg++], NULL, 16);
-			size = (ulong) simple_strtoul (argv[arg], NULL, 16);
-
-			result = fpga_load (mezz, addr, size);
-
-			if (result == LOAD_SUCCESS) {
-				printf ("SUCCEEDED\n");
-				return 0;
-			} else if (result == LOAD_FAIL_NOCONF)
-				printf ("FAILED (no CONF)\n");
-			else if (result == LOAD_FAIL_NOINIT)
-				printf ("FAILED (no INIT)\n");
-			else
-				printf ("FAILED (no DONE)\n");
-			return 1;
-		}
-		break;
-
-	default:
-		break;
-	}
-
-	return cmd_usage(cmdtp);
-}
-U_BOOT_CMD(
-	fpga,	6,	1,	do_fpga,
-	"FPGA sub-system",
-	"load [type] addr size\n"
-	"  - write the configuration data at memory address `addr',\n"
-	"    size `size' bytes, into the FPGA of type `type' (either\n"
-	"    `main' or `mezz', default `main'). e.g.\n"
-	"        `fpga load 100000 7d8f'\n"
-	"    loads the main FPGA with config data at address 100000\n"
-	"    HEX, size 7d8f HEX (32143 DEC) bytes\n"
-	"fpga tftp file addr\n"
-	"  - transfers `file' from the tftp server into memory at\n"
-	"    address `addr', then writes the entire file contents\n"
-	"    into the main FPGA\n"
-	"fpga store addr\n"
-	"  - read configuration data from the main FPGA (the mezz\n"
-	"    FPGA is write-only), into address `addr'. There must be\n"
-	"    enough memory available at `addr' to hold all the config\n"
-	"    data - the size of which is determined by VC:???\n"
-	"fpga info\n"
-	"  - print information about the Hymod FPGA, namely the\n"
-	"    memory addresses at which the four FPGA local bus\n"
-	"    address spaces appear in the physical address space"
-);
-/* ------------------------------------------------------------------------- */
-int
-do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	uchar data[HYMOD_EEPROM_SIZE];
-	uint addr = CONFIG_SYS_I2C_EEPROM_ADDR;
-
-	switch (argc) {
-
-	case 1:
-		addr |= HYMOD_EEOFF_MAIN;
-		break;
-
-	case 2:
-		if (strcmp (argv[1], "main") == 0) {
-			addr |= HYMOD_EEOFF_MAIN;
-			break;
-		}
-		if (strcmp (argv[1], "mezz") == 0) {
-			addr |= HYMOD_EEOFF_MEZZ;
-			break;
-		}
-		/* fall through ... */
-
-	default:
-		return cmd_usage(cmdtp);
-	}
-
-	memset (data, 0, HYMOD_EEPROM_SIZE);
-
-	eeprom_write (addr, 0, data, HYMOD_EEPROM_SIZE);
-
-	return 0;
-}
-U_BOOT_CMD(
-	eeclear,	1,	0,	do_eecl,
-	"Clear the eeprom on a Hymod board",
-	"[type]\n"
-	"  - write zeroes into the EEPROM on the board of type `type'\n"
-	"    (`type' is either `main' or `mezz' - default `main')\n"
-	"    Note: the EEPROM write enable jumper must be installed"
-);
-
-/* ------------------------------------------------------------------------- */
-
-int
-do_htest (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-#if 0
-	int rc;
-#endif
-#ifdef CONFIG_ETHER_LOOPBACK_TEST
-	extern void eth_loopback_test (void);
-#endif /* CONFIG_ETHER_LOOPBACK_TEST */
-
-	printf ("HYMOD tests - ensure loopbacks etc. are connected\n\n");
-
-#if 0
-	/* Load FPGA with test program */
-
-	printf ("Loading test FPGA program ...");
-
-	rc = fpga_load (0, test_bitfile, sizeof (test_bitfile));
-
-	switch (rc) {
-
-	case LOAD_SUCCESS:
-		printf (" SUCCEEDED\n");
-		break;
-
-	case LOAD_FAIL_NOCONF:
-		printf (" FAILED (no configuration space defined)\n");
-		return 1;
-
-	case LOAD_FAIL_NOINIT:
-		printf (" FAILED (timeout - no INIT signal seen)\n");
-		return 1;
-
-	case LOAD_FAIL_NODONE:
-		printf (" FAILED (timeout - no DONE signal seen)\n");
-		return 1;
-
-	default:
-		printf (" FAILED (unknown return code from fpga_load\n");
-		return 1;
-	}
-
-	/* run Local Bus <=> Xilinx tests */
-
-	/* tell Xilinx to run ZBT Ram, High Speed serial and Mezzanine tests */
-
-	/* run SDRAM test */
-#endif
-
-#ifdef CONFIG_ETHER_LOOPBACK_TEST
-	/* run Ethernet test */
-	eth_loopback_test ();
-#endif /* CONFIG_ETHER_LOOPBACK_TEST */
-
-	return 0;
-}
-
-#endif
diff --git a/board/hymod/config.mk b/board/hymod/config.mk
deleted file mode 100644
index 2eeea50377a..00000000000
--- a/board/hymod/config.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# HYMOD boards
-#
-
-PLATFORM_CPPFLAGS += -I$(srctree)
-
-OBJCOPYFLAGS = --remove-section=.ppcenv
diff --git a/board/hymod/eeprom.c b/board/hymod/eeprom.c
deleted file mode 100644
index ffb0df19768..00000000000
--- a/board/hymod/eeprom.c
+++ /dev/null
@@ -1,678 +0,0 @@
-/*
- * (C) Copyright 2001
- * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8260.h>
-
-/* imports from fetch.c */
-extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *));
-
-/* imports from input.c */
-extern int hymod_get_serno (const char *);
-
-/* this is relative to the root of the server's tftp directory */
-static char *def_bddb_cfgdir = "/hymod/bddb";
-
-static int
-hymod_eeprom_load (int which, hymod_eeprom_t *ep)
-{
-	unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \
-		(which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
-	unsigned offset = 0;
-	uchar data[HYMOD_EEPROM_MAXLEN], *dp, *edp;
-	hymod_eehdr_t hdr;
-	ulong len, crc;
-
-	memset (ep, 0, sizeof *ep);
-
-	eeprom_read (dev_addr, offset, (uchar *)&hdr, sizeof (hdr));
-	offset += sizeof (hdr);
-
-	if (hdr.id != HYMOD_EEPROM_ID || hdr.ver > HYMOD_EEPROM_VER ||
-	  (len = hdr.len) > HYMOD_EEPROM_MAXLEN)
-	    return (0);
-
-	eeprom_read (dev_addr, offset, data, len);
-	offset += len;
-
-	eeprom_read (dev_addr, offset, (uchar *)&crc, sizeof (ulong));
-	offset += sizeof (ulong);
-
-	if (crc32 (crc32 (0, (uchar *)&hdr, sizeof hdr), data, len) != crc)
-		return (0);
-
-	ep->ver = hdr.ver;
-	dp = data; edp = dp + len;
-
-	for (;;) {
-		ulong rtyp;
-		uchar rlen, *rdat;
-
-		rtyp = *dp++;
-		if ((rtyp & 0x80) == 0)
-			rlen = *dp++;
-		else {
-			uchar islarge = rtyp & 0x40;
-
-			rtyp = ((rtyp & 0x3f) << 8) | *dp++;
-			if (islarge) {
-				rtyp = (rtyp << 8) | *dp++;
-				rtyp = (rtyp << 8) | *dp++;
-			}
-
-			rlen = *dp++;
-			rlen = (rlen << 8) | *dp++;
-			if (islarge) {
-				rlen = (rlen << 8) | *dp++;
-				rlen = (rlen << 8) | *dp++;
-			}
-		}
-
-		if (rtyp == 0)
-			break;
-
-		rdat = dp;
-		dp += rlen;
-
-		if (dp > edp)	/* error? */
-			break;
-
-		switch (rtyp) {
-
-		case HYMOD_EEREC_SERNO:		/* serial number */
-			if (rlen == sizeof (ulong))
-				ep->serno = \
-					((ulong)rdat[0] << 24) | \
-					((ulong)rdat[1] << 16) | \
-					((ulong)rdat[2] << 8) | \
-					(ulong)rdat[3];
-			break;
-
-		case HYMOD_EEREC_DATE:		/* date */
-			if (rlen == sizeof (hymod_date_t)) {
-				ep->date.year = ((ushort)rdat[0] << 8) | \
-					(ushort)rdat[1];
-				ep->date.month = rdat[2];
-				ep->date.day = rdat[3];
-			}
-			break;
-
-		case HYMOD_EEREC_BATCH:		/* batch */
-			if (rlen <= HYMOD_MAX_BATCH)
-				memcpy (ep->batch, rdat, ep->batchlen = rlen);
-			break;
-
-		case HYMOD_EEREC_TYPE:		/* board type */
-			if (rlen == 1)
-				ep->bdtype = *rdat;
-			break;
-
-		case HYMOD_EEREC_REV:		/* board revision */
-			if (rlen == 1)
-				ep->bdrev = *rdat;
-			break;
-
-		case HYMOD_EEREC_SDRAM:		/* sdram size(s) */
-			if (rlen > 0 && rlen <= HYMOD_MAX_SDRAM) {
-				int i;
-
-				for (i = 0; i < rlen; i++)
-					ep->sdramsz[i] = rdat[i];
-				ep->nsdram = rlen;
-			}
-			break;
-
-		case HYMOD_EEREC_FLASH:		/* flash size(s) */
-			if (rlen > 0 && rlen <= HYMOD_MAX_FLASH) {
-				int i;
-
-				for (i = 0; i < rlen; i++)
-					ep->flashsz[i] = rdat[i];
-				ep->nflash = rlen;
-			}
-			break;
-
-		case HYMOD_EEREC_ZBT:		/* zbt ram size(s) */
-			if (rlen > 0 && rlen <= HYMOD_MAX_ZBT) {
-				int i;
-
-				for (i = 0; i < rlen; i++)
-					ep->zbtsz[i] = rdat[i];
-				ep->nzbt = rlen;
-			}
-			break;
-
-		case HYMOD_EEREC_XLXTYP:	/* xilinx fpga type(s) */
-			if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
-				int i;
-
-				for (i = 0; i < rlen; i++)
-					ep->xlx[i].type = rdat[i];
-				ep->nxlx = rlen;
-			}
-			break;
-
-		case HYMOD_EEREC_XLXSPD:	/* xilinx fpga speed(s) */
-			if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
-				int i;
-
-				for (i = 0; i < rlen; i++)
-					ep->xlx[i].speed = rdat[i];
-			}
-			break;
-
-		case HYMOD_EEREC_XLXTMP:	/* xilinx fpga temperature(s) */
-			if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
-				int i;
-
-				for (i = 0; i < rlen; i++)
-					ep->xlx[i].temp = rdat[i];
-			}
-			break;
-
-		case HYMOD_EEREC_XLXGRD:	/* xilinx fpga grade(s) */
-			if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
-				int i;
-
-				for (i = 0; i < rlen; i++)
-					ep->xlx[i].grade = rdat[i];
-			}
-			break;
-
-		case HYMOD_EEREC_CPUTYP:	/* CPU type */
-			if (rlen == 1)
-				ep->mpc.type = *rdat;
-			break;
-
-		case HYMOD_EEREC_CPUSPD:	/* CPU speed */
-			if (rlen == 1)
-				ep->mpc.cpuspd = *rdat;
-			break;
-
-		case HYMOD_EEREC_CPMSPD:	/* CPM speed */
-			if (rlen == 1)
-				ep->mpc.cpmspd = *rdat;
-			break;
-
-		case HYMOD_EEREC_BUSSPD:	/* bus speed */
-			if (rlen == 1)
-				ep->mpc.busspd = *rdat;
-			break;
-
-		case HYMOD_EEREC_HSTYPE:	/* hs-serial chip type */
-			if (rlen == 1)
-				ep->hss.type = *rdat;
-			break;
-
-		case HYMOD_EEREC_HSCHIN:	/* num hs-serial input chans */
-			if (rlen == 1)
-				ep->hss.nchin = *rdat;
-			break;
-
-		case HYMOD_EEREC_HSCHOUT:	/* num hs-serial output chans */
-			if (rlen == 1)
-				ep->hss.nchout = *rdat;
-			break;
-
-		default:	/* ignore */
-			break;
-		}
-	}
-
-	return (1);
-}
-
-/* maps an ascii "name=value" into a binary eeprom data record */
-typedef
-	struct _eerec_map {
-		char *name;
-		uint type;
-		uchar *(*handler) \
-			(struct _eerec_map *, uchar *, uchar *, uchar *);
-		uint length;
-		uint maxlen;
-	}
-eerec_map_t;
-
-static uchar *
-uint_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
-{
-	char *eval;
-	ulong lval;
-
-	lval = simple_strtol ((char *)val, &eval, 10);
-
-	if ((uchar *)eval == val || *eval != '\0') {
-		printf ("%s rec (%s) is not a valid uint\n", rp->name, val);
-		return (NULL);
-	}
-
-	if (dp + 2 + rp->length > edp) {
-		printf ("can't fit %s rec into eeprom\n", rp->name);
-		return (NULL);
-	}
-
-	*dp++ = rp->type;
-	*dp++ = rp->length;
-
-	switch (rp->length) {
-
-	case 1:
-		if (lval >= 256) {
-			printf ("%s rec value (%lu) out of range (0-255)\n",
-				rp->name, lval);
-			return (NULL);
-		}
-		*dp++ = lval;
-		break;
-
-	case 2:
-		if (lval >= 65536) {
-			printf ("%s rec value (%lu) out of range (0-65535)\n",
-				rp->name, lval);
-			return (NULL);
-		}
-		*dp++ = lval >> 8;
-		*dp++ = lval;
-		break;
-
-	case 4:
-		*dp++ = lval >> 24;
-		*dp++ = lval >> 16;
-		*dp++ = lval >> 8;
-		*dp++ = lval;
-		break;
-
-	default:
-		printf ("huh? rp->length not 1, 2 or 4! (%d)\n", rp->length);
-		return (NULL);
-	}
-
-	return (dp);
-}
-
-static uchar *
-date_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
-{
-	hymod_date_t date;
-	char *p = (char *)val;
-	char *ep;
-	ulong lval;
-
-	lval = simple_strtol (p, &ep, 10);
-	if (ep == p || *ep++ != '-') {
-bad_date:
-		printf ("%s rec (%s) is not a valid date\n", rp->name, val);
-		return (NULL);
-	}
-	if (lval >= 65536)
-		goto bad_date;
-	date.year = lval;
-
-	lval = simple_strtol (p = ep, &ep, 10);
-	if (ep == p || *ep++ != '-' || lval == 0 || lval > 12)
-		goto bad_date;
-	date.month = lval;
-
-	lval = simple_strtol (p = ep, &ep, 10);
-	if (ep == p || *ep != '\0' || lval == 0 || lval > 31)
-		goto bad_date;
-	date.day = lval;
-
-	if (dp + 2 + rp->length > edp) {
-		printf ("can't fit %s rec into eeprom\n", rp->name);
-		return (NULL);
-	}
-
-	*dp++ = rp->type;
-	*dp++ = rp->length;
-	*dp++ = date.year >> 8;
-	*dp++ = date.year;
-	*dp++ = date.month;
-	*dp++ = date.day;
-
-	return (dp);
-}
-
-static uchar *
-string_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
-{
-	uint len;
-
-	if ((len = strlen ((char *)val)) > rp->maxlen) {
-		printf ("%s rec (%s) string is too long (%d>%d)\n",
-			rp->name, val, len, rp->maxlen);
-		return (NULL);
-	}
-
-	if (dp + 2 + len > edp) {
-		printf ("can't fit %s rec into eeprom\n", rp->name);
-		return (NULL);
-	}
-
-	*dp++ = rp->type;
-	*dp++ = len;
-	memcpy (dp, val, len);
-	dp += len;
-
-	return (dp);
-}
-
-static uchar *
-bytes_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
-{
-	uchar bytes[HYMOD_MAX_BYTES], nbytes, *p;
-	char *ep;
-
-	for (nbytes = 0, p = val; *p != '\0'; p = (uchar *)ep) {
-		ulong lval;
-
-		lval = simple_strtol ((char *)p, &ep, 10);
-		if ((uchar *)ep == p || (*ep != '\0' && *ep != ',') || \
-		    lval >= 256) {
-			printf ("%s rec (%s) byte array has invalid uint\n",
-				rp->name, val);
-			return (NULL);
-		}
-		if (nbytes >= HYMOD_MAX_BYTES) {
-			printf ("%s rec (%s) byte array too long\n",
-				rp->name, val);
-			return (NULL);
-		}
-		bytes[nbytes++] = lval;
-
-		if (*ep != '\0')
-			ep++;
-	}
-
-	if (dp + 2 + nbytes > edp) {
-		printf ("can't fit %s rec into eeprom\n", rp->name);
-		return (NULL);
-	}
-
-	*dp++ = rp->type;
-	*dp++ = nbytes;
-	memcpy (dp, bytes, nbytes);
-	dp += nbytes;
-
-	return (dp);
-}
-
-static eerec_map_t eerec_map[] = {
-	/* name      type                 handler         len max             */
-	{ "serno",   HYMOD_EEREC_SERNO,   uint_handler,   4,  0               },
-	{ "date",    HYMOD_EEREC_DATE,    date_handler,   4,  0               },
-	{ "batch",   HYMOD_EEREC_BATCH,   string_handler, 0,  HYMOD_MAX_BATCH },
-	{ "type",    HYMOD_EEREC_TYPE,    uint_handler,   1,  0               },
-	{ "rev",     HYMOD_EEREC_REV,     uint_handler,   1,  0               },
-	{ "sdram",   HYMOD_EEREC_SDRAM,   bytes_handler,  0,  HYMOD_MAX_SDRAM },
-	{ "flash",   HYMOD_EEREC_FLASH,   bytes_handler,  0,  HYMOD_MAX_FLASH },
-	{ "zbt",     HYMOD_EEREC_ZBT,     bytes_handler,  0,  HYMOD_MAX_ZBT   },
-	{ "xlxtyp",  HYMOD_EEREC_XLXTYP,  bytes_handler,  0,  HYMOD_MAX_XLX   },
-	{ "xlxspd",  HYMOD_EEREC_XLXSPD,  bytes_handler,  0,  HYMOD_MAX_XLX   },
-	{ "xlxtmp",  HYMOD_EEREC_XLXTMP,  bytes_handler,  0,  HYMOD_MAX_XLX   },
-	{ "xlxgrd",  HYMOD_EEREC_XLXGRD,  bytes_handler,  0,  HYMOD_MAX_XLX   },
-	{ "cputyp",  HYMOD_EEREC_CPUTYP,  uint_handler,   1,  0               },
-	{ "cpuspd",  HYMOD_EEREC_CPUSPD,  uint_handler,   1,  0               },
-	{ "cpmspd",  HYMOD_EEREC_CPMSPD,  uint_handler,   1,  0               },
-	{ "busspd",  HYMOD_EEREC_BUSSPD,  uint_handler,   1,  0               },
-	{ "hstype",  HYMOD_EEREC_HSTYPE,  uint_handler,   1,  0               },
-	{ "hschin",  HYMOD_EEREC_HSCHIN,  uint_handler,   1,  0               },
-	{ "hschout", HYMOD_EEREC_HSCHOUT, uint_handler,   1,  0               },
-};
-
-static int neerecs = sizeof eerec_map / sizeof eerec_map[0];
-
-static uchar data[HYMOD_EEPROM_SIZE], *sdp, *dp, *edp;
-
-static int
-eerec_callback (uchar *name, uchar *val)
-{
-	eerec_map_t *rp;
-
-	for (rp = eerec_map; rp < &eerec_map[neerecs]; rp++)
-		if (strcmp ((char *)name, rp->name) == 0)
-			break;
-
-	if (rp >= &eerec_map[neerecs])
-		return (0);
-
-	if ((dp = (*rp->handler) (rp, val, dp, edp)) == NULL)
-		return (0);
-
-	return (1);
-}
-
-static int
-hymod_eeprom_fetch(int which, char *filename, ulong addr)
-{
-	unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \
-		(which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
-	hymod_eehdr_t *hp = (hymod_eehdr_t *)&data[0];
-	ulong crc;
-
-	memset (hp, 0, sizeof *hp);
-	hp->id = HYMOD_EEPROM_ID;
-	hp->ver = HYMOD_EEPROM_VER;
-
-	dp = sdp = (uchar *)(hp + 1);
-	edp = dp + HYMOD_EEPROM_MAXLEN;
-
-	if (fetch_and_parse (filename, addr, eerec_callback) == 0)
-		return (0);
-
-	hp->len = dp - sdp;
-
-	crc = crc32 (0, data, dp - data);
-	memcpy (dp, &crc, sizeof (ulong));
-	dp += sizeof (ulong);
-
-	eeprom_write (dev_addr, 0, data, dp - data);
-
-	return (1);
-}
-
-static char *type_vals[] = {
-	"NONE", "IO", "CLP", "DSP", "INPUT", "ALT-INPUT", "DISPLAY"
-};
-
-static char *xlxtyp_vals[] = {
-	"NONE", "XCV300E", "XCV400E", "XCV600E"
-};
-
-static char *xlxspd_vals[] = {
-	"NONE", "6", "7", "8"
-};
-
-static char *xlxtmp_vals[] = {
-	"NONE", "COM", "IND"
-};
-
-static char *xlxgrd_vals[] = {
-	"NONE", "NORMAL", "ENGSAMP"
-};
-
-static char *cputyp_vals[] = {
-	"NONE", "MPC8260"
-};
-
-static char *clk_vals[] = {
-	"NONE", "33", "66", "100", "133", "166", "200"
-};
-
-static char *hstype_vals[] = {
-	"NONE", "AMCC-S2064A"
-};
-
-static void
-print_mem (char *l, char *s, uchar n, uchar a[])
-{
-	if (n > 0) {
-		if (n == 1)
-			printf ("%s%dMB %s", s, 1 << (a[0] - 20), l);
-		else {
-			ulong t = 0;
-			int i;
-
-			for (i = 0; i < n; i++)
-				t += 1 << (a[i] - 20);
-
-			printf ("%s%luMB %s (%d banks:", s, t, l, n);
-
-			for (i = 0; i < n; i++)
-				printf ("%dMB%s",
-					1 << (a[i] - 20),
-					(i == n - 1) ? ")" : ",");
-		}
-	}
-	else
-		printf ("%sNO %s", s, l);
-}
-
-void
-hymod_eeprom_print (hymod_eeprom_t *ep)
-{
-	int i;
-
-	printf ("         Hymod %s board, rev %03d\n",
-		type_vals[ep->bdtype], ep->bdrev);
-
-	printf ("         serial #: %010lu, date %04d-%02d-%02d",
-		ep->serno, ep->date.year, ep->date.month, ep->date.day);
-	if (ep->batchlen > 0)
-		printf (", batch \"%.*s\"", ep->batchlen, ep->batch);
-	puts ("\n");
-
-	switch (ep->bdtype) {
-
-	case HYMOD_BDTYPE_IO:
-	case HYMOD_BDTYPE_CLP:
-	case HYMOD_BDTYPE_DSP:
-		printf ("         Motorola %s CPU, speeds: %s/%s/%s",
-		    cputyp_vals[ep->mpc.type], clk_vals[ep->mpc.cpuspd],
-		    clk_vals[ep->mpc.cpmspd], clk_vals[ep->mpc.busspd]);
-
-		print_mem ("SDRAM", ", ", ep->nsdram, ep->sdramsz);
-
-		print_mem ("FLASH", ", ", ep->nflash, ep->flashsz);
-
-		puts ("\n");
-
-		print_mem ("ZBT", "         ", ep->nzbt, ep->zbtsz);
-
-		if (ep->nxlx > 0) {
-			hymod_xlx_t *xp;
-
-			if (ep->nxlx == 1) {
-				xp = &ep->xlx[0];
-				printf (", Xilinx %s FPGA (%s/%s/%s)",
-					xlxtyp_vals[xp->type],
-					xlxspd_vals[xp->speed],
-					xlxtmp_vals[xp->temp],
-					xlxgrd_vals[xp->grade]);
-			}
-			else {
-				printf (", %d Xilinx FPGAs (", ep->nxlx);
-				for (i = 0; i < ep->nxlx; i++) {
-					xp = &ep->xlx[i];
-					printf ("%s[%s/%s/%s]%s",
-					    xlxtyp_vals[xp->type],
-					    xlxspd_vals[xp->speed],
-					    xlxtmp_vals[xp->temp],
-					    xlxgrd_vals[xp->grade],
-					    (i == ep->nxlx - 1) ? ")" : ", ");
-				}
-			}
-		}
-		else
-			puts(", NO FPGAs");
-
-		puts ("\n");
-
-		if (ep->hss.type > 0)
-			printf ("         High Speed Serial: "
-				"%s, %d input%s, %d output%s\n",
-				hstype_vals[ep->hss.type],
-				ep->hss.nchin,
-				(ep->hss.nchin == 1 ? "" : "s"),
-				ep->hss.nchout,
-				(ep->hss.nchout == 1 ? "" : "s"));
-		break;
-
-	case HYMOD_BDTYPE_INPUT:
-	case HYMOD_BDTYPE_ALTINPUT:
-	case HYMOD_BDTYPE_DISPLAY:
-		break;
-
-	default:
-		/* crap! */
-		printf ("         UNKNOWN BOARD TYPE: %d\n", ep->bdtype);
-		break;
-	}
-}
-
-int
-hymod_eeprom_read (int which, hymod_eeprom_t *ep)
-{
-	char *label = which ? "mezzanine" : "main";
-	unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \
-		(which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
-	char filename[50], prompt[50], *dir;
-	int serno, count = 0, rc;
-
-	rc = eeprom_probe (dev_addr, 0);
-
-	if (rc > 0) {
-		printf ("*** probe for eeprom failed with code %d\n", rc);
-		return (0);
-	}
-
-	if (rc < 0)
-		return (rc);
-
-	sprintf (prompt, "Enter %s board serial number: ", label);
-
-	if ((dir = getenv ("bddb_cfgdir")) == NULL)
-		dir = def_bddb_cfgdir;
-
-	for (;;) {
-		int rc;
-
-		if (hymod_eeprom_load (which, ep))
-			return (1);
-
-		printf ("*** %s board EEPROM contents are %sinvalid\n",
-			label, count == 0 ? "" : "STILL ");
-
-		puts ("*** will fetch from server (Ctrl-C to abort)\n");
-
-		serno = hymod_get_serno (prompt);
-
-		if (serno < 0) {
-			if (serno == -1)
-				puts ("\n*** interrupted!");
-			else
-				puts ("\n*** timeout!");
-			puts (" - ignoring eeprom contents\n");
-			return (0);
-		}
-
-		sprintf (filename, "%s/%010d.cfg", dir, serno);
-
-		printf ("*** fetching %s board EEPROM contents from server\n",
-			label);
-
-		rc = hymod_eeprom_fetch (which, filename, CONFIG_SYS_LOAD_ADDR);
-
-		if (rc == 0) {
-			puts ("*** fetch failed - ignoring eeprom contents\n");
-			return (0);
-		}
-
-		count++;
-	}
-}
diff --git a/board/hymod/env.c b/board/hymod/env.c
deleted file mode 100644
index 66c5115b217..00000000000
--- a/board/hymod/env.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * (C) Copyright 2003
- * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/ctype.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* imports from fetch.c */
-extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *));
-
-/* this is relative to the root of the server's tftp directory */
-static char *def_global_env_path = "/hymod/global_env";
-
-static int
-env_callback (uchar *name, uchar *value)
-{
-	hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
-	char ov[CONFIG_SYS_CBSIZE], nv[CONFIG_SYS_CBSIZE], *p, *q, *nn, c, *curver, *newver;
-	int override = 1, append = 0, remove = 0, nnl, ovl, nvl;
-
-	nn = (char *)name;
-
-	if (*nn == '-') {
-		override = 0;
-		nn++;
-	}
-
-	while (isblank(*nn))
-		nn++;
-
-	if ((nnl = strlen (nn)) == 0) {
-		printf ("Empty name in global env file\n");
-		return (0);
-	}
-
-	if ((c = nn[nnl - 1]) == '+' || c == '-') {
-		if (c == '+')
-			append = 1;
-		else
-			remove = 1;
-		nn[--nnl] = '\0';
-	}
-
-	while (nnl > 0 && isblank(nn[nnl - 1]))
-		nn[--nnl] = '\0';
-	if (nnl == 0) {
-		printf ("Empty name in global env file\n");
-		return (0);
-	}
-
-	p = (char *)value;
-	q = nv;
-
-	while (isblank(*p))
-		p++;
-
-	nvl = strlen (p);
-	while (nvl > 0 && isblank(p[nvl - 1]))
-		p[--nvl] = '\0';
-
-	while ((*q = *p++) != '\0') {
-		if (*q == '%') {
-			switch (*p++) {
-
-			case '\0':	/* whoops - back up */
-				p--;
-				break;
-
-			case '%':	/* a single percent character */
-				q++;
-				break;
-
-			case 's':	/* main board serial number as string */
-				q += sprintf (q, "%010lu",
-					cp->main.eeprom.serno);
-				break;
-
-			case 'S':	/* main board serial number as number */
-				q += sprintf (q, "%lu", cp->main.eeprom.serno);
-				break;
-
-			default:	/* ignore any others */
-				break;
-			}
-		}
-		else
-			q++;
-	}
-
-	if ((nvl = q - nv) == 0) {
-		setenv (nn, NULL);
-		return (1);
-	}
-
-	if ((curver = getenv ("global_env_version")) == NULL)
-		curver = "unknown";
-
-	if ((newver = getenv ("new_genv_version")) == NULL || \
-	    strcmp (curver, newver) == 0) {
-		if (strcmp (nn, "version") == 0)
-			setenv ("new_genv_version", nv);
-		return (1);
-	}
-
-	if ((p = getenv (nn)) != NULL) {
-
-		strcpy (ov, p);
-		ovl = strlen (ov);
-
-		if (append) {
-
-			if (strstr (ov, nv) == NULL) {
-
-				printf ("Appending '%s' to env var '%s'\n",
-					nv, nn);
-
-				while (nvl >= 0) {
-					nv[ovl + 1 + nvl] = nv[nvl];
-					nvl--;
-				}
-
-				nv[ovl] = ' ';
-
-				while (--ovl >= 0)
-					nv[ovl] = ov[ovl];
-
-				setenv (nn, nv);
-			}
-
-			return (1);
-		}
-
-		if (remove) {
-
-			if (strstr (ov, nv) != NULL) {
-
-				printf ("Removing '%s' from env var '%s'\n",
-					nv, nn);
-
-				while ((p = strstr (ov, nv)) != NULL) {
-					q = p + nvl;
-					if (*q == ' ')
-						q++;
-					strcpy(p, q);
-				}
-
-				setenv (nn, ov);
-			}
-
-			return (1);
-		}
-
-		if (!override || strcmp (ov, nv) == 0)
-			return (1);
-
-		printf ("Re-setting env cmd '%s' from '%s' to '%s'\n",
-			nn, ov, nv);
-	}
-	else
-		printf ("Setting env cmd '%s' to '%s'\n", nn, nv);
-
-	setenv (nn, nv);
-	return (1);
-}
-
-void
-hymod_check_env (void)
-{
-	char *p, *path, *curver, *newver;
-	int firsttime = 0, needsave = 0;
-
-	if (getenv ("global_env_loaded") == NULL) {
-		puts ("*** global environment has never been loaded\n");
-		puts ("*** fetching from server");
-		firsttime = 1;
-	}
-	else if ((p = getenv ("always_check_env")) != NULL &&
-	    strcmp (p, "yes") == 0)
-		puts ("*** checking for updated global environment");
-	else
-		return;
-
-	puts (" (Control-C to Abort)\n");
-
-	if ((path = getenv ("global_env_path")) == NULL || *path == '\0')
-		path = def_global_env_path;
-
-	if (fetch_and_parse (path, CONFIG_SYS_LOAD_ADDR, env_callback) == 0) {
-		puts ("*** Fetch of global environment failed!\n");
-		return;
-	}
-
-	if ((newver = getenv ("new_genv_version")) == NULL) {
-		puts ("*** Version number not set - contents ignored!\n");
-		return;
-	}
-
-	if ((curver = getenv ("global_env_version")) == NULL || \
-	    strcmp (curver, newver) != 0) {
-		setenv ("global_env_version", newver);
-		needsave = 1;
-	}
-	else
-		printf ("*** Global environment up-to-date (ver %s)\n", curver);
-
-	setenv ("new_genv_version", NULL);
-
-	if (firsttime) {
-		setenv ("global_env_loaded", "yes");
-		needsave = 1;
-	}
-
-	if (needsave)
-		puts ("\n*** Remember to run the 'saveenv' "
-			"command to save the changes\n\n");
-}
diff --git a/board/hymod/fetch.c b/board/hymod/fetch.c
deleted file mode 100644
index da9373ffb0f..00000000000
--- a/board/hymod/fetch.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * (C) Copyright 2001
- * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-
-/* imports from input.c */
-extern int hymod_get_ethaddr (void);
-
-int
-fetch_and_parse (char *fn, ulong addr, int (*cback)(uchar *, uchar *))
-{
-	char *ethaddr;
-	uchar *fp, *efp;
-	int rc, count = 0;
-
-	while ((ethaddr = getenv ("ethaddr")) == NULL || *ethaddr == '\0') {
-
-		printf ("*** Ethernet address is%s not set\n",
-			count == 0 ? "" : " STILL");
-
-		if ((rc = hymod_get_ethaddr ()) < 0) {
-			if (rc == -1)
-				puts ("\n*** interrupted!");
-			else
-				puts ("\n*** timeout!");
-			printf (" - fetch of '%s' aborted\n", fn);
-			return (0);
-		}
-
-		count++;
-	}
-
-	copy_filename (BootFile, fn, sizeof (BootFile));
-	load_addr = addr;
-	NetBootFileXferSize = 0;
-
-	if (NetLoop(TFTPGET) == 0) {
-		printf ("tftp transfer of file '%s' failed\n", fn);
-		return (0);
-	}
-
-	if (NetBootFileXferSize == 0) {
-		printf ("can't determine size of file '%s'\n", fn);
-		return (0);
-	}
-
-	fp = (uchar *)load_addr;
-	efp = fp + NetBootFileXferSize;
-
-	do {
-		uchar *name, *value;
-
-		if (*fp == '#' || *fp == '\n') {
-			/* skip this line */
-			while (fp < efp && *fp++ != '\n')
-				;
-			continue;
-		}
-
-		name = fp;
-
-		while (fp < efp && *fp != '=' && *fp != '\n')
-			fp++;
-		if (fp >= efp)
-			break;
-		if (*fp == '\n') {
-			fp++;
-			continue;
-		}
-		*fp++ = '\0';
-
-		value = fp;
-
-		while (fp < efp && *fp != '\n')
-			fp++;
-		if (fp[-1] == '\r')
-			fp[-1] = '\0';
-		*fp++ = '\0';	/* ok if we go off the end here */
-
-		if ((*cback)(name, value) == 0)
-			return (0);
-
-	} while (fp < efp);
-
-	return (1);
-}
diff --git a/board/hymod/flash.c b/board/hymod/flash.c
deleted file mode 100644
index 02e519c695e..00000000000
--- a/board/hymod/flash.c
+++ /dev/null
@@ -1,490 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00
- */
-
-#include <common.h>
-#include <mpc8260.h>
-#include <board/hymod/flash.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Protection Flags:
- */
-#define FLAG_PROTECT_SET	0x01
-#define FLAG_PROTECT_CLEAR	0x02
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * probe for flash bank at address "base" and store info about it
- * in the flash_info entry "fip". Fatal error if nothing there.
- */
-static void
-bank_probe (flash_info_t *fip, volatile bank_addr_t base)
-{
-	volatile bank_addr_t addr;
-	bank_word_t word;
-	int i;
-
-	/* reset the flash */
-	*base = BANK_CMD_RST;
-
-	/* put flash into read id mode */
-	*base = BANK_CMD_RD_ID;
-
-	/* check the manufacturer id - must be intel */
-	word = *BANK_REG_MAN_CODE (base);
-	if (word != BANK_FILL_WORD (INTEL_MANUFACT&0xff))
-		panic ("\nbad manufacturer's code (0x%08lx) at addr 0x%08lx",
-			(unsigned long)word, (unsigned long)base);
-
-	/* check the device id */
-	word = *BANK_REG_DEV_CODE (base);
-	switch (word) {
-
-	case BANK_FILL_WORD (INTEL_ID_28F320J5&0xff):
-		fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J5;
-		fip->sector_count = 32;
-		break;
-
-	case BANK_FILL_WORD (INTEL_ID_28F640J5&0xff):
-		fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J5;
-		fip->sector_count = 64;
-		break;
-
-	case BANK_FILL_WORD (INTEL_ID_28F320J3A&0xff):
-		fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J3A;
-		fip->sector_count = 32;
-		break;
-
-	case BANK_FILL_WORD (INTEL_ID_28F640J3A&0xff):
-		fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J3A;
-		fip->sector_count = 64;
-		break;
-
-	case BANK_FILL_WORD (INTEL_ID_28F128J3A&0xff):
-		fip->flash_id = FLASH_MAN_INTEL | FLASH_28F128J3A;
-		fip->sector_count = 128;
-		break;
-
-	default:
-		panic ("\nbad device code (0x%08lx) at addr 0x%08lx",
-			(unsigned long)word, (unsigned long)base);
-	}
-
-	if (fip->sector_count >= CONFIG_SYS_MAX_FLASH_SECT)
-		panic ("\ntoo many sectors (%d) in flash at address 0x%08lx",
-			fip->sector_count, (unsigned long)base);
-
-	addr = base;
-	for (i = 0; i < fip->sector_count; i++) {
-		fip->start[i] = (unsigned long)addr;
-		fip->protect[i] = 0;
-		addr = BANK_ADDR_NEXT_BLK (addr);
-	}
-
-	fip->size = (bank_size_t)addr - (bank_size_t)base;
-
-	/* reset the flash */
-	*base = BANK_CMD_RST;
-}
-
-static void
-bank_reset (flash_info_t *info, int sect)
-{
-	volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
-
-#ifdef FLASH_DEBUG
-	printf ("writing reset cmd to addr 0x%08lx\n", (unsigned long)addr);
-#endif
-
-	*addr = BANK_CMD_RST;
-}
-
-static void
-bank_erase_init (flash_info_t *info, int sect)
-{
-	volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
-	int flag;
-
-#ifdef FLASH_DEBUG
-	printf ("erasing sector %d, addr = 0x%08lx\n",
-		sect, (unsigned long)addr);
-#endif
-
-	/* Disable intrs which might cause a timeout here */
-	flag = disable_interrupts ();
-
-#ifdef FLASH_DEBUG
-	printf ("writing erase cmd to addr 0x%08lx\n", (unsigned long)addr);
-#endif
-	*addr = BANK_CMD_ERASE1;
-	*addr = BANK_CMD_ERASE2;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-}
-
-static int
-bank_erase_poll (flash_info_t *info, int sect)
-{
-	volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
-	bank_word_t stat = *addr;
-
-#ifdef FLASH_DEBUG
-	printf ("checking status at addr 0x%08lx [0x%08lx]\n",
-		(unsigned long)addr, (unsigned long)stat);
-#endif
-
-	if ((stat & BANK_STAT_RDY) == BANK_STAT_RDY) {
-		if ((stat & BANK_STAT_ERR) != 0) {
-			printf ("failed on sector %d [0x%08lx] at "
-				"address 0x%08lx\n", sect,
-				(unsigned long)stat, (unsigned long)addr);
-			*addr = BANK_CMD_CLR_STAT;
-			return (-1);
-		}
-		else
-			return (1);
-	}
-	else
-		return (0);
-}
-
-static int
-bank_write_word (volatile bank_addr_t addr, bank_word_t value)
-{
-	bank_word_t stat;
-	ulong start;
-	int flag, retval;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	*addr = BANK_CMD_PROG;
-
-	*addr = value;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	retval = 0;
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	do {
-		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			retval = 1;
-			goto done;
-		}
-		stat = *addr;
-	} while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
-
-	if ((stat & BANK_STAT_ERR) != 0) {
-		printf ("flash program failed [0x%08lx] at address 0x%08lx\n",
-			(unsigned long)stat, (unsigned long)addr);
-		*addr = BANK_CMD_CLR_STAT;
-		retval = 3;
-	}
-
-done:
-	/* reset to read mode */
-	*addr = BANK_CMD_RST;
-
-	return (retval);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long
-flash_init (void)
-{
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	bank_probe (&flash_info[0], (bank_addr_t)CONFIG_SYS_FLASH_BASE);
-
-	/*
-	 * protect monitor and environment sectors
-	 */
-
-#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
-	(void)flash_protect (FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      &flash_info[0]);
-#endif
-
-#if defined(CONFIG_SYS_FLASH_ENV_ADDR)
-	(void)flash_protect (FLAG_PROTECT_SET,
-		      CONFIG_SYS_FLASH_ENV_ADDR,
-#if defined(CONFIG_SYS_FLASH_ENV_BUF)
-		      CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_BUF - 1,
-#else
-		      CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_SIZE - 1,
-#endif
-		      &flash_info[0]);
-#endif
-
-	return flash_info[0].size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void
-flash_print_info (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F320J5:	printf ("28F320J5 (32 Mbit, 2 x 16bit)\n");
-				break;
-	case FLASH_28F640J5:	printf ("28F640J5 (64 Mbit, 2 x 16bit)\n");
-				break;
-	case FLASH_28F320J3A:	printf ("28F320J3A (32 Mbit, 2 x 16bit)\n");
-				break;
-	case FLASH_28F640J3A:	printf ("28F640J3A (64 Mbit, 2 x 16bit)\n");
-				break;
-	case FLASH_28F128J3A:	printf ("28F320J3A (128 Mbit, 2 x 16bit)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-	return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-/*-----------------------------------------------------------------------
- */
-
-int
-flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	int prot, sect, haderr;
-	ulong start, now, last;
-	int rcode = 0;
-
-#ifdef FLASH_DEBUG
-	printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
-		"  Bank # %d: ", s_last - s_first + 1, s_first, s_last,
-		(info - flash_info) + 1);
-	flash_print_info (info);
-#endif
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sector%s will not be erased\n",
-			prot, (prot > 1 ? "s" : ""));
-	}
-
-	start = get_timer (0);
-	last = 0;
-	haderr = 0;
-
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			ulong estart;
-			int sectdone;
-
-			bank_erase_init (info, sect);
-
-			/* wait at least 80us - let's wait 1 ms */
-			udelay (1000);
-
-			estart = get_timer (start);
-
-			do {
-				now = get_timer (start);
-
-				if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
-					printf ("Timeout (sect %d)\n", sect);
-					haderr = 1;
-					rcode = 1;
-					break;
-				}
-
-#ifndef FLASH_DEBUG
-				/* show that we're waiting */
-				if ((now - last) > 1000) { /* every second */
-					putc ('.');
-					last = now;
-				}
-#endif
-
-				sectdone = bank_erase_poll (info, sect);
-
-				if (sectdone < 0) {
-					haderr = 1;
-					rcode = 1;
-					break;
-				}
-
-			} while (!sectdone);
-
-			if (haderr)
-				break;
-		}
-	}
-
-	if (haderr > 0)
-		printf (" failed\n");
-	else
-		printf (" done\n");
-
-	/* reset to read mode */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			bank_reset (info, sect);
-		}
-	}
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 3 - Program failed
- */
-static int
-write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	/* Check if Flash is (sufficiently) erased */
-	if ((*(ulong *)dest & data) != data)
-		return (2);
-
-	return (bank_write_word ((bank_addr_t)dest, (bank_word_t)data));
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 3 - Program failed
- */
-
-int
-write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_word (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/hymod/flash.h b/board/hymod/flash.h
deleted file mode 100644
index 6ea282341f8..00000000000
--- a/board/hymod/flash.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
-
-/* Commands */
-#define ISF_CMD_RST		0xFF		/* reset flash */
-#define ISF_CMD_RD_ID		0x90		/* read the id and lock bits */
-#define ISF_CMD_RD_QUERY	0x98		/* read device capabilities */
-#define ISF_CMD_RD_STAT		0x70		/* read the status register */
-#define ISF_CMD_CLR_STAT	0x50		/* clear the staus register */
-#define ISF_CMD_WR_BUF		0xE8		/* clear the staus register */
-#define ISF_CMD_PROG		0x40		/* program word command */
-#define ISF_CMD_ERASE1		0x20		/* 1st word for block erase */
-#define ISF_CMD_ERASE2		0xD0		/* 2nd word for block erase */
-#define ISF_CMD_ERASE_SUSP	0xB0		/* suspend block erase */
-#define ISF_CMD_LOCK		0x60		/* 1st word for all lock cmds */
-#define ISF_CMD_SET_LOCK_BLK	0x01		/* 2nd wrd set block lock bit */
-#define ISF_CMD_SET_LOCK_MSTR	0xF1		/* 2nd wrd set master lck bit */
-#define ISF_CMD_CLR_LOCK_BLK	0xD0		/* 2nd wrd clear blk lck bit */
-
-/* status register bits */
-#define ISF_STAT_DPS		0x02		/* Device Protect Status */
-#define ISF_STAT_VPPS		0x08		/* VPP Status */
-#define ISF_STAT_PSLBS		0x10		/* Program+Set Lock Bit Stat */
-#define ISF_STAT_ECLBS		0x20		/* Erase+Clr Lock Bit Stat */
-#define ISF_STAT_ESS		0x40		/* Erase Suspend Status */
-#define ISF_STAT_RDY		0x80		/* WSM Mach Status, 1=rdy */
-
-#define ISF_STAT_ERR		(ISF_STAT_VPPS | ISF_STAT_DPS | \
-				    ISF_STAT_ECLBS | ISF_STAT_PSLBS)
-
-/* register addresses, valid only following an ISF_CMD_RD_ID command */
-#define ISF_REG_MAN_CODE	0x00		/* manufacturer code */
-#define ISF_REG_DEV_CODE	0x01		/* device code */
-#define ISF_REG_BLK_LCK		0x02		/* block lock configuration */
-#define ISF_REG_MST_LCK		0x03		/* master lock configuration */
-
-/********************** DEFINES for Hymod Flash ******************************/
-
-/*
- * this code requires that the flash on any Hymod board appear as a bank
- * of two (identical) 16bit Intel StrataFlash chips with 64Kword erase
- * sectors (or blocks), running in x16 bit mode and connected side-by-side
- * to make a 32-bit wide bus.
- */
-
-typedef unsigned long bank_word_t;
-typedef bank_word_t bank_blk_t[64 * 1024];
-
-#define BANK_FILL_WORD(b)	(((bank_word_t)(b) << 16) | (bank_word_t)(b))
-
-#ifdef EXAMPLE
-
-/* theoretically the following examples should also work */
-
-/* one flash chip in x8 mode with 128Kword sectors and 8bit bus */
-typedef unsigned char bank_word_t;
-typedef bank_word_t bank_blk_t[128 * 1024];
-#define BANK_FILL_WORD(b)	((bank_word_t)(b))
-
-/* four flash chips in x16 mode with 32Kword sectors and 64bit bus */
-typedef unsigned long long bank_word_t;
-typedef bank_word_t bank_blk_t[32 * 1024];
-#define BANK_FILL_WORD(b)	( \
-				    ((bank_word_t)(b) << 48) \
-				    ((bank_word_t)(b) << 32) \
-				    ((bank_word_t)(b) << 16) \
-				    ((bank_word_t)(b) <<  0) \
-				)
-
-#endif /* EXAMPLE */
-
-/* the sizes of these two types should probably be the same */
-typedef bank_word_t *bank_addr_t;
-typedef unsigned long bank_size_t;
-
-/* align bank addresses and sizes to bank word boundaries */
-#define BANK_ADDR_WORD_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
-				    & ~(sizeof (bank_word_t) - 1)))
-#define BANK_SIZE_WORD_ALIGN(s)	(((bank_size_t)(s) + sizeof (bank_word_t) - 1) \
-				    & ~(sizeof (bank_word_t) - 1))
-
-/* align bank addresses and sizes to bank block boundaries */
-#define BANK_ADDR_BLK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
-				    & ~(sizeof (bank_blk_t) - 1)))
-#define BANK_SIZE_BLK_ALIGN(s)	(((bank_size_t)(s) + sizeof (bank_blk_t) - 1) \
-				    & ~(sizeof (bank_blk_t) - 1))
-
-/* add an offset to a bank address */
-#define BANK_ADDR_OFFSET(a, o)	((bank_addr_t)((bank_size_t)(a) + \
-				    (bank_size_t)(o)))
-
-/* adjust a bank address to start of next word, block or bank */
-#define BANK_ADDR_NEXT_WORD(a)	BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
-				    sizeof (bank_word_t))
-#define BANK_ADDR_NEXT_BLK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
-				    sizeof (bank_blk_t))
-
-/* get bank address of register r given a bank base address a and block num b */
-#define BANK_ADDR_REG(a, b, r)	BANK_ADDR_OFFSET(BANK_ADDR_OFFSET((a), \
-				    (bank_size_t)(b) * sizeof (bank_blk_t)), \
-					(bank_size_t)(r) * sizeof (bank_word_t))
-
-/* make a bank word value for each StrataFlash value */
-
-/* Commands */
-#define BANK_CMD_RST		BANK_FILL_WORD(ISF_CMD_RST)
-#define BANK_CMD_RD_ID		BANK_FILL_WORD(ISF_CMD_RD_ID)
-#define BANK_CMD_RD_STAT	BANK_FILL_WORD(ISF_CMD_RD_STAT)
-#define BANK_CMD_CLR_STAT	BANK_FILL_WORD(ISF_CMD_CLR_STAT)
-#define BANK_CMD_ERASE1		BANK_FILL_WORD(ISF_CMD_ERASE1)
-#define BANK_CMD_ERASE2		BANK_FILL_WORD(ISF_CMD_ERASE2)
-#define BANK_CMD_PROG		BANK_FILL_WORD(ISF_CMD_PROG)
-#define BANK_CMD_LOCK		BANK_FILL_WORD(ISF_CMD_LOCK)
-#define BANK_CMD_SET_LOCK_BLK	BANK_FILL_WORD(ISF_CMD_SET_LOCK_BLK)
-#define BANK_CMD_SET_LOCK_MSTR	BANK_FILL_WORD(ISF_CMD_SET_LOCK_MSTR)
-#define BANK_CMD_CLR_LOCK_BLK	BANK_FILL_WORD(ISF_CMD_CLR_LOCK_BLK)
-
-/* status register bits */
-#define BANK_STAT_DPS		BANK_FILL_WORD(ISF_STAT_DPS)
-#define BANK_STAT_PSS		BANK_FILL_WORD(ISF_STAT_PSS)
-#define BANK_STAT_VPPS		BANK_FILL_WORD(ISF_STAT_VPPS)
-#define BANK_STAT_PSLBS		BANK_FILL_WORD(ISF_STAT_PSLBS)
-#define BANK_STAT_ECLBS		BANK_FILL_WORD(ISF_STAT_ECLBS)
-#define BANK_STAT_ESS		BANK_FILL_WORD(ISF_STAT_ESS)
-#define BANK_STAT_RDY		BANK_FILL_WORD(ISF_STAT_RDY)
-
-#define BANK_STAT_ERR		BANK_FILL_WORD(ISF_STAT_ERR)
-
-/* make a bank register address for each StrataFlash register address */
-
-#define BANK_REG_MAN_CODE(a)	BANK_ADDR_REG((a), 0, ISF_REG_MAN_CODE)
-#define BANK_REG_DEV_CODE(a)	BANK_ADDR_REG((a), 0, ISF_REG_DEV_CODE)
-#define BANK_REG_BLK_LCK(a, b)	BANK_ADDR_REG((a), (b), ISF_REG_BLK_LCK)
-#define BANK_REG_MST_LCK(a)	BANK_ADDR_REG((a), 0, ISF_REG_MST_LCK)
diff --git a/board/hymod/global_env b/board/hymod/global_env
deleted file mode 100644
index ac12fd7f18f..00000000000
--- a/board/hymod/global_env
+++ /dev/null
@@ -1,145 +0,0 @@
-# DONT FORGET TO CHANGE THE "version" VAR BELOW IF YOU MAKE CHANGES TO THIS FILE
-
-# (C) Copyright 2001
-# Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-
-#
-# global_env
-#
-# file used by Hymod boards to initialise the u-boot non-volatile
-# environment when u-boot is first run (it determines this by the
-# absence of the environment variable "global_env_loaded")
-#
-# format of this file is:
-#
-#	1. blank lines and lines beginning with '#' are ignored
-#	2. all other lines must have the form <name>=<value>
-#	3. if a percent appears anywhere, it is replaced like so:
-#
-#		%s	serial number of the main board (10 digit zero filled)
-#		%S	serial number of the main board (plain number)
-#		%%	a percentage character
-#		... otherwise the %x is discarded
-#
-# if first character in <name> is a dash ('-'), then an existing env var
-# will not be overwritten (the dash is removed). i.e. it is only set if
-# it does not exist
-#
-# if last character in <name> is a plus ('+'), then <value> will be appended
-# to any existing env var (the plus is ignored). Duplicates of <value> are
-# removed.
-#
-# similarly, if the last character in <name> is a minus ('-'), then any
-# occurences of <value> in the current value of <name> will removed (the
-# minus is ignored).
-#
-# leading and trailing whitespace is removed in both <name> and <value>
-# (after processing any initial or final plus/minus in <name>).
-#
-
-# MISCELLANEOUS PARAMETERS
-
-# version must always come first
-version=4
-
-# set the ip address based on the main board serial number
-ipaddr=192.168.1.%S
-serverip=192.168.1.254
-
-# stop auto execute after tftp (not a very good name really)
-autostart=no
-
-# setting this to "yes" forces the global_env file to be loaded and processed
-# if the current version is different to the version in the file
-always_check_env=no
-
-# BOOTING COMMANDS AND PARAMETERS
-
-# command to run when "auto-booting"
-bootcmd=bootm 40080000
-
-# how long the "countdown" to automatically running "bootcmd" is
-bootdelay=2
-
-# how long before it "times out" console input and attempts to run "bootcmd"
-bootretry=5
-
-# arguments passed to the boot program (i.e. linux kernel) via register 6
-# the linux kernel (v2.4) uses the following registers:
-#	r3 - address of board information structure
-#	r4 - address of initial ramdisk image (0 means no initrd)
-#	r5 - size of initial ramdisk image
-#	r6 - address of command line string
--bootargs=root=/dev/mtdblock5 rootfstype=squashfs ro
-
-# these four are for hymod linux integrated into our Sun network
-bootargs+=serialno=%S
-bootargs+=nisclient nisdomain=mlb.dmt.csiro.au nissrvadr=138.194.112.4
-bootargs+=nfsclient
-bootargs+=automount
-
-# start a web server by default
-bootargs+=webserver
-
-# give negotiation time to finish
-bootargs+=netsleep=5
-
-# then our ciscos don't pass packets for 25-30 secs after that, so
-# pinging the server until it responds prevents network connections
-# from failing...
-bootargs+=netping
-
-# these are old bootargs - we don't need them anymore
-bootargs-=preload=unix,i2c-cpm,i2c-dev
-bootargs-=ramdisk_size=32768
-bootargs-=ramdisk_size=24576
-
-# FLASH MANIPULATION COMMANDS
-
-#
-# 16M flash, 64 x 256K sectors, mapped at address 0x40000000
-#
-# Sector(s)	Address		Size	Description
-#
-#  0 -  0	0x40000000	256K	boot code
-#  1 -  1	0x40040000	256K	non volatile environment
-#  2 -  4	0x40080000	768K	linux kernel image
-#  5 -  7	0x40140000	768K	alternate linux kernel image
-#  8 - 47	0x40200000	 10M	linux initial ramdisk image
-# 48 - 63	0x40c00000	  4M	ramdisk image for applications
-#
-
-fetchboot=tftp 100000 /hymod/u-boot.bin
-eraseboot=protect off 1:0 ; erase 1:0 ; protect on 1:0
-copyboot=protect off 1:0 ; cp.b 100000 40000000 40000 ; protect on 1:0
-cmpboot=cmp.b 100000 40000000 40000
-newboot=run fetchboot eraseboot copyboot cmpboot
-
-fetchlinux=tftp 100000 /hymod/linux.bin
-eraselinux=erase 1:2-4
-copylinux=cp.b 100000 40080000 ${filesize}
-cmplinux=cmp.b 100000 40080000 ${filesize}
-newlinux=run fetchlinux eraselinux copylinux cmplinux
-
-fetchaltlinux=tftp 100000 /hymod/altlinux.bin
-erasealtlinux=erase 1:5-7
-copyaltlinux=cp.b 100000 40140000 ${filesize}
-cmpaltlinux=cmp.b 100000 40140000 ${filesize}
-newaltlinux=run fetchaltlinux erasealtlinux copyaltlinux cmpaltlinux
-
-fetchroot=tftp 100000 /hymod/root.bin
-eraseroot=erase 1:8-47
-copyroot=cp.b 100000 40200000 ${filesize}
-cmproot=cmp.b 100000 40200000 ${filesize}
-newroot=run fetchroot eraseroot copyroot cmproot
-
-fetchard=tftp 100000 /hymod/apprd.bin
-eraseard=erase 1:48-63
-copyard=cp.b 100000 40c00000 ${filesize}
-cmpard=cmp.b 100000 40c00000 ${filesize}
-newapprd=run fetchard eraseard copyard cmpard
-
-# pass above map to linux mtd driver
-bootargs+=mtdparts=phys:256k(u-boot),256k(u-boot-env),768k(linux),768k(altlinux),10m(root),4m(hymod)
diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c
deleted file mode 100644
index 0183f781dec..00000000000
--- a/board/hymod/hymod.c
+++ /dev/null
@@ -1,521 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00
- */
-
-#include <common.h>
-#include <bootretry.h>
-#include <cli.h>
-#include <mpc8260.h>
-#include <mpc8260_irq.h>
-#include <ioports.h>
-#include <i2c.h>
-#include <asm/iopin_8260.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-/* imports from eeprom.c */
-extern int hymod_eeprom_read (int, hymod_eeprom_t *);
-extern void hymod_eeprom_print (hymod_eeprom_t *);
-
-/* imports from env.c */
-extern void hymod_check_env (void);
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-	/* Port A configuration */
-	{
-		/* cnf par sor dir odr dat */
-		{   1,  1,  1,  0,  0,  0   },	/* PA31: FCC1 MII COL */
-		{   1,  1,  1,  0,  0,  0   },	/* PA30: FCC1 MII CRS */
-		{   1,  1,  1,  1,  0,  0   },	/* PA29: FCC1 MII TX_ER */
-		{   1,  1,  1,  1,  0,  0   },	/* PA28: FCC1 MII TX_EN */
-		{   1,  1,  1,  0,  0,  0   },	/* PA27: FCC1 MII RX_DV */
-		{   1,  1,  1,  0,  0,  0   },	/* PA26: FCC1 MII RX_ER */
-		{   1,  0,  0,  1,  0,  0   },	/* PA25: FCC2 MII MDIO */
-		{   1,  0,  0,  1,  0,  0   },	/* PA24: FCC2 MII MDC */
-		{   1,  0,  0,  1,  0,  0   },	/* PA23: FCC3 MII MDIO */
-		{   1,  0,  0,  1,  0,  0   },	/* PA22: FCC3 MII MDC */
-		{   1,  1,  0,  1,  0,  0   },	/* PA21: FCC1 MII TxD[3] */
-		{   1,  1,  0,  1,  0,  0   },	/* PA20: FCC1 MII TxD[2] */
-		{   1,  1,  0,  1,  0,  0   },	/* PA19: FCC1 MII TxD[1] */
-		{   1,  1,  0,  1,  0,  0   },	/* PA18: FCC1 MII TxD[0] */
-		{   1,  1,  0,  0,  0,  0   },	/* PA17: FCC1 MII RxD[3] */
-		{   1,  1,  0,  0,  0,  0   },	/* PA16: FCC1 MII RxD[2] */
-		{   1,  1,  0,  0,  0,  0   },	/* PA15: FCC1 MII RxD[1] */
-		{   1,  1,  0,  0,  0,  0   },	/* PA14: FCC1 MII RxD[0] */
-		{   1,  0,  0,  1,  0,  0   },	/* PA13: FCC1 MII MDIO */
-		{   1,  0,  0,  1,  0,  0   },	/* PA12: FCC1 MII MDC */
-		{   1,  0,  0,  1,  0,  0   },	/* PA11: SEL_CD */
-		{   1,  0,  0,  0,  0,  0   },	/* PA10: FLASH STS1 */
-		{   1,  0,  0,  0,  0,  0   },	/* PA09: FLASH STS0 */
-		{   1,  0,  0,  0,  0,  0   },	/* PA08: FLASH ~PE */
-		{   1,  0,  0,  0,  0,  0   },	/* PA07: WATCH ~HRESET */
-		{   1,  0,  0,  0,  1,  0   },	/* PA06: VC DONE */
-		{   1,  0,  0,  1,  1,  0   },	/* PA05: VC INIT */
-		{   1,  0,  0,  1,  0,  0   },	/* PA04: VC ~PROG */
-		{   1,  0,  0,  1,  0,  0   },	/* PA03: VM ENABLE */
-		{   1,  0,  0,  0,  1,  0   },	/* PA02: VM DONE */
-		{   1,  0,  0,  1,  1,  0   },	/* PA01: VM INIT */
-		{   1,  0,  0,  1,  0,  0   }	/* PA00: VM ~PROG */
-	},
-
-	/* Port B configuration */
-	{
-		/* cnf par sor dir odr dat */
-		{   1,  1,  0,  1,  0,  0   },	/* PB31: FCC2 MII TX_ER */
-		{   1,  1,  0,  0,  0,  0   },	/* PB30: FCC2 MII RX_DV */
-		{   1,  1,  1,  1,  0,  0   },	/* PB29: FCC2 MII TX_EN */
-		{   1,  1,  0,  0,  0,  0   },	/* PB28: FCC2 MII RX_ER */
-		{   1,  1,  0,  0,  0,  0   },	/* PB27: FCC2 MII COL */
-		{   1,  1,  0,  0,  0,  0   },	/* PB26: FCC2 MII CRS */
-		{   1,  1,  0,  1,  0,  0   },	/* PB25: FCC2 MII TxD[3] */
-		{   1,  1,  0,  1,  0,  0   },	/* PB24: FCC2 MII TxD[2] */
-		{   1,  1,  0,  1,  0,  0   },	/* PB23: FCC2 MII TxD[1] */
-		{   1,  1,  0,  1,  0,  0   },	/* PB22: FCC2 MII TxD[0] */
-		{   1,  1,  0,  0,  0,  0   },	/* PB21: FCC2 MII RxD[0] */
-		{   1,  1,  0,  0,  0,  0   },	/* PB20: FCC2 MII RxD[1] */
-		{   1,  1,  0,  0,  0,  0   },	/* PB19: FCC2 MII RxD[2] */
-		{   1,  1,  0,  0,  0,  0   },	/* PB18: FCC2 MII RxD[3] */
-		{   1,  1,  0,  0,  0,  0   },	/* PB17: FCC3 MII RX_DV */
-		{   1,  1,  0,  0,  0,  0   },	/* PB16: FCC3 MII RX_ER */
-		{   1,  1,  0,  1,  0,  0   },	/* PB15: FCC3 MII TX_ER */
-		{   1,  1,  0,  1,  0,  0   },	/* PB14: FCC3 MII TX_EN */
-		{   1,  1,  0,  0,  0,  0   },	/* PB13: FCC3 MII COL */
-		{   1,  1,  0,  0,  0,  0   },	/* PB12: FCC3 MII CRS */
-		{   1,  1,  0,  0,  0,  0   },	/* PB11: FCC3 MII RxD[3] */
-		{   1,  1,  0,  0,  0,  0   },	/* PB10: FCC3 MII RxD[2] */
-		{   1,  1,  0,  0,  0,  0   },	/* PB09: FCC3 MII RxD[1] */
-		{   1,  1,  0,  0,  0,  0   },	/* PB08: FCC3 MII RxD[0] */
-		{   1,  1,  0,  1,  0,  0   },	/* PB07: FCC3 MII TxD[3] */
-		{   1,  1,  0,  1,  0,  0   },	/* PB06: FCC3 MII TxD[2] */
-		{   1,  1,  0,  1,  0,  0   },	/* PB05: FCC3 MII TxD[1] */
-		{   1,  1,  0,  1,  0,  0   },	/* PB04: FCC3 MII TxD[0] */
-		{   0,  0,  0,  0,  0,  0   },	/* PB03: pin doesn't exist */
-		{   0,  0,  0,  0,  0,  0   },	/* PB02: pin doesn't exist */
-		{   0,  0,  0,  0,  0,  0   },	/* PB01: pin doesn't exist */
-		{   0,  0,  0,  0,  0,  0   }	/* PB00: pin doesn't exist */
-	},
-
-	/* Port C configuration */
-	{
-		/* cnf par sor dir odr dat */
-		{   1,  0,  0,  0,  0,  0   },	/* PC31: MEZ ~IACK */
-		{   0,  0,  0,  0,  0,  0   },	/* PC30: ? */
-		{   1,  1,  0,  0,  0,  0   },	/* PC29: CLK SCCx */
-		{   1,  1,  0,  0,  0,  0   },	/* PC28: CLK4 */
-		{   1,  1,  0,  0,  0,  0   },	/* PC27: CLK SCCF */
-		{   1,  1,  0,  0,  0,  0   },	/* PC26: CLK 32K */
-		{   1,  1,  0,  0,  0,  0   },	/* PC25: BRG4/CLK7 */
-		{   0,  0,  0,  0,  0,  0   },	/* PC24: ? */
-		{   1,  1,  0,  0,  0,  0   },	/* PC23: CLK SCCx */
-		{   1,  1,  0,  0,  0,  0   },	/* PC22: FCC1 MII RX_CLK */
-		{   1,  1,  0,  0,  0,  0   },	/* PC21: FCC1 MII TX_CLK */
-		{   1,  1,  0,  0,  0,  0   },	/* PC20: CLK SCCF */
-		{   1,  1,  0,  0,  0,  0   },	/* PC19: FCC2 MII RX_CLK */
-		{   1,  1,  0,  0,  0,  0   },	/* PC18: FCC2 MII TX_CLK */
-		{   1,  1,  0,  0,  0,  0   },	/* PC17: FCC3 MII RX_CLK */
-		{   1,  1,  0,  0,  0,  0   },	/* PC16: FCC3 MII TX_CLK */
-		{   1,  0,  0,  0,  0,  0   },	/* PC15: SCC1 UART ~CTS */
-		{   1,  0,  0,  0,  0,  0   },	/* PC14: SCC1 UART ~CD */
-		{   1,  0,  0,  0,  0,  0   },	/* PC13: SCC2 UART ~CTS */
-		{   1,  0,  0,  0,  0,  0   },	/* PC12: SCC2 UART ~CD */
-		{   1,  0,  0,  1,  0,  0   },	/* PC11: SCC1 UART ~DTR */
-		{   1,  0,  0,  1,  0,  0   },	/* PC10: SCC1 UART ~DSR */
-		{   1,  0,  0,  1,  0,  0   },	/* PC09: SCC2 UART ~DTR */
-		{   1,  0,  0,  1,  0,  0   },	/* PC08: SCC2 UART ~DSR */
-		{   1,  0,  0,  0,  0,  0   },	/* PC07: TEMP ~ALERT */
-		{   1,  0,  0,  0,  0,  0   },	/* PC06: FCC3 INT */
-		{   1,  0,  0,  0,  0,  0   },	/* PC05: FCC2 INT */
-		{   1,  0,  0,  0,  0,  0   },	/* PC04: FCC1 INT */
-		{   0,  1,  1,  1,  0,  0   },	/* PC03: SDMA IDMA2 ~DACK */
-		{   0,  1,  1,  0,  0,  0   },	/* PC02: SDMA IDMA2 ~DONE */
-		{   0,  1,  0,  0,  0,  0   },	/* PC01: SDMA IDMA2 ~DREQ */
-		{   1,  1,  0,  1,  0,  0   }	/* PC00: BRG7 */
-	},
-
-	/* Port D configuration */
-	{
-		/* cnf par sor dir odr dat */
-		{   1,  1,  0,  0,  0,  0   },	/* PD31: SCC1 UART RxD */
-		{   1,  1,  1,  1,  0,  0   },	/* PD30: SCC1 UART TxD */
-		{   1,  0,  0,  1,  0,  0   },	/* PD29: SCC1 UART ~RTS */
-		{   1,  1,  0,  0,  0,  0   },	/* PD28: SCC2 UART RxD */
-		{   1,  1,  0,  1,  0,  0   },	/* PD27: SCC2 UART TxD */
-		{   1,  0,  0,  1,  0,  0   },	/* PD26: SCC2 UART ~RTS */
-		{   1,  0,  0,  0,  0,  0   },	/* PD25: SCC1 UART ~RI */
-		{   1,  0,  0,  0,  0,  0   },	/* PD24: SCC2 UART ~RI */
-		{   1,  0,  0,  1,  0,  0   },	/* PD23: CLKGEN PD */
-		{   1,  0,  0,  0,  0,  0   },	/* PD22: USER3 */
-		{   1,  0,  0,  0,  0,  0   },	/* PD21: USER2 */
-		{   1,  0,  0,  0,  0,  0   },	/* PD20: USER1 */
-		{   1,  1,  1,  0,  0,  0   },	/* PD19: SPI ~SEL */
-		{   1,  1,  1,  0,  0,  0   },	/* PD18: SPI CLK */
-		{   1,  1,  1,  0,  0,  0   },	/* PD17: SPI MOSI */
-		{   1,  1,  1,  0,  0,  0   },	/* PD16: SPI MISO */
-		{   1,  1,  1,  0,  1,  0   },	/* PD15: I2C SDA */
-		{   1,  1,  1,  0,  1,  0   },	/* PD14: I2C SCL */
-		{   1,  0,  0,  1,  0,  1   },	/* PD13: TEMP ~STDBY */
-		{   1,  0,  0,  1,  0,  1   },	/* PD12: FCC3 ~RESET */
-		{   1,  0,  0,  1,  0,  1   },	/* PD11: FCC2 ~RESET */
-		{   1,  0,  0,  1,  0,  1   },	/* PD10: FCC1 ~RESET */
-		{   1,  0,  0,  0,  0,  0   },	/* PD09: PD9 */
-		{   1,  0,  0,  0,  0,  0   },	/* PD08: PD8 */
-		{   1,  0,  0,  1,  0,  1   },	/* PD07: PD7 */
-		{   1,  0,  0,  1,  0,  1   },	/* PD06: PD6 */
-		{   1,  0,  0,  1,  0,  1   },	/* PD05: PD5 */
-		{   1,  0,  0,  1,  0,  1   },	/* PD04: PD4 */
-		{   0,  0,  0,  0,  0,  0   },	/* PD03: pin doesn't exist */
-		{   0,  0,  0,  0,  0,  0   },	/* PD02: pin doesn't exist */
-		{   0,  0,  0,  0,  0,  0   },	/* PD01: pin doesn't exist */
-		{   0,  0,  0,  0,  0,  0   }	/* PD00: pin doesn't exist */
-	}
-};
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * AMI FS6377 Clock Generator configuration table
- *
- * the "fs6377_regs[]" table entries correspond to FS6377 registers
- * 0 - 15 (total of 16 bytes).
- *
- * the data is written to the FS6377 via the i2c bus using address in
- * "fs6377_addr" (address is 7 bits - R/W bit not included).
- *
- * The fs6377 has four clock outputs: A, B, C and D.
- *
- * Outputs C and D can each provide two different clock outputs C1/D1 or
- * C2/D2 depending on the state of the SEL_CD input which is connected to
- * the MPC8260 I/O port pin PA11. PA11 output (SEL_CD input) low (or 0)
- * selects C1/D1 and PA11 output (SEL_CD input) high (or 1) selects C2/D2.
- *
- * PA11 defaults to output low (or 0) in the i/o port config table above.
- *
- * Output A provides a 100MHz for the High Speed Serial chips. Output B
- * provides a 3.6864MHz clock for more accurate asynchronous serial bit
- * rates. Output C is routed to the mezzanine connector but is currently
- * unused - both C1 and C2 are set to 16MHz. Output D is used by both the
- * alt-input and display mezzanine boards for their video chips. The
- * alt-input board requires a clock of 24.576MHz and this is available on
- * D1 (PA11=SEL_CD=0). The display board requires a clock of 27MHz and this
- * is available on D2 (PA11=SEL_CD=1).
- *
- * So the default is a clock suitable for the alt-input board. PA11 is toggled
- * later in misc_init_r(), if a display board is detected.
- */
-
-uchar fs6377_addr = 0x5c;
-
-uchar fs6377_regs[16] = {
-	 12,  75,  64,  25, 144, 128,  25, 192,
-	  0,  16, 135, 192, 224,  64,  64, 192
-};
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * special board initialisation, after clocks and timebase have been
- * set up but before environment and serial are initialised.
- *
- * added so that very early initialisations can be done using the i2c
- * driver (which requires the clocks, to calculate the dividers, and
- * the timebase, for udelay())
- */
-
-int
-board_postclk_init (void)
-{
-	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
-	/*
-	 * Initialise the FS6377 clock chip
-	 *
-	 * the secondary address is the register number from where to
-	 * start the write - I want to write all the registers
-	 *
-	 * don't bother checking return status - we have no console yet
-	 * to print it on, nor any RAM to store it in - it will be obvious
-	 * if this doesn't work
-	 */
-	(void) i2c_write (fs6377_addr, 0, 1, fs6377_regs,
-					sizeof (fs6377_regs));
-
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity: Hardwired to HYMOD
- */
-
-int
-checkboard (void)
-{
-	puts ("Board: HYMOD\n");
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * miscellaneous (early - while running in flash) initialisations.
- */
-
-#define _NOT_USED_	0xFFFFFFFF
-
-uint upmb_table[] = {
-	/* Read Single Beat (RSS) - offset 0x00 */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/* Read Burst (RBS) - offset 0x08 */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/* Write Single Beat (WSS) - offset 0x18 */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/* Write Burst (WSS) - offset 0x20 */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/* Refresh Timer (PTS) - offset 0x30 */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/* Exception Condition (EXS) - offset 0x3c */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
-};
-
-uint upmc_table[] = {
-	/* Read Single Beat (RSS) - offset 0x00 */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/* Read Burst (RBS) - offset 0x08 */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/* Write Single Beat (WSS) - offset 0x18 */
-	0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000,
-	0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/* Write Burst (WSS) - offset 0x20 */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/* Refresh Timer (PTS) - offset 0x30 */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/* Exception Condition (EXS) - offset 0x3c */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
-};
-
-int
-misc_init_f (void)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-
-	printf ("UPMs:  ");
-
-	upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]);
-	memctl->memc_mbmr = CONFIG_SYS_MBMR;
-
-	upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]);
-	memctl->memc_mcmr = CONFIG_SYS_MCMR;
-
-	printf ("configured\n");
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t
-initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-	volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
-	ulong psdmr = CONFIG_SYS_PSDMR;
-	int i;
-
-	/*
-	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
-	 *
-	 * "At system reset, initialization software must set up the
-	 *  programmable parameters in the memory controller banks registers
-	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
-	 *  system software should execute the following initialization sequence
-	 *  for each SDRAM device.
-	 *
-	 *  1. Issue a PRECHARGE-ALL-BANKS command
-	 *  2. Issue eight CBR REFRESH commands
-	 *  3. Issue a MODE-SET command to initialize the mode register
-	 *
-	 *  The initial commands are executed by setting P/LSDMR[OP] and
-	 *  accessing the SDRAM with a single-byte transaction."
-	 *
-	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
-	 */
-
-	memctl->memc_psrt = CONFIG_SYS_PSRT;
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
-	*ramaddr = c;
-
-	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
-	for (i = 0; i < 8; i++)
-		*ramaddr = c;
-
-	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
-	*ramaddr = c;
-
-	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
-	*ramaddr = c;
-
-	return (CONFIG_SYS_SDRAM_SIZE << 20);
-}
-
-/* ------------------------------------------------------------------------- */
-/* miscellaneous initialisations after relocation into ram (misc_init_r)     */
-/*									     */
-/* loads the data in the main board and mezzanine board eeproms into	     */
-/* the hymod configuration struct stored in the board information area.	     */
-/*									     */
-/* if the contents of either eeprom is invalid, prompts for a serial	     */
-/* number (and an ethernet address if required) then fetches a file	     */
-/* containing information to be stored in the eeprom from the tftp server    */
-/* (the file name is based on the serial number and a built-in path)	     */
-
-int
-last_stage_init (void)
-{
-	hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
-	int rc;
-
-	/*
-	 * we use the cli_readline() function, but we also want
-	 * command timeout enabled
-	 */
-	bootretry_init_cmd_timeout();
-
-	memset ((void *) cp, 0, sizeof (*cp));
-
-	/* set up main board config info */
-
-	rc = hymod_eeprom_read (0, &cp->main.eeprom);
-
-	puts ("EEPROM:main...");
-	if (rc < 0)
-		puts ("NOT PRESENT\n");
-	else if (rc == 0)
-		puts ("INVALID\n");
-	else {
-		cp->main.eeprom.valid = 1;
-
-		printf ("OK (ver %u)\n", cp->main.eeprom.ver);
-		hymod_eeprom_print (&cp->main.eeprom);
-
-		/*
-		 * hard-wired assumption here: all hymod main boards will have
-		 * one xilinx fpga, with the interrupt line connected to IRQ2
-		 *
-		 * One day, this might be based on the board type
-		 */
-
-		cp->main.xlx[0].mmap.prog.exists = 1;
-		cp->main.xlx[0].mmap.prog.size = FPGA_MAIN_CFG_SIZE;
-		cp->main.xlx[0].mmap.prog.base = FPGA_MAIN_CFG_BASE;
-
-		cp->main.xlx[0].mmap.reg.exists = 1;
-		cp->main.xlx[0].mmap.reg.size = FPGA_MAIN_REG_SIZE;
-		cp->main.xlx[0].mmap.reg.base = FPGA_MAIN_REG_BASE;
-
-		cp->main.xlx[0].mmap.port.exists = 1;
-		cp->main.xlx[0].mmap.port.size = FPGA_MAIN_PORT_SIZE;
-		cp->main.xlx[0].mmap.port.base = FPGA_MAIN_PORT_BASE;
-
-		cp->main.xlx[0].iopins.prog_pin.port = FPGA_MAIN_PROG_PORT;
-		cp->main.xlx[0].iopins.prog_pin.pin = FPGA_MAIN_PROG_PIN;
-		cp->main.xlx[0].iopins.prog_pin.flag = 1;
-		cp->main.xlx[0].iopins.init_pin.port = FPGA_MAIN_INIT_PORT;
-		cp->main.xlx[0].iopins.init_pin.pin = FPGA_MAIN_INIT_PIN;
-		cp->main.xlx[0].iopins.init_pin.flag = 1;
-		cp->main.xlx[0].iopins.done_pin.port = FPGA_MAIN_DONE_PORT;
-		cp->main.xlx[0].iopins.done_pin.pin = FPGA_MAIN_DONE_PIN;
-		cp->main.xlx[0].iopins.done_pin.flag = 1;
-#ifdef FPGA_MAIN_ENABLE_PORT
-		cp->main.xlx[0].iopins.enable_pin.port = FPGA_MAIN_ENABLE_PORT;
-		cp->main.xlx[0].iopins.enable_pin.pin = FPGA_MAIN_ENABLE_PIN;
-		cp->main.xlx[0].iopins.enable_pin.flag = 1;
-#endif
-
-		cp->main.xlx[0].irq = FPGA_MAIN_IRQ;
-	}
-
-	/* set up mezzanine board config info */
-
-	rc = hymod_eeprom_read (1, &cp->mezz.eeprom);
-
-	puts ("EEPROM:mezz...");
-	if (rc < 0)
-		puts ("NOT PRESENT\n");
-	else if (rc == 0)
-		puts ("INVALID\n");
-	else {
-		cp->main.eeprom.valid = 1;
-
-		printf ("OK (ver %u)\n", cp->mezz.eeprom.ver);
-		hymod_eeprom_print (&cp->mezz.eeprom);
-	}
-
-	cp->crc = crc32 (0, (unsigned char *)cp, offsetof (hymod_conf_t, crc));
-
-	hymod_check_env ();
-
-	return (0);
-}
-
-#ifdef CONFIG_SHOW_ACTIVITY
-void board_show_activity (ulong timebase)
-{
-#ifdef CONFIG_SYS_HYMOD_DBLEDS
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-	volatile iop8260_t *iop = &immr->im_ioport;
-	static int shift = 0;
-
-	if ((timestamp % CONFIG_SYS_HZ) == 0) {
-		if (++shift > 3)
-			shift = 0;
-		iop->iop_pdatd =
-				(iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift));
-	}
-#endif /* CONFIG_SYS_HYMOD_DBLEDS */
-}
-
-void show_activity(int arg)
-{
-}
-#endif /* CONFIG_SHOW_ACTIVITY */
diff --git a/board/hymod/hymod.h b/board/hymod/hymod.h
deleted file mode 100644
index 7024d8a807d..00000000000
--- a/board/hymod/hymod.h
+++ /dev/null
@@ -1,305 +0,0 @@
-/*
- * (C) Copyright 2001
- * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _HYMOD_H_
-#define _HYMOD_H_
-
-#ifdef CONFIG_MPC8260
-#include <asm/iopin_8260.h>
-#endif
-
-/*
- * hymod configuration data - passed by boot code via the board information
- * structure (only U-Boot has support for this at the moment)
- *
- * there are three types of data passed up from the boot monitor. the first
- * (type hymod_eeprom_t) is the eeprom data that was read off both the main
- * (or mother) board and the mezzanine board (if any). this data defines how
- * many Xilinx fpgas are on each board, and their types (among other things).
- * the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where
- * in the physical address space the various Xilinx fpga access regions have
- * been mapped by the boot rom. the third type of data (type xlx_iopins_t,
- * one per Xilinx fpga) defines which io port pins are connected to the various
- * signals required to program a Xilinx fpga.
- *
- * A ram/flash "bank" refers to memory controlled by the same chip select.
- *
- * the eeprom contents are defined as in technical note #2 - basically,
- * a header, zero or more records in no particular order, and a 32 bit crc
- * a record is 1 or more type bytes, a length byte and "length" bytes.
- */
-
-#define HYMOD_EEPROM_ID		0xAA	/* eeprom id byte */
-#define HYMOD_EEPROM_VER	1	/* eeprom contents version (0-127) */
-#define HYMOD_EEPROM_SIZE	256	/* number of bytes in the eeprom */
-
-/* eeprom header */
-typedef
-    struct {
-	unsigned char id;		/* eeprom id byte */
-	unsigned char :1;
-	unsigned char ver:7;		/* eeprom contents version number */
-	unsigned long len;		/* total # of bytes btw hdr and crc */
-    }
-hymod_eehdr_t;
-
-/* maximum number of bytes available for eeprom data records */
-#define HYMOD_EEPROM_MAXLEN	(HYMOD_EEPROM_SIZE \
-					- sizeof (hymod_eehdr_t) \
-					- sizeof (unsigned long))
-
-/* eeprom data record */
-typedef
-    union {
-	struct {
-	    unsigned char topbit:1;
-	    unsigned char type:7;
-	    unsigned char len;
-	    unsigned char data[1];	/* variable length */
-	} small;
-	struct {
-	    unsigned short topbit:1;
-	    unsigned short nxtbit:1;
-	    unsigned short type:14;
-	    unsigned short len;
-	    unsigned char data[1];	/* variable length */
-	} medium;
-	struct {
-	    unsigned long topbit:1;
-	    unsigned long nxtbit:1;
-	    unsigned long type:30;
-	    unsigned long len;
-	    unsigned char data[1];	/* variable length */
-	} large;
-    }
-hymod_eerec_t;
-
-#define HYMOD_EEOFF_MAIN	0x00	/* i2c addr offset for main eeprom */
-#define HYMOD_EEOFF_MEZZ	0x04	/* i2c addr offset for mezz eepomr */
-
-/* eeprom record types */
-#define HYMOD_EEREC_SERNO	1	/* serial number */
-#define HYMOD_EEREC_DATE	2	/* date */
-#define HYMOD_EEREC_BATCH	3	/* batch id */
-#define HYMOD_EEREC_TYPE	4	/* board type */
-#define HYMOD_EEREC_REV		5	/* revision number */
-#define HYMOD_EEREC_SDRAM	6	/* sdram sizes */
-#define HYMOD_EEREC_FLASH	7	/* flash sizes */
-#define HYMOD_EEREC_ZBT		8	/* zbt ram sizes */
-#define HYMOD_EEREC_XLXTYP	9	/* Xilinx fpga types */
-#define HYMOD_EEREC_XLXSPD	10	/* Xilinx fpga speeds */
-#define HYMOD_EEREC_XLXTMP	11	/* Xilinx fpga temperatures */
-#define HYMOD_EEREC_XLXGRD	12	/* Xilinx fpga grades */
-#define HYMOD_EEREC_CPUTYP	13	/* Motorola CPU type */
-#define HYMOD_EEREC_CPUSPD	14	/* CPU speed */
-#define HYMOD_EEREC_BUSSPD	15	/* bus speed */
-#define HYMOD_EEREC_CPMSPD	16	/* CPM speed */
-#define HYMOD_EEREC_HSTYPE	17	/* high-speed serial chip type */
-#define HYMOD_EEREC_HSCHIN	18	/* high-speed serial input channels */
-#define HYMOD_EEREC_HSCHOUT	19	/* high-speed serial output channels */
-
-/* some dimensions */
-#define HYMOD_MAX_BATCH		32	/* max no. of bytes in batch id */
-#define HYMOD_MAX_SDRAM		4	/* max sdram "banks" on any board */
-#define HYMOD_MAX_FLASH		4	/* max flash "banks" on any board */
-#define HYMOD_MAX_ZBT		16	/* max ZBT rams on any board */
-#define HYMOD_MAX_XLX		4	/* max Xilinx fpgas on any board */
-
-#define HYMOD_MAX_BYTES		16	/* enough to store any bytes array */
-
-/* board types */
-#define HYMOD_BDTYPE_NONE	0	/* information not present */
-#define HYMOD_BDTYPE_IO		1	/* I/O main board */
-#define HYMOD_BDTYPE_CLP	2	/* CLP main board */
-#define HYMOD_BDTYPE_DSP	3	/* DSP main board */
-#define HYMOD_BDTYPE_INPUT	4	/* video input mezzanine board */
-#define HYMOD_BDTYPE_ALTINPUT	5	/* video input mezzanine board */
-#define HYMOD_BDTYPE_DISPLAY	6	/* video display mezzanine board */
-#define HYMOD_BDTYPE_MAX	7	/* first invalid value */
-
-/* Xilinx fpga types */
-#define HYMOD_XTYP_NONE		0	/* information not present */
-#define HYMOD_XTYP_XCV300E	1	/* Xilinx Virtex 300 */
-#define HYMOD_XTYP_XCV400E	2	/* Xilinx Virtex 400 */
-#define HYMOD_XTYP_XCV600E	3	/* Xilinx Virtex 600 */
-#define HYMOD_XTYP_MAX		4	/* first invalid value */
-
-/* Xilinx fpga speeds */
-#define HYMOD_XSPD_NONE		0	/* information not present */
-#define HYMOD_XSPD_SIX		1
-#define HYMOD_XSPD_SEVEN	2
-#define HYMOD_XSPD_EIGHT	3
-#define HYMOD_XSPD_MAX		4	/* first invalid value */
-
-/* Xilinx fpga temperatures */
-#define HYMOD_XTMP_NONE		0	/* information not present */
-#define HYMOD_XTMP_COM		1
-#define HYMOD_XTMP_IND		2
-#define HYMOD_XTMP_MAX		3	/* first invalid value */
-
-/* Xilinx fpga grades */
-#define HYMOD_XTMP_NONE		0	/* information not present */
-#define HYMOD_XTMP_NORMAL	1
-#define HYMOD_XTMP_ENGSAMP	2
-#define HYMOD_XTMP_MAX		3	/* first invalid value */
-
-/* CPU types */
-#define HYMOD_CPUTYPE_NONE	0	/* information not present */
-#define HYMOD_CPUTYPE_MPC8260	1	/* Motorola MPC8260 embedded powerpc */
-#define HYMOD_CPUTYPE_MAX	2	/* first invalid value */
-
-/* CPU/BUS/CPM clock speeds */
-#define HYMOD_CLKSPD_NONE	0	/* information not present */
-#define HYMOD_CLKSPD_33MHZ	1
-#define HYMOD_CLKSPD_66MHZ	2
-#define HYMOD_CLKSPD_100MHZ	3
-#define HYMOD_CLKSPD_133MHZ	4
-#define HYMOD_CLKSPD_166MHZ	5
-#define HYMOD_CLKSPD_200MHZ	6
-#define HYMOD_CLKSPD_MAX	7	/* first invalid value */
-
-/* high speed serial chip types */
-#define HYMOD_HSSTYPE_NONE	0	/* information not present */
-#define HYMOD_HSSTYPE_AMCC52064	1
-#define HYMOD_HSSTYPE_MAX	2	/* first invalid value */
-
-/* a date (yyyy-mm-dd) */
-typedef
-    struct {
-	unsigned short year;
-	unsigned char month;
-	unsigned char day;
-    }
-hymod_date_t;
-
-/* describes a Xilinx fpga */
-typedef
-    struct {
-	unsigned char type;		/* chip type */
-	unsigned char speed;		/* chip speed rating */
-	unsigned char temp;		/* chip temperature rating */
-	unsigned char grade;		/* chip grade */
-    }
-hymod_xlx_t;
-
-/* describes a Motorola embedded processor */
-typedef
-    struct {
-	unsigned char type;		/* CPU type */
-	unsigned char cpuspd;		/* speed of the PowerPC core */
-	unsigned char busspd;		/* speed of the system and 60x bus */
-	unsigned char cpmspd;		/* speed of the CPM co-processor */
-    }
-hymod_mpc_t;
-
-/* info about high-speed (1Gbit) serial interface */
-typedef
-    struct {
-	unsigned char type;		/* high-speed serial chip type */
-	unsigned char nchin;		/* number of input channels mounted */
-	unsigned char nchout;		/* number of output channels mounted */
-    }
-hymod_hss_t;
-
-/*
- * this defines the contents of the serial eeprom that exists on every
- * hymod board, including mezzanine boards (the serial eeprom will be
- * faked for early development boards that don't have one)
- */
-
-typedef
-    struct {
-	unsigned char valid:1;		/* contents of this struct is valid */
-	unsigned char ver:7;		/* eeprom contents version */
-	unsigned char bdtype;		/* board type */
-	unsigned char bdrev;		/* board revision */
-	unsigned char batchlen;		/* length of batch string below */
-	unsigned long serno;		/* serial number */
-	hymod_date_t date;		/* manufacture date */
-	unsigned char batch[32];	/* manufacturer specific batch id */
-	unsigned char nsdram;		/* # of ram "banks" */
-	unsigned char nflash;		/* # of flash "banks" */
-	unsigned char nzbt;		/* # of ZBT rams */
-	unsigned char nxlx;		/* # of Xilinx fpgas */
-	unsigned char sdramsz[HYMOD_MAX_SDRAM];	/* log2 of sdram size */
-	unsigned char flashsz[HYMOD_MAX_FLASH];	/* log2 of flash size */
-	unsigned char zbtsz[HYMOD_MAX_ZBT];	/* log2 of ZBT ram size */
-	hymod_xlx_t xlx[HYMOD_MAX_XLX];	/* Xilinx fpga info */
-	hymod_mpc_t mpc;		/* Motorola MPC CPU info */
-	hymod_hss_t hss;		/* high-speed serial info */
-    }
-hymod_eeprom_t;
-
-/*
- * this defines a region in the processor's physical address space
- */
-typedef
-    struct {
-	unsigned long exists:1;		/* 1 if the region exists, 0 if not */
-	unsigned long size:31;		/* size in bytes */
-	unsigned long base;		/* base address */
-    }
-xlx_prgn_t;
-
-/*
- * this defines where the various Xilinx fpga access regions are mapped
- * into the physical address space of the processor
- */
-typedef
-    struct {
-	xlx_prgn_t prog;		/* program access region */
-	xlx_prgn_t reg;			/* register access region */
-	xlx_prgn_t port;		/* port access region */
-    }
-xlx_mmap_t;
-
-/*
- * this defines which 8260 i/o port pins are connected to the various
- * signals required for programming a Xilinx fpga
- */
-typedef
-    struct {
-	iopin_t prog_pin;		/* assert for >= 300ns to program */
-	iopin_t init_pin;		/* goes high when fpga is cleared */
-	iopin_t done_pin;		/* goes high when program is done */
-	iopin_t enable_pin;		/* some fpgas need enabling */
-    }
-xlx_iopins_t;
-
-/* all info about one Xilinx chip */
-typedef
-    struct {
-	xlx_mmap_t mmap;
-	xlx_iopins_t iopins;
-	unsigned long irq:8;		/* h/w intr req number for this fpga */
-    }
-xlx_info_t;
-
-/* all info about one hymod board */
-typedef
-    struct {
-	hymod_eeprom_t eeprom;
-	xlx_info_t xlx[HYMOD_MAX_XLX];
-    }
-hymod_board_t;
-
-/*
- * this defines the configuration information of a hymod board-set
- * (main board + possible mezzanine board). In future, there may be
- * more than one mezzanine board (stackable?) - if so, add a "mezz2"
- * field, and so on... or make mezz an array?
- */
-typedef
-    struct {
-	unsigned long ver:8;		/* version control */
-	hymod_board_t main;		/* main board info */
-	hymod_board_t mezz;		/* mezzanine board info */
-	unsigned long crc;		/* ensures kernel and boot prom agree */
-    }
-hymod_conf_t;
-
-#endif /* _HYMOD_H_ */
diff --git a/board/hymod/input.c b/board/hymod/input.c
deleted file mode 100644
index a9035d34059..00000000000
--- a/board/hymod/input.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * (C) Copyright 2003
- * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <bootretry.h>
-#include <cli.h>
-
-int
-hymod_get_serno (const char *prompt)
-{
-	for (;;) {
-		int n, serno;
-		char *p;
-
-		bootretry_reset_cmd_timeout();
-
-		n = cli_readline(prompt);
-
-		if (n < 0)
-			return (n);
-
-		if (n == 0)
-			continue;
-
-		serno = (int) simple_strtol (console_buffer, &p, 10);
-
-		if (p > console_buffer && *p == '\0' && serno > 0)
-			return (serno);
-
-		printf ("Invalid number (%s) - please re-enter\n",
-			console_buffer);
-	}
-}
-
-int
-hymod_get_ethaddr (void)
-{
-	for (;;) {
-		int n;
-
-		bootretry_reset_cmd_timeout();
-
-		n = cli_readline("Enter board ethernet address: ");
-
-		if (n < 0)
-			return (n);
-
-		if (n == 0)
-			continue;
-
-		if (n == 17) {
-			int i;
-			char *p, *q;
-
-			/* see if it looks like an ethernet address */
-
-			p = console_buffer;
-
-			for (i = 0; i < 6; i++) {
-				char term = (i == 5 ? '\0' : ':');
-
-				(void)simple_strtol (p, &q, 16);
-
-				if ((q - p) != 2 || *q++ != term)
-					break;
-
-				p = q;
-			}
-
-			if (i == 6) {
-				/* it looks ok - set it */
-				printf ("Setting ethernet addr to %s\n",
-					console_buffer);
-
-				setenv ("ethaddr", console_buffer);
-
-				puts ("Remember to do a 'saveenv' to "
-					"make it permanent\n");
-
-				return (0);
-			}
-		}
-
-		printf ("Invalid ethernet addr (%s) - please re-enter\n",
-			console_buffer);
-	}
-}
diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds
deleted file mode 100644
index 1dfd2b20f75..00000000000
--- a/board/hymod/u-boot.lds
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8260/start.o	(.text)
-/*
-    common/dlmalloc.o	(.text)
-    arch/powerpc/lib/ppcstring.o	(.text)
-    lib/vsprintf.o	(.text)
-    lib/crc32.o		(.text)
-    lib/zlib.o		(.text)
-
-    . = env_offset;
-*/
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.eh_frame)
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  . = ALIGN(256 * 1024);
-  .ppcenv	:
-  {
-    common/env_embedded.o (.ppcenv)
-  }
-  . = ALIGN(4);
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug
deleted file mode 100644
index b9c84c77d64..00000000000
--- a/board/hymod/u-boot.lds.debug
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib/vsprintf.o	(.text)
-    lib/crc32.o		(.text)
-
-    . = env_offset;
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/icpdas/lp8x4x/Kconfig b/board/icpdas/lp8x4x/Kconfig
index 4374fb654f0..3e87c4016ba 100644
--- a/board/icpdas/lp8x4x/Kconfig
+++ b/board/icpdas/lp8x4x/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_LP8X4X
 
-config SYS_CPU
-	default "pxa"
-
 config SYS_BOARD
 	default "lp8x4x"
 
diff --git a/board/icu862/Kconfig b/board/icu862/Kconfig
deleted file mode 100644
index da11d7b4500..00000000000
--- a/board/icu862/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_ICU862
-
-config SYS_BOARD
-	default "icu862"
-
-config SYS_CONFIG_NAME
-	default "ICU862"
-
-endif
diff --git a/board/icu862/MAINTAINERS b/board/icu862/MAINTAINERS
deleted file mode 100644
index 7fe16d15b76..00000000000
--- a/board/icu862/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-ICU862 BOARD
-M:	Wolfgang Denk <wd@denx.de>
-S:	Maintained
-F:	board/icu862/
-F:	include/configs/ICU862.h
-F:	configs/ICU862_defconfig
-F:	configs/ICU862_100MHz_defconfig
diff --git a/board/icu862/Makefile b/board/icu862/Makefile
deleted file mode 100644
index 263f21b96e2..00000000000
--- a/board/icu862/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= icu862.o flash.o pcmcia.o
diff --git a/board/icu862/flash.c b/board/icu862/flash.c
deleted file mode 100644
index a84ab99f35e..00000000000
--- a/board/icu862/flash.c
+++ /dev/null
@@ -1,575 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef  CONFIG_ENV_SIZE
-#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef  CONFIG_ENV_SECT_SIZE
-#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	unsigned long size_b0;
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0,
-			size_b0 >> 20);
-	}
-
-	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
-	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
-	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      &flash_info[0]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
-		      &flash_info[0]);
-#endif
-
-	/* ICU862 Board has only one Flash Bank */
-	flash_info[0].size = size_b0;
-
-	return size_b0;
-
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-	int i;
-
-	/* set up sector start address table */
-	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
-		((info->flash_id & FLASH_TYPEMASK) == FLASH_AM033C)) {
-		/* set sector offsets for uniform sector type	*/
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00040000);
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		puts ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	puts ("AMD ");		break;
-	case FLASH_MAN_FUJ:	puts ("FUJITSU ");	break;
-	case FLASH_MAN_BM:	puts ("BRIGHT MICRO ");	break;
-	default:		puts ("Unknown Vendor "); break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM040:	puts ("29F040/29LV040 (4 Mbit, uniform sectors)\n");
-				break;
-	case FLASH_AM400B:	puts ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM400T:	puts ("AM29LV400T (4 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM800B:	puts ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM800T:	puts ("AM29LV800T (8 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM160B:	puts ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM160T:	puts ("AM29LV160T (16 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM320B:	puts ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM320T:	puts ("AM29LV320T (32 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM033C:	puts ("AM29LV033C (32 Mbit)\n");
-				break;
-	default:		puts ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	puts ("  Sector Start Addresses:");
-
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0) {
-			puts ("\n   ");
-		}
-
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-
-	puts ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	short i;
-#if 0
-	ulong base = (ulong)addr;
-#endif
-	uchar value;
-
-	/* Write auto select command: read Manufacturer ID */
-#if 0
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00900090;
-#else
-	addr[0x0555] = 0xAAAAAAAA;
-	addr[0x02AA] = 0x55555555;
-	addr[0x0555] = 0x90909090;
-#endif
-
-	value = addr[0];
-
-	switch (value + (value << 16)) {
-	case AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-
-	case FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		break;
-	}
-
-	value = addr[1];			/* device ID		*/
-
-	switch ((unsigned long)value) {
-	case AMD_ID_F040B:
-		info->flash_id += FLASH_AM040;
-		info->sector_count = 8;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-#if 0	/* enable when device IDs are available */
-	case AMD_ID_LV320T:
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-
-	case AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-#endif
-	case AMD_ID_LV033C:
-		info->flash_id += FLASH_AM033C;
-		info->sector_count = 64;
-		info->size = 0x01000000;
-		break;				/* => 16Mb		*/
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-
-	}
-
-#if 0
-	/* set up sector start address table */
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-		}
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-	}
-#else
-	flash_get_offsets ((ulong)addr, &flash_info[0]);
-#endif
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr = (volatile unsigned long *)(info->start[i]);
-#if 1
-		/* We don't know why it happens, but on ICU Board	*
-		 * for AMD29033C flash we need to resend the command of	*
-		 * reading flash protection for upper 8 Mb of flash	*/
-		if ( i == 32 ) {
-			addr[0x0555] = 0xAAAAAAAA;
-			addr[0x02AA] = 0x55555555;
-			addr[0x0555] = 0x90909090;
-		}
-#endif
-		info->protect[i] = addr[2] & 1;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (volatile unsigned long *)info->start[0];
-#if 0
-		*addr = 0x00F000F0;	/* reset bank */
-#else
-		*addr = 0xF0F0F0F0;	/* reset bank */
-#endif
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			puts ("- missing\n");
-		} else {
-			puts ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id == FLASH_UNKNOWN) ||
-	    (info->flash_id > FLASH_AMD_COMP)) {
-		puts ("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		puts ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-#if 0
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00800080;
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-#else
-	addr[0x0555] = 0xAAAAAAAA;
-	addr[0x02AA] = 0x55555555;
-	addr[0x0555] = 0x80808080;
-	addr[0x0555] = 0xAAAAAAAA;
-	addr[0x02AA] = 0x55555555;
-#endif
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (vu_long*)(info->start[sect]);
-#if 0
-			addr[0] = 0x00300030;
-#else
-			addr[0] = 0x30303030;
-#endif
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (vu_long*)(info->start[l_sect]);
-#if 0
-	while ((addr[0] & 0x00800080) != 0x00800080)
-#else
-	while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
-#endif
-	{
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			puts ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-DONE:
-	/* reset to read mode */
-	addr = (volatile unsigned long *)info->start[0];
-#if 0
-	addr[0] = 0x00F000F0;	/* reset bank */
-#else
-	addr[0] = 0xF0F0F0F0;	/* reset bank */
-#endif
-
-	puts (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-#if 0
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00A000A0;
-#else
-	addr[0x0555] = 0xAAAAAAAA;
-	addr[0x02AA] = 0x55555555;
-	addr[0x0555] = 0xA0A0A0A0;
-#endif
-
-	*((vu_long *)dest) = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-#if 0
-	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080))
-#else
-	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080))
-#endif
-	{
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			return (1);
-		}
-	}
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/icu862/icu862.c b/board/icu862/icu862.c
deleted file mode 100644
index 4c0e919739e..00000000000
--- a/board/icu862/icu862.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <mpc8xx.h>
-
-/*
- *  Memory Controller Using
- *
- *  CS0 - Flash memory            (0x40000000)
- *  CS1 - SDRAM                   (0x00000000}
- *  CS2 - S/UNI Ultra ATM155
- *  CS3 - IDT 77106 ATM25
- *  CS4 - DSP HPI
- *  CS5 - E1/T1 Interface device
- *  CS6 - PCMCIA device
- *  CS7 - PCMCIA device
- */
-
-/* ------------------------------------------------------------------------- */
-
-#define _not_used_	0xffffffff
-
-const uint sdram_table[] = {
-	/* single read. (offset 0 in upm RAM) */
-	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
-	0x1ff77c47,
-
-	/* MRS initialization (offset 5) */
-
-	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
-
-	/* burst read. (offset 8 in upm RAM) */
-	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
-	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
-	_not_used_, _not_used_, _not_used_, _not_used_,
-	_not_used_, _not_used_, _not_used_, _not_used_,
-
-	/* single write. (offset 18 in upm RAM) */
-	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
-	_not_used_, _not_used_, _not_used_, _not_used_,
-
-	/* burst write. (offset 20 in upm RAM) */
-	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
-	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
-	_not_used_, _not_used_, _not_used_, _not_used_,
-	_not_used_, _not_used_, _not_used_, _not_used_,
-
-	/* refresh. (offset 30 in upm RAM) */
-	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
-	_not_used_, _not_used_, _not_used_, _not_used_,
-
-	/* exception. (offset 3c in upm RAM) */
-	0x7ffffc07, _not_used_, _not_used_, _not_used_
-};
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
-	puts ("Board: ICU862 Board\n");
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	long int size8, size9;
-	long int size_b0 = 0;
-	unsigned long reg;
-
-	upmconfig (UPMA, (uint *) sdram_table,
-			   sizeof (sdram_table) / sizeof (uint));
-
-	/*
-	 * Preliminary prescaler for refresh (depends on number of
-	 * banks): This value is selected for four cycles every 62.4 us
-	 * with two SDRAM banks or four cycles every 31.2 us with one
-	 * bank. It will be adjusted after memory sizing.
-	 */
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
-
-	memctl->memc_mar = 0x00000088;
-
-	/*
-	 * Map controller bank 1 to the SDRAM bank at
-	 * preliminary address - these have to be modified after the
-	 * SDRAM size has been determined.
-	 */
-	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
-	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
-
-	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
-
-	udelay (200);
-
-	/* perform SDRAM initializsation sequence */
-
-	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
-	udelay (200);
-	memctl->memc_mcr = 0x80002230;	/* SDRAM bank 0 - execute twice */
-	udelay (200);
-
-	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
-
-	udelay (1000);
-
-	/*
-	 * Check Bank 0 Memory Size for re-configuration
-	 *
-	 * try 8 column mode
-	 */
-	size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE1_PRELIM,
-					   SDRAM_MAX_SIZE);
-
-	udelay (1000);
-
-	/*
-	 * try 9 column mode
-	 */
-	size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE1_PRELIM,
-					   SDRAM_MAX_SIZE);
-
-	if (size8 < size9) {		/* leave configuration at 9 columns */
-		size_b0 = size9;
-/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
-	} else {					/* back to 8 columns            */
-		size_b0 = size8;
-		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
-		udelay (500);
-/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
-	}
-
-	udelay (1000);
-
-	/*
-	 * Adjust refresh rate depending on SDRAM type, both banks
-	 * For types > 128 MBit leave it at the current (fast) rate
-	 */
-	if ((size_b0 < 0x02000000)) {
-		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
-		udelay (1000);
-	}
-
-	/*
-	 * Final mapping
-	 */
-
-	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
-	/* adjust refresh rate depending on SDRAM type, one bank */
-	reg = memctl->memc_mptpr;
-	reg >>= 1;					/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
-	memctl->memc_mptpr = reg;
-
-	udelay (10000);
-
-	return (size_b0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
-						   long int maxsize)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	memctl->memc_mamr = mamr_value;
-
-	return (get_ram_size(base, maxsize));
-}
diff --git a/board/icu862/pcmcia.c b/board/icu862/pcmcia.c
deleted file mode 100644
index dbe3c3cf72f..00000000000
--- a/board/icu862/pcmcia.c
+++ /dev/null
@@ -1,262 +0,0 @@
-#include <common.h>
-#include <mpc8xx.h>
-#include <pcmcia.h>
-
-#undef	CONFIG_PCMCIA
-
-#if defined(CONFIG_CMD_PCMCIA)
-#define	CONFIG_PCMCIA
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
-#define	CONFIG_PCMCIA
-#endif
-
-#ifdef	CONFIG_PCMCIA
-
-#define PCMCIA_BOARD_MSG "ICU862"
-
-static void cfg_port_B (void)
-{
-	volatile cpm8xx_t	*cp;
-	uint reg;
-
-	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
-
-	/*
-	 * Configure Port B for TPS2205 PC-Card Power-Interface Switch
-	 *
-	 * Switch off all voltages, assert shutdown
-	 */
-	reg  = cp->cp_pbdat;
-	reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC |	/* VAVPP => Hi-Z */
-			TPS2205_VCC3    | TPS2205_VCC5    |	/* VAVCC => Hi-Z */
-			TPS2205_SHDN);				/* enable switch */
-	cp->cp_pbdat = reg;
-
-	cp->cp_pbpar &= ~(TPS2205_INPUTS | TPS2205_OUTPUTS);
-
-	reg = cp->cp_pbdir & ~(TPS2205_INPUTS);
-	cp->cp_pbdir = reg | TPS2205_OUTPUTS;
-
-	debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n",
-	       cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat);
-}
-
-int pcmcia_hardware_enable(int slot)
-{
-	volatile cpm8xx_t	*cp;
-	volatile pcmconf8xx_t	*pcmp;
-	volatile sysconf8xx_t	*sysp;
-	uint reg, pipr, mask;
-	int i;
-
-	debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
-	udelay(10000);
-
-	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
-
-	/* Configure Port B for TPS2205 PC-Card Power-Interface Switch */
-	cfg_port_B ();
-
-	/*
-	* Configure SIUMCR to enable PCMCIA port B
-	* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
-	*/
-	sysp->sc_siumcr &= ~SIUMCR_DBGC11;	/* set DBGC to 00 */
-
-	/* clear interrupt state, and disable interrupts */
-	pcmp->pcmc_pscr =  PCMCIA_MASK(_slot_);
-	pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
-	/*
-	* Disable interrupts, DMA, and PCMCIA buffers
-	* (isolate the interface) and assert RESET signal
-	*/
-	debug ("Disable PCMCIA buffers and assert RESET\n");
-	reg  = 0;
-	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
-	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
-	udelay(500);
-
-	/*
-	* Make sure there is a card in the slot, then configure the interface.
-	*/
-	udelay(10000);
-	debug ("[%d] %s: PIPR(%p)=0x%x\n",
-	       __LINE__,__FUNCTION__,
-	       &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
-	if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
-		printf ("   No Card found\n");
-		return (1);
-	}
-
-	/*
-	* Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
-	*/
-	mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
-	pipr = pcmp->pcmc_pipr;
-	debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
-	       pipr,
-	       (reg&PCMCIA_VS1(slot))?"n":"ff",
-	       (reg&PCMCIA_VS2(slot))?"n":"ff");
-
-	reg  = cp->cp_pbdat;
-	if ((pipr & mask) == mask) {
-		reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC |	/* VAVPP => Hi-Z */
-				TPS2205_VCC3);				/* 3V off	*/
-		reg &= ~(TPS2205_VCC5);				/* 5V on	*/
-		puts (" 5.0V card found: ");
-	} else {
-		reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC |	/* VAVPP => Hi-Z */
-				TPS2205_VCC5);				/* 5V off	*/
-		reg &= ~(TPS2205_VCC3);				/* 3V on	*/
-		puts (" 3.3V card found: ");
-	}
-
-	debug ("\nPB DAT: %08x -> 3.3V %s 5.0V %s VPP_PGM %s VPP_VCC %s\n",
-	       reg,
-	       (reg & TPS2205_VCC3)    ? "off" : "on",
-	       (reg & TPS2205_VCC5)    ? "off" : "on",
-	       (reg & TPS2205_VPP_PGM) ? "off" : "on",
-	       (reg & TPS2205_VPP_VCC) ? "off" : "on" );
-
-	cp->cp_pbdat = reg;
-
-	/*  Wait 500 ms; use this to check for over-current */
-	for (i=0; i<5000; ++i) {
-		if ((cp->cp_pbdat & TPS2205_OC) == 0) {
-			printf ("   *** Overcurrent - Safety shutdown ***\n");
-			cp->cp_pbdat &= ~(TPS2205_SHDN);
-			return (1);
-		}
-		udelay (100);
-	}
-
-	debug ("Enable PCMCIA buffers and stop RESET\n");
-	reg  =  PCMCIA_PGCRX(_slot_);
-	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
-	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
-
-	udelay(250000);	/* some cards need >150 ms to come up :-( */
-
-	debug ("# hardware_enable done\n");
-
-	return (0);
-}
-
-
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_hardware_disable(int slot)
-{
-	volatile immap_t	*immap;
-	volatile cpm8xx_t	*cp;
-	volatile pcmconf8xx_t	*pcmp;
-	u_long reg;
-
-	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
-	immap = (immap_t *)CONFIG_SYS_IMMR;
-	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
-	/* Shut down */
-	cp->cp_pbdat &= ~(TPS2205_SHDN);
-
-	/* Configure PCMCIA General Control Register */
-	debug ("Disable PCMCIA buffers and assert RESET\n");
-	reg  = 0;
-	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
-	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
-
-	udelay(10000);
-
-	return (0);
-}
-#endif
-
-
-int pcmcia_voltage_set(int slot, int vcc, int vpp)
-{
-	volatile cpm8xx_t	*cp;
-	volatile pcmconf8xx_t	*pcmp;
-	u_long reg;
-
-	debug ("voltage_set: "
-			PCMCIA_BOARD_MSG
-			" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
-	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
-	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-	/*
-	* Disable PCMCIA buffers (isolate the interface)
-	* and assert RESET signal
-	*/
-	debug ("Disable PCMCIA buffers and assert RESET\n");
-	reg  = PCMCIA_PGCRX(_slot_);
-	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
-	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
-	udelay(500);
-
-	/*
-	* Configure Port C pins for
-	* 5 Volts Enable and 3 Volts enable,
-	* Turn all power pins to Hi-Z
-	*/
-	debug ("PCMCIA power OFF\n");
-	cfg_port_B ();	/* Enables switch, but all in Hi-Z */
-
-	reg  = cp->cp_pbdat;
-
-	switch(vcc) {
-		case  0:			break;	/* Switch off		*/
-		case 33: reg &= ~TPS2205_VCC3;	break;	/* Switch on 3.3V	*/
-		case 50: reg &= ~TPS2205_VCC5;	break;	/* Switch on 5.0V	*/
-		default:			goto done;
-	}
-
-	/* Checking supported voltages */
-
-	debug ("PIPR: 0x%x --> %s\n",
-	       pcmp->pcmc_pipr,
-	       (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
-
-	cp->cp_pbdat = reg;
-
-#ifdef DEBUG
-{
-	char *s;
-
-	if ((reg & TPS2205_VCC3) == 0) {
-		s = "at 3.3V";
-	} else if ((reg & TPS2205_VCC5) == 0) {
-		s = "at 5.0V";
-	} else {
-		s = "down";
-	}
-	printf ("PCMCIA powered %s\n", s);
-}
-#endif
-
-done:
-	debug ("Enable PCMCIA buffers and stop RESET\n");
-	reg  =  PCMCIA_PGCRX(_slot_);
-	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
-	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
-	udelay(500);
-
-	debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
-	       slot+'A');
-	return (0);
-}
-
-#endif	/* CONFIG_PCMCIA */
diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds
deleted file mode 100644
index 00f63d2232d..00000000000
--- a/board/icu862/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2001-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug
deleted file mode 100644
index c7c6116b8b7..00000000000
--- a/board/icu862/u-boot.lds.debug
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib/vsprintf.o	(.text)
-    lib/crc32.o		(.text)
-    arch/powerpc/lib/extable.o	(.text)
-
-    . = env_offset;
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/ids/ids8247/Kconfig b/board/ids/ids8247/Kconfig
deleted file mode 100644
index bbab727d782..00000000000
--- a/board/ids/ids8247/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_IDS8247
-
-config SYS_BOARD
-	default "ids8247"
-
-config SYS_VENDOR
-	default "ids"
-
-config SYS_CONFIG_NAME
-	default "IDS8247"
-
-endif
diff --git a/board/ids/ids8247/MAINTAINERS b/board/ids/ids8247/MAINTAINERS
deleted file mode 100644
index 3173cdf01fa..00000000000
--- a/board/ids/ids8247/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-IDS8247 BOARD
-M:	Heiko Schocher <hs@denx.de>
-S:	Maintained
-F:	board/ids/ids8247/
-F:	include/configs/IDS8247.h
-F:	configs/IDS8247_defconfig
diff --git a/board/ids/ids8247/Makefile b/board/ids/ids8247/Makefile
deleted file mode 100644
index 99c47b6697c..00000000000
--- a/board/ids/ids8247/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2005
-# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= ids8247.o
diff --git a/board/ids/ids8247/ids8247.c b/board/ids/ids8247/ids8247.c
deleted file mode 100644
index 1b2d0e09a95..00000000000
--- a/board/ids/ids8247/ids8247.c
+++ /dev/null
@@ -1,390 +0,0 @@
-/*
- * (C) Copyright 2005
- * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <libfdt_env.h>
-#include <fdt_support.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A configuration */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PA31 */ {   1,   1,	 1,   0,   0,	0   }, /* FCC1 COL */
-	/* PA30 */ {   1,   1,	 1,   0,   0,	0   }, /* FCC1 CRS */
-	/* PA29 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC1 TXER */
-	/* PA28 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC1 TXEN */
-	/* PA27 */ {   1,   1,	 1,   0,   0,	0   }, /* FCC1 RXDV */
-	/* PA26 */ {   1,   1,	 1,   0,   0,	0   }, /* FCC1 RXER */
-	/* PA25 */ {   0,   0,	 0,   0,   1,	0   }, /* 8247_P0 */
-#if defined(CONFIG_SYS_I2C_SOFT)
-	/* PA24 */ {   1,   0,	 0,   0,   1,	1   }, /* I2C_SDA2 */
-	/* PA23 */ {   1,   0,	 0,   1,   1,	1   }, /* I2C_SCL2 */
-#else /* normal I/O port pins */
-	/* PA24 */ {   0,   0,	 0,   1,   0,	0   }, /* PA24 */
-	/* PA23 */ {   0,   0,	 0,   1,   0,	0   }, /* PA23 */
-#endif
-	/* PA22 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_DCD */
-	/* PA21 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC1 TXD3 */
-	/* PA20 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC1 TXD2 */
-	/* PA19 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC1 TXD1 */
-	/* PA18 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC1 TXD0 */
-	/* PA17 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 RXD0 */
-	/* PA16 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 RXD1 */
-	/* PA15 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 RXD2 */
-	/* PA14 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 RXD3 */
-	/* PA13 */ {   0,   0,	 0,   1,   1,	0   }, /* SMC2_RTS */
-	/* PA12 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_CTS */
-	/* PA11 */ {   0,   0,	 0,   1,   1,	0   }, /* SMC2_DTR */
-	/* PA10 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_DSR */
-	/* PA9	*/ {   0,   1,	 0,   1,   0,	0   }, /* SMC2 TXD */
-	/* PA8	*/ {   0,   1,	 0,   0,   0,	0   }, /* SMC2 RXD */
-	/* PA7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA7 */
-	/* PA6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA6 */
-	/* PA5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA5 */
-	/* PA4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA4 */
-	/* PA3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA3 */
-	/* PA2	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA2 */
-	/* PA1	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA1 */
-	/* PA0	*/ {   0,   0,	 0,   1,   0,	0   }  /* PA0 */
-    },
-
-    /* Port B configuration */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TX_ER */
-	/* PB30 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_DV */
-	/* PB29 */ {   0,   1,	 1,   1,   0,	0   }, /* FCC2 MII TX_EN */
-	/* PB28 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_ER */
-	/* PB27 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII COL */
-	/* PB26 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII CRS */
-	/* PB25 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[3] */
-	/* PB24 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[2] */
-	/* PB23 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[1] */
-	/* PB22 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[0] */
-	/* PB21 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[0] */
-	/* PB20 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[1] */
-	/* PB19 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[2] */
-	/* PB18 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   0,	 0,   0,   0,	0   }, /* PB17 */
-	/* PB16 */ {   0,   0,	 0,   0,   0,	0   }, /* PB16 */
-	/* PB15 */ {   0,   0,	 0,   0,   0,	0   }, /* PB15 */
-	/* PB14 */ {   0,   0,	 0,   0,   0,	0   }, /* PB14 */
-	/* PB13 */ {   0,   0,	 0,   0,   0,	0   }, /* PB13 */
-	/* PB12 */ {   0,   0,	 0,   0,   0,	0   }, /* PB12 */
-	/* PB11 */ {   0,   0,	 0,   0,   0,	0   }, /* PB11 */
-	/* PB10 */ {   0,   0,	 0,   0,   0,	0   }, /* PB10 */
-	/* PB9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB9 */
-	/* PB8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB8 */
-	/* PB7	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB7 */
-	/* PB6	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB6 */
-	/* PB5	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB5 */
-	/* PB4	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB4 */
-	/* PB3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PB2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PB1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PB0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
-    },
-
-    /* Port C */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,	 0,   1,   0,	0   }, /* PC31 */
-	/* PC30 */ {   0,   0,	 0,   1,   0,	0   }, /* PC30 */
-	/* PC29 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CLSN */
-	/* PC28 */ {   0,   1,	 1,   0,   0,	0   }, /* SYNC_OUT */
-	/* PC27 */ {   0,   0,	 0,   1,   0,	0   }, /* PC27 */
-	/* PC26 */ {   0,   0,	 0,   1,   0,	0   }, /* PC26 */
-	/* PC25 */ {   0,   1,	 1,   0,   0,	0   }, /* SYNC_IN */
-	/* PC24 */ {   0,   0,	 0,   1,   0,	0   }, /* PC24 */
-	/* PC23 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 MII TX_CLK */
-	/* PC22 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 MII RX_CLK */
-	/* PC21 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RXCLK */
-	/* PC20 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN TXCLK */
-	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_CLK */
-	/* PC18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII TX_CLK */
-	/* PC17 */ {   0,   0,	 0,   1,   0,	0   }, /* PC17 */
-	/* PC16 */ {   0,   0,	 0,   1,   0,	0   }, /* PC16 */
-	/* PC15 */ {   0,   0,	 0,   1,   0,	0   }, /* PC15 */
-	/* PC14 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CD */
-	/* PC13 */ {   0,   0,	 0,   1,   0,	0   }, /* PC13 */
-	/* PC12 */ {   0,   0,	 0,   1,   0,	0   }, /* PC12 */
-	/* PC11 */ {   0,   0,	 0,   1,   0,	0   }, /* PC11 */
-	/* PC10 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC2 MDC */
-	/* PC9	*/ {   0,   0,	 0,   1,   0,	0   }, /* FCC2 MDIO */
-	/* PC8	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC8 */
-	/* PC7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC7 */
-	/* PC6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC6 */
-	/* PC5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC5 */
-	/* PC4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC4 */
-	/* PC3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC3 */
-	/* PC2	*/ {   0,   0,	 0,   1,   0,	1   }, /* ENET FDE */
-	/* PC1	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET DSQE */
-	/* PC0	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET LBK */
-    },
-
-    /* Port D */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PD31 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RxD */
-	/* PD30 */ {   0,   1,	 1,   1,   0,	0   }, /* SCC1 EN TxD */
-	/* PD29 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC1 EN TENA */
-	/* PD28 */ {   0,   0,	 0,   1,   0,	0   }, /* PD28 */
-	/* PD27 */ {   0,   0,	 0,   1,   0,	0   }, /* PD27 */
-	/* PD26 */ {   0,   0,	 0,   1,   0,	0   }, /* PD26 */
-	/* PD25 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC3_RX */
-	/* PD24 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC3_TX */
-	/* PD23 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC3_RTS */
-	/* PD22 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC4_RXD */
-	/* PD21 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC4_TXD */
-	/* PD20 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC4_RTS */
-	/* PD19 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_SEL */
-	/* PD18 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_CLK */
-	/* PD17 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_MOSI */
-	/* PD16 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_MISO */
-#if defined(CONFIG_HARD_I2C)
-	/* PD15 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SDA1 */
-	/* PD14 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SCL1 */
-#else /* normal I/O port pins */
-	/* PD15 */ {   0,   1,	 1,   0,   1,	0   }, /* PD15 */
-	/* PD14 */ {   0,   1,	 1,   0,   1,	0   }, /* PD14 */
-#endif
-	/* PD13 */ {   0,   0,	 0,   0,   0,	0   }, /* PD13 */
-	/* PD12 */ {   0,   0,	 0,   0,   0,	0   }, /* PD12 */
-	/* PD11 */ {   0,   0,	 0,   0,   0,	0   }, /* PD11 */
-	/* PD10 */ {   0,   0,	 0,   0,   0,	0   }, /* PD10 */
-	/* PD9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PD9 */
-	/* PD8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PD8 */
-	/* PD7	*/ {   1,   0,	 0,   1,   0,	1   }, /* MII_MDIO */
-	/* PD6	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD6 */
-	/* PD5	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD5 */
-	/* PD4	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD4 */
-	/* PD3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PD2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PD1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PD0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
-    }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
-	puts ("Board: IDS 8247\n");
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
-						  ulong orx, volatile uchar * base)
-{
-	volatile uchar c = 0xff;
-	volatile uint *sdmr_ptr;
-	volatile uint *orx_ptr;
-	ulong maxsize, size;
-	int i;
-
-	/* We must be able to test a location outsize the maximum legal size
-	 * to find out THAT we are outside; but this address still has to be
-	 * mapped by the controller. That means, that the initial mapping has
-	 * to be (at least) twice as large as the maximum expected size.
-	 */
-	maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
-
-	sdmr_ptr = &memctl->memc_psdmr;
-	orx_ptr = &memctl->memc_or2;
-
-	*orx_ptr = orx;
-
-	/*
-	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
-	 *
-	 * "At system reset, initialization software must set up the
-	 *  programmable parameters in the memory controller banks registers
-	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
-	 *  system software should execute the following initialization sequence
-	 *  for each SDRAM device.
-	 *
-	 *  1. Issue a PRECHARGE-ALL-BANKS command
-	 *  2. Issue eight CBR REFRESH commands
-	 *  3. Issue a MODE-SET command to initialize the mode register
-	 *
-	 *  The initial commands are executed by setting P/LSDMR[OP] and
-	 *  accessing the SDRAM with a single-byte transaction."
-	 *
-	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
-	 */
-
-	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
-	*base = c;
-
-	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
-	for (i = 0; i < 8; i++)
-		*base = c;
-
-	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
-
-	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
-	*base = c;
-
-	size = get_ram_size((long *)base, maxsize);
-	*orx_ptr = orx | ~(size - 1);
-
-	return (size);
-}
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-
-	long psize;
-
-	psize = 16 * 1024 * 1024;
-
-	memctl->memc_psrt = CONFIG_SYS_PSRT;
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	/* 60x SDRAM setup:
-	 */
-	psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2,
-						  (uchar *) CONFIG_SYS_SDRAM_BASE);
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	icache_enable ();
-
-	return (psize);
-}
-
-int misc_init_r (void)
-{
-	gd->bd->bi_flashstart = 0xff800000;
-	return 0;
-}
-
-#if defined(CONFIG_CMD_NAND)
-#include <nand.h>
-#include <linux/mtd/mtd.h>
-#include <asm/io.h>
-
-static u8 hwctl;
-
-static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-	struct nand_chip *this = mtd->priv;
-
-	if (ctrl & NAND_CTRL_CHANGE) {
-		if ( ctrl & NAND_CLE ) {
-			hwctl |= 0x1;
-			writeb(0x00, (this->IO_ADDR_W + 0x0a));
-		} else {
-			hwctl &= ~0x1;
-			writeb(0x00, (this->IO_ADDR_W + 0x08));
-		}
-		if ( ctrl & NAND_ALE ) {
-			hwctl |= 0x2;
-			writeb(0x00, (this->IO_ADDR_W + 0x09));
-		} else {
-			hwctl &= ~0x2;
-			writeb(0x00, (this->IO_ADDR_W + 0x08));
-		}
-		if ( (ctrl & NAND_NCE) != NAND_NCE)
-			writeb(0x00, (this->IO_ADDR_W + 0x0c));
-		else
-			writeb(0x00, (this->IO_ADDR_W + 0x08));
-	}
-	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, this->IO_ADDR_W);
-
-}
-
-static u_char ids_nand_read_byte(struct mtd_info *mtd)
-{
-	struct nand_chip *this = mtd->priv;
-
-	return readb(this->IO_ADDR_R);
-}
-
-static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	struct nand_chip *nand = mtd->priv;
-	int i;
-
-	for (i = 0; i < len; i++) {
-		if (hwctl & 0x1)
-			writeb(buf[i], (nand->IO_ADDR_W + 0x02));
-		else if (hwctl & 0x2)
-			writeb(buf[i], (nand->IO_ADDR_W + 0x01));
-		else
-			writeb(buf[i], nand->IO_ADDR_W);
-	}
-}
-
-static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
-{
-	struct nand_chip *this = mtd->priv;
-	int i;
-
-	for (i = 0; i < len; i++) {
-		buf[i] = readb(this->IO_ADDR_R);
-	}
-}
-
-static int ids_nand_dev_ready(struct mtd_info *mtd)
-{
-	/* constant delay (see also tR in the datasheet) */
-	udelay(12);
-	return 1;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
-	nand->ecc.mode = NAND_ECC_SOFT;
-
-	/* Reference hardware control function */
-	nand->cmd_ctrl  = ids_nand_hwctrl;
-	nand->read_byte  = ids_nand_read_byte;
-	nand->write_buf  = ids_nand_write_buf;
-	nand->read_buf   = ids_nand_read_buf;
-	nand->dev_ready  = ids_nand_dev_ready;
-	nand->chip_delay = 12;
-
-	return 0;
-}
-
-#endif	/* CONFIG_CMD_NAND */
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup( blob, bd);
-}
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig
index 401962c4bdd..4c06d0c0d80 100644
--- a/board/imgtec/malta/Kconfig
+++ b/board/imgtec/malta/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MALTA
 
-config SYS_CPU
-	default "mips32"
-
 config SYS_BOARD
 	default "malta"
 
diff --git a/board/imx31_phycore/Kconfig b/board/imx31_phycore/Kconfig
index cf3358dfe0a..d3d202556dc 100644
--- a/board/imx31_phycore/Kconfig
+++ b/board/imx31_phycore/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_IMX31_PHYCORE
 
-config SYS_CPU
-	default "arm1136"
-
 config SYS_BOARD
 	default "imx31_phycore"
 
diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c
index c3443bdc883..086a473e887 100644
--- a/board/iomega/iconnect/iconnect.c
+++ b/board/iomega/iconnect/iconnect.c
@@ -9,7 +9,7 @@
 #include <common.h>
 #include <miiphy.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include "iconnect.h"
 
@@ -22,9 +22,9 @@ int board_early_init_f(void)
 	 * There are maximum 64 gpios controlled through 2 sets of registers
 	 * the below configuration configures mainly initial LED status
 	 */
-	kw_config_gpio(ICONNECT_OE_VAL_LOW,
-			ICONNECT_OE_VAL_HIGH,
-			ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
+	mvebu_config_gpio(ICONNECT_OE_VAL_LOW,
+			  ICONNECT_OE_VAL_HIGH,
+			  ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
 	static const u32 kwmpp_config[] = {
@@ -87,7 +87,7 @@ int board_early_init_f(void)
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
diff --git a/board/isee/igep0033/Kconfig b/board/isee/igep0033/Kconfig
index 4f3aaf481b0..e989e4b15cf 100644
--- a/board/isee/igep0033/Kconfig
+++ b/board/isee/igep0033/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_AM335X_IGEP0033
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "igep0033"
 
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 3b2b1f15b8e..7b87cc27c41 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -5,6 +5,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <dm.h>
+#include <ns16550.h>
 #include <twl4030.h>
 #include <netdev.h>
 #include <asm/gpio.h>
@@ -30,6 +32,17 @@ static const u32 gpmc_lan_config[] = {
 };
 #endif
 
+static const struct ns16550_platdata igep_serial = {
+	OMAP34XX_UART3,
+	2,
+	V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(igep_uart) = {
+	"serial_omap",
+	&igep_serial
+};
+
 /*
  * Routine: board_init
  * Description: Early hardware init.
diff --git a/board/jornada/Kconfig b/board/jornada/Kconfig
index 9c11a136514..195bc26f9e8 100644
--- a/board/jornada/Kconfig
+++ b/board/jornada/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_JORNADA
 
-config SYS_CPU
-	default "sa1100"
-
 config SYS_BOARD
 	default "jornada"
 
diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c
index ed0575cb05a..35546d24e87 100644
--- a/board/karo/tk71/tk71.c
+++ b/board/karo/tk71/tk71.c
@@ -8,7 +8,7 @@
 #include <common.h>
 #include <miiphy.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include <asm/io.h>
 
@@ -26,9 +26,9 @@ int board_early_init_f(void)
 	 * There are maximum 64 gpios controlled through 2 sets of registers
 	 * the  below configuration configures mainly initial LED status
 	 */
-	kw_config_gpio(TK71_OE_VAL_LOW,
-			TK71_OE_VAL_HIGH,
-			TK71_OE_LOW, TK71_OE_HIGH);
+	mvebu_config_gpio(TK71_OE_VAL_LOW,
+			  TK71_OE_VAL_HIGH,
+			  TK71_OE_LOW, TK71_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
 	static const u32 kwmpp_config[] = {
@@ -97,7 +97,7 @@ int board_init(void)
 	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
 
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
diff --git a/board/karo/tx25/Kconfig b/board/karo/tx25/Kconfig
index 24edcc43bcd..42746c1c0f6 100644
--- a/board/karo/tx25/Kconfig
+++ b/board/karo/tx25/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_TX25
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "tx25"
 
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 35402c800bd..1c7c108cb5a 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -20,7 +20,7 @@
 #include <spi.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 
 #include "../common/common.h"
@@ -222,11 +222,11 @@ int board_early_init_f(void)
 	u32 tmp;
 
 	/* set the 2 bitbang i2c pins as output gpios */
-	tmp = readl(KW_GPIO0_BASE + 4);
-	writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
+	tmp = readl(MVEBU_GPIO0_BASE + 4);
+	writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
 #endif
 	/* adjust SDRAM size for bank 0 */
-	kw_sdram_size_adjust(0);
+	mvebu_sdram_size_adjust(0);
 	kirkwood_mpp_conf(kwmpp_config, NULL);
 	return 0;
 }
@@ -234,7 +234,7 @@ int board_early_init_f(void)
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	/*
 	 * The KM_FLASH_GPIO_PIN switches between using a
diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h
index d407d66ae69..a6a55eef491 100644
--- a/board/logicpd/am3517evm/am3517evm.h
+++ b/board/logicpd/am3517evm/am3517evm.h
@@ -333,7 +333,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
 	/* JTAG */\
-	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_NTRST),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) \
diff --git a/board/logicpd/imx27lite/Kconfig b/board/logicpd/imx27lite/Kconfig
index 842d1baa474..c7de2e3814c 100644
--- a/board/logicpd/imx27lite/Kconfig
+++ b/board/logicpd/imx27lite/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_IMX27LITE
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "imx27lite"
 
@@ -19,9 +16,6 @@ endif
 
 if TARGET_MAGNESIUM
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "imx27lite"
 
diff --git a/board/logicpd/imx31_litekit/Kconfig b/board/logicpd/imx31_litekit/Kconfig
index a87fa81d82f..d90f854a18b 100644
--- a/board/logicpd/imx31_litekit/Kconfig
+++ b/board/logicpd/imx31_litekit/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_IMX31_LITEKIT
 
-config SYS_CPU
-	default "arm1136"
-
 config SYS_BOARD
 	default "imx31_litekit"
 
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
index 075fe949ae4..1fd9f2cf01c 100644
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -230,6 +230,6 @@ void set_muxconf_regs(void)
 	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0));
 	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0));
 	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(JTAG_NTRST),		(IEN  | PTD | DIS | M0));
 	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0));
 }
diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c
index 461a852724e..9ef002637a6 100644
--- a/board/logicpd/zoom1/zoom1.c
+++ b/board/logicpd/zoom1/zoom1.c
@@ -15,6 +15,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <dm.h>
+#include <ns16550.h>
 #include <netdev.h>
 #include <twl4030.h>
 #include <asm/io.h>
@@ -41,6 +43,17 @@ static const u32 gpmc_lab_enet[] = {
 	/*CONF7- computed as params */
 };
 
+static const struct ns16550_platdata zoom1_serial = {
+	OMAP34XX_UART3,
+	2,
+	V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(zoom1_uart) = {
+	"serial_omap",
+	&zoom1_serial
+};
+
 /*
  * Routine: board_init
  * Description: Early hardware init.
diff --git a/board/matrix_vision/common/Makefile b/board/matrix_vision/common/Makefile
deleted file mode 100644
index 699da1ca275..00000000000
--- a/board/matrix_vision/common/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= mv_common.o
diff --git a/board/matrix_vision/common/mv_common.c b/board/matrix_vision/common/mv_common.c
deleted file mode 100644
index 1be5aba2e94..00000000000
--- a/board/matrix_vision/common/mv_common.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <environment.h>
-#include <fpga.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_ENV_IS_NOWHERE
-static char* entries_to_keep[] = {
-	"serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt",
-	"fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr",
-	"static_ipaddr", "static_netmask", "static_gateway",
-	"syslog", "watchdog", "netboot", "evo8serialnumber" };
-
-#define MV_MAX_ENV_ENTRY_LENGTH	64
-#define MV_KEEP_ENTRIES		ARRAY_SIZE(entries_to_keep)
-
-void mv_reset_environment(void)
-{
-	int i;
-	char *s[MV_KEEP_ENTRIES];
-	char entries[MV_KEEP_ENTRIES][MV_MAX_ENV_ENTRY_LENGTH];
-
-	printf("\n*** RESET ENVIRONMENT ***\n");
-
-	memset(entries, 0, MV_KEEP_ENTRIES * MV_MAX_ENV_ENTRY_LENGTH);
-	for (i = 0; i < MV_KEEP_ENTRIES; i++) {
-		s[i] = getenv(entries_to_keep[i]);
-		if (s[i]) {
-			printf("save '%s' : %s\n", entries_to_keep[i], s[i]);
-			strncpy(entries[i], s[i], MV_MAX_ENV_ENTRY_LENGTH);
-		}
-	}
-
-	gd->env_valid = 0;
-	env_relocate();
-
-	for (i = 0; i < MV_KEEP_ENTRIES; i++) {
-		if (s[i]) {
-			printf("restore '%s' : %s\n", entries_to_keep[i], s[i]);
-			setenv(entries_to_keep[i], s[i]);
-		}
-	}
-
-	saveenv();
-}
-#endif
-
-int mv_load_fpga(void)
-{
-	int result;
-	size_t data_size = 0;
-	void *fpga_data = NULL;
-	char *datastr = getenv("fpgadata");
-	char *sizestr = getenv("fpgadatasize");
-
-	if (getenv("skip_fpga")) {
-		printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
-		return -1;
-	}
-	printf("loading FPGA\n");
-
-	if (datastr)
-		fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
-	if (sizestr)
-		data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
-	if (!data_size) {
-		printf("fpgadatasize invalid -> FPGA _not_ loaded !\n");
-		return -1;
-	}
-
-	result = fpga_load(0, fpga_data, data_size, BIT_FULL);
-	if (!result)
-		bootstage_mark(BOOTSTAGE_ID_START);
-
-	return result;
-}
-
-u8 *dhcp_vendorex_prep(u8 *e)
-{
-	char *ptr;
-
-	/* DHCP vendor-class-identifier = 60 */
-	if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
-		*e++ = 60;
-		*e++ = strlen(ptr);
-		while (*ptr)
-			*e++ = *ptr++;
-	}
-	/* DHCP_CLIENT_IDENTIFIER = 61 */
-	if ((ptr = getenv("dhcp_client_id"))) {
-		*e++ = 61;
-		*e++ = strlen(ptr);
-		while (*ptr)
-			*e++ = *ptr++;
-	}
-
-	return e;
-}
-
-u8 *dhcp_vendorex_proc(u8 *popt)
-{
-	return NULL;
-}
diff --git a/board/matrix_vision/common/mv_common.h b/board/matrix_vision/common/mv_common.h
deleted file mode 100644
index 369394356cd..00000000000
--- a/board/matrix_vision/common/mv_common.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright 2008 Matrix Vision GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-extern int mv_load_fpga(void);
-extern void mv_reset_environment(void);
diff --git a/board/maxbcm/Kconfig b/board/maxbcm/Kconfig
new file mode 100644
index 00000000000..d34e2abf367
--- /dev/null
+++ b/board/maxbcm/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_MAXBCM
+
+config SYS_CPU
+	string
+	default "armv7"
+
+config SYS_BOARD
+	string
+	default "maxbcm"
+
+config SYS_SOC
+	string
+	default "armada-xp"
+
+config SYS_CONFIG_NAME
+	string
+	default "maxbcm"
+
+endif
diff --git a/board/maxbcm/MAINTAINERS b/board/maxbcm/MAINTAINERS
new file mode 100644
index 00000000000..3c8af212160
--- /dev/null
+++ b/board/maxbcm/MAINTAINERS
@@ -0,0 +1,6 @@
+MAXBCM BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/maxbcm/
+F:	include/configs/maxbcm.h
+F:	configs/maxbcm_defconfig
diff --git a/board/maxbcm/Makefile b/board/maxbcm/Makefile
new file mode 100644
index 00000000000..37c17d6d29f
--- /dev/null
+++ b/board/maxbcm/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= maxbcm.o
diff --git a/board/maxbcm/binary.0 b/board/maxbcm/binary.0
new file mode 100644
index 00000000000..17bfad99dc9
--- /dev/null
+++ b/board/maxbcm/binary.0
@@ -0,0 +1,17 @@
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
+
+In a few weeks, mainline U-Boot will get support to generate the
+bin_hdr with the DDR training code itself. By implementing this code
+as SPL U-Boot. Then this file will not be needed any more and will
+get removed.
+
diff --git a/board/maxbcm/kwbimage.cfg b/board/maxbcm/kwbimage.cfg
new file mode 100644
index 00000000000..5a3bc67c1c8
--- /dev/null
+++ b/board/maxbcm/kwbimage.cfg
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/maxbcm/binary.0 0000005b 00000068
diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c
new file mode 100644
index 00000000000..7fc83ee8205
--- /dev/null
+++ b/board/maxbcm/maxbcm.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/mbus.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Base addresses for the external device chip selects */
+#define DEV_CS0_BASE		0xe0000000
+#define DEV_CS1_BASE		0xe1000000
+#define DEV_CS2_BASE		0xe2000000
+#define DEV_CS3_BASE		0xe3000000
+
+/* Needed for dynamic (board-specific) mbus configuration */
+extern struct mvebu_mbus_state mbus_state;
+
+int board_early_init_f(void)
+{
+	/*
+	 * Don't configure MPP (pin multiplexing) and GPIO here,
+	 * its already done in bin_hdr
+	 */
+
+	/*
+	 * Setup some board specific mbus address windows
+	 */
+	mbus_dt_setup_win(&mbus_state, DEV_CS0_BASE, 16 << 20,
+			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS0);
+	mbus_dt_setup_win(&mbus_state, DEV_CS1_BASE, 16 << 20,
+			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
+	mbus_dt_setup_win(&mbus_state, DEV_CS2_BASE, 16 << 20,
+			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS2);
+	mbus_dt_setup_win(&mbus_state, DEV_CS3_BASE, 16 << 20,
+			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS3);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: maxBCM\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E6185 switch */
+void reset_phy(void)
+{
+	u16 devadr = CONFIG_PHY_BASE_ADDR;
+	char *name = "neta0";
+	u16 reg;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* todo: fill this with the real setup / config code */
+
+	printf("88E6185 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
index 75046fe7ab8..288a1aeb705 100644
--- a/board/micronas/vct/Kconfig
+++ b/board/micronas/vct/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_VCT
 
-config SYS_CPU
-	default "mips32"
-
 config SYS_BOARD
 	default "vct"
 
@@ -12,4 +9,28 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "vct"
 
+menu "vct board options"
+
+choice
+	prompt "Board variant"
+
+config VCT_PLATINUM
+	bool "Enable VCT_PLATINUM"
+
+config VCT_PLATINUMAVC
+	bool "Enable VCT_PLATINUMAVC"
+
+config VCT_PREMIUM
+	bool "Enable VCT_PLATINUMAVC"
+
+endchoice
+
+config VCT_ONENAND
+	bool "Enable VCT_ONENAND"
+
+config VCT_SMALL_IMAGE
+	bool "Enable VCT_SMALL_IMAGE"
+
+endmenu
+
 endif
diff --git a/board/mpl/vcma9/Kconfig b/board/mpl/vcma9/Kconfig
index 08b0fa01847..a1564521b2a 100644
--- a/board/mpl/vcma9/Kconfig
+++ b/board/mpl/vcma9/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_VCMA9
 
-config SYS_CPU
-	default "arm920t"
-
 config SYS_BOARD
 	default "vcma9"
 
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index d01abcee13c..51125df34f0 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -47,46 +47,19 @@ const struct tegra_sysinfo sysinfo = {
 	CONFIG_TEGRA_BOARD_STRING
 };
 
-void __pinmux_init(void)
-{
-}
-
-void pinmux_init(void) __attribute__((weak, alias("__pinmux_init")));
-
-void __pin_mux_usb(void)
-{
-}
-
-void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb")));
-
-void __pin_mux_spi(void)
-{
-}
-
-void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi")));
-
-void __gpio_early_init_uart(void)
-{
-}
-
-void gpio_early_init_uart(void)
-__attribute__((weak, alias("__gpio_early_init_uart")));
+__weak void pinmux_init(void) {}
+__weak void pin_mux_usb(void) {}
+__weak void pin_mux_spi(void) {}
+__weak void gpio_early_init_uart(void) {}
+__weak void pin_mux_display(void) {}
 
 #if defined(CONFIG_TEGRA_NAND)
-void __pin_mux_nand(void)
+__weak void pin_mux_nand(void)
 {
 	funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
 }
-
-void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand")));
 #endif
 
-void __pin_mux_display(void)
-{
-}
-
-void pin_mux_display(void) __attribute__((weak, alias("__pin_mux_display")));
-
 /*
  * Routine: power_det_init
  * Description: turn off power detects
@@ -114,9 +87,8 @@ int board_init(void)
 	clock_init();
 	clock_verify();
 
-#ifdef CONFIG_FDT_SPI
+#ifdef CONFIG_TEGRA_SPI
 	pin_mux_spi();
-	spi_init();
 #endif
 
 #ifdef CONFIG_PWM_TEGRA
@@ -205,12 +177,10 @@ int board_late_init(void)
 }
 
 #if defined(CONFIG_TEGRA_MMC)
-void __pin_mux_mmc(void)
+__weak void pin_mux_mmc(void)
 {
 }
 
-void pin_mux_mmc(void) __attribute__((weak, alias("__pin_mux_mmc")));
-
 /* this is a weak define that we are overriding */
 int board_mmc_init(bd_t *bd)
 {
diff --git a/board/nvidia/common/emc.c b/board/nvidia/common/emc.c
index 8124f8aafde..8c62f36a7b0 100644
--- a/board/nvidia/common/emc.c
+++ b/board/nvidia/common/emc.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include "emc.h"
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/emc.h>
diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
index d338818a64e..de4eb355982 100644
--- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
+++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
@@ -283,6 +283,11 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
 	PINCFG(PCC2,                   DEFAULT,      DOWN,   NORMAL,   INPUT,   DEFAULT, DEFAULT),
 	PINCFG(SDMMC4_CLK_PCC4,        SDMMC4,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
 	PINCFG(CLK2_REQ_PCC5,          DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L0_RST_N_PDD1,      PE0,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L0_CLKREQ_N_PDD2,   PE0,          UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_WAKE_N_PDD3,        PE,           UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_L1_RST_N_PDD5,      PE1,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PEX_L1_CLKREQ_N_PDD6,   PE1,          UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
 	PINCFG(CLK3_OUT_PEE0,          EXTPERIPH3,   NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
 	PINCFG(CLK3_REQ_PEE1,          DEFAULT,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
 	PINCFG(DAP_MCLK1_REQ_PEE2,     SATA,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 6a243f0aea9..11472ebaf20 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/tegra.h>
+#include <asm/arch-tegra/board.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
 #include <asm/arch/gpio.h>
diff --git a/board/olimex/mx23_olinuxino/Kconfig b/board/olimex/mx23_olinuxino/Kconfig
index fb093092852..0b151c9bb81 100644
--- a/board/olimex/mx23_olinuxino/Kconfig
+++ b/board/olimex/mx23_olinuxino/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_MX23_OLINUXINO
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "mx23_olinuxino"
 
diff --git a/board/overo/overo.c b/board/overo/overo.c
index 13220c56dd0..dfb8602bafc 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -13,6 +13,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <dm.h>
+#include <ns16550.h>
 #include <netdev.h>
 #include <twl4030.h>
 #include <linux/mtd/nand.h>
@@ -25,12 +27,19 @@
 #include <asm/mach-types.h>
 #include "overo.h"
 
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/ehci-omap.h>
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #define TWL4030_I2C_BUS			0
 #define EXPANSION_EEPROM_I2C_BUS	2
 #define EXPANSION_EEPROM_I2C_ADDRESS	0x51
 
+#define GUMSTIX_EMPTY_EEPROM		0x0
+
 #define GUMSTIX_SUMMIT			0x01000200
 #define GUMSTIX_TOBI			0x02000200
 #define GUMSTIX_TOBI_DUO		0x03000200
@@ -56,21 +65,17 @@ static struct {
 	char fab_revision[8];
 	char env_var[16];
 	char env_setting[64];
-} expansion_config;
+} expansion_config = {0x0};
 
-#if defined(CONFIG_CMD_NET)
-static void setup_net_chip(void);
-#endif
+static const struct ns16550_platdata overo_serial = {
+	OMAP34XX_UART3,
+	2,
+	V_NS16550_CLK
+};
 
-/* GPMC definitions for LAN9221 chips on Tobi expansion boards */
-static const u32 gpmc_lan_config[] = {
-    NET_LAN9221_GPMC_CONFIG1,
-    NET_LAN9221_GPMC_CONFIG2,
-    NET_LAN9221_GPMC_CONFIG3,
-    NET_LAN9221_GPMC_CONFIG4,
-    NET_LAN9221_GPMC_CONFIG5,
-    NET_LAN9221_GPMC_CONFIG6,
-    /*CONFIG7- computed as params */
+U_BOOT_DEVICE(overo_uart) = {
+	"serial_omap",
+	&overo_serial
 };
 
 /*
@@ -213,6 +218,9 @@ int get_sdio2_config(void)
  */
 unsigned int get_expansion_id(void)
 {
+	if (expansion_config.device_vendor != 0x0)
+		return expansion_config.device_vendor;
+
 	i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
 
 	/* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */
@@ -241,10 +249,6 @@ int misc_init_r(void)
 	twl4030_power_init();
 	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
 
-#if defined(CONFIG_CMD_NET)
-	setup_net_chip();
-#endif
-
 	printf("Board revision: %d\n", get_board_revision());
 
 	switch (get_sdio2_config()) {
@@ -266,6 +270,7 @@ int misc_init_r(void)
 		printf("Recognized Summit expansion board (rev %d %s)\n",
 			expansion_config.revision,
 			expansion_config.fab_revision);
+		MUX_GUMSTIX();
 		setenv("defaultdisplay", "dvi");
 		setenv("expansionname", "summit");
 		break;
@@ -273,6 +278,7 @@ int misc_init_r(void)
 		printf("Recognized Tobi expansion board (rev %d %s)\n",
 			expansion_config.revision,
 			expansion_config.fab_revision);
+		MUX_GUMSTIX();
 		setenv("defaultdisplay", "dvi");
 		setenv("expansionname", "tobi");
 		break;
@@ -280,20 +286,20 @@ int misc_init_r(void)
 		printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
 			expansion_config.revision,
 			expansion_config.fab_revision);
-		/* second lan chip */
-		enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4],
-		    0x2B000000, GPMC_SIZE_16M);
+		MUX_GUMSTIX();
 		break;
 	case GUMSTIX_PALO35:
 		printf("Recognized Palo35 expansion board (rev %d %s)\n",
 			expansion_config.revision,
 			expansion_config.fab_revision);
+		MUX_GUMSTIX();
 		setenv("defaultdisplay", "lcd35");
 		break;
 	case GUMSTIX_PALO43:
 		printf("Recognized Palo43 expansion board (rev %d %s)\n",
 			expansion_config.revision,
 			expansion_config.fab_revision);
+		MUX_GUMSTIX();
 		setenv("defaultdisplay", "lcd43");
 		setenv("expansionname", "palo43");
 		break;
@@ -301,6 +307,7 @@ int misc_init_r(void)
 		printf("Recognized Chestnut43 expansion board (rev %d %s)\n",
 			expansion_config.revision,
 			expansion_config.fab_revision);
+		MUX_GUMSTIX();
 		setenv("defaultdisplay", "lcd43");
 		setenv("expansionname", "chestnut43");
 		break;
@@ -308,11 +315,13 @@ int misc_init_r(void)
 		printf("Recognized Pinto expansion board (rev %d %s)\n",
 			expansion_config.revision,
 			expansion_config.fab_revision);
+		MUX_GUMSTIX();
 		break;
 	case GUMSTIX_GALLOP43:
 		printf("Recognized Gallop43 expansion board (rev %d %s)\n",
 			expansion_config.revision,
 			expansion_config.fab_revision);
+		MUX_GUMSTIX();
 		setenv("defaultdisplay", "lcd43");
 		setenv("expansionname", "gallop43");
 		break;
@@ -320,6 +329,7 @@ int misc_init_r(void)
 		printf("Recognized Alto35 expansion board (rev %d %s)\n",
 			expansion_config.revision,
 			expansion_config.fab_revision);
+		MUX_GUMSTIX();
 		MUX_ALTO35();
 		setenv("defaultdisplay", "lcd35");
 		setenv("expansionname", "alto35");
@@ -328,21 +338,25 @@ int misc_init_r(void)
 		printf("Recognized Stagecoach expansion board (rev %d %s)\n",
 			expansion_config.revision,
 			expansion_config.fab_revision);
+		MUX_GUMSTIX();
 		break;
 	case GUMSTIX_THUMBO:
 		printf("Recognized Thumbo expansion board (rev %d %s)\n",
 			expansion_config.revision,
 			expansion_config.fab_revision);
+		MUX_GUMSTIX();
 		break;
 	case GUMSTIX_TURTLECORE:
 		printf("Recognized Turtlecore expansion board (rev %d %s)\n",
 			expansion_config.revision,
 			expansion_config.fab_revision);
+		MUX_GUMSTIX();
 		break;
 	case GUMSTIX_ARBOR43C:
 		printf("Recognized Arbor43C expansion board (rev %d %s)\n",
 			expansion_config.revision,
 			expansion_config.fab_revision);
+		MUX_GUMSTIX();
 		MUX_ARBOR43C();
 		setenv("defaultdisplay", "lcd43");
 		break;
@@ -350,16 +364,17 @@ int misc_init_r(void)
 		printf("Recognized Ettus Research USRP-E (rev %d %s)\n",
 			expansion_config.revision,
 			expansion_config.fab_revision);
+		MUX_GUMSTIX();
 		MUX_USRP_E();
 		setenv("defaultdisplay", "dvi");
 		break;
 	case GUMSTIX_NO_EEPROM:
-		puts("No EEPROM on expansion board\n");
+	case GUMSTIX_EMPTY_EEPROM:
+		puts("No or empty EEPROM on expansion board\n");
+		MUX_GUMSTIX();
 		setenv("expansionname", "tobi");
 		break;
 	default:
-		if (expansion_id == 0x0)
-			setenv("expansionname", "tobi");
 		printf("Unrecognized expansion board 0x%08x\n", expansion_id);
 		break;
 	}
@@ -388,7 +403,18 @@ void set_muxconf_regs(void)
 	MUX_OVERO();
 }
 
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SPL_BUILD)
+/* GPMC definitions for LAN9221 chips on Tobi expansion boards */
+static const u32 gpmc_lan_config[] = {
+	NET_LAN9221_GPMC_CONFIG1,
+	NET_LAN9221_GPMC_CONFIG2,
+	NET_LAN9221_GPMC_CONFIG3,
+	NET_LAN9221_GPMC_CONFIG4,
+	NET_LAN9221_GPMC_CONFIG5,
+	NET_LAN9221_GPMC_CONFIG6,
+	/*CONFIG7- computed as params */
+};
+
 /*
  * Routine: setup_net_chip
  * Description: Setting up the configuration GPMC registers specific to the
@@ -398,10 +424,6 @@ static void setup_net_chip(void)
 {
 	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 
-	/* first lan chip */
-	enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
-			GPMC_SIZE_16M);
-
 	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
 	writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
 	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
@@ -409,7 +431,14 @@ static void setup_net_chip(void)
 	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
 	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
 		&ctrl_base->gpmc_nadv_ale);
+}
 
+/*
+ * Routine: reset_net_chip
+ * Description: Reset the Ethernet hardware.
+ */
+static void reset_net_chip(void)
+{
 	/* Make GPIO 64 as output pin and send a magic pulse through it */
 	if (!gpio_request(64, "")) {
 		gpio_direction_output(64, 0);
@@ -420,16 +449,42 @@ static void setup_net_chip(void)
 		gpio_set_value(64, 1);
 	}
 }
-#endif
 
 int board_eth_init(bd_t *bis)
 {
+	unsigned int expansion_id;
 	int rc = 0;
+
 #ifdef CONFIG_SMC911X
-	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+	expansion_id = get_expansion_id();
+	switch (expansion_id) {
+	case GUMSTIX_TOBI_DUO:
+		/* second lan chip */
+		enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4],
+				      0x2B000000, GPMC_SIZE_16M);
+		/* no break */
+	case GUMSTIX_TOBI:
+	case GUMSTIX_CHESTNUT43:
+	case GUMSTIX_STAGECOACH:
+	case GUMSTIX_NO_EEPROM:
+	case GUMSTIX_EMPTY_EEPROM:
+		/* first lan chip */
+		enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
+				      0x2C000000, GPMC_SIZE_16M);
+
+		setup_net_chip();
+		reset_net_chip();
+
+		rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+		break;
+	default:
+		break;
+	}
 #endif
+
 	return rc;
 }
+#endif
 
 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
@@ -437,3 +492,32 @@ int board_mmc_init(bd_t *bis)
 	return omap_mmc_init(0, 0, 0, -1, -1);
 }
 #endif
+
+#if defined(CONFIG_USB_EHCI) &&  !defined(CONFIG_SPL_BUILD)
+static struct omap_usbhs_board_data usbhs_bdata = {
+	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
+};
+
+#define GUMSTIX_GPIO_USBH_CPEN		168
+int ehci_hcd_init(int index, enum usb_init_type init,
+		  struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+	/* Enable USB power */
+	if (!gpio_request(GUMSTIX_GPIO_USBH_CPEN, "usbh_cpen"))
+		gpio_direction_output(GUMSTIX_GPIO_USBH_CPEN, 1);
+
+	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(void)
+{
+	/* Disable USB power */
+	gpio_set_value(GUMSTIX_GPIO_USBH_CPEN, 0);
+	gpio_free(GUMSTIX_GPIO_USBH_CPEN);
+
+	return omap_ehci_hcd_stop();
+}
+
+#endif /* CONFIG_USB_EHCI */
diff --git a/board/overo/overo.h b/board/overo/overo.h
index 57725d867f2..d0edf86365a 100644
--- a/board/overo/overo.h
+++ b/board/overo/overo.h
@@ -101,13 +101,9 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) /*GPMC_D14*/\
 	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) /*GPMC_D15*/\
 	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
-	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
 	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
 	MUX_VAL(CP(GPMC_NCS3),		(IEN  | PTU | EN  | M4)) /*GPIO_54*/\
 								 /* - MMC1_WP*/\
-	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
-	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
-	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M0)) /*GPMC_nCS6*/\
 	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M0)) /*GPMC_nCS7*/\
 	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /*GPMC_nCS3*/\
 	MUX_VAL(CP(GPMC_CLK),		(IEN  | PTU | EN  | M0)) /*GPMC_CLK*/\
@@ -117,45 +113,11 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
 	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
 	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
-	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
-	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
-								 /* - SMSC911X_NRES*/\
-	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | DIS | M4)) /*GPIO_65*/\
- /*DSS*/\
-	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
-	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
-	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
-	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
-	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
-	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
-	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
-	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
-	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
-	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
-	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
-	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
-	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
-	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
-	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
-	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
-	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
-	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
-	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
-	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
-	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
-	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
-	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
-	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
-	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
-	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
-	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
-	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
  /*CAMERA*/\
 	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | DIS | M0)) /*CAM_HS */\
 	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | DIS | M0)) /*CAM_VS */\
 	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
 	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | DIS | M0)) /*CAM_PCLK*/\
-	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
 	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
 	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
 	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
@@ -168,13 +130,8 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
 	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
 	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
-	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
-	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M0)) /*CAM_WEN*/\
-	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
 	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | EN  | M4)) /*GPIO_112*/\
 	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | EN  | M4)) /*GPIO_113*/\
-	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | EN  | M4)) /*GPIO_114*/\
-								 /* - PEN_DOWN*/\
 	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | EN  | M4)) /*GPIO_115*/\
  /*Audio Interface */\
 	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
@@ -208,14 +165,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
 	MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M1)) /*UART2_TX*/\
 	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M1)) /*UART2_RX*/\
-	MUX_VAL(CP(UART2_CTS),		(IEN  | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
-	MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M4)) /*GPIO_145*/\
-	MUX_VAL(CP(UART2_TX),		(IEN  | PTD | DIS | M4)) /*GPIO_146*/\
-	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M4)) /*GPIO_147*/\
-	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
 	MUX_VAL(CP(UART1_RTS),		(IEN  | PTU | DIS | M4)) /*GPIO_149*/ \
-	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
-	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
 	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP4_CLKX*/\
 	MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M0)) /*McBSP4_DR*/\
 	MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M0)) /*McBSP4_DX*/\
@@ -228,7 +178,6 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP1_FSX*/\
 	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP1_CLKX*/\
  /*Serial Interface*/\
-	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
 	MUX_VAL(CP(UART3_RTS_SD),	(IEN  | PTU | EN  | M4)) /*GPIO_164 W2W_*/\
 								 /* BT_NRESET*/\
 	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTU | EN  | M0)) /*UART3_RX_IRRX*/\
@@ -255,14 +204,6 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
 	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
 	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
-	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*HDQ_SIO*/\
-	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) /*McSPI1_CLK*/\
-	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI1_SIMO */\
-	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI1_SOMI */\
-	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
-	MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
-	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | DIS | M4)) /*GPIO_176 */\
-								 /* - LAN_INTR */\
 	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA2*/\
 	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA7*/\
 	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M3)) /*HSUSB2_DATA4*/\
@@ -281,21 +222,9 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
 	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
 	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
-	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTU | EN  | M4)) /*GPIO_10*/\
-	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M4)) /*GPIO_186*/\
-	MUX_VAL(CP(ETK_CLK_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_CLK*/\
-	MUX_VAL(CP(ETK_CTL_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_CMD*/\
-	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_14*/\
 	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | EN  | M4)) /*GPIO_15 - X_GATE*/\
 	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_16*/\
 								 /* - W2W_NRESET*/\
-	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT3*/\
-	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT0*/\
-	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT1*/\
-	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT2*/\
-	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_21*/\
-	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_22*/\
-	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_23*/\
 	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
 	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
 	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M3)) /*HSUSB2_DIR*/\
@@ -369,6 +298,85 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
 	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
 
+#define MUX_GUMSTIX() \
+  /*GPMC*/\
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M0)) /*GPMC_nCS6*/\
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M4)) /*GPIO_63*/\
+								 /* - CAM_IRQ*/\
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
+								 /* - SMSC911X_NRES*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | DIS | M4)) /*GPIO_65*/\
+ /*DSS*/\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*CAMERA*/\
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M0)) /*CAM_WEN*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | EN  | M4)) /*GPIO_114*/\
+								 /* - PEN_DOWN*/\
+ /*Bluetooth*/\
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
+	MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M4)) /*GPIO_145*/\
+	MUX_VAL(CP(UART2_TX),		(IEN  | PTD | DIS | M4)) /*GPIO_146*/\
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M4)) /*GPIO_147*/\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+ /*Serial Interface*/\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
+	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*HDQ_SIO*/\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) /*McSPI1_CLK*/\
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI1_SIMO */\
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI1_SOMI */\
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
+	MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | DIS | M4)) /*GPIO_176 */\
+								 /* - LAN_INTR */\
+ /*Control and debug */\
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTU | EN  | M4)) /*GPIO_10*/\
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M4)) /*GPIO_186*/\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_CLK*/\
+	MUX_VAL(CP(ETK_CTL_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_CMD*/\
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_14*/\
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT3*/\
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT0*/\
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT1*/\
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT2*/\
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_21*/\
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_22*/\
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_23*/\
+
 #define MUX_OVERO_SDIO2_DIRECT() \
 	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
 	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
diff --git a/board/palmld/Kconfig b/board/palmld/Kconfig
index a749c8d2bbc..31112957192 100644
--- a/board/palmld/Kconfig
+++ b/board/palmld/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_PALMLD
 
-config SYS_CPU
-	default "pxa"
-
 config SYS_BOARD
 	default "palmld"
 
diff --git a/board/palmtc/Kconfig b/board/palmtc/Kconfig
index 5207490e88b..3eb71988376 100644
--- a/board/palmtc/Kconfig
+++ b/board/palmtc/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_PALMTC
 
-config SYS_CPU
-	default "pxa"
-
 config SYS_BOARD
 	default "palmtc"
 
diff --git a/board/palmtreo680/Kconfig b/board/palmtreo680/Kconfig
index 1992970aedc..b5fdb9a361a 100644
--- a/board/palmtreo680/Kconfig
+++ b/board/palmtreo680/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_PALMTREO680
 
-config SYS_CPU
-	default "pxa"
-
 config SYS_BOARD
 	default "palmtreo680"
 
diff --git a/board/pandora/pandora.h b/board/pandora/pandora.h
index cbf4186f71e..268b92998f6 100644
--- a/board/pandora/pandora.h
+++ b/board/pandora/pandora.h
@@ -310,7 +310,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SYS_BOOT6),		(IEN  | PTD | DIS | M4)) /*GPIO_8*/\
 	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
  /*JTAG*/\
-	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) /*JTAG_nTRST*/\
+	MUX_VAL(CP(JTAG_NTRST),		(IEN  | PTD | DIS | M0)) /*JTAG_NTRST*/\
 	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) /*JTAG_TCK*/\
 	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) /*JTAG_TMS*/\
 	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) /*JTAG_TDI*/\
diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
index ef2844a4974..251db6ab637 100644
--- a/board/pb1x00/Kconfig
+++ b/board/pb1x00/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_PB1X00
 
-config SYS_CPU
-	default "mips32"
-
 config SYS_BOARD
 	default "pb1x00"
 
diff --git a/board/phytec/pcm051/Kconfig b/board/phytec/pcm051/Kconfig
index f4ed7fdbac4..2cc0d8872d7 100644
--- a/board/phytec/pcm051/Kconfig
+++ b/board/phytec/pcm051/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_PCM051
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "pcm051"
 
diff --git a/board/ppcag/bg0900/Kconfig b/board/ppcag/bg0900/Kconfig
index 9d301c2926f..d7f2368a230 100644
--- a/board/ppcag/bg0900/Kconfig
+++ b/board/ppcag/bg0900/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_BG0900
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "bg0900"
 
diff --git a/board/prodrive/p3mx/64460.h b/board/prodrive/p3mx/64460.h
deleted file mode 100644
index 9cf7feea584..00000000000
--- a/board/prodrive/p3mx/64460.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * main board support/init for the Galileo Eval board DB64460.
- */
-
-#ifndef __64460_H__
-#define __64460_H__
-
-/* CPU Configuration bits */
-#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
-#define	CPU_CONF_SINGLE_CPU	(1 << 11)
-#define	CPU_CONF_ENDIANESS	(1 << 12)
-#define CPU_CONF_PIPELINE	(1 << 13)
-#define CPU_CONF_STOP_RETRY	(1 << 17)
-#define CPU_CONF_MULTI_DECODE	(1 << 18)
-#define CPU_CONF_DP_VALID	(1 << 19)
-#define CPU_CONF_PERR_PROP	(1 << 22)
-#define CPU_CONF_AACK_DELAY_2	(1 << 25)
-#define CPU_CONF_AP_VALID	(1 << 26)
-#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
-
-/* CPU Master Control bits */
-#define CPU_MAST_CTL_ARB_EN	(1 << 8)
-#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
-#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
-#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
-#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
-#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
-
-#endif /* __64460_H__ */
diff --git a/board/prodrive/p3mx/Kconfig b/board/prodrive/p3mx/Kconfig
deleted file mode 100644
index 28fb8bb3a07..00000000000
--- a/board/prodrive/p3mx/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P3MX
-
-config SYS_BOARD
-	default "p3mx"
-
-config SYS_VENDOR
-	default "prodrive"
-
-config SYS_CONFIG_NAME
-	default "p3mx"
-
-endif
diff --git a/board/prodrive/p3mx/MAINTAINERS b/board/prodrive/p3mx/MAINTAINERS
deleted file mode 100644
index e60fdb64aa6..00000000000
--- a/board/prodrive/p3mx/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-P3MX BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/prodrive/p3mx/
-F:	include/configs/p3mx.h
-F:	configs/p3m7448_defconfig
-F:	configs/p3m750_defconfig
diff --git a/board/prodrive/p3mx/Makefile b/board/prodrive/p3mx/Makefile
deleted file mode 100644
index 6ddda2296d3..00000000000
--- a/board/prodrive/p3mx/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= misc.o
-obj-y	+= p3mx.o mpsc.o mv_eth.o pci.o sdram_init.o serial.o \
-		../../Marvell/common/i2c.o ../../Marvell/common/memory.o
diff --git a/board/prodrive/p3mx/eth.h b/board/prodrive/p3mx/eth.h
deleted file mode 100644
index d5fe3cb5d33..00000000000
--- a/board/prodrive/p3mx/eth.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __EVB64360_ETH_H__
-#define __EVB64360_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-
-
-int db64360_eth0_poll(void);
-int db64360_eth0_transmit(unsigned int s, volatile char *p);
-void db64360_eth0_disable(void);
-bool network_start(bd_t *bis);
-
-int mv6446x_eth_initialize(bd_t *);
-
-#endif /* __EVB64360_ETH_H__ */
diff --git a/board/prodrive/p3mx/misc.S b/board/prodrive/p3mx/misc.S
deleted file mode 100644
index 233fd83bcca..00000000000
--- a/board/prodrive/p3mx/misc.S
+++ /dev/null
@@ -1,245 +0,0 @@
-#include <config.h>
-#include <74xx_7xx.h>
-#include "version.h"
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#include "../../Marvell/include/mv_gen_reg.h"
-
-#ifdef CONFIG_ECC
-	/* Galileo specific asm code for initializing ECC */
-	.globl board_relocate_rom
-board_relocate_rom:
-	mflr	r7
-	/* update the location of the GT registers */
-	lis	r11, CONFIG_SYS_GT_REGS@h
-	/* if we're using ECC, we must use the DMA engine to copy ourselves */
-	bl	start_idma_transfer_0
-	bl	wait_for_idma_0
-	bl	stop_idma_engine_0
-
-	mtlr	r7
-	blr
-
-	.globl board_init_ecc
-board_init_ecc:
-	mflr	r7
-	/* NOTE: r10 still contains the location we've been relocated to
-	 * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
-
-	/* now that we're running from ram, init the rest of main memory
-	 * for ECC use */
-	lis	r8, CONFIG_SYS_MONITOR_LEN@h
-	ori	r8, r8, CONFIG_SYS_MONITOR_LEN@l
-
-	divw	r3, r10, r8
-
-	/* set up the counter, and init the starting address */
-	mtctr	r3
-	li	r12, 0
-
-	/* bytes per transfer */
-	mr	r5, r8
-about_to_init_ecc:
-1:	mr	r3, r12
-	mr	r4, r12
-	bl	start_idma_transfer_0
-	bl	wait_for_idma_0
-	bl	stop_idma_engine_0
-	add	r12, r12, r8
-	bdnz	1b
-
-	mtlr	r7
-	blr
-
-	/* r3:	dest addr
-	 * r4:	source addr
-	 * r5:	byte count
-	 * r11: gt regbase
-	 * trashes:	 r6, r5
-	 */
-start_idma_transfer_0:
-	/* set the byte count, including the OWN bit */
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0_DMA_BYTE_COUNT
-	stwbrx	r5, 0, (r6)
-
-	/* set the source address */
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
-	stwbrx	r4, 0, (r6)
-
-	/* set the dest address */
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
-	stwbrx	r3, 0, (r6)
-
-	/* set the next record pointer */
-	li	r5, 0
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0NEXT_RECORD_POINTER
-	stwbrx	r5, 0, (r6)
-
-	/* set the low control register */
-	/* bit 9 is NON chained mode, bit 31 is new style descriptors.
-	   bit 12 is channel enable */
-	ori	r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
-	/* 15 shifted by 16 (oris) == bit 31 */
-	oris	r5, r5, (1 << 15)
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0CONTROL
-	stwbrx	r5, 0, (r6)
-
-	blr
-
-	/* this waits for the bytecount to return to zero, indicating
-	 * that the trasfer is complete */
-wait_for_idma_0:
-	mr	r5, r11
-	lis	r6, 0xff
-	ori	r6, r6, 0xffff
-	ori	r5, r5, CHANNEL0_DMA_BYTE_COUNT
-1:	lwbrx	r4, 0, (r5)
-	and.	r4, r4, r6
-	bne	1b
-
-	blr
-
-	/* this turns off channel 0 of the idma engine */
-stop_idma_engine_0:
-	/* shut off the DMA engine */
-	li	r5, 0
-	mr	r6, r11
-	ori	r6, r6, CHANNEL0CONTROL
-	stwbrx	r5, 0, (r6)
-
-	blr
-#endif
-
-#ifdef CONFIG_SYS_BOARD_ASM_INIT
-	/* NOTE: trashes r3-r7 */
-	.globl board_asm_init
-board_asm_init:
-	/* just move the GT registers to where they belong */
-	lis	r3, CONFIG_SYS_DFL_GT_REGS@h
-	ori	r3, r3, CONFIG_SYS_DFL_GT_REGS@l
-	lis	r4, CONFIG_SYS_GT_REGS@h
-	ori	r4, r4, CONFIG_SYS_GT_REGS@l
-	li	r5, INTERNAL_SPACE_DECODE
-
-	/* test to see if we've already moved */
-	lwbrx	r6, r5, r4
-	andi.	r6, r6, 0xffff
-	/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
-/*	rlwinm	r7, r4, 8, 16, 31
-	rlwinm	r7, r4, 12, 16, 31	*/ /* original */
-	rlwinm	r7, r4, 16, 16, 31
-	/* -----------------------------------------------------*/
-	cmp	cr0, r7, r6
-	beqlr
-
-	/* nope, have to move the registers */
-	lwbrx	r6, r5, r3
-	andis.	r6, r6, 0xffff
-	or	r6, r6, r7
-	stwbrx	r6, r5, r3
-
-	/* now, poll for the change */
-1:	lwbrx	r7, r5, r4
-	cmp	cr0, r7, r6
-	bne	1b
-
-	lis	r3, CONFIG_SYS_INT_SRAM_BASE@h
-	ori	r3, r3, CONFIG_SYS_INT_SRAM_BASE@l
-	rlwinm  r3, r3, 16, 16, 31
-	lis	r4, CONFIG_SYS_GT_REGS@h
-	ori	r4, r4, CONFIG_SYS_GT_REGS@l
-	li	r5, INTEGRATED_SRAM_BASE_ADDR
-	stwbrx  r3, r5, r4
-
-2:	lwbrx	r6, r5, r4
-	cmp	cr0, r3, r6
-	bne	2b
-
-	/* done! */
-	blr
-#endif
-
-/* For use of the debug LEDs */
-	.global led_on0_relocated
-led_on0_relocated:
-	xor	r21, r21, r21
-	xor	r18, r18, r18
-	lis	r18, 0xFC80
-	ori	r18, r18, 0x8000
-/*	stw	r21, 0x0(r18)   */
-	sync
-	blr
-
-	.global led_off0_relocated
-led_off0_relocated:
-	xor	r21, r21, r21
-	xor	r18, r18, r18
-	lis	r18, 0xFC81
-	ori	r18, r18, 0x4000
-/*	stw	r21, 0x0(r18)   */
-	sync
-	blr
-
-	.global led_on0
-led_on0:
-	xor	r18, r18, r18
-	lis	r18, 0x1c80
-	ori	r18, r18, 0x8000
-/*	stw	r18, 0x0(r18)  */
-	sync
-	blr
-
-	.global led_off0
-led_off0:
-	xor	r18, r18, r18
-	lis	r18, 0x1c81
-	ori	r18, r18, 0x4000
-/*	stw	r18, 0x0(r18)  */
-	sync
-	blr
-
-	.global led_on1
-led_on1:
-	xor	r18, r18, r18
-	lis	r18, 0x1c80
-	ori	r18, r18, 0xc000
-/*	stw	r18, 0x0(r18)  */
-	sync
-	blr
-
-	.global led_off1
-led_off1:
-	xor	r18, r18, r18
-	lis	r18, 0x1c81
-	ori	r18, r18, 0x8000
-/*	stw	r18, 0x0(r18)  */
-	sync
-	blr
-
-	.global led_on2
-led_on2:
-	xor	r18, r18, r18
-	lis	r18, 0x1c81
-	ori	r18, r18, 0x0000
-/*	stw	r18, 0x0(r18)  */
-	sync
-	blr
-
-	.global led_off2
-led_off2:
-	xor	r18, r18, r18
-	lis	r18, 0x1c81
-	ori	r18, r18, 0xc000
-/*	stw	r18, 0x0(r18)  */
-	sync
-	blr
diff --git a/board/prodrive/p3mx/mpsc.c b/board/prodrive/p3mx/mpsc.c
deleted file mode 100644
index 97d09093bf5..00000000000
--- a/board/prodrive/p3mx/mpsc.c
+++ /dev/null
@@ -1,997 +0,0 @@
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*************************************************************************
- * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
-  ************************************************************************/
-
-/*
- * mpsc.c - driver for console over the MPSC.
- */
-
-
-#include <common.h>
-#include <config.h>
-#include <asm/cache.h>
-
-#include <malloc.h>
-#include "mpsc.h"
-
-#include "mv_regs.h"
-
-#include "../../Marvell/include/memory.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Define this if you wish to use the MPSC as a register based UART.
- * This will force the serial port to not use the SDMA engine at all.
- */
-#undef CONFIG_MPSC_DEBUG_PORT
-
-
-int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
-char (*mpsc_getchar) (void) = mpsc_getchar_debug;
-int (*mpsc_test_char) (void) = mpsc_test_char_debug;
-
-
-static volatile unsigned int *rx_desc_base = NULL;
-static unsigned int rx_desc_index = 0;
-static volatile unsigned int *tx_desc_base = NULL;
-static unsigned int tx_desc_index = 0;
-
-/* local function declarations */
-static int galmpsc_connect (int channel, int connect);
-static int galmpsc_route_rx_clock (int channel, int brg);
-static int galmpsc_route_tx_clock (int channel, int brg);
-static int galmpsc_write_config_regs (int mpsc, int mode);
-static int galmpsc_config_channel_regs (int mpsc);
-static int galmpsc_set_char_length (int mpsc, int value);
-static int galmpsc_set_stop_bit_length (int mpsc, int value);
-static int galmpsc_set_parity (int mpsc, int value);
-static int galmpsc_enter_hunt (int mpsc);
-static int galmpsc_set_brkcnt (int mpsc, int value);
-static int galmpsc_set_tcschar (int mpsc, int value);
-static int galmpsc_set_snoop (int mpsc, int value);
-static int galmpsc_shutdown (int mpsc);
-
-static int galsdma_set_RFT (int channel);
-static int galsdma_set_SFM (int channel);
-static int galsdma_set_rxle (int channel);
-static int galsdma_set_txle (int channel);
-static int galsdma_set_burstsize (int channel, unsigned int value);
-static int galsdma_set_RC (int channel, unsigned int value);
-
-static int galbrg_set_CDV (int channel, int value);
-static int galbrg_enable (int channel);
-static int galbrg_disable (int channel);
-static int galbrg_set_clksrc (int channel, int value);
-static int galbrg_set_CUV (int channel, int value);
-
-static void galsdma_enable_rx (void);
-static int galsdma_set_mem_space (unsigned int memSpace,
-				  unsigned int memSpaceTarget,
-				  unsigned int memSpaceAttr,
-				  unsigned int baseAddress,
-				  unsigned int size);
-
-
-#define SOFTWARE_CACHE_MANAGEMENT
-
-#ifdef SOFTWARE_CACHE_MANAGEMENT
-#define FLUSH_DCACHE(a,b)		 if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
-#define INVALIDATE_DCACHE(a,b)		 if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
-#else
-#define FLUSH_DCACHE(a,b)
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
-#define INVALIDATE_DCACHE(a,b)
-#endif
-
-#ifdef CONFIG_MPSC_DEBUG_PORT
-static void mpsc_debug_init (void)
-{
-
-	volatile unsigned int temp;
-
-	/* Clear the CFR  (CHR4) */
-	/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
-	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
-	temp &= 0xffffff00;
-	temp |= BIT29;
-	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
-		      temp);
-
-	/* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
-	temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
-	temp |= (BIT12 | BIT15);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
-		      temp);
-
-	/* Set int mask */
-	temp = GTREGREAD (GALMPSC_0_INT_MASK);
-	temp |= BIT6;
-	GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
-}
-#endif
-
-char mpsc_getchar_debug (void)
-{
-	volatile int temp;
-	volatile unsigned int cause;
-
-	cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
-	while ((cause & BIT6) == 0) {
-		cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
-	}
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
-			  (CHANNEL * GALMPSC_REG_GAP));
-	/* By writing 1's to the set bits, the register is cleared */
-	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
-		      temp);
-	GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
-	return (temp >> 16) & 0xff;
-}
-
-/* special function for running out of flash.  doesn't modify any
- * global variables [josh] */
-int mpsc_putchar_early (char ch)
-{
-	int mpsc = CHANNEL;
-	int temp =
-		GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
-	galmpsc_set_tcschar (mpsc, ch);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
-		      temp | 0x200);
-
-#define MAGIC_FACTOR	(10*1000000)
-
-	udelay (MAGIC_FACTOR / gd->baudrate);
-	return 0;
-}
-
-/* This is used after relocation, see serial.c and mpsc_init2 */
-static int mpsc_putchar_sdma (char ch)
-{
-	volatile unsigned int *p;
-	unsigned int temp;
-
-
-	/* align the descriptor */
-	p = tx_desc_base;
-	memset ((void *) p, 0, 8 * sizeof (unsigned int));
-
-	/* fill one 64 bit buffer */
-	/* word swap, pad with 0 */
-	p[4] = 0;		/* x */
-	p[5] = (unsigned int) ch;	/* x */
-
-	/* CHANGED completely according to GT64260A dox - NTL */
-	p[0] = 0x00010001;	/* 0 */
-	p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* 4 */
-	p[2] = 0;		/* 8 */
-	p[3] = (unsigned int) &p[4];	/* c */
-
-#if 0
-	p[9] = DESC_FIRST | DESC_LAST;
-	p[10] = (unsigned int) &p[0];
-	p[11] = (unsigned int) &p[12];
-#endif
-
-	FLUSH_DCACHE (&p[0], &p[8]);
-
-	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
-		      (unsigned int) &p[0]);
-	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
-		      (unsigned int) &p[0]);
-
-	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
-	temp |= (TX_DEMAND | TX_STOP);
-	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
-
-	INVALIDATE_DCACHE (&p[1], &p[2]);
-
-	while (p[1] & DESC_OWNER_BIT) {
-		udelay (100);
-		INVALIDATE_DCACHE (&p[1], &p[2]);
-	}
-	return 0;
-}
-
-char mpsc_getchar_sdma (void)
-{
-	static unsigned int done = 0;
-	volatile char ch;
-	unsigned int len = 0, idx = 0, temp;
-
-	volatile unsigned int *p;
-
-
-	do {
-		p = &rx_desc_base[rx_desc_index * 8];
-
-		INVALIDATE_DCACHE (&p[0], &p[1]);
-		/* Wait for character */
-		while (p[1] & DESC_OWNER_BIT) {
-			udelay (100);
-			INVALIDATE_DCACHE (&p[0], &p[1]);
-		}
-
-		/* Handle error case */
-		if (p[1] & (1 << 15)) {
-			printf ("oops, error: %08x\n", p[1]);
-
-			temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
-					  (CHANNEL * GALMPSC_REG_GAP));
-			temp |= (1 << 23);
-			GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
-				      (CHANNEL * GALMPSC_REG_GAP), temp);
-
-			/* Can't poll on abort bit, so we just wait. */
-			udelay (100);
-
-			galsdma_enable_rx ();
-		}
-
-		/* Number of bytes left in this descriptor */
-		len = p[0] & 0xffff;
-
-		if (len) {
-			/* Where to look */
-			idx = 5;
-			if (done > 3)
-				idx = 4;
-			if (done > 7)
-				idx = 7;
-			if (done > 11)
-				idx = 6;
-
-			INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
-			ch = p[idx] & 0xff;
-			done++;
-		}
-
-		if (done < len) {
-			/* this descriptor has more bytes still
-			 * shift down the char we just read, and leave the
-			 * buffer in place for the next time around
-			 */
-			p[idx] = p[idx] >> 8;
-			FLUSH_DCACHE (&p[idx], &p[idx + 1]);
-		}
-
-		if (done == len) {
-			/* nothing left in this descriptor.
-			 * go to next one
-			 */
-			p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
-			p[0] = 0x00100000;
-			FLUSH_DCACHE (&p[0], &p[1]);
-			/* Next descriptor */
-			rx_desc_index = (rx_desc_index + 1) % RX_DESC;
-			done = 0;
-		}
-	} while (len == 0);	/* galileo bug.. len might be zero */
-
-	return ch;
-}
-
-
-int mpsc_test_char_debug (void)
-{
-	if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
-		return 0;
-	else {
-		return 1;
-	}
-}
-
-
-int mpsc_test_char_sdma (void)
-{
-	volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
-
-	INVALIDATE_DCACHE (&p[1], &p[2]);
-
-	if (p[1] & DESC_OWNER_BIT)
-		return 0;
-	else
-		return 1;
-}
-
-int mpsc_init (int baud)
-{
-	/* BRG CONFIG */
-	galbrg_set_baudrate (CHANNEL, baud);
-	galbrg_set_clksrc (CHANNEL, 8);	/* set source=Tclk */
-	galbrg_set_CUV (CHANNEL, 0);	/* set up CountUpValue */
-	galbrg_enable (CHANNEL);	/* Enable BRG */
-
-	/* Set up clock routing */
-	galmpsc_connect (CHANNEL, GALMPSC_CONNECT);	/* connect it */
-
-	galmpsc_route_rx_clock (CHANNEL, CHANNEL);	/* chosse BRG0 for Rx */
-	galmpsc_route_tx_clock (CHANNEL, CHANNEL);	/* chose BRG0 for Tx */
-
-	/* reset MPSC state */
-	galmpsc_shutdown (CHANNEL);
-
-	/* SDMA CONFIG */
-	galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8);	/* in 64 bit words (8 bytes) */
-	galsdma_set_txle (CHANNEL);
-	galsdma_set_rxle (CHANNEL);
-	galsdma_set_RC (CHANNEL, 0xf);
-	galsdma_set_SFM (CHANNEL);
-	galsdma_set_RFT (CHANNEL);
-
-	/* MPSC CONFIG */
-	galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
-	galmpsc_config_channel_regs (CHANNEL);
-	galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8);	/* 8 */
-	galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE);	/* N */
-	galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1);	/* 1 */
-
-#ifdef CONFIG_MPSC_DEBUG_PORT
-	mpsc_debug_init ();
-#endif
-
-	/* COMM_MPSC CONFIG */
-#ifdef SOFTWARE_CACHE_MANAGEMENT
-	galmpsc_set_snoop (CHANNEL, 0);	/* disable snoop */
-#else
-	galmpsc_set_snoop (CHANNEL, 1);	/* enable snoop */
-#endif
-
-	return 0;
-}
-
-
-void mpsc_sdma_init (void)
-{
-	/* Setup SDMA channel0 SDMA_CONFIG_REG*/
-	GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
-
-	/*  Enable MPSC-Window0 for DRAM Bank 0 */
-	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT,
-				   MV64460_SDMA_DRAM_CS_0_TARGET,
-				   0,
-				   memoryGetBankBaseAddress(0),
-				   memoryGetBankSize(0)) != true)
-		printf ("%s: SDMA_Window0 memory setup failed !!! \n",
-			__FUNCTION__);
-
-
-	/*  Enable MPSC-Window1 for DRAM Bank 1 */
-	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT,
-				   MV64460_SDMA_DRAM_CS_1_TARGET,
-				   0,
-				   memoryGetBankBaseAddress(1),
-				   memoryGetBankSize(1)) != true)
-		printf ("%s: SDMA_Window1 memory setup failed !!! \n",
-			__FUNCTION__);
-
-
-	/*  Disable MPSC-Window2 */
-	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT,
-				   MV64460_SDMA_DRAM_CS_2_TARGET,
-				   0,
-				   memoryGetBankBaseAddress(2),
-				   memoryGetBankSize(2)) != true)
-		printf ("%s: SDMA_Window2 memory setup failed !!! \n",
-			__FUNCTION__);
-
-
-	/*  Disable MPSC-Window3 */
-	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT,
-				   MV64460_SDMA_DRAM_CS_3_TARGET,
-				   0,
-				   memoryGetBankBaseAddress(3),
-				   memoryGetBankSize(3)) != true)
-		printf ("%s: SDMA_Window3 memory setup failed !!! \n",
-			__FUNCTION__);
-
-	/*  Setup MPSC0 access mode Window0 full access */
-	GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
-			 (MV64460_SDMA_WIN_ACCESS_FULL <<
-			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
-
-	/*  Setup MPSC1 access mode Window1 full access */
-	GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
-			 (MV64460_SDMA_WIN_ACCESS_FULL <<
-			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
-
-	/* Setup MPSC internal address space base address	*/
-	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
-
-	/* no high address remap*/
-	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
-	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
-
-	/* clear interrupt cause register for MPSC (fault register)*/
-	GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
-}
-
-
-void mpsc_init2 (void)
-{
-	int i;
-
-#ifndef CONFIG_MPSC_DEBUG_PORT
-	mpsc_putchar = mpsc_putchar_sdma;
-	mpsc_getchar = mpsc_getchar_sdma;
-	mpsc_test_char = mpsc_test_char_sdma;
-#endif
-	/* RX descriptors */
-	rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
-						sizeof (unsigned int));
-
-	/* align descriptors */
-	rx_desc_base = (unsigned int *)
-		(((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
-
-	rx_desc_index = 0;
-
-	memset ((void *) rx_desc_base, 0,
-		(RX_DESC * 8) * sizeof (unsigned int));
-
-	for (i = 0; i < RX_DESC; i++) {
-		rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4];	/* Buffer */
-		rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8];	/* Next descriptor */
-		rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* Command & control */
-		rx_desc_base[i * 8] = 0x00100000;
-	}
-	rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
-
-	FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
-	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
-		      (unsigned int) &rx_desc_base[0]);
-
-	/* TX descriptors */
-	tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
-						sizeof (unsigned int));
-
-	/* align descriptors */
-	tx_desc_base = (unsigned int *)
-		(((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
-
-	tx_desc_index = -1;
-
-	memset ((void *) tx_desc_base, 0,
-		(TX_DESC * 8) * sizeof (unsigned int));
-
-	for (i = 0; i < TX_DESC; i++) {
-		tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
-		tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
-		tx_desc_base[i * 8 + 3] =
-			(unsigned int) &tx_desc_base[i * 8 + 4];
-		tx_desc_base[i * 8 + 2] =
-			(unsigned int) &tx_desc_base[(i + 1) * 8];
-		tx_desc_base[i * 8 + 1] =
-			DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
-
-		/* set sbytecnt and shadow byte cnt to 1 */
-		tx_desc_base[i * 8] = 0x00010001;
-	}
-	tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
-
-	FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
-
-	udelay (100);
-
-	galsdma_enable_rx ();
-
-	return;
-}
-
-int galbrg_set_baudrate (int channel, int rate)
-{
-	int clock;
-
-	galbrg_disable (channel);	/*ok */
-
-#ifdef ZUMA_NTL
-	/* from tclk */
-	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
-#else
-	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
-#endif
-
-	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
-
-	galbrg_enable (channel);
-
-	gd->baudrate = rate;
-
-	return 0;
-}
-
-/* ------------------------------------------------------------------ */
-
-/* Below are all the private functions that no one else needs */
-
-static int galbrg_set_CDV (int channel, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp &= 0xFFFF0000;
-	temp |= (value & 0x0000FFFF);
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galbrg_enable (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp |= 0x00010000;
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galbrg_disable (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp &= 0xFFFEFFFF;
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galbrg_set_clksrc (int channel, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp &= 0xFFC3FFFF;	/* Bit 18 - 21 (MV 64260 18-22) */
-	temp |= (value << 18);
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-	return 0;
-}
-
-static int galbrg_set_CUV (int channel, int value)
-{
-	/* set CountUpValue */
-	GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
-
-	return 0;
-}
-
-#if 0
-static int galbrg_reset (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
-	temp |= 0x20000;
-	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
-	return 0;
-}
-#endif
-
-static int galsdma_set_RFT (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp |= 0x00000001;
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_SFM (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp |= 0x00000002;
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_rxle (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp |= 0x00000040;
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_txle (int channel)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp |= 0x00000080;
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_RC (int channel, unsigned int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp &= ~0x0000003c;
-	temp |= (value << 2);
-	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
-		      temp);
-
-	return 0;
-}
-
-static int galsdma_set_burstsize (int channel, unsigned int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
-	temp &= 0xFFFFCFFF;
-	switch (value) {
-	case 8:
-		GT_REG_WRITE (GALSDMA_0_CONF_REG +
-			      (channel * GALSDMA_REG_DIFF),
-			      (temp | (0x3 << 12)));
-		break;
-
-	case 4:
-		GT_REG_WRITE (GALSDMA_0_CONF_REG +
-			      (channel * GALSDMA_REG_DIFF),
-			      (temp | (0x2 << 12)));
-		break;
-
-	case 2:
-		GT_REG_WRITE (GALSDMA_0_CONF_REG +
-			      (channel * GALSDMA_REG_DIFF),
-			      (temp | (0x1 << 12)));
-		break;
-
-	case 1:
-		GT_REG_WRITE (GALSDMA_0_CONF_REG +
-			      (channel * GALSDMA_REG_DIFF),
-			      (temp | (0x0 << 12)));
-		break;
-
-	default:
-		return -1;
-		break;
-	}
-
-	return 0;
-}
-
-static int galmpsc_connect (int channel, int connect)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
-
-	if ((channel == 0) && connect)
-		temp &= ~0x00000007;
-	else if ((channel == 1) && connect)
-		temp &= ~(0x00000007 << 6);
-	else if ((channel == 0) && !connect)
-		temp |= 0x00000007;
-	else
-		temp |= (0x00000007 << 6);
-
-	/* Just in case... */
-	temp &= 0x3fffffff;
-
-	GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
-
-	return 0;
-}
-
-static int galmpsc_route_rx_clock (int channel, int brg)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_RxC_ROUTE);
-
-	if (channel == 0) {
-		temp &= ~0x0000000F;
-		temp |= brg;
-	} else {
-		temp &= ~0x00000F00;
-		temp |= (brg << 8);
-	}
-
-	GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
-
-	return 0;
-}
-
-static int galmpsc_route_tx_clock (int channel, int brg)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_TxC_ROUTE);
-
-	if (channel == 0) {
-		temp &= ~0x0000000F;
-		temp |= brg;
-	} else {
-		temp &= ~0x00000F00;
-		temp |= (brg << 8);
-	}
-
-	GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
-
-	return 0;
-}
-
-static int galmpsc_write_config_regs (int mpsc, int mode)
-{
-	if (mode == GALMPSC_UART) {
-		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
-		GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
-			      0x000004c4);
-
-		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
-		GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
-			      0x024003f8);
-		/*        22 2222 1111 */
-		/*        54 3210 9876 */
-		/* 0000 0010 0000 0000 */
-		/*       1 */
-		/*       098 7654 3210 */
-		/* 0000 0011 1111 1000 */
-	} else
-		return -1;
-
-	return 0;
-}
-
-static int galmpsc_config_channel_regs (int mpsc)
-{
-	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
-
-	galmpsc_set_brkcnt (mpsc, 0x3);
-	galmpsc_set_tcschar (mpsc, 0xab);
-
-	return 0;
-}
-
-static int galmpsc_set_brkcnt (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
-	temp &= 0x0000FFFF;
-	temp |= (value << 16);
-	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_set_tcschar (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
-	temp &= 0xFFFF0000;
-	temp |= value;
-	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_set_char_length (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
-	temp &= 0xFFFFCFFF;
-	temp |= (value << 12);
-	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_set_stop_bit_length (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
-	temp &= 0xFFFFBFFF;
-	temp |= (value << 14);
-	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_set_parity (int mpsc, int value)
-{
-	unsigned int temp;
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
-	if (value != -1) {
-		temp &= 0xFFF3FFF3;
-		temp |= ((value << 18) | (value << 2));
-		temp |= ((value << 17) | (value << 1));
-	} else {
-		temp &= 0xFFF1FFF1;
-	}
-
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	return 0;
-}
-
-static int galmpsc_enter_hunt (int mpsc)
-{
-	int temp;
-
-	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
-	temp |= 0x80000000;
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
-	       MPSC_ENTER_HUNT) {
-		udelay (1);
-	}
-	return 0;
-}
-
-
-static int galmpsc_shutdown (int mpsc)
-{
-	unsigned int temp;
-
-	/* cause RX abort (clears RX) */
-	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
-	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
-	temp &= ~MPSC_ENTER_HUNT;
-	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
-	GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
-	GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
-
-	/* shut down the MPSC */
-	GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
-	GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
-	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
-
-	udelay (100);
-
-	/* shut down the sdma engines. */
-	/* reset config to default */
-	GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
-
-	udelay (100);
-
-	/* clear the SDMA current and first TX and RX pointers */
-	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
-	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
-	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
-
-	udelay (100);
-
-	return 0;
-}
-
-static void galsdma_enable_rx (void)
-{
-	int temp;
-
-	/* Enable RX processing */
-	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
-	temp |= RX_ENABLE;
-	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
-
-	galmpsc_enter_hunt (CHANNEL);
-}
-
-static int galmpsc_set_snoop (int mpsc, int value)
-{
-	int reg =
-		mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
-		MPSC_0_ADDRESS_CONTROL_LOW;
-	int temp = GTREGREAD (reg);
-
-	if (value)
-		temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
-	else
-		temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
-	GT_REG_WRITE (reg, temp);
-	return 0;
-}
-
-/*******************************************************************************
-* galsdma_set_mem_space - Set MV64460 IDMA memory decoding map.
-*
-* DESCRIPTION:
-*       the MV64460 SDMA has its own address decoding map that is de-coupled
-*       from the CPU interface address decoding windows. The SDMA channels
-*       share four address windows. Each region can be individually configured
-*       by this function by associating it to a target interface and setting
-*       base and size values.
-*
-*      NOTE!!!
-*       The size must be in 64Kbyte granularity.
-*       The base address must be aligned to the size.
-*       The size must be a series of 1s followed by a series of zeros
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       true for success, false otherwise.
-*
-*******************************************************************************/
-
-static int galsdma_set_mem_space (unsigned int memSpace,
-				  unsigned int memSpaceTarget,
-				  unsigned int memSpaceAttr,
-				  unsigned int baseAddress, unsigned int size)
-{
-	unsigned int temp;
-
-	if (size == 0) {
-		GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
-				   1 << memSpace);
-		return true;
-	}
-
-	/* The base address must be aligned to the size.  */
-	if (baseAddress % size != 0) {
-		return false;
-	}
-	if (size < 0x10000) {
-		return false;
-	}
-
-	/* Align size and base to 64K */
-	baseAddress &= 0xffff0000;
-	size &= 0xffff0000;
-	temp = size >> 16;
-
-	/* Checking that the size is a sequence of '1' followed by a
-	   sequence of '0' starting from LSB to MSB. */
-	while ((temp > 0) && (temp & 0x1)) {
-		temp = temp >> 1;
-	}
-
-	if (temp != 0) {
-		GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
-			      (baseAddress | memSpaceTarget | memSpaceAttr));
-		GT_REG_WRITE ((MV64460_CUNIT_SIZE0 + memSpace * 8),
-			      (size - 1) & 0xffff0000);
-		GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
-				   1 << memSpace);
-	} else {
-		/* An invalid size was specified */
-		return false;
-	}
-	return true;
-}
diff --git a/board/prodrive/p3mx/mpsc.h b/board/prodrive/p3mx/mpsc.h
deleted file mode 100644
index 241f28a31ab..00000000000
--- a/board/prodrive/p3mx/mpsc.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*************************************************************************
- * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
-  ************************************************************************/
-
-
-/*
- * mpsc.h - header file for MPSC in uart mode (console driver)
- */
-
-#ifndef __MPSC_H__
-#define __MPSC_H__
-
-/* include actual Galileo defines */
-#include "../../Marvell/include/mv_gen_reg.h"
-
-/* driver related defines */
-
-int mpsc_init(int baud);
-void mpsc_sdma_init(void);
-void mpsc_init2(void);
-int galbrg_set_baudrate(int channel, int rate);
-
-int mpsc_putchar_early(char ch);
-char mpsc_getchar_debug(void);
-int mpsc_test_char_debug(void);
-
-int mpsc_test_char_sdma(void);
-
-extern int (*mpsc_putchar)(char ch);
-extern char (*mpsc_getchar)(void);
-extern int (*mpsc_test_char)(void);
-
-#define CHANNEL CONFIG_MPSC_PORT
-
-#define TX_DESC     5
-#define RX_DESC     20
-
-#define DESC_FIRST  0x00010000
-#define DESC_LAST   0x00020000
-#define DESC_OWNER_BIT  0x80000000
-
-#define TX_DEMAND   0x00800000
-#define TX_STOP     0x00010000
-#define RX_ENABLE   0x00000080
-
-#define SDMA_RX_ABORT		  (1 << 15)
-#define SDMA_TX_ABORT		  (1 << 31)
-#define MPSC_TX_ABORT		  (1 << 7)
-#define MPSC_RX_ABORT             (1 << 23)
-#define MPSC_ENTER_HUNT           (1 << 31)
-
-/* MPSC defines */
-
-#define GALMPSC_CONNECT            0x1
-#define GALMPSC_DISCONNECT         0x0
-
-#define GALMPSC_UART               0x1
-
-#define GALMPSC_STOP_BITS_1        0x0
-#define GALMPSC_STOP_BITS_2        0x1
-#define GALMPSC_CHAR_LENGTH_8      0x3
-#define GALMPSC_CHAR_LENGTH_7      0x2
-
-#define GALMPSC_PARITY_ODD         0x0
-#define GALMPSC_PARITY_EVEN        0x2
-#define GALMPSC_PARITY_MARK        0x3
-#define GALMPSC_PARITY_SPACE       0x1
-#define GALMPSC_PARITY_NONE        -1
-
-#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
-#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
-#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
-#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
-#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
-#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
-#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
-
-#define GALMPSC_REG_GAP            0x1000
-
-#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
-#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
-#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
-#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
-#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
-#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
-#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
-#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
-#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
-#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
-#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
-#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
-
-#define GALSDMA_COMMAND_FIRST     (1 << 16)
-#define GALSDMA_COMMAND_LAST      (1 << 17)
-#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
-#define GALSDMA_COMMAND_AUTO      (1 << 30)
-#define GALSDMA_COMMAND_OWNER     (1 << 31)
-
-#define GALSDMA_RX                 0
-#define GALSDMA_TX                 1
-
-/* CHANNEL2 should be CHANNEL1, according to documentation,
- * but to work with the current GTREGS file...
- */
-#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
-#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
-#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
-#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
-#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
-#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
-#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
-#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
-#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
-#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
-#define GALSDMA_REG_DIFF           0x2000
-
-/* WRONG in gt64260R.h */
-#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
-#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
-#define GALMPSC_0_INT_CAUSE        0xb804
-#define GALMPSC_0_INT_MASK         0xb884
-
-#define GALSDMA_MODE_UART          0
-#define GALSDMA_MODE_BISYNC        1
-#define GALSDMA_MODE_HDLC          2
-#define GALSDMA_MODE_TRANSPARENT   3
-
-#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
-#define GALBRG_REG_GAP             0x0008
-#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
-
-#endif /* __MPSC_H__ */
diff --git a/board/prodrive/p3mx/mv_eth.c b/board/prodrive/p3mx/mv_eth.c
deleted file mode 100644
index ebd93c0288e..00000000000
--- a/board/prodrive/p3mx/mv_eth.c
+++ /dev/null
@@ -1,3291 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * mv_eth.c - header file for the polled mode GT ethernet driver
- */
-#include <common.h>
-#include <net.h>
-#include <malloc.h>
-#include <miiphy.h>
-
-#include "mv_eth.h"
-
-/* enable Debug outputs */
-
-#undef DEBUG_MV_ETH
-
-#ifdef DEBUG_MV_ETH
-#define DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-/* PHY DFCDL Registers */
-#define ETH_PHY_DFCDL_CONFIG0_REG	0x2100
-#define ETH_PHY_DFCDL_CONFIG1_REG	0x2104
-#define ETH_PHY_DFCDL_ADDR_REG		0x2110
-#define ETH_PHY_DFCDL_DATA0_REG		0x2114
-
-#define PHY_AUTONEGOTIATE_TIMEOUT	4000	/* 4000 ms autonegotiate timeout */
-#define PHY_UPDATE_TIMEOUT		10000
-
-#undef MV64460_CHECKSUM_OFFLOAD
-/*************************************************************************
-*  The first part is the high level driver of the gigE ethernet ports.	 *
-*************************************************************************/
-
-/* Definition for configuring driver */
-/* #define UPDATE_STATS_BY_SOFTWARE */
-#undef MV64460_RX_QUEUE_FILL_ON_TASK
-
-/* Constants */
-#define MAGIC_ETH_RUNNING		8031971
-#define MV64460_INTERNAL_SRAM_SIZE	_256K
-#define EXTRA_BYTES 32
-#define WRAP	   ETH_HLEN + 2 + 4 + 16
-#define BUFFER_MTU dev->mtu + WRAP
-#define INT_CAUSE_UNMASK_ALL		0x0007ffff
-#define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
-#ifdef MV64460_RX_FILL_ON_TASK
-#define INT_CAUSE_MASK_ALL		0x00000000
-#define INT_CAUSE_CHECK_BITS		INT_CAUSE_UNMASK_ALL
-#define INT_CAUSE_CHECK_BITS_EXT	INT_CAUSE_UNMASK_ALL_EXT
-#endif
-
-/* Read/Write to/from MV64460 internal registers */
-#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
-#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
-#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
-#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
-
-#define my_cpu_to_le32(x) my_le32_to_cpu((x))
-
-/* Static function declarations */
-static int mv64460_eth_real_open (struct eth_device *eth);
-static int mv64460_eth_real_stop (struct eth_device *eth);
-static struct net_device_stats *mv64460_eth_get_stats (struct eth_device
-						       *dev);
-static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
-static void mv64460_eth_update_stat (struct eth_device *dev);
-bool db64460_eth_start (struct eth_device *eth);
-unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
-				   unsigned int mib_offset);
-int mv64460_eth_receive (struct eth_device *dev);
-
-int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length);
-
-int mv_miiphy_read(const char *devname, unsigned char phy_addr,
-		   unsigned char phy_reg, unsigned short *value);
-int mv_miiphy_write(const char *devname, unsigned char phy_addr,
-		    unsigned char phy_reg, unsigned short value);
-
-int phy_setup_aneg (char *devname, unsigned char addr);
-
-#ifndef	 UPDATE_STATS_BY_SOFTWARE
-static void mv64460_eth_print_stat (struct eth_device *dev);
-#endif
-
-extern unsigned int INTERNAL_REG_BASE_ADDR;
-
-unsigned long my_le32_to_cpu (unsigned long x)
-{
-	return (((x & 0x000000ffU) << 24) |
-		((x & 0x0000ff00U) << 8) |
-		((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
-}
-
-/*************************************************
- *Helper functions - used inside the driver only *
- *************************************************/
-#ifdef DEBUG_MV_ETH
-void print_globals (struct eth_device *dev)
-{
-	printf ("Ethernet PRINT_Globals-Debug function\n");
-	printf ("Base Address for ETH_PORT_INFO:	%08x\n",
-		(unsigned int) dev->priv);
-	printf ("Base Address for mv64460_eth_priv:	%08x\n",
-		(unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
-				 port_private));
-
-	printf ("GT Internal Base Address:	%08x\n",
-		INTERNAL_REG_BASE_ADDR);
-	printf ("Base Address for TX-DESCs:	%08x	Number of allocated Buffers %d\n",
-		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE);
-	printf ("Base Address for RX-DESCs:	%08x	Number of allocated Buffers %d\n",
-		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE);
-	printf ("Base Address for RX-Buffer:	%08x	allocated Bytes %d\n",
-		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
-		p_rx_buffer_base[0],
-		(MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32);
-	printf ("Base Address for TX-Buffer:	%08x	allocated Bytes %d\n",
-		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
-		p_tx_buffer_base[0],
-		(MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32);
-}
-#endif
-
-/**********************************************************************
- * mv64460_eth_print_phy_status
- *
- * Prints gigabit ethenret phy status
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-void mv64460_eth_print_phy_status (struct eth_device *dev)
-{
-	struct mv64460_eth_priv *port_private;
-	unsigned int port_num;
-	ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	unsigned int port_status, phy_reg_data;
-
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-	/* Check Link status on phy */
-	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
-	if (!(phy_reg_data & 0x20)) {
-		printf ("Ethernet port changed link status to DOWN\n");
-	} else {
-		port_status =
-			MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
-		printf ("Ethernet status port %d: Link up", port_num);
-		printf (", %s",
-			(port_status & BIT2) ? "Full Duplex" : "Half Duplex");
-		if (port_status & BIT4)
-			printf (", Speed 1 Gbps");
-		else
-			printf (", %s",
-				(port_status & BIT5) ? "Speed 100 Mbps" :
-				"Speed 10 Mbps");
-		printf ("\n");
-	}
-}
-
-/**********************************************************************
- * u-boot entry functions for mv64460_eth
- *
- **********************************************************************/
-int db64460_eth_probe (struct eth_device *dev)
-{
-	return ((int) db64460_eth_start (dev));
-}
-
-int db64460_eth_poll (struct eth_device *dev)
-{
-	return mv64460_eth_receive (dev);
-}
-
-int db64460_eth_transmit(struct eth_device *dev, void *packet, int length)
-{
-	mv64460_eth_xmit (dev, packet, length);
-	return 0;
-}
-
-void db64460_eth_disable (struct eth_device *dev)
-{
-	mv64460_eth_stop (dev);
-}
-
-#define DFCDL(write,read)   ((write << 6) | read)
-unsigned int  ethDfcdls[] = {
-	DFCDL(0,0),	DFCDL(1,1),	DFCDL(2,2),	DFCDL(3,3),
-	DFCDL(4,4),	DFCDL(5,5),	DFCDL(6,6),	DFCDL(7,7),
-	DFCDL(8,8),	DFCDL(9,9),	DFCDL(10,10),	DFCDL(11,11),
-	DFCDL(12,12),	DFCDL(13,13),	DFCDL(14,14),	DFCDL(15,15),
-	DFCDL(16,16),	DFCDL(17,17),	DFCDL(18,18),	DFCDL(19,19),
-	DFCDL(20,20),	DFCDL(21,21),	DFCDL(22,22),	DFCDL(23,23),
-	DFCDL(24,24),	DFCDL(25,25),	DFCDL(26,26),	DFCDL(27,27),
-	DFCDL(28,28),	DFCDL(29,29),	DFCDL(30,30),	DFCDL(31,31),
-	DFCDL(32,32),	DFCDL(33,33),	DFCDL(34,34),	DFCDL(35,35),
-	DFCDL(36,36),	DFCDL(37,37),	DFCDL(38,38),	DFCDL(39,39),
-	DFCDL(40,40),	DFCDL(41,41),	DFCDL(42,42),	DFCDL(43,43),
-	DFCDL(44,44),	DFCDL(45,45),	DFCDL(46,46),	DFCDL(47,47),
-	DFCDL(48,48),	DFCDL(49,49),	DFCDL(50,50),	DFCDL(51,51),
-	DFCDL(52,52),	DFCDL(53,53),	DFCDL(54,54),	DFCDL(55,55),
-	DFCDL(56,56),	DFCDL(57,57),	DFCDL(58,58),	DFCDL(59,59),
-	DFCDL(60,60),	DFCDL(61,61),	DFCDL(62,62),	DFCDL(63,63),
-};
-
-void mv_eth_phy_init (void)
-{
-	int i;
-
-	MV_REG_WRITE (ETH_PHY_DFCDL_ADDR_REG, 0);
-
-	for (i = 0; i < 64; i++) {
-		MV_REG_WRITE (ETH_PHY_DFCDL_DATA0_REG, ethDfcdls[i]);
-	}
-
-	MV_REG_WRITE (ETH_PHY_DFCDL_CONFIG0_REG, 0x300000);
-}
-
-void mv6446x_eth_initialize (bd_t * bis)
-{
-	struct eth_device *dev;
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	int devnum, x, temp;
-	char *s, *e, buf[64];
-
-	/* P3M750 only
-	 * Set RGMII clock drives strength
-	 */
-	temp = MV_REG_READ(0x20A0);
-	temp |= 0x04000080;
-	MV_REG_WRITE(0x20A0, temp);
-
-	mv_eth_phy_init();
-
-	for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
-		dev = calloc (sizeof (*dev), 1);
-		if (!dev) {
-			printf ("%s: mv_enet%d allocation failure, %s\n",
-				__FUNCTION__, devnum, "eth_device structure");
-			return;
-		}
-
-		/* must be less than sizeof(dev->name) */
-		sprintf (dev->name, "mv_enet%d", devnum);
-
-#ifdef DEBUG
-		printf ("Initializing %s\n", dev->name);
-#endif
-
-		/* Extract the MAC address from the environment */
-		switch (devnum) {
-		case 0:
-			s = "ethaddr";
-			break;
-		case 1:
-			s = "eth1addr";
-			break;
-		case 2:
-			s = "eth2addr";
-			break;
-		default:	/* this should never happen */
-			printf ("%s: Invalid device number %d\n",
-				__FUNCTION__, devnum);
-			return;
-		}
-
-		temp = getenv_f(s, buf, sizeof (buf));
-		s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
-		printf ("Setting MAC %d to %s\n", devnum, s);
-#endif
-		for (x = 0; x < 6; ++x) {
-			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
-			if (s)
-				s = (*e) ? e + 1 : e;
-		}
-		/* ronen - set the MAC addr in the HW */
-		eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
-
-		dev->init = (void *) db64460_eth_probe;
-		dev->halt = (void *) ethernet_phy_reset;
-		dev->send = (void *) db64460_eth_transmit;
-		dev->recv = (void *) db64460_eth_poll;
-
-		ethernet_private = calloc (sizeof (*ethernet_private), 1);
-		dev->priv = (void *)ethernet_private;
-		if (!ethernet_private) {
-			printf ("%s: %s allocation failure, %s\n",
-				__FUNCTION__, dev->name,
-				"Private Device Structure");
-			free (dev);
-			return;
-		}
-		/* start with an zeroed ETH_PORT_INFO */
-		memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
-		memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
-
-		/* set pointer to memory for stats data structure etc... */
-		port_private = calloc (sizeof (*ethernet_private), 1);
-		ethernet_private->port_private = (void *)port_private;
-		if (!port_private) {
-			printf ("%s: %s allocation failure, %s\n",
-				__FUNCTION__, dev->name,
-				"Port Private Device Structure");
-
-			free (ethernet_private);
-			free (dev);
-			return;
-		}
-
-		port_private->stats =
-			calloc (sizeof (struct net_device_stats), 1);
-		if (!port_private->stats) {
-			printf ("%s: %s allocation failure, %s\n",
-				__FUNCTION__, dev->name,
-				"Net stat Structure");
-
-			free (port_private);
-			free (ethernet_private);
-			free (dev);
-			return;
-		}
-		memset (ethernet_private->port_private, 0,
-			sizeof (struct mv64460_eth_priv));
-		switch (devnum) {
-		case 0:
-			ethernet_private->port_num = ETH_0;
-			break;
-		case 1:
-			ethernet_private->port_num = ETH_1;
-			break;
-		case 2:
-			ethernet_private->port_num = ETH_2;
-			break;
-		default:
-			printf ("Invalid device number %d\n", devnum);
-			break;
-		};
-
-		port_private->port_num = devnum;
-		/*
-		 * Read MIB counter on the GT in order to reset them,
-		 * then zero all the stats fields in memory
-		 */
-		mv64460_eth_update_stat (dev);
-		memset (port_private->stats, 0,
-			sizeof (struct net_device_stats));
-		/* Extract the MAC address from the environment */
-		switch (devnum) {
-		case 0:
-			s = "ethaddr";
-			break;
-		case 1:
-			s = "eth1addr";
-			break;
-		case 2:
-			s = "eth2addr";
-			break;
-		default:	/* this should never happen */
-			printf ("%s: Invalid device number %d\n",
-				__FUNCTION__, devnum);
-			return;
-		}
-
-		temp = getenv_f(s, buf, sizeof (buf));
-		s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
-		printf ("Setting MAC %d to %s\n", devnum, s);
-#endif
-		for (x = 0; x < 6; ++x) {
-			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
-			if (s)
-				s = (*e) ? e + 1 : e;
-		}
-
-		DP (printf ("Allocating descriptor and buffer rings\n"));
-
-		ethernet_private->p_rx_desc_area_base[0] =
-			(ETH_RX_DESC *) memalign (16,
-						  RX_DESC_ALIGNED_SIZE *
-						  MV64460_RX_QUEUE_SIZE + 1);
-		ethernet_private->p_tx_desc_area_base[0] =
-			(ETH_TX_DESC *) memalign (16,
-						  TX_DESC_ALIGNED_SIZE *
-						  MV64460_TX_QUEUE_SIZE + 1);
-
-		ethernet_private->p_rx_buffer_base[0] =
-			(char *) memalign (16,
-					   MV64460_RX_QUEUE_SIZE *
-					   MV64460_TX_BUFFER_SIZE + 1);
-		ethernet_private->p_tx_buffer_base[0] =
-			(char *) memalign (16,
-					   MV64460_RX_QUEUE_SIZE *
-					   MV64460_TX_BUFFER_SIZE + 1);
-
-#ifdef DEBUG_MV_ETH
-		/* DEBUG OUTPUT prints adresses of globals */
-		print_globals (dev);
-#endif
-		eth_register (dev);
-
-		miiphy_register(dev->name, mv_miiphy_read, mv_miiphy_write);
-	}
-	DP (printf ("%s: exit\n", __FUNCTION__));
-
-}
-
-/**********************************************************************
- * mv64460_eth_open
- *
- * This function is called when openning the network device. The function
- * should initialize all the hardware, initialize cyclic Rx/Tx
- * descriptors chain and buffers and allocate an IRQ to the network
- * device.
- *
- * Input : a pointer to the network device structure
- * / / ronen - changed the output to match  net/eth.c needs
- * Output : nonzero of success , zero if fails.
- * under construction
- **********************************************************************/
-
-int mv64460_eth_open (struct eth_device *dev)
-{
-	return (mv64460_eth_real_open (dev));
-}
-
-/* Helper function for mv64460_eth_open */
-static int mv64460_eth_real_open (struct eth_device *dev)
-{
-
-	unsigned int queue;
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	unsigned int port_num;
-	ushort reg_short;
-	int speed;
-	int duplex;
-	int i;
-	int reg;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	/* ronen - when we update the MAC env params we only update dev->enetaddr
-	   see ./net/eth.c eth_set_enetaddr() */
-	memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
-
-	port_private = (struct mv64460_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-	/* Stop RX Queues */
-	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), 0x0000ff00);
-
-	/* Clear the ethernet port interrupts */
-	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
-	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
-
-	/* Unmask RX buffer and TX end interrupt */
-	MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num),
-		      INT_CAUSE_UNMASK_ALL);
-
-	/* Unmask phy and link status changes interrupts */
-	MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
-		      INT_CAUSE_UNMASK_ALL_EXT);
-
-	/* Set phy address of the port */
-	ethernet_private->port_phy_addr = 0x1 + (port_num << 1);
-	reg = ethernet_private->port_phy_addr;
-
-	/* Activate the DMA channels etc */
-	eth_port_init (ethernet_private);
-
-	/* "Allocate" setup TX rings */
-
-	for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
-		unsigned int size;
-
-		port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE;
-		size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE);	/*size = no of DESCs times DESC-size */
-		ethernet_private->tx_desc_area_size[queue] = size;
-
-		/* first clear desc area completely */
-		memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
-			0, ethernet_private->tx_desc_area_size[queue]);
-
-		/* initialize tx desc ring with low level driver */
-		if (ether_init_tx_desc_ring
-		    (ethernet_private, ETH_Q0,
-		     port_private->tx_ring_size[queue],
-		     MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
-		     (unsigned int) ethernet_private->
-		     p_tx_desc_area_base[queue],
-		     (unsigned int) ethernet_private->
-		     p_tx_buffer_base[queue]) == false)
-			printf ("### Error initializing TX Ring\n");
-	}
-
-	/* "Allocate" setup RX rings */
-	for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
-		unsigned int size;
-
-		/* Meantime RX Ring are fixed - but must be configurable by user */
-		port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE;
-		size = (port_private->rx_ring_size[queue] *
-			RX_DESC_ALIGNED_SIZE);
-		ethernet_private->rx_desc_area_size[queue] = size;
-
-		/* first clear desc area completely */
-		memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
-			0, ethernet_private->rx_desc_area_size[queue]);
-		if ((ether_init_rx_desc_ring
-		     (ethernet_private, ETH_Q0,
-		      port_private->rx_ring_size[queue],
-		      MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
-		      (unsigned int) ethernet_private->
-		      p_rx_desc_area_base[queue],
-		      (unsigned int) ethernet_private->
-		      p_rx_buffer_base[queue])) == false)
-			printf ("### Error initializing RX Ring\n");
-	}
-
-	eth_port_start (ethernet_private);
-
-	/* Set maximum receive buffer to 9700 bytes */
-	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num),
-		      (0x5 << 17) |
-		      (MV_REG_READ
-		       (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num))
-		       & 0xfff1ffff));
-
-	/*
-	 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
-	 * disable the leaky bucket mechanism .
-	 */
-
-	MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
-	MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
-
-#if defined(CONFIG_PHY_RESET)
-	/*
-	 * Reset the phy, only if its the first time through
-	 * otherwise, just check the speeds & feeds
-	 */
-	if (port_private->first_init == 0) {
-		port_private->first_init = 1;
-		ethernet_phy_reset (port_num);
-
-		/* Start/Restart autonegotiation */
-		phy_setup_aneg (dev->name, reg);
-		udelay (1000);
-	}
-#endif /* defined(CONFIG_PHY_RESET) */
-
-	miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
-
-	/*
-	 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
-	 */
-	if ((reg_short & BMSR_ANEGCAPABLE)
-	    && !(reg_short & BMSR_ANEGCOMPLETE)) {
-		puts ("Waiting for PHY auto negotiation to complete");
-		i = 0;
-		while (!(reg_short & BMSR_ANEGCOMPLETE)) {
-			/*
-			 * Timeout reached ?
-			 */
-			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
-				puts (" TIMEOUT !\n");
-				break;
-			}
-
-			if ((i++ % 1000) == 0) {
-				putc ('.');
-			}
-			udelay (1000);	/* 1 ms */
-			miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
-
-		}
-		puts (" done\n");
-		udelay (500000);	/* another 500 ms (results in faster booting) */
-	}
-
-	speed = miiphy_speed (dev->name, reg);
-	duplex = miiphy_duplex (dev->name, reg);
-
-	printf ("ENET Speed is %d Mbps - %s duplex connection\n",
-		(int) speed, (duplex == HALF) ? "HALF" : "FULL");
-
-	port_private->eth_running = MAGIC_ETH_RUNNING;
-	return 1;
-}
-
-static int mv64460_eth_free_tx_rings (struct eth_device *dev)
-{
-	unsigned int queue;
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	unsigned int port_num;
-	volatile ETH_TX_DESC *p_tx_curr_desc;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-	/* Stop Tx Queues */
-	MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
-		      0x0000ff00);
-
-	/* Free TX rings */
-	DP (printf ("Clearing previously allocated TX queues... "));
-	for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
-		/* Free on TX rings */
-		for (p_tx_curr_desc =
-		     ethernet_private->p_tx_desc_area_base[queue];
-		     ((unsigned int) p_tx_curr_desc <= (unsigned int)
-		      ethernet_private->p_tx_desc_area_base[queue] +
-		      ethernet_private->tx_desc_area_size[queue]);
-		     p_tx_curr_desc =
-		     (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
-				      TX_DESC_ALIGNED_SIZE)) {
-			/* this is inside for loop */
-			if (p_tx_curr_desc->return_info != 0) {
-				p_tx_curr_desc->return_info = 0;
-				DP (printf ("freed\n"));
-			}
-		}
-		DP (printf ("Done\n"));
-	}
-	return 0;
-}
-
-static int mv64460_eth_free_rx_rings (struct eth_device *dev)
-{
-	unsigned int queue;
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	unsigned int port_num;
-	volatile ETH_RX_DESC *p_rx_curr_desc;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-	/* Stop RX Queues */
-	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
-		      0x0000ff00);
-
-	/* Free RX rings */
-	DP (printf ("Clearing previously allocated RX queues... "));
-	for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
-		/* Free preallocated skb's on RX rings */
-		for (p_rx_curr_desc =
-		     ethernet_private->p_rx_desc_area_base[queue];
-		     (((unsigned int) p_rx_curr_desc <
-		       ((unsigned int) ethernet_private->
-			p_rx_desc_area_base[queue] +
-			ethernet_private->rx_desc_area_size[queue])));
-		     p_rx_curr_desc =
-		     (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
-				      RX_DESC_ALIGNED_SIZE)) {
-			if (p_rx_curr_desc->return_info != 0) {
-				p_rx_curr_desc->return_info = 0;
-				DP (printf ("freed\n"));
-			}
-		}
-		DP (printf ("Done\n"));
-	}
-	return 0;
-}
-
-/**********************************************************************
- * mv64460_eth_stop
- *
- * This function is used when closing the network device.
- * It updates the hardware,
- * release all memory that holds buffers and descriptors and release the IRQ.
- * Input : a pointer to the device structure
- * Output : zero if success , nonzero if fails
- *********************************************************************/
-
-int mv64460_eth_stop (struct eth_device *dev)
-{
-	/* Disable all gigE address decoder */
-	MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
-	DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
-	mv64460_eth_real_stop (dev);
-
-	return 0;
-};
-
-/* Helper function for mv64460_eth_stop */
-
-static int mv64460_eth_real_stop (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	unsigned int port_num;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-	port_num = port_private->port_num;
-
-	mv64460_eth_free_tx_rings (dev);
-	mv64460_eth_free_rx_rings (dev);
-
-	eth_port_reset (ethernet_private->port_num);
-	/* Disable ethernet port interrupts */
-	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
-	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
-	/* Mask RX buffer and TX end interrupt */
-	MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0);
-	/* Mask phy and link status changes interrupts */
-	MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
-	MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH,
-			   BIT0 << port_num);
-	/* Print Network statistics */
-#ifndef	 UPDATE_STATS_BY_SOFTWARE
-	/*
-	 * Print statistics (only if ethernet is running),
-	 * then zero all the stats fields in memory
-	 */
-	if (port_private->eth_running == MAGIC_ETH_RUNNING) {
-		port_private->eth_running = 0;
-		mv64460_eth_print_stat (dev);
-	}
-	memset (port_private->stats, 0, sizeof (struct net_device_stats));
-#endif
-	DP (printf ("\nEthernet stopped ... \n"));
-	return 0;
-}
-
-/**********************************************************************
- * mv64460_eth_start_xmit
- *
- * This function is queues a packet in the Tx descriptor for
- * required port.
- *
- * Input : skb - a pointer to socket buffer
- *	   dev - a pointer to the required port
- *
- * Output : zero upon success
- **********************************************************************/
-
-int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
-		      int dataSize)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	PKT_INFO pkt_info;
-	ETH_FUNC_RET_STATUS status;
-	struct net_device_stats *stats;
-	ETH_FUNC_RET_STATUS release_result;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-
-	stats = port_private->stats;
-
-	/* Update packet info data structure */
-	pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;	/* DMA owned, first last */
-	pkt_info.byte_cnt = dataSize;
-	pkt_info.buf_ptr = (unsigned int) dataPtr;
-	pkt_info.return_info = 0;
-
-	status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
-	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
-		printf ("Error on transmitting packet ..");
-		if (status == ETH_QUEUE_FULL)
-			printf ("ETH Queue is full. \n");
-		if (status == ETH_QUEUE_LAST_RESOURCE)
-			printf ("ETH Queue: using last available resource. \n");
-		return 1;
-	}
-
-	/* Update statistics and start of transmittion time */
-	stats->tx_bytes += dataSize;
-	stats->tx_packets++;
-
-	/* Check if packet(s) is(are) transmitted correctly (release everything) */
-	do {
-		release_result =
-			eth_tx_return_desc (ethernet_private, ETH_Q0,
-					    &pkt_info);
-		switch (release_result) {
-		case ETH_OK:
-			DP (printf ("descriptor released\n"));
-			if (pkt_info.cmd_sts & BIT0) {
-				printf ("Error in TX\n");
-				stats->tx_errors++;
-			}
-			break;
-		case ETH_RETRY:
-			DP (printf ("transmission still in process\n"));
-			break;
-
-		case ETH_ERROR:
-			printf ("routine can not access Tx desc ring\n");
-			break;
-
-		case ETH_END_OF_JOB:
-			DP (printf ("the routine has nothing to release\n"));
-			break;
-		default:	/* should not happen */
-			break;
-		}
-	} while (release_result == ETH_OK);
-
-	return 0;	/* success */
-}
-
-/**********************************************************************
- * mv64460_eth_receive
- *
- * This function is forward packets that are received from the port's
- * queues toward kernel core or FastRoute them to another interface.
- *
- * Input : dev - a pointer to the required interface
- *	   max - maximum number to receive (0 means unlimted)
- *
- * Output : number of served packets
- **********************************************************************/
-
-int mv64460_eth_receive (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	PKT_INFO pkt_info;
-	struct net_device_stats *stats;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private = (struct mv64460_eth_priv *) ethernet_private->port_private;
-	stats = port_private->stats;
-
-	while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == ETH_OK)) {
-#ifdef DEBUG_MV_ETH
-		if (pkt_info.byte_cnt != 0) {
-			printf ("%s: Received %d byte Packet @ 0x%x\n",
-				__FUNCTION__, pkt_info.byte_cnt,
-				pkt_info.buf_ptr);
-			if(pkt_info.buf_ptr != 0){
-				for(i=0; i < pkt_info.byte_cnt; i++){
-					if((i % 4) == 0){
-						printf("\n0x");
-					}
-					printf("%02x", ((char*)pkt_info.buf_ptr)[i]);
-				}
-				printf("\n");
-			}
-		}
-#endif
-		/* Update statistics. Note byte count includes 4 byte CRC count */
-		stats->rx_packets++;
-		stats->rx_bytes += pkt_info.byte_cnt;
-
-		/*
-		 * In case received a packet without first / last bits on OR the error
-		 * summary bit is on, the packets needs to be dropeed.
-		 */
-		if (((pkt_info.
-		      cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
-		     (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
-		    || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
-			stats->rx_dropped++;
-
-			printf ("Received packet spread on multiple descriptors\n");
-
-			/* Is this caused by an error ? */
-			if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
-				stats->rx_errors++;
-			}
-
-			/* free these descriptors again without forwarding them to the higher layers */
-			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
-			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
-
-			if (eth_rx_return_buff
-			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
-				printf ("Error while returning the RX Desc to Ring\n");
-			} else {
-				DP (printf ("RX Desc returned to Ring\n"));
-			}
-			/* /free these descriptors again */
-		} else {
-
-/* !!! call higher layer processing */
-#ifdef DEBUG_MV_ETH
-			printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
-#endif
-			/* let the upper layer handle the packet */
-			NetReceive ((uchar *) pkt_info.buf_ptr,
-				    (int) pkt_info.byte_cnt);
-
-/* **************************************************************** */
-/* free descriptor  */
-			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
-			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
-			DP (printf ("RX: pkt_info.buf_ptr =	%x\n", pkt_info.buf_ptr));
-			if (eth_rx_return_buff
-			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
-				printf ("Error while returning the RX Desc to Ring\n");
-			} else {
-				DP (printf ("RX: Desc returned to Ring\n"));
-			}
-
-/* **************************************************************** */
-
-		}
-	}
-	mv64460_eth_get_stats (dev);	/* update statistics */
-	return 1;
-}
-
-/**********************************************************************
- * mv64460_eth_get_stats
- *
- * Returns a pointer to the interface statistics.
- *
- * Input : dev - a pointer to the required interface
- *
- * Output : a pointer to the interface's statistics
- **********************************************************************/
-
-static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-
-	mv64460_eth_update_stat (dev);
-
-	return port_private->stats;
-}
-
-/**********************************************************************
- * mv64460_eth_update_stat
- *
- * Update the statistics structure in the private data structure
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64460_eth_update_stat (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	struct net_device_stats *stats;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-	stats = port_private->stats;
-
-	/* These are false updates */
-	stats->rx_packets += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_FRAMES_RECEIVED);
-	stats->tx_packets += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_FRAMES_SENT);
-	stats->rx_bytes += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
-	/*
-	 * Ideally this should be as follows -
-	 *
-	 *   stats->rx_bytes   += stats->rx_bytes +
-	 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
-	 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
-	 *
-	 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
-	 * is just a dummy read for proper work of the GigE port
-	 */
-	(void)eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
-	stats->tx_bytes += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_OCTETS_SENT_LOW);
-	(void)eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_GOOD_OCTETS_SENT_HIGH);
-	stats->rx_errors += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_MAC_RECEIVE_ERROR);
-
-	/* Rx dropped is for received packet with CRC error */
-	stats->rx_dropped +=
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_BAD_CRC_EVENT);
-	stats->multicast += (unsigned long)
-		eth_read_mib_counter (ethernet_private->port_num,
-				      ETH_MIB_MULTICAST_FRAMES_RECEIVED);
-	stats->collisions +=
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_COLLISION) +
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_LATE_COLLISION);
-	/* detailed rx errors */
-	stats->rx_length_errors +=
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_UNDERSIZE_RECEIVED)
-		+
-		(unsigned long) eth_read_mib_counter (ethernet_private->
-						      port_num,
-						      ETH_MIB_OVERSIZE_RECEIVED);
-	/* detailed tx errors */
-}
-
-#ifndef	 UPDATE_STATS_BY_SOFTWARE
-/**********************************************************************
- * mv64460_eth_print_stat
- *
- * Update the statistics structure in the private data structure
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64460_eth_print_stat (struct eth_device *dev)
-{
-	ETH_PORT_INFO *ethernet_private;
-	struct mv64460_eth_priv *port_private;
-	struct net_device_stats *stats;
-
-	ethernet_private = (ETH_PORT_INFO *) dev->priv;
-	port_private =
-		(struct mv64460_eth_priv *) ethernet_private->port_private;
-	stats = port_private->stats;
-
-	/* These are false updates */
-	printf ("\n### Network statistics: ###\n");
-	printf ("--------------------------\n");
-	printf (" Packets received:		%ld\n", stats->rx_packets);
-	printf (" Packets send:			%ld\n", stats->tx_packets);
-	printf (" Received bytes:		%ld\n", stats->rx_bytes);
-	printf (" Send bytes:			%ld\n", stats->tx_bytes);
-	if (stats->rx_errors != 0)
-		printf (" Rx Errors:			%ld\n",
-			stats->rx_errors);
-	if (stats->rx_dropped != 0)
-		printf (" Rx dropped (CRC Errors):	%ld\n",
-			stats->rx_dropped);
-	if (stats->multicast != 0)
-		printf (" Rx mulicast frames:		%ld\n",
-			stats->multicast);
-	if (stats->collisions != 0)
-		printf (" No. of collisions:		%ld\n",
-			stats->collisions);
-	if (stats->rx_length_errors != 0)
-		printf (" Rx length errors:		%ld\n",
-			stats->rx_length_errors);
-}
-#endif
-
-/**************************************************************************
- *network_start - Network Kick Off Routine UBoot
- *Inputs :
- *Outputs :
- **************************************************************************/
-
-bool db64460_eth_start (struct eth_device *dev)
-{
-	return (mv64460_eth_open (dev));	/* calls real open */
-}
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The second part is the low level driver of the gigE ethernet ports.	 *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-/*
- * based on Linux code
- * arch/powerpc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
-
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/********************************************************************************
- * Marvell's Gigabit Ethernet controller low level driver
- *
- * DESCRIPTION:
- *	 This file introduce low level API to Marvell's Gigabit Ethernet
- *		controller. This Gigabit Ethernet Controller driver API controls
- *		1) Operations (i.e. port init, start, reset etc').
- *		2) Data flow (i.e. port send, receive etc').
- *		Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
- *		struct.
- *		This struct includes user configuration information as well as
- *		driver internal data needed for its operations.
- *
- *		Supported Features:
- *		- This low level driver is OS independent. Allocating memory for
- *		  the descriptor rings and buffers are not within the scope of
- *		  this driver.
- *		- The user is free from Rx/Tx queue managing.
- *		- This low level driver introduce functionality API that enable
- *		  the to operate Marvell's Gigabit Ethernet Controller in a
- *		  convenient way.
- *		- Simple Gigabit Ethernet port operation API.
- *		- Simple Gigabit Ethernet port data flow API.
- *		- Data flow and operation API support per queue functionality.
- *		- Support cached descriptors for better performance.
- *		- Enable access to all four DRAM banks and internal SRAM memory
- *		  spaces.
- *		- PHY access and control API.
- *		- Port control register configuration API.
- *		- Full control over Unicast and Multicast MAC configurations.
- *
- *		Operation flow:
- *
- *		Initialization phase
- *		This phase complete the initialization of the ETH_PORT_INFO
- *		struct.
- *		User information regarding port configuration has to be set
- *		prior to calling the port initialization routine. For example,
- *		the user has to assign the port_phy_addr field which is board
- *		depended parameter.
- *		In this phase any port Tx/Rx activity is halted, MIB counters
- *		are cleared, PHY address is set according to user parameter and
- *		access to DRAM and internal SRAM memory spaces.
- *
- *		Driver ring initialization
- *		Allocating memory for the descriptor rings and buffers is not
- *		within the scope of this driver. Thus, the user is required to
- *		allocate memory for the descriptors ring and buffers. Those
- *		memory parameters are used by the Rx and Tx ring initialization
- *		routines in order to curve the descriptor linked list in a form
- *		of a ring.
- *		Note: Pay special attention to alignment issues when using
- *		cached descriptors/buffers. In this phase the driver store
- *		information in the ETH_PORT_INFO struct regarding each queue
- *		ring.
- *
- *		Driver start
- *		This phase prepares the Ethernet port for Rx and Tx activity.
- *		It uses the information stored in the ETH_PORT_INFO struct to
- *		initialize the various port registers.
- *
- *		Data flow:
- *		All packet references to/from the driver are done using PKT_INFO
- *		struct.
- *		This struct is a unified struct used with Rx and Tx operations.
- *		This way the user is not required to be familiar with neither
- *		Tx nor Rx descriptors structures.
- *		The driver's descriptors rings are management by indexes.
- *		Those indexes controls the ring resources and used to indicate
- *		a SW resource error:
- *		'current'
- *		This index points to the current available resource for use. For
- *		example in Rx process this index will point to the descriptor
- *		that will be passed to the user upon calling the receive routine.
- *		In Tx process, this index will point to the descriptor
- *		that will be assigned with the user packet info and transmitted.
- *		'used'
- *		This index points to the descriptor that need to restore its
- *		resources. For example in Rx process, using the Rx buffer return
- *		API will attach the buffer returned in packet info to the
- *		descriptor pointed by 'used'. In Tx process, using the Tx
- *		descriptor return will merely return the user packet info with
- *		the command status of  the transmitted buffer pointed by the
- *		'used' index. Nevertheless, it is essential to use this routine
- *		to update the 'used' index.
- *		'first'
- *		This index supports Tx Scatter-Gather. It points to the first
- *		descriptor of a packet assembled of multiple buffers. For example
- *		when in middle of Such packet we have a Tx resource error the
- *		'curr' index get the value of 'first' to indicate that the ring
- *		returned to its state before trying to transmit this packet.
- *
- *		Receive operation:
- *		The eth_port_receive API set the packet information struct,
- *		passed by the caller, with received information from the
- *		'current' SDMA descriptor.
- *		It is the user responsibility to return this resource back
- *		to the Rx descriptor ring to enable the reuse of this source.
- *		Return Rx resource is done using the eth_rx_return_buff API.
- *
- *		Transmit operation:
- *		The eth_port_send API supports Scatter-Gather which enables to
- *		send a packet spanned over multiple buffers. This means that
- *		for each packet info structure given by the user and put into
- *		the Tx descriptors ring, will be transmitted only if the 'LAST'
- *		bit will be set in the packet info command status field. This
- *		API also consider restriction regarding buffer alignments and
- *		sizes.
- *		The user must return a Tx resource after ensuring the buffer
- *		has been transmitted to enable the Tx ring indexes to update.
- *
- *		BOARD LAYOUT
- *		This device is on-board.  No jumper diagram is necessary.
- *
- *		EXTERNAL INTERFACE
- *
- *	 Prior to calling the initialization routine eth_port_init() the user
- *	 must set the following fields under ETH_PORT_INFO struct:
- *	 port_num	      User Ethernet port number.
- *	 port_phy_addr		    User PHY address of Ethernet port.
- *	 port_mac_addr[6]	    User defined port MAC address.
- *	 port_config	      User port configuration value.
- *	 port_config_extend    User port config extend value.
- *	 port_sdma_config      User port SDMA config value.
- *	 port_serial_control   User port serial control value.
- *	 *port_virt_to_phys ()	User function to cast virtual addr to CPU bus addr.
- *	 *port_private	      User scratch pad for user specific data structures.
- *
- *	 This driver introduce a set of default values:
- *	 PORT_CONFIG_VALUE	     Default port configuration value
- *	 PORT_CONFIG_EXTEND_VALUE    Default port extend configuration value
- *	 PORT_SDMA_CONFIG_VALUE	     Default sdma control value
- *	 PORT_SERIAL_CONTROL_VALUE   Default port serial control value
- *
- *		This driver data flow is done using the PKT_INFO struct which is
- *		a unified struct for Rx and Tx operations:
- *		byte_cnt	Tx/Rx descriptor buffer byte count.
- *		l4i_chk		CPU provided TCP Checksum. For Tx operation only.
- *		cmd_sts		Tx/Rx descriptor command status.
- *		buf_ptr		Tx/Rx descriptor buffer pointer.
- *		return_info	Tx/Rx user resource return information.
- *
- *
- *		EXTERNAL SUPPORT REQUIREMENTS
- *
- *		This driver requires the following external support:
- *
- *		D_CACHE_FLUSH_LINE (address, address offset)
- *
- *		This macro applies assembly code to flush and invalidate cache
- *		line.
- *		address	       - address base.
- *		address offset - address offset
- *
- *
- *		CPU_PIPE_FLUSH
- *
- *		This macro applies assembly code to flush the CPU pipeline.
- *
- *******************************************************************************/
-/* includes */
-
-/* defines */
-/* SDMA command macros */
-#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
- MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
-
-#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
- MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
- (1 << (8 + tx_queue)))
-
-#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
-MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
-
-#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
-MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
-
-#define CURR_RFD_GET(p_curr_desc, queue) \
- ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
-
-#define CURR_RFD_SET(p_curr_desc, queue) \
- (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
-
-#define USED_RFD_GET(p_used_desc, queue) \
- ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
-
-#define USED_RFD_SET(p_used_desc, queue)\
-(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
-
-
-#define CURR_TFD_GET(p_curr_desc, queue) \
- ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
-
-#define CURR_TFD_SET(p_curr_desc, queue) \
- (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
-
-#define USED_TFD_GET(p_used_desc, queue) \
- ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
-
-#define USED_TFD_SET(p_used_desc, queue) \
- (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
-
-#define FIRST_TFD_GET(p_first_desc, queue) \
- ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
-
-#define FIRST_TFD_SET(p_first_desc, queue) \
- (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
-
-
-/* Macros that save access to desc in order to find next desc pointer  */
-#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
-
-#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
-
-#define LINK_UP_TIMEOUT		100000
-#define PHY_BUSY_TIMEOUT    10000000
-
-/* locals */
-
-/* PHY routines */
-static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
-static int ethernet_phy_get (ETH_PORT eth_port_num);
-
-/* Ethernet Port routines */
-static void eth_set_access_control (ETH_PORT eth_port_num,
-				    ETH_WIN_PARAM * param);
-static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
-			      ETH_QUEUE queue, int option);
-#if 0				/* FIXME */
-static bool eth_port_smc_addr (ETH_PORT eth_port_num,
-			       unsigned char mc_byte,
-			       ETH_QUEUE queue, int option);
-static bool eth_port_omc_addr (ETH_PORT eth_port_num,
-			       unsigned char crc8,
-			       ETH_QUEUE queue, int option);
-#endif
-
-static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
-			int byte_count);
-
-void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
-
-
-typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
-u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
-{
-	u32 result = 0;
-	u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
-
-	if (enable & (1 << bank))
-		return 0;
-	if (bank == BANK0)
-		result = MV_REG_READ (MV64460_CS_0_BASE_ADDR);
-	if (bank == BANK1)
-		result = MV_REG_READ (MV64460_CS_1_BASE_ADDR);
-	if (bank == BANK2)
-		result = MV_REG_READ (MV64460_CS_2_BASE_ADDR);
-	if (bank == BANK3)
-		result = MV_REG_READ (MV64460_CS_3_BASE_ADDR);
-	result &= 0x0000ffff;
-	result = result << 16;
-	return result;
-}
-
-u32 mv_get_dram_bank_size (MEMORY_BANK bank)
-{
-	u32 result = 0;
-	u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
-
-	if (enable & (1 << bank))
-		return 0;
-	if (bank == BANK0)
-		result = MV_REG_READ (MV64460_CS_0_SIZE);
-	if (bank == BANK1)
-		result = MV_REG_READ (MV64460_CS_1_SIZE);
-	if (bank == BANK2)
-		result = MV_REG_READ (MV64460_CS_2_SIZE);
-	if (bank == BANK3)
-		result = MV_REG_READ (MV64460_CS_3_SIZE);
-	result += 1;
-	result &= 0x0000ffff;
-	result = result << 16;
-	return result;
-}
-
-u32 mv_get_internal_sram_base (void)
-{
-	u32 result;
-
-	result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR);
-	result &= 0x0000ffff;
-	result = result << 16;
-	return result;
-}
-
-/*******************************************************************************
-* eth_port_init - Initialize the Ethernet port driver
-*
-* DESCRIPTION:
-*	This function prepares the ethernet port to start its activity:
-*	1) Completes the ethernet port driver struct initialization toward port
-*	    start routine.
-*	2) Resets the device to a quiescent state in case of warm reboot.
-*	3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
-*	4) Clean MAC tables. The reset status of those tables is unknown.
-*	5) Set PHY address.
-*	Note: Call this routine prior to eth_port_start routine and after setting
-*	user values in the user fields of Ethernet port control struct (i.e.
-*	port_phy_addr).
-*
-* INPUT:
-*	ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
-*
-* OUTPUT:
-*	See description.
-*
-* RETURN:
-*	None.
-*
-*******************************************************************************/
-static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
-{
-	int queue;
-	ETH_WIN_PARAM win_param;
-
-	p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
-	p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
-	p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
-	p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
-
-	p_eth_port_ctrl->port_rx_queue_command = 0;
-	p_eth_port_ctrl->port_tx_queue_command = 0;
-
-	/* Zero out SW structs */
-	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
-		CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
-		USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
-		p_eth_port_ctrl->rx_resource_err[queue] = false;
-	}
-
-	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
-		CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
-		USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
-		FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
-		p_eth_port_ctrl->tx_resource_err[queue] = false;
-	}
-
-	eth_port_reset (p_eth_port_ctrl->port_num);
-
-	/* Set access parameters for DRAM bank 0 */
-	win_param.win = ETH_WIN0;	/* Use Ethernet window 0 */
-	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR	*/
-	win_param.attributes = EBAR_ATTR_DRAM_CS0;	/* Enable DRAM bank   */
-#ifndef CONFIG_NOT_COHERENT_CACHE
-	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
-	win_param.high_addr = 0;
-	/* Get bank base */
-	win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
-	win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
-	if (win_param.size == 0)
-		win_param.enable = 0;
-	else
-		win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	/* Set access parameters for DRAM bank 1 */
-	win_param.win = ETH_WIN1;	/* Use Ethernet window 1 */
-	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
-	win_param.attributes = EBAR_ATTR_DRAM_CS1;	/* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
-	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
-	win_param.high_addr = 0;
-	/* Get bank base */
-	win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
-	win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
-	if (win_param.size == 0)
-		win_param.enable = 0;
-	else
-		win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	/* Set access parameters for DRAM bank 2 */
-	win_param.win = ETH_WIN2;	/* Use Ethernet window 2 */
-	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
-	win_param.attributes = EBAR_ATTR_DRAM_CS2;	/* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
-	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
-	win_param.high_addr = 0;
-	/* Get bank base */
-	win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
-	win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
-	if (win_param.size == 0)
-		win_param.enable = 0;
-	else
-		win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	/* Set access parameters for DRAM bank 3 */
-	win_param.win = ETH_WIN3;	/* Use Ethernet window 3 */
-	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
-	win_param.attributes = EBAR_ATTR_DRAM_CS3;	/* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
-	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
-	win_param.high_addr = 0;
-	/* Get bank base */
-	win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
-	win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
-	if (win_param.size == 0)
-		win_param.enable = 0;
-	else
-		win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	/* Set access parameters for Internal SRAM */
-	win_param.win = ETH_WIN4;	/* Use Ethernet window 0 */
-	win_param.target = EBAR_TARGET_CBS;	/* Target - Internal SRAM */
-	win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
-	win_param.high_addr = 0;
-	win_param.base_addr = mv_get_internal_sram_base ();	/* Get base addr */
-	win_param.size = MV64460_INTERNAL_SRAM_SIZE;	/* Get bank size */
-	win_param.enable = 1;	/* Enable the access */
-	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
-
-	/* Set the access control for address window (EPAPR) READ & WRITE */
-	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
-	eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
-
-	ethernet_phy_set (p_eth_port_ctrl->port_num,
-			  p_eth_port_ctrl->port_phy_addr);
-
-	return;
-
-}
-
-/*******************************************************************************
-* eth_port_start - Start the Ethernet port activity.
-*
-* DESCRIPTION:
-*	This routine prepares the Ethernet port for Rx and Tx activity:
-*	1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
-*	    has been initialized a descriptor's ring (using ether_init_tx_desc_ring
-*	    for Tx and ether_init_rx_desc_ring for Rx)
-*	2. Initialize and enable the Ethernet configuration port by writing to
-*	    the port's configuration and command registers.
-*	3. Initialize and enable the SDMA by writing to the SDMA's
-*    configuration and command registers.
-*	After completing these steps, the ethernet port SDMA can starts to
-*	perform Rx and Tx activities.
-*
-*	Note: Each Rx and Tx queue descriptor's list must be initialized prior
-*	to calling this function (use ether_init_tx_desc_ring for Tx queues and
-*	ether_init_rx_desc_ring for Rx queues).
-*
-* INPUT:
-*	ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
-*
-* OUTPUT:
-*	Ethernet port is ready to receive and transmit.
-*
-* RETURN:
-*	false if the port PHY is not up.
-*	true otherwise.
-*
-*******************************************************************************/
-static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
-{
-	int queue;
-	volatile ETH_TX_DESC *p_tx_curr_desc;
-	volatile ETH_RX_DESC *p_rx_curr_desc;
-	unsigned int phy_reg_data;
-	ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
-
-	/* Assignment of Tx CTRP of given queue */
-	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
-		CURR_TFD_GET (p_tx_curr_desc, queue);
-		MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
-			       (eth_port_num)
-			       + (4 * queue)),
-			      ((unsigned int) p_tx_curr_desc));
-
-	}
-
-	/* Assignment of Rx CRDP of given queue */
-	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
-		CURR_RFD_GET (p_rx_curr_desc, queue);
-		MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
-			       (eth_port_num)
-			       + (4 * queue)),
-			      ((unsigned int) p_rx_curr_desc));
-
-		if (p_rx_curr_desc != NULL)
-			/* Add the assigned Ethernet address to the port's address table */
-			eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
-					      p_eth_port_ctrl->port_mac_addr,
-					      queue);
-	}
-
-	/* Assign port configuration and command. */
-	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
-		      p_eth_port_ctrl->port_config);
-
-	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
-		      p_eth_port_ctrl->port_config_extend);
-
-	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
-		      p_eth_port_ctrl->port_serial_control);
-
-	MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
-			 ETH_SERIAL_PORT_ENABLE);
-
-	/* Assign port SDMA configuration */
-	MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
-		      p_eth_port_ctrl->port_sdma_config);
-
-	MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
-		      (eth_port_num), 0x3fffffff);
-	MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
-		      (eth_port_num), 0x03fffcff);
-	/* Turn off the port/queue bandwidth limitation */
-	MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
-
-	/* Enable port Rx. */
-	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
-		      p_eth_port_ctrl->port_rx_queue_command);
-
-	/* Check if link is up */
-	eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
-
-	if (!(phy_reg_data & 0x20))
-		return false;
-
-	return true;
-}
-
-/*******************************************************************************
-* eth_port_uc_addr_set - This function Set the port Unicast address.
-*
-* DESCRIPTION:
-*		This function Set the port Ethernet MAC address.
-*
-* INPUT:
-*	ETH_PORT eth_port_num	  Port number.
-*	char *	      p_addr		Address to be set
-*	ETH_QUEUE	  queue		Rx queue number for this MAC address.
-*
-* OUTPUT:
-*	Set MAC address low and high registers. also calls eth_port_uc_addr()
-*	To set the unicast table with the proper information.
-*
-* RETURN:
-*	N/A.
-*
-*******************************************************************************/
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
-				  unsigned char *p_addr, ETH_QUEUE queue)
-{
-	unsigned int mac_h;
-	unsigned int mac_l;
-
-	mac_l = (p_addr[4] << 8) | (p_addr[5]);
-	mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
-		(p_addr[2] << 8) | (p_addr[3] << 0);
-
-	MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
-	MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
-
-	/* Accept frames of this address */
-	eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
-
-	return;
-}
-
-/*******************************************************************************
-* eth_port_uc_addr - This function Set the port unicast address table
-*
-* DESCRIPTION:
-*	This function locates the proper entry in the Unicast table for the
-*	specified MAC nibble and sets its properties according to function
-*	parameters.
-*
-* INPUT:
-*	ETH_PORT	eth_port_num	  Port number.
-*	unsigned char uc_nibble		Unicast MAC Address last nibble.
-*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
-*	int			option	    0 = Add, 1 = remove address.
-*
-* OUTPUT:
-*	This function add/removes MAC addresses from the port unicast address
-*	table.
-*
-* RETURN:
-*	true is output succeeded.
-*	false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_uc_addr (ETH_PORT eth_port_num,
-			      unsigned char uc_nibble,
-			      ETH_QUEUE queue, int option)
-{
-	unsigned int unicast_reg;
-	unsigned int tbl_offset;
-	unsigned int reg_offset;
-
-	/* Locate the Unicast table entry */
-	uc_nibble = (0xf & uc_nibble);
-	tbl_offset = (uc_nibble / 4) * 4;	/* Register offset from unicast table base */
-	reg_offset = uc_nibble % 4;	/* Entry offset within the above register */
-
-	switch (option) {
-	case REJECT_MAC_ADDR:
-		/* Clear accepts frame bit at specified unicast DA table entry */
-		unicast_reg =
-			MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
-				      (eth_port_num)
-				      + tbl_offset));
-
-		unicast_reg &= (0x0E << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
-			       (eth_port_num)
-			       + tbl_offset), unicast_reg);
-		break;
-
-	case ACCEPT_MAC_ADDR:
-		/* Set accepts frame bit at unicast DA filter table entry */
-		unicast_reg =
-			MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
-				      (eth_port_num)
-				      + tbl_offset));
-
-		unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
-			       (eth_port_num)
-			       + tbl_offset), unicast_reg);
-
-		break;
-
-	default:
-		return false;
-	}
-	return true;
-}
-
-#if 0				/* FIXME */
-/*******************************************************************************
-* eth_port_mc_addr - Multicast address settings.
-*
-* DESCRIPTION:
-*	This API controls the MV device MAC multicast support.
-*	The MV device supports multicast using two tables:
-*	1) Special Multicast Table for MAC addresses of the form
-*	   0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
-*	   The MAC DA[7:0] bits are used as a pointer to the Special Multicast
-*	   Table entries in the DA-Filter table.
-*	   In this case, the function calls eth_port_smc_addr() routine to set the
-*	   Special Multicast Table.
-*	2) Other Multicast Table for multicast of another type. A CRC-8bit
-*	   is used as an index to the Other Multicast Table entries in the
-*	   DA-Filter table.
-*	   In this case, the function calculates the CRC-8bit value and calls
-*	   eth_port_omc_addr() routine to set the Other Multicast Table.
-* INPUT:
-*	ETH_PORT	eth_port_num	  Port number.
-*	unsigned char	*p_addr		Unicast MAC Address.
-*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
-*	int			option	    0 = Add, 1 = remove address.
-*
-* OUTPUT:
-*	See description.
-*
-* RETURN:
-*	true is output succeeded.
-*	false if add_address_table_entry( ) failed.
-*
-*******************************************************************************/
-static void eth_port_mc_addr (ETH_PORT eth_port_num,
-			      unsigned char *p_addr,
-			      ETH_QUEUE queue, int option)
-{
-	unsigned int mac_h;
-	unsigned int mac_l;
-	unsigned char crc_result = 0;
-	int mac_array[48];
-	int crc[8];
-	int i;
-
-	if ((p_addr[0] == 0x01) &&
-	    (p_addr[1] == 0x00) &&
-	    (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
-
-		eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
-	} else {
-		/* Calculate CRC-8 out of the given address */
-		mac_h = (p_addr[0] << 8) | (p_addr[1]);
-		mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
-			(p_addr[4] << 8) | (p_addr[5] << 0);
-
-		for (i = 0; i < 32; i++)
-			mac_array[i] = (mac_l >> i) & 0x1;
-		for (i = 32; i < 48; i++)
-			mac_array[i] = (mac_h >> (i - 32)) & 0x1;
-
-		crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
-			mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
-			mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
-			mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
-			mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
-			mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
-			mac_array[6] ^ mac_array[0];
-
-		crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
-			mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
-			mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
-			mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
-			mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
-			mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
-			mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
-			mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
-			mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
-			mac_array[0];
-
-		crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
-			mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
-			mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
-			mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
-			mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
-			mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
-			mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
-			mac_array[2] ^ mac_array[1] ^ mac_array[0];
-
-		crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
-			mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
-			mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
-			mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
-			mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
-			mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
-			mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
-			mac_array[2] ^ mac_array[1];
-
-		crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
-			mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
-			mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
-			mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
-			mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
-			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
-			mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
-			mac_array[2];
-
-		crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
-			mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
-			mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
-			mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
-			mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
-			mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
-			mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
-			mac_array[3];
-
-		crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
-			mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
-			mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
-			mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
-			mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
-			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
-			mac_array[6] ^ mac_array[5] ^ mac_array[4];
-
-		crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
-			mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
-			mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
-			mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
-			mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
-			mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
-			mac_array[6] ^ mac_array[5];
-
-		for (i = 0; i < 8; i++)
-			crc_result = crc_result | (crc[i] << i);
-
-		eth_port_omc_addr (eth_port_num, crc_result, queue, option);
-	}
-	return;
-}
-
-/*******************************************************************************
-* eth_port_smc_addr - Special Multicast address settings.
-*
-* DESCRIPTION:
-*	This routine controls the MV device special MAC multicast support.
-*	The Special Multicast Table for MAC addresses supports MAC of the form
-*	0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
-*	The MAC DA[7:0] bits are used as a pointer to the Special Multicast
-*	Table entries in the DA-Filter table.
-*	This function set the Special Multicast Table appropriate entry
-*	according to the argument given.
-*
-* INPUT:
-*	ETH_PORT	eth_port_num	  Port number.
-*	unsigned char	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
-*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
-*	int			option	    0 = Add, 1 = remove address.
-*
-* OUTPUT:
-*	See description.
-*
-* RETURN:
-*	true is output succeeded.
-*	false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_smc_addr (ETH_PORT eth_port_num,
-			       unsigned char mc_byte,
-			       ETH_QUEUE queue, int option)
-{
-	unsigned int smc_table_reg;
-	unsigned int tbl_offset;
-	unsigned int reg_offset;
-
-	/* Locate the SMC table entry */
-	tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
-	reg_offset = mc_byte % 4;	/* Entry offset within the above register */
-	queue &= 0x7;
-
-	switch (option) {
-	case REJECT_MAC_ADDR:
-		/* Clear accepts frame bit at specified Special DA table entry */
-		smc_table_reg =
-			MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
-		smc_table_reg &= (0x0E << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
-		break;
-
-	case ACCEPT_MAC_ADDR:
-		/* Set accepts frame bit at specified Special DA table entry */
-		smc_table_reg =
-			MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
-		smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
-		break;
-
-	default:
-		return false;
-	}
-	return true;
-}
-
-/*******************************************************************************
-* eth_port_omc_addr - Multicast address settings.
-*
-* DESCRIPTION:
-*	This routine controls the MV device Other MAC multicast support.
-*	The Other Multicast Table is used for multicast of another type.
-*	A CRC-8bit is used as an index to the Other Multicast Table entries
-*	in the DA-Filter table.
-*	The function gets the CRC-8bit value from the calling routine and
-*      set the Other Multicast Table appropriate entry according to the
-*	CRC-8 argument given.
-*
-* INPUT:
-*	ETH_PORT	eth_port_num	  Port number.
-*	unsigned char	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
-*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
-*	int			option	    0 = Add, 1 = remove address.
-*
-* OUTPUT:
-*	See description.
-*
-* RETURN:
-*	true is output succeeded.
-*	false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_omc_addr (ETH_PORT eth_port_num,
-			       unsigned char crc8,
-			       ETH_QUEUE queue, int option)
-{
-	unsigned int omc_table_reg;
-	unsigned int tbl_offset;
-	unsigned int reg_offset;
-
-	/* Locate the OMC table entry */
-	tbl_offset = (crc8 / 4) * 4;	/* Register offset from OMC table base */
-	reg_offset = crc8 % 4;	/* Entry offset within the above register */
-	queue &= 0x7;
-
-	switch (option) {
-	case REJECT_MAC_ADDR:
-		/* Clear accepts frame bit at specified Other DA table entry */
-		omc_table_reg =
-			MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
-		omc_table_reg &= (0x0E << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
-		break;
-
-	case ACCEPT_MAC_ADDR:
-		/* Set accepts frame bit at specified Other DA table entry */
-		omc_table_reg =
-			MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
-		omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
-
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
-		break;
-
-	default:
-		return false;
-	}
-	return true;
-}
-#endif
-
-/*******************************************************************************
-* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
-*
-* DESCRIPTION:
-*	Go through all the DA filter tables (Unicast, Special Multicast & Other
-*	Multicast) and set each entry to 0.
-*
-* INPUT:
-*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-*	Multicast and Unicast packets are rejected.
-*
-* RETURN:
-*	None.
-*
-*******************************************************************************/
-static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
-{
-	int table_index;
-
-	/* Clear DA filter unicast table (Ex_dFUT) */
-	for (table_index = 0; table_index <= 0xC; table_index += 4)
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
-			       (eth_port_num) + table_index), 0);
-
-	for (table_index = 0; table_index <= 0xFC; table_index += 4) {
-		/* Clear DA filter special multicast table (Ex_dFSMT) */
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
-		/* Clear DA filter other multicast table (Ex_dFOMT) */
-		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
-	}
-}
-
-/*******************************************************************************
-* eth_clear_mib_counters - Clear all MIB counters
-*
-* DESCRIPTION:
-*	This function clears all MIB counters of a specific ethernet port.
-*	A read from the MIB counter will reset the counter.
-*
-* INPUT:
-*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-*	After reading all MIB counters, the counters resets.
-*
-* RETURN:
-*	MIB counter value.
-*
-*******************************************************************************/
-static void eth_clear_mib_counters (ETH_PORT eth_port_num)
-{
-	int i;
-
-	/* Perform dummy reads from MIB counters */
-	for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
-	     i += 4) {
-		(void)MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE
-				      (eth_port_num) + i));
-	}
-
-	return;
-}
-
-/*******************************************************************************
-* eth_read_mib_counter - Read a MIB counter
-*
-* DESCRIPTION:
-*	This function reads a MIB counter of a specific ethernet port.
-*	NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
-*	following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
-*	register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
-*	ETH_MIB_GOOD_OCTETS_SENT_HIGH
-*
-* INPUT:
-*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
-*	unsigned int mib_offset	  MIB counter offset (use ETH_MIB_... macros).
-*
-* OUTPUT:
-*	After reading the MIB counter, the counter resets.
-*
-* RETURN:
-*	MIB counter value.
-*
-*******************************************************************************/
-unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
-				   unsigned int mib_offset)
-{
-	return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num)
-			     + mib_offset));
-}
-
-/*******************************************************************************
-* ethernet_phy_set - Set the ethernet port PHY address.
-*
-* DESCRIPTION:
-*	This routine set the ethernet port PHY address according to given
-*	parameter.
-*
-* INPUT:
-*		ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-*	Set PHY Address Register with given PHY address parameter.
-*
-* RETURN:
-*	None.
-*
-*******************************************************************************/
-static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
-{
-	unsigned int reg_data;
-
-	reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
-
-	reg_data &= ~(0x1F << (5 * eth_port_num));
-	reg_data |= (phy_addr << (5 * eth_port_num));
-
-	MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data);
-
-	return;
-}
-
-/*******************************************************************************
- * ethernet_phy_get - Get the ethernet port PHY address.
- *
- * DESCRIPTION:
- *	 This routine returns the given ethernet port PHY address.
- *
- * INPUT:
- *		ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- *	 None.
- *
- * RETURN:
- *	 PHY address.
- *
- *******************************************************************************/
-static int ethernet_phy_get (ETH_PORT eth_port_num)
-{
-	unsigned int reg_data;
-
-	reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
-
-	return ((reg_data >> (5 * eth_port_num)) & 0x1f);
-}
-
-/***********************************************************/
-/* (Re)start autonegotiation				   */
-/***********************************************************/
-int phy_setup_aneg (char *devname, unsigned char addr)
-{
-	unsigned short ctl, adv;
-
-	/* Setup standard advertise */
-	miiphy_read (devname, addr, MII_ADVERTISE, &adv);
-	adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 |
-		LPA_100FULL | LPA_100HALF | LPA_10FULL |
-		LPA_10HALF);
-	miiphy_write (devname, addr, MII_ADVERTISE, adv);
-
-	miiphy_read (devname, addr, MII_CTRL1000, &adv);
-	adv |= (0x0300);
-	miiphy_write (devname, addr, MII_CTRL1000, adv);
-
-	/* Start/Restart aneg */
-	miiphy_read (devname, addr, MII_BMCR, &ctl);
-	ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
-	miiphy_write (devname, addr, MII_BMCR, ctl);
-
-	return 0;
-}
-
-/*******************************************************************************
- * ethernet_phy_reset - Reset Ethernet port PHY.
- *
- * DESCRIPTION:
- *	 This routine utilize the SMI interface to reset the ethernet port PHY.
- *	 The routine waits until the link is up again or link up is timeout.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- *	 The ethernet port PHY renew its link.
- *
- * RETURN:
- *	 None.
- *
- *******************************************************************************/
-static bool ethernet_phy_reset (ETH_PORT eth_port_num)
-{
-	unsigned int time_out = 50;
-	unsigned int phy_reg_data;
-
-	eth_port_read_smi_reg (eth_port_num, 20, &phy_reg_data);
-	phy_reg_data |= 0x0083; /* Set bit 7 to 1 for different RGMII timing */
-	eth_port_write_smi_reg (eth_port_num, 20, phy_reg_data);
-
-	/* Reset the PHY */
-	eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
-	phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
-	eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
-
-	/* Poll on the PHY LINK */
-	do {
-		eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
-
-		if (time_out-- == 0)
-			return false;
-	}
-	while (!(phy_reg_data & 0x20));
-
-	return true;
-}
-
-/*******************************************************************************
- * eth_port_reset - Reset Ethernet port
- *
- * DESCRIPTION:
- *	This routine resets the chip by aborting any SDMA engine activity and
- *	clearing the MIB counters. The Receiver and the Transmit unit are in
- *	idle state after this command is performed and the port is disabled.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- *	 Channel activity is halted.
- *
- * RETURN:
- *	 None.
- *
- *******************************************************************************/
-static void eth_port_reset (ETH_PORT eth_port_num)
-{
-	unsigned int reg_data;
-
-	/* Stop Tx port activity. Check port Tx activity. */
-	reg_data =
-		MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
-			     (eth_port_num));
-
-	if (reg_data & 0xFF) {
-		/* Issue stop command for active channels only */
-		MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
-			      (eth_port_num), (reg_data << 8));
-
-		/* Wait for all Tx activity to terminate. */
-		do {
-			/* Check port cause register that all Tx queues are stopped */
-			reg_data =
-				MV_REG_READ
-				(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
-				 (eth_port_num));
-		}
-		while (reg_data & 0xFF);
-	}
-
-	/* Stop Rx port activity. Check port Rx activity. */
-	reg_data =
-		MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
-			     (eth_port_num));
-
-	if (reg_data & 0xFF) {
-		/* Issue stop command for active channels only */
-		MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
-			      (eth_port_num), (reg_data << 8));
-
-		/* Wait for all Rx activity to terminate. */
-		do {
-			/* Check port cause register that all Rx queues are stopped */
-			reg_data =
-				MV_REG_READ
-				(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
-				 (eth_port_num));
-		}
-		while (reg_data & 0xFF);
-	}
-
-	/* Clear all MIB counters */
-	eth_clear_mib_counters (eth_port_num);
-
-	/* Reset the Enable bit in the Configuration Register */
-	reg_data =
-		MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG
-			     (eth_port_num));
-	reg_data &= ~ETH_SERIAL_PORT_ENABLE;
-	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
-		      reg_data);
-
-	return;
-}
-
-#if 0				/* Not needed here */
-/*******************************************************************************
- * ethernet_set_config_reg - Set specified bits in configuration register.
- *
- * DESCRIPTION:
- *	 This function sets specified bits in the given ethernet
- *	 configuration register.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
- *	unsigned int	value	32 bit value.
- *
- * OUTPUT:
- *	The set bits in the value parameter are set in the configuration
- *	register.
- *
- * RETURN:
- *	None.
- *
- *******************************************************************************/
-static void ethernet_set_config_reg (ETH_PORT eth_port_num,
-				     unsigned int value)
-{
-	unsigned int eth_config_reg;
-
-	eth_config_reg =
-		MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num));
-	eth_config_reg |= value;
-	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
-		      eth_config_reg);
-
-	return;
-}
-#endif
-
-#if 0				/* FIXME */
-/*******************************************************************************
- * ethernet_reset_config_reg - Reset specified bits in configuration register.
- *
- * DESCRIPTION:
- *	 This function resets specified bits in the given Ethernet
- *	 configuration register.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
- *	unsigned int	value	32 bit value.
- *
- * OUTPUT:
- *	The set bits in the value parameter are reset in the configuration
- *	register.
- *
- * RETURN:
- *	None.
- *
- *******************************************************************************/
-static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
-				       unsigned int value)
-{
-	unsigned int eth_config_reg;
-
-	eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
-				      (eth_port_num));
-	eth_config_reg &= ~value;
-	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
-		      eth_config_reg);
-
-	return;
-}
-#endif
-
-#if 0				/* Not needed here */
-/*******************************************************************************
- * ethernet_get_config_reg - Get the port configuration register
- *
- * DESCRIPTION:
- *	 This function returns the configuration register value of the given
- *	 ethernet port.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- *	 None.
- *
- * RETURN:
- *	 Port configuration register value.
- *
- *******************************************************************************/
-static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
-{
-	unsigned int eth_config_reg;
-
-	eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
-				      (eth_port_num));
-	return eth_config_reg;
-}
-
-#endif
-
-/*******************************************************************************
- * eth_port_read_smi_reg - Read PHY registers
- *
- * DESCRIPTION:
- *	 This routine utilize the SMI interface to interact with the PHY in
- *	 order to perform PHY register read.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
- *	 unsigned int	phy_reg	  PHY register address offset.
- *	 unsigned int	*value	 Register value buffer.
- *
- * OUTPUT:
- *	 Write the value of a specified PHY register into given buffer.
- *
- * RETURN:
- *	 false if the PHY is busy or read data is not in valid state.
- *	 true otherwise.
- *
- *******************************************************************************/
-static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
-				   unsigned int phy_reg, unsigned int *value)
-{
-	unsigned int reg_value;
-	unsigned int time_out = PHY_BUSY_TIMEOUT;
-	int phy_addr;
-
-	phy_addr = ethernet_phy_get (eth_port_num);
-
-	/* first check that it is not busy */
-	do {
-		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
-		if (time_out-- == 0) {
-			return false;
-		}
-	}
-	while (reg_value & ETH_SMI_BUSY);
-
-	/* not busy */
-
-	MV_REG_WRITE (MV64460_ETH_SMI_REG,
-		      (phy_addr << 16) | (phy_reg << 21) |
-		      ETH_SMI_OPCODE_READ);
-
-	time_out = PHY_BUSY_TIMEOUT;	/* initialize the time out var again */
-
-	do {
-		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
-		if (time_out-- == 0) {
-			return false;
-		}
-	}
-	while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
-
-	/* Wait for the data to update in the SMI register */
-#define PHY_UPDATE_TIMEOUT	10000
-	for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
-
-	reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
-
-	*value = reg_value & 0xffff;
-
-	return true;
-}
-
-int mv_miiphy_read(const char *devname, unsigned char phy_addr,
-		   unsigned char phy_reg, unsigned short *value)
-{
-	unsigned int reg_value;
-	unsigned int time_out = PHY_BUSY_TIMEOUT;
-
-	/* first check that it is not busy */
-	do {
-		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
-		if (time_out-- == 0) {
-			return false;
-		}
-	}
-	while (reg_value & ETH_SMI_BUSY);
-
-	/* not busy */
-	MV_REG_WRITE (MV64460_ETH_SMI_REG,
-		      (phy_addr << 16) | (phy_reg << 21) |
-		      ETH_SMI_OPCODE_READ);
-
-	time_out = PHY_BUSY_TIMEOUT;	/* initialize the time out var again */
-
-	do {
-		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
-		if (time_out-- == 0) {
-			return false;
-		}
-	}
-	while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
-
-	/* Wait for the data to update in the SMI register */
-	for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
-
-	reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
-
-	*value = reg_value & 0xffff;
-
-	return 0;
-}
-
-/*******************************************************************************
- * eth_port_write_smi_reg - Write to PHY registers
- *
- * DESCRIPTION:
- *	 This routine utilize the SMI interface to interact with the PHY in
- *	 order to perform writes to PHY registers.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
- *	unsigned int   phy_reg	 PHY register address offset.
- *	unsigned int	value	Register value.
- *
- * OUTPUT:
- *	Write the given value to the specified PHY register.
- *
- * RETURN:
- *	false if the PHY is busy.
- *	true otherwise.
- *
- *******************************************************************************/
-static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
-				    unsigned int phy_reg, unsigned int value)
-{
-	unsigned int reg_value;
-	unsigned int time_out = PHY_BUSY_TIMEOUT;
-	int phy_addr;
-
-	phy_addr = ethernet_phy_get (eth_port_num);
-
-	/* first check that it is not busy */
-	do {
-		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
-		if (time_out-- == 0) {
-			return false;
-		}
-	}
-	while (reg_value & ETH_SMI_BUSY);
-
-	/* not busy */
-	MV_REG_WRITE (MV64460_ETH_SMI_REG,
-		      (phy_addr << 16) | (phy_reg << 21) |
-		      ETH_SMI_OPCODE_WRITE | (value & 0xffff));
-	return true;
-}
-
-int mv_miiphy_write(const char *devname, unsigned char phy_addr,
-		    unsigned char phy_reg, unsigned short value)
-{
-	unsigned int reg_value;
-	unsigned int time_out = PHY_BUSY_TIMEOUT;
-
-	/* first check that it is not busy */
-	do {
-		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
-		if (time_out-- == 0) {
-			return false;
-		}
-	}
-	while (reg_value & ETH_SMI_BUSY);
-
-	/* not busy */
-	MV_REG_WRITE (MV64460_ETH_SMI_REG,
-		      (phy_addr << 16) | (phy_reg << 21) |
-		      ETH_SMI_OPCODE_WRITE | (value & 0xffff));
-	return 0;
-}
-
-/*******************************************************************************
- * eth_set_access_control - Config address decode parameters for Ethernet unit
- *
- * DESCRIPTION:
- *	 This function configures the address decode parameters for the Gigabit
- *	 Ethernet Controller according the given parameters struct.
- *
- * INPUT:
- *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
- *	 ETH_WIN_PARAM	*param	 Address decode parameter struct.
- *
- * OUTPUT:
- *	 An access window is opened using the given access parameters.
- *
- * RETURN:
- *	 None.
- *
- *******************************************************************************/
-static void eth_set_access_control (ETH_PORT eth_port_num,
-				    ETH_WIN_PARAM * param)
-{
-	unsigned int access_prot_reg;
-
-	/* Set access control register */
-	access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG
-				       (eth_port_num));
-	access_prot_reg &= (~(3 << (param->win * 2)));	/* clear window permission */
-	access_prot_reg |= (param->access_ctrl << (param->win * 2));
-	MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num),
-		      access_prot_reg);
-
-	/* Set window Size reg (SR) */
-	MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 +
-		       (ETH_SIZE_REG_GAP * param->win)),
-		      (((param->size / 0x10000) - 1) << 16));
-
-	/* Set window Base address reg (BA) */
-	MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
-		      (param->target | param->attributes | param->base_addr));
-	/* High address remap reg (HARR) */
-	if (param->win < 4)
-		MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 +
-			       (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
-			      param->high_addr);
-
-	/* Base address enable reg (BARER) */
-	if (param->enable == 1)
-		MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
-				   (1 << param->win));
-	else
-		MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
-				 (1 << param->win));
-}
-
-/*******************************************************************************
- * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
- *
- * DESCRIPTION:
- *	 This function prepares a Rx chained list of descriptors and packet
- *	 buffers in a form of a ring. The routine must be called after port
- *	 initialization routine and before port start routine.
- *	 The Ethernet SDMA engine uses CPU bus addresses to access the various
- *	 devices in the system (i.e. DRAM). This function uses the ethernet
- *	 struct 'virtual to physical' routine (set by the user) to set the ring
- *	 with physical addresses.
- *
- * INPUT:
- *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	rx_queue	 Number of Rx queue.
- *	int			rx_desc_num	  Number of Rx descriptors
- *	int			rx_buff_size	  Size of Rx buffer
- *	unsigned int	rx_desc_base_addr  Rx descriptors memory area base addr.
- *	unsigned int	rx_buff_base_addr  Rx buffer memory area base addr.
- *
- * OUTPUT:
- *	The routine updates the Ethernet port control struct with information
- *	regarding the Rx descriptors and buffers.
- *
- * RETURN:
- *	false if the given descriptors memory area is not aligned according to
- *	Ethernet SDMA specifications.
- *	true otherwise.
- *
- *******************************************************************************/
-static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
-				     ETH_QUEUE rx_queue,
-				     int rx_desc_num,
-				     int rx_buff_size,
-				     unsigned int rx_desc_base_addr,
-				     unsigned int rx_buff_base_addr)
-{
-	ETH_RX_DESC *p_rx_desc;
-	ETH_RX_DESC *p_rx_prev_desc;	/* pointer to link with the last descriptor */
-	unsigned int buffer_addr;
-	int ix;			/* a counter */
-
-	p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
-	p_rx_prev_desc = p_rx_desc;
-	buffer_addr = rx_buff_base_addr;
-
-	/* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
-	if (rx_buff_base_addr & 0xF)
-		return false;
-
-	/* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
-	if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
-		return false;
-
-	/* Rx buffers must be 64-bit aligned.	    */
-	if ((rx_buff_base_addr + rx_buff_size) & 0x7)
-		return false;
-
-	/* initialize the Rx descriptors ring */
-	for (ix = 0; ix < rx_desc_num; ix++) {
-		p_rx_desc->buf_size = rx_buff_size;
-		p_rx_desc->byte_cnt = 0x0000;
-		p_rx_desc->cmd_sts =
-			ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
-		p_rx_desc->next_desc_ptr =
-			((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
-		p_rx_desc->buf_ptr = buffer_addr;
-		p_rx_desc->return_info = 0x00000000;
-		D_CACHE_FLUSH_LINE (p_rx_desc, 0);
-		buffer_addr += rx_buff_size;
-		p_rx_prev_desc = p_rx_desc;
-		p_rx_desc = (ETH_RX_DESC *)
-			((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
-	}
-
-	/* Closing Rx descriptors ring */
-	p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
-	D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
-
-	/* Save Rx desc pointer to driver struct. */
-	CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
-	USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
-
-	p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
-		(ETH_RX_DESC *) rx_desc_base_addr;
-	p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
-		rx_desc_num * RX_DESC_ALIGNED_SIZE;
-
-	p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
-
-	return true;
-}
-
-/*******************************************************************************
- * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
- *
- * DESCRIPTION:
- *	 This function prepares a Tx chained list of descriptors and packet
- *	 buffers in a form of a ring. The routine must be called after port
- *	 initialization routine and before port start routine.
- *	 The Ethernet SDMA engine uses CPU bus addresses to access the various
- *	 devices in the system (i.e. DRAM). This function uses the ethernet
- *	 struct 'virtual to physical' routine (set by the user) to set the ring
- *	 with physical addresses.
- *
- * INPUT:
- *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	tx_queue	 Number of Tx queue.
- *	int			tx_desc_num	  Number of Tx descriptors
- *	int			tx_buff_size	  Size of Tx buffer
- *	unsigned int	tx_desc_base_addr  Tx descriptors memory area base addr.
- *	unsigned int	tx_buff_base_addr  Tx buffer memory area base addr.
- *
- * OUTPUT:
- *	The routine updates the Ethernet port control struct with information
- *	regarding the Tx descriptors and buffers.
- *
- * RETURN:
- *	false if the given descriptors memory area is not aligned according to
- *	Ethernet SDMA specifications.
- *	true otherwise.
- *
- *******************************************************************************/
-static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
-				     ETH_QUEUE tx_queue,
-				     int tx_desc_num,
-				     int tx_buff_size,
-				     unsigned int tx_desc_base_addr,
-				     unsigned int tx_buff_base_addr)
-{
-
-	ETH_TX_DESC *p_tx_desc;
-	ETH_TX_DESC *p_tx_prev_desc;
-	unsigned int buffer_addr;
-	int ix;			/* a counter */
-
-	/* save the first desc pointer to link with the last descriptor */
-	p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
-	p_tx_prev_desc = p_tx_desc;
-	buffer_addr = tx_buff_base_addr;
-
-	/* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
-	if (tx_buff_base_addr & 0xF)
-		return false;
-
-	/* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
-	if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
-	    || (tx_buff_size < TX_BUFFER_MIN_SIZE))
-		return false;
-
-	/* Initialize the Tx descriptors ring */
-	for (ix = 0; ix < tx_desc_num; ix++) {
-		p_tx_desc->byte_cnt = 0x0000;
-		p_tx_desc->l4i_chk = 0x0000;
-		p_tx_desc->cmd_sts = 0x00000000;
-		p_tx_desc->next_desc_ptr =
-			((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
-
-		p_tx_desc->buf_ptr = buffer_addr;
-		p_tx_desc->return_info = 0x00000000;
-		D_CACHE_FLUSH_LINE (p_tx_desc, 0);
-		buffer_addr += tx_buff_size;
-		p_tx_prev_desc = p_tx_desc;
-		p_tx_desc = (ETH_TX_DESC *)
-			((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
-
-	}
-	/* Closing Tx descriptors ring */
-	p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
-	D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
-	/* Set Tx desc pointer in driver struct. */
-	CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
-	USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
-
-	/* Init Tx ring base and size parameters */
-	p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
-		(ETH_TX_DESC *) tx_desc_base_addr;
-	p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
-		(tx_desc_num * TX_DESC_ALIGNED_SIZE);
-
-	/* Add the queue to the list of Tx queues of this port */
-	p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
-
-	return true;
-}
-
-/*******************************************************************************
- * eth_port_send - Send an Ethernet packet
- *
- * DESCRIPTION:
- *	This routine send a given packet described by p_pktinfo parameter. It
- *	supports transmitting of a packet spaned over multiple buffers. The
- *	routine updates 'curr' and 'first' indexes according to the packet
- *	segment passed to the routine. In case the packet segment is first,
- *	the 'first' index is update. In any case, the 'curr' index is updated.
- *	If the routine get into Tx resource error it assigns 'curr' index as
- *	'first'. This way the function can abort Tx process of multiple
- *	descriptors per packet.
- *
- * INPUT:
- *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	tx_queue	 Number of Tx queue.
- *	PKT_INFO	*p_pkt_info	  User packet buffer.
- *
- * OUTPUT:
- *	Tx ring 'curr' and 'first' indexes are updated.
- *
- * RETURN:
- *	ETH_QUEUE_FULL in case of Tx resource error.
- *	ETH_ERROR in case the routine can not access Tx desc ring.
- *	ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
- *	ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
-					  ETH_QUEUE tx_queue,
-					  PKT_INFO * p_pkt_info)
-{
-	volatile ETH_TX_DESC *p_tx_desc_first;
-	volatile ETH_TX_DESC *p_tx_desc_curr;
-	volatile ETH_TX_DESC *p_tx_next_desc_curr;
-	volatile ETH_TX_DESC *p_tx_desc_used;
-	unsigned int command_status;
-
-	/* Do not process Tx ring in case of Tx ring resource error */
-	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
-		return ETH_QUEUE_FULL;
-
-	/* Get the Tx Desc ring indexes */
-	CURR_TFD_GET (p_tx_desc_curr, tx_queue);
-	USED_TFD_GET (p_tx_desc_used, tx_queue);
-
-	if (p_tx_desc_curr == NULL)
-		return ETH_ERROR;
-
-	/* The following parameters are used to save readings from memory */
-	p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
-	command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
-
-	if (command_status & (ETH_TX_FIRST_DESC)) {
-		/* Update first desc */
-		FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
-		p_tx_desc_first = p_tx_desc_curr;
-	} else {
-		FIRST_TFD_GET (p_tx_desc_first, tx_queue);
-		command_status |= ETH_BUFFER_OWNED_BY_DMA;
-	}
-
-	/* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
-	/* boundary. We use the memory allocated for Tx descriptor. This memory	 */
-	/* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
-	if (p_pkt_info->byte_cnt <= 8) {
-		printf ("You have failed in the < 8 bytes errata - fixme\n");	/* RABEEH - TBD */
-		return ETH_ERROR;
-
-		p_tx_desc_curr->buf_ptr =
-			(unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
-		eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
-			    p_pkt_info->byte_cnt);
-	} else
-		p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
-
-	p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
-	p_tx_desc_curr->return_info = p_pkt_info->return_info;
-
-	if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
-		/* Set last desc with DMA ownership and interrupt enable. */
-		p_tx_desc_curr->cmd_sts = command_status |
-			ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
-
-		if (p_tx_desc_curr != p_tx_desc_first)
-			p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
-
-		/* Flush CPU pipe */
-
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
-		CPU_PIPE_FLUSH;
-
-		/* Apply send command */
-		ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
-
-		/* Finish Tx packet. Update first desc in case of Tx resource error */
-		p_tx_desc_first = p_tx_next_desc_curr;
-		FIRST_TFD_SET (p_tx_desc_first, tx_queue);
-
-	} else {
-		p_tx_desc_curr->cmd_sts = command_status;
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
-	}
-
-	/* Check for ring index overlap in the Tx desc ring */
-	if (p_tx_next_desc_curr == p_tx_desc_used) {
-		/* Update the current descriptor */
-		CURR_TFD_SET (p_tx_desc_first, tx_queue);
-
-		p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
-		return ETH_QUEUE_LAST_RESOURCE;
-	} else {
-		/* Update the current descriptor */
-		CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
-		return ETH_OK;
-	}
-}
-
-/*******************************************************************************
- * eth_tx_return_desc - Free all used Tx descriptors
- *
- * DESCRIPTION:
- *	This routine returns the transmitted packet information to the caller.
- *	It uses the 'first' index to support Tx desc return in case a transmit
- *	of a packet spanned over multiple buffer still in process.
- *	In case the Tx queue was in "resource error" condition, where there are
- *	no available Tx resources, the function resets the resource error flag.
- *
- * INPUT:
- *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	tx_queue	 Number of Tx queue.
- *	PKT_INFO	*p_pkt_info	  User packet buffer.
- *
- * OUTPUT:
- *	Tx ring 'first' and 'used' indexes are updated.
- *
- * RETURN:
- *	ETH_ERROR in case the routine can not access Tx desc ring.
- *	ETH_RETRY in case there is transmission in process.
- *	ETH_END_OF_JOB if the routine has nothing to release.
- *	ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
-					       p_eth_port_ctrl,
-					       ETH_QUEUE tx_queue,
-					       PKT_INFO * p_pkt_info)
-{
-	volatile ETH_TX_DESC *p_tx_desc_used = NULL;
-	volatile ETH_TX_DESC *p_tx_desc_first = NULL;
-	unsigned int command_status;
-
-	/* Get the Tx Desc ring indexes */
-	USED_TFD_GET (p_tx_desc_used, tx_queue);
-	FIRST_TFD_GET (p_tx_desc_first, tx_queue);
-
-	/* Sanity check */
-	if (p_tx_desc_used == NULL)
-		return ETH_ERROR;
-
-	command_status = p_tx_desc_used->cmd_sts;
-
-	/* Still transmitting... */
-	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
-		return ETH_RETRY;
-	}
-
-	/* Stop release. About to overlap the current available Tx descriptor */
-	if ((p_tx_desc_used == p_tx_desc_first) &&
-	    (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
-		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
-		return ETH_END_OF_JOB;
-	}
-
-	/* Pass the packet information to the caller */
-	p_pkt_info->cmd_sts = command_status;
-	p_pkt_info->return_info = p_tx_desc_used->return_info;
-	p_tx_desc_used->return_info = 0;
-
-	/* Update the next descriptor to release. */
-	USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
-
-	/* Any Tx return cancels the Tx resource error status */
-	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
-		p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
-
-	D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
-
-	return ETH_OK;
-
-}
-
-/*******************************************************************************
- * eth_port_receive - Get received information from Rx ring.
- *
- * DESCRIPTION:
- *	This routine returns the received data to the caller. There is no
- *	data copying during routine operation. All information is returned
- *	using pointer to packet information struct passed from the caller.
- *	If the routine exhausts Rx ring resources then the resource error flag
- *	is set.
- *
- * INPUT:
- *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	rx_queue	 Number of Rx queue.
- *	PKT_INFO	*p_pkt_info	  User packet buffer.
- *
- * OUTPUT:
- *	Rx ring current and used indexes are updated.
- *
- * RETURN:
- *	ETH_ERROR in case the routine can not access Rx desc ring.
- *	ETH_QUEUE_FULL if Rx ring resources are exhausted.
- *	ETH_END_OF_JOB if there is no received data.
- *	ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
-					     ETH_QUEUE rx_queue,
-					     PKT_INFO * p_pkt_info)
-{
-	volatile ETH_RX_DESC *p_rx_curr_desc;
-	volatile ETH_RX_DESC *p_rx_next_curr_desc;
-	volatile ETH_RX_DESC *p_rx_used_desc;
-	unsigned int command_status;
-
-	/* Do not process Rx ring in case of Rx ring resource error */
-	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
-		printf ("\nRx Queue is full ...\n");
-		return ETH_QUEUE_FULL;
-	}
-
-	/* Get the Rx Desc ring 'curr and 'used' indexes */
-	CURR_RFD_GET (p_rx_curr_desc, rx_queue);
-	USED_RFD_GET (p_rx_used_desc, rx_queue);
-
-	/* Sanity check */
-	if (p_rx_curr_desc == NULL)
-		return ETH_ERROR;
-
-	/* The following parameters are used to save readings from memory */
-	p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
-	command_status = p_rx_curr_desc->cmd_sts;
-
-	/* Nothing to receive... */
-	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
-/*	DP(printf("Rx: command_status: %08x\n", command_status)); */
-		D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
-/*	DP(printf("\nETH_END_OF_JOB ...\n"));*/
-		return ETH_END_OF_JOB;
-	}
-
-	p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
-	p_pkt_info->cmd_sts = command_status;
-	p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
-	p_pkt_info->return_info = p_rx_curr_desc->return_info;
-	p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
-
-	/* Clean the return info field to indicate that the packet has been */
-	/* moved to the upper layers					    */
-	p_rx_curr_desc->return_info = 0;
-
-	/* Update 'curr' in data structure */
-	CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
-
-	/* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
-	if (p_rx_next_curr_desc == p_rx_used_desc)
-		p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
-
-	D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
-	CPU_PIPE_FLUSH;
-
-	return ETH_OK;
-}
-
-/*******************************************************************************
- * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
- *
- * DESCRIPTION:
- *	This routine returns a Rx buffer back to the Rx ring. It retrieves the
- *	next 'used' descriptor and attached the returned buffer to it.
- *	In case the Rx ring was in "resource error" condition, where there are
- *	no available Rx resources, the function resets the resource error flag.
- *
- * INPUT:
- *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE	rx_queue	 Number of Rx queue.
- *	PKT_INFO	*p_pkt_info	  Information on the returned buffer.
- *
- * OUTPUT:
- *	New available Rx resource in Rx descriptor ring.
- *
- * RETURN:
- *	ETH_ERROR in case the routine can not access Rx desc ring.
- *	ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
-					       p_eth_port_ctrl,
-					       ETH_QUEUE rx_queue,
-					       PKT_INFO * p_pkt_info)
-{
-	volatile ETH_RX_DESC *p_used_rx_desc;	/* Where to return Rx resource */
-
-	/* Get 'used' Rx descriptor */
-	USED_RFD_GET (p_used_rx_desc, rx_queue);
-
-	/* Sanity check */
-	if (p_used_rx_desc == NULL)
-		return ETH_ERROR;
-
-	p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
-	p_used_rx_desc->return_info = p_pkt_info->return_info;
-	p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
-	p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE;	/* Reset Buffer size */
-
-	/* Flush the write pipe */
-	CPU_PIPE_FLUSH;
-
-	/* Return the descriptor to DMA ownership */
-	p_used_rx_desc->cmd_sts =
-		ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
-
-	/* Flush descriptor and CPU pipe */
-	D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
-	CPU_PIPE_FLUSH;
-
-	/* Move the used descriptor pointer to the next descriptor */
-	USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
-
-	/* Any Rx return cancels the Rx resource error status */
-	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
-		p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
-
-	return ETH_OK;
-}
-
-/*******************************************************************************
- * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
- *
- * DESCRIPTION:
- *	This routine sets the RX coalescing interrupt mechanism parameter.
- *	This parameter is a timeout counter, that counts in 64 t_clk
- *	chunks ; that when timeout event occurs a maskable interrupt
- *	occurs.
- *	The parameter is calculated using the tClk of the MV-643xx chip
- *	, and the required delay of the interrupt in usec.
- *
- * INPUT:
- *	ETH_PORT eth_port_num	   Ethernet port number
- *	unsigned int t_clk	  t_clk of the MV-643xx chip in HZ units
- *	unsigned int delay	 Delay in usec
- *
- * OUTPUT:
- *	Interrupt coalescing mechanism value is set in MV-643xx chip.
- *
- * RETURN:
- *	The interrupt coalescing value set in the gigE port.
- *
- *******************************************************************************/
-#if 0				/* FIXME */
-static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
-					  unsigned int t_clk,
-					  unsigned int delay)
-{
-	unsigned int coal;
-
-	coal = ((t_clk / 1000000) * delay) / 64;
-	/* Set RX Coalescing mechanism */
-	MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
-		      ((coal & 0x3fff) << 8) |
-		      (MV_REG_READ
-		       (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num))
-		       & 0xffc000ff));
-	return coal;
-}
-
-#endif
-/*******************************************************************************
- * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
- *
- * DESCRIPTION:
- *	This routine sets the TX coalescing interrupt mechanism parameter.
- *	This parameter is a timeout counter, that counts in 64 t_clk
- *	chunks ; that when timeout event occurs a maskable interrupt
- *	occurs.
- *	The parameter is calculated using the t_cLK frequency of the
- *	MV-643xx chip and the required delay in the interrupt in uSec
- *
- * INPUT:
- *	ETH_PORT eth_port_num	   Ethernet port number
- *	unsigned int t_clk	  t_clk of the MV-643xx chip in HZ units
- *	unsigned int delay	 Delay in uSeconds
- *
- * OUTPUT:
- *	Interrupt coalescing mechanism value is set in MV-643xx chip.
- *
- * RETURN:
- *	The interrupt coalescing value set in the gigE port.
- *
- *******************************************************************************/
-#if 0				/* FIXME */
-static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
-					  unsigned int t_clk,
-					  unsigned int delay)
-{
-	unsigned int coal;
-
-	coal = ((t_clk / 1000000) * delay) / 64;
-	/* Set TX Coalescing mechanism */
-	MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
-		      coal << 4);
-	return coal;
-}
-#endif
-
-/*******************************************************************************
- * eth_b_copy - Copy bytes from source to destination
- *
- * DESCRIPTION:
- *	 This function supports the eight bytes limitation on Tx buffer size.
- *	 The routine will zero eight bytes starting from the destination address
- *	 followed by copying bytes from the source address to the destination.
- *
- * INPUT:
- *	 unsigned int src_addr	  32 bit source address.
- *	 unsigned int dst_addr	  32 bit destination address.
- *	 int	    byte_count	  Number of bytes to copy.
- *
- * OUTPUT:
- *	 See description.
- *
- * RETURN:
- *	 None.
- *
- *******************************************************************************/
-static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
-			int byte_count)
-{
-	/* Zero the dst_addr area */
-	*(unsigned int *) dst_addr = 0x0;
-
-	while (byte_count != 0) {
-		*(char *) dst_addr = *(char *) src_addr;
-		dst_addr++;
-		src_addr++;
-		byte_count--;
-	}
-}
diff --git a/board/prodrive/p3mx/mv_eth.h b/board/prodrive/p3mx/mv_eth.h
deleted file mode 100644
index 7bbd7f045cf..00000000000
--- a/board/prodrive/p3mx/mv_eth.h
+++ /dev/null
@@ -1,815 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * mv_eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __DB64460_ETH_H__
-#define __DB64460_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-#include <net.h>
-#include "mv_regs.h"
-#include <asm/errno.h>
-#include "../../Marvell/include/core.h"
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The first part is the high level driver of the gigE ethernet ports.	 *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
-#ifndef MAX_SKB_FRAGS
-#define MAX_SKB_FRAGS 0
-#endif
-
-/* Port attributes */
-/*#define MAX_RX_QUEUE_NUM	8*/
-/*#define MAX_TX_QUEUE_NUM	8*/
-#define MAX_RX_QUEUE_NUM	1
-#define MAX_TX_QUEUE_NUM	1
-
-
-/* Use one TX queue and one RX queue */
-#define MV64460_TX_QUEUE_NUM 1
-#define MV64460_RX_QUEUE_NUM 1
-
-/*
- * Number of RX / TX descriptors on RX / TX rings.
- * Note that allocating RX descriptors is done by allocating the RX
- * ring AND a preallocated RX buffers (skb's) for each descriptor.
- * The TX descriptors only allocates the TX descriptors ring,
- * with no pre allocated TX buffers (skb's are allocated by higher layers.
- */
-
-/* Default TX ring size is 10 descriptors */
-#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
-#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
-#else
-#define MV64460_TX_QUEUE_SIZE 4
-#endif
-
-/* Default RX ring size is 4 descriptors */
-#ifdef	CONFIG_MV64460_ETH_RXQUEUE_SIZE
-#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
-#else
-#define MV64460_RX_QUEUE_SIZE 4
-#endif
-
-#ifdef CONFIG_RX_BUFFER_SIZE
-#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
-#else
-#define MV64460_RX_BUFFER_SIZE 1600
-#endif
-
-#ifdef CONFIG_TX_BUFFER_SIZE
-#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
-#else
-#define MV64460_TX_BUFFER_SIZE 1600
-#endif
-
-/*
- *	Network device statistics. Akin to the 2.0 ether stats but
- *	with byte counters.
- */
-
-struct net_device_stats
-{
-	unsigned long	rx_packets;		/* total packets received	*/
-	unsigned long	tx_packets;		/* total packets transmitted	*/
-	unsigned long	rx_bytes;		/* total bytes received		*/
-	unsigned long	tx_bytes;		/* total bytes transmitted	*/
-	unsigned long	rx_errors;		/* bad packets received		*/
-	unsigned long	tx_errors;		/* packet transmit problems	*/
-	unsigned long	rx_dropped;		/* no space in linux buffers	*/
-	unsigned long	tx_dropped;		/* no space available in linux	*/
-	unsigned long	multicast;		/* multicast packets received	*/
-	unsigned long	collisions;
-
-	/* detailed rx_errors: */
-	unsigned long	rx_length_errors;
-	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
-	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
-	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
-	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
-	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
-
-	/* detailed tx_errors */
-	unsigned long	tx_aborted_errors;
-	unsigned long	tx_carrier_errors;
-	unsigned long	tx_fifo_errors;
-	unsigned long	tx_heartbeat_errors;
-	unsigned long	tx_window_errors;
-
-	/* for cslip etc */
-	unsigned long	rx_compressed;
-	unsigned long	tx_compressed;
-};
-
-
-/* Private data structure used for ethernet device */
-struct mv64460_eth_priv {
-    unsigned int port_num;
-    struct net_device_stats *stats;
-
-    /* to buffer area aligned */
-    char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
-    char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
-
-    /* Size of Tx Ring per queue */
-    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
-
-    /* Size of Rx Ring per queue */
-    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
-
-    /* Magic Number for Ethernet running */
-    unsigned int eth_running;
-
-    int first_init;
-};
-
-int mv64460_eth_init (struct eth_device *dev);
-int mv64460_eth_stop (struct eth_device *dev);
-int mv64460_eth_start_xmit(struct eth_device *dev, void *packet, int length);
-int mv64460_eth_open (struct eth_device *dev);
-
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-*  The second part is the low level driver of the gigE ethernet ports.	 *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-
-
-/********************************************************************************
- * Header File for : MV-643xx network interface header
- *
- * DESCRIPTION:
- *	 This header file contains macros typedefs and function declaration for
- *	 the Marvell Gig Bit Ethernet Controller.
- *
- * DEPENDENCIES:
- *	 None.
- *
- *******************************************************************************/
-
-
-#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
-#ifdef CONFIG_MV64460_SRAM_CACHEABLE
-/* In case SRAM is cacheable but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset)       \
-{		    \
-  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case SRAM is cache coherent or non-cacheable */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif
-#else
-#ifdef CONFIG_NOT_COHERENT_CACHE
-/* In case of descriptors on DDR but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset)       \
-{		    \
-  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case of descriptors on DDR and cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif /* CONFIG_NOT_COHERENT_CACHE */
-#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
-
-
-#define CPU_PIPE_FLUSH		   \
-{		  \
-  __asm__ __volatile__ ("eieio");	  \
-}
-
-
-/* defines  */
-
-/* Default port configuration value */
-#define PORT_CONFIG_VALUE			\
-	     ETH_UNICAST_NORMAL_MODE		|   \
-	     ETH_DEFAULT_RX_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
-	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
-	     ETH_RECEIVE_BC_IF_IP		|   \
-	     ETH_RECEIVE_BC_IF_ARP		|   \
-	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
-	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
-	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
-	     ETH_DEFAULT_RX_BPDU_QUEUE_0
-
-/* Default port extend configuration value */
-#define PORT_CONFIG_EXTEND_VALUE		\
-	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
-	     ETH_PARTITION_DISABLE
-
-
-/* Default sdma control value */
-#ifdef CONFIG_NOT_COHERENT_CACHE
-#define PORT_SDMA_CONFIG_VALUE				\
-			 ETH_RX_BURST_SIZE_16_64BIT	|	\
-			 GT_ETH_IPG_INT_RX(0)			|	\
-			 ETH_TX_BURST_SIZE_16_64BIT;
-#else
-#define PORT_SDMA_CONFIG_VALUE			\
-			 ETH_RX_BURST_SIZE_4_64BIT	|	\
-			 GT_ETH_IPG_INT_RX(0)			|	\
-			 ETH_TX_BURST_SIZE_4_64BIT;
-#endif
-
-#define GT_ETH_IPG_INT_RX(value)		\
-	    ((value & 0x3fff) << 8)
-
-/* Default port serial control value */
-#define PORT_SERIAL_CONTROL_VALUE			    \
-			ETH_FORCE_LINK_PASS			|	\
-			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
-			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
-			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
-			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
-			ETH_FORCE_BP_MODE_NO_JAM		|	\
-			BIT9					|	\
-			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
-			ETH_RETRANSMIT_16_ETTEMPTS		|	\
-			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
-			ETH_DTE_ADV_0				|	\
-			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
-			ETH_AUTO_NEG_NO_CHANGE			|	\
-			ETH_MAX_RX_PACKET_1552BYTE		|	\
-			ETH_CLR_EXT_LOOPBACK			|	\
-			ETH_SET_FULL_DUPLEX_MODE		|	\
-			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
-
-#define RX_BUFFER_MAX_SIZE  0xFFFF
-#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
-
-#define RX_BUFFER_MIN_SIZE  0x8
-#define TX_BUFFER_MIN_SIZE  0x8
-
-/* Tx WRR confoguration macros */
-#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
-#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
-#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
-
-/* MAC accepet/reject macros */
-#define ACCEPT_MAC_ADDR	    0
-#define REJECT_MAC_ADDR	    1
-
-/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define RX_DESC_ALIGNED_SIZE		0x20
-#define TX_DESC_ALIGNED_SIZE		0x20
-
-/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
-#define TX_BUF_OFFSET_IN_DESC	    0x18
-/* Buffer offset from buffer pointer */
-#define RX_BUF_OFFSET				0x2
-
-/* Gap define */
-#define ETH_BAR_GAP					0x8
-#define ETH_SIZE_REG_GAP				0x8
-#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
-#define ETH_PORT_ACCESS_CTRL_GAP			0x4
-
-/* Gigabit Ethernet Unit Global Registers */
-
-/* MIB Counters register definitions */
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
-#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
-#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
-#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
-#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
-#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
-#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
-#define ETH_MIB_FRAMES_64_OCTETS	   0x20
-#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
-#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
-#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
-#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
-#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
-#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
-#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
-#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
-#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
-#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
-#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
-#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
-#define ETH_MIB_FC_SENT			   0x54
-#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
-#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
-#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
-#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
-#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
-#define ETH_MIB_JABBER_RECEIVED		   0x6c
-#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
-#define ETH_MIB_BAD_CRC_EVENT		   0x74
-#define ETH_MIB_COLLISION		   0x78
-#define ETH_MIB_LATE_COLLISION		   0x7c
-
-/* Port serial status reg (PSR) */
-#define ETH_INTERFACE_GMII_MII				0
-#define ETH_INTERFACE_PCM				BIT0
-#define ETH_LINK_IS_DOWN				0
-#define ETH_LINK_IS_UP					BIT1
-#define ETH_PORT_AT_HALF_DUPLEX				0
-#define ETH_PORT_AT_FULL_DUPLEX				BIT2
-#define ETH_RX_FLOW_CTRL_DISABLED			0
-#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
-#define ETH_GMII_SPEED_100_10				0
-#define ETH_GMII_SPEED_1000				BIT4
-#define ETH_MII_SPEED_10				0
-#define ETH_MII_SPEED_100				BIT5
-#define ETH_NO_TX					0
-#define ETH_TX_IN_PROGRESS				BIT7
-#define ETH_BYPASS_NO_ACTIVE				0
-#define ETH_BYPASS_ACTIVE				BIT8
-#define ETH_PORT_NOT_AT_PARTITION_STATE			0
-#define ETH_PORT_AT_PARTITION_STATE			BIT9
-#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
-#define ETH_PORT_TX_FIFO_EMPTY				BIT10
-
-
-/* These macros describes the Port configuration reg (Px_cR) bits */
-#define ETH_UNICAST_NORMAL_MODE				0
-#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
-#define ETH_DEFAULT_RX_QUEUE_0				0
-#define ETH_DEFAULT_RX_QUEUE_1				BIT1
-#define ETH_DEFAULT_RX_QUEUE_2				BIT2
-#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_4				BIT3
-#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
-#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
-#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
-#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
-#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
-#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
-#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
-#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
-#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
-#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
-#define ETH_RECEIVE_BC_IF_IP				0
-#define ETH_REJECT_BC_IF_IP				BIT8
-#define ETH_RECEIVE_BC_IF_ARP				0
-#define ETH_REJECT_BC_IF_ARP				BIT9
-#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
-#define ETH_CAPTURE_TCP_FRAMES_DIS			0
-#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
-#define ETH_CAPTURE_UDP_FRAMES_DIS			0
-#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
-#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
-#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
-#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
-#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
-#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
-#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
-#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
-#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
-#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
-#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
-#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
-#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
-#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
-#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
-#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
-#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
-
-
-/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
-#define ETH_CLASSIFY_EN					BIT0
-#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
-#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
-#define ETH_PARTITION_DISABLE				0
-#define ETH_PARTITION_ENABLE				BIT2
-
-
-/* Tx/Rx queue command reg (RQCR/TQCR)*/
-#define ETH_QUEUE_0_ENABLE				BIT0
-#define ETH_QUEUE_1_ENABLE				BIT1
-#define ETH_QUEUE_2_ENABLE				BIT2
-#define ETH_QUEUE_3_ENABLE				BIT3
-#define ETH_QUEUE_4_ENABLE				BIT4
-#define ETH_QUEUE_5_ENABLE				BIT5
-#define ETH_QUEUE_6_ENABLE				BIT6
-#define ETH_QUEUE_7_ENABLE				BIT7
-#define ETH_QUEUE_0_DISABLE				BIT8
-#define ETH_QUEUE_1_DISABLE				BIT9
-#define ETH_QUEUE_2_DISABLE				BIT10
-#define ETH_QUEUE_3_DISABLE				BIT11
-#define ETH_QUEUE_4_DISABLE				BIT12
-#define ETH_QUEUE_5_DISABLE				BIT13
-#define ETH_QUEUE_6_DISABLE				BIT14
-#define ETH_QUEUE_7_DISABLE				BIT15
-
-/* These macros describes the Port Sdma configuration reg (SDCR) bits */
-#define ETH_RIFB					BIT0
-#define ETH_RX_BURST_SIZE_1_64BIT			0
-#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
-#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
-#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
-#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
-#define ETH_BLM_RX_NO_SWAP				BIT4
-#define ETH_BLM_RX_BYTE_SWAP				0
-#define ETH_BLM_TX_NO_SWAP				BIT5
-#define ETH_BLM_TX_BYTE_SWAP				0
-#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
-#define ETH_DESCRIPTORS_NO_SWAP				0
-#define ETH_TX_BURST_SIZE_1_64BIT			0
-#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
-#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
-#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
-#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
-
-/* These macros describes the Port serial control reg (PSCR) bits */
-#define ETH_SERIAL_PORT_DISABLE				0
-#define ETH_SERIAL_PORT_ENABLE				BIT0
-#define ETH_FORCE_LINK_PASS				BIT1
-#define ETH_DO_NOT_FORCE_LINK_PASS			0
-#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
-#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
-#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
-#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
-#define ETH_ADV_NO_FLOW_CTRL				0
-#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
-#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
-#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
-#define ETH_FORCE_BP_MODE_NO_JAM			0
-#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
-#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
-#define ETH_FORCE_LINK_FAIL				0
-#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
-#define ETH_RETRANSMIT_16_ETTEMPTS			0
-#define ETH_RETRANSMIT_FOREVER				BIT11
-#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
-#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
-#define ETH_DTE_ADV_0					0
-#define ETH_DTE_ADV_1					BIT14
-#define ETH_DISABLE_AUTO_NEG_BYPASS			0
-#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
-#define ETH_AUTO_NEG_NO_CHANGE				0
-#define ETH_RESTART_AUTO_NEG				BIT16
-#define ETH_MAX_RX_PACKET_1518BYTE			0
-#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
-#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
-#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
-#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
-#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
-#define ETH_SET_EXT_LOOPBACK				BIT20
-#define ETH_CLR_EXT_LOOPBACK				0
-#define ETH_SET_FULL_DUPLEX_MODE			BIT21
-#define ETH_SET_HALF_DUPLEX_MODE			0
-#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
-#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
-#define ETH_SET_GMII_SPEED_TO_10_100			0
-#define ETH_SET_GMII_SPEED_TO_1000			BIT23
-#define ETH_SET_MII_SPEED_TO_10				0
-#define ETH_SET_MII_SPEED_TO_100			BIT24
-
-
-/* SMI reg */
-#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
-#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
-#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
-#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
-
-/* SDMA command status fields macros */
-
-/* Tx & Rx descriptors status */
-#define ETH_ERROR_SUMMARY		    (BIT0)
-
-/* Tx & Rx descriptors command */
-#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
-
-/* Tx descriptors status */
-#define ETH_LC_ERROR			    (0	  )
-#define ETH_UR_ERROR			    (BIT1 )
-#define ETH_RL_ERROR			    (BIT2 )
-#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
-
-/* Rx descriptors status */
-#define ETH_CRC_ERROR			    (0	  )
-#define ETH_OVERRUN_ERROR		    (BIT1 )
-#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
-#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
-#define ETH_VLAN_TAGGED			    (BIT19)
-#define ETH_BPDU_FRAME			    (BIT20)
-#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
-#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
-#define ETH_OTHER_FRAME_TYPE		    (BIT22)
-#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
-#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
-#define ETH_FRAME_HEADER_OK		    (BIT25)
-#define ETH_RX_LAST_DESC		    (BIT26)
-#define ETH_RX_FIRST_DESC		    (BIT27)
-#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
-#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
-#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
-
-/* Rx descriptors byte count */
-#define ETH_FRAME_FRAGMENTED		    (BIT2)
-
-/* Tx descriptors command */
-#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
-#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
-#define ETH_TCP_FRAME			    (0	  )
-#define ETH_UDP_FRAME			    (BIT16)
-#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
-#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
-#define ETH_ZERO_PADDING		    (BIT19)
-#define ETH_TX_LAST_DESC		    (BIT20)
-#define ETH_TX_FIRST_DESC		    (BIT21)
-#define ETH_GEN_CRC			    (BIT22)
-#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
-#define ETH_AUTO_MODE			    (BIT30)
-
-/* Address decode parameters */
-/* Ethernet Base Address Register bits */
-#define EBAR_TARGET_DRAM					0x00000000
-#define EBAR_TARGET_DEVICE					0x00000001
-#define EBAR_TARGET_CBS						0x00000002
-#define EBAR_TARGET_PCI0					0x00000003
-#define EBAR_TARGET_PCI1					0x00000004
-#define EBAR_TARGET_CUNIT					0x00000005
-#define EBAR_TARGET_AUNIT					0x00000006
-#define EBAR_TARGET_GUNIT					0x00000007
-
-/* Window attributes */
-#define EBAR_ATTR_DRAM_CS0					0x00000E00
-#define EBAR_ATTR_DRAM_CS1					0x00000D00
-#define EBAR_ATTR_DRAM_CS2					0x00000B00
-#define EBAR_ATTR_DRAM_CS3					0x00000700
-
-/* DRAM Target interface */
-#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
-
-/* Device Bus Target interface */
-#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
-#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
-#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
-#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
-#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
-
-/* PCI Target interface */
-#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
-#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
-#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
-#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
-#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
-#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
-#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
-#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
-#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
-#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
-
-/* CPU 60x bus or internal SRAM interface */
-#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
-#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
-#define EBAR_ATTR_CBS_SRAM					0x00000000
-#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
-
-/* Window access control */
-#define EWIN_ACCESS_NOT_ALLOWED 0
-#define EWIN_ACCESS_READ_ONLY	BIT0
-#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
-#define EWIN0_ACCESS_MASK		0x0003
-#define EWIN1_ACCESS_MASK		0x000C
-#define EWIN2_ACCESS_MASK		0x0030
-#define EWIN3_ACCESS_MASK		0x00C0
-
-/* typedefs */
-
-typedef enum _eth_port
-{
-    ETH_0 = 0,
-	ETH_1 = 1,
-	ETH_2 = 2
-}ETH_PORT;
-
-typedef enum _eth_func_ret_status
-{
-    ETH_OK,			/* Returned as expected.		    */
-    ETH_ERROR,			/* Fundamental error.			    */
-    ETH_RETRY,			/* Could not process request. Try later.    */
-    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
-    ETH_QUEUE_FULL,		/* Ring resource error.			    */
-    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
-}ETH_FUNC_RET_STATUS;
-
-typedef enum _eth_queue
-{
-	ETH_Q0 = 0,
-	ETH_Q1 = 1,
-	ETH_Q2 = 2,
-	ETH_Q3 = 3,
-	ETH_Q4 = 4,
-	ETH_Q5 = 5,
-	ETH_Q6 = 6,
-    ETH_Q7 = 7
-} ETH_QUEUE;
-
-typedef enum _addr_win
-{
-	ETH_WIN0,
-	ETH_WIN1,
-	ETH_WIN2,
-	ETH_WIN3,
-	ETH_WIN4,
-    ETH_WIN5
-} ETH_ADDR_WIN;
-
-typedef enum _eth_target
-{
-	ETH_TARGET_DRAM	 ,
-	ETH_TARGET_DEVICE,
-	ETH_TARGET_CBS	 ,
-	ETH_TARGET_PCI0	 ,
-	ETH_TARGET_PCI1
-}ETH_TARGET;
-
-typedef struct _eth_rx_desc
-{
-	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
-	unsigned short	buf_size	   ;	/* Buffer size			    */
-	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
-	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
-	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} ETH_RX_DESC;
-
-
-typedef struct _eth_tx_desc
-{
-    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
-    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
-    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
-    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
-    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} ETH_TX_DESC;
-
-/* Unified struct for Rx and Tx operations. The user is not required to */
-/* be familier with neither Tx nor Rx descriptors.			 */
-typedef struct _pkt_info
-{
-	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
-	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
-	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
-	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
-    unsigned int    return_info ;    /* User resource return information */
-} PKT_INFO;
-
-
-typedef struct _eth_win_param
-{
-    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
-    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
-    unsigned short attributes;	/* BAR attributes. See above macros. */
-    unsigned int base_addr; /* Window base address in unsigned int form */
-    unsigned int high_addr; /* Window high address in unsigned int form */
-    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
-    bool enable; /* Enable/disable access to the window. */
-    unsigned short access_ctrl; /* Access ctrl register. see above macros */
-} ETH_WIN_PARAM;
-
-
-/* Ethernet port specific infomation */
-
-typedef struct _eth_port_ctrl
-{
-    ETH_PORT  port_num; /* User Ethernet port number */
-    int port_phy_addr;	/* User phy address of Ethrnet port */
-    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
-    unsigned int  port_config; /* User port configuration value */
-    unsigned int  port_config_extend; /* User port config extend value */
-    unsigned int  port_sdma_config; /* User port SDMA config value */
-    unsigned int  port_serial_control; /* User port serial control value */
-    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
-    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
-
-    /* User function to cast virtual address to CPU bus address */
-    unsigned int  (*port_virt_to_phys)(unsigned int addr);
-    /* User scratch pad for user specific data structures */
-    void *port_private;
-
-    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
-    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
-
-    /* Tx/Rx rings managment indexes fields. For driver use */
-
-    /* Next available Rx resource */
-    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
-    /* Returning Rx resource */
-    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
-
-    /* Next available Tx resource */
-    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
-    /* Returning Tx resource */
-    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
-    /* An extra Tx index to support transmit of multiple buffers per packet */
-    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
-
-    /* Tx/Rx rings size and base variables fields. For driver use */
-
-    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
-    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
-    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
-
-    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
-    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
-    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
-
-} ETH_PORT_INFO;
-
-
-/* ethernet.h API list */
-
-/* Port operation control routines */
-static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
-static void eth_port_reset(ETH_PORT	eth_port_num);
-static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
-
-
-/* Port MAC address routines */
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
-				  unsigned char *p_addr,
-				  ETH_QUEUE queue);
-#if 0	/* FIXME */
-static void eth_port_mc_addr	(ETH_PORT eth_port_num,
-				 unsigned char *p_addr,
-				 ETH_QUEUE queue,
-				 int option);
-#endif
-
-/* PHY and MIB routines */
-static bool ethernet_phy_reset(ETH_PORT eth_port_num);
-
-static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
-				   unsigned int phy_reg,
-				   unsigned int value);
-
-static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
-				  unsigned int phy_reg,
-				  unsigned int* value);
-
-static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
-
-/* Port data flow control routines */
-static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
-					     ETH_QUEUE tx_queue,
-					     PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
-					      ETH_QUEUE tx_queue,
-					      PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
-					     ETH_QUEUE rx_queue,
-					     PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
-					      ETH_QUEUE rx_queue,
-					      PKT_INFO *p_pkt_info);
-
-
-static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
-				    ETH_QUEUE	tx_queue,
-				    int				tx_desc_num,
-				    int				tx_buff_size,
-				    unsigned int	tx_desc_base_addr,
-				    unsigned int	tx_buff_base_addr);
-
-static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
-				    ETH_QUEUE	rx_queue,
-				    int				rx_desc_num,
-				    int				rx_buff_size,
-				    unsigned int	rx_desc_base_addr,
-				    unsigned int	rx_buff_base_addr);
-
-#endif /* MV64460_ETH_ */
diff --git a/board/prodrive/p3mx/mv_regs.h b/board/prodrive/p3mx/mv_regs.h
deleted file mode 100644
index 279a7e9610d..00000000000
--- a/board/prodrive/p3mx/mv_regs.h
+++ /dev/null
@@ -1,1109 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/********************************************************************************
-* gt64460r.h - GT-64460 Internal registers definition file.
-*
-* DESCRIPTION:
-*	None.
-*
-* DEPENDENCIES:
-*	None.
-*
-*******************************************************************************/
-
-#ifndef __INCmv_regsh
-#define __INCmv_regsh
-
-#define MV64460
-
-/* Supported by the Atlantis */
-#define MV64460_INCLUDE_PCI_1
-#define MV64460_INCLUDE_PCI_0_ARBITER
-#define MV64460_INCLUDE_PCI_1_ARBITER
-#define MV64460_INCLUDE_SNOOP_SUPPORT
-#define MV64460_INCLUDE_P2P
-#define MV64460_INCLUDE_ETH_PORT_2
-#define MV64460_INCLUDE_CPU_MAPPING
-#define MV64460_INCLUDE_MPSC
-
-/* Not supported features */
-#undef	INCLUDE_CNTMR_4_7
-#undef	INCLUDE_DMA_4_7
-
-/****************************************/
-/* Processor Address Space		*/
-/****************************************/
-
-/* DDR SDRAM BAR and size registers */
-
-#define MV64460_CS_0_BASE_ADDR					    0x008
-#define MV64460_CS_0_SIZE					    0x010
-#define MV64460_CS_1_BASE_ADDR					    0x208
-#define MV64460_CS_1_SIZE					    0x210
-#define MV64460_CS_2_BASE_ADDR					    0x018
-#define MV64460_CS_2_SIZE					    0x020
-#define MV64460_CS_3_BASE_ADDR					    0x218
-#define MV64460_CS_3_SIZE					    0x220
-
-/* Devices BAR and size registers */
-
-#define MV64460_DEV_CS0_BASE_ADDR				    0x028
-#define MV64460_DEV_CS0_SIZE					    0x030
-#define MV64460_DEV_CS1_BASE_ADDR				    0x228
-#define MV64460_DEV_CS1_SIZE					    0x230
-#define MV64460_DEV_CS2_BASE_ADDR				    0x248
-#define MV64460_DEV_CS2_SIZE					    0x250
-#define MV64460_DEV_CS3_BASE_ADDR				    0x038
-#define MV64460_DEV_CS3_SIZE					    0x040
-#define MV64460_BOOTCS_BASE_ADDR				    0x238
-#define MV64460_BOOTCS_SIZE					    0x240
-
-/* PCI 0 BAR and size registers */
-
-#define MV64460_PCI_0_IO_BASE_ADDR				    0x048
-#define MV64460_PCI_0_IO_SIZE					    0x050
-#define MV64460_PCI_0_MEMORY0_BASE_ADDR				    0x058
-#define MV64460_PCI_0_MEMORY0_SIZE				    0x060
-#define MV64460_PCI_0_MEMORY1_BASE_ADDR				    0x080
-#define MV64460_PCI_0_MEMORY1_SIZE				    0x088
-#define MV64460_PCI_0_MEMORY2_BASE_ADDR				    0x258
-#define MV64460_PCI_0_MEMORY2_SIZE				    0x260
-#define MV64460_PCI_0_MEMORY3_BASE_ADDR				    0x280
-#define MV64460_PCI_0_MEMORY3_SIZE				    0x288
-
-/* PCI 1 BAR and size registers */
-#define MV64460_PCI_1_IO_BASE_ADDR				    0x090
-#define MV64460_PCI_1_IO_SIZE					    0x098
-#define MV64460_PCI_1_MEMORY0_BASE_ADDR				    0x0a0
-#define MV64460_PCI_1_MEMORY0_SIZE				    0x0a8
-#define MV64460_PCI_1_MEMORY1_BASE_ADDR				    0x0b0
-#define MV64460_PCI_1_MEMORY1_SIZE				    0x0b8
-#define MV64460_PCI_1_MEMORY2_BASE_ADDR				    0x2a0
-#define MV64460_PCI_1_MEMORY2_SIZE				    0x2a8
-#define MV64460_PCI_1_MEMORY3_BASE_ADDR				    0x2b0
-#define MV64460_PCI_1_MEMORY3_SIZE				    0x2b8
-
-/* SRAM base address */
-#define MV64460_INTEGRATED_SRAM_BASE_ADDR			    0x268
-
-/* internal registers space base address */
-#define MV64460_INTERNAL_SPACE_BASE_ADDR			    0x068
-
-/* Enables the CS , DEV_CS , PCI 0 and PCI 1
-   windows above */
-#define MV64460_BASE_ADDR_ENABLE				    0x278
-
-/****************************************/
-/* PCI remap registers			*/
-/****************************************/
-      /* PCI 0 */
-#define MV64460_PCI_0_IO_ADDR_REMAP				    0x0f0
-#define MV64460_PCI_0_MEMORY0_LOW_ADDR_REMAP			    0x0f8
-#define MV64460_PCI_0_MEMORY0_HIGH_ADDR_REMAP			    0x320
-#define MV64460_PCI_0_MEMORY1_LOW_ADDR_REMAP			    0x100
-#define MV64460_PCI_0_MEMORY1_HIGH_ADDR_REMAP			    0x328
-#define MV64460_PCI_0_MEMORY2_LOW_ADDR_REMAP			    0x2f8
-#define MV64460_PCI_0_MEMORY2_HIGH_ADDR_REMAP			    0x330
-#define MV64460_PCI_0_MEMORY3_LOW_ADDR_REMAP			    0x300
-#define MV64460_PCI_0_MEMORY3_HIGH_ADDR_REMAP			    0x338
-      /* PCI 1 */
-#define MV64460_PCI_1_IO_ADDR_REMAP				    0x108
-#define MV64460_PCI_1_MEMORY0_LOW_ADDR_REMAP			    0x110
-#define MV64460_PCI_1_MEMORY0_HIGH_ADDR_REMAP			    0x340
-#define MV64460_PCI_1_MEMORY1_LOW_ADDR_REMAP			    0x118
-#define MV64460_PCI_1_MEMORY1_HIGH_ADDR_REMAP			    0x348
-#define MV64460_PCI_1_MEMORY2_LOW_ADDR_REMAP			    0x310
-#define MV64460_PCI_1_MEMORY2_HIGH_ADDR_REMAP			    0x350
-#define MV64460_PCI_1_MEMORY3_LOW_ADDR_REMAP			    0x318
-#define MV64460_PCI_1_MEMORY3_HIGH_ADDR_REMAP			    0x358
-
-#define MV64460_CPU_PCI_0_HEADERS_RETARGET_CONTROL		    0x3b0
-#define MV64460_CPU_PCI_0_HEADERS_RETARGET_BASE			    0x3b8
-#define MV64460_CPU_PCI_1_HEADERS_RETARGET_CONTROL		    0x3c0
-#define MV64460_CPU_PCI_1_HEADERS_RETARGET_BASE			    0x3c8
-#define MV64460_CPU_GE_HEADERS_RETARGET_CONTROL			    0x3d0
-#define MV64460_CPU_GE_HEADERS_RETARGET_BASE			    0x3d8
-#define MV64460_CPU_IDMA_HEADERS_RETARGET_CONTROL		    0x3e0
-#define MV64460_CPU_IDMA_HEADERS_RETARGET_BASE			    0x3e8
-
-/****************************************/
-/*	   CPU Control Registers	*/
-/****************************************/
-
-#define MV64460_CPU_CONFIG					    0x000
-#define MV64460_CPU_MODE					    0x120
-#define MV64460_CPU_MASTER_CONTROL				    0x160
-#define MV64460_CPU_CROSS_BAR_CONTROL_LOW			    0x150
-#define MV64460_CPU_CROSS_BAR_CONTROL_HIGH			    0x158
-#define MV64460_CPU_CROSS_BAR_TIMEOUT				    0x168
-
-/****************************************/
-/* SMP RegisterS			*/
-/****************************************/
-
-#define MV64460_SMP_WHO_AM_I					    0x200
-#define MV64460_SMP_CPU0_DOORBELL				    0x214
-#define MV64460_SMP_CPU0_DOORBELL_CLEAR				    0x21C
-#define MV64460_SMP_CPU1_DOORBELL				    0x224
-#define MV64460_SMP_CPU1_DOORBELL_CLEAR				    0x22C
-#define MV64460_SMP_CPU0_DOORBELL_MASK				    0x234
-#define MV64460_SMP_CPU1_DOORBELL_MASK				    0x23C
-#define MV64460_SMP_SEMAPHOR0					    0x244
-#define MV64460_SMP_SEMAPHOR1					    0x24c
-#define MV64460_SMP_SEMAPHOR2					    0x254
-#define MV64460_SMP_SEMAPHOR3					    0x25c
-#define MV64460_SMP_SEMAPHOR4					    0x264
-#define MV64460_SMP_SEMAPHOR5					    0x26c
-#define MV64460_SMP_SEMAPHOR6					    0x274
-#define MV64460_SMP_SEMAPHOR7					    0x27c
-
-/****************************************/
-/*  CPU Sync Barrier Register		*/
-/****************************************/
-
-#define MV64460_CPU_0_SYNC_BARRIER_TRIGGER			    0x0c0
-#define MV64460_CPU_0_SYNC_BARRIER_VIRTUAL			    0x0c8
-#define MV64460_CPU_1_SYNC_BARRIER_TRIGGER			    0x0d0
-#define MV64460_CPU_1_SYNC_BARRIER_VIRTUAL			    0x0d8
-
-/****************************************/
-/* CPU Access Protect			*/
-/****************************************/
-
-#define MV64460_CPU_PROTECT_WINDOW_0_BASE_ADDR			    0x180
-#define MV64460_CPU_PROTECT_WINDOW_0_SIZE			    0x188
-#define MV64460_CPU_PROTECT_WINDOW_1_BASE_ADDR			    0x190
-#define MV64460_CPU_PROTECT_WINDOW_1_SIZE			    0x198
-#define MV64460_CPU_PROTECT_WINDOW_2_BASE_ADDR			    0x1a0
-#define MV64460_CPU_PROTECT_WINDOW_2_SIZE			    0x1a8
-#define MV64460_CPU_PROTECT_WINDOW_3_BASE_ADDR			    0x1b0
-#define MV64460_CPU_PROTECT_WINDOW_3_SIZE			    0x1b8
-
-
-/****************************************/
-/*	    CPU Error Report		*/
-/****************************************/
-
-#define MV64460_CPU_ERROR_ADDR_LOW				    0x070
-#define MV64460_CPU_ERROR_ADDR_HIGH				    0x078
-#define MV64460_CPU_ERROR_DATA_LOW				    0x128
-#define MV64460_CPU_ERROR_DATA_HIGH				    0x130
-#define MV64460_CPU_ERROR_PARITY				    0x138
-#define MV64460_CPU_ERROR_CAUSE					    0x140
-#define MV64460_CPU_ERROR_MASK					    0x148
-
-/****************************************/
-/*	CPU Interface Debug Registers	*/
-/****************************************/
-
-#define MV64460_PUNIT_SLAVE_DEBUG_LOW				    0x360
-#define MV64460_PUNIT_SLAVE_DEBUG_HIGH				    0x368
-#define MV64460_PUNIT_MASTER_DEBUG_LOW				    0x370
-#define MV64460_PUNIT_MASTER_DEBUG_HIGH				    0x378
-#define MV64460_PUNIT_MMASK					    0x3e4
-
-/****************************************/
-/*  Integrated SRAM Registers		*/
-/****************************************/
-
-#define MV64460_SRAM_CONFIG					    0x380
-#define MV64460_SRAM_TEST_MODE					    0X3F4
-#define MV64460_SRAM_ERROR_CAUSE				    0x388
-#define MV64460_SRAM_ERROR_ADDR					    0x390
-#define MV64460_SRAM_ERROR_ADDR_HIGH				    0X3F8
-#define MV64460_SRAM_ERROR_DATA_LOW				    0x398
-#define MV64460_SRAM_ERROR_DATA_HIGH				    0x3a0
-#define MV64460_SRAM_ERROR_DATA_PARITY				    0x3a8
-
-/****************************************/
-/* SDRAM Configuration			*/
-/****************************************/
-
-#define MV64460_SDRAM_CONFIG					    0x1400
-#define MV64460_D_UNIT_CONTROL_LOW				    0x1404
-#define MV64460_D_UNIT_CONTROL_HIGH				    0x1424
-#define MV64460_D_UNIT_MMASK					    0x14B0
-#define MV64460_SDRAM_TIMING_CONTROL_LOW			    0x1408
-#define MV64460_SDRAM_TIMING_CONTROL_HIGH			    0x140c
-#define MV64460_SDRAM_ADDR_CONTROL				    0x1410
-#define MV64460_SDRAM_OPEN_PAGES_CONTROL			    0x1414
-#define MV64460_SDRAM_OPERATION					    0x1418
-#define MV64460_SDRAM_MODE					    0x141c
-#define MV64460_EXTENDED_DRAM_MODE				    0x1420
-#define MV64460_SDRAM_CROSS_BAR_CONTROL_LOW			    0x1430
-#define MV64460_SDRAM_CROSS_BAR_CONTROL_HIGH			    0x1434
-#define MV64460_SDRAM_CROSS_BAR_TIMEOUT				    0x1438
-#define MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION		    0x14c0
-#define MV64460_SDRAM_DATA_PADS_CALIBRATION			    0x14c4
-
-/****************************************/
-/* SDRAM Error Report			*/
-/****************************************/
-
-#define MV64460_SDRAM_ERROR_DATA_LOW				    0x1444
-#define MV64460_SDRAM_ERROR_DATA_HIGH				    0x1440
-#define MV64460_SDRAM_ERROR_ADDR				    0x1450
-#define MV64460_SDRAM_RECEIVED_ECC				    0x1448
-#define MV64460_SDRAM_CALCULATED_ECC				    0x144c
-#define MV64460_SDRAM_ECC_CONTROL				    0x1454
-#define MV64460_SDRAM_ECC_ERROR_COUNTER				    0x1458
-
-/******************************************/
-/*  Controlled Delay Line (CDL) Registers */
-/******************************************/
-
-#define MV64460_DFCDL_CONFIG0					    0x1480
-#define MV64460_DFCDL_CONFIG1					    0x1484
-#define MV64460_DLL_WRITE					    0x1488
-#define MV64460_DLL_READ					    0x148c
-#define MV64460_SRAM_ADDR					    0x1490
-#define MV64460_SRAM_DATA0					    0x1494
-#define MV64460_SRAM_DATA1					    0x1498
-#define MV64460_SRAM_DATA2					    0x149c
-#define MV64460_DFCL_PROBE					    0x14a0
-
-/******************************************/
-/*   Debug Registers			  */
-/******************************************/
-
-#define MV64460_DUNIT_DEBUG_LOW					    0x1460
-#define MV64460_DUNIT_DEBUG_HIGH				    0x1464
-#define MV64460_DUNIT_MMASK					    0X1b40
-
-/****************************************/
-/* Device Parameters			*/
-/****************************************/
-
-#define MV64460_DEVICE_BANK0_PARAMETERS				    0x45c
-#define MV64460_DEVICE_BANK1_PARAMETERS				    0x460
-#define MV64460_DEVICE_BANK2_PARAMETERS				    0x464
-#define MV64460_DEVICE_BANK3_PARAMETERS				    0x468
-#define MV64460_DEVICE_BOOT_BANK_PARAMETERS			    0x46c
-#define MV64460_DEVICE_INTERFACE_CONTROL			    0x4c0
-#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		    0x4c8
-#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		    0x4cc
-#define MV64460_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT		    0x4c4
-
-/****************************************/
-/* Device interrupt registers		*/
-/****************************************/
-
-#define MV64460_DEVICE_INTERRUPT_CAUSE				    0x4d0
-#define MV64460_DEVICE_INTERRUPT_MASK				    0x4d4
-#define MV64460_DEVICE_ERROR_ADDR				    0x4d8
-#define MV64460_DEVICE_ERROR_DATA				    0x4dc
-#define MV64460_DEVICE_ERROR_PARITY				    0x4e0
-
-/****************************************/
-/* Device debug registers		*/
-/****************************************/
-
-#define MV64460_DEVICE_DEBUG_LOW				    0x4e4
-#define MV64460_DEVICE_DEBUG_HIGH				    0x4e8
-#define MV64460_RUNIT_MMASK					    0x4f0
-
-/****************************************/
-/* PCI Slave Address Decoding registers */
-/****************************************/
-
-#define MV64460_PCI_0_CS_0_BANK_SIZE				    0xc08
-#define MV64460_PCI_1_CS_0_BANK_SIZE				    0xc88
-#define MV64460_PCI_0_CS_1_BANK_SIZE				    0xd08
-#define MV64460_PCI_1_CS_1_BANK_SIZE				    0xd88
-#define MV64460_PCI_0_CS_2_BANK_SIZE				    0xc0c
-#define MV64460_PCI_1_CS_2_BANK_SIZE				    0xc8c
-#define MV64460_PCI_0_CS_3_BANK_SIZE				    0xd0c
-#define MV64460_PCI_1_CS_3_BANK_SIZE				    0xd8c
-#define MV64460_PCI_0_DEVCS_0_BANK_SIZE				    0xc10
-#define MV64460_PCI_1_DEVCS_0_BANK_SIZE				    0xc90
-#define MV64460_PCI_0_DEVCS_1_BANK_SIZE				    0xd10
-#define MV64460_PCI_1_DEVCS_1_BANK_SIZE				    0xd90
-#define MV64460_PCI_0_DEVCS_2_BANK_SIZE				    0xd18
-#define MV64460_PCI_1_DEVCS_2_BANK_SIZE				    0xd98
-#define MV64460_PCI_0_DEVCS_3_BANK_SIZE				    0xc14
-#define MV64460_PCI_1_DEVCS_3_BANK_SIZE				    0xc94
-#define MV64460_PCI_0_DEVCS_BOOT_BANK_SIZE			    0xd14
-#define MV64460_PCI_1_DEVCS_BOOT_BANK_SIZE			    0xd94
-#define MV64460_PCI_0_P2P_MEM0_BAR_SIZE				    0xd1c
-#define MV64460_PCI_1_P2P_MEM0_BAR_SIZE				    0xd9c
-#define MV64460_PCI_0_P2P_MEM1_BAR_SIZE				    0xd20
-#define MV64460_PCI_1_P2P_MEM1_BAR_SIZE				    0xda0
-#define MV64460_PCI_0_P2P_I_O_BAR_SIZE				    0xd24
-#define MV64460_PCI_1_P2P_I_O_BAR_SIZE				    0xda4
-#define MV64460_PCI_0_CPU_BAR_SIZE				    0xd28
-#define MV64460_PCI_1_CPU_BAR_SIZE				    0xda8
-#define MV64460_PCI_0_INTERNAL_SRAM_BAR_SIZE			    0xe00
-#define MV64460_PCI_1_INTERNAL_SRAM_BAR_SIZE			    0xe80
-#define MV64460_PCI_0_EXPANSION_ROM_BAR_SIZE			    0xd2c
-#define MV64460_PCI_1_EXPANSION_ROM_BAR_SIZE			    0xd9c
-#define MV64460_PCI_0_BASE_ADDR_REG_ENABLE			    0xc3c
-#define MV64460_PCI_1_BASE_ADDR_REG_ENABLE			    0xcbc
-#define MV64460_PCI_0_CS_0_BASE_ADDR_REMAP			    0xc48
-#define MV64460_PCI_1_CS_0_BASE_ADDR_REMAP			    0xcc8
-#define MV64460_PCI_0_CS_1_BASE_ADDR_REMAP			    0xd48
-#define MV64460_PCI_1_CS_1_BASE_ADDR_REMAP			    0xdc8
-#define MV64460_PCI_0_CS_2_BASE_ADDR_REMAP			    0xc4c
-#define MV64460_PCI_1_CS_2_BASE_ADDR_REMAP			    0xccc
-#define MV64460_PCI_0_CS_3_BASE_ADDR_REMAP			    0xd4c
-#define MV64460_PCI_1_CS_3_BASE_ADDR_REMAP			    0xdcc
-#define MV64460_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP			    0xF04
-#define MV64460_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP			    0xF84
-#define MV64460_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP			    0xF08
-#define MV64460_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP			    0xF88
-#define MV64460_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP			    0xF0C
-#define MV64460_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP			    0xF8C
-#define MV64460_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP			    0xF10
-#define MV64460_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP			    0xF90
-#define MV64460_PCI_0_DEVCS_0_BASE_ADDR_REMAP			    0xc50
-#define MV64460_PCI_1_DEVCS_0_BASE_ADDR_REMAP			    0xcd0
-#define MV64460_PCI_0_DEVCS_1_BASE_ADDR_REMAP			    0xd50
-#define MV64460_PCI_1_DEVCS_1_BASE_ADDR_REMAP			    0xdd0
-#define MV64460_PCI_0_DEVCS_2_BASE_ADDR_REMAP			    0xd58
-#define MV64460_PCI_1_DEVCS_2_BASE_ADDR_REMAP			    0xdd8
-#define MV64460_PCI_0_DEVCS_3_BASE_ADDR_REMAP			    0xc54
-#define MV64460_PCI_1_DEVCS_3_BASE_ADDR_REMAP			    0xcd4
-#define MV64460_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xd54
-#define MV64460_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xdd4
-#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xd5c
-#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xddc
-#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xd60
-#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xde0
-#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xd64
-#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xde4
-#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xd68
-#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xde8
-#define MV64460_PCI_0_P2P_I_O_BASE_ADDR_REMAP			    0xd6c
-#define MV64460_PCI_1_P2P_I_O_BASE_ADDR_REMAP			    0xdec
-#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_LOW			    0xd70
-#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_LOW			    0xdf0
-#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_HIGH			    0xd74
-#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_HIGH			    0xdf4
-#define MV64460_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf00
-#define MV64460_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf80
-#define MV64460_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		    0xf38
-#define MV64460_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		    0xfb8
-#define MV64460_PCI_0_ADDR_DECODE_CONTROL			    0xd3c
-#define MV64460_PCI_1_ADDR_DECODE_CONTROL			    0xdbc
-#define MV64460_PCI_0_HEADERS_RETARGET_CONTROL			    0xF40
-#define MV64460_PCI_1_HEADERS_RETARGET_CONTROL			    0xFc0
-#define MV64460_PCI_0_HEADERS_RETARGET_BASE			    0xF44
-#define MV64460_PCI_1_HEADERS_RETARGET_BASE			    0xFc4
-#define MV64460_PCI_0_HEADERS_RETARGET_HIGH			    0xF48
-#define MV64460_PCI_1_HEADERS_RETARGET_HIGH			    0xFc8
-
-/***********************************/
-/*   PCI Control Register Map	   */
-/***********************************/
-
-#define MV64460_PCI_0_DLL_STATUS_AND_COMMAND			    0x1d20
-#define MV64460_PCI_1_DLL_STATUS_AND_COMMAND			    0x1da0
-#define MV64460_PCI_0_MPP_PADS_DRIVE_CONTROL			    0x1d1C
-#define MV64460_PCI_1_MPP_PADS_DRIVE_CONTROL			    0x1d9C
-#define MV64460_PCI_0_COMMAND					    0xc00
-#define MV64460_PCI_1_COMMAND					    0xc80
-#define MV64460_PCI_0_MODE					    0xd00
-#define MV64460_PCI_1_MODE					    0xd80
-#define MV64460_PCI_0_RETRY					    0xc04
-#define MV64460_PCI_1_RETRY					    0xc84
-#define MV64460_PCI_0_READ_BUFFER_DISCARD_TIMER			    0xd04
-#define MV64460_PCI_1_READ_BUFFER_DISCARD_TIMER			    0xd84
-#define MV64460_PCI_0_MSI_TRIGGER_TIMER				    0xc38
-#define MV64460_PCI_1_MSI_TRIGGER_TIMER				    0xcb8
-#define MV64460_PCI_0_ARBITER_CONTROL				    0x1d00
-#define MV64460_PCI_1_ARBITER_CONTROL				    0x1d80
-#define MV64460_PCI_0_CROSS_BAR_CONTROL_LOW			    0x1d08
-#define MV64460_PCI_1_CROSS_BAR_CONTROL_LOW			    0x1d88
-#define MV64460_PCI_0_CROSS_BAR_CONTROL_HIGH			    0x1d0c
-#define MV64460_PCI_1_CROSS_BAR_CONTROL_HIGH			    0x1d8c
-#define MV64460_PCI_0_CROSS_BAR_TIMEOUT				    0x1d04
-#define MV64460_PCI_1_CROSS_BAR_TIMEOUT				    0x1d84
-#define MV64460_PCI_0_SYNC_BARRIER_TRIGGER_REG			    0x1D18
-#define MV64460_PCI_1_SYNC_BARRIER_TRIGGER_REG			    0x1D98
-#define MV64460_PCI_0_SYNC_BARRIER_VIRTUAL_REG			    0x1d10
-#define MV64460_PCI_1_SYNC_BARRIER_VIRTUAL_REG			    0x1d90
-#define MV64460_PCI_0_P2P_CONFIG				    0x1d14
-#define MV64460_PCI_1_P2P_CONFIG				    0x1d94
-
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_LOW			    0x1e00
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_HIGH		    0x1e04
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_0			    0x1e08
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_LOW			    0x1e10
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_HIGH		    0x1e14
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_1			    0x1e18
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_LOW			    0x1e20
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_HIGH		    0x1e24
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_2			    0x1e28
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_LOW			    0x1e30
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_HIGH		    0x1e34
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_3			    0x1e38
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_LOW			    0x1e40
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_HIGH		    0x1e44
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_4			    0x1e48
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_LOW			    0x1e50
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_HIGH		    0x1e54
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_5			    0x1e58
-
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_LOW			    0x1e80
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_HIGH		    0x1e84
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_0			    0x1e88
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_LOW			    0x1e90
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_HIGH		    0x1e94
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_1			    0x1e98
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_LOW			    0x1ea0
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_HIGH		    0x1ea4
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_2			    0x1ea8
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_LOW			    0x1eb0
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_HIGH		    0x1eb4
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_3			    0x1eb8
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_LOW			    0x1ec0
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_HIGH		    0x1ec4
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_4			    0x1ec8
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_LOW			    0x1ed0
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_HIGH		    0x1ed4
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_5			    0x1ed8
-
-/****************************************/
-/*   PCI Configuration Access Registers */
-/****************************************/
-
-#define MV64460_PCI_0_CONFIG_ADDR				    0xcf8
-#define MV64460_PCI_0_CONFIG_DATA_VIRTUAL_REG			    0xcfc
-#define MV64460_PCI_1_CONFIG_ADDR				    0xc78
-#define MV64460_PCI_1_CONFIG_DATA_VIRTUAL_REG			    0xc7c
-#define MV64460_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xc34
-#define MV64460_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xcb4
-
-/****************************************/
-/*   PCI Error Report Registers		*/
-/****************************************/
-
-#define MV64460_PCI_0_SERR_MASK					    0xc28
-#define MV64460_PCI_1_SERR_MASK					    0xca8
-#define MV64460_PCI_0_ERROR_ADDR_LOW				    0x1d40
-#define MV64460_PCI_1_ERROR_ADDR_LOW				    0x1dc0
-#define MV64460_PCI_0_ERROR_ADDR_HIGH				    0x1d44
-#define MV64460_PCI_1_ERROR_ADDR_HIGH				    0x1dc4
-#define MV64460_PCI_0_ERROR_ATTRIBUTE				    0x1d48
-#define MV64460_PCI_1_ERROR_ATTRIBUTE				    0x1dc8
-#define MV64460_PCI_0_ERROR_COMMAND				    0x1d50
-#define MV64460_PCI_1_ERROR_COMMAND				    0x1dd0
-#define MV64460_PCI_0_ERROR_CAUSE				    0x1d58
-#define MV64460_PCI_1_ERROR_CAUSE				    0x1dd8
-#define MV64460_PCI_0_ERROR_MASK				    0x1d5c
-#define MV64460_PCI_1_ERROR_MASK				    0x1ddc
-
-/****************************************/
-/*   PCI Debug Registers		*/
-/****************************************/
-
-#define MV64460_PCI_0_MMASK					    0X1D24
-#define MV64460_PCI_1_MMASK					    0X1DA4
-
-/*********************************************/
-/* PCI Configuration, Function 0, Registers  */
-/*********************************************/
-
-#define MV64460_PCI_DEVICE_AND_VENDOR_ID			    0x000
-#define MV64460_PCI_STATUS_AND_COMMAND				    0x004
-#define MV64460_PCI_CLASS_CODE_AND_REVISION_ID			    0x008
-#define MV64460_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	    0x00C
-
-#define MV64460_PCI_SCS_0_BASE_ADDR_LOW				    0x010
-#define MV64460_PCI_SCS_0_BASE_ADDR_HIGH			    0x014
-#define MV64460_PCI_SCS_1_BASE_ADDR_LOW				    0x018
-#define MV64460_PCI_SCS_1_BASE_ADDR_HIGH			    0x01C
-#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW	    0x020
-#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH	    0x024
-#define MV64460_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	    0x02c
-#define MV64460_PCI_EXPANSION_ROM_BASE_ADDR_REG			    0x030
-#define MV64460_PCI_CAPABILTY_LIST_POINTER			    0x034
-#define MV64460_PCI_INTERRUPT_PIN_AND_LINE			    0x03C
-       /* capability list */
-#define MV64460_PCI_POWER_MANAGEMENT_CAPABILITY			    0x040
-#define MV64460_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044
-#define MV64460_PCI_VPD_ADDR					    0x048
-#define MV64460_PCI_VPD_DATA					    0x04c
-#define MV64460_PCI_MSI_MESSAGE_CONTROL				    0x050
-#define MV64460_PCI_MSI_MESSAGE_ADDR				    0x054
-#define MV64460_PCI_MSI_MESSAGE_UPPER_ADDR			    0x058
-#define MV64460_PCI_MSI_MESSAGE_DATA				    0x05c
-#define MV64460_PCI_X_COMMAND					    0x060
-#define MV64460_PCI_X_STATUS					    0x064
-#define MV64460_PCI_COMPACT_PCI_HOT_SWAP			    0x068
-
-/***********************************************/
-/*   PCI Configuration, Function 1, Registers  */
-/***********************************************/
-
-#define MV64460_PCI_SCS_2_BASE_ADDR_LOW				    0x110
-#define MV64460_PCI_SCS_2_BASE_ADDR_HIGH			    0x114
-#define MV64460_PCI_SCS_3_BASE_ADDR_LOW				    0x118
-#define MV64460_PCI_SCS_3_BASE_ADDR_HIGH			    0x11c
-#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_LOW			    0x120
-#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH		    0x124
-
-/***********************************************/
-/*  PCI Configuration, Function 2, Registers   */
-/***********************************************/
-
-#define MV64460_PCI_DEVCS_0_BASE_ADDR_LOW			    0x210
-#define MV64460_PCI_DEVCS_0_BASE_ADDR_HIGH			    0x214
-#define MV64460_PCI_DEVCS_1_BASE_ADDR_LOW			    0x218
-#define MV64460_PCI_DEVCS_1_BASE_ADDR_HIGH			    0x21c
-#define MV64460_PCI_DEVCS_2_BASE_ADDR_LOW			    0x220
-#define MV64460_PCI_DEVCS_2_BASE_ADDR_HIGH			    0x224
-
-/***********************************************/
-/*  PCI Configuration, Function 3, Registers   */
-/***********************************************/
-
-#define MV64460_PCI_DEVCS_3_BASE_ADDR_LOW			    0x310
-#define MV64460_PCI_DEVCS_3_BASE_ADDR_HIGH			    0x314
-#define MV64460_PCI_BOOT_CS_BASE_ADDR_LOW			    0x318
-#define MV64460_PCI_BOOT_CS_BASE_ADDR_HIGH			    0x31c
-#define MV64460_PCI_CPU_BASE_ADDR_LOW				    0x220
-#define MV64460_PCI_CPU_BASE_ADDR_HIGH				    0x224
-
-/***********************************************/
-/*  PCI Configuration, Function 4, Registers   */
-/***********************************************/
-
-#define MV64460_PCI_P2P_MEM0_BASE_ADDR_LOW			    0x410
-#define MV64460_PCI_P2P_MEM0_BASE_ADDR_HIGH			    0x414
-#define MV64460_PCI_P2P_MEM1_BASE_ADDR_LOW			    0x418
-#define MV64460_PCI_P2P_MEM1_BASE_ADDR_HIGH			    0x41c
-#define MV64460_PCI_P2P_I_O_BASE_ADDR				    0x420
-#define MV64460_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR		    0x424
-
-/****************************************/
-/* Messaging Unit Registers (I20)	*/
-/****************************************/
-
-#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x010
-#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x014
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x018
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x01C
-#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE		    0x020
-#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x024
-#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x028
-#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE		    0x02C
-#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x030
-#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x034
-#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x040
-#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x044
-#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE		    0x050
-#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE		    0x054
-#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x060
-#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x064
-#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x068
-#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x06C
-#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x070
-#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x074
-#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x0F8
-#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x0FC
-
-#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x090
-#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x094
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x098
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x09C
-#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0A0
-#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0A4
-#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0A8
-#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0AC
-#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0B0
-#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0B4
-#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C0
-#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C4
-#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE		    0x0D0
-#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE		    0x0D4
-#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E0
-#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0E4
-#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E8
-#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x0EC
-#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0F0
-#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0F4
-#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x078
-#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x07C
-
-#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C10
-#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C14
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C18
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C1C
-#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C20
-#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C24
-#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C28
-#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C2C
-#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C30
-#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C34
-#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C40
-#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C44
-#define MV64460_I2O_QUEUE_CONTROL_REG_CPU0_SIDE			    0x1C50
-#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE		    0x1C54
-#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C60
-#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C64
-#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1C68
-#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1C6C
-#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C70
-#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C74
-#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1CF8
-#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1CFC
-#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C90
-#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C94
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C98
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C9C
-#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CA0
-#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CA4
-#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CA8
-#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CAC
-#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CB0
-#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CB4
-#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC0
-#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC4
-#define MV64460_I2O_QUEUE_CONTROL_REG_CPU1_SIDE			    0x1CD0
-#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE		    0x1CD4
-#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE0
-#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CE4
-#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE8
-#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1CEC
-#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CF0
-#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CF4
-#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1C78
-#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1C7C
-
-/****************************************/
-/*	  Ethernet Unit Registers		*/
-/****************************************/
-
-#define MV64460_ETH_PHY_ADDR_REG				    0x2000
-#define MV64460_ETH_SMI_REG					    0x2004
-#define MV64460_ETH_UNIT_DEFAULT_ADDR_REG			    0x2008
-#define MV64460_ETH_UNIT_DEFAULTID_REG				    0x200c
-#define MV64460_ETH_UNIT_INTERRUPT_CAUSE_REG			    0x2080
-#define MV64460_ETH_UNIT_INTERRUPT_MASK_REG			    0x2084
-#define MV64460_ETH_UNIT_INTERNAL_USE_REG			    0x24fc
-#define MV64460_ETH_UNIT_ERROR_ADDR_REG				    0x2094
-#define MV64460_ETH_BAR_0					    0x2200
-#define MV64460_ETH_BAR_1					    0x2208
-#define MV64460_ETH_BAR_2					    0x2210
-#define MV64460_ETH_BAR_3					    0x2218
-#define MV64460_ETH_BAR_4					    0x2220
-#define MV64460_ETH_BAR_5					    0x2228
-#define MV64460_ETH_SIZE_REG_0					    0x2204
-#define MV64460_ETH_SIZE_REG_1					    0x220c
-#define MV64460_ETH_SIZE_REG_2					    0x2214
-#define MV64460_ETH_SIZE_REG_3					    0x221c
-#define MV64460_ETH_SIZE_REG_4					    0x2224
-#define MV64460_ETH_SIZE_REG_5					    0x222c
-#define MV64460_ETH_HEADERS_RETARGET_BASE_REG			    0x2230
-#define MV64460_ETH_HEADERS_RETARGET_CONTROL_REG		    0x2234
-#define MV64460_ETH_HIGH_ADDR_REMAP_REG_0			    0x2280
-#define MV64460_ETH_HIGH_ADDR_REMAP_REG_1			    0x2284
-#define MV64460_ETH_HIGH_ADDR_REMAP_REG_2			    0x2288
-#define MV64460_ETH_HIGH_ADDR_REMAP_REG_3			    0x228c
-#define MV64460_ETH_BASE_ADDR_ENABLE_REG			    0x2290
-#define MV64460_ETH_ACCESS_PROTECTION_REG(port)			   (0x2294 + (port<<2))
-#define MV64460_ETH_MIB_COUNTERS_BASE(port)			   (0x3000 + (port<<7))
-#define MV64460_ETH_PORT_CONFIG_REG(port)			   (0x2400 + (port<<10))
-#define MV64460_ETH_PORT_CONFIG_EXTEND_REG(port)		   (0x2404 + (port<<10))
-#define MV64460_ETH_MII_SERIAL_PARAMETRS_REG(port)		   (0x2408 + (port<<10))
-#define MV64460_ETH_GMII_SERIAL_PARAMETRS_REG(port)		   (0x240c + (port<<10))
-#define MV64460_ETH_VLAN_ETHERTYPE_REG(port)			   (0x2410 + (port<<10))
-#define MV64460_ETH_MAC_ADDR_LOW(port)				   (0x2414 + (port<<10))
-#define MV64460_ETH_MAC_ADDR_HIGH(port)				   (0x2418 + (port<<10))
-#define MV64460_ETH_SDMA_CONFIG_REG(port)			   (0x241c + (port<<10))
-#define MV64460_ETH_DSCP_0(port)				   (0x2420 + (port<<10))
-#define MV64460_ETH_DSCP_1(port)				   (0x2424 + (port<<10))
-#define MV64460_ETH_DSCP_2(port)				   (0x2428 + (port<<10))
-#define MV64460_ETH_DSCP_3(port)				   (0x242c + (port<<10))
-#define MV64460_ETH_DSCP_4(port)				   (0x2430 + (port<<10))
-#define MV64460_ETH_DSCP_5(port)				   (0x2434 + (port<<10))
-#define MV64460_ETH_DSCP_6(port)				   (0x2438 + (port<<10))
-#define MV64460_ETH_PORT_SERIAL_CONTROL_REG(port)		   (0x243c + (port<<10))
-#define MV64460_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		   (0x2440 + (port<<10))
-#define MV64460_ETH_PORT_STATUS_REG(port)			   (0x2444 + (port<<10))
-#define MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(port)		   (0x2448 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_FIXED_PRIORITY(port)		   (0x244c + (port<<10))
-#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)	   (0x2450 + (port<<10))
-#define MV64460_ETH_MAXIMUM_TRANSMIT_UNIT(port)			   (0x2458 + (port<<10))
-#define MV64460_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)	   (0x245c + (port<<10))
-#define MV64460_ETH_INTERRUPT_CAUSE_REG(port)			   (0x2460 + (port<<10))
-#define MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG(port)		   (0x2464 + (port<<10))
-#define MV64460_ETH_INTERRUPT_MASK_REG(port)			   (0x2468 + (port<<10))
-#define MV64460_ETH_INTERRUPT_EXTEND_MASK_REG(port)		   (0x246c + (port<<10))
-#define MV64460_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2470 + (port<<10))
-#define MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2474 + (port<<10))
-#define MV64460_ETH_RX_MINIMAL_FRAME_SIZE_REG(port)		   (0x247c + (port<<10))
-#define MV64460_ETH_RX_DISCARDED_FRAMES_COUNTER(port)		   (0x2484 + (port<<10)
-#define MV64460_ETH_PORT_DEBUG_0_REG(port)			   (0x248c + (port<<10))
-#define MV64460_ETH_PORT_DEBUG_1_REG(port)			   (0x2490 + (port<<10))
-#define MV64460_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)		   (0x2494 + (port<<10))
-#define MV64460_ETH_INTERNAL_USE_REG(port)			   (0x24fc + (port<<10))
-#define MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(port)		   (0x2680 + (port<<10))
-#define MV64460_ETH_CURRENT_SERVED_TX_DESC_PTR(port)		   (0x2684 + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x260c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x261c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x262c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x263c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x264c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x265c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x266c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x267c + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x26c0 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x26c4 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x26c8 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x26cc + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x26d0 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x26d4 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x26d8 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x26dc + (port<<10))
-#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)		   (0x2700 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)		   (0x2710 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)		   (0x2720 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)		   (0x2730 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)		   (0x2740 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)		   (0x2750 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)		   (0x2760 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)		   (0x2770 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)	   (0x2704 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)	   (0x2714 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)	   (0x2724 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)	   (0x2734 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)	   (0x2744 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)	   (0x2754 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)	   (0x2764 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)	   (0x2774 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_0_ARBITER_CONFIG(port)		   (0x2708 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_1_ARBITER_CONFIG(port)		   (0x2718 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_2_ARBITER_CONFIG(port)		   (0x2728 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_3_ARBITER_CONFIG(port)		   (0x2738 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_4_ARBITER_CONFIG(port)		   (0x2748 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_5_ARBITER_CONFIG(port)		   (0x2758 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_6_ARBITER_CONFIG(port)		   (0x2768 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_7_ARBITER_CONFIG(port)		   (0x2778 + (port<<10))
-#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)		   (0x2780 + (port<<10))
-#define MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
-#define MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)	   (0x3500 + (port<<10))
-#define MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE(port)		   (0x3600 + (port<<10))
-
-/*******************************************/
-/*	    CUNIT  Registers		   */
-/*******************************************/
-
-	 /* Address Decoding Register Map */
-
-#define MV64460_CUNIT_BASE_ADDR_REG0				    0xf200
-#define MV64460_CUNIT_BASE_ADDR_REG1				    0xf208
-#define MV64460_CUNIT_BASE_ADDR_REG2				    0xf210
-#define MV64460_CUNIT_BASE_ADDR_REG3				    0xf218
-#define MV64460_CUNIT_SIZE0					    0xf204
-#define MV64460_CUNIT_SIZE1					    0xf20c
-#define MV64460_CUNIT_SIZE2					    0xf214
-#define MV64460_CUNIT_SIZE3					    0xf21c
-#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG0			    0xf240
-#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG1			    0xf244
-#define MV64460_CUNIT_BASE_ADDR_ENABLE_REG			    0xf250
-#define MV64460_MPSC0_ACCESS_PROTECTION_REG			    0xf254
-#define MV64460_MPSC1_ACCESS_PROTECTION_REG			    0xf258
-#define MV64460_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG		    0xf25C
-
-	/*  Error Report Registers  */
-
-#define MV64460_CUNIT_INTERRUPT_CAUSE_REG			    0xf310
-#define MV64460_CUNIT_INTERRUPT_MASK_REG			    0xf314
-#define MV64460_CUNIT_ERROR_ADDR				    0xf318
-
-	/*  Cunit Control Registers */
-
-#define MV64460_CUNIT_ARBITER_CONTROL_REG			    0xf300
-#define MV64460_CUNIT_CONFIG_REG				    0xb40c
-#define MV64460_CUNIT_CRROSBAR_TIMEOUT_REG			    0xf304
-
-	/*  Cunit Debug Registers   */
-
-#define MV64460_CUNIT_DEBUG_LOW					    0xf340
-#define MV64460_CUNIT_DEBUG_HIGH				    0xf344
-#define MV64460_CUNIT_MMASK					    0xf380
-
-	/*  Cunit Base Address Enable Window Bits*/
-#define MV64460_CUNIT_BASE_ADDR_WIN_0_BIT			 0x0
-#define MV64460_CUNIT_BASE_ADDR_WIN_1_BIT			 0x1
-#define MV64460_CUNIT_BASE_ADDR_WIN_2_BIT			 0x2
-#define MV64460_CUNIT_BASE_ADDR_WIN_3_BIT			 0x3
-
-	/*  MPSCs Clocks Routing Registers  */
-
-#define MV64460_MPSC_ROUTING_REG				    0xb400
-#define MV64460_MPSC_RX_CLOCK_ROUTING_REG			    0xb404
-#define MV64460_MPSC_TX_CLOCK_ROUTING_REG			    0xb408
-
-	/*  MPSCs Interrupts Registers	  */
-
-#define MV64460_MPSC_CAUSE_REG(port)				   (0xb804 + (port<<3))
-#define MV64460_MPSC_MASK_REG(port)				   (0xb884 + (port<<3))
-
-#define MV64460_MPSC_MAIN_CONFIG_LOW(port)			   (0x8000 + (port<<12))
-#define MV64460_MPSC_MAIN_CONFIG_HIGH(port)			   (0x8004 + (port<<12))
-#define MV64460_MPSC_PROTOCOL_CONFIG(port)			   (0x8008 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG1(port)				   (0x800c + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG2(port)				   (0x8010 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG3(port)				   (0x8014 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG4(port)				   (0x8018 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG5(port)				   (0x801c + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG6(port)				   (0x8020 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG7(port)				   (0x8024 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG8(port)				   (0x8028 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG9(port)				   (0x802c + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG10(port)			   (0x8030 + (port<<12))
-
-	/*  MPSC0 Registers	 */
-
-
-/***************************************/
-/*	    SDMA Registers	       */
-/***************************************/
-
-#define MV64460_SDMA_CONFIG_REG(channel)			(0x4000 + (channel<<13))
-#define MV64460_SDMA_COMMAND_REG(channel)			(0x4008 + (channel<<13))
-#define MV64460_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)	(0x4810 + (channel<<13))
-#define MV64460_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
-#define MV64460_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))
-
-#define MV64460_SDMA_CAUSE_REG					    0xb800
-#define MV64460_SDMA_MASK_REG					    0xb880
-
-
-/****************************************/
-/* SDMA Address Space Targets		*/
-/****************************************/
-
-#define MV64460_SDMA_DRAM_CS_0_TARGET				    0x0e00
-#define MV64460_SDMA_DRAM_CS_1_TARGET				    0x0d00
-#define MV64460_SDMA_DRAM_CS_2_TARGET				    0x0b00
-#define MV64460_SDMA_DRAM_CS_3_TARGET				    0x0700
-
-#define MV64460_SDMA_DEV_CS_0_TARGET				    0x1e01
-#define MV64460_SDMA_DEV_CS_1_TARGET				    0x1d01
-#define MV64460_SDMA_DEV_CS_2_TARGET				    0x1b01
-#define MV64460_SDMA_DEV_CS_3_TARGET				    0x1701
-
-#define MV64460_SDMA_BOOT_CS_TARGET				    0x0f00
-
-#define MV64460_SDMA_SRAM_TARGET				    0x0003
-#define MV64460_SDMA_60X_BUS_TARGET				    0x4003
-
-#define MV64460_PCI_0_TARGET					    0x0003
-#define MV64460_PCI_1_TARGET					    0x0004
-
-
-/* Devices BAR and size registers */
-
-#define MV64460_DEV_CS0_BASE_ADDR				    0x028
-#define MV64460_DEV_CS0_SIZE					    0x030
-#define MV64460_DEV_CS1_BASE_ADDR				    0x228
-#define MV64460_DEV_CS1_SIZE					    0x230
-#define MV64460_DEV_CS2_BASE_ADDR				    0x248
-#define MV64460_DEV_CS2_SIZE					    0x250
-#define MV64460_DEV_CS3_BASE_ADDR				    0x038
-#define MV64460_DEV_CS3_SIZE					    0x040
-#define MV64460_BOOTCS_BASE_ADDR				    0x238
-#define MV64460_BOOTCS_SIZE					    0x240
-
-/* SDMA Window access protection */
-#define MV64460_SDMA_WIN_ACCESS_NOT_ALLOWED 0
-#define MV64460_SDMA_WIN_ACCESS_READ_ONLY 1
-#define MV64460_SDMA_WIN_ACCESS_FULL 2
-
-/* BRG Interrupts */
-
-#define MV64460_BRG_CONFIG_REG(brg)				 (0xb200 + (brg<<3))
-#define MV64460_BRG_BAUDE_TUNING_REG(brg)			 (0xb204 + (brg<<3))
-#define MV64460_BRG_CAUSE_REG					    0xb834
-#define MV64460_BRG_MASK_REG					    0xb8b4
-
-/****************************************/
-/* DMA Channel Control			*/
-/****************************************/
-
-#define MV64460_DMA_CHANNEL0_CONTROL				    0x840
-#define MV64460_DMA_CHANNEL0_CONTROL_HIGH			    0x880
-#define MV64460_DMA_CHANNEL1_CONTROL				    0x844
-#define MV64460_DMA_CHANNEL1_CONTROL_HIGH			    0x884
-#define MV64460_DMA_CHANNEL2_CONTROL				    0x848
-#define MV64460_DMA_CHANNEL2_CONTROL_HIGH			    0x888
-#define MV64460_DMA_CHANNEL3_CONTROL				    0x84C
-#define MV64460_DMA_CHANNEL3_CONTROL_HIGH			    0x88C
-
-
-/****************************************/
-/*	     IDMA Registers		*/
-/****************************************/
-
-#define MV64460_DMA_CHANNEL0_BYTE_COUNT				    0x800
-#define MV64460_DMA_CHANNEL1_BYTE_COUNT				    0x804
-#define MV64460_DMA_CHANNEL2_BYTE_COUNT				    0x808
-#define MV64460_DMA_CHANNEL3_BYTE_COUNT				    0x80C
-#define MV64460_DMA_CHANNEL0_SOURCE_ADDR			    0x810
-#define MV64460_DMA_CHANNEL1_SOURCE_ADDR			    0x814
-#define MV64460_DMA_CHANNEL2_SOURCE_ADDR			    0x818
-#define MV64460_DMA_CHANNEL3_SOURCE_ADDR			    0x81c
-#define MV64460_DMA_CHANNEL0_DESTINATION_ADDR			    0x820
-#define MV64460_DMA_CHANNEL1_DESTINATION_ADDR			    0x824
-#define MV64460_DMA_CHANNEL2_DESTINATION_ADDR			    0x828
-#define MV64460_DMA_CHANNEL3_DESTINATION_ADDR			    0x82C
-#define MV64460_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		    0x830
-#define MV64460_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		    0x834
-#define MV64460_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		    0x838
-#define MV64460_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		    0x83C
-#define MV64460_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		    0x870
-#define MV64460_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		    0x874
-#define MV64460_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		    0x878
-#define MV64460_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		    0x87C
-
- /*  IDMA Address Decoding Base Address Registers  */
-
-#define MV64460_DMA_BASE_ADDR_REG0				    0xa00
-#define MV64460_DMA_BASE_ADDR_REG1				    0xa08
-#define MV64460_DMA_BASE_ADDR_REG2				    0xa10
-#define MV64460_DMA_BASE_ADDR_REG3				    0xa18
-#define MV64460_DMA_BASE_ADDR_REG4				    0xa20
-#define MV64460_DMA_BASE_ADDR_REG5				    0xa28
-#define MV64460_DMA_BASE_ADDR_REG6				    0xa30
-#define MV64460_DMA_BASE_ADDR_REG7				    0xa38
-
- /*  IDMA Address Decoding Size Address Register   */
-
-#define MV64460_DMA_SIZE_REG0					    0xa04
-#define MV64460_DMA_SIZE_REG1					    0xa0c
-#define MV64460_DMA_SIZE_REG2					    0xa14
-#define MV64460_DMA_SIZE_REG3					    0xa1c
-#define MV64460_DMA_SIZE_REG4					    0xa24
-#define MV64460_DMA_SIZE_REG5					    0xa2c
-#define MV64460_DMA_SIZE_REG6					    0xa34
-#define MV64460_DMA_SIZE_REG7					    0xa3C
-
- /* IDMA Address Decoding High Address Remap and Access
-		  Protection Registers			  */
-
-#define MV64460_DMA_HIGH_ADDR_REMAP_REG0			    0xa60
-#define MV64460_DMA_HIGH_ADDR_REMAP_REG1			    0xa64
-#define MV64460_DMA_HIGH_ADDR_REMAP_REG2			    0xa68
-#define MV64460_DMA_HIGH_ADDR_REMAP_REG3			    0xa6C
-#define MV64460_DMA_BASE_ADDR_ENABLE_REG			    0xa80
-#define MV64460_DMA_CHANNEL0_ACCESS_PROTECTION_REG		    0xa70
-#define MV64460_DMA_CHANNEL1_ACCESS_PROTECTION_REG		    0xa74
-#define MV64460_DMA_CHANNEL2_ACCESS_PROTECTION_REG		    0xa78
-#define MV64460_DMA_CHANNEL3_ACCESS_PROTECTION_REG		    0xa7c
-#define MV64460_DMA_ARBITER_CONTROL				    0x860
-#define MV64460_DMA_CROSS_BAR_TIMEOUT				    0x8d0
-
- /*  IDMA Headers Retarget Registers   */
-
-#define MV64460_DMA_HEADERS_RETARGET_CONTROL			    0xa84
-#define MV64460_DMA_HEADERS_RETARGET_BASE			    0xa88
-
- /*  IDMA Interrupt Register  */
-
-#define MV64460_DMA_INTERRUPT_CAUSE_REG				    0x8c0
-#define MV64460_DMA_INTERRUPT_CAUSE_MASK			    0x8c4
-#define MV64460_DMA_ERROR_ADDR					    0x8c8
-#define MV64460_DMA_ERROR_SELECT				    0x8cc
-
- /*  IDMA Debug Register ( for internal use )	 */
-
-#define MV64460_DMA_DEBUG_LOW					    0x8e0
-#define MV64460_DMA_DEBUG_HIGH					    0x8e4
-#define MV64460_DMA_SPARE					    0xA8C
-
-/****************************************/
-/* Timer_Counter			*/
-/****************************************/
-
-#define MV64460_TIMER_COUNTER0					    0x850
-#define MV64460_TIMER_COUNTER1					    0x854
-#define MV64460_TIMER_COUNTER2					    0x858
-#define MV64460_TIMER_COUNTER3					    0x85C
-#define MV64460_TIMER_COUNTER_0_3_CONTROL			    0x864
-#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_CAUSE		    0x868
-#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_MASK		    0x86c
-
-/****************************************/
-/*	   Watchdog registers		*/
-/****************************************/
-
-#define MV64460_WATCHDOG_CONFIG_REG				    0xb410
-#define MV64460_WATCHDOG_VALUE_REG				    0xb414
-
-/****************************************/
-/* I2C Registers			*/
-/****************************************/
-
-#define MV64460_I2C_SLAVE_ADDR					    0xc000
-#define MV64460_I2C_EXTENDED_SLAVE_ADDR				    0xc010
-#define MV64460_I2C_DATA					    0xc004
-#define MV64460_I2C_CONTROL					    0xc008
-#define MV64460_I2C_STATUS_BAUDE_RATE				    0xc00C
-#define MV64460_I2C_SOFT_RESET					    0xc01c
-
-/****************************************/
-/* GPP Interface Registers		*/
-/****************************************/
-
-#define MV64460_GPP_IO_CONTROL					    0xf100
-#define MV64460_GPP_LEVEL_CONTROL				    0xf110
-#define MV64460_GPP_VALUE					    0xf104
-#define MV64460_GPP_INTERRUPT_CAUSE				    0xf108
-#define MV64460_GPP_INTERRUPT_MASK0				    0xf10c
-#define MV64460_GPP_INTERRUPT_MASK1				    0xf114
-#define MV64460_GPP_VALUE_SET					    0xf118
-#define MV64460_GPP_VALUE_CLEAR					    0xf11c
-
-/****************************************/
-/* Interrupt Controller Registers	*/
-/****************************************/
-
-/****************************************/
-/* Interrupts				*/
-/****************************************/
-
-#define MV64460_MAIN_INTERRUPT_CAUSE_LOW			    0x004
-#define MV64460_MAIN_INTERRUPT_CAUSE_HIGH			    0x00c
-#define MV64460_CPU_INTERRUPT0_MASK_LOW				    0x014
-#define MV64460_CPU_INTERRUPT0_MASK_HIGH			    0x01c
-#define MV64460_CPU_INTERRUPT0_SELECT_CAUSE			    0x024
-#define MV64460_CPU_INTERRUPT1_MASK_LOW				    0x034
-#define MV64460_CPU_INTERRUPT1_MASK_HIGH			    0x03c
-#define MV64460_CPU_INTERRUPT1_SELECT_CAUSE			    0x044
-#define MV64460_INTERRUPT0_MASK_0_LOW				    0x054
-#define MV64460_INTERRUPT0_MASK_0_HIGH				    0x05c
-#define MV64460_INTERRUPT0_SELECT_CAUSE				    0x064
-#define MV64460_INTERRUPT1_MASK_0_LOW				    0x074
-#define MV64460_INTERRUPT1_MASK_0_HIGH				    0x07c
-#define MV64460_INTERRUPT1_SELECT_CAUSE				    0x084
-
-/****************************************/
-/*	MPP Interface Registers		*/
-/****************************************/
-
-#define MV64460_MPP_CONTROL0					    0xf000
-#define MV64460_MPP_CONTROL1					    0xf004
-#define MV64460_MPP_CONTROL2					    0xf008
-#define MV64460_MPP_CONTROL3					    0xf00c
-
-/****************************************/
-/*    Serial Initialization registers	*/
-/****************************************/
-
-#define MV64460_SERIAL_INIT_LAST_DATA				    0xf324
-#define MV64460_SERIAL_INIT_CONTROL				    0xf328
-#define MV64460_SERIAL_INIT_STATUS				    0xf32c
-
-
-#endif /* __INCgt64460rh */
diff --git a/board/prodrive/p3mx/p3mx.c b/board/prodrive/p3mx/p3mx.c
deleted file mode 100644
index 28c4ebad977..00000000000
--- a/board/prodrive/p3mx/p3mx.c
+++ /dev/null
@@ -1,838 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Based on original work by
- *	Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
- *	Josh Huber, (C) Copyright 2001 Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
- * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
- * modifications for the P3M750 by roel.loeffen@prodrive.nl
- */
-
-/*
- * p3m750.c - main board support/init for the Prodrive p3m750/p3m7448.
- */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include "../../Marvell/include/memory.h"
-#include "../../Marvell/include/pci.h"
-#include "../../Marvell/include/mv_gen_reg.h"
-#include <net.h>
-#include <i2c.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "64460.h"
-#include "mv_regs.h"
-#include "p3mx.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#undef	DEBUG
-/*#define	DEBUG */
-
-#ifdef CONFIG_PCI
-#define	MAP_PCI
-#endif /* of CONFIG_PCI */
-
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-extern flash_info_t flash_info[];
-
-/* ------------------------------------------------------------------------- */
-
-/* this is the current GT register space location */
-/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
-
-/* Unfortunately, we cant change it while we are in flash, so we initialize it
- * to the "final" value. This means that any debug_led calls before
- * board_early_init_f wont work right (like in cpu_init_f).
- * See also my_remap_gt_regs below. (NTL)
- */
-
-void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
-int display_mem_map (void);
-void set_led(int);
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * This is a version of the GT register space remapping function that
- * doesn't touch globals (meaning, it's ok to run from flash.)
- *
- * Unfortunately, this has the side effect that a writable
- * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
- */
-
-void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
-{
-	u32 temp;
-
-	/* check and see if it's already moved */
-	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 16)
-		return;
-
-	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 16);
-
-	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
-}
-
-#ifdef CONFIG_PCI
-
-static void gt_pci_config (void)
-{
-	unsigned int stat;
-	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, */
-					/* FuncNum 10:8, RegNum 7:2 */
-
-	/*
-	 * In PCIX mode devices provide their own bus and device numbers.
-	 * We query the Discovery II's
-	 * config registers by writing ones to the bus and device.
-	 * We then update the Virtual register with the correct value for the
-	 * bus and device.
-	 */
-	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/* if  PCI-X */
-		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
-
-		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
-
-		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
-		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
-
-	}
-	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/* if  PCI-X */
-		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
-		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
-
-		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
-		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
-	}
-
-	/* Enable master */
-	PCI_MASTER_ENABLE (0, SELF);
-	PCI_MASTER_ENABLE (1, SELF);
-
-	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
-	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
-	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) |
-		(1 << 18);
-	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
-	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
-
-	/* ronen:
-	 * add write to pci remap registers for 64460.
-	 * in 64360 when writing to pci base go and overide remap automaticaly,
-	 * in 64460 it doesn't
-	 */
-	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
-	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
-	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
-	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
-	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
-
-	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
-
-	/* PCI interface settings */
-	/* Timeout set to retry forever */
-	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
-	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
-
-	/* ronen - enable only CS0 and Internal reg!! */
-	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-
-	/* ronen:
-	 * update the pci internal registers base address.
-	 */
-#ifdef MAP_PCI
-	for (stat = 0; stat <= PCI_HOST1; stat++)
-		pciWriteConfigReg (stat,
-				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
-				   SELF, CONFIG_SYS_GT_REGS);
-#endif
-
-}
-#endif
-
-/* Setup CPU interface paramaters */
-static void gt_cpu_config (void)
-{
-	cpu_t cpu = get_cpu_type ();
-	ulong tmp;
-
-	/* cpu configuration register */
-	tmp = GTREGREAD (CPU_CONFIGURATION);
-	/* set the SINGLE_CPU bit  see MV64460 */
-#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
-	tmp |= CPU_CONF_SINGLE_CPU;
-#endif
-	tmp &= ~CPU_CONF_AACK_DELAY_2;
-	tmp |= CPU_CONF_DP_VALID;
-	tmp |= CPU_CONF_AP_VALID;
-	tmp |= CPU_CONF_PIPELINE;
-	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
-
-	/* CPU master control register */
-	tmp = GTREGREAD (CPU_MASTER_CONTROL);
-	tmp |= CPU_MAST_CTL_ARB_EN;
-
-	if ((cpu == CPU_7400) ||
-	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
-
-		tmp |= CPU_MAST_CTL_CLEAN_BLK;
-		tmp |= CPU_MAST_CTL_FLUSH_BLK;
-
-	} else {
-		/* cleanblock must be cleared for CPUs
-		 * that do not support this command (603e, 750)
-		 * see Res#1 */
-		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
-		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
-	}
-	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
-}
-
-/*
- * board_early_init_f.
- *
- * set up gal. device mappings, etc.
- */
-int board_early_init_f (void)
-{
-	/* set up the GT the way the kernel wants it
-	 * the call to move the GT register space will obviously
-	 * fail if it has already been done, but we're going to assume
-	 * that if it's not at the power-on location, it's where we put
-	 * it last time. (huber)
-	 */
-	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
-
-#ifdef CONFIG_PCI
-	gt_pci_config ();
-#endif
-	/* mask all external interrupt sources */
-	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
-	/* new in >MV6436x */
-	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
-	/* --------------------- */
-	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
-	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
-	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
-
-	/* Device and Boot bus settings
-	 */
-	memoryMapDeviceSpace(DEVICE0, 0, 0);
-	GT_REG_WRITE(DEVICE_BANK0PARAMETERS, 0);
-	memoryMapDeviceSpace(DEVICE1, 0, 0);
-	GT_REG_WRITE(DEVICE_BANK1PARAMETERS, 0);
-	memoryMapDeviceSpace(DEVICE2, 0, 0);
-	GT_REG_WRITE(DEVICE_BANK2PARAMETERS, 0);
-	memoryMapDeviceSpace(DEVICE3, 0, 0);
-	GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0);
-
-	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_BOOT_PAR);
-
-	gt_cpu_config();
-
-	/* MPP setup */
-	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
-	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
-	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
-	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
-
-	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
-
-	set_led(LED_RED);
-
-	return 0;
-}
-
-/* various things to do after relocation */
-
-int misc_init_r ()
-{
-	u8 val;
-
-	icache_enable ();
-#ifdef CONFIG_SYS_L2
-	l2cache_enable ();
-#endif
-#ifdef CONFIG_MPSC
-	mpsc_sdma_init ();
-	mpsc_init2 ();
-#endif
-
-	/*
-	 * Enable trickle changing in RTC upon powerup
-	 * No diode, 250 ohm series resistor
-	 */
-	val = 0xa5;
-	i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 8, 1, &val, 1);
-
-	return 0;
-}
-
-void after_reloc (ulong dest_addr, gd_t * gd)
-{
-	memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE);
-
-/*	display_mem_map(); */
-
-	/* now, jump to the main U-Boot board init code */
-	set_led(LED_GREEN);
-	board_init_r (gd, dest_addr);
-	/* NOTREACHED */
-}
-
-/*
- * Check Board Identity:
- * right now, assume borad type. (there is just one...after all)
- */
-
-int checkboard (void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: %s", CONFIG_SYS_BOARD_NAME);
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return (0);
-}
-
-void set_led(int col)
-{
-	int tmp;
-	int on_pin;
-	int off_pin;
-
-	/* Program Mpp[22] as Gpp[22]
-	 * Program Mpp[23] as Gpp[23]
-	 */
-	tmp = GTREGREAD(MPP_CONTROL2);
-	tmp &= 0x00ffffff;
-	GT_REG_WRITE(MPP_CONTROL2,tmp);
-
-	/* Program Gpp[22] and Gpp[23] as output
-	 */
-	tmp = GTREGREAD(GPP_IO_CONTROL);
-	tmp |= 0x00C00000;
-	GT_REG_WRITE(GPP_IO_CONTROL, tmp);
-
-	/* Program Gpp[22] and Gpp[23] as active high
-	 */
-	tmp = GTREGREAD(GPP_LEVEL_CONTROL);
-	tmp &= 0xff3fffff;
-	GT_REG_WRITE(GPP_LEVEL_CONTROL, tmp);
-
-	switch(col) {
-	default:
-	case LED_OFF :
-		on_pin  = 0;
-		off_pin = ((1 << 23) | (1 << 22));
-		break;
-	case LED_RED :
-		on_pin  = (1 << 23);
-		off_pin = (1 << 22);
-		break;
-	case LED_GREEN :
-		on_pin  = (1 << 22);
-		off_pin = (1 << 23);
-		break;
-	case LED_ORANGE :
-		on_pin  = ((1 << 23) | (1 << 22));
-		off_pin = 0;
-		break;
-	}
-
-	/* Set output Gpp[22] and Gpp[23]
-	 */
-	tmp = GTREGREAD(GPP_VALUE);
-	tmp |= on_pin;
-	tmp &= ~off_pin;
-	GT_REG_WRITE(GPP_VALUE, tmp);
-}
-
-int display_mem_map (void)
-{
-	int i;
-	unsigned int base, size, width;
-#ifdef CONFIG_PCI
-	int j;
-#endif
-
-	/* SDRAM */
-	printf ("SD (DDR) RAM\n");
-	for (i = 0; i <= BANK3; i++) {
-		base = memoryGetBankBaseAddress (i);
-		size = memoryGetBankSize (i);
-		if (size != 0)
-			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
-				i, base, size >> 20);
-	}
-#ifdef CONFIG_PCI
-	/* CPU's PCI windows */
-	for (i = 0; i <= PCI_HOST1; i++) {
-		printf ("\nCPU's PCI %d windows\n", i);
-		base = pciGetSpaceBase (i, PCI_IO);
-		size = pciGetSpaceSize (i, PCI_IO);
-		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
-			size >> 20);
-		/* ronen currently only first PCI MEM is used 3 */
-		for (j = 0; j <= PCI_REGION0; j++) {
-			base = pciGetSpaceBase (i, j);
-			size = pciGetSpaceSize (i, j);
-			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",
-				j, base, size >> 20);
-		}
-	}
-#endif /* of CONFIG_PCI */
-
-	/* Bootrom */
-	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
-	size = memoryGetDeviceSize (BOOT_DEVICE);
-	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
-	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\t- FLASH\n",
-		base, size >> 20, width);
-
-	return (0);
-}
-
-/* DRAM check routines copied from gw8260 */
-
-#if defined (CONFIG_SYS_DRAM_TEST)
-
-/*********************************************************************/
-/* NAME:  move64() -  moves a double word (64-bit)		     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   this function performs a double word move from the data at	     */
-/*   the source pointer to the location at the destination pointer.  */
-/*								     */
-/* INPUTS:							     */
-/*   unsigned long long *src  - pointer to data to move		     */
-/*								     */
-/* OUTPUTS:							     */
-/*   unsigned long long *dest - pointer to locate to move data	     */
-/*								     */
-/* RETURNS:							     */
-/*   None							     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*   May cloober fr0.						     */
-/*								     */
-/*********************************************************************/
-static void move64 (unsigned long long *src, unsigned long long *dest)
-{
-	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
-	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
-	     : : : "fr0");		/* Clobbers fr0         */
-	return;
-}
-
-
-#if defined (CONFIG_SYS_DRAM_TEST_DATA)
-
-unsigned long long pattern[] = {
-	0xaaaaaaaaaaaaaaaaULL,
-	0xccccccccccccccccULL,
-	0xf0f0f0f0f0f0f0f0ULL,
-	0xff00ff00ff00ff00ULL,
-	0xffff0000ffff0000ULL,
-	0xffffffff00000000ULL,
-	0x00000000ffffffffULL,
-	0x0000ffff0000ffffULL,
-	0x00ff00ff00ff00ffULL,
-	0x0f0f0f0f0f0f0f0fULL,
-	0x3333333333333333ULL,
-	0x5555555555555555ULL
-};
-
-/*********************************************************************/
-/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Tests data lines for shorts and opens by forcing adjacent data  */
-/*   to opposite states. Because the data lines could be routed in   */
-/*   an arbitrary manner the must ensure test patterns ensure that   */
-/*   every case is tested. By using the following series of binary   */
-/*   patterns every combination of adjacent bits is test regardless  */
-/*   of routing.						     */
-/*								     */
-/*     ...101010101010101010101010				     */
-/*     ...110011001100110011001100				     */
-/*     ...111100001111000011110000				     */
-/*     ...111111110000000011111111				     */
-/*								     */
-/*   Carrying this out, gives us six hex patterns as follows:	     */
-/*								     */
-/*     0xaaaaaaaaaaaaaaaa					     */
-/*     0xcccccccccccccccc					     */
-/*     0xf0f0f0f0f0f0f0f0					     */
-/*     0xff00ff00ff00ff00					     */
-/*     0xffff0000ffff0000					     */
-/*     0xffffffff00000000					     */
-/*								     */
-/*   The number test patterns will always be given by:		     */
-/*								     */
-/*   log(base 2)(number data bits) = log2 (64) = 6		     */
-/*								     */
-/*   To test for short and opens to other signals on our boards. we  */
-/*   simply							     */
-/*   test with the 1's complemnt of the paterns as well.	     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern				     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*  Assumes only one one SDRAM bank				     */
-/*								     */
-/*********************************************************************/
-int mem_test_data (void)
-{
-	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
-	unsigned long long temp64 = 0;
-	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
-	int i;
-	unsigned int hi, lo;
-
-	for (i = 0; i < num_patterns; i++) {
-		move64 (&(pattern[i]), pmem);
-		move64 (pmem, &temp64);
-
-		/* hi = (temp64>>32) & 0xffffffff;          */
-		/* lo = temp64 & 0xffffffff;                */
-		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
-
-		hi = (pattern[i] >> 32) & 0xffffffff;
-		lo = pattern[i] & 0xffffffff;
-		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
-
-		if (temp64 != pattern[i]) {
-			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
-				hi, lo);
-			return 1;
-		}
-	}
-
-	return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_DATA */
-
-#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
-/*********************************************************************/
-/* NAME:  mem_test_address() -	test address lines		     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   This function performs a test to verify that each word im	     */
-/*   memory is uniquly addressable. The test sequence is as follows: */
-/*								     */
-/*   1) write the address of each word to each word.		     */
-/*   2) verify that each location equals its address		     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern and address			     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_test_address (void)
-{
-	volatile unsigned int *pmem =
-		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
-	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
-	unsigned int i;
-
-	/* write address to each location */
-	for (i = 0; i < size; i++)
-		pmem[i] = i;
-
-	/* verify each loaction */
-	for (i = 0; i < size; i++) {
-		if (pmem[i] != i) {
-			printf ("\n   Address Test Failed at 0x%x", i);
-			return 1;
-		}
-	}
-	return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
-
-#if defined (CONFIG_SYS_DRAM_TEST_WALK)
-/*********************************************************************/
-/* NAME:   mem_march() -  memory march				     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Marches up through memory. At each location verifies rmask if   */
-/*   read = 1. At each location write wmask if	write = 1. Displays  */
-/*   failing address and pattern.				     */
-/*								     */
-/* INPUTS:							     */
-/*   volatile unsigned long long * base - start address of test	     */
-/*   unsigned int size - number of dwords(64-bit) to test	     */
-/*   unsigned long long rmask - read verify mask		     */
-/*   unsigned long long wmask - wrtie verify mask		     */
-/*   short read - verifies rmask if read = 1			     */
-/*   short write  - writes wmask if write = 1			     */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays failing test pattern and address			     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_march (volatile unsigned long long *base,
-	       unsigned int size,
-	       unsigned long long rmask,
-	       unsigned long long wmask, short read, short write)
-{
-	unsigned int i;
-	unsigned long long temp = 0;
-	unsigned int hitemp, lotemp, himask, lomask;
-
-	for (i = 0; i < size; i++) {
-		if (read != 0) {
-			/* temp = base[i]; */
-			move64 ((unsigned long long *) &(base[i]), &temp);
-			if (rmask != temp) {
-				hitemp = (temp >> 32) & 0xffffffff;
-				lotemp = temp & 0xffffffff;
-				himask = (rmask >> 32) & 0xffffffff;
-				lomask = rmask & 0xffffffff;
-
-				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
-				return 1;
-			}
-		}
-		if (write != 0) {
-			/*  base[i] = wmask; */
-			move64 (&wmask, (unsigned long long *) &(base[i]));
-		}
-	}
-	return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_WALK */
-
-/*********************************************************************/
-/* NAME:   mem_test_walk() -  a simple walking ones test	     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Performs a walking ones through entire physical memory. The     */
-/*   test uses as series of memory marches, mem_march(), to verify   */
-/*   and write the test patterns to memory. The test sequence is as  */
-/*   follows:							     */
-/*     1) march writing 0000...0001				     */
-/*     2) march verifying 0000...0001  , writing  0000...0010	     */
-/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
-/*	   the write mask equals 1000...0000			     */
-/*     4) march verifying 1000...0000				     */
-/*   The test fails if any of the memory marches return a failure.   */
-/*								     */
-/* OUTPUTS:							     */
-/*   Displays which pass on the memory test is executing	     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int mem_test_walk (void)
-{
-	unsigned long long mask;
-	volatile unsigned long long *pmem =
-		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
-	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
-
-	unsigned int i;
-
-	mask = 0x01;
-
-	printf ("Initial Pass");
-	mem_march (pmem, size, 0x0, 0x1, 0, 1);
-
-	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-	printf ("		");
-	printf ("         ");
-	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-
-	for (i = 0; i < 63; i++) {
-		printf ("Pass %2d", i + 2);
-		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
-			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
-			return 1;
-		}
-		mask = mask << 1;
-		printf ("\b\b\b\b\b\b\b");
-	}
-
-	printf ("Last Pass");
-	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
-		/* printf("mask: 0x%x", mask); */
-		return 1;
-	}
-	printf ("\b\b\b\b\b\b\b\b\b");
-	printf ("	     ");
-	printf ("\b\b\b\b\b\b\b\b\b");
-
-	return 0;
-}
-
-/*********************************************************************/
-/* NAME:    testdram() -  calls any enabled memory tests	     */
-/*								     */
-/* DESCRIPTION:							     */
-/*   Runs memory tests if the environment test variables are set to  */
-/*   'y'.							     */
-/*								     */
-/* INPUTS:							     */
-/*   testdramdata    - If set to 'y', data test is run.		     */
-/*   testdramaddress - If set to 'y', address test is run.	     */
-/*   testdramwalk    - If set to 'y', walking ones test is run	     */
-/*								     */
-/* OUTPUTS:							     */
-/*   None							     */
-/*								     */
-/* RETURNS:							     */
-/*   0 -  Passed test						     */
-/*   1 -  Failed test						     */
-/*								     */
-/* RESTRICTIONS/LIMITATIONS:					     */
-/*								     */
-/*								     */
-/*********************************************************************/
-int testdram (void)
-{
-	int rundata    = 0;
-	int runaddress = 0;
-	int runwalk    = 0;
-
-#ifdef CONFIG_SYS_DRAM_TEST_DATA
-	rundata = getenv_yesno("testdramdata") == 1;
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
-	runaddress = getenv_yesno("testdramaddress") == 1;
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_WALK
-	runwalk = getenv_yesno("testdramwalk") == 1;
-#endif
-
-	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
-		printf ("Testing RAM from 0x%08x to 0x%08x ...  "
-			"(don't panic... that will take a moment !!!!)\n",
-			CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
-#ifdef CONFIG_SYS_DRAM_TEST_DATA
-	if (rundata == 1) {
-		printf ("Test DATA ...  ");
-		if (mem_test_data () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
-	if (runaddress == 1) {
-		printf ("Test ADDRESS ...  ");
-		if (mem_test_address () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_WALK
-	if (runwalk == 1) {
-		printf ("Test WALKING ONEs ...  ");
-		if (mem_test_walk () == 1) {
-			printf ("failed \n");
-			return 1;
-		} else
-			printf ("ok \n");
-	}
-#endif
-	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
-		printf ("passed\n");
-	return 0;
-
-}
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-/* ronen - the below functions are used by the bootm function           */
-/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
-/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
-/*    the kernel data areas.                                            */
-/*  - we diable and invalidate the icache and dcache.                   */
-void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
-{
-	u32 temp;
-
-	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
-	if ((temp & 0xffff) == new_loc >> 16)
-		return;
-
-	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
-		0xffff0000) | (new_loc >> 16);
-
-	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
-	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
-							new_loc |
-							(INTERNAL_SPACE_DECODE)))))
-	       != temp);
-
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return mv6446x_eth_initialize(bis);
-}
diff --git a/board/prodrive/p3mx/p3mx.h b/board/prodrive/p3mx/p3mx.h
deleted file mode 100644
index e6518cb5921..00000000000
--- a/board/prodrive/p3mx/p3mx.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * (C) Copyright 2005
- *
- * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. roel.loeffen@prodrive.nl
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __P3MX_H__
-#define __P3MX_H__
-
-#define LED_OFF		1
-#define LED_GREEN	2
-#define LED_RED		3
-#define LED_ORANGE	4
-
-#endif /* __P3MX_H__ */
diff --git a/board/prodrive/p3mx/pci.c b/board/prodrive/p3mx/pci.c
deleted file mode 100644
index 56cdfc29596..00000000000
--- a/board/prodrive/p3mx/pci.c
+++ /dev/null
@@ -1,1003 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/* PCI.c - PCI functions */
-
-
-#include <common.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-
-#include "../../Marvell/include/pci.h"
-
-#undef DEBUG
-#undef IDE_SET_NATIVE_MODE
-static unsigned int local_buses[] = { 0, 0 };
-
-static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
-	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
-	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
-};
-
-#ifdef CONFIG_USE_CPCIDVI
-typedef struct {
-	unsigned int base;
-	unsigned int init;
-} GT_CPCIDVI_ROM_T;
-
-static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
-#endif
-
-#ifdef DEBUG
-static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
-static void gt_pci_bus_mode_display (PCI_HOST host)
-{
-	unsigned int mode;
-
-
-	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
-	switch (mode) {
-	case 0:
-		printf ("PCI %d bus mode: Conventional PCI\n", host);
-		break;
-	case 1:
-		printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
-		break;
-	case 2:
-		printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
-		break;
-	case 3:
-		printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
-		break;
-	default:
-		printf ("Unknown BUS %d\n", mode);
-	}
-}
-#endif
-
-static const unsigned int pci_p2p_configuration_reg[] = {
-	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-static const unsigned int pci_configuration_address[] = {
-	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
-};
-
-static const unsigned int pci_configuration_data[] = {
-	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
-	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
-};
-
-static const unsigned int pci_error_cause_reg[] = {
-	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
-};
-
-static const unsigned int pci_arbiter_control[] = {
-	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
-};
-
-static const unsigned int pci_address_space_en[] = {
-	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
-};
-
-static const unsigned int pci_snoop_control_base_0_low[] = {
-	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_snoop_control_top_0[] = {
-	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
-};
-
-static const unsigned int pci_access_control_base_0_low[] = {
-	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_access_control_top_0[] = {
-	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
-};
-
-static const unsigned int pci_scs_bank_size[2][4] = {
-	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
-	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
-	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
-	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
-};
-
-static const unsigned int pci_p2p_configuration[] = {
-	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-
-/********************************************************************
-* pciWriteConfigReg - Write to a PCI configuration register
-*		    - Make sure the GT is configured as a master before writing
-*		      to another device on the PCI.
-*		    - The function takes care of Big/Little endian conversion.
-*
-*
-* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
-*		   (or any other PCI device spec)
-*	    pciDevNum: The device number needs to be addressed.
-*
-*  Configuration Address 0xCF8:
-*
-*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|00|
-*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
-*
-*********************************************************************/
-void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
-			unsigned int pciDevNum, unsigned int data)
-{
-	volatile unsigned int DataForAddrReg;
-	unsigned int functionNum;
-	unsigned int busNum = 0;
-	unsigned int addr;
-
-	if (pciDevNum > 32)	/* illegal device Number */
-		return;
-	if (pciDevNum == SELF) {	/* configure our configuration space. */
-		pciDevNum =
-			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
-			0x1f;
-		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
-			0xff0000;
-	}
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xfc;
-	DataForAddrReg =
-		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
-	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
-	GT_REG_READ (pci_configuration_address[host], &addr);
-	if (addr != DataForAddrReg)
-		return;
-	GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-/********************************************************************
-* pciReadConfigReg  - Read from a PCI0 configuration register
-*		    - Make sure the GT is configured as a master before reading
-*		      from another device on the PCI.
-*		    - The function takes care of Big/Little endian conversion.
-* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
-*			spec)
-*	    pciDevNum: The device number needs to be addressed.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-*		  cause register to make sure the data is valid
-*
-*  Configuration Address 0xCF8:
-*
-*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|00|
-*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
-*
-*********************************************************************/
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
-			       unsigned int pciDevNum)
-{
-	volatile unsigned int DataForAddrReg;
-	unsigned int data;
-	unsigned int functionNum;
-	unsigned int busNum = 0;
-
-	if (pciDevNum > 32)	/* illegal device Number */
-		return 0xffffffff;
-	if (pciDevNum == SELF) {	/* configure our configuration space. */
-		pciDevNum =
-			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
-			0x1f;
-		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
-			0xff0000;
-	}
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xfc;
-	DataForAddrReg =
-		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
-	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
-	GT_REG_READ (pci_configuration_address[host], &data);
-	if (data != DataForAddrReg)
-		return 0xffffffff;
-	GT_REG_READ (pci_configuration_data[host], &data);
-	return data;
-}
-
-/********************************************************************
-* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
-*				the agent is placed on another Bus. For more
-*				information read P2P in the PCI spec.
-*
-* Inputs:   unsigned int regOffset - The register offset as it apears in the
-*	    GT spec (or any other PCI device spec).
-*	    unsigned int pciDevNum - The device number needs to be addressed.
-*	    unsigned int busNum - On which bus does the Target agent connect
-*				  to.
-*	    unsigned int data - data to be written.
-*
-*  Configuration Address 0xCF8:
-*
-*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|01|
-*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
-*
-*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
-*   PCI spec referring to P2P.
-*
-*********************************************************************/
-void pciOverBridgeWriteConfigReg (PCI_HOST host,
-				  unsigned int regOffset,
-				  unsigned int pciDevNum,
-				  unsigned int busNum, unsigned int data)
-{
-	unsigned int DataForReg;
-	unsigned int functionNum;
-
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xff;
-	busNum = busNum << 16;
-	if (pciDevNum == SELF) {	/* This board */
-		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
-	} else {
-		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
-			BIT31 | BIT0;
-	}
-	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
-	GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-
-/********************************************************************
-* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
-*				the agent target locate on another PCI bus.
-*			      - Make sure the GT is configured as a master
-*				before reading from another device on the PCI.
-*			      - The function takes care of Big/Little endian
-*				conversion.
-* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
-*			 spec). (configuration register offset.)
-*	    pciDevNum: The device number needs to be addressed.
-*	    busNum: the Bus number where the agent is place.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-*		  cause register to make sure the data is valid
-*
-*  Configuration Address 0xCF8:
-*
-*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|01|
-*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
-*
-*********************************************************************/
-unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
-					 unsigned int regOffset,
-					 unsigned int pciDevNum,
-					 unsigned int busNum)
-{
-	unsigned int DataForReg;
-	unsigned int data;
-	unsigned int functionNum;
-
-	functionNum = regOffset & 0x00000700;
-	pciDevNum = pciDevNum << 11;
-	regOffset = regOffset & 0xff;
-	busNum = busNum << 16;
-	if (pciDevNum == SELF) {	/* This board */
-		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
-	} else {		/* agent on another bus */
-
-		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
-			BIT0 | BIT31;
-	}
-	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
-	GT_REG_READ (pci_configuration_data[host], &data);
-	return data;
-}
-
-
-/********************************************************************
-* pciGetRegOffset - Gets the register offset for this region config.
-*
-* INPUT:   Bus, Region - The bus and region we ask for its base address.
-* OUTPUT:   N/A
-* RETURNS: PCI register base address
-*********************************************************************/
-static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
-{
-	switch (host) {
-	case PCI_HOST0:
-		switch (region) {
-		case PCI_IO:
-			return PCI_0I_O_LOW_DECODE_ADDRESS;
-		case PCI_REGION0:
-			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-		case PCI_REGION1:
-			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
-		case PCI_REGION2:
-			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
-		case PCI_REGION3:
-			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
-		}
-	case PCI_HOST1:
-		switch (region) {
-		case PCI_IO:
-			return PCI_1I_O_LOW_DECODE_ADDRESS;
-		case PCI_REGION0:
-			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
-		case PCI_REGION1:
-			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
-		case PCI_REGION2:
-			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
-		case PCI_REGION3:
-			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
-		}
-	}
-	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-}
-
-static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
-{
-	switch (host) {
-	case PCI_HOST0:
-		switch (region) {
-		case PCI_IO:
-			return PCI_0I_O_ADDRESS_REMAP;
-		case PCI_REGION0:
-			return PCI_0MEMORY0_ADDRESS_REMAP;
-		case PCI_REGION1:
-			return PCI_0MEMORY1_ADDRESS_REMAP;
-		case PCI_REGION2:
-			return PCI_0MEMORY2_ADDRESS_REMAP;
-		case PCI_REGION3:
-			return PCI_0MEMORY3_ADDRESS_REMAP;
-		}
-	case PCI_HOST1:
-		switch (region) {
-		case PCI_IO:
-			return PCI_1I_O_ADDRESS_REMAP;
-		case PCI_REGION0:
-			return PCI_1MEMORY0_ADDRESS_REMAP;
-		case PCI_REGION1:
-			return PCI_1MEMORY1_ADDRESS_REMAP;
-		case PCI_REGION2:
-			return PCI_1MEMORY2_ADDRESS_REMAP;
-		case PCI_REGION3:
-			return PCI_1MEMORY3_ADDRESS_REMAP;
-		}
-	}
-	return PCI_0MEMORY0_ADDRESS_REMAP;
-}
-
-/********************************************************************
-* pciGetBaseAddress - Gets the base address of a PCI.
-*	    - If the PCI size is 0 then this base address has no meaning!!!
-*
-*
-* INPUT:   Bus, Region - The bus and region we ask for its base address.
-* OUTPUT:   N/A
-* RETURNS: PCI base address.
-*********************************************************************/
-unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int regBase;
-	unsigned int regEnd;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &regBase);
-	GT_REG_READ (regOffset + 8, &regEnd);
-
-	if (regEnd <= regBase)
-		return 0xffffffff;	/* ERROR !!! */
-
-	regBase = regBase << 16;
-	return regBase;
-}
-
-bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
-		  unsigned int bankBase, unsigned int bankLength)
-{
-	unsigned int low = 0xfff;
-	unsigned int high = 0x0;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-	unsigned int remapOffset = pciGetRemapOffset (host, region);
-
-	if (bankLength != 0) {
-		low = (bankBase >> 16) & 0xffff;
-		high = ((bankBase + bankLength) >> 16) - 1;
-	}
-
-	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
-	GT_REG_WRITE (regOffset + 8, high);
-
-	if (bankLength != 0) {	/* must do AFTER writing maps */
-		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
-								   dont support upper 32
-								   in this driver */
-	}
-	return true;
-}
-
-unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int low;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &low);
-	return (low & 0xffff) << 16;
-}
-
-unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
-{
-	unsigned int low, high;
-	unsigned int regOffset = pciGetRegOffset (host, region);
-
-	GT_REG_READ (regOffset, &low);
-	GT_REG_READ (regOffset + 8, &high);
-	return ((high & 0xffff) + 1) << 16;
-}
-
-
-/* ronen - 7/Dec/03*/
-/********************************************************************
-* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
-* Inputs: one of the PCI BAR
-*********************************************************************/
-void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
-	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
-	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-/********************************************************************
-* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
-*
-* Inputs: base and size of PCI SCS
-*********************************************************************/
-void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
-		       unsigned int pciDramBase, unsigned int pciDramSize)
-{
-	/*ronen different function for 3rd bank. */
-	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
-
-	pciDramBase = pciDramBase & 0xfffff000;
-	pciDramBase = pciDramBase | (pciReadConfigReg (host,
-						       PCI_SCS_0_BASE_ADDRESS
-						       + offset,
-						       SELF) & 0x00000fff);
-	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
-			   pciDramBase);
-	if (pciDramSize == 0)
-		pciDramSize++;
-	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
-	gtPciEnableInternalBAR (host, bank);
-}
-
-/********************************************************************
-* pciSetRegionFeatures - This function modifys one of the 8 regions with
-*			  feature bits given as an input.
-*			- Be advised to check the spec before modifying them.
-* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
-*	  unsigned int features - See file: pci.h there are defintion for those
-*				  region features.
-*	  unsigned int baseAddress - The region base Address.
-*	  unsigned int topAddress - The region top Address.
-* Returns: false if one of the parameters is erroneous true otherwise.
-*********************************************************************/
-bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
-			   unsigned int features, unsigned int baseAddress,
-			   unsigned int regionLength)
-{
-	unsigned int accessLow;
-	unsigned int accessHigh;
-	unsigned int accessTop = baseAddress + regionLength;
-
-	if (regionLength == 0) {	/* close the region. */
-		pciDisableAccessRegion (host, region);
-		return true;
-	}
-	/* base Address is store is bits [11:0] */
-	accessLow = (baseAddress & 0xfff00000) >> 20;
-	/* All the features are update according to the defines in pci.h (to be on
-	   the safe side we disable bits: [11:0] */
-	accessLow = accessLow | (features & 0xfffff000);
-	/* write to the Low Access Region register */
-	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
-		      accessLow);
-
-	accessHigh = (accessTop & 0xfff00000) >> 20;
-
-	/* write to the High Access Region register */
-	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
-		      accessHigh - 1);
-	return true;
-}
-
-/********************************************************************
-* pciDisableAccessRegion - Disable The given Region by writing MAX size
-*			    to its low Address and MIN size to its high Address.
-*
-* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
-* Returns:  N/A.
-*********************************************************************/
-void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
-{
-	/* writing back the registers default values. */
-	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
-		      0x01001fff);
-	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
-}
-
-/********************************************************************
-* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
-*
-* Inputs:   N/A
-* Returns:  true.
-*********************************************************************/
-bool pciArbiterEnable (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
-	return true;
-}
-
-/********************************************************************
-* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
-*
-* Inputs:   N/A
-* Returns:  true
-*********************************************************************/
-bool pciArbiterDisable (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
-	return true;
-}
-
-/********************************************************************
-* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
-*
-* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
-*	    PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
-*	    PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
-*	    PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
-*	    PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
-*	    PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
-*	    PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
-* Returns:  true
-*********************************************************************/
-bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
-				  PCI_AGENT_PRIO externalAgent0,
-				  PCI_AGENT_PRIO externalAgent1,
-				  PCI_AGENT_PRIO externalAgent2,
-				  PCI_AGENT_PRIO externalAgent3,
-				  PCI_AGENT_PRIO externalAgent4,
-				  PCI_AGENT_PRIO externalAgent5)
-{
-	unsigned int regData;
-	unsigned int writeData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
-		(externalAgent1 << 9) + (externalAgent2 << 10) +
-		(externalAgent3 << 11) + (externalAgent4 << 12) +
-		(externalAgent5 << 13);
-	regData = (regData & 0xffffc07f) | writeData;
-	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
-	return true;
-}
-
-/********************************************************************
-* pciParkingDisable - Park on last option disable, with this function you can
-*		       disable the park on last mechanism for each agent.
-*		       disabling this option for all agents results parking
-*		       on the internal master.
-*
-* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
-*	  PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
-*	  PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
-*	  PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
-*	  PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
-*	  PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
-*	  PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
-* Returns:  true
-*********************************************************************/
-bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
-			PCI_AGENT_PARK externalAgent0,
-			PCI_AGENT_PARK externalAgent1,
-			PCI_AGENT_PARK externalAgent2,
-			PCI_AGENT_PARK externalAgent3,
-			PCI_AGENT_PARK externalAgent4,
-			PCI_AGENT_PARK externalAgent5)
-{
-	unsigned int regData;
-	unsigned int writeData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
-		(externalAgent1 << 16) + (externalAgent2 << 17) +
-		(externalAgent3 << 18) + (externalAgent4 << 19) +
-		(externalAgent5 << 20);
-	regData = (regData & ~(0x7f << 14)) | writeData;
-	GT_REG_WRITE (pci_arbiter_control[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
-*			respond to grant assertion within a window specified in
-*			the input value: 'brokenValue'.
-*
-* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
-*			grant without asserting frame.
-* Returns:  Error for illegal broken value otherwise true.
-*********************************************************************/
-bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
-{
-	unsigned int data;
-	unsigned int regData;
-
-	if (brokenValue > 0xf)
-		return false;	/* brokenValue must be 4 bit */
-	data = brokenValue << 3;
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	regData = (regData & 0xffffff87) | data;
-	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
-	return true;
-}
-
-/********************************************************************
-* pciDisableBrokenAgentDetection - This function disable the Broken agent
-*			    Detection mechanism.
-*			    NOTE: This operation may cause a dead lock on the
-*			    pci0 arbitration.
-*
-* Inputs:   N/A
-* Returns:  true.
-*********************************************************************/
-bool pciDisableBrokenAgentDetection (PCI_HOST host)
-{
-	unsigned int regData;
-
-	GT_REG_READ (pci_arbiter_control[host], &regData);
-	regData = regData & 0xfffffffd;
-	GT_REG_WRITE (pci_arbiter_control[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciP2PConfig - This function set the PCI_n P2P configurate.
-*		  For more information on the P2P read PCI spec.
-*
-* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
-*				       Boundry.
-*	   unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
-*				       Boundry.
-*	   unsigned int busNum - The CPI bus number to which the PCI interface
-*				       is connected.
-*	   unsigned int devNum - The PCI interface's device number.
-*
-* Returns:  true.
-*********************************************************************/
-bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
-		   unsigned int SecondBusHigh,
-		   unsigned int busNum, unsigned int devNum)
-{
-	unsigned int regData;
-
-	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
-		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
-	GT_REG_WRITE (pci_p2p_configuration[host], regData);
-	return true;
-}
-
-/********************************************************************
-* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
-*			   supports Cache Coherency in the PCI_n interface.
-* Inputs: region - One of the four regions.
-*	  snoopType - There is four optional Types:
-*			 1. No Snoop.
-*			 2. Snoop to WT region.
-*			 3. Snoop to WB region.
-*			 4. Snoop & Invalidate to WB region.
-*	  baseAddress - Base Address of this region.
-*	  regionLength - Region length.
-* Returns: false if one of the parameters is wrong otherwise return true.
-*********************************************************************/
-bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
-			    PCI_SNOOP_TYPE snoopType,
-			    unsigned int baseAddress,
-			    unsigned int regionLength)
-{
-	unsigned int snoopXbaseAddress;
-	unsigned int snoopXtopAddress;
-	unsigned int data;
-	unsigned int snoopHigh = baseAddress + regionLength;
-
-	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
-		return false;
-	snoopXbaseAddress =
-		pci_snoop_control_base_0_low[host] + 0x10 * region;
-	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
-	if (regionLength == 0) {	/* closing the region */
-		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
-		GT_REG_WRITE (snoopXtopAddress, 0);
-		return true;
-	}
-	baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
-	data = (baseAddress >> 20) | snoopType << 12;
-	GT_REG_WRITE (snoopXbaseAddress, data);
-	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
-	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
-	return true;
-}
-
-static int gt_read_config_dword (struct pci_controller *hose,
-				 pci_dev_t dev, int offset, u32 * value)
-{
-	int bus = PCI_BUS (dev);
-
-	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
-		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
-					   PCI_DEV (dev));
-	} else {
-		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
-						     cfg_addr, offset,
-						     PCI_DEV (dev), bus);
-	}
-
-	return 0;
-}
-
-static int gt_write_config_dword (struct pci_controller *hose,
-				  pci_dev_t dev, int offset, u32 value)
-{
-	int bus = PCI_BUS (dev);
-
-	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
-		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
-				   PCI_DEV (dev), value);
-	} else {
-		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
-					     offset, PCI_DEV (dev), bus,
-					     value);
-	}
-	return 0;
-}
-
-
-static void gt_setup_ide (struct pci_controller *hose,
-			  pci_dev_t dev, struct pci_config_table *entry)
-{
-	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
-	u32 bar_response, bar_value;
-	int bar;
-
-	for (bar = 0; bar < 6; bar++) {
-		/*ronen different function for 3rd bank. */
-		unsigned int offset =
-			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
-
-		pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
-					     0x0);
-		pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
-					    &bar_response);
-
-		pciauto_region_allocate (bar_response &
-					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
-					 pci_io : hose->pci_mem, ide_bar[bar],
-					 &bar_value);
-
-		pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
-					     bar_value);
-	}
-}
-
-#ifdef CONFIG_USE_CPCIDVI
-static void gt_setup_cpcidvi (struct pci_controller *hose,
-			      pci_dev_t dev, struct pci_config_table *entry)
-{
-	u32		  bar_value, pci_response;
-
-	pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
-	pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
-	pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
-	pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
-	pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
-	pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
-	pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
-	pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
-	gt_cpcidvi_rom.base = bar_value & 0xffffff00;
-	gt_cpcidvi_rom.init = 1;
-}
-
-unsigned char gt_cpcidvi_in8(unsigned int offset)
-{
-	unsigned char	  data;
-
-	if (gt_cpcidvi_rom.init == 0) {
-		return(0);
-		}
-	data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
-	return(data);
-}
-
-void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
-{
-	unsigned int	  off;
-
-	if (gt_cpcidvi_rom.init == 0) {
-		return;
-	}
-	off = data;
-	off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
-	in8(off);
-	return;
-}
-#endif
-
-/* TODO BJW: Change this for DB64360. This was pulled from the EV64260	*/
-/* and is curently not called *. */
-#if 0
-static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
-{
-	unsigned char pin, irq;
-
-	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
-
-	if (pin == 1) {		/* only allow INT A */
-		irq = pci_irq_swizzle[(PCI_HOST) hose->
-				      cfg_addr][PCI_DEV (dev)];
-		if (irq)
-			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
-	}
-}
-#endif
-
-struct pci_config_table gt_config_table[] = {
-#ifdef CONFIG_USE_CPCIDVI
-	{PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
-	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
-#endif
-	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
-	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
-	{}
-};
-
-struct pci_controller pci0_hose = {
-/*    fixup_irq: gt_fixup_irq, */
-	config_table:gt_config_table,
-};
-
-struct pci_controller pci1_hose = {
-/*    fixup_irq: gt_fixup_irq, */
-	config_table:gt_config_table,
-};
-
-void pci_init_board (void)
-{
-	unsigned int command;
-#ifdef CONFIG_PCI_PNP
-	unsigned int bar;
-#endif
-#ifdef DEBUG
-	gt_pci_bus_mode_display (PCI_HOST0);
-#endif
-#ifdef CONFIG_USE_CPCIDVI
-	gt_cpcidvi_rom.init = 0;
-	gt_cpcidvi_rom.base = 0;
-#endif
-
-	pci0_hose.config_table = gt_config_table;
-	pci1_hose.config_table = gt_config_table;
-
-#ifdef CONFIG_USE_CPCIDVI
-	gt_config_table[0].config_device =  gt_setup_cpcidvi;
-#endif
-	gt_config_table[1].config_device =  gt_setup_ide;
-
-	pci0_hose.first_busno = 0;
-	pci0_hose.last_busno = 0xff;
-	local_buses[0] = pci0_hose.first_busno;
-
-	/* PCI memory space */
-	pci_set_region (pci0_hose.regions + 0,
-			CONFIG_SYS_PCI0_0_MEM_SPACE,
-			CONFIG_SYS_PCI0_0_MEM_SPACE,
-			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region (pci0_hose.regions + 1,
-			CONFIG_SYS_PCI0_IO_SPACE_PCI,
-			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
-
-	pci_set_ops (&pci0_hose,
-		     pci_hose_read_config_byte_via_dword,
-		     pci_hose_read_config_word_via_dword,
-		     gt_read_config_dword,
-		     pci_hose_write_config_byte_via_dword,
-		     pci_hose_write_config_word_via_dword,
-		     gt_write_config_dword);
-	pci0_hose.region_count = 2;
-
-	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
-
-	pci_register_hose (&pci0_hose);
-	pciArbiterDisable(PCI_HOST0); /* on PMC modules no arbiter is used */
-	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
-	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MASTER;
-	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MEMORY;
-	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-
-#ifdef CONFIG_PCI_PNP
-	pciauto_config_init(&pci0_hose);
-	pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
-#endif
-#ifdef CONFIG_PCI_SCAN_SHOW
-	printf("PCI:   Bus Dev VenId DevId Class Int\n");
-#endif
-	pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno);
-
-#ifdef DEBUG
-	gt_pci_bus_mode_display (PCI_HOST1);
-#endif
-	pci1_hose.first_busno = pci0_hose.last_busno + 1;
-	pci1_hose.last_busno = 0xff;
-	pci1_hose.current_busno = pci1_hose.first_busno;
-	local_buses[1] = pci1_hose.first_busno;
-
-	/* PCI memory space */
-	pci_set_region (pci1_hose.regions + 0,
-			CONFIG_SYS_PCI1_0_MEM_SPACE,
-			CONFIG_SYS_PCI1_0_MEM_SPACE,
-			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region (pci1_hose.regions + 1,
-			CONFIG_SYS_PCI1_IO_SPACE_PCI,
-			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
-
-	pci_set_ops (&pci1_hose,
-		     pci_hose_read_config_byte_via_dword,
-		     pci_hose_read_config_word_via_dword,
-		     gt_read_config_dword,
-		     pci_hose_write_config_byte_via_dword,
-		     pci_hose_write_config_word_via_dword,
-		     gt_write_config_dword);
-
-	pci1_hose.region_count = 2;
-
-	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
-
-	pci_register_hose (&pci1_hose);
-
-	pciArbiterEnable (PCI_HOST1);
-	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
-
-	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MASTER;
-	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-#ifdef CONFIG_PCI_PNP
-	pciauto_config_init(&pci1_hose);
-	pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar);
-#endif
-	pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno);
-
-	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MEMORY;
-	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-}
-#endif /* of CONFIG_PCI */
diff --git a/board/prodrive/p3mx/sdram_init.c b/board/prodrive/p3mx/sdram_init.c
deleted file mode 100644
index 4220930bc54..00000000000
--- a/board/prodrive/p3mx/sdram_init.c
+++ /dev/null
@@ -1,418 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*************************************************************************
- * adaption for the Marvell DB64460 Board
- * Ingo Assmus (ingo.assmus@keymile.com)
- *************************************************************************/
-
-/* sdram_init.c - automatic memory sizing */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include "../../Marvell/include/memory.h"
-#include "../../Marvell/include/pci.h"
-#include "../../Marvell/include/mv_gen_reg.h"
-#include <net.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "../../Marvell/common/i2c.h"
-#include "64460.h"
-#include "mv_regs.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#undef	DEBUG
-#define MAP_PCI
-
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-int set_dfcdlInit (void);	/* setup delay line of Mv64460 */
-int mvDmaIsChannelActive (int);
-int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
-int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
-
-#define D_CACHE_FLUSH_LINE(addr, offset)				\
-	{								\
-		__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-	}
-
-int memory_map_bank (unsigned int bankNo,
-		     unsigned int bankBase, unsigned int bankLength)
-{
-#if defined (MAP_PCI) && defined (CONFIG_PCI)
-	PCI_HOST host;
-#endif
-
-#ifdef DEBUG
-	if (bankLength > 0) {
-		printf ("mapping bank %d at %08x - %08x\n",
-			bankNo, bankBase, bankBase + bankLength - 1);
-	} else {
-		printf ("unmapping bank %d\n", bankNo);
-	}
-#endif
-
-	memoryMapBank (bankNo, bankBase, bankLength);
-
-#if defined (MAP_PCI) && defined (CONFIG_PCI)
-	for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
-		const int features =
-			PREFETCH_ENABLE |
-			DELAYED_READ_ENABLE |
-			AGGRESSIVE_PREFETCH |
-			READ_LINE_AGGRESSIVE_PREFETCH |
-			READ_MULTI_AGGRESSIVE_PREFETCH |
-			MAX_BURST_4 | PCI_NO_SWAP;
-
-		pciMapMemoryBank (host, bankNo, bankBase, bankLength);
-
-		pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
-				       bankLength);
-
-		pciSetRegionFeatures (host, bankNo, features, bankBase,
-				      bankLength);
-	}
-#endif
-
-	return 0;
-}
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-long int dram_size (long int *base, long int maxsize)
-{
-	volatile long int *addr, *b = base;
-	long int cnt, val, save1, save2;
-
-#define STARTVAL (1<<20)	/* start test at 1M */
-	for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
-	     cnt <<= 1) {
-		addr = base + cnt;	/* pointer arith! */
-
-		save1 = *addr;	/* save contents of addr */
-		save2 = *b;	/* save contents of base */
-
-		*addr = cnt;	/* write cnt to addr */
-		*b = 0;		/* put null at base */
-
-		/* check at base address */
-		if ((*b) != 0) {
-			*addr = save1;	/* restore *addr */
-			*b = save2;	/* restore *b */
-			return (0);
-		}
-		val = *addr;	/* read *addr */
-		val = *addr;	/* read *addr */
-
-		*addr = save1;
-		*b = save2;
-
-		if (val != cnt) {
-			DP (printf
-			    ("Found %08x  at Address %08x (failure)\n",
-			     (unsigned int) val, (unsigned int) addr));
-			/* fix boundary condition.. STARTVAL means zero */
-			if (cnt == STARTVAL / sizeof (long))
-				cnt = 0;
-			return (cnt * sizeof (long));
-		}
-	}
-
-	return maxsize;
-}
-
-#define SDRAM_NORMAL			0x0
-#define SDRAM_PRECHARGE_ALL		0x1
-#define SDRAM_REFRESH_ALL		0x2
-#define SDRAM_MODE_REG_SETUP		0x3
-#define SDRAM_XTEN_MODE_REG_SETUP	0x4
-#define SDRAM_NOP			0x5
-#define SDRAM_SELF_REFRESH		0x7
-
-phys_size_t initdram (int board_type)
-{
-	int tmp;
-	int start;
-	ulong size;
-	ulong memSpaceAttr;
-	ulong dest;
-
-	/* first disable all banks */
-	memory_map_bank(0, 0, 0);
-	memory_map_bank(1, 0, 0);
-	memory_map_bank(2, 0, 0);
-	memory_map_bank(3, 0, 0);
-
-	/* calibrate delay lines */
-	set_dfcdlInit();
-
-	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_NOP);		/* 0x1418 */
-	do {
-		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
-	} while(tmp != 0x0);
-
-	/* SDRAM controller configuration */
-#ifdef CONFIG_MV64460_ECC
-	GT_REG_WRITE(MV64460_SDRAM_CONFIG,		0x58201400);	/* 0x1400 */
-#else
-	GT_REG_WRITE(MV64460_SDRAM_CONFIG,		0x58200400);	/* 0x1400 */
-#endif
-	GT_REG_WRITE(MV64460_D_UNIT_CONTROL_LOW,	0xC3000540);	/* 0x1404  */
-	GT_REG_WRITE(MV64460_D_UNIT_CONTROL_HIGH,	0x0300F777);	/* 0x1424 */
-	GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_LOW,	0x01712220);	/* 0x1408 */
-	GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_HIGH, 0x0000005D);	/* 0x140C */
-	GT_REG_WRITE(MV64460_SDRAM_ADDR_CONTROL,	0x00000012);	/* 0x1410 */
-	GT_REG_WRITE(MV64460_SDRAM_OPEN_PAGES_CONTROL,	0x00000001);	/* 0x1414 */
-
-	/* SDRAM drive strength */
-	GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000000); /* 0x14C0 */
-	GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000008); /* 0x14C0 */
-	GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000000);	    /* 0x14C4 */
-	GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000008);	    /* 0x14C4 */
-
-	/* setup SDRAM device registers */
-
-	/* precharge all */
-	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL);	/* 0x1418 */
-	do {
-		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
-	} while(tmp != 0x0);
-
-	/* enable DLL */
-	GT_REG_WRITE(MV64460_EXTENDED_DRAM_MODE, 0x00000000);			/* 0x1420 */
-	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_XTEN_MODE_REG_SETUP);	/* 0x1418 */
-	do {
-		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
-	} while(tmp != 0x0);
-
-	/* reset DLL */
-	GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000132);	/* 0x141C */
-	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP);	/* 0x1418 */
-	do {
-		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
-	} while(tmp != 0x0);
-
-	/* precharge all */
-	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL);	/* 0x1418 */
-	do {
-		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
-	} while(tmp != 0x0);
-
-	/* wait for 2 auto refresh commands */
-	udelay(20);
-
-	/* un-reset DLL */
-	GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000032);	/* 0x141C */
-	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP);	/* 0x1418 */
-	do {
-		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
-	} while(tmp != 0x0);
-
-	/* wait 200 cycles */
-	udelay(2);  /* FIXME  make this dynamic for the system clock */
-
-	/* SDRAM init done */
-	memory_map_bank(0, CONFIG_SYS_SDRAM_BASE,  (256 << 20));
-#ifdef CONFIG_SYS_SDRAM1_BASE
-	memory_map_bank(1, CONFIG_SYS_SDRAM1_BASE, (256 << 20));
-#endif
-
-	/* DUNIT_MMASK: enable SnoopHitEn bit to avoid errata CPU-#4
-	 */
-	tmp = GTREGREAD(MV64460_D_UNIT_MMASK);				/* 0x14B0 */
-	GT_REG_WRITE(MV64460_D_UNIT_MMASK, tmp | 0x2);
-
-	start = (0 << 20);
-#ifdef CONFIG_P3M750
-	size = (512 << 20);
-#elif defined (CONFIG_P3M7448)
-	size = (128 << 20);
-#endif
-
-#ifdef CONFIG_MV64460_ECC
-	memSpaceAttr = ((~(BIT0 << 0)) & 0xf) << 8;
-	mvDmaSetMemorySpace (0, 0, memSpaceAttr, start, size);
-	for (dest = start; dest < start + size; dest += _8M) {
-		mvDmaTransfer (0, start, dest, _8M,
-			       BIT8 /*DMA_DTL_128BYTES */  |
-			       BIT3 /*DMA_HOLD_SOURCE_ADDR */ |
-			       BIT11 /*DMA_BLOCK_TRANSFER_MODE */ );
-		while (mvDmaIsChannelActive (0));
-	}
-#endif
-
-	return (size);
-}
-
-void board_add_ram_info(int use_default)
-{
-	u32 val;
-
-	puts(" (CL=");
-	switch ((GTREGREAD(MV64460_SDRAM_MODE) >> 4) & 0x7) {
-	case 0x2:
-		puts("2");
-		break;
-	case 0x3:
-		puts("3");
-		break;
-	case 0x5:
-		puts("1.5");
-		break;
-	case 0x6:
-		puts("2.5");
-		break;
-	}
-
-	val = GTREGREAD(MV64460_SDRAM_CONFIG);
-
-	puts(", ECC ");
-	if (val & 0x00001000)
-		puts("enabled)");
-	else
-		puts("not enabled)");
-}
-
-/*
- * mvDmaIsChannelActive - Check if IDMA channel is active
- *
- * channel	= IDMA channel number from 0 to 7
- */
-int mvDmaIsChannelActive (int channel)
-{
-	ulong data;
-
-	data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * channel);
-	if (data & BIT14)	/* activity status */
-		return 1;
-
-	return 0;
-}
-
-/*
- * mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
- *			 map.
- *
- * memSpace	= IDMA memory window number from 0 to 7
- * trg_if	= Target interface:
- *		  0x0 DRAM
- *		  0x1 Device Bus
- *		  0x2 Integrated SDRAM (or CPU bus 60x only)
- *		  0x3 PCI0
- *		  0x4 PCI1
- * attr		= IDMA attributes (see MV datasheet)
- * base_addr	= Sets up memory window for transfers
- *
- */
-int mvDmaSetMemorySpace (ulong memSpace,
-			 ulong trg_if,
-			 ulong attr, ulong base_addr, ulong size)
-{
-	ulong temp;
-
-	/* The base address must be aligned to the size.  */
-	if (base_addr % size != 0)
-		return 0;
-
-	if (size >= 0x10000) {	 /* 64K */
-		size &= 0xffff0000;
-		base_addr = (base_addr & 0xffff0000);
-		/* Set the new attributes */
-		GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8,
-			      (base_addr | trg_if | attr));
-		GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8),
-			      (size - 1) & 0xffff0000);
-		temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG);
-		GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
-			      (temp & ~(BIT0 << memSpace)));
-		return 1;
-	}
-
-	return 0;
-}
-
-/*
- * mvDmaTransfer - Transfer data from src_addr to dst_addr on one of the 4
- *		   DMA channels.
- *
- * channel	= IDMA channel number from 0 to 3
- * destAddr	= Destination address
- * sourceAddr	= Source address
- * size		= Size in bytes
- * command	= See MV datasheet
- *
- */
-int mvDmaTransfer (int channel, ulong sourceAddr,
-		   ulong destAddr, ulong size, ulong command)
-{
-	ulong engOffReg = 0;	/* Engine Offset Register */
-
-	if (size > 0xffff)
-		command = command | BIT31;	/* DMA_16M_DESCRIPTOR_MODE */
-	command = command | ((command >> 6) & 0x7);
-	engOffReg = channel * 4;
-	GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg, size);
-	GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, sourceAddr);
-	GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, destAddr);
-	command = command |
-		BIT12	|			/* DMA_CHANNEL_ENABLE */
-		BIT9;				/* DMA_NON_CHAIN_MODE */
-	/* Activate DMA channel By writting to mvDmaControlRegister */
-	GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command);
-	return 1;
-}
-
-/****************************************************************************************
- *			       SDRAM INIT						*
- *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb	*
- *		 This procedure fits only the Atlantis					*
- *											*
- ***************************************************************************************/
-
-/****************************************************************************************
- *			       DFCDL initialize MV643xx Design Considerations		*
- *											*
- ***************************************************************************************/
-int set_dfcdlInit (void)
-{
-	int i;
-
-	/* Values from MV64460 User Manual */
-	unsigned int dfcdl_tbl[] = { 0x00000000, 0x00000001, 0x00000042, 0x00000083,
-				     0x000000c4, 0x00000105, 0x00000146, 0x00000187,
-				     0x000001c8, 0x00000209, 0x0000024a, 0x0000028b,
-				     0x000002cc, 0x0000030d, 0x0000034e, 0x0000038f,
-				     0x000003d0, 0x00000411, 0x00000452, 0x00000493,
-				     0x000004d4, 0x00000515, 0x00000556, 0x00000597,
-				     0x000005d8, 0x00000619, 0x0000065a, 0x0000069b,
-				     0x000006dc, 0x0000071d, 0x0000075e, 0x0000079f,
-				     0x000007e0, 0x00000821, 0x00000862, 0x000008a3,
-				     0x000008e4, 0x00000925, 0x00000966, 0x000009a7,
-				     0x000009e8, 0x00000a29, 0x00000a6a, 0x00000aab,
-				     0x00000aec, 0x00000b2d, 0x00000b6e, 0x00000baf,
-				     0x00000bf0, 0x00000c31, 0x00000c72, 0x00000cb3,
-				     0x00000cf4, 0x00000d35, 0x00000d76, 0x00000db7,
-				     0x00000df8, 0x00000e39, 0x00000e7a, 0x00000ebb,
-				     0x00000efc, 0x00000f3d, 0x00000f7e, 0x00000fbf };
-
-	for (i = 0; i < 64; i++)
-		GT_REG_WRITE (SRAM_DATA0, dfcdl_tbl[i]);
-	GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000);	/* enable dynamic delay line updating */
-
-	return (0);
-}
diff --git a/board/prodrive/p3mx/serial.c b/board/prodrive/p3mx/serial.c
deleted file mode 100644
index 5b7b989860f..00000000000
--- a/board/prodrive/p3mx/serial.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * modified for cpci750 board by
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * serial.c - serial support for esd cpci750 board
- */
-
-/* supports the MPSC */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-#include "../../Marvell/include/memory.h"
-
-#include "mpsc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int p3mx_serial_init(void)
-{
-	mpsc_init (gd->baudrate);
-
-	return (0);
-}
-
-static void p3mx_serial_putc(const char c)
-{
-	if (c == '\n')
-		mpsc_putchar ('\r');
-
-	mpsc_putchar (c);
-}
-
-static int p3mx_serial_getc(void)
-{
-	return mpsc_getchar ();
-}
-
-static int p3mx_serial_tstc(void)
-{
-	return mpsc_test_char ();
-}
-
-static void p3mx_serial_setbrg(void)
-{
-	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
-}
-
-static struct serial_device p3mx_serial_drv = {
-	.name	= "p3mx_serial",
-	.start	= p3mx_serial_init,
-	.stop	= NULL,
-	.setbrg	= p3mx_serial_setbrg,
-	.putc	= p3mx_serial_putc,
-	.puts	= default_serial_puts,
-	.getc	= p3mx_serial_getc,
-	.tstc	= p3mx_serial_tstc,
-};
-
-void p3mx_serial_initialize(void)
-{
-	serial_register(&p3mx_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &p3mx_serial_drv;
-}
-
-#if defined(CONFIG_CMD_KGDB)
-void kgdb_serial_init (void)
-{
-}
-
-void putDebugChar (int c)
-{
-	serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
-	serial_puts (str);
-}
-
-int getDebugChar (void)
-{
-	return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
-	return;
-}
-#endif
diff --git a/board/pxa255_idp/Kconfig b/board/pxa255_idp/Kconfig
index e8b1d47fcf1..544831199d4 100644
--- a/board/pxa255_idp/Kconfig
+++ b/board/pxa255_idp/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_PXA255_IDP
 
-config SYS_CPU
-	default "pxa"
-
 config SYS_BOARD
 	default "pxa255_idp"
 
diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig
index e4d9663c2de..18d78b51008 100644
--- a/board/qemu-mips/Kconfig
+++ b/board/qemu-mips/Kconfig
@@ -1,25 +1,10 @@
 if TARGET_QEMU_MIPS
 
-config SYS_CPU
-	default "mips32"
-
-config SYS_BOARD
-	default "qemu-mips"
-
-config SYS_CONFIG_NAME
-	default "qemu-mips"
-
-endif
-
-if TARGET_QEMU_MIPS64
-
-config SYS_CPU
-	default "mips64"
-
 config SYS_BOARD
 	default "qemu-mips"
 
 config SYS_CONFIG_NAME
-	default "qemu-mips64"
+	default "qemu-mips" if 32BIT
+	default "qemu-mips64" if 64BIT
 
 endif
diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c
index 976ba4ce942..f01fb1c6e76 100644
--- a/board/raidsonic/ib62x0/ib62x0.c
+++ b/board/raidsonic/ib62x0/ib62x0.c
@@ -11,7 +11,7 @@
 #include <miiphy.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include "ib62x0.h"
 
@@ -24,9 +24,9 @@ int board_early_init_f(void)
 	 * There are maximum 64 gpios controlled through 2 sets of registers
 	 * the below configuration configures mainly initial LED status
 	 */
-	kw_config_gpio(IB62x0_OE_VAL_LOW,
-			IB62x0_OE_VAL_HIGH,
-			IB62x0_OE_LOW, IB62x0_OE_HIGH);
+	mvebu_config_gpio(IB62x0_OE_VAL_LOW,
+			  IB62x0_OE_VAL_HIGH,
+			  IB62x0_OE_LOW, IB62x0_OE_HIGH);
 
 	/* Set SATA activity LEDs to default off */
 	writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
@@ -62,7 +62,7 @@ int board_early_init_f(void)
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
diff --git a/board/raspberrypi/rpi_b/Kconfig b/board/raspberrypi/rpi_b/Kconfig
index 1a767b28710..501d511f599 100644
--- a/board/raspberrypi/rpi_b/Kconfig
+++ b/board/raspberrypi/rpi_b/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_RPI_B
 
-config SYS_CPU
-	default "arm1176"
-
 config SYS_BOARD
 	default "rpi_b"
 
diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi_b/rpi_b.c
index 220bb90dc1a..7445f5318ad 100644
--- a/board/raspberrypi/rpi_b/rpi_b.c
+++ b/board/raspberrypi/rpi_b/rpi_b.c
@@ -16,21 +16,38 @@
 
 #include <common.h>
 #include <config.h>
+#include <dm.h>
 #include <fdt_support.h>
 #include <lcd.h>
 #include <mmc.h>
+#include <asm/gpio.h>
 #include <asm/arch/mbox.h>
 #include <asm/arch/sdhci.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static const struct bcm2835_gpio_platdata gpio_platdata = {
+	.base = BCM2835_GPIO_BASE,
+};
+
+U_BOOT_DEVICE(bcm2835_gpios) = {
+	.name = "gpio_bcm2835",
+	.platdata = &gpio_platdata,
+};
+
 struct msg_get_arm_mem {
 	struct bcm2835_mbox_hdr hdr;
 	struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
 	u32 end_tag;
 };
 
+struct msg_get_mac_address {
+	struct bcm2835_mbox_hdr hdr;
+	struct bcm2835_mbox_tag_get_mac_address get_mac_address;
+	u32 end_tag;
+};
+
 struct msg_set_power_state {
 	struct bcm2835_mbox_hdr hdr;
 	struct bcm2835_mbox_tag_set_power_state set_power_state;
@@ -62,6 +79,29 @@ int dram_init(void)
 	return 0;
 }
 
+int misc_init_r(void)
+{
+	ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16);
+	int ret;
+
+	if (getenv("usbethaddr"))
+		return 0;
+
+	BCM2835_MBOX_INIT_HDR(msg);
+	BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS);
+
+	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+	if (ret) {
+		printf("bcm2835: Could not query MAC address\n");
+		/* Ignore error; not critical */
+		return 0;
+	}
+
+	eth_setenv_enetaddr("usbethaddr", msg->get_mac_address.body.resp.mac);
+
+	return 0;
+}
+
 static int power_on_module(u32 module)
 {
 	ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 16);
diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c
index 5eedbf8ce66..3aad532367b 100644
--- a/board/renesas/sh7752evb/sh7752evb.c
+++ b/board/renesas/sh7752evb/sh7752evb.c
@@ -9,6 +9,7 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/mmc.h>
+#include <spi.h>
 #include <spi_flash.h>
 
 int checkboard(void)
diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c
index 42b920fb333..9f6494561c6 100644
--- a/board/renesas/sh7753evb/sh7753evb.c
+++ b/board/renesas/sh7753evb/sh7753evb.c
@@ -9,6 +9,7 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/mmc.h>
+#include <spi.h>
 #include <spi_flash.h>
 
 int checkboard(void)
diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c
index 1464f48b43a..ddcf275f6e7 100644
--- a/board/renesas/sh7757lcr/sh7757lcr.c
+++ b/board/renesas/sh7757lcr/sh7757lcr.c
@@ -9,6 +9,7 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/mmc.h>
+#include <spi.h>
 #include <spi_flash.h>
 
 int checkboard(void)
diff --git a/board/ronetix/pm9261/Kconfig b/board/ronetix/pm9261/Kconfig
index 4a2ca02c671..a4934c582ec 100644
--- a/board/ronetix/pm9261/Kconfig
+++ b/board/ronetix/pm9261/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_PM9261
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "pm9261"
 
diff --git a/board/ronetix/pm9263/Kconfig b/board/ronetix/pm9263/Kconfig
index 95129190fd6..339a6ea1694 100644
--- a/board/ronetix/pm9263/Kconfig
+++ b/board/ronetix/pm9263/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_PM9263
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "pm9263"
 
diff --git a/board/ronetix/pm9g45/Kconfig b/board/ronetix/pm9g45/Kconfig
index 0c0af962d4e..65fc5c48386 100644
--- a/board/ronetix/pm9g45/Kconfig
+++ b/board/ronetix/pm9g45/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_PM9G45
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "pm9g45"
 
diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c
index 83fd3bd754b..881d0805225 100644
--- a/board/samsung/arndale/arndale.c
+++ b/board/samsung/arndale/arndale.c
@@ -6,9 +6,9 @@
 
 #include <common.h>
 #include <usb.h>
+#include <asm/gpio.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/dwmmc.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/power.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -19,6 +19,8 @@ int board_usb_init(int index, enum usb_init_type init)
 	/* Configure gpios for usb 3503 hub:
 	 * disconnect, toggle reset and connect
 	 */
+	gpio_request(EXYNOS5_GPIO_D17, "usb_connect");
+	gpio_request(EXYNOS5_GPIO_X35, "usb_reset");
 	gpio_direction_output(EXYNOS5_GPIO_D17, 0);
 	gpio_direction_output(EXYNOS5_GPIO_X35, 0);
 
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 5c3c5bb9254..8b4c8e9a9db 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -13,10 +13,10 @@
 #include <tmu.h>
 #include <netdev.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/board.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/dwmmc.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/power.h>
@@ -28,19 +28,15 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int __exynos_early_init_f(void)
+__weak int exynos_early_init_f(void)
 {
 	return 0;
 }
-int exynos_early_init_f(void)
-	__attribute__((weak, alias("__exynos_early_init_f")));
 
-int __exynos_power_init(void)
+__weak int exynos_power_init(void)
 {
 	return 0;
 }
-int exynos_power_init(void)
-	__attribute__((weak, alias("__exynos_power_init")));
 
 #if defined CONFIG_EXYNOS_TMU
 /* Boot Time Thermal Analysis for SoC temperature threshold breach */
@@ -87,9 +83,6 @@ int board_init(void)
 	boot_temp_check();
 #endif
 
-#ifdef CONFIG_EXYNOS_SPI
-	spi_init();
-#endif
 	return exynos_init();
 }
 
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index 8766f0ca068..4538ac7f2a2 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -14,7 +14,6 @@
 #include <malloc.h>
 #include <linux/sizes.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
 #include <asm/gpio.h>
 #include <linux/input.h>
 #include <power/pmic.h>
@@ -412,6 +411,8 @@ void check_boot_mode(void)
 void keys_init(void)
 {
 	/* Set direction to input */
+	gpio_request(KEY_VOL_UP_GPIO, "volume-up");
+	gpio_request(KEY_VOL_DOWN_GPIO, "volume-down");
 	gpio_direction_input(KEY_VOL_UP_GPIO);
 	gpio_direction_input(KEY_VOL_DOWN_GPIO);
 }
diff --git a/board/samsung/goni/Kconfig b/board/samsung/goni/Kconfig
index a320c2bcb5f..cbbf5a93156 100644
--- a/board/samsung/goni/Kconfig
+++ b/board/samsung/goni/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_S5P_GONI
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "goni"
 
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index eb0f9bffae0..58cf96eaa84 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -7,7 +7,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 #include <asm/arch/mmc.h>
 #include <power/pmic.h>
 #include <usb/s3c_udc.h>
@@ -33,6 +33,16 @@ int board_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+void i2c_init_board(void)
+{
+	gpio_request(S5PC110_GPIO_J43, "i2c_clk");
+	gpio_request(S5PC110_GPIO_J40, "i2c_data");
+	gpio_direction_output(S5PC110_GPIO_J43, 1);
+	gpio_direction_output(S5PC110_GPIO_J40, 1);
+}
+#endif
+
 int power_init_board(void)
 {
 	int ret;
@@ -80,6 +90,7 @@ int board_mmc_init(bd_t *bis)
 	int i, ret, ret_sd = 0;
 
 	/* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */
+	gpio_request(S5PC110_GPIO_J27, "massmemory_en");
 	gpio_direction_output(S5PC110_GPIO_J27, 1);
 
 	/*
@@ -108,6 +119,7 @@ int board_mmc_init(bd_t *bis)
 	 * SD card (T_FLASH) detect and init
 	 * T_FLASH_DETECT: EINT28: GPH3[4] input mode
 	 */
+	gpio_request(S5PC110_GPIO_H34, "t_flash_detect");
 	gpio_cfg_pin(S5PC110_GPIO_H34, S5P_GPIO_INPUT);
 	gpio_set_pull(S5PC110_GPIO_H34, S5P_GPIO_PULL_UP);
 
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
index 5edb250f06b..33003ee9b56 100644
--- a/board/samsung/odroid/odroid.c
+++ b/board/samsung/odroid/odroid.c
@@ -356,21 +356,29 @@ static void board_clock_init(void)
 static void board_gpio_init(void)
 {
 	/* eMMC Reset Pin */
+	gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");
+
 	gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
 	gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
 	gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
 
 	/* Enable FAN (Odroid U3) */
+	gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control");
+
 	gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
 	gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
 	gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
 
 	/* OTG Vbus output (Odroid U3+) */
+	gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus");
+
 	gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
 	gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
 	gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
 
 	/* OTG INT (Odroid U3+) */
+	gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT");
+
 	gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
 	gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
 	gpio_direction_input(EXYNOS4X12_GPIO_X31);
@@ -403,7 +411,6 @@ static void board_init_i2c(void)
 int exynos_early_init_f(void)
 {
 	board_clock_init();
-	board_gpio_init();
 
 	return 0;
 }
@@ -414,6 +421,8 @@ int exynos_init(void)
 	gd->ram_size -= SZ_1M;
 	gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M;
 
+	board_gpio_init();
+
 	return 0;
 }
 
diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c
index a539267a1ca..99a2facd1ee 100644
--- a/board/samsung/origen/origen.c
+++ b/board/samsung/origen/origen.c
@@ -6,8 +6,8 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/periph.h>
 #include <asm/arch/pinmux.h>
diff --git a/board/samsung/smdk2410/Kconfig b/board/samsung/smdk2410/Kconfig
index 94f1e3c4ccf..e987b6496fd 100644
--- a/board/samsung/smdk2410/Kconfig
+++ b/board/samsung/smdk2410/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_SMDK2410
 
-config SYS_CPU
-	default "arm920t"
-
 config SYS_BOARD
 	default "smdk2410"
 
diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c
index d6ce1337b94..53ff7061d73 100644
--- a/board/samsung/smdk5250/exynos5-dt.c
+++ b/board/samsung/smdk5250/exynos5-dt.c
@@ -29,6 +29,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static void board_enable_audio_codec(void)
 {
 	/* Enable MAX98095 Codec */
+	gpio_request(EXYNOS5_GPIO_X17, "max98095_enable");
 	gpio_direction_output(EXYNOS5_GPIO_X17, 1);
 	gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
 }
@@ -199,16 +200,19 @@ static int board_dp_bridge_setup(void)
 	/* Setup the GPIOs */
 
 	/* PD is ACTIVE_LOW, and initially de-asserted */
+	gpio_request(EXYNOS5_GPIO_Y25, "dp_bridge_pd");
 	gpio_set_pull(EXYNOS5_GPIO_Y25, S5P_GPIO_PULL_NONE);
 	gpio_direction_output(EXYNOS5_GPIO_Y25, 1);
 
 	/* Reset is ACTIVE_LOW */
+	gpio_request(EXYNOS5_GPIO_X15, "dp_bridge_reset");
 	gpio_set_pull(EXYNOS5_GPIO_X15, S5P_GPIO_PULL_NONE);
 	gpio_direction_output(EXYNOS5_GPIO_X15, 0);
 
 	udelay(10);
 	gpio_set_value(EXYNOS5_GPIO_X15, 1);
 
+	gpio_request(EXYNOS5_GPIO_X07, "dp_bridge_hpd");
 	gpio_direction_input(EXYNOS5_GPIO_X07);
 
 	/*
@@ -236,10 +240,12 @@ static int board_dp_bridge_setup(void)
 void exynos_cfg_lcd_gpio(void)
 {
 	/* For Backlight */
+	gpio_request(EXYNOS5_GPIO_B20, "lcd_backlight");
 	gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
 	gpio_set_value(EXYNOS5_GPIO_B20, 1);
 
 	/* LCD power on */
+	gpio_request(EXYNOS5_GPIO_X15, "lcd_power");
 	gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
 	gpio_set_value(EXYNOS5_GPIO_X15, 1);
 
@@ -276,6 +282,7 @@ void exynos_backlight_on(unsigned int on)
 	mdelay(10);
 
 	/* board_dp_backlight_en */
+	gpio_request(EXYNOS5_GPIO_X30, "board_dp_backlight_en");
 	gpio_direction_output(EXYNOS5_GPIO_X30, 1);
 #endif
 }
diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c
index 270ee834e65..a691222b8b1 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -11,9 +11,9 @@
 #include <lcd.h>
 #include <spi.h>
 #include <errno.h>
+#include <asm/gpio.h>
 #include <asm/arch/board.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/system.h>
 #include <asm/arch/dp_info.h>
@@ -74,9 +74,12 @@ void exynos_lcd_power_on(void)
 	mdelay(5);
 
 	/* TODO(ajaykumar.rs@samsung.com): Use device tree */
+	gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");
 	gpio_direction_output(EXYNOS5420_GPIO_X35, 1);	/* EDP_SLP# */
 	mdelay(10);
+	gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");
 	gpio_direction_output(EXYNOS5420_GPIO_Y77, 1);	/* EDP_RST# */
+	gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
 	gpio_direction_input(EXYNOS5420_GPIO_X26);	/* EDP_HPD */
 	gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
 
@@ -88,6 +91,7 @@ void exynos_lcd_power_on(void)
 void exynos_backlight_on(unsigned int onoff)
 {
 	/* For PWM */
+	gpio_request(EXYNOS5420_GPIO_B20, "backlight_on");
 	gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(0x1));
 	gpio_set_value(EXYNOS5420_GPIO_B20, 1);
 
diff --git a/board/samsung/smdkc100/Kconfig b/board/samsung/smdkc100/Kconfig
index 5e6b0ddcdaa..d2157b4d05f 100644
--- a/board/samsung/smdkc100/Kconfig
+++ b/board/samsung/smdkc100/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_SMDKC100
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "smdkc100"
 
diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c
index e009564a598..66b6a9801f7 100644
--- a/board/samsung/smdkc100/smdkc100.c
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -7,9 +7,9 @@
  */
 
 #include <common.h>
+#include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/sromc.h>
-#include <asm/arch/gpio.h>
 #include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c
index 8eca358981f..cb7f9b0ac88 100644
--- a/board/samsung/smdkv310/smdkv310.c
+++ b/board/samsung/smdkv310/smdkv310.c
@@ -5,10 +5,10 @@
  */
 
 #include <common.h>
+#include <asm/gpio.h>
 #include <asm/io.h>
 #include <netdev.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/periph.h>
 #include <asm/arch/pinmux.h>
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 3dd340b7d8d..e163e45a587 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -10,8 +10,8 @@
 #include <common.h>
 #include <lcd.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/mipi_dsim.h>
@@ -63,6 +63,8 @@ void i2c_init_board(void)
 	}
 
 	/* I2C_8 -> FG */
+	gpio_request(EXYNOS4_GPIO_Y40, "i2c_clk");
+	gpio_request(EXYNOS4_GPIO_Y41, "i2c_data");
 	gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
 	gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
 }
@@ -346,12 +348,17 @@ int exynos_power_init(void)
 static unsigned int get_hw_revision(void)
 {
 	int hwrev = 0;
+	char str[10];
 	int i;
 
 	/* hw_rev[3:0] == GPE1[3:0] */
-	for (i = EXYNOS4_GPIO_E10; i < EXYNOS4_GPIO_E14; i++) {
-		gpio_cfg_pin(i, S5P_GPIO_INPUT);
-		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+	for (i = 0; i < 4; i++) {
+		int pin = i + EXYNOS4_GPIO_E10;
+
+		sprintf(str, "hw_rev%d", i);
+		gpio_request(pin, str);
+		gpio_cfg_pin(pin, S5P_GPIO_INPUT);
+		gpio_set_pull(pin, S5P_GPIO_PULL_NONE);
 	}
 
 	udelay(1);
@@ -517,6 +524,7 @@ static void board_power_init(void)
 static void exynos_uart_init(void)
 {
 	/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
+	gpio_request(EXYNOS4_GPIO_Y47, "uart_sel");
 	gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP);
 	gpio_direction_output(EXYNOS4_GPIO_Y47, 1);
 }
@@ -534,6 +542,7 @@ int exynos_early_init_f(void)
 
 void exynos_reset_lcd(void)
 {
+	gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
 	gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
 	udelay(10000);
 	gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index fa26e61244f..a7377497e5d 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <lcd.h>
+#include <asm/gpio.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/power.h>
 #include <asm/arch/mipi_dsim.h>
@@ -32,6 +33,7 @@ static inline u32 get_model_rev(void);
 static void check_hw_revision(void)
 {
 	int modelrev = 0;
+	char str[12];
 	int i;
 
 	/*
@@ -40,13 +42,22 @@ static void check_hw_revision(void)
 	 * TRM say that it may cause unexcepted state and leakage current.
 	 * and pull-none is only for output function.
 	 */
-	for (i = EXYNOS4X12_GPIO_M10; i < EXYNOS4X12_GPIO_M12; i++)
-		gpio_cfg_pin(i, S5P_GPIO_INPUT);
+	for (i = 0; i < 2; i++) {
+		int pin = i + EXYNOS4X12_GPIO_M10;
+
+		sprintf(str, "model_rev%d", i);
+		gpio_request(pin, str);
+		gpio_cfg_pin(pin, S5P_GPIO_INPUT);
+	}
 
 	/* GPM1[5:2]: HW_REV[3:0] */
-	for (i = EXYNOS4X12_GPIO_M12; i < EXYNOS4X12_GPIO_M16; i++) {
-		gpio_cfg_pin(i, S5P_GPIO_INPUT);
-		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+	for (i = 0; i < 4; i++) {
+		int pin = i + EXYNOS4X12_GPIO_M12;
+
+		sprintf(str, "hw_rev%d", i);
+		gpio_request(pin, str);
+		gpio_cfg_pin(pin, S5P_GPIO_INPUT);
+		gpio_set_pull(pin, S5P_GPIO_PULL_NONE);
 	}
 
 	/* GPM1[1:0]: MODEL_REV[1:0] */
@@ -102,10 +113,14 @@ static void board_init_i2c(void)
 	}
 
 	/* I2C_8 */
+	gpio_request(EXYNOS4X12_GPIO_F14, "i2c8_clk");
+	gpio_request(EXYNOS4X12_GPIO_F15, "i2c8_data");
 	gpio_direction_output(EXYNOS4X12_GPIO_F14, 1);
 	gpio_direction_output(EXYNOS4X12_GPIO_F15, 1);
 
 	/* I2C_9 */
+	gpio_request(EXYNOS4X12_GPIO_M21, "i2c9_clk");
+	gpio_request(EXYNOS4X12_GPIO_M20, "i2c9_data");
 	gpio_direction_output(EXYNOS4X12_GPIO_M21, 1);
 	gpio_direction_output(EXYNOS4X12_GPIO_M20, 1);
 }
@@ -387,6 +402,7 @@ void exynos_lcd_power_on(void)
 	struct pmic *p = pmic_get("MAX77686_PMIC");
 
 	/* LCD_2.2V_EN: GPC0[1] */
+	gpio_request(EXYNOS4X12_GPIO_C01, "lcd_2v2_en");
 	gpio_set_pull(EXYNOS4X12_GPIO_C01, S5P_GPIO_PULL_UP);
 	gpio_direction_output(EXYNOS4X12_GPIO_C01, 1);
 
@@ -399,6 +415,7 @@ void exynos_lcd_power_on(void)
 void exynos_reset_lcd(void)
 {
 	/* reset lcd */
+	gpio_request(EXYNOS4X12_GPIO_F21, "lcd_reset");
 	gpio_direction_output(EXYNOS4X12_GPIO_F21, 0);
 	udelay(10);
 	gpio_set_value(EXYNOS4X12_GPIO_F21, 1);
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index 47e7f538d65..df4671394f6 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -12,7 +12,6 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <asm/arch/adc.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/watchdog.h>
 #include <ld9040.h>
@@ -202,53 +201,6 @@ int exynos_early_init_f(void)
 	return 0;
 }
 
-#ifdef CONFIG_SOFT_SPI
-static void soft_spi_init(void)
-{
-	gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK,
-		CONFIG_SOFT_SPI_MODE & SPI_CPOL);
-	gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1);
-	gpio_direction_input(CONFIG_SOFT_SPI_GPIO_MISO);
-	gpio_direction_output(CONFIG_SOFT_SPI_GPIO_CS,
-		!(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
-		!(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
-	SPI_SCL(1);
-	gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
-		CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
-		!(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
-}
-
-int  spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void universal_spi_scl(int bit)
-{
-	gpio_set_value(CONFIG_SOFT_SPI_GPIO_SCLK, bit);
-}
-
-void universal_spi_sda(int bit)
-{
-	gpio_set_value(CONFIG_SOFT_SPI_GPIO_MOSI, bit);
-}
-
-int universal_spi_read(void)
-{
-	return gpio_get_value(CONFIG_SOFT_SPI_GPIO_MISO);
-}
-#endif
-
 static void init_pmic_lcd(void)
 {
 	unsigned char val;
@@ -331,9 +283,8 @@ void exynos_cfg_lcd_gpio(void)
 	}
 
 	/* gpio pad configuration for LCD reset. */
+	gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
 	gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT);
-
-	spi_init();
 }
 
 int mipi_power(void)
@@ -377,6 +328,8 @@ void exynos_enable_ldo(unsigned int onoff)
 
 int exynos_init(void)
 {
+	char buf[16];
+
 	gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
 
 	switch (get_hwrev()) {
@@ -387,6 +340,7 @@ int exynos_init(void)
 		 * you should set it HIGH since it removes the inverter
 		 */
 		/* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
+		gpio_request(EXYNOS4_GPIO_E36, "ldo_en");
 		gpio_direction_output(EXYNOS4_GPIO_E36, 0);
 		break;
 	default:
@@ -395,13 +349,18 @@ int exynos_init(void)
 		 * But set it as HIGH to ensure
 		 */
 		/* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
+		gpio_request(EXYNOS4_GPIO_E13, "massmemory_en");
 		gpio_direction_output(EXYNOS4_GPIO_E13, 1);
 		break;
 	}
 
-#ifdef CONFIG_SOFT_SPI
-	soft_spi_init();
-#endif
+	/* Request soft I2C gpios */
+	sprintf(buf, "soft_i2c_scl");
+	gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, buf);
+
+	sprintf(buf, "soft_i2c_sda");
+	gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, buf);
+
 	check_hw_revision();
 	printf("HW Revision:\t0x%x\n", board_rev);
 
diff --git a/board/sandisk/sansa_fuze_plus/Kconfig b/board/sandisk/sansa_fuze_plus/Kconfig
index 99e7379cd27..ab4a29255cc 100644
--- a/board/sandisk/sansa_fuze_plus/Kconfig
+++ b/board/sandisk/sansa_fuze_plus/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_SANSA_FUZE_PLUS
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "sansa_fuze_plus"
 
diff --git a/board/scb9328/Kconfig b/board/scb9328/Kconfig
index 7ff7dbc4a5a..68e99ea2e33 100644
--- a/board/scb9328/Kconfig
+++ b/board/scb9328/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_SCB9328
 
-config SYS_CPU
-	default "arm920t"
-
 config SYS_BOARD
 	default "scb9328"
 
diff --git a/board/schulercontrol/sc_sps_1/Kconfig b/board/schulercontrol/sc_sps_1/Kconfig
index 379e53b5568..2461d0cc504 100644
--- a/board/schulercontrol/sc_sps_1/Kconfig
+++ b/board/schulercontrol/sc_sps_1/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_SC_SPS_1
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "sc_sps_1"
 
diff --git a/board/siemens/corvus/Kconfig b/board/siemens/corvus/Kconfig
index 80018c51b59..7b505aac36f 100644
--- a/board/siemens/corvus/Kconfig
+++ b/board/siemens/corvus/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_CORVUS
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "corvus"
 
diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig
index b930a76fa9f..d138ecea9d4 100644
--- a/board/siemens/draco/Kconfig
+++ b/board/siemens/draco/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_DRACO
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "draco"
 
@@ -19,9 +16,6 @@ endif
 
 if TARGET_DXR2
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "draco"
 
diff --git a/board/siemens/pxm2/Kconfig b/board/siemens/pxm2/Kconfig
index f76ec69bba7..62604ecb392 100644
--- a/board/siemens/pxm2/Kconfig
+++ b/board/siemens/pxm2/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_PXM2
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "pxm2"
 
diff --git a/board/siemens/rut/Kconfig b/board/siemens/rut/Kconfig
index b7e49dac26d..33710776628 100644
--- a/board/siemens/rut/Kconfig
+++ b/board/siemens/rut/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_RUT
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "rut"
 
diff --git a/board/siemens/taurus/Kconfig b/board/siemens/taurus/Kconfig
index 1fedbd36bcc..c07d244bc36 100644
--- a/board/siemens/taurus/Kconfig
+++ b/board/siemens/taurus/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_TAURUS
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "taurus"
 
diff --git a/board/silica/pengwyn/Kconfig b/board/silica/pengwyn/Kconfig
index 90bfb69e5ed..f2e1098f62a 100644
--- a/board/silica/pengwyn/Kconfig
+++ b/board/silica/pengwyn/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_PENGWYN
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "pengwyn"
 
diff --git a/board/solidrun/hummingboard/Kconfig b/board/solidrun/hummingboard/Kconfig
index a4eb62fcef8..36b79045bc4 100644
--- a/board/solidrun/hummingboard/Kconfig
+++ b/board/solidrun/hummingboard/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_HUMMINGBOARD
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "hummingboard"
 
diff --git a/board/spear/spear300/Kconfig b/board/spear/spear300/Kconfig
index 5b702ced698..27360f32e41 100644
--- a/board/spear/spear300/Kconfig
+++ b/board/spear/spear300/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_SPEAR300
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "spear300"
 
diff --git a/board/spear/spear310/Kconfig b/board/spear/spear310/Kconfig
index b8f51547337..0c95fa35a00 100644
--- a/board/spear/spear310/Kconfig
+++ b/board/spear/spear310/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_SPEAR310
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "spear310"
 
diff --git a/board/spear/spear320/Kconfig b/board/spear/spear320/Kconfig
index 150d64ff98e..df176230f40 100644
--- a/board/spear/spear320/Kconfig
+++ b/board/spear/spear320/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_SPEAR320
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "spear320"
 
diff --git a/board/spear/spear600/Kconfig b/board/spear/spear600/Kconfig
index f03e19ebd3c..d562e64f078 100644
--- a/board/spear/spear600/Kconfig
+++ b/board/spear/spear600/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_SPEAR600
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "spear600"
 
diff --git a/board/spear/x600/Kconfig b/board/spear/x600/Kconfig
index 620be5f56ed..6a1c5c7b401 100644
--- a/board/spear/x600/Kconfig
+++ b/board/spear/x600/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_X600
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "x600"
 
diff --git a/board/st-ericsson/snowball/Kconfig b/board/st-ericsson/snowball/Kconfig
index 7eb99697d5f..0b3a0cca6ce 100644
--- a/board/st-ericsson/snowball/Kconfig
+++ b/board/st-ericsson/snowball/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_SNOWBALL
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "snowball"
 
diff --git a/board/st-ericsson/u8500/Kconfig b/board/st-ericsson/u8500/Kconfig
index ca258762697..909f30db4b6 100644
--- a/board/st-ericsson/u8500/Kconfig
+++ b/board/st-ericsson/u8500/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_U8500_HREF
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "u8500"
 
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index bcd0a55a1e5..5b2d091122d 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -1,28 +1,141 @@
-if TARGET_SUN4I
+if ARCH_SUNXI
 
-config SYS_CONFIG_NAME
-	default "sun4i"
+choice
+	prompt "Sunxi SoC Variant"
 
-endif
+config MACH_SUN4I
+	bool "sun4i (Allwinner A10)"
+	select CPU_V7
+	select SUPPORT_SPL
 
-if TARGET_SUN5I
+config MACH_SUN5I
+	bool "sun5i (Allwinner A13)"
+	select CPU_V7
+	select SUPPORT_SPL
 
-config SYS_CONFIG_NAME
-	default "sun5i"
+config MACH_SUN6I
+	bool "sun6i (Allwinner A31)"
+	select CPU_V7
 
-endif
+config MACH_SUN7I
+	bool "sun7i (Allwinner A20)"
+	select CPU_V7
+	select SUPPORT_SPL
+
+config MACH_SUN8I
+	bool "sun8i (Allwinner A23)"
+	select CPU_V7
 
-if TARGET_SUN7I
+endchoice
 
 config SYS_CONFIG_NAME
-	default "sun7i"
+	string
+	default "sun4i" if MACH_SUN4I
+	default "sun5i" if MACH_SUN5I
+	default "sun6i" if MACH_SUN6I
+	default "sun7i" if MACH_SUN7I
+	default "sun8i" if MACH_SUN8I
 
-endif
+choice
+	prompt "Board"
+
+config TARGET_A10_OLINUXINO_L
+	bool "A10_OLINUXINO_L"
+	depends on MACH_SUN4I
+
+config TARGET_A10S_OLINUXINO_M
+	bool "A10S_OLINUXINO_M"
+	depends on MACH_SUN5I
+
+config TARGET_A13_OLINUXINOM
+	bool "A13_OLINUXINOM"
+	depends on MACH_SUN5I
+
+config TARGET_A13_OLINUXINO
+	bool "A13_OLINUXINO"
+	depends on MACH_SUN5I
+
+config TARGET_A20_OLINUXINO_L2
+	bool "A20_OLINUXINO_L2"
+	depends on MACH_SUN7I
+
+config TARGET_A20_OLINUXINO_L
+	bool "A20_OLINUXINO_L"
+	depends on MACH_SUN7I
+
+config TARGET_A20_OLINUXINO_M
+	bool "A20_OLINUXINO_M"
+	depends on MACH_SUN7I
+
+config TARGET_AUXTEK_T004
+	bool "AUXTEK_T004"
+	depends on MACH_SUN5I
+
+config TARGET_BANANAPI
+	bool "BANANAPI"
+	depends on MACH_SUN7I
+
+config TARGET_COLOMBUS
+	bool "COLOMBUS"
+	depends on MACH_SUN6I
+
+config TARGET_CUBIEBOARD2
+	bool "CUBIEBOARD2"
+	depends on MACH_SUN7I
+
+config TARGET_CUBIEBOARD
+	bool "CUBIEBOARD"
+	depends on MACH_SUN4I
 
-if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN7I
+config TARGET_CUBIETRUCK
+	bool "CUBIETRUCK"
+	depends on MACH_SUN7I
 
-config SYS_CPU
-	default "armv7"
+config TARGET_IPPO_Q8H_V5
+	bool "IPPO_Q8H_V5"
+	depends on MACH_SUN8I
+
+config TARGET_PCDUINO3
+	bool "PCDUINO3"
+	depends on MACH_SUN7I
+
+config TARGET_MELE_A1000G
+	bool "MELE_A1000G"
+	depends on MACH_SUN4I
+
+config TARGET_MELE_A1000
+	bool "MELE_A1000"
+	depends on MACH_SUN4I
+
+config TARGET_MELE_M3
+	bool "MELE_M3"
+	depends on MACH_SUN7I
+
+config TARGET_MINI_X_1GB
+	bool "MINI_X_1GB"
+	depends on MACH_SUN4I
+
+config TARGET_MINI_X
+	bool "MINI_X"
+	depends on MACH_SUN4I
+
+config TARGET_BA10_TV_BOX
+	bool "BA10_TV_BOX"
+	depends on MACH_SUN4I
+
+config TARGET_I12_TVBOX
+	bool "I12_TVBOX"
+	depends on MACH_SUN7I
+
+config TARGET_QT840A
+	bool "QT840A"
+	depends on MACH_SUN7I
+
+config TARGET_R7DONGLE
+	bool "R7DONGLE"
+	depends on MACH_SUN5I
+
+endchoice
 
 config SYS_BOARD
 	default "sunxi"
@@ -30,7 +143,53 @@ config SYS_BOARD
 config SYS_SOC
 	default "sunxi"
 
+config SPL_FEL
+	bool "SPL/FEL mode support"
+	depends on SPL
+	default n
+
 config FDTFILE
 	string "Default fdtfile env setting for this board"
 
+config OLD_SUNXI_KERNEL_COMPAT
+	boolean "Enable workarounds for booting old kernels"
+	default n
+	---help---
+	Set this to enable various workarounds for old kernels, this results in
+	sub-optimal settings for newer kernels, only enable if needed.
+
+config MMC0_CD_PIN
+	string "Card detect pin for mmc0"
+	default ""
+	---help---
+	Set the card detect pin for mmc0, leave empty to not use cd. This
+	takes a string in the format understood by sunxi_name_to_gpio, e.g.
+	PH1 for pin 1 of port H.
+
+config MMC1_CD_PIN
+	string "Card detect pin for mmc1"
+	default ""
+	---help---
+	See MMC0_CD_PIN help text.
+
+config MMC2_CD_PIN
+	string "Card detect pin for mmc2"
+	default ""
+	---help---
+	See MMC0_CD_PIN help text.
+
+config MMC3_CD_PIN
+	string "Card detect pin for mmc3"
+	default ""
+	---help---
+	See MMC0_CD_PIN help text.
+
+config MMC_SUNXI_SLOT_EXTRA
+	int "mmc extra slot number"
+	default -1
+	---help---
+	sunxi builds always enable mmc0, some boards also have a second sdcard
+	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
+	support for this.
+
 endif
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 4f32195dcd9..b3c77a83cb7 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -8,6 +8,7 @@ F:	configs/ba10_tv_box_defconfig
 F:	configs/Cubieboard_defconfig
 F:	configs/Mele_A1000_defconfig
 F:	configs/Mele_A1000G_defconfig
+F:	configs/Mele_M3_defconfig
 F:	configs/Mini-X_defconfig
 F:	configs/Mini-X-1Gb_defconfig
 F:	include/configs/sun5i.h
@@ -21,6 +22,7 @@ F:	configs/A20-OLinuXino_MICRO_defconfig
 F:	configs/Bananapi_defconfig
 F:	configs/i12-tvbox_defconfig
 F:	configs/Linksprite_pcDuino3_defconfig
+F:	configs/Linksprite_pcDuino3_fdt_defconfig
 F:	configs/qt840a_defconfig
 
 CUBIEBOARD2 BOARD
@@ -38,3 +40,19 @@ M:	FUKAUMI Naoki <naobsd@gmail.com>
 S:	Maintained
 F:	board/sunxi/dram_a20_olinuxino_l.c
 F:	configs/A20-OLinuXino-Lime_defconfig
+
+A20-OLINUXINO-LIME2 BOARD
+M:	Iain Paton <ipaton0@gmail.com>
+S:	Maintained
+F:	board/sunxi/dram_a20_olinuxino_l2.c
+F:	configs/A20-OLinuXino-Lime2_defconfig
+
+COLOMBUS BOARD
+M:	Maxime Ripard <maxime.ripard@free-electrons.com>
+S:	Maintained
+F:	configs/Colombus_defconfig
+
+IPPO-Q8H-V5 BOARD
+M:	Chen-Yu Tsai <wens@csie.org>
+S:	Maintained
+F:	configs/Ippo_q8h_v5_defconfig
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index 56073a024d1..b84ff9b8ef8 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -11,24 +11,26 @@
 obj-y	+= board.o
 obj-$(CONFIG_SUNXI_GMAC)	+= gmac.o
 obj-$(CONFIG_SUNXI_AHCI)	+= ahci.o
-obj-$(CONFIG_A10_OLINUXINO_L)	+= dram_a10_olinuxino_l.o
-obj-$(CONFIG_A10S_OLINUXINO_M)	+= dram_a10s_olinuxino_m.o
-obj-$(CONFIG_A13_OLINUXINO)	+= dram_a13_olinuxino.o
-obj-$(CONFIG_A13_OLINUXINOM)	+= dram_a13_oli_micro.o
-obj-$(CONFIG_A20_OLINUXINO_L)	+= dram_a20_olinuxino_l.o
-obj-$(CONFIG_A20_OLINUXINO_M)	+= dram_sun7i_384_1024_iow16.o
+obj-$(CONFIG_TARGET_A10_OLINUXINO_L)	+= dram_a10_olinuxino_l.o
+obj-$(CONFIG_TARGET_A10S_OLINUXINO_M)	+= dram_a10s_olinuxino_m.o
+obj-$(CONFIG_TARGET_A13_OLINUXINO)	+= dram_a13_olinuxino.o
+obj-$(CONFIG_TARGET_A13_OLINUXINOM)	+= dram_a13_oli_micro.o
+obj-$(CONFIG_TARGET_A20_OLINUXINO_L)	+= dram_a20_olinuxino_l.o
+obj-$(CONFIG_TARGET_A20_OLINUXINO_L2)	+= dram_a20_olinuxino_l2.o
+obj-$(CONFIG_TARGET_A20_OLINUXINO_M)	+= dram_sun7i_384_1024_iow16.o
 # This is not a typo, uses the same mem settings as the a10s-olinuxino-m
-obj-$(CONFIG_AUXTEK_T004)	+= dram_a10s_olinuxino_m.o
-obj-$(CONFIG_BA10_TV_BOX)	+= dram_sun4i_384_1024_iow8.o
-obj-$(CONFIG_BANANAPI)		+= dram_bananapi.o
-obj-$(CONFIG_CUBIEBOARD)	+= dram_cubieboard.o
-obj-$(CONFIG_CUBIEBOARD2)	+= dram_cubieboard2.o
-obj-$(CONFIG_CUBIETRUCK)	+= dram_cubietruck.o
-obj-$(CONFIG_I12_TVBOX)		+= dram_sun7i_384_1024_iow16.o
-obj-$(CONFIG_MELE_A1000)	+= dram_sun4i_360_512.o
-obj-$(CONFIG_MELE_A1000G)	+= dram_sun4i_360_1024_iow8.o
-obj-$(CONFIG_MINI_X)		+= dram_sun4i_360_512.o
-obj-$(CONFIG_MINI_X_1GB)	+= dram_sun4i_360_1024_iow16.o
-obj-$(CONFIG_PCDUINO3)		+= dram_linksprite_pcduino3.o
-obj-$(CONFIG_QT840A)		+= dram_sun7i_384_512_busw16_iow16.o
-obj-$(CONFIG_R7DONGLE)		+= dram_r7dongle.o
+obj-$(CONFIG_TARGET_AUXTEK_T004)	+= dram_a10s_olinuxino_m.o
+obj-$(CONFIG_TARGET_BA10_TV_BOX)	+= dram_sun4i_384_1024_iow8.o
+obj-$(CONFIG_TARGET_BANANAPI)		+= dram_bananapi.o
+obj-$(CONFIG_TARGET_CUBIEBOARD)		+= dram_cubieboard.o
+obj-$(CONFIG_TARGET_CUBIEBOARD2)	+= dram_cubieboard2.o
+obj-$(CONFIG_TARGET_CUBIETRUCK)		+= dram_cubietruck.o
+obj-$(CONFIG_TARGET_I12_TVBOX)		+= dram_sun7i_384_1024_iow16.o
+obj-$(CONFIG_TARGET_MELE_A1000)		+= dram_sun4i_360_512.o
+obj-$(CONFIG_TARGET_MELE_A1000G)	+= dram_sun4i_360_1024_iow8.o
+obj-$(CONFIG_TARGET_MELE_M3)		+= dram_sun7i_384_1024_iow16.o
+obj-$(CONFIG_TARGET_MINI_X)		+= dram_sun4i_360_512.o
+obj-$(CONFIG_TARGET_MINI_X_1GB)		+= dram_sun4i_360_1024_iow16.o
+obj-$(CONFIG_TARGET_PCDUINO3)		+= dram_linksprite_pcduino3.o
+obj-$(CONFIG_TARGET_QT840A)		+= dram_sun7i_384_512_busw16_iow16.o
+obj-$(CONFIG_TARGET_R7DONGLE)		+= dram_r7dongle.o
diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c
index 0c262eabb75..5e123285b03 100644
--- a/board/sunxi/ahci.c
+++ b/board/sunxi/ahci.c
@@ -74,6 +74,7 @@ void scsi_init(void)
 {
 	printf("SUNXI SCSI INIT\n");
 #ifdef CONFIG_SATAPWR
+	gpio_request(CONFIG_SATAPWR, "satapwr");
 	gpio_direction_output(CONFIG_SATAPWR, 1);
 #endif
 
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 2179e234e21..03890c8c9ce 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -12,6 +12,7 @@
  */
 
 #include <common.h>
+#include <mmc.h>
 #ifdef CONFIG_AXP152_POWER
 #include <axp152.h>
 #endif
@@ -70,9 +71,9 @@ static void mmc_pinmux_setup(int sdc)
 		break;
 
 	case 1:
-		/* CMD-PH22, CLK-PH23, D0~D3-PH24~27 : 5 */
-		for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
-			sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1);
+		/* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */
+		for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
+			sunxi_gpio_set_cfgpin(pin, SUN5I_GPG3_SDC1);
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
@@ -104,11 +105,36 @@ static void mmc_pinmux_setup(int sdc)
 
 int board_mmc_init(bd_t *bis)
 {
+	__maybe_unused struct mmc *mmc0, *mmc1;
+	__maybe_unused char buf[512];
+
 	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
-	sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
-#if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA)
+	mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
+	if (!mmc0)
+		return -1;
+
+#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
 	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
-	sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
+	mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
+	if (!mmc1)
+		return -1;
+#endif
+
+#if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
+	/*
+	 * Both mmc0 and mmc2 are bootable, figure out where we're booting
+	 * from. Try mmc0 first, just like the brom does.
+	 */
+	if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 &&
+	    mmc0->block_dev.block_read(0, 16, 1, buf) == 1) {
+		buf[12] = 0;
+		if (strcmp(&buf[4], "eGON.BT0") == 0)
+			return 0;
+	}
+
+	/* no bootable card in mmc0, so we must be booting from mmc2, swap */
+	mmc0->block_dev.dev = 1;
+	mmc1->block_dev.dev = 0;
 #endif
 
 	return 0;
diff --git a/board/sunxi/dram_a20_olinuxino_l2.c b/board/sunxi/dram_a20_olinuxino_l2.c
new file mode 100644
index 00000000000..2115d37470a
--- /dev/null
+++ b/board/sunxi/dram_a20_olinuxino_l2.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+	.clock = 480,
+	.type = 3,
+	.rank_num = 1,
+	.density = 4096,
+	.io_width = 16,
+	.bus_width = 32,
+	.cas = 9,
+	.zq = 0x7f,
+	.odt_en = 0,
+	.size = 1024,
+	.tpr0 = 0x42d899b7,
+	.tpr1 = 0xa090,
+	.tpr2 = 0x22a00,
+	.tpr3 = 0,
+	.tpr4 = 0,
+	.tpr5 = 0,
+	.emr1 = 0x4,
+	.emr2 = 0x10,
+	.emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+	return dramc_init(&dram_para);
+}
diff --git a/board/syteco/jadecpu/Kconfig b/board/syteco/jadecpu/Kconfig
index 3965e90ad91..6e9392e21fc 100644
--- a/board/syteco/jadecpu/Kconfig
+++ b/board/syteco/jadecpu/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_JADECPU
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "jadecpu"
 
diff --git a/board/syteco/zmx25/Kconfig b/board/syteco/zmx25/Kconfig
index 260774dced1..59a415d65fa 100644
--- a/board/syteco/zmx25/Kconfig
+++ b/board/syteco/zmx25/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_ZMX25
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "zmx25"
 
diff --git a/board/taskit/stamp9g20/Kconfig b/board/taskit/stamp9g20/Kconfig
index 67be227b727..3139f9af864 100644
--- a/board/taskit/stamp9g20/Kconfig
+++ b/board/taskit/stamp9g20/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_STAMP9G20
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "stamp9g20"
 
diff --git a/board/technexion/tao3530/tao3530.h b/board/technexion/tao3530/tao3530.h
index daff1094802..4a94399fc98 100644
--- a/board/technexion/tao3530/tao3530.h
+++ b/board/technexion/tao3530/tao3530.h
@@ -275,7 +275,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SYS_OFF_MODE), (IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(SYS_CLKOUT1), (IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(SYS_CLKOUT2), (IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(JTAG_nTRST),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_NTRST),	(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(JTAG_TCK),	(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(JTAG_TMS),	(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(JTAG_TDI),	(IEN  | PTD | DIS | M0)) \
diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c
index 054e7ccdedf..a4aed3ba8ba 100644
--- a/board/technexion/twister/twister.c
+++ b/board/technexion/twister/twister.c
@@ -16,6 +16,8 @@
 #include <asm/omap_gpio.h>
 #include <asm/arch/mmc_host_def.h>
 #include <i2c.h>
+#include <spl.h>
+#include <mmc.h>
 #include <asm/gpio.h>
 #ifdef CONFIG_USB_EHCI
 #include <usb.h>
diff --git a/board/technexion/twister/twister.h b/board/technexion/twister/twister.h
index 62fbfdfed64..e286bd4522f 100644
--- a/board/technexion/twister/twister.h
+++ b/board/technexion/twister/twister.h
@@ -337,7 +337,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
 	/* JTAG */\
-	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_NTRST),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) \
diff --git a/board/teejet/mt_ventoux/mt_ventoux.h b/board/teejet/mt_ventoux/mt_ventoux.h
index aba71a84bf9..bc85ad4350a 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.h
+++ b/board/teejet/mt_ventoux/mt_ventoux.h
@@ -339,7 +339,7 @@ const omap3_sysinfo sysinfo = {
 			/* gpio_10 */\
 	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
 	/* JTAG */\
-	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_NTRST),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) \
diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig
index d8958ef0b86..b9f6bd71229 100644
--- a/board/ti/am335x/Kconfig
+++ b/board/ti/am335x/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_AM335X_EVM
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "am335x"
 
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index f4bb9f890b5..680f6560f25 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -359,9 +359,9 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
 		configure_module_pin_mux(i2c1_pin_mux);
 		configure_module_pin_mux(mii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux);
-#if defined(CONFIG_NAND)
+#if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT)
 		configure_module_pin_mux(nand_pin_mux);
-#elif defined(CONFIG_NOR)
+#elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
 		configure_module_pin_mux(bone_norcape_pin_mux);
 #else
 		configure_module_pin_mux(mmc1_pin_mux);
diff --git a/board/ti/am3517crane/am3517crane.h b/board/ti/am3517crane/am3517crane.h
index e131c8fb99f..6289ca787c1 100644
--- a/board/ti/am3517crane/am3517crane.h
+++ b/board/ti/am3517crane/am3517crane.h
@@ -284,7 +284,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SYS_CLKOUT1),    (IEN  | PTD | DIS | M4))/*GPIO_10 TP*/\
 	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0))\
 	/*JTAG*/\
-	MUX_VAL(CP(JTAG_nTRST),	(IEN  | PTD | DIS | M0))\
+	MUX_VAL(CP(JTAG_NTRST),	(IEN  | PTD | DIS | M0))\
 	MUX_VAL(CP(JTAG_TCK),   (IEN  | PTD | DIS | M0))\
 	MUX_VAL(CP(JTAG_TMS),   (IEN  | PTD | DIS | M0))\
 	MUX_VAL(CP(JTAG_TDI),	(IEN  | PTD | DIS | M0))\
diff --git a/board/ti/am43xx/Kconfig b/board/ti/am43xx/Kconfig
index 47b96bd7edd..8d1c16883d8 100644
--- a/board/ti/am43xx/Kconfig
+++ b/board/ti/am43xx/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_AM43XX_EVM
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "am43xx"
 
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 94b99bf5376..4c5e38136fd 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -14,6 +14,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <dm.h>
+#include <ns16550.h>
 #ifdef CONFIG_STATUS_LED
 #include <status_led.h>
 #endif
@@ -70,6 +72,17 @@ static struct {
 	char env_setting[64];
 } expansion_config;
 
+static const struct ns16550_platdata beagle_serial = {
+	OMAP34XX_UART3,
+	2,
+	V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(beagle_uart) = {
+	"serial_omap",
+	&beagle_serial
+};
+
 /*
  * Routine: board_init
  * Description: Early hardware init.
@@ -103,22 +116,22 @@ int board_init(void)
  */
 static int get_board_revision(void)
 {
-	int revision;
-
-	if (!gpio_request(171, "") &&
-	    !gpio_request(172, "") &&
-	    !gpio_request(173, "")) {
-
-		gpio_direction_input(171);
-		gpio_direction_input(172);
-		gpio_direction_input(173);
-
-		revision = gpio_get_value(173) << 2 |
-			   gpio_get_value(172) << 1 |
-			   gpio_get_value(171);
-	} else {
-		printf("Error: unable to acquire board revision GPIOs\n");
-		revision = -1;
+	static int revision = -1;
+
+	if (revision == -1) {
+		if (!gpio_request(171, "rev0") &&
+		    !gpio_request(172, "rev1") &&
+		    !gpio_request(173, "rev2")) {
+			gpio_direction_input(171);
+			gpio_direction_input(172);
+			gpio_direction_input(173);
+
+			revision = gpio_get_value(173) << 2 |
+				gpio_get_value(172) << 1 |
+				gpio_get_value(171);
+		} else {
+			printf("Error: unable to acquire board revision GPIOs\n");
+		}
 	}
 
 	return revision;
@@ -258,7 +271,7 @@ static void beagle_dvi_pup(void)
 	case REVISION_AXBX:
 	case REVISION_CX:
 	case REVISION_C4:
-		gpio_request(170, "");
+		gpio_request(170, "dvi");
 		gpio_direction_output(170, 0);
 		gpio_set_value(170, 1);
 		break;
diff --git a/board/ti/beagle/led.c b/board/ti/beagle/led.c
index 89b8dd3c3c1..a913a4c84aa 100644
--- a/board/ti/beagle/led.c
+++ b/board/ti/beagle/led.c
@@ -27,47 +27,46 @@ void green_led_on(void)
 }
 #endif
 
+static int get_led_gpio(led_id_t mask)
+{
+#ifdef STATUS_LED_BIT
+	if (STATUS_LED_BIT & mask)
+		return BEAGLE_LED_USR0;
+#endif
+#ifdef STATUS_LED_BIT1
+	if (STATUS_LED_BIT1 & mask)
+		return BEAGLE_LED_USR1;
+#endif
+
+	return 0;
+}
+
 void __led_init (led_id_t mask, int state)
 {
-	__led_set (mask, state);
+	int toggle_gpio;
+
+	toggle_gpio = get_led_gpio(mask);
+
+	if (toggle_gpio && !gpio_request(toggle_gpio, "led"))
+		__led_set(mask, state);
 }
 
 void __led_toggle (led_id_t mask)
 {
-	int state, toggle_gpio = 0;
-#ifdef STATUS_LED_BIT
-	if (!toggle_gpio && STATUS_LED_BIT & mask)
-		toggle_gpio = BEAGLE_LED_USR0;
-#endif
-#ifdef STATUS_LED_BIT1
-	if (!toggle_gpio && STATUS_LED_BIT1 & mask)
-		toggle_gpio = BEAGLE_LED_USR1;
-#endif
+	int state, toggle_gpio;
+
+	toggle_gpio = get_led_gpio(mask);
 	if (toggle_gpio) {
-		if (!gpio_request(toggle_gpio, "")) {
-			gpio_direction_output(toggle_gpio, 0);
-			state = gpio_get_value(toggle_gpio);
-			gpio_set_value(toggle_gpio, !state);
-		}
+		state = gpio_get_value(toggle_gpio);
+		gpio_direction_output(toggle_gpio, !state);
 	}
 }
 
 void __led_set (led_id_t mask, int state)
 {
-#ifdef STATUS_LED_BIT
-	if (STATUS_LED_BIT & mask) {
-		if (!gpio_request(BEAGLE_LED_USR0, "")) {
-			gpio_direction_output(BEAGLE_LED_USR0, 0);
-			gpio_set_value(BEAGLE_LED_USR0, state);
-		}
-	}
-#endif
-#ifdef STATUS_LED_BIT1
-	if (STATUS_LED_BIT1 & mask) {
-		if (!gpio_request(BEAGLE_LED_USR1, "")) {
-			gpio_direction_output(BEAGLE_LED_USR1, 0);
-			gpio_set_value(BEAGLE_LED_USR1, state);
-		}
-	}
-#endif
+	int toggle_gpio;
+
+	toggle_gpio = get_led_gpio(mask);
+	if (toggle_gpio)
+		gpio_direction_output(toggle_gpio, state);
 }
diff --git a/board/ti/evm/evm.h b/board/ti/evm/evm.h
index f50193d99af..91e9b88c548 100644
--- a/board/ti/evm/evm.h
+++ b/board/ti/evm/evm.h
@@ -300,7 +300,7 @@ static void reset_net_chip(void);
 	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
 	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
 	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) /*SYS_CLKOUT2*/\
-	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) /*JTAG_nTRST*/\
+	MUX_VAL(CP(JTAG_NTRST),		(IEN  | PTD | DIS | M0)) /*JTAG_NTRST*/\
 	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) /*JTAG_TCK*/\
 	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) /*JTAG_TMS*/\
 	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) /*JTAG_TDI*/\
diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig
index 9c1e103a20f..96c5f22eade 100644
--- a/board/ti/ks2_evm/Kconfig
+++ b/board/ti/ks2_evm/Kconfig
@@ -23,3 +23,19 @@ config SYS_CONFIG_NAME
 	default "k2hk_evm"
 
 endif
+
+if TARGET_K2L_EVM
+
+config SYS_BOARD
+	string
+	default "ks2_evm"
+
+config SYS_VENDOR
+	string
+	default "ti"
+
+config SYS_CONFIG_NAME
+	string
+	default "k2l_evm"
+
+endif
diff --git a/board/ti/ks2_evm/MAINTAINERS b/board/ti/ks2_evm/MAINTAINERS
index 595a80a8bc6..87c36c9d14a 100644
--- a/board/ti/ks2_evm/MAINTAINERS
+++ b/board/ti/ks2_evm/MAINTAINERS
@@ -6,3 +6,5 @@ F:	include/configs/k2hk_evm.h
 F:	configs/k2hk_evm_defconfig
 F:	include/configs/k2e_evm.h
 F:	configs/k2e_evm_defconfig
+F:	include/configs/k2l_evm.h
+F:	configs/k2l_evm_defconfig
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
index 00f1164833c..071dbee180a 100644
--- a/board/ti/ks2_evm/Makefile
+++ b/board/ti/ks2_evm/Makefile
@@ -11,3 +11,5 @@ obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
 obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
 obj-$(CONFIG_K2E_EVM) += board_k2e.o
 obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
+obj-$(CONFIG_K2L_EVM) += board_k2l.o
+obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index dfe7be60e71..40294934525 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -9,11 +9,13 @@
 
 #include "board.h"
 #include <common.h>
+#include <spl.h>
 #include <exports.h>
 #include <fdt_support.h>
 #include <asm/arch/ddr3.h>
-#include <asm/arch/emac_defs.h>
+#include <asm/arch/psc_defs.h>
 #include <asm/ti-common/ti-aemif.h>
+#include <asm/ti-common/keystone_net.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -38,6 +40,7 @@ int dram_init(void)
 	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 				    CONFIG_MAX_RAM_BANK_SIZE);
 	aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+	ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE);
 	return 0;
 }
 
@@ -68,6 +71,15 @@ int board_eth_init(bd_t *bis)
 	int port_num;
 	char link_type_name[32];
 
+	/* By default, select PA PLL clock as PA clock source */
+	if (psc_enable_module(KS2_LPSC_PA))
+		return -1;
+	if (psc_enable_module(KS2_LPSC_CPGMAC))
+		return -1;
+	if (psc_enable_module(KS2_LPSC_CRYPTO))
+		return -1;
+	pass_pll_pa_clk_enable();
+
 	port_num = get_num_eth_ports();
 
 	for (j = 0; j < port_num; j++) {
@@ -83,6 +95,24 @@ int board_eth_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+	spl_init_keystone_plls();
+	preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+#if defined(CONFIG_SPL_SPI_LOAD)
+	return BOOT_DEVICE_SPI;
+#else
+	puts("Unknown boot device\n");
+	hang();
+#endif
+}
+#endif
+
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
@@ -225,5 +255,7 @@ void ft_board_setup_ex(void *blob, bd_t *bd)
 			reserve_start += 2;
 		}
 	}
+
+	ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
 }
 #endif
diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h
index d91ef736129..2bbd79245ba 100644
--- a/board/ti/ks2_evm/board.h
+++ b/board/ti/ks2_evm/board.h
@@ -10,10 +10,11 @@
 #ifndef _KS2_BOARD
 #define _KS2_BOARD
 
-#include <asm/arch/emac_defs.h>
+#include <asm/ti-common/keystone_net.h>
 
 extern struct eth_priv_t eth_priv_cfg[];
 
 int get_num_eth_ports(void);
+void spl_init_keystone_plls(void);
 
 #endif
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index 5472a43c43f..43dfc48a53d 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -10,6 +10,7 @@
 #include <common.h>
 #include <asm/arch/ddr3.h>
 #include <asm/arch/hardware.h>
+#include <asm/ti-common/keystone_net.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -35,10 +36,75 @@ static struct pll_init_data core_pll_config[] = {
 	CORE_PLL_1500,
 };
 
-
 static struct pll_init_data pa_pll_config =
 	PASS_PLL_1000;
 
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+	{
+		.int_name        = "K2E_EMAC0",
+		.rx_flow         = 0,
+		.phy_addr        = 0,
+		.slave_port      = 1,
+		.sgmii_link_type = SGMII_LINK_MAC_PHY,
+	},
+	{
+		.int_name        = "K2E_EMAC1",
+		.rx_flow         = 8,
+		.phy_addr        = 1,
+		.slave_port      = 2,
+		.sgmii_link_type = SGMII_LINK_MAC_PHY,
+	},
+	{
+		.int_name        = "K2E_EMAC2",
+		.rx_flow         = 16,
+		.phy_addr        = 2,
+		.slave_port      = 3,
+		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+	},
+	{
+		.int_name        = "K2E_EMAC3",
+		.rx_flow         = 24,
+		.phy_addr        = 3,
+		.slave_port      = 4,
+		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+	},
+	{
+		.int_name        = "K2E_EMAC4",
+		.rx_flow         = 32,
+		.phy_addr        = 4,
+		.slave_port      = 5,
+		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+	},
+	{
+		.int_name        = "K2E_EMAC5",
+		.rx_flow         = 40,
+		.phy_addr        = 5,
+		.slave_port      = 6,
+		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+	},
+	{
+		.int_name        = "K2E_EMAC6",
+		.rx_flow         = 48,
+		.phy_addr        = 6,
+		.slave_port      = 7,
+		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+	},
+	{
+		.int_name        = "K2E_EMAC7",
+		.rx_flow         = 56,
+		.phy_addr        = 7,
+		.slave_port      = 8,
+		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+	},
+};
+
+int get_num_eth_ports(void)
+{
+	return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
+}
+#endif
+
 #if defined(CONFIG_BOARD_EARLY_INIT_F)
 int board_early_init_f(void)
 {
@@ -52,3 +118,14 @@ int board_early_init_f(void)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_SPL_BUILD
+static struct pll_init_data spl_pll_config[] = {
+	CORE_PLL_800,
+};
+
+void spl_init_keystone_plls(void)
+{
+	init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+#endif
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
index 6fb3d2123df..ed181f44b89 100644
--- a/board/ti/ks2_evm/board_k2hk.c
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -10,7 +10,7 @@
 #include <common.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/emac_defs.h>
+#include <asm/ti-common/keystone_net.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -100,3 +100,15 @@ int board_early_init_f(void)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_SPL_BUILD
+static struct pll_init_data spl_pll_config[] = {
+	CORE_PLL_799,
+	TETRIS_PLL_500,
+};
+
+void spl_init_keystone_plls(void)
+{
+	init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+#endif
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
new file mode 100644
index 00000000000..559d20ca88e
--- /dev/null
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -0,0 +1,72 @@
+/*
+ * K2L EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+#include <asm/ti-common/ti-aemif.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+	[sys_clk]	= 122880000,
+	[alt_core_clk]	= 100000000,
+	[pa_clk]	= 122880000,
+	[tetris_clk]	= 122880000,
+	[ddr3_clk]	= 100000000,
+	[pcie_clk]	= 100000000,
+	[sgmii_clk]	= 156250000,
+	[usb_clk]	= 100000000,
+};
+
+static struct pll_init_data core_pll_config[] = {
+	CORE_PLL_799,
+	CORE_PLL_1000,
+	CORE_PLL_1198,
+};
+
+static struct pll_init_data tetris_pll_config[] = {
+	TETRIS_PLL_799,
+	TETRIS_PLL_1000,
+	TETRIS_PLL_1198,
+	TETRIS_PLL_1352,
+	TETRIS_PLL_1401,
+};
+
+static struct pll_init_data pa_pll_config =
+	PASS_PLL_983;
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	int speed;
+
+	speed = get_max_dev_speed();
+	init_pll(&core_pll_config[speed]);
+
+	init_pll(&pa_pll_config);
+
+	speed = get_max_arm_speed();
+	init_pll(&tetris_pll_config[speed]);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+static struct pll_init_data spl_pll_config[] = {
+	CORE_PLL_799,
+	TETRIS_PLL_491,
+};
+
+void spl_init_keystone_plls(void)
+{
+	init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+#endif
diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c
index f7da9f2bcba..ab44676793c 100644
--- a/board/ti/ks2_evm/ddr3_cfg.c
+++ b/board/ti/ks2_evm/ddr3_cfg.c
@@ -133,6 +133,42 @@ struct ddr3_emif_config ddr3_1600_4g = {
 };
 #endif
 
+struct ddr3_phy_config ddr3phy_1600_2g = {
+	.pllcr          = 0x0001C000ul,
+	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
+	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
+	.ptr0           = 0x42C21590ul,
+	.ptr1           = 0xD05612C0ul,
+	.ptr2           = 0, /* not set in gel */
+	.ptr3           = 0x0D861A80ul,
+	.ptr4           = 0x0C827100ul,
+	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+	.dcr_val        = ((1 << 10)),
+	.dtpr0          = 0x9D5CBB66ul,
+	.dtpr1          = 0x12868300ul,
+	.dtpr2          = 0x5002D200ul,
+	.mr0            = 0x00001C70ul,
+	.mr1            = 0x00000006ul,
+	.mr2            = 0x00000018ul,
+	.dtcr           = 0x710035C7ul,
+	.pgcr2          = 0x00F07A12ul,
+	.zq0cr1         = 0x0001005Dul,
+	.zq1cr1         = 0x0001005Bul,
+	.zq2cr1         = 0x0001005Bul,
+	.pir_v1         = 0x00000033ul,
+	.pir_v2         = 0x0000FF81ul,
+};
+
+struct ddr3_emif_config ddr3_1600_2g = {
+	.sdcfg          = 0x6200CE62ul,
+	.sdtim1         = 0x166C9855ul,
+	.sdtim2         = 0x00001D4Aul,
+	.sdtim3         = 0x435DFF53ul,
+	.sdtim4         = 0x543F0CFFul,
+	.zqcfg          = 0x70073200ul,
+	.sdrfc          = 0x00001869ul,
+};
+
 int ddr3_get_dimm_params(char *dimm_name)
 {
 	int ret;
diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h
index 15fcf52ef19..5bd786cff8e 100644
--- a/board/ti/ks2_evm/ddr3_cfg.h
+++ b/board/ti/ks2_evm/ddr3_cfg.h
@@ -19,6 +19,9 @@ extern struct ddr3_emif_config ddr3_1333_2g;
 extern struct ddr3_phy_config ddr3phy_1600_4g;
 extern struct ddr3_emif_config ddr3_1600_4g;
 
+extern struct ddr3_phy_config ddr3phy_1600_2g;
+extern struct ddr3_emif_config ddr3_1600_2g;
+
 int ddr3_get_dimm_params(char *dimm_name);
 
 #endif /* __DDR3_CFG_H */
diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c
index 6070a997702..a1c3d05f8e5 100644
--- a/board/ti/ks2_evm/ddr3_k2hk.c
+++ b/board/ti/ks2_evm/ddr3_k2hk.c
@@ -12,6 +12,8 @@
 #include <asm/arch/ddr3.h>
 #include <asm/arch/hardware.h>
 
+static int ddr3_size;
+
 struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
 struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
 
@@ -44,12 +46,14 @@ void ddr3_init(void)
 			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
 					  &ddr3_1600_8g);
 			printf("DRAM:  Capacity 8 GiB (includes reported below)\n");
+			ddr3_size = 8;
 		} else {
 			ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
 			ddr3_1600_8g.sdcfg |= 0x1000;
 			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
 					  &ddr3_1600_8g);
 			printf("DRAM:  Capacity 4 GiB (includes reported below)\n");
+			ddr3_size = 4;
 		}
 	} else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
 		init_pll(&ddr3a_333);
@@ -70,11 +74,15 @@ void ddr3_init(void)
 			}
 			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
 					  &ddr3_1333_2g);
+			ddr3_size = 2;
+			printf("DRAM:  2 GiB");
 		} else {
 			ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
 			ddr3_1333_2g.sdcfg |= 0x1000;
 			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
 					  &ddr3_1333_2g);
+			ddr3_size = 1;
+			printf("DRAM:  1 GiB");
 		}
 	} else {
 		printf("Unknown SO-DIMM. Cannot configure DDR3\n");
@@ -86,3 +94,11 @@ void ddr3_init(void)
 	if (cpu_revision() <= 1)
 		ddr3_err_reset_workaround();
 }
+
+/**
+ * ddr3_get_size - return ddr3 size in GiB
+ */
+int ddr3_get_size(void)
+{
+	return ddr3_size;
+}
diff --git a/board/ti/ks2_evm/ddr3_k2l.c b/board/ti/ks2_evm/ddr3_k2l.c
new file mode 100644
index 00000000000..15a14f2aafe
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_k2l.c
@@ -0,0 +1,38 @@
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+
+static int ddr3_size;
+static struct pll_init_data ddr3_400 = DDR3_PLL_400;
+
+void ddr3_init(void)
+{
+	init_pll(&ddr3_400);
+
+	/* No SO-DIMM, 2GB discreet DDR */
+	printf("DRAM: 2 GiB\n");
+	ddr3_size = 2;
+
+	/* Reset DDR3 PHY after PLL enabled */
+	ddr3_reset_ddrphy();
+
+	ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g);
+	ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g);
+}
+
+/**
+ * ddr3_get_size - return ddr3 size in GiB
+ */
+int ddr3_get_size(void)
+{
+	return ddr3_size;
+}
diff --git a/board/ti/sdp3430/sdp.h b/board/ti/sdp3430/sdp.h
index 2acb302591e..0e631897e38 100644
--- a/board/ti/sdp3430/sdp.h
+++ b/board/ti/sdp3430/sdp.h
@@ -265,7 +265,7 @@
 	MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\
 	MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\
 	MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\
-	MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\
+	MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\
 	MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
 	MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
 	MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
diff --git a/board/ti/ti814x/Kconfig b/board/ti/ti814x/Kconfig
index 9bd3d73427b..2960099a8e5 100644
--- a/board/ti/ti814x/Kconfig
+++ b/board/ti/ti814x/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_TI814X_EVM
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "ti814x"
 
diff --git a/board/ti/ti816x/Kconfig b/board/ti/ti816x/Kconfig
index c0bdb9eac3c..95973b47f1e 100644
--- a/board/ti/ti816x/Kconfig
+++ b/board/ti/ti816x/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_TI816X_EVM
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "ti816x"
 
diff --git a/board/ti/tnetv107xevm/Kconfig b/board/ti/tnetv107xevm/Kconfig
index aa80d0f41a3..637f20e847e 100644
--- a/board/ti/tnetv107xevm/Kconfig
+++ b/board/ti/tnetv107xevm/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_TNETV107X_EVM
 
-config SYS_CPU
-	default "arm1176"
-
 config SYS_BOARD
 	default "tnetv107xevm"
 
diff --git a/board/timll/devkit3250/Kconfig b/board/timll/devkit3250/Kconfig
index 087356d4bac..e3bd4569d6e 100644
--- a/board/timll/devkit3250/Kconfig
+++ b/board/timll/devkit3250/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_DEVKIT3250
 
-config SYS_CPU
-	default "arm926ejs"
-
 config SYS_BOARD
 	default "devkit3250"
 
diff --git a/board/toradex/apalis_t30/Kconfig b/board/toradex/apalis_t30/Kconfig
new file mode 100644
index 00000000000..f1dcda59275
--- /dev/null
+++ b/board/toradex/apalis_t30/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_APALIS_T30
+
+config SYS_BOARD
+	default "apalis_t30"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "apalis_t30"
+
+endif
diff --git a/board/toradex/apalis_t30/MAINTAINERS b/board/toradex/apalis_t30/MAINTAINERS
new file mode 100644
index 00000000000..01bc73e46d5
--- /dev/null
+++ b/board/toradex/apalis_t30/MAINTAINERS
@@ -0,0 +1,7 @@
+Apalis T30
+M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
+S:	Maintained
+F:	board/toradex/apalis_t30/
+F:	include/configs/apalis_t30.h
+F:	configs/apalis_t30_defconfig
+F:	arch/arm/dts/tegra30-apalis.dtb
diff --git a/board/toradex/apalis_t30/Makefile b/board/toradex/apalis_t30/Makefile
new file mode 100644
index 00000000000..a968e6b79e4
--- /dev/null
+++ b/board/toradex/apalis_t30/Makefile
@@ -0,0 +1,6 @@
+# Copyright (c) 2014 Marcel Ziswiler
+# SPDX-License-Identifier:      GPL-2.0+
+
+include $(srctree)/board/nvidia/common/common.mk
+
+obj-y	+= apalis_t30.o
diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c
new file mode 100644
index 00000000000..b9d694a2688
--- /dev/null
+++ b/board/toradex/apalis_t30/apalis_t30.c
@@ -0,0 +1,92 @@
+/*
+ *  (C) Copyright 2014
+ *  Marcel Ziswiler <marcel@ziswiler.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pinmux.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <netdev.h>
+
+#include "pinmux-config-apalis_t30.h"
+
+#define PMU_I2C_ADDRESS		0x2D
+#define MAX_I2C_RETRY		3
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_config_pingrp_table(tegra3_pinmux_common,
+				   ARRAY_SIZE(tegra3_pinmux_common));
+
+	pinmux_config_pingrp_table(unused_pins_lowpower,
+				   ARRAY_SIZE(unused_pins_lowpower));
+
+	/* Initialize any non-default pad configs (APB_MISC_GP regs) */
+	pinmux_config_drvgrp_table(apalis_t30_padctrl,
+				   ARRAY_SIZE(apalis_t30_padctrl));
+}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+	unsigned int old_bus;
+	u8 addr, data[1];
+	int err;
+
+	old_bus = i2c_get_bus_num();
+
+	err = i2c_set_bus_num(0);
+	if (err) {
+		debug("failed to set I2C bus\n");
+		return err;
+	}
+
+	/* TPS659110: VDD2_OP_REG = 1.05V */
+	data[0] = 0x27;
+	addr = 0x25;
+
+	err = i2c_write(PMU_I2C_ADDRESS, addr, 1, data, 1);
+	if (err) {
+		debug("failed to set VDD supply\n");
+		return err;
+	}
+
+	/* TPS659110: VDD2_REG 7.5 mV/us, ACTIVE */
+	data[0] = 0x0D;
+	addr = 0x24;
+
+	err = i2c_write(PMU_I2C_ADDRESS, addr, 1, data, 1);
+	if (err) {
+		debug("failed to enable VDD supply\n");
+		return err;
+	}
+
+	/* TPS659110: LDO6_REG = 1.1V, ACTIVE */
+	data[0] = 0x0D;
+	addr = 0x35;
+
+	err = i2c_write(PMU_I2C_ADDRESS, addr, 1, data, 1);
+	if (err) {
+		debug("failed to set AVDD supply\n");
+		return err;
+	}
+
+	i2c_set_bus_num(old_bus);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+#endif /* CONFIG_PCI_TEGRA */
diff --git a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
new file mode 100644
index 00000000000..c988d395c19
--- /dev/null
+++ b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2014, Marcel Ziswiler
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _PINMUX_CONFIG_APALIS_T30_H_
+#define _PINMUX_CONFIG_APALIS_T30_H_
+
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io)		\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od)	\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset	\
+	}
+
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{							\
+		.drvgrp		= PMUX_DRVGRP_##_drvgrp,	\
+		.slwf		= _slwf,			\
+		.slwr		= _slwr,			\
+		.drvup		= _drvup,			\
+		.drvdn		= _drvdn,			\
+		.lpmd		= PMUX_LPMD_##_lpmd,		\
+		.schmt		= PMUX_SCHMT_##_schmt,		\
+		.hsm		= PMUX_HSM_##_hsm,		\
+	}
+
+static struct pmux_pingrp_config tegra3_pinmux_common[] = {
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, NORMAL, NORMAL, INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, NORMAL, NORMAL, INPUT),
+
+	/* SDMMC4 pinmux (eMMC) */
+	LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C3 pinmux */
+	I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE),
+
+	/* I2C4 pinmux */
+	I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* Power I2C pinmux */
+	I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
+	/* UARTA RX, make sure we don't get input form a floating Pin */
+	DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(LCD_SDIN_PZ2, SPI5, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDOUT_PN5, SPI5, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(LCD_CS0_N_PN4, SPI5, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(LCD_SCK_PZ4, SPI5, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
+	LV_PINMUX(VI_D0_PT4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D1_PD5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D2_PL0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D3_PL1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D5_PL3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D7_PL5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D10_PT2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D11_PT3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_HSYNC_PD7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N_PC0, PWM0, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PU0, RSVD1, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(PU1, RSVD1, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(PU2, RSVD1, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(PU3, PWM0, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PU6, PWM3, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_AD10_PH2, NAND, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_A17_PB0, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_A18_PB1, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_A19_PK7, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */
+
+	DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, OUTPUT),
+
+	DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
+
+	/* multiplexed VI_D2, VI_D3, VI_D4, VI_D5, VI_D6, VI_D7, VI_D8 and VI_D9
+	 */
+	DEFAULT_PINMUX(KB_ROW0_PR0, RSVD2, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW1_PR1, RSVD2, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW2_PR2, RSVD2, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW3_PR3, RSVD2, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW4_PR4, RSVD3, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, TRISTATE, INPUT),
+
+	/* GPIOs */
+	DEFAULT_PINMUX(KB_ROW10_PS2, SDMMC2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW11_PS3, SDMMC2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW12_PS4, SDMMC2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW13_PS5, SDMMC2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW14_PS6, SDMMC2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW15_PS7, SDMMC2, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL2_PQ2, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL3_PQ3, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL4_PQ4, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL6_PQ6, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(PV0, RSVD1, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT),
+	/* multiplexed KB_COL0 */
+	DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, TRISTATE, OUTPUT),
+
+	DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_AD12_PH4, NAND, DOWN, TRISTATE, OUTPUT), /* NC */
+	DEFAULT_PINMUX(GMI_AD14_PH6, NAND, DOWN, TRISTATE, OUTPUT), /* NC */
+
+	DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, NORMAL, INPUT),
+};
+
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
+	DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CLK_PK1, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD0_PG0, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD1_PG1, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD2_PG2, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD3_PG3, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD4_PG4, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD5_PG5, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD6_PG6, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD7_PG7, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD11_PH3, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD13_PH5, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, DOWN, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_DQS_PI2, NAND, DOWN, TRISTATE, OUTPUT),
+};
+
+static struct pmux_drvgrp_config apalis_t30_padctrl[] = {
+	/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+	DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
+		SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif	/* _PINMUX_CONFIG_APALIS_T30_H_ */
diff --git a/board/toradex/colibri_pxa270/Kconfig b/board/toradex/colibri_pxa270/Kconfig
index e4b1a5e5081..949407a0423 100644
--- a/board/toradex/colibri_pxa270/Kconfig
+++ b/board/toradex/colibri_pxa270/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_COLIBRI_PXA270
 
-config SYS_CPU
-	default "pxa"
-
 config SYS_BOARD
 	default "colibri_pxa270"
 
diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c
index ed043f49b37..f4bc7d8728e 100644
--- a/board/toradex/colibri_t30/colibri_t30.c
+++ b/board/toradex/colibri_t30/colibri_t30.c
@@ -35,7 +35,7 @@ void pinmux_init(void)
 void pin_mux_usb(void)
 {
 	/* Reset ASIX using LAN_RESET */
-	gpio_request(GPIO_PDD0, NULL);
+	gpio_request(GPIO_PDD0, "LAN_RESET");
 	gpio_direction_output(GPIO_PDD0, 0);
 	udelay(5);
 	gpio_set_value(GPIO_PDD0, 1);
diff --git a/board/tqc/tqm8260/Kconfig b/board/tqc/tqm8260/Kconfig
deleted file mode 100644
index 90a96ebebe5..00000000000
--- a/board/tqc/tqm8260/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_TQM8260
-
-config SYS_BOARD
-	default "tqm8260"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM8260"
-
-endif
diff --git a/board/tqc/tqm8260/MAINTAINERS b/board/tqc/tqm8260/MAINTAINERS
deleted file mode 100644
index 266910fe054..00000000000
--- a/board/tqc/tqm8260/MAINTAINERS
+++ /dev/null
@@ -1,16 +0,0 @@
-TQM8260 BOARD
-M:	Wolfgang Denk <wd@denx.de>
-S:	Maintained
-F:	board/tqc/tqm8260/
-F:	include/configs/TQM8260.h
-F:	configs/TQM8255_AA_defconfig
-F:	configs/TQM8260_AA_defconfig
-F:	configs/TQM8260_AB_defconfig
-F:	configs/TQM8260_AC_defconfig
-F:	configs/TQM8260_AD_defconfig
-F:	configs/TQM8260_AE_defconfig
-F:	configs/TQM8260_AF_defconfig
-F:	configs/TQM8260_AG_defconfig
-F:	configs/TQM8260_AH_defconfig
-F:	configs/TQM8260_AI_defconfig
-F:	configs/TQM8265_AA_defconfig
diff --git a/board/tqc/tqm8260/Makefile b/board/tqc/tqm8260/Makefile
deleted file mode 100644
index 6b8573d9abf..00000000000
--- a/board/tqc/tqm8260/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= tqm8260.o ../tqm8xx/load_sernum_ethaddr.o
diff --git a/board/tqc/tqm8260/README b/board/tqc/tqm8260/README
deleted file mode 100644
index 93b55068f57..00000000000
--- a/board/tqc/tqm8260/README
+++ /dev/null
@@ -1,415 +0,0 @@
-
-This file contains basic information on the port of U-Boot to TQM8260.
-All the changes fit in the common U-Boot infrastructure, providing a
-new TQM8260-specific entry in makefiles. To build U-Boot for TQM8260,
-type "make TQM8260_config", edit the "include/config_TQM8260.h" file
-if necessary, then type "make".
-
-
-Common file modifications:
---------------------------
-
-The following common files have been modified by this project:
-(starting from the ppcboot-0.9.3/ directory)
-
-MAKEALL			- TQM8260 entry added
-Makefile		- TQM8260_config entry added
-arch/powerpc/cpu/mpc8260/Makefile	- soft_i2c.o module added
-arch/powerpc/cpu/mpc8260/ether_scc.c	- TQM8260-specific definitions added, an obvious
-			  bug fixed (fcr -> scr)
-arch/powerpc/cpu/mpc8260/ether_fcc.c	- TQM8260-specific definitions added
-include/flash.h		- added definitions for the AM29LV640D Flash chip
-
-
-New files:
-----------
-
-The following new files have been added by this project:
-(starting from the ppcboot-0.9.3/ directory)
-
-board/tqm8260/		  - board-specific directory
-board/tqm8260/Makefile	  - board-specific makefile
-board/tqm8260/config.mk	  - config file
-board/tqm8260/flash.c	  - flash driver (for AM29LV640D)
-board/tqm8260/ppcboot.lds - linker script
-board/tqm8260/tqm8260.c	  - ioport and memory initialization
-arch/powerpc/cpu/mpc8260/soft_i2c.c	  - software i2c EEPROM driver
-include/config_TQM8260.h  - main configuration file
-
-
-New configuration options:
---------------------------
-
-CONFIG_TQM8260
-
-	Main board-specific option (should be defined for TQM8260).
-
-CONFIG_82xx_CONS_SMC1
-
-	If defined, SMC1 will be used as the console
-
-CONFIG_82xx_CONS_SMC2
-
-	If defined, SMC2 will be used as the console
-
-CONFIG_SYS_INIT_LOCAL_SDRAM
-
-	If defined, the SDRAM on the local bus will be initialized and
-	mapped at BR2.
-
-
-Acceptance criteria tests:
---------------------------
-
-The following tests have been conducted to validate the port of U-Boot
-to TQM8260:
-
-1. Operation on serial console:
-
-With the CONFIG_82xx_CONS_SMC1 option defined in the main configuration file,
-the U-Boot output appeared on the serial terminal connected to COM1 as
-follows:
-
-------------------------------------------------------------------------------
-=> help
-go      - start application at address 'addr'
-run     - run commands in an environment variable
-bootm   - boot application image from memory
-bootp   - boot image via network using BootP/TFTP protocol
-tftpboot- boot image via network using TFTP protocol
-	       and env variables ipaddr and serverip
-rarpboot- boot image via network using RARP/TFTP protocol
-bootd   - boot default, i.e., run 'bootcmd'
-loads   - load S-Record file over serial line
-loadb   - load binary file over serial line (kermit mode)
-md      - memory display
-mm      - memory modify (auto-incrementing)
-nm      - memory modify (constant address)
-mw      - memory write (fill)
-cp      - memory copy
-cmp     - memory compare
-crc32   - checksum calculation
-base    - print or set address offset
-printenv- print environment variables
-setenv  - set environment variables
-saveenv - save environment variables to persistent storage
-protect - enable or disable FLASH write protection
-erase   - erase FLASH memory
-flinfo  - print FLASH memory information
-bdinfo  - print Board Info structure
-iminfo  - print header information for application image
-coninfo - print console devices and informations
-eeprom  - EEPROM sub-system
-loop    - infinite loop on address range
-mtest   - simple RAM test
-icache  - enable or disable instruction cache
-dcache  - enable or disable data cache
-reset   - Perform RESET of the CPU
-echo    - echo args to console
-version - print monitor version
-help    - print online help
-?       - alias for 'help'
-=>
-------------------------------------------------------------------------------
-
-
-2. Flash driver operation
-
-The following sequence was performed to test the "flinfo" command:
-
-------------------------------------------------------------------------------
-=> flinfo
-
-Bank # 1: AMD 29LV640D (64 M, uniform sector)
-  Size: 32 MB in 128 Sectors
-  Sector Start Addresses:
-    40000000      40040000 (RO) 40080000      400C0000      40100000
-    40140000      40180000      401C0000      40200000      40240000
-    40280000      402C0000      40300000      40340000      40380000
-    403C0000      40400000      40440000      40480000      404C0000
-    40500000      40540000      40580000      405C0000      40600000
-    40640000      40680000      406C0000      40700000      40740000
-    40780000      407C0000      40800000      40840000      40880000
-    408C0000      40900000      40940000      40980000      409C0000
-    40A00000      40A40000      40A80000      40AC0000      40B00000
-    40B40000      40B80000      40BC0000      40C00000      40C40000
-    40C80000      40CC0000      40D00000      40D40000      40D80000
-    40DC0000      40E00000      40E40000      40E80000      40EC0000
-    40F00000      40F40000      40F80000      40FC0000      41000000
-    41040000      41080000      410C0000      41100000      41140000
-    41180000      411C0000      41200000      41240000      41280000
-    412C0000      41300000      41340000      41380000      413C0000
-    41400000      41440000      41480000      414C0000      41500000
-    41540000      41580000      415C0000      41600000      41640000
-    41680000      416C0000      41700000      41740000      41780000
-    417C0000      41800000      41840000      41880000      418C0000
-    41900000      41940000      41980000      419C0000      41A00000
-    41A40000      41A80000      41AC0000      41B00000      41B40000
-    41B80000      41BC0000      41C00000      41C40000      41C80000
-    41CC0000      41D00000      41D40000      41D80000      41DC0000
-    41E00000      41E40000      41E80000      41EC0000      41F00000
-    41F40000      41F80000      41FC0000
-=>
-------------------------------------------------------------------------------
-
-
-The following sequence was performed to test the erase command:
-
-------------------------------------------------------------------------------
-=> cp 0 40080000 10
-Copy to Flash... done
-=> erase 40080000 400bffff
-Erase Flash from 0x40080000 to 0x400bffff
-.. done
-Erased 1 sectors
-=> md 40080000
-40080000: ffffffff ffffffff ffffffff ffffffff    ................
-40080010: ffffffff ffffffff ffffffff ffffffff    ................
-40080020: ffffffff ffffffff ffffffff ffffffff    ................
-40080030: ffffffff ffffffff ffffffff ffffffff    ................
-40080040: ffffffff ffffffff ffffffff ffffffff    ................
-40080050: ffffffff ffffffff ffffffff ffffffff    ................
-40080060: ffffffff ffffffff ffffffff ffffffff    ................
-40080070: ffffffff ffffffff ffffffff ffffffff    ................
-40080080: ffffffff ffffffff ffffffff ffffffff    ................
-40080090: ffffffff ffffffff ffffffff ffffffff    ................
-400800a0: ffffffff ffffffff ffffffff ffffffff    ................
-400800b0: ffffffff ffffffff ffffffff ffffffff    ................
-400800c0: ffffffff ffffffff ffffffff ffffffff    ................
-400800d0: ffffffff ffffffff ffffffff ffffffff    ................
-400800e0: ffffffff ffffffff ffffffff ffffffff    ................
-400800f0: ffffffff ffffffff ffffffff ffffffff    ................
-=> cp 0 40080000 10
-Copy to Flash... done
-=> erase 1:2
-Erase Flash Sectors 2-2 in Bank # 1
-.. done
-=> md 40080000
-40080000: ffffffff ffffffff ffffffff ffffffff    ................
-40080010: ffffffff ffffffff ffffffff ffffffff    ................
-40080020: ffffffff ffffffff ffffffff ffffffff    ................
-40080030: ffffffff ffffffff ffffffff ffffffff    ................
-40080040: ffffffff ffffffff ffffffff ffffffff    ................
-40080050: ffffffff ffffffff ffffffff ffffffff    ................
-40080060: ffffffff ffffffff ffffffff ffffffff    ................
-40080070: ffffffff ffffffff ffffffff ffffffff    ................
-40080080: ffffffff ffffffff ffffffff ffffffff    ................
-40080090: ffffffff ffffffff ffffffff ffffffff    ................
-400800a0: ffffffff ffffffff ffffffff ffffffff    ................
-400800b0: ffffffff ffffffff ffffffff ffffffff    ................
-400800c0: ffffffff ffffffff ffffffff ffffffff    ................
-400800d0: ffffffff ffffffff ffffffff ffffffff    ................
-400800e0: ffffffff ffffffff ffffffff ffffffff    ................
-400800f0: ffffffff ffffffff ffffffff ffffffff    ................
-=> cp 0 40080000 10
-Copy to Flash... done
-=> cp 0 400c0000 10
-Copy to Flash... done
-=> erase 1:2-3
-Erase Flash Sectors 2-3 in Bank # 1
-... done
-=> md 40080000
-40080000: ffffffff ffffffff ffffffff ffffffff    ................
-40080010: ffffffff ffffffff ffffffff ffffffff    ................
-40080020: ffffffff ffffffff ffffffff ffffffff    ................
-40080030: ffffffff ffffffff ffffffff ffffffff    ................
-40080040: ffffffff ffffffff ffffffff ffffffff    ................
-40080050: ffffffff ffffffff ffffffff ffffffff    ................
-40080060: ffffffff ffffffff ffffffff ffffffff    ................
-40080070: ffffffff ffffffff ffffffff ffffffff    ................
-40080080: ffffffff ffffffff ffffffff ffffffff    ................
-40080090: ffffffff ffffffff ffffffff ffffffff    ................
-400800a0: ffffffff ffffffff ffffffff ffffffff    ................
-400800b0: ffffffff ffffffff ffffffff ffffffff    ................
-400800c0: ffffffff ffffffff ffffffff ffffffff    ................
-400800d0: ffffffff ffffffff ffffffff ffffffff    ................
-400800e0: ffffffff ffffffff ffffffff ffffffff    ................
-400800f0: ffffffff ffffffff ffffffff ffffffff    ................
-=> md 400c0000
-400c0000: ffffffff ffffffff ffffffff ffffffff    ................
-400c0010: ffffffff ffffffff ffffffff ffffffff    ................
-400c0020: ffffffff ffffffff ffffffff ffffffff    ................
-400c0030: ffffffff ffffffff ffffffff ffffffff    ................
-400c0040: ffffffff ffffffff ffffffff ffffffff    ................
-400c0050: ffffffff ffffffff ffffffff ffffffff    ................
-400c0060: ffffffff ffffffff ffffffff ffffffff    ................
-400c0070: ffffffff ffffffff ffffffff ffffffff    ................
-400c0080: ffffffff ffffffff ffffffff ffffffff    ................
-400c0090: ffffffff ffffffff ffffffff ffffffff    ................
-400c00a0: ffffffff ffffffff ffffffff ffffffff    ................
-400c00b0: ffffffff ffffffff ffffffff ffffffff    ................
-400c00c0: ffffffff ffffffff ffffffff ffffffff    ................
-400c00d0: ffffffff ffffffff ffffffff ffffffff    ................
-400c00e0: ffffffff ffffffff ffffffff ffffffff    ................
-400c00f0: ffffffff ffffffff ffffffff ffffffff    ................
-=>
-------------------------------------------------------------------------------
-
-
-The following sequence was performed to test the Flash programming commands:
-
-------------------------------------------------------------------------------
-=> erase 40080000 400bffff
-Erase Flash from 0x40080000 to 0x400bffff
-.. done
-Erased 1 sectors
-=> cp 0 40080000 10
-Copy to Flash... done
-=> md 0
-00000000: 00000000 00000104 61100200 01000000    ........a.......
-00000010: 00000000 00000000 81140000 82000100    ................
-00000020: 01080000 00004000 22800000 00000600    ......@.".......
-00000030: 00200800 00000000 10000100 00008000    . ..............
-00000040: 00812000 00000200 00020000 80000000    .. .............
-00000050: 00028001 00001000 00040400 00000200    ................
-00000060: 20480000 00000000 20090000 00142000     H...... ..... .
-00000070: 00000000 00004000 24210000 10000000    ......@.$!......
-00000080: 02440002 10000000 00200008 00000000    .D....... ......
-00000090: 02440900 00000000 30a40000 00004400    .D......0.....D.
-000000a0: 04420800 00000000 00000040 00020000    .B.........@....
-000000b0: 05020000 00100000 00060000 00000000    ................
-000000c0: 00400000 00000000 00080000 00040000    .@..............
-000000d0: 10400000 00800004 00000000 00000200    .@..............
-000000e0: 80890000 00010004 00080000 00000020    ...............
-000000f0: 08000000 10000000 00010000 00000000    ................
-=> md 40080000
-40080000: 00000000 00000104 61100200 01000000    ........a.......
-40080010: 00000000 00000000 81140000 82000100    ................
-40080020: 01080000 00004000 22800000 00000600    ......@.".......
-40080030: 00200800 00000000 10000100 00008000    . ..............
-40080040: ffffffff ffffffff ffffffff ffffffff    ................
-40080050: ffffffff ffffffff ffffffff ffffffff    ................
-40080060: ffffffff ffffffff ffffffff ffffffff    ................
-40080070: ffffffff ffffffff ffffffff ffffffff    ................
-40080080: ffffffff ffffffff ffffffff ffffffff    ................
-40080090: ffffffff ffffffff ffffffff ffffffff    ................
-400800a0: ffffffff ffffffff ffffffff ffffffff    ................
-400800b0: ffffffff ffffffff ffffffff ffffffff    ................
-400800c0: ffffffff ffffffff ffffffff ffffffff    ................
-400800d0: ffffffff ffffffff ffffffff ffffffff    ................
-400800e0: ffffffff ffffffff ffffffff ffffffff    ................
-400800f0: ffffffff ffffffff ffffffff ffffffff    ................
-=>
-------------------------------------------------------------------------------
-
-
-The following sequence was performed to test storage of the environment
-variables in Flash:
-
-------------------------------------------------------------------------------
-=> setenv foo bar
-=> saveenv
-Un-Protected 1 sectors
-Erasing Flash...
-.. done
-Erased 1 sectors
-Saving Environment to Flash...
-Protected 1 sectors
-=> reset
-...
-=> printenv
-bootdelay=CONFIG_BOOTDELAY
-baudrate=9600
-ipaddr=192.168.4.7
-serverip=192.168.4.1
-ethaddr=66:55:44:33:22:11
-foo=bar
-stdin=serial
-stdout=serial
-stderr=serial
-
-Environment size: 170/262140 bytes
-=>
-------------------------------------------------------------------------------
-
-
-The following sequence was performed to test image download and run over
-Ethernet interface (both interfaces were tested):
-
-------------------------------------------------------------------------------
-=> tftpboot 40000 hello_world.bin
-ARP broadcast 1
-TFTP from server 192.168.2.2; our IP address is 192.168.2.7
-Filename 'hello_world.bin'.
-Load address: 0x40000
-Loading: #############
-done
-Bytes transferred = 65912 (10178 hex)
-=> go 40004
-## Starting application at 0x00040004 ...
-Hello World
-argc = 1
-argv[0] = "40004"
-argv[1] = "<NULL>"
-Hit any key to exit ...
-
-## Application terminated, rc = 0x0
-=>
-------------------------------------------------------------------------------
-
-
-The following sequence was performed to test eeprom read/write commands:
-
-------------------------------------------------------------------------------
-=> md 40000
-00040000: 00018148 9421ffe0 7c0802a6 bf61000c    ...H.!..|....a..
-00040010: 90010024 48000005 7fc802a6 801effe8    ...$H...........
-00040020: 7fc0f214 7c7f1b78 813f004c 7c9c2378    ....|..x.?.L|.#x
-00040030: 807e8000 7cbd2b78 80090010 3b600000    .~..|.+x....;`..
-00040040: 7c0803a6 4e800021 813f004c 7f84e378    |...N..!.?.L...x
-00040050: 807e8004 80090010 7c0803a6 4e800021    .~......|...N..!
-00040060: 7c1be000 4181003c 80bd0000 813f004c    |...A..<.....?.L
-00040070: 3bbd0004 2c050000 40820008 80be8008    ;...,...@.......
-00040080: 80090010 7f64db78 807e800c 3b7b0001    .....d.x.~..;{..
-00040090: 7c0803a6 4e800021 7c1be000 4081ffcc    |...N..!|...@...
-000400a0: 813f004c 807e8010 80090010 7c0803a6    .?.L.~......|...
-000400b0: 4e800021 813f004c 80090004 7c0803a6    N..!.?.L....|...
-000400c0: 4e800021 2c030000 4182ffec 813f004c    N..!,...A....?.L
-000400d0: 80090000 7c0803a6 4e800021 813f004c    ....|...N..!.?.L
-000400e0: 807e8014 80090010 7c0803a6 4e800021    .~......|...N..!
-000400f0: 38600000 80010024 7c0803a6 bb61000c    8`.....$|....a..
-=> eeprom write 40000 0 40
-
-EEPROM write: addr 00040000  off 0000  count 64 ... done
-=> mw 50000 0 1000
-=> eeprom read 50000 0 40
-
-EEPROM read: addr 00050000  off 0000  count 64 ... done
-=> md 50000
-00050000: 00018148 9421ffe0 7c0802a6 bf61000c    ...H.!..|....a..
-00050010: 90010024 48000005 7fc802a6 801effe8    ...$H...........
-00050020: 7fc0f214 7c7f1b78 813f004c 7c9c2378    ....|..x.?.L|.#x
-00050030: 807e8000 7cbd2b78 80090010 3b600000    .~..|.+x....;`..
-00050040: 00000000 00000000 00000000 00000000    ................
-00050050: 00000000 00000000 00000000 00000000    ................
-00050060: 00000000 00000000 00000000 00000000    ................
-00050070: 00000000 00000000 00000000 00000000    ................
-00050080: 00000000 00000000 00000000 00000000    ................
-00050090: 00000000 00000000 00000000 00000000    ................
-000500a0: 00000000 00000000 00000000 00000000    ................
-000500b0: 00000000 00000000 00000000 00000000    ................
-000500c0: 00000000 00000000 00000000 00000000    ................
-000500d0: 00000000 00000000 00000000 00000000    ................
-000500e0: 00000000 00000000 00000000 00000000    ................
-000500f0: 00000000 00000000 00000000 00000000    ................
-=>
-------------------------------------------------------------------------------
-
-
-Patch per Mon, 06 Aug 2001 17:57:27:
-
-- upgraded Flash support (added support for the following chips:
-  AM29LV800T/B, AM29LV160T/B, AM29DL322T/B, AM29DL323T/B)
-- BCR tweakage for the 8260 bus mode
-- SIUMCR tweakage enabling the MI interrupt (IRQ7)
-
-To simplify switching between the bus modes, a new configuration
-option (CONFIG_BUSMODE_60x) has been added to the "config_TQM8260.h"
-file. If it is defined, BCR will be configured for the 60x mode,
-otherwise - for the 8260 mode.
-
-Concerning the SIUMCR modification: it's hard to predict whether it
-will induce any problems on the other (60x mode) board. However, the
-problems (if they appear) should be easy to notice - if the board
-does not boot, it's most likely caused by the DPPC configuration in
-SIUMCR.
diff --git a/board/tqc/tqm8260/tqm8260.c b/board/tqc/tqm8260/tqm8260.c
deleted file mode 100644
index c361f188f79..00000000000
--- a/board/tqc/tqm8260/tqm8260.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A configuration */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PA31 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 *ATMTXEN */
-	/* PA30 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTCA   */
-	/* PA29 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTSOC  */
-	/* PA28 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 *ATMRXEN */
-	/* PA27 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRSOC */
-	/* PA26 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRCA */
-	/* PA25 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
-	/* PA24 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
-	/* PA23 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
-	/* PA22 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
-	/* PA21 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
-	/* PA20 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
-	/* PA19 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
-	/* PA18 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
-	/* PA17 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[7] */
-	/* PA16 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[6] */
-	/* PA15 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[5] */
-	/* PA14 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[4] */
-	/* PA13 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[3] */
-	/* PA12 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[2] */
-	/* PA11 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[1] */
-	/* PA10 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[0] */
-	/* PA9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
-	/* PA8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
-	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
-	/* PA6  */ {   0,   0,   0,   1,   0,   0   }, /* PA6 */
-	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
-	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
-	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
-	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
-	/* PA1  */ {   0,   0,   0,   1,   0,   0   }, /* PA1 */
-	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
-    },
-
-    /* Port B configuration */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
-	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
-	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
-	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
-	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
-	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
-	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
-	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
-	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
-	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
-	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
-	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
-	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
-	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
-	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
-	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
-	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
-	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
-	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
-	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
-	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
-	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
-	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
-	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
-	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
-	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
-	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    },
-
-    /* Port C */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
-	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
-	/* PC29 */ {   1,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
-	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
-	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* PC27 */
-	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
-	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
-	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
-	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
-	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
-	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
-	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
-	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
-	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
-	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
-	/* PC16 */ {   0,   0,   0,   1,   0,   0   }, /* PC16 */
-	/* PC15 */ {   0,   0,   0,   1,   0,   0   }, /* PC15 */
-	/* PC14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
-	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
-	/* PC12 */ {   0,   0,   0,   1,   0,   0   }, /* PC12 */
-	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* PC11 */
-	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* FCC2 MDC */
-	/* PC9  */ {   0,   0,   0,   1,   0,   0   }, /* FCC2 MDIO */
-	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
-	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
-	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
-	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
-	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
-	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
-	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
-	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
-	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
-    },
-
-    /* Port D */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
-	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
-	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
-	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* PD28 */
-	/* PD27 */ {   0,   0,   0,   1,   0,   0   }, /* PD27 */
-	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
-	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
-	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
-	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
-	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
-	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
-	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
-	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
-	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
-	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
-	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
-#if defined(CONFIG_SYS_I2C_SOFT)
-	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
-	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
-#else
-#if defined(CONFIG_HARD_I2C)
-	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
-#else /* normal I/O port pins */
-	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
-#endif
-#endif
-	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
-	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
-	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
-	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
-	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
-	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
-	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
-	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
-	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	puts ("Board: ");
-
-	if (i < 0 || strncmp(buf, "TQM82", 5)) {
-		puts ("### No HW ID - assuming TQM8260\n");
-		return (0);
-	}
-
-	puts (buf);
-	putc ('\n');
-
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
-						  ulong orx, volatile uchar * base)
-{
-	volatile uchar c = 0xff;
-	volatile uint *sdmr_ptr;
-	volatile uint *orx_ptr;
-	ulong maxsize, size;
-	int i;
-
-	/* We must be able to test a location outsize the maximum legal size
-	 * to find out THAT we are outside; but this address still has to be
-	 * mapped by the controller. That means, that the initial mapping has
-	 * to be (at least) twice as large as the maximum expected size.
-	 */
-	maxsize = (1 + (~orx | 0x7fff)) / 2;
-
-	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
-	 * we are configuring CS1 if base != 0
-	 */
-	sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
-	orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
-
-	*orx_ptr = orx;
-
-	/*
-	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
-	 *
-	 * "At system reset, initialization software must set up the
-	 *  programmable parameters in the memory controller banks registers
-	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
-	 *  system software should execute the following initialization sequence
-	 *  for each SDRAM device.
-	 *
-	 *  1. Issue a PRECHARGE-ALL-BANKS command
-	 *  2. Issue eight CBR REFRESH commands
-	 *  3. Issue a MODE-SET command to initialize the mode register
-	 *
-	 *  The initial commands are executed by setting P/LSDMR[OP] and
-	 *  accessing the SDRAM with a single-byte transaction."
-	 *
-	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
-	 */
-
-	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
-	*base = c;
-
-	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
-	for (i = 0; i < 8; i++)
-		*base = c;
-
-	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
-
-	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
-	*base = c;
-
-	size = get_ram_size((long *)base, maxsize);
-	*orx_ptr = orx | ~(size - 1);
-
-	return (size);
-}
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	long size8, size9;
-#endif
-	long psize, lsize;
-
-	psize = 16 * 1024 * 1024;
-	lsize = 0;
-
-	memctl->memc_psrt = CONFIG_SYS_PSRT;
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#if 0							/* Just for debugging */
-#define	prt_br_or(brX,orX) do {				\
-    ulong start =  memctl->memc_ ## brX & 0xFFFF8000;	\
-    ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF;	\
-    printf ("\n"					\
-	    #brX " 0x%08x  " #orX " 0x%08x "		\
-	    "==> 0x%08lx ... 0x%08lx = %ld MB\n",	\
-	memctl->memc_ ## brX, memctl->memc_ ## orX,	\
-	start, start+sizem, (sizem+1)>>20);		\
-    } while (0)
-	prt_br_or (br0, or0);
-	prt_br_or (br1, or1);
-	prt_br_or (br2, or2);
-	prt_br_or (br3, or3);
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-	/* 60x SDRAM setup:
-	 */
-	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
-					  (uchar *) CONFIG_SYS_SDRAM_BASE);
-	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
-					  (uchar *) CONFIG_SYS_SDRAM_BASE);
-
-	if (size8 < size9) {
-		psize = size9;
-		printf ("(60x:9COL - %ld MB, ", psize >> 20);
-	} else {
-		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
-						  (uchar *) CONFIG_SYS_SDRAM_BASE);
-		printf ("(60x:8COL - %ld MB, ", psize >> 20);
-	}
-
-	/* Local SDRAM setup:
-	 */
-#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
-	memctl->memc_lsrt = CONFIG_SYS_LSRT;
-	size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
-					  (uchar *) SDRAM_BASE2_PRELIM);
-	size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL,
-					  (uchar *) SDRAM_BASE2_PRELIM);
-
-	if (size8 < size9) {
-		lsize = size9;
-		printf ("Local:9COL - %ld MB) using ", lsize >> 20);
-	} else {
-		lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
-						  (uchar *) SDRAM_BASE2_PRELIM);
-		printf ("Local:8COL - %ld MB) using ", lsize >> 20);
-	}
-
-#if 0
-	/* Set up BR2 so that the local SDRAM goes
-	 * right after the 60x SDRAM
-	 */
-	memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) |
-			(CONFIG_SYS_SDRAM_BASE + psize);
-#endif
-#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	icache_enable ();
-
-	return (psize);
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/tqc/tqm8272/Kconfig b/board/tqc/tqm8272/Kconfig
deleted file mode 100644
index 7b5cd8bc7c9..00000000000
--- a/board/tqc/tqm8272/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_TQM8272
-
-config SYS_BOARD
-	default "tqm8272"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM8272"
-
-endif
diff --git a/board/tqc/tqm8272/MAINTAINERS b/board/tqc/tqm8272/MAINTAINERS
deleted file mode 100644
index 988d2b189bc..00000000000
--- a/board/tqc/tqm8272/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TQM8272 BOARD
-#M:	-
-S:	Maintained
-F:	board/tqc/tqm8272/
-F:	include/configs/TQM8272.h
-F:	configs/TQM8272_defconfig
diff --git a/board/tqc/tqm8272/Makefile b/board/tqc/tqm8272/Makefile
deleted file mode 100644
index 8bf02414e30..00000000000
--- a/board/tqc/tqm8272/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= tqm8272.o ../tqm8xx/load_sernum_ethaddr.o nand.o
diff --git a/board/tqc/tqm8272/nand.c b/board/tqc/tqm8272/nand.c
deleted file mode 100644
index 7fb2dfabc17..00000000000
--- a/board/tqc/tqm8272/nand.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * (C) Copyright 2008
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-
-#include "tqm8272.h"
-
-/* UPM pattern for bus clock = 66.7 MHz */
-static const uint upmTable67[] =
-{
-    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
-    /* 0x00 */	0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
-    /* 0x04 */	0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
-    /* 0x18 */	0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
-    /* 0x1C */	0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Write Burst RAM array entry -> unused */
-    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Refresh Timer RAM array entry -> unused */
-    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Exception RAM array entry -> unsused */
-    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 100 MHz */
-static const uint upmTable100[] =
-{
-    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
-    /* 0x00 */	0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
-    /* 0x04 */	0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
-    /* 0x18 */	0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
-    /* 0x1C */	0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Write Burst RAM array entry -> unused */
-    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Refresh Timer RAM array entry -> unused */
-    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Exception RAM array entry -> unsused */
-    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 133.3 MHz */
-static const uint upmTable133[] =
-{
-    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
-    /* 0x00 */	0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
-    /* 0x04 */	0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
-    /* 0x18 */	0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
-    /* 0x1C */	0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Write Burst RAM array entry -> unused */
-    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Refresh Timer RAM array entry -> unused */
-    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Exception RAM array entry -> unsused */
-    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-static int	chipsel = 0;
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-#include <linux/mtd/mtd.h>
-
-static u8 hwctl = 0;
-
-static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
-
-	if (hwctl & 0x1) {
-		WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS);
-	} else if (hwctl & 0x2) {
-		WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS);
-	} else {
-		WRITE_NAND(byte, base);
-	}
-}
-
-static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-	if (ctrl & NAND_CTRL_CHANGE) {
-		if ( ctrl & NAND_CLE )
-			hwctl |= 0x1;
-		else
-			hwctl &= ~0x1;
-		if ( ctrl & NAND_ALE )
-			hwctl |= 0x2;
-		else
-			hwctl &= ~0x2;
-	}
-	if (cmd != NAND_CMD_NONE)
-		upmnand_write_byte (mtd, cmd);
-}
-
-static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
-
-	return READ_NAND(base);
-}
-
-static int tqm8272_dev_ready(struct mtd_info *mtdinfo)
-{
-	/* constant delay (see also tR in the datasheet) */
-	udelay(12); \
-	return 1;
-}
-
-#ifndef CONFIG_NAND_SPL
-static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
-	int	i;
-
-	for (i = 0; i< len; i++)
-		buf[i] = *base;
-}
-
-static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
-	int	i;
-
-	for (i = 0; i< len; i++)
-		*base = buf[i];
-}
-
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
-	int	i;
-
-	for (i = 0; i < len; i++)
-		if (buf[i] != *base)
-			return -1;
-	return 0;
-}
-#endif
-#endif /* #ifndef CONFIG_NAND_SPL */
-
-void board_nand_select_device(struct nand_chip *nand, int chip)
-{
-	chipsel = chip;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
-	static	int	UpmInit = 0;
-	volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immr->im_memctl;
-
-	if (hwinf.nand == 0) return -1;
-
-	/* Setup the UPM */
-	if (UpmInit == 0) {
-		switch (hwinf.busclk_real) {
-		case 100000000:
-			upmconfig (UPMB, (uint *) upmTable100,
-			   sizeof (upmTable100) / sizeof (uint));
-			break;
-		case 133333333:
-			upmconfig (UPMB, (uint *) upmTable133,
-			   sizeof (upmTable133) / sizeof (uint));
-			break;
-		default:
-			upmconfig (UPMB, (uint *) upmTable67,
-			   sizeof (upmTable67) / sizeof (uint));
-			break;
-		}
-		UpmInit = 1;
-	}
-
-	/* Setup the memctrl */
-	memctl->memc_or3 = CONFIG_SYS_NAND_OR;
-	memctl->memc_br3 = CONFIG_SYS_NAND_BR;
-	memctl->memc_mbmr = (MxMR_OP_NORM);
-
-	nand->ecc.mode = NAND_ECC_SOFT;
-
-	nand->cmd_ctrl	 = upmnand_hwcontrol;
-	nand->read_byte	 = upmnand_read_byte;
-	nand->dev_ready	 = tqm8272_dev_ready;
-
-#ifndef CONFIG_NAND_SPL
-	nand->write_buf	 = tqm8272_write_buf;
-	nand->read_buf	 = tqm8272_read_buf;
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-	nand->verify_buf = tqm8272_verify_buf;
-#endif
-#endif
-
-	/*
-	 * Select required NAND chip
-	 */
-	board_nand_select_device(nand, 0);
-	return 0;
-}
-
-#endif
diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c
deleted file mode 100644
index d6508681e9a..00000000000
--- a/board/tqc/tqm8272/tqm8272.c
+++ /dev/null
@@ -1,944 +0,0 @@
-/*
- * (C) Copyright 2006
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-
-#include <command.h>
-#include <netdev.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/m8260_pci.h>
-#endif
-#include "tqm8272.h"
-
-#if 0
-#define deb_printf(fmt,arg...) \
-	printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg)
-#else
-#define deb_printf(fmt,arg...) \
-	do { } while (0)
-#endif
-
-#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
-unsigned long board_get_cpu_clk_f (void);
-#endif
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A configuration */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PA31 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 *ATMTXEN */
-	/* PA30 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTCA	*/
-	/* PA29 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTSOC	*/
-	/* PA28 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 *ATMRXEN */
-	/* PA27 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRSOC */
-	/* PA26 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRCA */
-	/* PA25 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[0] */
-	/* PA24 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[1] */
-	/* PA23 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[2] */
-	/* PA22 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[3] */
-	/* PA21 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[4] */
-	/* PA20 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[5] */
-	/* PA19 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[6] */
-	/* PA18 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[7] */
-	/* PA17 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[7] */
-	/* PA16 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[6] */
-	/* PA15 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[5] */
-	/* PA14 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[4] */
-	/* PA13 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[3] */
-	/* PA12 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[2] */
-	/* PA11 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[1] */
-	/* PA10 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[0] */
-	/* PA9	*/ {   1,   1,	 0,   1,   0,	0   }, /* SMC2 TXD */
-	/* PA8	*/ {   1,   1,	 0,   0,   0,	0   }, /* SMC2 RXD */
-	/* PA7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA7 */
-	/* PA6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA6 */
-	/* PA5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA5 */
-	/* PA4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA4 */
-	/* PA3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA3 */
-	/* PA2	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA2 */
-	/* PA1	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA1 */
-	/* PA0	*/ {   0,   0,	 0,   1,   0,	0   }  /* PA0 */
-    },
-
-    /* Port B configuration */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TX_ER */
-	/* PB30 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_DV */
-	/* PB29 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC2 MII TX_EN */
-	/* PB28 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_ER */
-	/* PB27 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII COL */
-	/* PB26 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII CRS */
-	/* PB25 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[3] */
-	/* PB24 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[2] */
-	/* PB23 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[1] */
-	/* PB22 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[0] */
-	/* PB21 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[0] */
-	/* PB20 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[1] */
-	/* PB19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[2] */
-	/* PB18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   0,	 0,   0,   0,	0   }, /* PB17 */
-	/* PB16 */ {   0,   0,	 0,   0,   0,	0   }, /* PB16 */
-	/* PB15 */ {   0,   0,	 0,   0,   0,	0   }, /* PB15 */
-	/* PB14 */ {   0,   0,	 0,   0,   0,	0   }, /* PB14 */
-	/* PB13 */ {   0,   0,	 0,   0,   0,	0   }, /* PB13 */
-	/* PB12 */ {   0,   0,	 0,   0,   0,	0   }, /* PB12 */
-	/* PB11 */ {   0,   0,	 0,   0,   0,	0   }, /* PB11 */
-	/* PB10 */ {   0,   0,	 0,   0,   0,	0   }, /* PB10 */
-	/* PB9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB9 */
-	/* PB8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB8 */
-	/* PB7	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB7 */
-	/* PB6	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB6 */
-	/* PB5	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB5 */
-	/* PB4	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB4 */
-	/* PB3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PB2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PB1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PB0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
-    },
-
-    /* Port C */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,	 0,   1,   0,	0   }, /* PC31 */
-	/* PC30 */ {   0,   0,	 0,   0,   0,	0   }, /* PC30 */
-	/* PC29 */ {   1,   1,	 1,   0,   0,	0   }, /* SCC1 EN *CLSN */
-	/* PC28 */ {   0,   0,	 0,   1,   0,	0   }, /* PC28 */
-	/* PC27 */ {   0,   0,	 0,   1,   0,	0   }, /* PC27 */
-	/* PC26 */ {   0,   0,	 0,   1,   0,	0   }, /* PC26 */
-	/* PC25 */ {   0,   0,	 0,   1,   0,	0   }, /* PC25 */
-	/* PC24 */ {   0,   0,	 0,   1,   0,	0   }, /* PC24 */
-	/* PC23 */ {   0,   1,	 0,   1,   0,	0   }, /* ATMTFCLK */
-	/* PC22 */ {   0,   1,	 0,   0,   0,	0   }, /* ATMRFCLK */
-	/* PC21 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC1 EN RXCLK */
-	/* PC20 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC1 EN TXCLK */
-	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_CLK */
-	/* PC18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII TX_CLK */
-	/* PC17 */ {   1,   0,	 0,   1,   0,	0   }, /* PC17 MDC */
-	/* PC16 */ {   1,   0,	 0,   0,   0,	0   }, /* PC16 MDIO*/
-	/* PC15 */ {   0,   0,	 0,   1,   0,	0   }, /* PC15 */
-	/* PC14 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CD */
-	/* PC13 */ {   0,   0,	 0,   1,   0,	0   }, /* PC13 */
-	/* PC12 */ {   0,   0,	 0,   1,   0,	0   }, /* PC12 */
-	/* PC11 */ {   0,   0,	 0,   1,   0,	0   }, /* PC11 */
-	/* PC10 */ {   0,   0,	 0,   1,   0,	0   }, /* PC10 */
-	/* PC9	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC9 */
-	/* PC8	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC8 */
-	/* PC7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC7 */
-	/* PC6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC6 */
-	/* PC5	*/ {   1,   1,	 0,   1,   0,	0   }, /* PC5 SMC1 TXD */
-	/* PC4	*/ {   1,   1,	 0,   0,   0,	0   }, /* PC4 SMC1 RXD */
-	/* PC3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC3 */
-	/* PC2	*/ {   0,   0,	 0,   1,   0,	1   }, /* ENET FDE */
-	/* PC1	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET DSQE */
-	/* PC0	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET LBK */
-    },
-
-    /* Port D */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PD31 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC1 EN RxD */
-	/* PD30 */ {   1,   1,	 1,   1,   0,	0   }, /* SCC1 EN TxD */
-	/* PD29 */ {   1,   1,	 0,   1,   0,	0   }, /* SCC1 EN TENA */
-	/* PD28 */ {   0,   0,	 0,   1,   0,	0   }, /* PD28 */
-	/* PD27 */ {   0,   0,	 0,   1,   0,	0   }, /* PD27 */
-	/* PD26 */ {   0,   0,	 0,   1,   0,	0   }, /* PD26 */
-	/* PD25 */ {   0,   0,	 0,   1,   0,	0   }, /* PD25 */
-	/* PD24 */ {   0,   0,	 0,   1,   0,	0   }, /* PD24 */
-	/* PD23 */ {   0,   0,	 0,   1,   0,	0   }, /* PD23 */
-	/* PD22 */ {   0,   0,	 0,   1,   0,	0   }, /* PD22 */
-	/* PD21 */ {   0,   0,	 0,   1,   0,	0   }, /* PD21 */
-	/* PD20 */ {   0,   0,	 0,   1,   0,	0   }, /* PD20 */
-	/* PD19 */ {   0,   0,	 0,   1,   0,	0   }, /* PD19 */
-	/* PD18 */ {   0,   0,	 0,   1,   0,	0   }, /* PD19 */
-	/* PD17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXPRTY */
-	/* PD16 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXPRTY */
-#if defined(CONFIG_SYS_I2C_SOFT)
-	/* PD15 */ {   1,   0,	 0,   1,   1,	1   }, /* I2C SDA */
-	/* PD14 */ {   1,   0,	 0,   1,   1,	1   }, /* I2C SCL */
-#else
-#if defined(CONFIG_HARD_I2C)
-	/* PD15 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SDA */
-	/* PD14 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SCL */
-#else /* normal I/O port pins */
-	/* PD15 */ {   0,   1,	 1,   0,   1,	0   }, /* I2C SDA */
-	/* PD14 */ {   0,   1,	 1,   0,   1,	0   }, /* I2C SCL */
-#endif
-#endif
-	/* PD13 */ {   0,   0,	 0,   0,   0,	0   }, /* PD13 */
-	/* PD12 */ {   0,   0,	 0,   0,   0,	0   }, /* PD12 */
-	/* PD11 */ {   0,   0,	 0,   0,   0,	0   }, /* PD11 */
-	/* PD10 */ {   0,   0,	 0,   0,   0,	0   }, /* PD10 */
-	/* PD9	*/ {   1,   1,	 0,   1,   0,	0   }, /* SMC1 TXD */
-	/* PD8	*/ {   1,   1,	 0,   0,   0,	0   }, /* SMC1 RXD */
-	/* PD7	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD7 */
-	/* PD6	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD6 */
-	/* PD5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PD5 */
-	/* PD4	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD4 */
-	/* PD3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PD2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PD1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
-	/* PD0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
-    }
-};
-
-/* UPM pattern for slow init */
-static const uint upmTableSlow[] =
-{
-    /* Offset	UPM Read Single RAM array entry */
-    /* 0x00 */	0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00,
-    /* 0x04 */	0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Write Single RAM array entry */
-    /* 0x18 */	0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80,
-    /* 0x1C */	0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
-
-		/* UPM Write Burst RAM array entry -> unused */
-    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Refresh Timer RAM array entry -> unused */
-    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Exception RAM array entry -> unused */
-    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for fast init */
-static const uint upmTableFast[] =
-{
-    /* Offset	UPM Read Single RAM array entry */
-    /* 0x00 */	0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00,
-    /* 0x04 */	0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Write Single RAM array entry */
-    /* 0x18 */	0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00,
-    /* 0x1C */	0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
-
-		/* UPM Write Burst RAM array entry -> unused */
-    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Refresh Timer RAM array entry -> unused */
-    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Exception RAM array entry -> unused */
-    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
-	char *p = (char *) HWIB_INFO_START_ADDR;
-
-	puts ("Board: ");
-	if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
-		puts (p);
-	} else {
-		puts ("No HWIB assuming TQM8272");
-	}
-	putc ('\n');
-
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
-static int get_cas_latency (void)
-{
-	/* get it from the option -ts in CIB */
-	/* default is 3 */
-	int	ret = 3;
-	int	pos = 0;
-	char	*p = (char *) CIB_INFO_START_ADDR;
-
-	while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
-		if (*p < ' ' || *p > '~') { /* ASCII strings! */
-			return ret;
-		}
-		if (*p == '-') {
-			if ((p[1] == 't') && (p[2] == 's')) {
-				return (p[4] - '0');
-			}
-		}
-		p++;
-		pos++;
-	}
-	return ret;
-}
-#endif
-
-static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col)
-{
-#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
-	int	clk = board_get_cpu_clk_f ();
-	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	int	busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0);
-	int	cas;
-
-	sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \
-			 PSDMR_BUFCMD);
-	if (busmode) {
-		switch (clk) {
-			case 66666666:
-				sdmr |= (PSDMR_RFRC_66MHZ_60X | \
-					PSDMR_PRETOACT_66MHZ_60X | \
-					PSDMR_WRC_66MHZ_60X | \
-					PSDMR_BUFCMD_66MHZ_60X);
-				break;
-			case 100000000:
-				sdmr |= (PSDMR_RFRC_100MHZ_60X | \
-					PSDMR_PRETOACT_100MHZ_60X | \
-					PSDMR_WRC_100MHZ_60X | \
-					PSDMR_BUFCMD_100MHZ_60X);
-				break;
-
-		}
-	} else {
-		switch (clk) {
-			case 66666666:
-				sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \
-					PSDMR_PRETOACT_66MHZ_SINGLE | \
-					PSDMR_WRC_66MHZ_SINGLE | \
-					PSDMR_BUFCMD_66MHZ_SINGLE);
-				break;
-			case 100000000:
-				sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \
-					PSDMR_PRETOACT_100MHZ_SINGLE | \
-					PSDMR_WRC_100MHZ_SINGLE | \
-					PSDMR_BUFCMD_100MHZ_SINGLE);
-				break;
-			case 133333333:
-				sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \
-					PSDMR_PRETOACT_133MHZ_SINGLE | \
-					PSDMR_WRC_133MHZ_SINGLE | \
-					PSDMR_BUFCMD_133MHZ_SINGLE);
-				break;
-		}
-	}
-	cas = get_cas_latency();
-	sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK);
-	sdmr |= cas;
-	sdmr |= ((cas - 1) << 6);
-	return sdmr;
-#else
-	return sdmr;
-#endif
-}
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
-						  ulong orx, volatile uchar * base, int col)
-{
-	volatile uchar c = 0xff;
-	volatile uint *sdmr_ptr;
-	volatile uint *orx_ptr;
-	ulong maxsize, size;
-	int i;
-
-	/* We must be able to test a location outsize the maximum legal size
-	 * to find out THAT we are outside; but this address still has to be
-	 * mapped by the controller. That means, that the initial mapping has
-	 * to be (at least) twice as large as the maximum expected size.
-	 */
-	maxsize = (1 + (~orx | 0x7fff)) / 2;
-
-	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
-	 * we are configuring CS1 if base != 0
-	 */
-	sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
-	orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
-
-	*orx_ptr = orx;
-	sdmr = set_sdram_timing (sdmr_ptr, sdmr, col);
-	/*
-	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
-	 *
-	 * "At system reset, initialization software must set up the
-	 *  programmable parameters in the memory controller banks registers
-	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
-	 *  system software should execute the following initialization sequence
-	 *  for each SDRAM device.
-	 *
-	 *  1. Issue a PRECHARGE-ALL-BANKS command
-	 *  2. Issue eight CBR REFRESH commands
-	 *  3. Issue a MODE-SET command to initialize the mode register
-	 *
-	 *  The initial commands are executed by setting P/LSDMR[OP] and
-	 *  accessing the SDRAM with a single-byte transaction."
-	 *
-	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
-	 */
-
-	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
-	*base = c;
-
-	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
-	for (i = 0; i < 8; i++)
-		*base = c;
-
-	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
-
-	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
-	*base = c;
-
-	size = get_ram_size((long *)base, maxsize);
-	*orx_ptr = orx | ~(size - 1);
-
-	return (size);
-}
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	long size8, size9;
-#endif
-	long psize;
-
-	psize = 16 * 1024 * 1024;
-
-	memctl->memc_psrt = CONFIG_SYS_PSRT;
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	/* 60x SDRAM setup:
-	 */
-	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
-					  (uchar *) CONFIG_SYS_SDRAM_BASE, 8);
-	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
-					  (uchar *) CONFIG_SYS_SDRAM_BASE, 9);
-
-	if (size8 < size9) {
-		psize = size9;
-		printf ("(60x:9COL - %ld MB, ", psize >> 20);
-	} else {
-		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
-						  (uchar *) CONFIG_SYS_SDRAM_BASE, 8);
-		printf ("(60x:8COL - %ld MB, ", psize >> 20);
-	}
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	icache_enable ();
-
-	return (psize);
-}
-
-
-static inline int scanChar (char *p, int len, unsigned long *number)
-{
-	int	akt = 0;
-
-	*number = 0;
-	while (akt < len) {
-		if ((*p >= '0') && (*p <= '9')) {
-			*number *= 10;
-			*number += *p - '0';
-			p += 1;
-		} else {
-			if (*p == '-')	return akt;
-			return -1;
-		}
-		akt ++;
-	}
-	return akt;
-}
-
-static int dump_hwib(void)
-{
-	HWIB_INFO	*hw = &hwinf;
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
-	if (i < 0)
-		buf[0] = '\0';
-
-	if (hw->OK) {
-		printf ("HWIB on %x\n", HWIB_INFO_START_ADDR);
-		printf ("serial : %s\n", buf);
-		printf ("ethaddr: %s\n", hw->ethaddr);
-		printf ("FLASH	: %x nr:%d\n", hw->flash, hw->flash_nr);
-		printf ("RAM	: %x cs:%d\n", hw->ram, hw->ram_cs);
-		printf ("CPU	: %lu\n", hw->cpunr);
-		printf ("CAN	: %d\n", hw->can);
-		if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom);
-		else printf ("No EEprom\n");
-		if (hw->nand) {
-			printf ("NAND	: %x\n", hw->nand);
-			printf ("NAND CS: %d\n", hw->nand_cs);
-		} else { printf ("No NAND\n");}
-		printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII"));
-		printf ("  real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \
-				 "60x" : "Single PQII"));
-		printf ("Option : %lx\n", hw->option);
-		printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no"));
-		printf ("CPM Clk: %d\n", hw->cpmcl);
-		printf ("CPU Clk: %d\n", hw->cpucl);
-		printf ("Bus Clk: %d\n", hw->buscl);
-		if (hw->busclk_real_ok) {
-			printf ("  real Clk: %d\n", hw->busclk_real);
-		}
-		printf ("CAS	: %d\n", get_cas_latency());
-	} else {
-		printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR);
-	}
-	return 0;
-}
-
-static inline int search_real_busclk (int *clk)
-{
-	int	part = 0, pos = 0;
-	char *p = (char *) CIB_INFO_START_ADDR;
-	int	ok = 0;
-
-	while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
-		if (*p < ' ' || *p > '~') { /* ASCII strings! */
-			return 0;
-		}
-		switch (part) {
-		default:
-			if (*p == '-') {
-				++part;
-			}
-			break;
-		case 3:
-			if (*p == '-') {
-				++part;
-				break;
-			}
-			if (*p == 'b') {
-				ok = 1;
-				p++;
-				break;
-			}
-			if (ok) {
-				switch (*p) {
-				case '6':
-					*clk = 66666666;
-					return 1;
-					break;
-				case '1':
-					if (p[1] == '3') {
-						*clk = 133333333;
-					} else {
-						*clk = 100000000;
-					}
-					return 1;
-					break;
-				}
-			}
-			break;
-		}
-		p++;
-	}
-	return 0;
-}
-
-int analyse_hwib (void)
-{
-	char	*p = (char *) HWIB_INFO_START_ADDR;
-	int	anz;
-	int	part = 1, i = 0, pos = 0;
-	HWIB_INFO	*hw = &hwinf;
-
-	deb_printf(" %s pointer: %p\n", __FUNCTION__, p);
-	/* Head = TQM */
-	if (*((unsigned long *)p) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
-		deb_printf("No HWIB\n");
-		return -1;
-	}
-	p += 3;
-	if (scanChar (p, 4, &hw->cpunr) < 0) {
-		deb_printf("No CPU\n");
-		return -2;
-	}
-	p +=4;
-
-	hw->flash = 0x200000 << (*p - 'A');
-	p++;
-	hw->flash_nr = *p - '0';
-	p++;
-
-	hw->ram = 0x2000000 << (*p - 'A');
-	p++;
-	if (*p == '2') {
-		hw->ram_cs = 2;
-		p++;
-	}
-
-	if (*p == 'A') hw->can = 1;
-	if (*p == 'B') hw->can = 2;
-	p +=1;
-	p +=1;	/* connector */
-	if (*p != '0') {
-		hw->eeprom = 0x1000 << (*p - 'A');
-	}
-	p++;
-
-	if ((*p < '0') || (*p > '9')) {
-		/* NAND before z-option */
-		hw->nand = 0x8000000 << (*p - 'A');
-		p++;
-		hw->nand_cs = *p - '0';
-		p += 2;
-	}
-	/* z-option */
-	anz = scanChar (p, 4, &hw->option);
-	if (anz < 0) {
-		deb_printf("No option\n");
-		return -3;
-	}
-	if (hw->option & 0x8) hw->Bus = 1;
-	p += anz;
-	if (*p != '-') {
-		deb_printf("No -\n");
-		return -4;
-	}
-	p++;
-	/* C option */
-	if (*p == 'E') {
-		hw->SecEng = 1;
-		p++;
-	}
-	switch (*p) {
-		case 'M': hw->cpucl = 266666666;
-			break;
-		case 'P': hw->cpucl = 300000000;
-			break;
-		case 'T': hw->cpucl = 400000000;
-			break;
-		default:
-			deb_printf("No CPU Clk: %c\n", *p);
-			return -5;
-			break;
-	}
-	p++;
-	switch (*p) {
-		case 'I': hw->cpmcl = 200000000;
-			break;
-		case 'M': hw->cpmcl = 300000000;
-			break;
-		default:
-			deb_printf("No CPM Clk\n");
-			return -6;
-			break;
-	}
-	p++;
-	switch (*p) {
-		case 'B': hw->buscl = 66666666;
-			break;
-		case 'E': hw->buscl = 100000000;
-			break;
-		case 'F': hw->buscl = 133333333;
-			break;
-		default:
-			deb_printf("No BUS Clk\n");
-			return -7;
-			break;
-	}
-	p++;
-
-	hw->OK = 1;
-	/* search MAC Address */
-	while ((*p != '\0') && (pos < CONFIG_SYS_HWINFO_SIZE)) {
-		if (*p < ' ' || *p > '~') { /* ASCII strings! */
-			return 0;
-		}
-		switch (part) {
-		default:
-			if (*p == ' ') {
-				++part;
-				i = 0;
-			}
-			break;
-		case 3:			/* Copy MAC address */
-			if (*p == ' ') {
-				++part;
-				i = 0;
-				break;
-			}
-			hw->ethaddr[i++] = *p;
-			if ((i % 3) == 2)
-				hw->ethaddr[i++] = ':';
-			break;
-
-		}
-		p++;
-	}
-
-	hw->busclk_real_ok = search_real_busclk (&hw->busclk_real);
-	return 0;
-}
-
-#if defined(CONFIG_GET_CPU_STR_F)
-/* !! This routine runs from Flash */
-char get_cpu_str_f (char *buf)
-{
-	char *p = (char *) HWIB_INFO_START_ADDR;
-	int	i = 0;
-
-	buf[i++] = 'M';
-	buf[i++] = 'P';
-	buf[i++] = 'C';
-	if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
-		buf[i++] = *&p[3];
-		buf[i++] = *&p[4];
-		buf[i++] = *&p[5];
-		buf[i++] = *&p[6];
-	} else {
-		buf[i++] = '8';
-		buf[i++] = '2';
-		buf[i++] = '7';
-		buf[i++] = 'x';
-	}
-	buf[i++] = 0;
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
-/* !! This routine runs from Flash */
-unsigned long board_get_cpu_clk_f (void)
-{
-	char *p = (char *) HWIB_INFO_START_ADDR;
-	int i = 0;
-
-	if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
-		if (search_real_busclk (&i))
-			return i;
-	}
-	return CONFIG_8260_CLKIN;
-}
-#endif
-
-#if CONFIG_BOARD_EARLY_INIT_R
-
-static int can_test (unsigned long off)
-{
-	volatile unsigned char	*base	= (unsigned char *) (CONFIG_SYS_CAN_BASE + off);
-
-	*(base + 0x17) = 'T';
-	*(base + 0x18) = 'Q';
-	*(base + 0x19) = 'M';
-	if ((*(base + 0x17) != 'T') ||
-	    (*(base + 0x18) != 'Q') ||
-	    (*(base + 0x19) != 'M')) {
-		return 0;
-	}
-	return 1;
-}
-
-static int can_config_one (unsigned long off)
-{
-	volatile unsigned char	*ctrl	= (unsigned char *) (CONFIG_SYS_CAN_BASE + off);
-	volatile unsigned char	*cpu_if = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x02);
-	volatile unsigned char	*clkout = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x1f);
-	unsigned char temp;
-
-	*cpu_if = 0x45;
-	temp = *ctrl;
-	temp |= 0x40;
-	*ctrl	= temp;
-	*clkout = 0x20;
-	temp = *ctrl;
-	temp &= ~0x40;
-	*ctrl	= temp;
-	return 0;
-}
-
-static int can_config (void)
-{
-	int	ret = 0;
-	can_config_one (0);
-	if (hwinf.can == 2) {
-		can_config_one (0x100);
-	}
-	/* make Test if they really there */
-	ret += can_test (0);
-	ret += can_test (0x100);
-	return ret;
-}
-
-static int init_can (void)
-{
-	volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immr->im_memctl;
-	int	count = 0;
-
-	if ((hwinf.OK) && (hwinf.can)) {
-		memctl->memc_or4 = CONFIG_SYS_CAN_OR;
-		memctl->memc_br4 = CONFIG_SYS_CAN_BR;
-		/* upm Init */
-		upmconfig (UPMC, (uint *) upmTableFast,
-			   sizeof (upmTableFast) / sizeof (uint));
-		memctl->memc_mcmr =	(MxMR_DSx_3_CYCL |
-					MxMR_GPL_x4DIS |
-					MxMR_RLFx_2X |
-					MxMR_WLFx_2X |
-					MxMR_OP_NORM);
-		/* can configure */
-		count = can_config ();
-		printf ("CAN:	%d @ %x\n", count, CONFIG_SYS_CAN_BASE);
-		if (hwinf.can != count) printf("!!! difference to HWIB\n");
-	} else {
-		printf ("CAN:	No\n");
-	}
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	analyse_hwib ();
-	init_can ();
-	return 0;
-}
-#endif
-
-int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	dump_hwib ();
-	return 0;
-}
-
-U_BOOT_CMD(
-	  hwib, 1,	1,	do_hwib_dump,
-	  "dump HWIB'",
-	  ""
-);
-
-#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
-static int get_flash_timing (void)
-{
-	/* get it from the option -tf in CIB */
-	/* default is 0x00000c84 */
-	int	ret = 0x00000c84;
-	int	pos = 0;
-	int	nr = 0;
-	char	*p = (char *) CIB_INFO_START_ADDR;
-
-	while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
-		if (*p < ' ' || *p > '~') { /* ASCII strings! */
-			return ret;
-		}
-		if (*p == '-') {
-			if ((p[1] == 't') && (p[2] == 'f')) {
-				p += 6;
-				ret = 0;
-				while (nr < 8) {
-				if ((*p >= '0') && (*p <= '9')) {
-					ret *= 0x10;
-					ret += *p - '0';
-					p += 1;
-					nr ++;
-				} else if ((*p >= 'A') && (*p <= 'F')) {
-					ret *= 10;
-					ret += *p - '7';
-					p += 1;
-					nr ++;
-				} else {
-					if (nr < 8) return 0x00000c84;
-					return ret;
-				}
-				}
-			}
-		}
-		p++;
-		pos++;
-	}
-	return ret;
-}
-
-/* Update the Flash_Size and the Flash Timing */
-int update_flash_size (int flash_size)
-{
-	volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immr->im_memctl;
-	unsigned long reg;
-	unsigned long tim;
-
-	/* I must use reg, otherwise the board hang */
-	reg = memctl->memc_or0;
-	reg &= ~ORxU_AM_MSK;
-	reg |= MEG_TO_AM(flash_size >> 20);
-	tim = get_flash_timing ();
-	reg &= ~0xfff;
-	reg |= (tim & 0xfff);
-	memctl->memc_or0 = reg;
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-int board_early_init_f (void)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-	immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
-	return 0;
-}
-
-extern void pci_mpc8250_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc8250_init(&hose);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
diff --git a/board/tqc/tqm8272/tqm8272.h b/board/tqc/tqm8272/tqm8272.h
deleted file mode 100644
index 1eeaf0e993c..00000000000
--- a/board/tqc/tqm8272/tqm8272.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * (C) Copyright 2008
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef	_TQM8272_HEADER_H
-#define	_TQM8272_HEADER_H
-
-#define _NOT_USED_	0xFFFFFFFF
-
-typedef struct{
-	int	Bus;
-	int	flash;
-	int	flash_nr;
-	int	ram;
-	int	ram_cs;
-	int	nand;
-	int	nand_cs;
-	int	eeprom;
-	int	can;
-	unsigned long	cpunr;
-	unsigned long	option;
-	int	SecEng;
-	int	cpucl;
-	int	cpmcl;
-	int	buscl;
-	int	busclk_real_ok;
-	int	busclk_real;
-	unsigned char	OK;
-	unsigned char  ethaddr[20];
-} HWIB_INFO;
-
-static HWIB_INFO	hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0,
-			 0, 0, 0, 0, 0, 0};
-#endif	/* __CONFIG_H */
diff --git a/board/tqc/tqma6/Kconfig b/board/tqc/tqma6/Kconfig
index b70cbf09df4..f8b3d1fd404 100644
--- a/board/tqc/tqma6/Kconfig
+++ b/board/tqc/tqma6/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_TQMA6
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "tqma6"
 
diff --git a/board/trizepsiv/Kconfig b/board/trizepsiv/Kconfig
index 9844c692a18..56b255709a2 100644
--- a/board/trizepsiv/Kconfig
+++ b/board/trizepsiv/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_TRIZEPSIV
 
-config SYS_CPU
-	default "pxa"
-
 config SYS_BOARD
 	default "trizepsiv"
 
diff --git a/board/ttcontrol/vision2/Kconfig b/board/ttcontrol/vision2/Kconfig
index 4e2271bdad8..cacd2c5dfe2 100644
--- a/board/ttcontrol/vision2/Kconfig
+++ b/board/ttcontrol/vision2/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_VISION2
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "vision2"
 
diff --git a/board/udoo/Kconfig b/board/udoo/Kconfig
index a98d0d6a4cf..970f39f0f7f 100644
--- a/board/udoo/Kconfig
+++ b/board/udoo/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_UDOO
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "udoo"
 
diff --git a/board/vpac270/Kconfig b/board/vpac270/Kconfig
index a046f01f6d4..1701b35d12a 100644
--- a/board/vpac270/Kconfig
+++ b/board/vpac270/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_VPAC270
 
-config SYS_CPU
-	default "pxa"
-
 config SYS_BOARD
 	default "vpac270"
 
diff --git a/board/w7o/fsboot.c b/board/w7o/fsboot.c
index 25fbb55c8e6..8f4fe310d7d 100644
--- a/board/w7o/fsboot.c
+++ b/board/w7o/fsboot.c
@@ -8,12 +8,11 @@
 #include <common.h>
 #include <config.h>
 #include <command.h>
+#include <elf.h>
 
 /*
  * FIXME: Add code to test image and it's header.
  */
-extern int valid_elf_image (unsigned long addr);
-
 static int
 image_check(ulong addr)
 {
diff --git a/board/wandboard/Kconfig b/board/wandboard/Kconfig
index c8627693f2c..39285667155 100644
--- a/board/wandboard/Kconfig
+++ b/board/wandboard/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_WANDBOARD
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "wandboard"
 
diff --git a/board/woodburn/Kconfig b/board/woodburn/Kconfig
index 67023199b6c..4699526cfd8 100644
--- a/board/woodburn/Kconfig
+++ b/board/woodburn/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_WOODBURN
 
-config SYS_CPU
-	default "arm1136"
-
 config SYS_BOARD
 	default "woodburn"
 
@@ -16,9 +13,6 @@ endif
 
 if TARGET_WOODBURN_SD
 
-config SYS_CPU
-	default "arm1136"
-
 config SYS_BOARD
 	default "woodburn"
 
diff --git a/board/xaeniax/Kconfig b/board/xaeniax/Kconfig
index 288f24b227b..519e21fb9a8 100644
--- a/board/xaeniax/Kconfig
+++ b/board/xaeniax/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_XAENIAX
 
-config SYS_CPU
-	default "pxa"
-
 config SYS_BOARD
 	default "xaeniax"
 
diff --git a/board/zipitz2/Kconfig b/board/zipitz2/Kconfig
index 5f7fe1b23de..c6635040a37 100644
--- a/board/zipitz2/Kconfig
+++ b/board/zipitz2/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_ZIPITZ2
 
-config SYS_CPU
-	default "pxa"
-
 config SYS_BOARD
 	default "zipitz2"
 
diff --git a/common/Makefile b/common/Makefile
index b19d3793b46..6cc4de8a73f 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -233,6 +233,7 @@ obj-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o
 obj-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o
 obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
 obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
+obj-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o
 obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
 obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
 obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
@@ -265,4 +266,6 @@ obj-y += aboot.o
 obj-y += fb_mmc.o
 endif
 
+obj-$(CONFIG_CMD_BLOB) += cmd_blob.o
+
 CFLAGS_env_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null)
diff --git a/common/aboot.c b/common/aboot.c
index d5c464bd7da..fba8e3e683e 100644
--- a/common/aboot.c
+++ b/common/aboot.c
@@ -208,6 +208,7 @@ void write_sparse_image(block_dev_desc_t *dev_desc,
 			break;
 
 			case CHUNK_TYPE_DONT_CARE:
+			blk += blkcnt;
 			total_blocks += chunk_header->chunk_sz;
 			break;
 
diff --git a/common/board_f.c b/common/board_f.c
index e6aa298d5a4..b5bebc9dc86 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -128,14 +128,11 @@ int init_func_watchdog_reset(void)
 }
 #endif /* CONFIG_WATCHDOG */
 
-void __board_add_ram_info(int use_default)
+__weak void board_add_ram_info(int use_default)
 {
 	/* please define platform specific board_add_ram_info() */
 }
 
-void board_add_ram_info(int)
-	__attribute__ ((weak, alias("__board_add_ram_info")));
-
 static int init_baud_rate(void)
 {
 	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
@@ -221,7 +218,7 @@ static int show_dram_config(void)
 	return 0;
 }
 
-void __dram_init_banksize(void)
+__weak void dram_init_banksize(void)
 {
 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
@@ -229,9 +226,6 @@ void __dram_init_banksize(void)
 #endif
 }
 
-void dram_init_banksize(void)
-	__attribute__((weak, alias("__dram_init_banksize")));
-
 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
 static int init_func_i2c(void)
 {
diff --git a/common/board_r.c b/common/board_r.c
index 7e1a76d97f7..7c339008ed2 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -60,7 +60,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 ulong monitor_flash_len;
 
-int __board_flash_wp_on(void)
+__weak int board_flash_wp_on(void)
 {
 	/*
 	 * Most flashes can't be detected when write protection is enabled,
@@ -70,16 +70,10 @@ int __board_flash_wp_on(void)
 	return 0;
 }
 
-int board_flash_wp_on(void)
-	__attribute__ ((weak, alias("__board_flash_wp_on")));
-
-void __cpu_secondary_init_r(void)
+__weak void cpu_secondary_init_r(void)
 {
 }
 
-void cpu_secondary_init_r(void)
-	__attribute__ ((weak, alias("__cpu_secondary_init_r")));
-
 static int initr_secondary_cpu(void)
 {
 	/*
@@ -354,7 +348,7 @@ static int initr_flash(void)
 }
 #endif
 
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) && !defined(CONFIG_DM_SPI)
 static int initr_spi(void)
 {
 	/* PPC does this here */
@@ -370,7 +364,7 @@ static int initr_spi(void)
 
 #ifdef CONFIG_CMD_NAND
 /* go init the NAND */
-int initr_nand(void)
+static int initr_nand(void)
 {
 	puts("NAND:  ");
 	nand_init();
@@ -380,7 +374,7 @@ int initr_nand(void)
 
 #if defined(CONFIG_CMD_ONENAND)
 /* go init the NAND */
-int initr_onenand(void)
+static int initr_onenand(void)
 {
 	puts("NAND:  ");
 	onenand_init();
@@ -389,7 +383,7 @@ int initr_onenand(void)
 #endif
 
 #ifdef CONFIG_GENERIC_MMC
-int initr_mmc(void)
+static int initr_mmc(void)
 {
 	puts("MMC:   ");
 	mmc_initialize(gd->bd);
@@ -398,7 +392,7 @@ int initr_mmc(void)
 #endif
 
 #ifdef CONFIG_HAS_DATAFLASH
-int initr_dataflash(void)
+static int initr_dataflash(void)
 {
 	AT91F_DataflashInit();
 	dataflash_print_info();
diff --git a/common/bootm.c b/common/bootm.c
index ff81a271a55..6b3ea8c61b6 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <bootstage.h>
 #include <bzlib.h>
+#include <errno.h>
 #include <fdt_support.h>
 #include <lmb.h>
 #include <malloc.h>
@@ -83,6 +84,7 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int argc,
 {
 	const void *os_hdr;
 	bool ep_found = false;
+	int ret;
 
 	/* get kernel image header, start address and length */
 	os_hdr = boot_get_kernel(cmdtp, flag, argc, argv,
@@ -102,6 +104,7 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int argc,
 
 		images.os.end = image_get_image_end(os_hdr);
 		images.os.load = image_get_load(os_hdr);
+		images.os.arch = image_get_arch(os_hdr);
 		break;
 #endif
 #if defined(CONFIG_FIT)
@@ -129,6 +132,13 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int argc,
 			return 1;
 		}
 
+		if (fit_image_get_arch(images.fit_hdr_os,
+				       images.fit_noffset_os,
+				       &images.os.arch)) {
+			puts("Can't get image ARCH!\n");
+			return 1;
+		}
+
 		images.os.end = fit_get_end(images.fit_hdr_os);
 
 		if (fit_image_get_load(images.fit_hdr_os, images.fit_noffset_os,
@@ -144,11 +154,11 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int argc,
 		images.os.type = IH_TYPE_KERNEL;
 		images.os.comp = IH_COMP_NONE;
 		images.os.os = IH_OS_LINUX;
-		images.ep = images.os.load;
-		ep_found = true;
 
 		images.os.end = android_image_get_end(os_hdr);
 		images.os.load = android_image_get_kload(os_hdr);
+		images.ep = images.os.load;
+		ep_found = true;
 		break;
 #endif
 	default:
@@ -156,8 +166,18 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int argc,
 		return 1;
 	}
 
-	/* find kernel entry point */
-	if (images.legacy_hdr_valid) {
+	/* If we have a valid setup.bin, we will use that for entry (x86) */
+	if (images.os.arch == IH_ARCH_I386 ||
+	    images.os.arch == IH_ARCH_X86_64) {
+		ulong len;
+
+		ret = boot_get_setup(&images, IH_ARCH_I386, &images.ep, &len);
+		if (ret < 0 && ret != -ENOENT) {
+			puts("Could not find a valid setup.bin for x86\n");
+			return 1;
+		}
+		/* Kernel entry point is the setup.bin */
+	} else if (images.legacy_hdr_valid) {
 		images.ep = image_get_ep(&images.legacy_hdr_os_copy);
 #if defined(CONFIG_FIT)
 	} else if (images.fit_uname_os) {
diff --git a/common/cli.c b/common/cli.c
index 272b0288d76..075ae9dc4ae 100644
--- a/common/cli.c
+++ b/common/cli.c
@@ -36,8 +36,11 @@ int run_command(const char *cmd, int flag)
 
 	return 0;
 #else
-	return parse_string_outer(cmd,
-			FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
+	int hush_flags = FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP;
+
+	if (flag & CMD_FLAG_ENV)
+		hush_flags |= FLAG_CONT_ON_NEWLINE;
+	return parse_string_outer(cmd, hush_flags);
 #endif
 }
 
@@ -125,7 +128,7 @@ int do_run(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			return 1;
 		}
 
-		if (run_command(arg, flag) != 0)
+		if (run_command(arg, flag | CMD_FLAG_ENV) != 0)
 			return 1;
 	}
 	return 0;
diff --git a/common/cli_hush.c b/common/cli_hush.c
index 38da5a09fa3..2b654b754f5 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -3170,7 +3170,8 @@ static int parse_stream_outer(struct in_str *inp, int flag)
 		update_ifs_map();
 		if (!(flag & FLAG_PARSE_SEMICOLON) || (flag & FLAG_REPARSING)) mapset((uchar *)";$&|", 0);
 		inp->promptmode=1;
-		rcode = parse_stream(&temp, &ctx, inp, '\n');
+		rcode = parse_stream(&temp, &ctx, inp,
+				     flag & FLAG_CONT_ON_NEWLINE ? -1 : '\n');
 #ifdef __U_BOOT__
 		if (rcode == 1) flag_repeat = 0;
 #endif
diff --git a/common/cmd_blob.c b/common/cmd_blob.c
new file mode 100644
index 00000000000..82ecaf09e5e
--- /dev/null
+++ b/common/cmd_blob.c
@@ -0,0 +1,109 @@
+/*
+ *
+ * Command for encapsulating/decapsulating blob of memory.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <malloc.h>
+#include <asm/byteorder.h>
+#include <linux/compiler.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * blob_decap() - Decapsulate the data as a blob
+ * @key_mod:	- Pointer to key modifier/key
+ * @src:	- Address of data to be decapsulated
+ * @dst:	- Address of data to be decapsulated
+ * @len:	- Size of data to be decapsulated
+ *
+ * Returns zero on success,and negative on error.
+ */
+__weak int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
+{
+	return 0;
+}
+
+/**
+ * blob_encap() - Encapsulate the data as a blob
+ * @key_mod:	- Pointer to key modifier/key
+ * @src:	- Address of data to be encapsulated
+ * @dst:	- Address of data to be encapsulated
+ * @len:	- Size of data to be encapsulated
+ *
+ * Returns zero on success,and negative on error.
+ */
+__weak int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
+{
+	return 0;
+}
+
+/**
+ * do_blob() - Handle the "blob" command-line command
+ * @cmdtp:	Command data struct pointer
+ * @flag:	Command flag
+ * @argc:	Command-line argument count
+ * @argv:	Array of command-line arguments
+ *
+ * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
+ * on error.
+ */
+static int do_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	uint32_t key_addr, src_addr, dst_addr, len;
+	uint8_t *km_ptr, *src_ptr, *dst_ptr;
+	int enc, ret = 0;
+
+	if (argc != 6)
+		return CMD_RET_USAGE;
+
+	if (!strncmp(argv[1], "enc", 3))
+		enc = 1;
+	else if (!strncmp(argv[1], "dec", 3))
+		enc = 0;
+	else
+		return CMD_RET_USAGE;
+
+	src_addr = simple_strtoul(argv[2], NULL, 16);
+	dst_addr = simple_strtoul(argv[3], NULL, 16);
+	len = simple_strtoul(argv[4], NULL, 16);
+	key_addr = simple_strtoul(argv[5], NULL, 16);
+
+	km_ptr = (uint8_t *)key_addr;
+	src_ptr = (uint8_t *)src_addr;
+	dst_ptr = (uint8_t *)dst_addr;
+
+	if (enc)
+		ret = blob_encap(km_ptr, src_ptr, dst_ptr, len);
+	else
+		ret = blob_decap(km_ptr, src_ptr, dst_ptr, len);
+
+	return ret;
+}
+
+/***************************************************/
+static char blob_help_text[] =
+	"enc src dst len km - Encapsulate and create blob of data\n"
+	"                          $len bytes long at address $src and\n"
+	"                          store the result at address $dst.\n"
+	"                          $km is the 16 byte key modifier\n"
+	"                          is also required for generation/use as\n"
+	"                          key for cryptographic operation. Key\n"
+	"                          modifier should be 16 byte long.\n"
+	"blob dec src dst len km - Decapsulate the  blob of data at address\n"
+	"                          $src and store result of $len byte at\n"
+	"                          addr $dst.\n"
+	"                          $km is the 16 byte key modifier\n"
+	"                          is also required for generation/use as\n"
+	"                          key for cryptographic operation. Key\n"
+	"                          modifier should be 16 byte long.\n";
+
+U_BOOT_CMD(
+	blob, 6, 1, do_blob,
+	"Blob encapsulation/decryption",
+	blob_help_text
+);
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 843ec6e0c26..67233600b15 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -12,6 +12,7 @@
 #include <bootm.h>
 #include <command.h>
 #include <environment.h>
+#include <errno.h>
 #include <image.h>
 #include <lmb.h>
 #include <malloc.h>
diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c
index a02f0cb0bbc..29f0f1f7841 100644
--- a/common/cmd_eeprom.c
+++ b/common/cmd_eeprom.c
@@ -389,13 +389,8 @@ void eeprom_init  (void)
 #if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
 	spi_init_f ();
 #endif
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) || \
-	defined(CONFIG_SYS_I2C)
-#ifdef CONFIG_SYS_I2C
-	i2c_init_all();
-#else
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 }
 
diff --git a/common/cmd_elf.c b/common/cmd_elf.c
index ab9c7e332d9..42a52965c27 100644
--- a/common/cmd_elf.c
+++ b/common/cmd_elf.c
@@ -14,6 +14,7 @@
  */
 
 #include <common.h>
+#include <bootm.h>
 #include <command.h>
 #include <linux/ctype.h>
 #include <net.h>
@@ -28,8 +29,7 @@ static unsigned long load_elf_image_phdr(unsigned long addr);
 static unsigned long load_elf_image_shdr(unsigned long addr);
 
 /* Allow ports to override the default behavior */
-__attribute__((weak))
-unsigned long do_bootelf_exec(ulong (*entry)(int, char * const[]),
+static unsigned long do_bootelf_exec(ulong (*entry)(int, char * const[]),
 			       int argc, char * const argv[])
 {
 	unsigned long ret;
diff --git a/common/cmd_gpio.c b/common/cmd_gpio.c
index 11f4e4031da..65d6df451c6 100644
--- a/common/cmd_gpio.c
+++ b/common/cmd_gpio.c
@@ -12,7 +12,7 @@
 #include <dm.h>
 #include <asm/gpio.h>
 
-int __weak name_to_gpio(const char *name)
+__weak int name_to_gpio(const char *name)
 {
 	return simple_strtoul(name, NULL, 10);
 }
@@ -25,13 +25,6 @@ enum gpio_cmd {
 };
 
 #if defined(CONFIG_DM_GPIO) && !defined(gpio_status)
-static const char * const gpio_function[GPIOF_COUNT] = {
-	"input",
-	"output",
-	"unused",
-	"unknown",
-	"func",
-};
 
 /* A few flags used by show_gpio() */
 enum {
@@ -40,22 +33,16 @@ enum {
 	FLAG_SHOW_NEWLINE	= 1 << 2,
 };
 
-static void show_gpio(struct udevice *dev, const char *bank_name, int offset,
-		      int *flagsp)
+static void gpio_get_description(struct udevice *dev, const char *bank_name,
+				 int offset, int *flagsp)
 {
-	struct dm_gpio_ops *ops = gpio_get_ops(dev);
-	int func = GPIOF_UNKNOWN;
 	char buf[80];
 	int ret;
 
-	BUILD_BUG_ON(GPIOF_COUNT != ARRAY_SIZE(gpio_function));
-
-	if (ops->get_function) {
-		ret = ops->get_function(dev, offset);
-		if (ret >= 0 && ret < ARRAY_SIZE(gpio_function))
-			func = ret;
-	}
-	if (!(*flagsp & FLAG_SHOW_ALL) && func == GPIOF_UNUSED)
+	ret = gpio_get_function(dev, offset, NULL);
+	if (ret < 0)
+		goto err;
+	if (!(*flagsp & FLAG_SHOW_ALL) && ret == GPIOF_UNUSED)
 		return;
 	if ((*flagsp & FLAG_SHOW_BANK) && bank_name) {
 		if (*flagsp & FLAG_SHOW_NEWLINE) {
@@ -65,20 +52,15 @@ static void show_gpio(struct udevice *dev, const char *bank_name, int offset,
 		printf("Bank %s:\n", bank_name);
 		*flagsp &= ~FLAG_SHOW_BANK;
 	}
-	*buf = '\0';
-	if (ops->get_state) {
-		ret = ops->get_state(dev, offset, buf, sizeof(buf));
-		if (ret) {
-			puts("<unknown>");
-			return;
-		}
-	} else {
-		sprintf(buf, "%s%u: %8s %d", bank_name, offset,
-			gpio_function[func], ops->get_value(dev, offset));
-	}
 
-	puts(buf);
-	puts("\n");
+	ret = gpio_get_status(dev, offset, buf, sizeof(buf));
+	if (ret)
+		goto err;
+
+	printf("%s\n", buf);
+	return;
+err:
+	printf("Error %d\n", ret);
 }
 
 static int do_gpio_status(bool all, const char *gpio_name)
@@ -101,8 +83,10 @@ static int do_gpio_status(bool all, const char *gpio_name)
 		if (all)
 			flags |= FLAG_SHOW_ALL;
 		bank_name = gpio_get_bank_info(dev, &num_bits);
-		if (!num_bits)
+		if (!num_bits) {
+			debug("GPIO device %s has no bits\n", dev->name);
 			continue;
+		}
 		banklen = bank_name ? strlen(bank_name) : 0;
 
 		if (!gpio_name || !bank_name ||
@@ -113,11 +97,12 @@ static int do_gpio_status(bool all, const char *gpio_name)
 			p = gpio_name + banklen;
 			if (gpio_name && *p) {
 				offset = simple_strtoul(p, NULL, 10);
-				show_gpio(dev, bank_name, offset, &flags);
+				gpio_get_description(dev, bank_name, offset,
+						     &flags);
 			} else {
 				for (offset = 0; offset < num_bits; offset++) {
-					show_gpio(dev, bank_name, offset,
-						  &flags);
+					gpio_get_description(dev, bank_name,
+							     offset, &flags);
 				}
 			}
 		}
diff --git a/common/cmd_io.c b/common/cmd_io.c
index eefac36f87e..c59148f413c 100644
--- a/common/cmd_io.c
+++ b/common/cmd_io.c
@@ -70,8 +70,8 @@ int do_io_iow(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 
 /**************************************************/
 U_BOOT_CMD(iod, 2, 0, do_io_iod,
-	   "IO space display", "[.b, .w, .l] address [# of objects]");
+	   "IO space display", "[.b, .w, .l] address");
 
 U_BOOT_CMD(iow, 3, 0, do_io_iow,
-	   "IO space modify (auto-incrementing address)",
-	   "[.b, .w, .l] address");
+	   "IO space modify",
+	   "[.b, .w, .l] address value");
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index bfca59e351f..0d50dcfe9c1 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -480,6 +480,9 @@ static int do_mem_cp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		if ((count % (64 << 10)) == 0)
 			WATCHDOG_RESET();
 	}
+	unmap_sysmem(buf);
+	unmap_sysmem(src);
+
 	return 0;
 }
 
diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
index b3f7687aee6..cbc107ea501 100644
--- a/common/cmd_scsi.c
+++ b/common/cmd_scsi.c
@@ -10,6 +10,7 @@
  */
 #include <common.h>
 #include <command.h>
+#include <inttypes.h>
 #include <asm/processor.h>
 #include <scsi.h>
 #include <image.h>
@@ -391,7 +392,7 @@ static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt,
 			blks=0;
 		}
 		debug("scsi_read_ext: startblk " LBAF
-		      ", blccnt %x buffer %lx\n",
+		      ", blccnt %x buffer %" PRIXPTR "\n",
 		      start, smallblks, buf_addr);
 		if (scsi_exec(pccb) != true) {
 			scsi_print_error(pccb);
@@ -401,7 +402,7 @@ static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt,
 		buf_addr+=pccb->datalen;
 	} while(blks!=0);
 	debug("scsi_read_ext: end startblk " LBAF
-	      ", blccnt %x buffer %lx\n", start, smallblks, buf_addr);
+	      ", blccnt %x buffer %" PRIXPTR "\n", start, smallblks, buf_addr);
 	return(blkcnt);
 }
 
@@ -445,7 +446,7 @@ static ulong scsi_write(int device, lbaint_t blknr,
 			start += blks;
 			blks = 0;
 		}
-		debug("%s: startblk " LBAF ", blccnt %x buffer %lx\n",
+		debug("%s: startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
 		      __func__, start, smallblks, buf_addr);
 		if (scsi_exec(pccb) != true) {
 			scsi_print_error(pccb);
@@ -454,7 +455,7 @@ static ulong scsi_write(int device, lbaint_t blknr,
 		}
 		buf_addr += pccb->datalen;
 	} while (blks != 0);
-	debug("%s: end startblk " LBAF ", blccnt %x buffer %lx\n",
+	debug("%s: end startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
 	      __func__, start, smallblks, buf_addr);
 	return blkcnt;
 }
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index c60e8d10df6..95a6f89a845 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -8,10 +8,13 @@
 
 #include <common.h>
 #include <div64.h>
+#include <dm.h>
 #include <malloc.h>
+#include <spi.h>
 #include <spi_flash.h>
 
 #include <asm/io.h>
+#include <dm/device-internal.h>
 
 static struct spi_flash *flash;
 
@@ -80,7 +83,12 @@ static int do_spi_flash_probe(int argc, char * const argv[])
 	unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
 	unsigned int mode = CONFIG_SF_DEFAULT_MODE;
 	char *endp;
+#ifdef CONFIG_DM_SPI_FLASH
+	struct udevice *new, *bus_dev;
+	int ret;
+#else
 	struct spi_flash *new;
+#endif
 
 	if (argc >= 2) {
 		cs = simple_strtoul(argv[1], &endp, 0);
@@ -108,6 +116,23 @@ static int do_spi_flash_probe(int argc, char * const argv[])
 			return -1;
 	}
 
+#ifdef CONFIG_DM_SPI_FLASH
+	/* Remove the old device, otherwise probe will just be a nop */
+	ret = spi_find_bus_and_cs(bus, cs, &bus_dev, &new);
+	if (!ret) {
+		device_remove(new);
+		device_unbind(new);
+	}
+	flash = NULL;
+	ret = spi_flash_probe_bus_cs(bus, cs, speed, mode, &new);
+	if (ret) {
+		printf("Failed to initialize SPI flash at %u:%u (error %d)\n",
+		       bus, cs, ret);
+		return 1;
+	}
+
+	flash = new->uclass_priv;
+#else
 	new = spi_flash_probe(bus, cs, speed, mode);
 	if (!new) {
 		printf("Failed to initialize SPI flash at %u:%u\n", bus, cs);
@@ -117,6 +142,7 @@ static int do_spi_flash_probe(int argc, char * const argv[])
 	if (flash)
 		spi_flash_free(flash);
 	flash = new;
+#endif
 
 	return 0;
 }
diff --git a/common/cmd_spi.c b/common/cmd_spi.c
index be5709c6173..64c3ffcf423 100644
--- a/common/cmd_spi.c
+++ b/common/cmd_spi.c
@@ -11,6 +11,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <dm.h>
 #include <errno.h>
 #include <spi.h>
 
@@ -42,19 +43,38 @@ static uchar 		din[MAX_SPI_BYTES];
 static int do_spi_xfer(int bus, int cs)
 {
 	struct spi_slave *slave;
-	int rcode = 0;
-
+	int ret = 0;
+
+#ifdef CONFIG_DM_SPI
+	char name[30], *str;
+	struct udevice *dev;
+
+	snprintf(name, sizeof(name), "generic_%d:%d", bus, cs);
+	str = strdup(name);
+	ret = spi_get_bus_and_cs(bus, cs, 1000000, mode, "spi_generic_drv",
+				 str, &dev, &slave);
+	if (ret)
+		return ret;
+#else
 	slave = spi_setup_slave(bus, cs, 1000000, mode);
 	if (!slave) {
 		printf("Invalid device %d:%d\n", bus, cs);
 		return -EINVAL;
 	}
+#endif
 
-	spi_claim_bus(slave);
-	if (spi_xfer(slave, bitlen, dout, din,
-		     SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
-		printf("Error during SPI transaction\n");
-		rcode = -EIO;
+	ret = spi_claim_bus(slave);
+	if (ret)
+		goto done;
+	ret = spi_xfer(slave, bitlen, dout, din,
+		       SPI_XFER_BEGIN | SPI_XFER_END);
+#ifndef CONFIG_DM_SPI
+	/* We don't get an error code in this case */
+	if (ret)
+		ret = -EIO;
+#endif
+	if (ret) {
+		printf("Error %d during SPI transaction\n", ret);
 	} else {
 		int j;
 
@@ -62,10 +82,13 @@ static int do_spi_xfer(int bus, int cs)
 			printf("%02X", din[j]);
 		printf("\n");
 	}
+done:
 	spi_release_bus(slave);
+#ifndef CONFIG_DM_SPI
 	spi_free_slave(slave);
+#endif
 
-	return rcode;
+	return ret;
 }
 
 /*
diff --git a/common/command.c b/common/command.c
index 746b7e3f0e7..4719f4978ba 100644
--- a/common/command.c
+++ b/common/command.c
@@ -18,13 +18,13 @@
  * for long help messages
  */
 
-int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int
-	      flag, int argc, char * const argv[])
+int _do_help(cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t *cmdtp, int flag,
+	     int argc, char * const argv[])
 {
 	int i;
 	int rcode = 0;
 
-	if (argc == 1) {	/*show list of commands */
+	if (argc == 1) {	/* show list of commands */
 		cmd_tbl_t *cmd_array[cmd_items];
 		int i, j, swaps;
 
@@ -38,8 +38,8 @@ int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int
 		for (i = cmd_items - 1; i > 0; --i) {
 			swaps = 0;
 			for (j = 0; j < i; ++j) {
-				if (strcmp (cmd_array[j]->name,
-					    cmd_array[j + 1]->name) > 0) {
+				if (strcmp(cmd_array[j]->name,
+					   cmd_array[j + 1]->name) > 0) {
 					cmd_tbl_t *tmp;
 					tmp = cmd_array[j];
 					cmd_array[j] = cmd_array[j + 1];
@@ -56,7 +56,7 @@ int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int
 			const char *usage = cmd_array[i]->usage;
 
 			/* allow user abort */
-			if (ctrlc ())
+			if (ctrlc())
 				return 1;
 			if (usage == NULL)
 				continue;
@@ -69,26 +69,23 @@ int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int
 	 * command help (long version)
 	 */
 	for (i = 1; i < argc; ++i) {
-		if ((cmdtp = find_cmd_tbl (argv[i], cmd_start, cmd_items )) != NULL) {
+		cmdtp = find_cmd_tbl(argv[i], cmd_start, cmd_items);
+		if (cmdtp != NULL) {
 			rcode |= cmd_usage(cmdtp);
 		} else {
-			printf ("Unknown command '%s' - try 'help'"
-				" without arguments for list of all"
-				" known commands\n\n", argv[i]
-					);
+			printf("Unknown command '%s' - try 'help' without arguments for list of all known commands\n\n",
+			       argv[i]);
 			rcode = 1;
 		}
 	}
 	return rcode;
 }
 
-/***************************************************************************
- * find command table entry for a command
- */
-cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len)
+/* find command table entry for a command */
+cmd_tbl_t *find_cmd_tbl(const char *cmd, cmd_tbl_t *table, int table_len)
 {
 	cmd_tbl_t *cmdtp;
-	cmd_tbl_t *cmdtp_temp = table;	/*Init value */
+	cmd_tbl_t *cmdtp_temp = table;	/* Init value */
 	const char *p;
 	int len;
 	int n_found = 0;
@@ -101,11 +98,9 @@ cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len)
 	 */
 	len = ((p = strchr(cmd, '.')) == NULL) ? strlen (cmd) : (p - cmd);
 
-	for (cmdtp = table;
-	     cmdtp != table + table_len;
-	     cmdtp++) {
-		if (strncmp (cmd, cmdtp->name, len) == 0) {
-			if (len == strlen (cmdtp->name))
+	for (cmdtp = table; cmdtp != table + table_len; cmdtp++) {
+		if (strncmp(cmd, cmdtp->name, len) == 0) {
+			if (len == strlen(cmdtp->name))
 				return cmdtp;	/* full match */
 
 			cmdtp_temp = cmdtp;	/* abbreviated command ? */
@@ -119,7 +114,7 @@ cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len)
 	return NULL;	/* not found or ambiguous command */
 }
 
-cmd_tbl_t *find_cmd (const char *cmd)
+cmd_tbl_t *find_cmd(const char *cmd)
 {
 	cmd_tbl_t *start = ll_entry_start(cmd_tbl_t, cmd);
 	const int len = ll_entry_count(cmd_tbl_t, cmd);
@@ -138,8 +133,8 @@ int cmd_usage(const cmd_tbl_t *cmdtp)
 		return 1;
 	}
 
-	puts (cmdtp->help);
-	putc ('\n');
+	puts(cmdtp->help);
+	putc('\n');
 #endif	/* CONFIG_SYS_LONGHELP */
 	return 1;
 }
@@ -194,7 +189,7 @@ static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv
 	}
 
 	/* more than one arg or one but the start of the next */
-	if (argc > 1 || (last_char == '\0' || isblank(last_char))) {
+	if (argc > 1 || last_char == '\0' || isblank(last_char)) {
 		cmdtp = find_cmd(argv[0]);
 		if (cmdtp == NULL || cmdtp->complete == NULL) {
 			cmdv[0] = NULL;
@@ -345,7 +340,8 @@ int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp)
 	argc = make_argv(tmp_buf, sizeof(argv)/sizeof(argv[0]), argv);
 
 	/* do the completion and return the possible completions */
-	i = complete_cmdv(argc, argv, last_char, sizeof(cmdv)/sizeof(cmdv[0]), cmdv);
+	i = complete_cmdv(argc, argv, last_char,
+			  sizeof(cmdv) / sizeof(cmdv[0]), cmdv);
 
 	/* no match; bell and out */
 	if (i == 0) {
@@ -365,7 +361,7 @@ int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp)
 		len = strlen(s);
 		sep = " ";
 		seplen = 1;
-	} else if (i > 1 && (j = find_common_prefix(cmdv)) != 0) {	/* more */
+	} else if (i > 1 && (j = find_common_prefix(cmdv)) != 0) { /* more */
 		k = strlen(argv[argc - 1]);
 		j -= k;
 		if (j > 0) {
@@ -414,7 +410,7 @@ int cmd_get_data_size(char* arg, int default_size)
 	 */
 	int len = strlen(arg);
 	if (len > 2 && arg[len-2] == '.') {
-		switch(arg[len-1]) {
+		switch (arg[len-1]) {
 		case 'b':
 			return 1;
 		case 'w':
@@ -448,10 +444,10 @@ void fixup_cmdtable(cmd_tbl_t *cmdtp, int size)
 	for (i = 0; i < size; i++) {
 		ulong addr;
 
-		addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
+		addr = (ulong)(cmdtp->cmd) + gd->reloc_off;
 #if DEBUG_COMMANDS
 		printf("Command \"%s\": 0x%08lx => 0x%08lx\n",
-		       cmdtp->name, (ulong) (cmdtp->cmd), addr);
+		       cmdtp->name, (ulong)(cmdtp->cmd), addr);
 #endif
 		cmdtp->cmd =
 			(int (*)(struct cmd_tbl_s *, int, int, char * const []))addr;
diff --git a/common/console.c b/common/console.c
index 5a2f4116002..4695386a332 100644
--- a/common/console.c
+++ b/common/console.c
@@ -7,6 +7,7 @@
 
 #include <common.h>
 #include <stdarg.h>
+#include <iomux.h>
 #include <malloc.h>
 #include <os.h>
 #include <serial.h>
@@ -621,7 +622,7 @@ inline void dbg(const char *fmt, ...)
 
 }
 #else
-inline void dbg(const char *fmt, ...)
+static inline void dbg(const char *fmt, ...)
 {
 }
 #endif
diff --git a/common/cros_ec.c b/common/cros_ec.c
index b8ce1b581aa..bb299bccfff 100644
--- a/common/cros_ec.c
+++ b/common/cros_ec.c
@@ -10,25 +10,44 @@
 
 #include <common.h>
 #include <cros_ec.h>
+#include <dm.h>
+#include <errno.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_DM_CROS_EC
 struct local_info {
 	struct cros_ec_dev *cros_ec_dev;	/* Pointer to cros_ec device */
 	int cros_ec_err;			/* Error for cros_ec, 0 if ok */
 };
 
 static struct local_info local;
+#endif
 
 struct cros_ec_dev *board_get_cros_ec_dev(void)
 {
+#ifdef CONFIG_DM_CROS_EC
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_CROS_EC, 0, &dev);
+	if (ret) {
+		debug("%s: Error %d\n", __func__, ret);
+		return NULL;
+	}
+	return dev->uclass_priv;
+#else
 	return local.cros_ec_dev;
+#endif
 }
 
 static int board_init_cros_ec_devices(const void *blob)
 {
+#ifndef CONFIG_DM_CROS_EC
 	local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
 	if (local.cros_ec_err)
 		return -1;  /* Will report in board_late_init() */
+#endif
 
 	return 0;
 }
@@ -40,5 +59,16 @@ int cros_ec_board_init(void)
 
 int cros_ec_get_error(void)
 {
+#ifdef CONFIG_DM_CROS_EC
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_CROS_EC, 0, &dev);
+	if (ret && ret != -ENODEV)
+		return ret;
+
+	return 0;
+#else
 	return local.cros_ec_err;
+#endif
 }
diff --git a/common/env_nand.c b/common/env_nand.c
index 5a734a9321a..749605fe3fa 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -124,7 +124,7 @@ int env_init(void)
  * The legacy NAND code saved the environment in the first NAND device i.e.,
  * nand_dev_desc + 0. This is also the behaviour using the new NAND code.
  */
-int writeenv(size_t offset, u_char *buf)
+static int writeenv(size_t offset, u_char *buf)
 {
 	size_t end = offset + CONFIG_ENV_RANGE;
 	size_t amount_saved = 0;
@@ -233,7 +233,7 @@ int saveenv(void)
 }
 #endif /* CMD_SAVEENV */
 
-int readenv(size_t offset, u_char *buf)
+static int readenv(size_t offset, u_char *buf)
 {
 	size_t end = offset + CONFIG_ENV_RANGE;
 	size_t amount_loaded = 0;
diff --git a/common/env_sf.c b/common/env_sf.c
index 37ab13ae178..5e3729c2c2d 100644
--- a/common/env_sf.c
+++ b/common/env_sf.c
@@ -12,6 +12,7 @@
 #include <common.h>
 #include <environment.h>
 #include <malloc.h>
+#include <spi.h>
 #include <spi_flash.h>
 #include <search.h>
 #include <errno.h>
diff --git a/common/exports.c b/common/exports.c
index b97ca48307d..88fcfc8cb6f 100644
--- a/common/exports.c
+++ b/common/exports.c
@@ -27,10 +27,12 @@ unsigned long get_version(void)
 # define i2c_write         dummy
 # define i2c_read          dummy
 #endif
-#ifndef CONFIG_CMD_SPI
+#if !defined(CONFIG_CMD_SPI) || defined(CONFIG_DM_SPI)
 # define spi_init          dummy
 # define spi_setup_slave   dummy
 # define spi_free_slave    dummy
+#endif
+#ifndef CONFIG_CMD_SPI
 # define spi_claim_bus     dummy
 # define spi_release_bus   dummy
 # define spi_xfer          dummy
diff --git a/common/image-android.c b/common/image-android.c
index 6ded7e2c97e..59079fc32b5 100644
--- a/common/image-android.c
+++ b/common/image-android.c
@@ -7,9 +7,26 @@
 #include <common.h>
 #include <image.h>
 #include <android_image.h>
+#include <malloc.h>
+#include <errno.h>
 
 static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1];
 
+/**
+ * android_image_get_kernel() - processes kernel part of Android boot images
+ * @hdr:	Pointer to image header, which is at the start
+ *			of the image.
+ * @verify:	Checksum verification flag. Currently unimplemented.
+ * @os_data:	Pointer to a ulong variable, will hold os data start
+ *			address.
+ * @os_len:	Pointer to a ulong variable, will hold os data length.
+ *
+ * This function returns the os image's start address and length. Also,
+ * it appends the kernel command line to the bootargs env variable.
+ *
+ * Return: Zero, os start address and length on success,
+ *		otherwise on failure.
+ */
 int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
 			     ulong *os_data, ulong *os_len)
 {
@@ -25,16 +42,32 @@ int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
 
 	printf("Kernel load addr 0x%08x size %u KiB\n",
 	       hdr->kernel_addr, DIV_ROUND_UP(hdr->kernel_size, 1024));
-	strncpy(andr_tmp_str, hdr->cmdline, ANDR_BOOT_ARGS_SIZE);
-	andr_tmp_str[ANDR_BOOT_ARGS_SIZE] = '\0';
-	if (strlen(andr_tmp_str)) {
-		printf("Kernel command line: %s\n", andr_tmp_str);
-		setenv("bootargs", andr_tmp_str);
+
+	int len = 0;
+	if (*hdr->cmdline) {
+		printf("Kernel command line: %s\n", hdr->cmdline);
+		len += strlen(hdr->cmdline);
+	}
+
+	char *bootargs = getenv("bootargs");
+	if (bootargs)
+		len += strlen(bootargs);
+
+	char *newbootargs = malloc(len + 2);
+	if (!newbootargs) {
+		puts("Error: malloc in android_image_get_kernel failed!\n");
+		return -ENOMEM;
+	}
+	*newbootargs = '\0';
+
+	if (bootargs) {
+		strcpy(newbootargs, bootargs);
+		strcat(newbootargs, " ");
 	}
-	if (hdr->ramdisk_size)
-		printf("RAM disk load addr 0x%08x size %u KiB\n",
-		       hdr->ramdisk_addr,
-		       DIV_ROUND_UP(hdr->ramdisk_size, 1024));
+	if (*hdr->cmdline)
+		strcat(newbootargs, hdr->cmdline);
+
+	setenv("bootargs", newbootargs);
 
 	if (os_data) {
 		*os_data = (ulong)hdr;
@@ -52,17 +85,18 @@ int android_image_check_header(const struct andr_img_hdr *hdr)
 
 ulong android_image_get_end(const struct andr_img_hdr *hdr)
 {
-	u32 size = 0;
+	ulong end;
 	/*
 	 * The header takes a full page, the remaining components are aligned
 	 * on page boundary
 	 */
-	size += hdr->page_size;
-	size += ALIGN(hdr->kernel_size, hdr->page_size);
-	size += ALIGN(hdr->ramdisk_size, hdr->page_size);
-	size += ALIGN(hdr->second_size, hdr->page_size);
+	end = (ulong)hdr;
+	end += hdr->page_size;
+	end += ALIGN(hdr->kernel_size, hdr->page_size);
+	end += ALIGN(hdr->ramdisk_size, hdr->page_size);
+	end += ALIGN(hdr->second_size, hdr->page_size);
 
-	return size;
+	return end;
 }
 
 ulong android_image_get_kload(const struct andr_img_hdr *hdr)
@@ -75,6 +109,10 @@ int android_image_get_ramdisk(const struct andr_img_hdr *hdr,
 {
 	if (!hdr->ramdisk_size)
 		return -1;
+
+	printf("RAM disk load addr 0x%08x size %u KiB\n",
+	       hdr->ramdisk_addr, DIV_ROUND_UP(hdr->ramdisk_size, 1024));
+
 	*rd_data = (unsigned long)hdr;
 	*rd_data += hdr->page_size;
 	*rd_data += ALIGN(hdr->kernel_size, hdr->page_size);
diff --git a/common/image-fit.c b/common/image-fit.c
index 255c4cac9ca..4ffc5aaa512 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1114,7 +1114,8 @@ int fit_image_check_arch(const void *fit, int noffset, uint8_t arch)
 
 	if (fit_image_get_arch(fit, noffset, &image_arch))
 		return 0;
-	return (arch == image_arch);
+	return (arch == image_arch) ||
+		(arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64);
 }
 
 /**
@@ -1434,7 +1435,7 @@ void fit_conf_print(const void *fit, int noffset, const char *p)
 		printf("%s  FDT:          %s\n", p, uname);
 }
 
-int fit_image_select(const void *fit, int rd_noffset, int verify)
+static int fit_image_select(const void *fit, int rd_noffset, int verify)
 {
 	fit_image_print(fit, rd_noffset, "   ");
 
@@ -1497,6 +1498,8 @@ static const char *fit_get_image_type_property(int type)
 		return FIT_KERNEL_PROP;
 	case IH_TYPE_RAMDISK:
 		return FIT_RAMDISK_PROP;
+	case IH_TYPE_X86_SETUP:
+		return FIT_SETUP_PROP;
 	}
 
 	return "unknown";
@@ -1591,7 +1594,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
 	}
 
 	bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH);
-#ifndef USE_HOSTCC
+#if !defined(USE_HOSTCC) && !defined(CONFIG_SANDBOX)
 	if (!fit_image_check_target_arch(fit, noffset)) {
 		puts("Unsupported Architecture\n");
 		bootstage_error(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH);
@@ -1693,3 +1696,23 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
 
 	return noffset;
 }
+
+int boot_get_setup_fit(bootm_headers_t *images, uint8_t arch,
+			ulong *setup_start, ulong *setup_len)
+{
+	int noffset;
+	ulong addr;
+	ulong len;
+	int ret;
+
+	addr = map_to_sysmem(images->fit_hdr_os);
+	noffset = fit_get_node_from_config(images, FIT_SETUP_PROP, addr);
+	if (noffset < 0)
+		return noffset;
+
+	ret = fit_image_load(images, addr, NULL, NULL, arch,
+			     IH_TYPE_X86_SETUP, BOOTSTAGE_ID_FIT_SETUP_START,
+			     FIT_LOAD_REQUIRED, setup_start, &len);
+
+	return ret;
+}
diff --git a/common/image.c b/common/image.c
index 085771c7639..b75a5ce29a6 100644
--- a/common/image.c
+++ b/common/image.c
@@ -85,6 +85,7 @@ static const table_entry_t uimage_arch[] = {
 	{	IH_ARCH_SANDBOX,	"sandbox",	"Sandbox",	},
 	{	IH_ARCH_ARM64,		"arm64",	"AArch64",	},
 	{	IH_ARCH_ARC,		"arc",		"ARC",		},
+	{	IH_ARCH_X86_64,		"x86_64",	"AMD x86_64",	},
 	{	-1,			"",		"",		},
 };
 
@@ -143,6 +144,7 @@ static const table_entry_t uimage_type[] = {
 	{	IH_TYPE_UBLIMAGE,   "ublimage",   "Davinci UBL image",},
 	{	IH_TYPE_MXSIMAGE,   "mxsimage",   "Freescale MXS Boot Image",},
 	{	IH_TYPE_ATMELIMAGE, "atmelimage", "ATMEL ROM-Boot Image",},
+	{	IH_TYPE_X86_SETUP,  "x86_setup",  "x86 setup.bin",    },
 	{	-1,		    "",		  "",			},
 };
 
@@ -1009,7 +1011,8 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
 		image_multi_getimg(images->legacy_hdr_os, 1, &rd_data, &rd_len);
 	}
 #ifdef CONFIG_ANDROID_BOOT_IMAGE
-	else if ((genimg_get_format(images) == IMAGE_FORMAT_ANDROID) &&
+	else if ((genimg_get_format((void *)images->os.start)
+			== IMAGE_FORMAT_ANDROID) &&
 		 (!android_image_get_ramdisk((void *)images->os.start,
 		 &rd_data, &rd_len))) {
 		/* empty */
@@ -1136,6 +1139,16 @@ error:
 }
 #endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */
 
+int boot_get_setup(bootm_headers_t *images, uint8_t arch,
+		   ulong *setup_start, ulong *setup_len)
+{
+#if defined(CONFIG_FIT)
+	return boot_get_setup_fit(images, arch, setup_start, setup_len);
+#else
+	return -ENOENT;
+#endif
+}
+
 #ifdef CONFIG_SYS_BOOT_GET_CMDLINE
 /**
  * boot_get_cmdline - allocate and initialize kernel cmdline
diff --git a/common/lcd.c b/common/lcd.c
index 217ec9dbd2e..787d80e3cbe 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -33,7 +33,6 @@
 
 #if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
 	defined(CONFIG_CPU_MONAHANS)
-#define CONFIG_CPU_PXA
 #include <asm/byteorder.h>
 #endif
 
@@ -1023,7 +1022,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 
 	switch (bmp_bpix) {
 	case 1: /* pass through */
-	case 8:
+	case 8: {
 #ifdef CONFIG_LCD_BMP_RLE8
 		u32 compression = get_unaligned_le32(&bmp->header.compression);
 		if (compression == BMP_BI_RLE8) {
@@ -1056,7 +1055,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 			fb -= byte_width + lcd_line_length;
 		}
 		break;
-
+	}
 #if defined(CONFIG_BMP_16BPP)
 	case 16:
 		for (i = 0; i < height; ++i) {
diff --git a/common/menu.c b/common/menu.c
index 94afeb29009..e81c074f36c 100644
--- a/common/menu.c
+++ b/common/menu.c
@@ -105,12 +105,9 @@ static inline void *menu_item_destroy(struct menu *m,
 	return NULL;
 }
 
-void __menu_display_statusline(struct menu *m)
+__weak void menu_display_statusline(struct menu *m)
 {
-	return;
 }
-void menu_display_statusline(struct menu *m)
-	__attribute__ ((weak, alias("__menu_display_statusline")));
 
 /*
  * Display a menu so the user can make a choice of an item. First display its
diff --git a/common/modem.c b/common/modem.c
index be54b101101..96b10648d86 100644
--- a/common/modem.c
+++ b/common/modem.c
@@ -19,7 +19,7 @@ static inline void mdm_readline(char *buf, int bufsiz)
 	for(;;) {
 		c = serial_getc();
 
-		/*		dbg("(%c)", c); */
+		debug("(%c)", c);
 
 		switch(c) {
 		case '\r':
@@ -40,7 +40,6 @@ static inline void mdm_readline(char *buf, int bufsiz)
 	}
 }
 
-extern void  dbg(const char *fmt, ...);
 int mdm_init (void)
 {
 	char env_str[16];
@@ -66,15 +65,15 @@ int mdm_init (void)
 			serial_puts("\n");
 			for(;;) {
 				mdm_readline(console_buffer, CONFIG_SYS_CBSIZE);
-				dbg("ini%d: [%s]", i, console_buffer);
+				debug("ini%d: [%s]", i, console_buffer);
 
 				if ((strcmp(console_buffer, "OK") == 0) ||
 					(strcmp(console_buffer, "ERROR") == 0)) {
-					dbg("ini%d: cmd done", i);
+					debug("ini%d: cmd done", i);
 					break;
 				} else /* in case we are originating call ... */
 					if (strncmp(console_buffer, "CONNECT", 7) == 0) {
-						dbg("ini%d: connect", i);
+						debug("ini%d: connect", i);
 						return 0;
 					}
 			}
@@ -90,9 +89,9 @@ int mdm_init (void)
 	for(;i > 1;) { /* if 'i' > 1 - wait for connection
 				  message from modem */
 		mdm_readline(console_buffer, CONFIG_SYS_CBSIZE);
-		dbg("ini_f: [%s]", console_buffer);
+		debug("ini_f: [%s]", console_buffer);
 		if (strncmp(console_buffer, "CONNECT", 7) == 0) {
-			dbg("ini_f: connected");
+			debug("ini_f: connected");
 			return 0;
 		}
 	}
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 64569c2cc6d..10a45899696 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
 obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
 obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
 obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
+obj-$(CONFIG_SPL_EXT_SUPPORT) += spl_ext.o
 obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o
 endif
diff --git a/common/spl/spl.c b/common/spl/spl.c
index b16664f8454..d85bab3928c 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -23,6 +23,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
 #endif
 #ifndef CONFIG_SYS_MONITOR_LEN
+/* Unknown U-Boot size, let's assume it will not be more than 200 KB */
 #define CONFIG_SYS_MONITOR_LEN	(200 * 1024)
 #endif
 
@@ -92,7 +93,6 @@ void spl_parse_image_header(const struct image_header *header)
 		/* Signature not found - assume u-boot.bin */
 		debug("mkimage signature not found - ih_magic = %x\n",
 			header->ih_magic);
-		/* Let's assume U-Boot will not be more than 200 KB */
 		spl_image.size = CONFIG_SYS_MONITOR_LEN;
 		spl_image.entry_point = CONFIG_SYS_UBOOT_START;
 		spl_image.load_addr = CONFIG_SYS_TEXT_BASE;
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
new file mode 100644
index 00000000000..d9eba5aef3a
--- /dev/null
+++ b/common/spl/spl_ext.c
@@ -0,0 +1,139 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/u-boot.h>
+#include <ext4fs.h>
+#include <image.h>
+
+#ifdef CONFIG_SPL_EXT_SUPPORT
+int spl_load_image_ext(block_dev_desc_t *block_dev,
+						int partition,
+						const char *filename)
+{
+	s32 err;
+	struct image_header *header;
+	int filelen;
+	disk_partition_t part_info = {};
+
+	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
+						sizeof(struct image_header));
+
+	if (get_partition_info(block_dev,
+			       partition, &part_info)) {
+		printf("spl: no partition table found\n");
+		return -1;
+	}
+
+	ext4fs_set_blk_dev(block_dev, &part_info);
+
+	err = ext4fs_mount(0);
+	if (!err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+		printf("%s: ext4fs mount err - %d\n", __func__, err);
+#endif
+		goto end;
+	}
+
+	filelen = err = ext4fs_open(filename);
+	if (err < 0) {
+		puts("spl: ext4fs_open failed\n");
+		goto end;
+	}
+	err = ext4fs_read((char *)header, sizeof(struct image_header));
+	if (err <= 0) {
+		puts("spl: ext4fs_read failed\n");
+		goto end;
+	}
+
+	spl_parse_image_header(header);
+
+	err = ext4fs_read((char *)spl_image.load_addr, filelen);
+
+end:
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+	if (err <= 0)
+		printf("%s: error reading image %s, err - %d\n",
+		       __func__, filename, err);
+#endif
+
+	return err <= 0;
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition)
+{
+	int err;
+	int filelen;
+	disk_partition_t part_info = {};
+	__maybe_unused char *file;
+
+	if (get_partition_info(block_dev,
+			       partition, &part_info)) {
+		printf("spl: no partition table found\n");
+		return -1;
+	}
+
+	ext4fs_set_blk_dev(block_dev, &part_info);
+
+	err = ext4fs_mount(0);
+	if (!err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+		printf("%s: ext4fs mount err - %d\n", __func__, err);
+#endif
+		return -1;
+	}
+
+#if defined(CONFIG_SPL_ENV_SUPPORT) && defined(CONFIG_SPL_OS_BOOT)
+	file = getenv("falcon_args_file");
+	if (file) {
+		filelen = err = ext4fs_open(file);
+		if (err < 0) {
+			puts("spl: ext4fs_open failed\n");
+			goto defaults;
+		}
+		err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen);
+		if (err <= 0) {
+			printf("spl: error reading image %s, err - %d, falling back to default\n",
+			       file, err);
+			goto defaults;
+		}
+		file = getenv("falcon_image_file");
+		if (file) {
+			err = spl_load_image_ext(block_dev, partition, file);
+			if (err != 0) {
+				puts("spl: falling back to default\n");
+				goto defaults;
+			}
+
+			return 0;
+		} else {
+			puts("spl: falcon_image_file not set in environment, falling back to default\n");
+		}
+	} else {
+		puts("spl: falcon_args_file not set in environment, falling back to default\n");
+	}
+
+defaults:
+#endif
+
+	filelen = err = ext4fs_open(CONFIG_SPL_FS_LOAD_ARGS_NAME);
+	if (err < 0)
+		puts("spl: ext4fs_open failed\n");
+
+	err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen);
+	if (err <= 0) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+		printf("%s: error reading image %s, err - %d\n",
+		       __func__, CONFIG_SPL_FS_LOAD_ARGS_NAME, err);
+#endif
+		return -1;
+	}
+
+	return spl_load_image_ext(block_dev, partition,
+			CONFIG_SPL_FS_LOAD_KERNEL_NAME);
+}
+#endif
+#endif
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index 56be9438814..350f7d9fd68 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -30,7 +30,7 @@ static int spl_register_fat_device(block_dev_desc_t *block_dev, int partition)
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
 		printf("%s: fat register err - %d\n", __func__, err);
 #endif
-		hang();
+		return err;
 	}
 
 	fat_registered = 1;
@@ -106,18 +106,18 @@ int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition)
 defaults:
 #endif
 
-	err = file_fat_read(CONFIG_SPL_FAT_LOAD_ARGS_NAME,
+	err = file_fat_read(CONFIG_SPL_FS_LOAD_ARGS_NAME,
 			    (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
 	if (err <= 0) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
 		printf("%s: error reading image %s, err - %d\n",
-		       __func__, CONFIG_SPL_FAT_LOAD_ARGS_NAME, err);
+		       __func__, CONFIG_SPL_FS_LOAD_ARGS_NAME, err);
 #endif
 		return -1;
 	}
 
 	return spl_load_image_fat(block_dev, partition,
-			CONFIG_SPL_FAT_LOAD_KERNEL_NAME);
+			CONFIG_SPL_FS_LOAD_KERNEL_NAME);
 }
 #endif
 #endif
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index fa6f891bc80..ee71f793a67 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -100,17 +100,31 @@ void spl_mmc_load_image(void)
 #endif
 		err = mmc_load_image_raw(mmc,
 			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+	} else if (boot_mode == MMCSD_MODE_FS) {
+		debug("boot mode - FS\n");
 #ifdef CONFIG_SPL_FAT_SUPPORT
-	} else if (boot_mode == MMCSD_MODE_FAT) {
-		debug("boot mode - FAT\n");
 #ifdef CONFIG_SPL_OS_BOOT
 		if (spl_start_uboot() || spl_load_image_fat_os(&mmc->block_dev,
-								CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION))
+								CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION))
 #endif
 		err = spl_load_image_fat(&mmc->block_dev,
-					CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION,
-					CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
+					CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION,
+					CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+		if(err)
+#endif /* CONFIG_SPL_FAT_SUPPORT */
+		{
+#ifdef CONFIG_SPL_EXT_SUPPORT
+#ifdef CONFIG_SPL_OS_BOOT
+		if (spl_start_uboot() || spl_load_image_ext_os(&mmc->block_dev,
+								CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION))
 #endif
+		err = spl_load_image_ext(&mmc->block_dev,
+					CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION,
+					CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+#endif /* CONFIG_SPL_EXT_SUPPORT */
+		}
+#endif /* defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) */
 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 	} else if (boot_mode == MMCSD_MODE_EMMCBOOT) {
 		/*
diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c
index 12e16d96039..aeea79315e2 100644
--- a/common/spl/spl_sata.c
+++ b/common/spl/spl_sata.c
@@ -42,7 +42,7 @@ void spl_sata_load_image(void)
 #endif
 	err = spl_load_image_fat(stor_dev,
 				CONFIG_SYS_SATA_FAT_BOOT_PARTITION,
-				CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
+				CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
 	if (err) {
 		puts("Error loading sata device\n");
 		hang();
diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c
index 53a9043795f..c81672b7981 100644
--- a/common/spl/spl_usb.c
+++ b/common/spl/spl_usb.c
@@ -49,7 +49,7 @@ void spl_usb_load_image(void)
 #endif
 		err = spl_load_image_fat(stor_dev,
 				CONFIG_SYS_USB_FAT_BOOT_PARTITION,
-				CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
+				CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
 
 		if (err) {
 			puts("Error loading USB device\n");
diff --git a/common/stdio.c b/common/stdio.c
index 82328150cba..adbfc890dd4 100644
--- a/common/stdio.c
+++ b/common/stdio.c
@@ -39,39 +39,39 @@ char *stdio_names[MAX_FILES] = { "stdin", "stdout", "stderr" };
 #endif
 
 #ifdef CONFIG_SYS_DEVICE_NULLDEV
-void nulldev_putc(struct stdio_dev *dev, const char c)
+static void nulldev_putc(struct stdio_dev *dev, const char c)
 {
 	/* nulldev is empty! */
 }
 
-void nulldev_puts(struct stdio_dev *dev, const char *s)
+static void nulldev_puts(struct stdio_dev *dev, const char *s)
 {
 	/* nulldev is empty! */
 }
 
-int nulldev_input(struct stdio_dev *dev)
+static int nulldev_input(struct stdio_dev *dev)
 {
 	/* nulldev is empty! */
 	return 0;
 }
 #endif
 
-void stdio_serial_putc(struct stdio_dev *dev, const char c)
+static void stdio_serial_putc(struct stdio_dev *dev, const char c)
 {
 	serial_putc(c);
 }
 
-void stdio_serial_puts(struct stdio_dev *dev, const char *s)
+static void stdio_serial_puts(struct stdio_dev *dev, const char *s)
 {
 	serial_puts(s);
 }
 
-int stdio_serial_getc(struct stdio_dev *dev)
+static int stdio_serial_getc(struct stdio_dev *dev)
 {
 	return serial_getc();
 }
 
-int stdio_serial_tstc(struct stdio_dev *dev)
+static int stdio_serial_tstc(struct stdio_dev *dev)
 {
 	return serial_tstc();
 }
@@ -197,6 +197,7 @@ int stdio_deregister_dev(struct stdio_dev *dev, int force)
 	}
 
 	list_del(&(dev->list));
+	free(dev);
 
 	/* reassign Device list */
 	list_for_each(pos, &(devs.list)) {
diff --git a/common/usb.c b/common/usb.c
index bd0f8d5d180..7d33a0f0869 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -927,7 +927,6 @@ int usb_new_device(struct usb_device *dev)
 	 * thread_id=5729457&forum_id=5398
 	 */
 	__maybe_unused struct usb_device_descriptor *desc;
-	int port = -1;
 	struct usb_device *parent = dev->parent;
 	unsigned short portstatus;
 
@@ -965,24 +964,10 @@ int usb_new_device(struct usb_device *dev)
 #endif
 
 	if (parent) {
-		int j;
-
-		/* find the port number we're at */
-		for (j = 0; j < parent->maxchild; j++) {
-			if (parent->children[j] == dev) {
-				port = j;
-				break;
-			}
-		}
-		if (port < 0) {
-			printf("usb_new_device:cannot locate device's port.\n");
-			return 1;
-		}
-
 		/* reset the port for the second time */
-		err = hub_port_reset(dev->parent, port, &portstatus);
+		err = hub_port_reset(dev->parent, dev->portnr - 1, &portstatus);
 		if (err < 0) {
-			printf("\n     Couldn't reset port %i\n", port);
+			printf("\n     Couldn't reset port %i\n", dev->portnr);
 			return 1;
 		}
 	}
diff --git a/common/usb_hub.c b/common/usb_hub.c
index c416e5e0b31..0f1eab44864 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -86,50 +86,11 @@ static void usb_hub_power_on(struct usb_hub_device *hub)
 	int i;
 	struct usb_device *dev;
 	unsigned pgood_delay = hub->desc.bPwrOn2PwrGood * 2;
-	ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
-	unsigned short portstatus;
-	int ret;
 
 	dev = hub->pusb_dev;
 
-	/*
-	 * Enable power to the ports:
-	 * Here we Power-cycle the ports: aka,
-	 * turning them off and turning on again.
-	 */
 	debug("enabling power on all ports\n");
 	for (i = 0; i < dev->maxchild; i++) {
-		usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_POWER);
-		debug("port %d returns %lX\n", i + 1, dev->status);
-	}
-
-	/* Wait at least 2*bPwrOn2PwrGood for PP to change */
-	mdelay(pgood_delay);
-
-	for (i = 0; i < dev->maxchild; i++) {
-		ret = usb_get_port_status(dev, i + 1, portsts);
-		if (ret < 0) {
-			debug("port %d: get_port_status failed\n", i + 1);
-			continue;
-		}
-
-		/*
-		 * Check to confirm the state of Port Power:
-		 * xHCI says "After modifying PP, s/w shall read
-		 * PP and confirm that it has reached the desired state
-		 * before modifying it again, undefined behavior may occur
-		 * if this procedure is not followed".
-		 * EHCI doesn't say anything like this, but no harm in keeping
-		 * this.
-		 */
-		portstatus = le16_to_cpu(portsts->wPortStatus);
-		if (portstatus & (USB_PORT_STAT_POWER << 1)) {
-			debug("port %d: Port power change failed\n", i + 1);
-			continue;
-		}
-	}
-
-	for (i = 0; i < dev->maxchild; i++) {
 		usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER);
 		debug("port %d returns %lX\n", i + 1, dev->status);
 	}
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index fdc083c70cf..bc7145ea79d 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -99,6 +99,11 @@ static const unsigned char usb_kbd_arrow[] = {
 #define USB_KBD_BOOT_REPORT_SIZE 8
 
 struct usb_kbd_pdata {
+	unsigned long	intpipe;
+	int		intpktsize;
+	int		intinterval;
+	struct int_queue *intq;
+
 	uint32_t	repeat_delay;
 
 	uint32_t	usb_in_pointer;
@@ -116,32 +121,6 @@ extern int __maybe_unused net_busy_flag;
 /* The period of time between two calls of usb_kbd_testc(). */
 static unsigned long __maybe_unused kbd_testc_tms;
 
-/* Generic keyboard event polling. */
-void usb_kbd_generic_poll(void)
-{
-	struct stdio_dev *dev;
-	struct usb_device *usb_kbd_dev;
-	struct usb_kbd_pdata *data;
-	struct usb_interface *iface;
-	struct usb_endpoint_descriptor *ep;
-	int pipe;
-	int maxp;
-
-	/* Get the pointer to USB Keyboard device pointer */
-	dev = stdio_get_by_name(DEVNAME);
-	usb_kbd_dev = (struct usb_device *)dev->priv;
-	data = usb_kbd_dev->privptr;
-	iface = &usb_kbd_dev->config.if_desc[0];
-	ep = &iface->ep_desc[0];
-	pipe = usb_rcvintpipe(usb_kbd_dev, ep->bEndpointAddress);
-
-	/* Submit a interrupt transfer request */
-	maxp = usb_maxpacket(usb_kbd_dev, pipe);
-	usb_submit_int_msg(usb_kbd_dev, pipe, data->new,
-		min(maxp, USB_KBD_BOOT_REPORT_SIZE),
-		ep->bInterval);
-}
-
 /* Puts character in the queue and sets up the in and out pointer. */
 static void usb_kbd_put_queue(struct usb_kbd_pdata *data, char c)
 {
@@ -331,23 +310,11 @@ static int usb_kbd_irq(struct usb_device *dev)
 static inline void usb_kbd_poll_for_event(struct usb_device *dev)
 {
 #if	defined(CONFIG_SYS_USB_EVENT_POLL)
-	struct usb_interface *iface;
-	struct usb_endpoint_descriptor *ep;
-	struct usb_kbd_pdata *data;
-	int pipe;
-	int maxp;
-
-	/* Get the pointer to USB Keyboard device pointer */
-	data = dev->privptr;
-	iface = &dev->config.if_desc[0];
-	ep = &iface->ep_desc[0];
-	pipe = usb_rcvintpipe(dev, ep->bEndpointAddress);
+	struct usb_kbd_pdata *data = dev->privptr;
 
 	/* Submit a interrupt transfer request */
-	maxp = usb_maxpacket(dev, pipe);
-	usb_submit_int_msg(dev, pipe, &data->new[0],
-		min(maxp, USB_KBD_BOOT_REPORT_SIZE),
-		ep->bInterval);
+	usb_submit_int_msg(dev, data->intpipe, &data->new[0], data->intpktsize,
+			   data->intinterval);
 
 	usb_kbd_irq_worker(dev);
 #elif	defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP)
@@ -358,6 +325,15 @@ static inline void usb_kbd_poll_for_event(struct usb_device *dev)
 		       1, 0, data->new, USB_KBD_BOOT_REPORT_SIZE);
 	if (memcmp(data->old, data->new, USB_KBD_BOOT_REPORT_SIZE))
 		usb_kbd_irq_worker(dev);
+#elif	defined(CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE)
+	struct usb_kbd_pdata *data = dev->privptr;
+	if (poll_int_queue(dev, data->intq)) {
+		usb_kbd_irq_worker(dev);
+		/* We've consumed all queued int packets, create new */
+		destroy_int_queue(dev, data->intq);
+		data->intq = create_int_queue(dev, data->intpipe, 1,
+				      USB_KBD_BOOT_REPORT_SIZE, data->new);
+	}
 #endif
 }
 
@@ -415,7 +391,6 @@ static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum)
 	struct usb_interface *iface;
 	struct usb_endpoint_descriptor *ep;
 	struct usb_kbd_pdata *data;
-	int pipe, maxp;
 
 	if (dev->descriptor.bNumConfigurations != 1)
 		return 0;
@@ -464,8 +439,10 @@ static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum)
 	/* Set IRQ handler */
 	dev->irq_handle = usb_kbd_irq;
 
-	pipe = usb_rcvintpipe(dev, ep->bEndpointAddress);
-	maxp = usb_maxpacket(dev, pipe);
+	data->intpipe = usb_rcvintpipe(dev, ep->bEndpointAddress);
+	data->intpktsize = min(usb_maxpacket(dev, data->intpipe),
+			       USB_KBD_BOOT_REPORT_SIZE);
+	data->intinterval = ep->bInterval;
 
 	/* We found a USB Keyboard, install it. */
 	usb_set_protocol(dev, iface->desc.bInterfaceNumber, 0);
@@ -474,9 +451,14 @@ static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum)
 	usb_set_idle(dev, iface->desc.bInterfaceNumber, REPEAT_RATE, 0);
 
 	debug("USB KBD: enable interrupt pipe...\n");
-	if (usb_submit_int_msg(dev, pipe, data->new,
-			       min(maxp, USB_KBD_BOOT_REPORT_SIZE),
-			       ep->bInterval) < 0) {
+#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
+	data->intq = create_int_queue(dev, data->intpipe, 1,
+				      USB_KBD_BOOT_REPORT_SIZE, data->new);
+	if (!data->intq) {
+#else
+	if (usb_submit_int_msg(dev, data->intpipe, data->new, data->intpktsize,
+			       data->intinterval) < 0) {
+#endif
 		printf("Failed to get keyboard state from device %04x:%04x\n",
 		       dev->descriptor.idVendor, dev->descriptor.idProduct);
 		/* Abort, we don't want to use that non-functional keyboard. */
@@ -550,9 +532,22 @@ int drv_usb_kbd_init(void)
 int usb_kbd_deregister(int force)
 {
 #ifdef CONFIG_SYS_STDIO_DEREGISTER
-	int ret = stdio_deregister(DEVNAME, force);
-	if (ret && ret != -ENODEV)
-		return ret;
+	struct stdio_dev *dev;
+	struct usb_device *usb_kbd_dev;
+	struct usb_kbd_pdata *data;
+
+	dev = stdio_get_by_name(DEVNAME);
+	if (dev) {
+		usb_kbd_dev = (struct usb_device *)dev->priv;
+		data = usb_kbd_dev->privptr;
+		if (stdio_deregister_dev(dev, force) != 0)
+			return 1;
+#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
+		destroy_int_queue(usb_kbd_dev, data->intq);
+#endif
+		free(data->new);
+		free(data);
+	}
 
 	return 0;
 #else
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 6ac358d5e2b..eb7706c100c 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -33,6 +33,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <inttypes.h>
 #include <asm/byteorder.h>
 #include <asm/processor.h>
 
@@ -1071,7 +1072,7 @@ unsigned long usb_stor_read(int device, lbaint_t blknr,
 	blks = blkcnt;
 
 	debug("\nusb_read: dev %d startblk " LBAF ", blccnt " LBAF
-	      " buffer %lx\n", device, start, blks, buf_addr);
+	      " buffer %" PRIxPTR "\n", device, start, blks, buf_addr);
 
 	do {
 		/* XXX need some comment here */
@@ -1101,7 +1102,7 @@ retry_it:
 	ss->flags &= ~USB_READY;
 
 	debug("usb_read: end startblk " LBAF
-	      ", blccnt %x buffer %lx\n",
+	      ", blccnt %x buffer %" PRIxPTR "\n",
 	      start, smallblks, buf_addr);
 
 	usb_disable_asynch(0); /* asynch transfer allowed */
@@ -1145,7 +1146,7 @@ unsigned long usb_stor_write(int device, lbaint_t blknr,
 	blks = blkcnt;
 
 	debug("\nusb_write: dev %d startblk " LBAF ", blccnt " LBAF
-	      " buffer %lx\n", device, start, blks, buf_addr);
+	      " buffer %" PRIxPTR "\n", device, start, blks, buf_addr);
 
 	do {
 		/* If write fails retry for max retry count else
@@ -1176,8 +1177,8 @@ retry_it:
 	} while (blks != 0);
 	ss->flags &= ~USB_READY;
 
-	debug("usb_write: end startblk " LBAF ", blccnt %x buffer %lx\n",
-	      start, smallblks, buf_addr);
+	debug("usb_write: end startblk " LBAF ", blccnt %x buffer %"
+	      PRIxPTR "\n", start, smallblks, buf_addr);
 
 	usb_disable_asynch(0); /* asynch transfer allowed */
 	if (blkcnt >= USB_MAX_XFER_BLK)
diff --git a/config.mk b/config.mk
index 2157537c823..64c2951ac1e 100644
--- a/config.mk
+++ b/config.mk
@@ -18,6 +18,8 @@ PLATFORM_LDFLAGS :=
 LDFLAGS :=
 LDFLAGS_FINAL :=
 OBJCOPYFLAGS :=
+# clear VENDOR for tcsh
+VENDOR :=
 #########################################################################
 
 ARCH := $(CONFIG_SYS_ARCH:"%"=%)
@@ -57,6 +59,11 @@ ifdef FTRACE
 PLATFORM_CPPFLAGS += -finstrument-functions -DFTRACE
 endif
 
+# Allow use of stdint.h if available
+ifneq ($(USE_STDINT),)
+PLATFORM_CPPFLAGS += -DCONFIG_USE_STDINT
+endif
+
 #########################################################################
 
 RELFLAGS := $(PLATFORM_RELFLAGS)
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index f9922936ab1..f0cbf21025a 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A10_OLINUXINO_L,AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
 CONFIG_FDTFILE="sun4i-a10-olinuxino-lime.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_A10_OLINUXINO_L=y
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index a578c067d4d..64756755bf9 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -1,5 +1,10 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A10S_OLINUXINO_M,AXP152_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPB(10)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPB(10)"
 CONFIG_FDTFILE="sun5i-a10s-olinuxino-micro.dtb"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=1
++S:CONFIG_MMC0_CD_PIN="PG1"
++S:CONFIG_MMC1_CD_PIN="PG13"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN5I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_TARGET_A10S_OLINUXINO_M=y
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index 9ae7b128517..d8b12391d86 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A13_OLINUXINOM,CONS_INDEX=2,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)"
 CONFIG_FDTFILE="sun5i-a13-olinuxino-micro.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN5I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_TARGET_A13_OLINUXINOM=y
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 2c726f308a2..91039dfc969 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A13_OLINUXINO,CONS_INDEX=2,AXP209_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)"
 CONFIG_FDTFILE="sun5i-a13-olinuxino.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN5I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_TARGET_A13_OLINUXINO=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
new file mode 100644
index 00000000000..f80b98ae90a
--- /dev/null
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -0,0 +1,7 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
+CONFIG_FDTFILE="sun7i-a20-olinuxino-lime2.dtb"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_A20_OLINUXINO_L2=y
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index ca79fd58aa6..d9e66b71551 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A20_OLINUXINO_L,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
 CONFIG_FDTFILE="sun7i-a20-olinuxino-lime.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_A20_OLINUXINO_L=y
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index 20a947ca723..1b9668d46df 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -1,5 +1,10 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A20_OLINUXINO_M,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
 CONFIG_FDTFILE="sun7i-a20-olinuxino-micro.dtb"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=3
++S:CONFIG_MMC0_CD_PIN="PH1"
++S:CONFIG_MMC3_CD_PIN="PH11"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_A20_OLINUXINO_M=y
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index ed06f5700c3..5b06ea0aead 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="AUXTEK_T004,AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)"
 CONFIG_FDTFILE="sun5i-a10s-auxtek-t004.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN5I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_TARGET_AUXTEK_T004=y
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index d59cf72eaac..196f6824cb4 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="BANANAPI,AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
 CONFIG_FDTFILE="sun7i-a20-bananapi.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_BANANAPI=y
diff --git a/configs/CPCI750_defconfig b/configs/CPCI750_defconfig
deleted file mode 100644
index abdd4d29fa6..00000000000
--- a/configs/CPCI750_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_74xx_7xx=y
-CONFIG_TARGET_CPCI750=y
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
new file mode 100644
index 00000000000..89291f90e97
--- /dev/null
+++ b/configs/Colombus_defconfig
@@ -0,0 +1,5 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_TARGET_COLOMBUS=y
+CONFIG_FDTFILE="sun6i-a31-colombus.dtb"
diff --git a/configs/Cubieboard2_FEL_defconfig b/configs/Cubieboard2_FEL_defconfig
deleted file mode 100644
index 353b04a3b1d..00000000000
--- a/configs/Cubieboard2_FEL_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD2,SPL_FEL,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-cubieboard2.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 11a0c5ff376..7e7a1ca3981 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD2,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
 CONFIG_FDTFILE="sun7i-a20-cubieboard2.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_CUBIEBOARD2=y
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index 8c1ff9584ea..0bc45fd2cb2 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD,AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
 CONFIG_FDTFILE="sun4i-a10-cubieboard.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_CUBIEBOARD=y
diff --git a/configs/Cubietruck_FEL_defconfig b/configs/Cubietruck_FEL_defconfig
deleted file mode 100644
index 23c5efb18ab..00000000000
--- a/configs/Cubietruck_FEL_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-cubietruck.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 1389f2138bb..b1f9f936fa8 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIETRUCK,AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
 CONFIG_FDTFILE="sun7i-a20-cubietruck.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_CUBIETRUCK=y
diff --git a/configs/DB64360_defconfig b/configs/DB64360_defconfig
deleted file mode 100644
index 358b0968f0b..00000000000
--- a/configs/DB64360_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_74xx_7xx=y
-CONFIG_TARGET_DB64360=y
diff --git a/configs/DB64460_defconfig b/configs/DB64460_defconfig
deleted file mode 100644
index 4ff2fadaa0d..00000000000
--- a/configs/DB64460_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_74xx_7xx=y
-CONFIG_TARGET_DB64460=y
diff --git a/configs/EVAL5200_defconfig b/configs/EVAL5200_defconfig
deleted file mode 100644
index 6a272d24ebe..00000000000
--- a/configs/EVAL5200_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="EVAL5200"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TOP5200=y
diff --git a/configs/HWW1U1A_defconfig b/configs/HWW1U1A_defconfig
deleted file mode 100644
index 8947be279ba..00000000000
--- a/configs/HWW1U1A_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_HWW1U1A=y
diff --git a/configs/ICU862_100MHz_defconfig b/configs/ICU862_100MHz_defconfig
deleted file mode 100644
index 72f0dfa79e0..00000000000
--- a/configs/ICU862_100MHz_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="100MHz"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_ICU862=y
diff --git a/configs/ICU862_defconfig b/configs/ICU862_defconfig
deleted file mode 100644
index b58ea05d162..00000000000
--- a/configs/ICU862_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_ICU862=y
diff --git a/configs/IDS8247_defconfig b/configs/IDS8247_defconfig
deleted file mode 100644
index b4dd23fdbae..00000000000
--- a/configs/IDS8247_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_IDS8247=y
diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig
new file mode 100644
index 00000000000..fc67bd9d56c
--- /dev/null
+++ b/configs/Ippo_q8h_v5_defconfig
@@ -0,0 +1,6 @@
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I=y
+CONFIG_TARGET_IPPO_Q8H_V5=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5.dtb"
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index efc53017897..a26ff0a70f4 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="PCDUINO3,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
 CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_PCDUINO3=y
diff --git a/configs/Linksprite_pcDuino3_fdt_defconfig b/configs/Linksprite_pcDuino3_fdt_defconfig
new file mode 100644
index 00000000000..a33f3a7981f
--- /dev/null
+++ b/configs/Linksprite_pcDuino3_fdt_defconfig
@@ -0,0 +1,11 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
+CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
+CONFIG_DM=y
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
+CONFIG_OF_CONTROL=y
+CONFIG_OF_SEPARATE=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_PCDUINO3=y
diff --git a/configs/MHPC_defconfig b/configs/MHPC_defconfig
deleted file mode 100644
index b05d3c4116f..00000000000
--- a/configs/MHPC_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_MHPC=y
diff --git a/configs/MINI5200_defconfig b/configs/MINI5200_defconfig
deleted file mode 100644
index dfe853ee621..00000000000
--- a/configs/MINI5200_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MINI5200"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TOP5200=y
diff --git a/configs/Mele_A1000G_defconfig b/configs/Mele_A1000G_defconfig
index 06c4cacc53b..2f4bf72c934 100644
--- a/configs/Mele_A1000G_defconfig
+++ b/configs/Mele_A1000G_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MELE_A1000G,AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
 CONFIG_FDTFILE="sun4i-a10-a1000.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_MELE_A1000G=y
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index d386c79e048..e2912b0afdb 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MELE_A1000,AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
 CONFIG_FDTFILE="sun4i-a10-a1000.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_MELE_A1000=y
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
new file mode 100644
index 00000000000..fe9ba11c392
--- /dev/null
+++ b/configs/Mele_M3_defconfig
@@ -0,0 +1,9 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,USB_EHCI"
+CONFIG_FDTFILE="sun7i-a20-m3.dtb"
++S:CONFIG_MMC_SUNXI_SLOT_EXTRA=2
++S:CONFIG_MMC0_CD_PIN="PH1"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_MELE_M3=y
diff --git a/configs/Mini-X-1Gb_defconfig b/configs/Mini-X-1Gb_defconfig
index 5db4aa3a147..b8fea012457 100644
--- a/configs/Mini-X-1Gb_defconfig
+++ b/configs/Mini-X-1Gb_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MINI_X_1GB,AXP209_POWER,USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
 CONFIG_FDTFILE="sun4i-a10-mini-xplus.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_MINI_X_1GB=y
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index 6718dcb68cf..0f6bbe06b2c 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MINI_X,AXP209_POWER,USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
 CONFIG_FDTFILE="sun4i-a10-mini-xplus.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_MINI_X=y
diff --git a/configs/TOP5200_defconfig b/configs/TOP5200_defconfig
deleted file mode 100644
index 86eed7fa7e7..00000000000
--- a/configs/TOP5200_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="TOP5200"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TOP5200=y
diff --git a/configs/TOP860_defconfig b/configs/TOP860_defconfig
deleted file mode 100644
index 9fcc6f6f59f..00000000000
--- a/configs/TOP860_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_TOP860=y
diff --git a/configs/TQM8255_AA_defconfig b/configs/TQM8255_AA_defconfig
deleted file mode 100644
index a9f9f015ff2..00000000000
--- a/configs/TQM8255_AA_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8255,300MHz"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
diff --git a/configs/TQM8260_AA_defconfig b/configs/TQM8260_AA_defconfig
deleted file mode 100644
index b762fe4a0da..00000000000
--- a/configs/TQM8260_AA_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,200MHz"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
diff --git a/configs/TQM8260_AB_defconfig b/configs/TQM8260_AB_defconfig
deleted file mode 100644
index 6ff8d17117f..00000000000
--- a/configs/TQM8260_AB_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,200MHz,L2_CACHE,BUSMODE_60x"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
diff --git a/configs/TQM8260_AC_defconfig b/configs/TQM8260_AC_defconfig
deleted file mode 100644
index 6ff8d17117f..00000000000
--- a/configs/TQM8260_AC_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,200MHz,L2_CACHE,BUSMODE_60x"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
diff --git a/configs/TQM8260_AD_defconfig b/configs/TQM8260_AD_defconfig
deleted file mode 100644
index 3f406a4f297..00000000000
--- a/configs/TQM8260_AD_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,BUSMODE_60x"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
diff --git a/configs/TQM8260_AE_defconfig b/configs/TQM8260_AE_defconfig
deleted file mode 100644
index 1077b191712..00000000000
--- a/configs/TQM8260_AE_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,266MHz"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
diff --git a/configs/TQM8260_AF_defconfig b/configs/TQM8260_AF_defconfig
deleted file mode 100644
index 3f406a4f297..00000000000
--- a/configs/TQM8260_AF_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,BUSMODE_60x"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
diff --git a/configs/TQM8260_AG_defconfig b/configs/TQM8260_AG_defconfig
deleted file mode 100644
index b0d67fa3268..00000000000
--- a/configs/TQM8260_AG_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
diff --git a/configs/TQM8260_AH_defconfig b/configs/TQM8260_AH_defconfig
deleted file mode 100644
index 65c73e83093..00000000000
--- a/configs/TQM8260_AH_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,L2_CACHE,BUSMODE_60x"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
diff --git a/configs/TQM8260_AI_defconfig b/configs/TQM8260_AI_defconfig
deleted file mode 100644
index 3f406a4f297..00000000000
--- a/configs/TQM8260_AI_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,BUSMODE_60x"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
diff --git a/configs/TQM8265_AA_defconfig b/configs/TQM8265_AA_defconfig
deleted file mode 100644
index d8806c4bb4f..00000000000
--- a/configs/TQM8265_AA_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8265,300MHz,BUSMODE_60x"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
diff --git a/configs/TQM8272_defconfig b/configs/TQM8272_defconfig
deleted file mode 100644
index 0070baf808c..00000000000
--- a/configs/TQM8272_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8272=y
diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig
index 38450c0d615..b631c410dc7 100644
--- a/configs/am335x_boneblack_defconfig
+++ b/configs/am335x_boneblack_defconfig
@@ -1,4 +1,4 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_AM335X_EVM=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index e25714366be..5837a0a4da7 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -1,5 +1,5 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT,ENABLE_VBOOT"
+CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_AM335X_EVM=y
 CONFIG_OF_CONTROL=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
new file mode 100644
index 00000000000..fc5e1e4d38b
--- /dev/null
+++ b/configs/apalis_t30_defconfig
@@ -0,0 +1,5 @@
++S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA30=y
++S:CONFIG_TARGET_APALIS_T30=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis"
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index 6f64875b4a2..0a1abea0a8d 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="BA10_TV_BOX,AXP209_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS1_GPIO=SUNXI_GPH(12)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS1_GPIO=SUNXI_GPH(12)"
 CONFIG_FDTFILE="sun4i-a10-ba10-tvbox.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_BA10_TV_BOX=y
diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
new file mode 100644
index 00000000000..7aa216c47d4
--- /dev/null
+++ b/configs/db-mv784mp-gp_defconfig
@@ -0,0 +1,2 @@
+CONFIG_ARM=y
+CONFIG_TARGET_DB_MV784MP_GP=y
diff --git a/configs/dbau1000_defconfig b/configs/dbau1000_defconfig
index 7c95629cfb4..aa4d338d435 100644
--- a/configs/dbau1000_defconfig
+++ b/configs/dbau1000_defconfig
@@ -1,3 +1,4 @@
 CONFIG_SYS_EXTRA_OPTIONS="DBAU1000"
 CONFIG_MIPS=y
 CONFIG_TARGET_DBAU1X00=y
+CONFIG_SYS_BIG_ENDIAN=y
diff --git a/configs/dbau1100_defconfig b/configs/dbau1100_defconfig
index 506f5da8cac..aac9f032b02 100644
--- a/configs/dbau1100_defconfig
+++ b/configs/dbau1100_defconfig
@@ -1,3 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="DBAU1100"
 CONFIG_MIPS=y
 CONFIG_TARGET_DBAU1X00=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_DBAU1100=y
diff --git a/configs/dbau1500_defconfig b/configs/dbau1500_defconfig
index 5a02a78610e..d96de13ff99 100644
--- a/configs/dbau1500_defconfig
+++ b/configs/dbau1500_defconfig
@@ -1,3 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="DBAU1500"
 CONFIG_MIPS=y
 CONFIG_TARGET_DBAU1X00=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_DBAU1500=y
diff --git a/configs/dbau1550_defconfig b/configs/dbau1550_defconfig
index 90150235244..a2dfe18c784 100644
--- a/configs/dbau1550_defconfig
+++ b/configs/dbau1550_defconfig
@@ -1,3 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="DBAU1550"
 CONFIG_MIPS=y
 CONFIG_TARGET_DBAU1X00=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_DBAU1550=y
diff --git a/configs/dbau1550_el_defconfig b/configs/dbau1550_el_defconfig
index 53b35ce60f5..767326f6d46 100644
--- a/configs/dbau1550_el_defconfig
+++ b/configs/dbau1550_el_defconfig
@@ -1,3 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="DBAU1550,SYS_LITTLE_ENDIAN"
 CONFIG_MIPS=y
 CONFIG_TARGET_DBAU1X00=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_DBAU1550=y
diff --git a/configs/gr_cpci_ax2000_defconfig b/configs/gr_cpci_ax2000_defconfig
index 6eb02ad1231..b59d07772fc 100644
--- a/configs/gr_cpci_ax2000_defconfig
+++ b/configs/gr_cpci_ax2000_defconfig
@@ -1,2 +1,3 @@
+CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SPARC=y
 CONFIG_TARGET_GR_CPCI_AX2000=y
diff --git a/configs/gr_ep2s60_defconfig b/configs/gr_ep2s60_defconfig
index 6e1eb83c770..2c69efa6052 100644
--- a/configs/gr_ep2s60_defconfig
+++ b/configs/gr_ep2s60_defconfig
@@ -1,2 +1,3 @@
+CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SPARC=y
 CONFIG_TARGET_GR_EP2S60=y
diff --git a/configs/gr_xc3s_1500_defconfig b/configs/gr_xc3s_1500_defconfig
index da846db371b..fecdd2507c2 100644
--- a/configs/gr_xc3s_1500_defconfig
+++ b/configs/gr_xc3s_1500_defconfig
@@ -1,2 +1,3 @@
+CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SPARC=y
 CONFIG_TARGET_GR_XC3S_1500=y
diff --git a/configs/grsim_defconfig b/configs/grsim_defconfig
index 2a7e8e70575..e3ffd69f194 100644
--- a/configs/grsim_defconfig
+++ b/configs/grsim_defconfig
@@ -1,2 +1,3 @@
+CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SPARC=y
 CONFIG_TARGET_GRSIM=y
diff --git a/configs/grsim_leon2_defconfig b/configs/grsim_leon2_defconfig
index e91eb968fec..6090e34e677 100644
--- a/configs/grsim_leon2_defconfig
+++ b/configs/grsim_leon2_defconfig
@@ -1,2 +1,3 @@
+CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SPARC=y
 CONFIG_TARGET_GRSIM_LEON2=y
diff --git a/configs/hymod_defconfig b/configs/hymod_defconfig
deleted file mode 100644
index a6dc1d88a9e..00000000000
--- a/configs/hymod_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_HYMOD=y
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index 2ef0f918287..5f5037e6982 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="I12_TVBOX,AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
 CONFIG_FDTFILE="sun7i-a20-i12-tvbox.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_I12_TVBOX=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
new file mode 100644
index 00000000000..45399cea6b7
--- /dev/null
+++ b/configs/k2l_evm_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_KEYSTONE=y
++S:CONFIG_TARGET_K2L_EVM=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
new file mode 100644
index 00000000000..2b479955108
--- /dev/null
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AQDS=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
new file mode 100644
index 00000000000..eeeb0d59078
--- /dev/null
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021ATWR=y
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index f3788b6db1f..5a178a76b31 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig
@@ -1,3 +1,3 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BIG_ENDIAN"
 CONFIG_MIPS=y
 CONFIG_TARGET_MALTA=y
+CONFIG_SYS_BIG_ENDIAN=y
diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
index 97d0e899da3..011525fc2b5 100644
--- a/configs/maltael_defconfig
+++ b/configs/maltael_defconfig
@@ -1,3 +1,3 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_LITTLE_ENDIAN"
 CONFIG_MIPS=y
 CONFIG_TARGET_MALTA=y
+CONFIG_SYS_LITTLE_ENDIAN=y
diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig
new file mode 100644
index 00000000000..4bcffd8c2da
--- /dev/null
+++ b/configs/maxbcm_defconfig
@@ -0,0 +1,2 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MAXBCM=y
diff --git a/configs/p3m7448_defconfig b/configs/p3m7448_defconfig
deleted file mode 100644
index 9b036895ee7..00000000000
--- a/configs/p3m7448_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P3M7448"
-CONFIG_PPC=y
-CONFIG_74xx_7xx=y
-CONFIG_TARGET_P3MX=y
diff --git a/configs/p3m750_defconfig b/configs/p3m750_defconfig
deleted file mode 100644
index e5377eb620c..00000000000
--- a/configs/p3m750_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P3M750"
-CONFIG_PPC=y
-CONFIG_74xx_7xx=y
-CONFIG_TARGET_P3MX=y
diff --git a/configs/pb1000_defconfig b/configs/pb1000_defconfig
index e226358fe2d..72c22a0876b 100644
--- a/configs/pb1000_defconfig
+++ b/configs/pb1000_defconfig
@@ -1,3 +1,4 @@
 CONFIG_SYS_EXTRA_OPTIONS="PB1000"
 CONFIG_MIPS=y
 CONFIG_TARGET_PB1X00=y
+CONFIG_SYS_LITTLE_ENDIAN=y
diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig
index 53f3126e71e..e6aba422f81 100644
--- a/configs/ph1_ld4_defconfig
+++ b/configs/ph1_ld4_defconfig
@@ -2,7 +2,10 @@ CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_UNIPHIER=y
 +S:CONFIG_MACH_PH1_LD4=y
+CONFIG_DM=y
 CONFIG_NAND_DENALI=y
 CONFIG_SYS_NAND_DENALI_64BIT=y
 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+CONFIG_DM_SERIAL=y
+CONFIG_UNIPHIER_SERIAL=y
 S:CONFIG_SPL_NAND_DENALI=y
diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig
index 209466ebcb3..334ec4bbdff 100644
--- a/configs/ph1_pro4_defconfig
+++ b/configs/ph1_pro4_defconfig
@@ -2,7 +2,10 @@ CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_UNIPHIER=y
 +S:CONFIG_MACH_PH1_PRO4=y
+CONFIG_DM=y
 CONFIG_NAND_DENALI=y
 CONFIG_SYS_NAND_DENALI_64BIT=y
 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+CONFIG_DM_SERIAL=y
+CONFIG_UNIPHIER_SERIAL=y
 S:CONFIG_SPL_NAND_DENALI=y
diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig
index 658977bcf62..4e8f354c9b5 100644
--- a/configs/ph1_sld8_defconfig
+++ b/configs/ph1_sld8_defconfig
@@ -2,7 +2,10 @@ CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_UNIPHIER=y
 +S:CONFIG_MACH_PH1_SLD8=y
+CONFIG_DM=y
 CONFIG_NAND_DENALI=y
 CONFIG_SYS_NAND_DENALI_64BIT=y
 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+CONFIG_DM_SERIAL=y
+CONFIG_UNIPHIER_SERIAL=y
 S:CONFIG_SPL_NAND_DENALI=y
diff --git a/configs/qemu_mips64_defconfig b/configs/qemu_mips64_defconfig
index 29483557698..3608bbe5524 100644
--- a/configs/qemu_mips64_defconfig
+++ b/configs/qemu_mips64_defconfig
@@ -1,3 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BIG_ENDIAN"
 CONFIG_MIPS=y
-CONFIG_TARGET_QEMU_MIPS64=y
+CONFIG_TARGET_QEMU_MIPS=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_CPU_MIPS64_R1=y
diff --git a/configs/qemu_mips64el_defconfig b/configs/qemu_mips64el_defconfig
index 13a039f0b81..a9ebd7b5ff2 100644
--- a/configs/qemu_mips64el_defconfig
+++ b/configs/qemu_mips64el_defconfig
@@ -1,3 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_LITTLE_ENDIAN"
 CONFIG_MIPS=y
-CONFIG_TARGET_QEMU_MIPS64=y
+CONFIG_TARGET_QEMU_MIPS=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS64_R1=y
diff --git a/configs/qemu_mips_defconfig b/configs/qemu_mips_defconfig
index 6b2c0290e97..f58dd2200ad 100644
--- a/configs/qemu_mips_defconfig
+++ b/configs/qemu_mips_defconfig
@@ -1,3 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BIG_ENDIAN"
 CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_CPU_MIPS32_R2=y
diff --git a/configs/qemu_mipsel_defconfig b/configs/qemu_mipsel_defconfig
index 57c87016c4d..84a45116fad 100644
--- a/configs/qemu_mipsel_defconfig
+++ b/configs/qemu_mipsel_defconfig
@@ -1,3 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_LITTLE_ENDIAN"
 CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32_R2=y
diff --git a/configs/qt840a_defconfig b/configs/qt840a_defconfig
index a8d4bb8845f..70f8159b39c 100644
--- a/configs/qt840a_defconfig
+++ b/configs/qt840a_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="QT840A,AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
 CONFIG_FDTFILE="sun7i-a20-i12-tvbox.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_QT840A=y
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index 6aba94201e8..7dbff40b508 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -1,5 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="R7DONGLE,AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)"
 CONFIG_FDTFILE="sun5i-a10s-r7-tv-dongle.dtb"
 +S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN5I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_TARGET_R7DONGLE=y
diff --git a/configs/top9000eval_xe_defconfig b/configs/top9000eval_xe_defconfig
deleted file mode 100644
index 7ea51f526a0..00000000000
--- a/configs/top9000eval_xe_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="EVAL9000"
-CONFIG_ARM=y
-CONFIG_TARGET_TOP9000=y
diff --git a/configs/top9000su_xe_defconfig b/configs/top9000su_xe_defconfig
deleted file mode 100644
index bf6b6f127f6..00000000000
--- a/configs/top9000su_xe_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SU9000"
-CONFIG_ARM=y
-CONFIG_TARGET_TOP9000=y
diff --git a/configs/vct_platinum_defconfig b/configs/vct_platinum_defconfig
index 9ff8b684214..32e9e8cc6d7 100644
--- a/configs/vct_platinum_defconfig
+++ b/configs/vct_platinum_defconfig
@@ -1,3 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUM=y
diff --git a/configs/vct_platinum_onenand_defconfig b/configs/vct_platinum_onenand_defconfig
index f33c97dc8f2..4346518a18a 100644
--- a/configs/vct_platinum_onenand_defconfig
+++ b/configs/vct_platinum_onenand_defconfig
@@ -1,3 +1,5 @@
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM,VCT_ONENAND"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUM=y
+CONFIG_VCT_ONENAND=y
diff --git a/configs/vct_platinum_onenand_small_defconfig b/configs/vct_platinum_onenand_small_defconfig
index 58c79955abf..fd522829668 100644
--- a/configs/vct_platinum_onenand_small_defconfig
+++ b/configs/vct_platinum_onenand_small_defconfig
@@ -1,4 +1,7 @@
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUM=y
+CONFIG_VCT_ONENAND=y
+CONFIG_VCT_SMALL_IMAGE=y
 # CONFIG_CMD_CRC32 is not set
diff --git a/configs/vct_platinum_small_defconfig b/configs/vct_platinum_small_defconfig
index f4f56c4f4cb..58f956d7dbb 100644
--- a/configs/vct_platinum_small_defconfig
+++ b/configs/vct_platinum_small_defconfig
@@ -1,4 +1,6 @@
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM,VCT_SMALL_IMAGE"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUM=y
+CONFIG_VCT_SMALL_IMAGE=y
 # CONFIG_CMD_CRC32 is not set
diff --git a/configs/vct_platinumavc_defconfig b/configs/vct_platinumavc_defconfig
index 8aaac56e3de..732565cb968 100644
--- a/configs/vct_platinumavc_defconfig
+++ b/configs/vct_platinumavc_defconfig
@@ -1,3 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUMAVC=y
diff --git a/configs/vct_platinumavc_onenand_defconfig b/configs/vct_platinumavc_onenand_defconfig
index 926c6e40504..670e7f92daa 100644
--- a/configs/vct_platinumavc_onenand_defconfig
+++ b/configs/vct_platinumavc_onenand_defconfig
@@ -1,3 +1,5 @@
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC,VCT_ONENAND"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUMAVC=y
+CONFIG_VCT_ONENAND=y
diff --git a/configs/vct_platinumavc_onenand_small_defconfig b/configs/vct_platinumavc_onenand_small_defconfig
index 31b4c9a8d61..31a4948e709 100644
--- a/configs/vct_platinumavc_onenand_small_defconfig
+++ b/configs/vct_platinumavc_onenand_small_defconfig
@@ -1,4 +1,7 @@
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUMAVC=y
+CONFIG_VCT_ONENAND=y
+CONFIG_VCT_SMALL_IMAGE=y
 # CONFIG_CMD_CRC32 is not set
diff --git a/configs/vct_platinumavc_small_defconfig b/configs/vct_platinumavc_small_defconfig
index 23f6561b34e..ce00a6c0f19 100644
--- a/configs/vct_platinumavc_small_defconfig
+++ b/configs/vct_platinumavc_small_defconfig
@@ -1,4 +1,6 @@
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC,VCT_SMALL_IMAGE"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUMAVC=y
+CONFIG_VCT_SMALL_IMAGE=y
 # CONFIG_CMD_CRC32 is not set
diff --git a/configs/vct_premium_defconfig b/configs/vct_premium_defconfig
index 0e16ff9cacd..a19e65d7e6f 100644
--- a/configs/vct_premium_defconfig
+++ b/configs/vct_premium_defconfig
@@ -1,3 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PREMIUM=y
diff --git a/configs/vct_premium_onenand_defconfig b/configs/vct_premium_onenand_defconfig
index 29734b82749..092d0f79d33 100644
--- a/configs/vct_premium_onenand_defconfig
+++ b/configs/vct_premium_onenand_defconfig
@@ -1,3 +1,5 @@
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM,VCT_ONENAND"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PREMIUM=y
+CONFIG_VCT_ONENAND=y
diff --git a/configs/vct_premium_onenand_small_defconfig b/configs/vct_premium_onenand_small_defconfig
index 354793edc85..eabfb88e0c3 100644
--- a/configs/vct_premium_onenand_small_defconfig
+++ b/configs/vct_premium_onenand_small_defconfig
@@ -1,4 +1,7 @@
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PREMIUM=y
+CONFIG_VCT_ONENAND=y
+CONFIG_VCT_SMALL_IMAGE=y
 # CONFIG_CMD_CRC32 is not set
diff --git a/configs/vct_premium_small_defconfig b/configs/vct_premium_small_defconfig
index a23ddb7e213..1ce0efd2734 100644
--- a/configs/vct_premium_small_defconfig
+++ b/configs/vct_premium_small_defconfig
@@ -1,4 +1,6 @@
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM,VCT_SMALL_IMAGE"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PREMIUM=y
+CONFIG_VCT_SMALL_IMAGE=y
 # CONFIG_CMD_CRC32 is not set
diff --git a/disk/part.c b/disk/part.c
index cfd77b0ff56..43485c9148b 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -57,7 +57,7 @@ static const struct block_drvr block_drvr[] = {
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef HAVE_BLOCK_DEVICE
-block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart)
+static block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart)
 {
 	const struct block_drvr *drvr = block_drvr;
 	block_dev_desc_t* (*reloc_get_dev)(int dev);
diff --git a/doc/README.SPL b/doc/README.SPL
index c283dcff62d..3ba313caa8f 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -54,6 +54,7 @@ CONFIG_SPL_SERIAL_SUPPORT (drivers/serial/libserial.o)
 CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o)
 CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o)
 CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
+CONFIG_SPL_EXT_SUPPORT
 CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
 CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
 CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
diff --git a/doc/README.kconfig b/doc/README.kconfig
index 3aad5b4185b..69dc45970b8 100644
--- a/doc/README.kconfig
+++ b/doc/README.kconfig
@@ -79,7 +79,7 @@ See below for how each configuration target works in U-Boot:
   ST:   - the line is valid for SPL and TPL images
   +S:   - the line is valid for Normal and SPL images
   +T:   - the line is valid for Normal and TPL images
-  +ST:  - the line is valid for Normal, SPL and SPL images
+  +ST:  - the line is valid for Normal, SPL and TPL images
 
   So, if neither CONFIG_SPL nor CONFIG_TPL is defined, the defconfig file
   has no "<condition>:" part and therefore has the same form as in Linux.
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 1dcdcc7bb65..bd4dd3c8299 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,14 +12,29 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
-MVBC_P           powerpc     mpc5xxx        -           -           Andre Schwarz <andre.schwarz@matrix-vision.de>
-MVSMR            powerpc     mpc5xxx        -           -           Andre Schwarz <andre.schwarz@matrix-vision.de>
-MERGERBOX        powerpc     mpc83xx        -           -           Andre Schwarz <andre.schwarz@matrix-vision.de>
-MVBLM7           powerpc     mpc83xx        -           -           Andre Schwarz <andre.schwarz@matrix-vision.de>
-bluestone        powerpc     ppc4xx         -           -           Tirumala Marri <tmarri@apm.com>
-CRAYL1           powerpc     ppc4xx         -           -           David Updegraff <dave@cray.com>
-KAREF            powerpc     ppc4xx         -           -           Travis Sawyer <travis.sawyer@sandburst.com>
-METROBOX         powerpc     ppc4xx         -           -           Travis Sawyer <travis.sawyer@sandburst.com>
+TOP5200		 powerpc     mpc5200	    -		-	    Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+TOP860		 powerpc     mpc860	    -		-	    Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+TOP9000		 arm	     at91sam9xeXXX  -		-	    Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+TQM8272          powerpc     mpc8260        f06f9a1     2014-10-27  Wolfgang Denk <wd@denx.de>
+TQM8260          powerpc     mpc8260        ccc1950     2014-10-27  Wolfgang Denk <wd@denx.de>
+IDS8247          powerpc     mpc8260        6afb357     2014-10-27  Heiko Schocher <hs@denx.de>
+HWW1U1A          powerpc     mpc85xx        4109cb0     2014-10-27  Kyle Moffett <Kyle.D.Moffett@boeing.com>
+hymod            powerpc     mpc8260        5038d7f     2014-10-27  Murray Jensen <Murray.Jensen@csiro.au>
+MHPC             powerpc     mpc8xx         1655f9f     2014-10-27  Frank Gottschling <fgottschling@eltec.de>
+ICU862           powerpc     mpc8xx         4af5f0f     2014-10-27  Wolfgang Denk <wd@denx.de>
+CPCI750		 powerpc     74xx_7xx	    03b0040	2014-10-27  Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+DB64360		 powerpc     74xx_7xx	    03b0040	2014-10-27
+DB64460		 powerpc     74xx_7xx	    03b0040	2014-10-27
+p3m750		 powerpc     74xx_7xx	    03b0040	2014-10-27  Stefan Roese <sr@denx.de>
+p3m7448		 powerpc     74xx_7xx	    03b0040	2014-10-27  Stefan Roese <sr@denx.de>
+MVBC_P           powerpc     mpc5xxx        af55e35	2014-10-10  Andre Schwarz <andre.schwarz@matrix-vision.de>
+MVSMR            powerpc     mpc5xxx        af55e35	2014-10-10  Andre Schwarz <andre.schwarz@matrix-vision.de>
+MERGERBOX        powerpc     mpc83xx        e7a5656	2014-10-10  Andre Schwarz <andre.schwarz@matrix-vision.de>
+MVBLM7           powerpc     mpc83xx        e7a5656	2014-10-10  Andre Schwarz <andre.schwarz@matrix-vision.de>
+bluestone        powerpc     ppc4xx         9ed3246	2014-10-10  Tirumala Marri <tmarri@apm.com>
+CRAYL1           powerpc     ppc4xx         1521cdc	2014-10-10  David Updegraff <dave@cray.com>
+KAREF            powerpc     ppc4xx         dc9617e	2014-10-10  Travis Sawyer <travis.sawyer@sandburst.com>
+METROBOX         powerpc     ppc4xx         dc9617e	2014-10-10  Travis Sawyer <travis.sawyer@sandburst.com>
 PK1C20           nios2       -              70fbc461    2014-08-24  Scott McNutt <smcnutt@psyent.com>
 PCI5441          nios2       -              70fbc461    2014-08-24  Scott McNutt <smcnutt@psyent.com>
 flagadm          powerpc     mpc8xx         aec6f8c5    2014-08-22  Kári Davíðsson <kd@flaga.is>
diff --git a/doc/README.standalone b/doc/README.standalone
index 2be5f27696f..e3000efcc62 100644
--- a/doc/README.standalone
+++ b/doc/README.standalone
@@ -21,7 +21,7 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications:
 2. The pointer to the jump table is passed to the application in a
    machine-dependent way. PowerPC, ARM, MIPS, Blackfin and Nios II
    architectures use a dedicated register to hold the pointer to the
-   'global_data' structure: r2 on PowerPC, r8 on ARM, k0 on MIPS,
+   'global_data' structure: r2 on PowerPC, r9 on ARM, k0 on MIPS,
    P3 on Blackfin and gp on Nios II. The x86 architecture does not
    use such a register; instead, the pointer to the 'global_data'
    structure is passed as 'argv[-1]' pointer.
diff --git a/doc/README.unaligned-memory-access.txt b/doc/README.unaligned-memory-access.txt
index 00529f5dac7..70a85f9cfe0 100644
--- a/doc/README.unaligned-memory-access.txt
+++ b/doc/README.unaligned-memory-access.txt
@@ -154,7 +154,7 @@ bool ether_addr_equal(const u8 *addr1, const u8 *addr2)
 #else
 	const u16 *a = (const u16 *)addr1;
 	const u16 *b = (const u16 *)addr2;
-	return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) != 0;
+	return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) == 0;
 #endif
 }
 
diff --git a/doc/SPI/README.altera_spi b/doc/SPI/README.altera_spi
new file mode 100644
index 00000000000..b07449f80d6
--- /dev/null
+++ b/doc/SPI/README.altera_spi
@@ -0,0 +1,6 @@
+SoCFPGA EPCS/EPCQx1 mini howto:
+- Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild
+- The controller base address is the "Base" in QSys + 0x400
+- Set MSEL[4:0]=10010 (AS Standard)
+- Load the bitstream into FPGA, enable bridges
+- Only then will the driver work
diff --git a/doc/device-tree-bindings/mtd/spi/spi-flash.txt b/doc/device-tree-bindings/mtd/spi/spi-flash.txt
new file mode 100644
index 00000000000..85522d8011b
--- /dev/null
+++ b/doc/device-tree-bindings/mtd/spi/spi-flash.txt
@@ -0,0 +1,25 @@
+* MTD SPI driver for serial flash chips
+
+Required properties:
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+  representing partitions.
+- compatible : Should be the manufacturer and the name of the chip. Bear in
+               mind that the DT binding is not U-Boot-only, but in case of
+               U-Boot, see spi_flash_params_table table in
+               drivers/mtd/spi/sf_params.c for the list of supported chips.
+- reg : Chip-Select number
+- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
+
+Optional properties:
+ - memory-map : Address and size of the flash, if memory mapped. This may
+                apply to Intel chipsets, which tend to memory-map flash.
+
+Example:
+
+	flash: m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spansion,m25p80";
+		reg = <0>;
+		spi-max-frequency = <40000000>;
+	};
diff --git a/doc/device-tree-bindings/spi/soft-spi.txt b/doc/device-tree-bindings/spi/soft-spi.txt
new file mode 100644
index 00000000000..d09c1a50765
--- /dev/null
+++ b/doc/device-tree-bindings/spi/soft-spi.txt
@@ -0,0 +1,34 @@
+Soft SPI
+
+The soft SPI bus implementation allows the use of GPIO pins to simulate a
+SPI bus. No SPI host is required for this to work. The down-side is that the
+performance will typically be much lower than a real SPI bus.
+
+The soft SPI node requires the following properties:
+
+compatible: "u-boot,soft-spi"
+soft_spi_cs: GPIO number to use for SPI chip select (output)
+soft_spi_sclk: GPIO number to use for SPI clock (output)
+soft_spi_mosi: GPIO number to use for SPI MOSI line (output)
+soft_spi_miso GPIO number to use for SPI MISO line (input)
+spi-delay-us: Number of microseconds of delay between each CS transition
+
+The GPIOs should be specified as required by the GPIO controller referenced.
+The first cell holds the phandle of the controller and the second cell
+typically holds the GPIO number.
+
+
+Example:
+
+	soft-spi {
+		compatible = "u-boot,soft-spi";
+		cs-gpio = <&gpio 235 0>;	/* Y43 */
+		sclk-gpio = <&gpio 225 0>;	/* Y31 */
+		mosi-gpio = <&gpio 227 0>;	/* Y33 */
+		miso-gpio = <&gpio 224 0>;	/* Y30 */
+		spi-delay-us = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cs@0 {
+		};
+	};
diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt
index f9b68beb6f6..0278dda4d77 100644
--- a/doc/driver-model/README.txt
+++ b/doc/driver-model/README.txt
@@ -95,7 +95,7 @@ are provided in test/dm. To run them, try:
 You should see something like this:
 
     <...U-Boot banner...>
-    Running 21 driver model tests
+    Running 29 driver model tests
     Test: dm_test_autobind
     Test: dm_test_autoprobe
     Test: dm_test_bus_children
@@ -103,6 +103,7 @@ You should see something like this:
     Device 'c-test@0': seq 0 is in use by 'a-test'
     Device 'c-test@1': seq 1 is in use by 'd-test'
     Test: dm_test_bus_children_funcs
+    Test: dm_test_bus_children_iterators
     Test: dm_test_bus_parent_data
     Test: dm_test_bus_parent_ops
     Test: dm_test_children
@@ -114,7 +115,12 @@ You should see something like this:
     Device 'd-test': seq 3 is in use by 'b-test'
     Device 'a-test': seq 0 is in use by 'd-test'
     Test: dm_test_gpio
-    sandbox_gpio: sb_gpio_get_value: error: offset 4 not reserved
+    extra-gpios: get_value: error: gpio b5 not reserved
+    Test: dm_test_gpio_anon
+    Test: dm_test_gpio_copy
+    Test: dm_test_gpio_leak
+    extra-gpios: get_value: error: gpio b5 not reserved
+    Test: dm_test_gpio_requestf
     Test: dm_test_leak
     Test: dm_test_lifecycle
     Test: dm_test_operations
@@ -122,6 +128,26 @@ You should see something like this:
     Test: dm_test_platdata
     Test: dm_test_pre_reloc
     Test: dm_test_remove
+    Test: dm_test_spi_find
+    Invalid chip select 0:0 (err=-19)
+    SF: Failed to get idcodes
+    Device 'name-emul': seq 0 is in use by 'name-emul'
+    SF: Detected M25P16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB
+    Test: dm_test_spi_flash
+    2097152 bytes written in 0 ms
+    SF: Detected M25P16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB
+    SPI flash test:
+    0 erase: 0 ticks, 65536000 KiB/s 524288.000 Mbps
+    1 check: 0 ticks, 65536000 KiB/s 524288.000 Mbps
+    2 write: 0 ticks, 65536000 KiB/s 524288.000 Mbps
+    3 read: 0 ticks, 65536000 KiB/s 524288.000 Mbps
+    Test passed
+    0 erase: 0 ticks, 65536000 KiB/s 524288.000 Mbps
+    1 check: 0 ticks, 65536000 KiB/s 524288.000 Mbps
+    2 write: 0 ticks, 65536000 KiB/s 524288.000 Mbps
+    3 read: 0 ticks, 65536000 KiB/s 524288.000 Mbps
+    Test: dm_test_spi_xfer
+    SF: Detected M25P16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB
     Test: dm_test_uclass
     Test: dm_test_uclass_before_ready
     Failures: 0
@@ -358,7 +384,9 @@ Device Sequence Numbers
 U-Boot numbers devices from 0 in many situations, such as in the command
 line for I2C and SPI buses, and the device names for serial ports (serial0,
 serial1, ...). Driver model supports this numbering and permits devices
-to be locating by their 'sequence'.
+to be locating by their 'sequence'. This numbering unique identifies a
+device in its uclass, so no two devices within a particular uclass can have
+the same sequence number.
 
 Sequence numbers start from 0 but gaps are permitted. For example, a board
 may have I2C buses 0, 1, 4, 5 but no 2 or 3. The choice of how devices are
diff --git a/doc/driver-model/spi-howto.txt b/doc/driver-model/spi-howto.txt
new file mode 100644
index 00000000000..719dbd5cdd2
--- /dev/null
+++ b/doc/driver-model/spi-howto.txt
@@ -0,0 +1,594 @@
+How to port a SPI driver to driver model
+========================================
+
+Here is a rough step-by-step guide. It is based around converting the
+exynos SPI driver to driver model (DM) and the example code is based
+around U-Boot v2014.10-rc2 (commit be9f643).
+
+It is quite long since it includes actual code examples.
+
+Before driver model, SPI drivers have their own private structure which
+contains 'struct spi_slave'. With driver model, 'struct spi_slave' still
+exists, but now it is 'per-child data' for the SPI bus. Each child of the
+SPI bus is a SPI slave. The information that was stored in the
+driver-specific slave structure can now be port in private data for the
+SPI bus.
+
+For example, struct tegra_spi_slave looks like this:
+
+struct tegra_spi_slave {
+	struct spi_slave slave;
+	struct tegra_spi_ctrl *ctrl;
+};
+
+In this case 'slave' will be in per-child data, and 'ctrl' will be in the
+SPI's buses private data.
+
+
+0. How long does this take?
+
+You should be able to complete this within 2 hours, including testing but
+excluding preparing the patches. The API is basically the same as before
+with only minor changes:
+
+- methods to set speed and mode are separated out
+- cs_info is used to get information on a chip select
+
+
+1. Enable driver mode for SPI and SPI flash
+
+Add these to your board config:
+
+#define CONFIG_DM_SPI
+#define CONFIG_DM_SPI_FLASH
+
+
+2. Add the skeleton
+
+Put this code at the bottom of your existing driver file:
+
+struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
+			unsigned int max_hz, unsigned int mode)
+{
+	return NULL;
+}
+
+struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
+				      int spi_node)
+{
+	return NULL;
+}
+
+static int exynos_spi_ofdata_to_platdata(struct udevice *dev)
+{
+	return -ENODEV;
+}
+
+static int exynos_spi_probe(struct udevice *dev)
+{
+	return -ENODEV;
+}
+
+static int exynos_spi_remove(struct udevice *dev)
+{
+	return -ENODEV;
+}
+
+static int exynos_spi_claim_bus(struct udevice *dev)
+{
+
+	return -ENODEV;
+}
+
+static int exynos_spi_release_bus(struct udevice *dev)
+{
+
+	return -ENODEV;
+}
+
+static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
+			    const void *dout, void *din, unsigned long flags)
+{
+
+	return -ENODEV;
+}
+
+static int exynos_spi_set_speed(struct udevice *dev, uint speed)
+{
+	return -ENODEV;
+}
+
+static int exynos_spi_set_mode(struct udevice *dev, uint mode)
+{
+	return -ENODEV;
+}
+
+static int exynos_cs_info(struct udevice *bus, uint cs,
+			  struct spi_cs_info *info)
+{
+	return -ENODEV;
+}
+
+static const struct dm_spi_ops exynos_spi_ops = {
+	.claim_bus	= exynos_spi_claim_bus,
+	.release_bus	= exynos_spi_release_bus,
+	.xfer		= exynos_spi_xfer,
+	.set_speed	= exynos_spi_set_speed,
+	.set_mode	= exynos_spi_set_mode,
+	.cs_info	= exynos_cs_info,
+};
+
+static const struct udevice_id exynos_spi_ids[] = {
+	{ .compatible = "samsung,exynos-spi" },
+	{ }
+};
+
+U_BOOT_DRIVER(exynos_spi) = {
+	.name	= "exynos_spi",
+	.id	= UCLASS_SPI,
+	.of_match = exynos_spi_ids,
+	.ops	= &exynos_spi_ops,
+	.ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
+	.probe	= exynos_spi_probe,
+	.remove	= exynos_spi_remove,
+};
+
+
+3. Replace 'exynos' in the above code with your driver name
+
+
+4. #ifdef out all of the code in your driver except for the above
+
+This will allow you to get it building, which means you can work
+incrementally. Since all the methods return an error initially, there is
+less chance that you will accidentally leave something in.
+
+Also, even though your conversion is basically a rewrite, it might help
+reviewers if you leave functions in the same place in the file,
+particularly for large drivers.
+
+
+5. Add some includes
+
+Add these includes to your driver:
+
+#include <dm.h>
+#include <errno.h>
+
+
+6. Build
+
+At this point you should be able to build U-Boot for your board with the
+empty SPI driver. You still have empty methods in your driver, but we will
+write these one by one.
+
+If you have spi_init() functions or the like that are called from your
+board then the build will fail. Remove these calls and make a note of the
+init that needs to be done.
+
+
+7. Set up your platform data structure
+
+This will hold the information your driver to operate, like its hardware
+address or maximum frequency.
+
+You may already have a struct like this, or you may need to create one
+from some of the #defines or global variables in the driver.
+
+Note that this information is not the run-time information. It should not
+include state that changes. It should be fixed throughout the live of
+U-Boot. Run-time information comes later.
+
+Here is what was in the exynos spi driver:
+
+struct spi_bus {
+	enum periph_id periph_id;
+	s32 frequency;		/* Default clock frequency, -1 for none */
+	struct exynos_spi *regs;
+	int inited;		/* 1 if this bus is ready for use */
+	int node;
+	uint deactivate_delay_us;	/* Delay to wait after deactivate */
+};
+
+Of these, inited is handled by DM and node is the device tree node, which
+DM tells you. The name is not quite right. So in this case we would use:
+
+struct exynos_spi_platdata {
+	enum periph_id periph_id;
+	s32 frequency;		/* Default clock frequency, -1 for none */
+	struct exynos_spi *regs;
+	uint deactivate_delay_us;	/* Delay to wait after deactivate */
+};
+
+
+8a. Write ofdata_to_platdata()   [for device tree only]
+
+This method will convert information in the device tree node into a C
+structure in your driver (called platform data). If you are not using
+device tree, go to 8b.
+
+DM will automatically allocate the struct for us when we are using device
+tree, but we need to tell it the size:
+
+U_BOOT_DRIVER(spi_exynos) = {
+...
+	.platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata),
+
+
+Here is a sample function. It gets a pointer to the platform data and
+fills in the fields from device tree.
+
+static int exynos_spi_ofdata_to_platdata(struct udevice *bus)
+{
+	struct exynos_spi_platdata *plat = bus->platdata;
+	const void *blob = gd->fdt_blob;
+	int node = bus->of_offset;
+
+	plat->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
+	plat->periph_id = pinmux_decode_periph_id(blob, node);
+
+	if (plat->periph_id == PERIPH_ID_NONE) {
+		debug("%s: Invalid peripheral ID %d\n", __func__,
+			plat->periph_id);
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	/* Use 500KHz as a suitable default */
+	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+					500000);
+	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
+					"spi-deactivate-delay", 0);
+	debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+	      __func__, plat->regs, plat->periph_id, plat->frequency,
+              plat->deactivate_delay_us);
+
+	return 0;
+}
+
+
+8b. Add the platform data  [non-device-tree only]
+
+Specify this data in a U_BOOT_DEVICE() declaration in your board file:
+
+struct exynos_spi_platdata platdata_spi0 = {
+	.periph_id = ...
+	.frequency = ...
+	.regs = ...
+	.deactivate_delay_us = ...
+};
+
+U_BOOT_DEVICE(board_spi0) = {
+	.name = "exynos_spi",
+	.platdata = &platdata_spi0,
+};
+
+You will unfortunately need to put the struct into a header file in this
+case so that your board file can use it.
+
+
+9. Add the device private data
+
+Most devices have some private data which they use to keep track of things
+while active. This is the run-time information and needs to be stored in
+a structure. There is probably a structure in the driver that includes a
+'struct spi_slave', so you can use that.
+
+struct exynos_spi_slave {
+	struct spi_slave slave;
+	struct exynos_spi *regs;
+	unsigned int freq;		/* Default frequency */
+	unsigned int mode;
+	enum periph_id periph_id;	/* Peripheral ID for this device */
+	unsigned int fifo_size;
+	int skip_preamble;
+	struct spi_bus *bus;		/* Pointer to our SPI bus info */
+	ulong last_transaction_us;	/* Time of last transaction end */
+};
+
+
+We should rename this to make its purpose more obvious, and get rid of
+the slave structure, so we have:
+
+struct exynos_spi_priv {
+	struct exynos_spi *regs;
+	unsigned int freq;		/* Default frequency */
+	unsigned int mode;
+	enum periph_id periph_id;	/* Peripheral ID for this device */
+	unsigned int fifo_size;
+	int skip_preamble;
+	ulong last_transaction_us;	/* Time of last transaction end */
+};
+
+
+DM can auto-allocate this also:
+
+U_BOOT_DRIVER(spi_exynos) = {
+...
+	.priv_auto_alloc_size = sizeof(struct exynos_spi_priv),
+
+
+Note that this is created before the probe method is called, and destroyed
+after the remove method is called. It will be zeroed when the probe
+method is called.
+
+
+10. Add the probe() and remove() methods
+
+Note: It's a good idea to build repeatedly as you are working, to avoid a
+huge amount of work getting things compiling at the end.
+
+The probe method is supposed to set up the hardware. U-Boot used to use
+spi_setup_slave() to do this. So take a look at this function and see
+what you can copy out to set things up.
+
+
+static int exynos_spi_probe(struct udevice *bus)
+{
+	struct exynos_spi_platdata *plat = dev_get_platdata(bus);
+	struct exynos_spi_priv *priv = dev_get_priv(bus);
+
+	priv->regs = plat->regs;
+	if (plat->periph_id == PERIPH_ID_SPI1 ||
+	    plat->periph_id == PERIPH_ID_SPI2)
+		priv->fifo_size = 64;
+	else
+		priv->fifo_size = 256;
+
+	priv->skip_preamble = 0;
+	priv->last_transaction_us = timer_get_us();
+	priv->freq = plat->frequency;
+	priv->periph_id = plat->periph_id;
+
+	return 0;
+}
+
+This implementation doesn't actually touch the hardware, which is somewhat
+unusual for a driver. In this case we will do that when the device is
+claimed by something that wants to use the SPI bus.
+
+For remove we could shut down the clocks, but in this case there is
+nothing to do. DM frees any memory that it allocated, so we can just
+remove exynos_spi_remove() and its reference in U_BOOT_DRIVER.
+
+
+11. Implement set_speed()
+
+This should set up clocks so that the SPI bus is running at the right
+speed. With the old API spi_claim_bus() would normally do this and several
+of the following functions, so let's look at that function:
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+	struct exynos_spi *regs = spi_slave->regs;
+	u32 reg = 0;
+	int ret;
+
+	ret = set_spi_clk(spi_slave->periph_id,
+					spi_slave->freq);
+	if (ret < 0) {
+		debug("%s: Failed to setup spi clock\n", __func__);
+		return ret;
+	}
+
+	exynos_pinmux_config(spi_slave->periph_id, PINMUX_FLAG_NONE);
+
+	spi_flush_fifo(slave);
+
+	reg = readl(&regs->ch_cfg);
+	reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
+
+	if (spi_slave->mode & SPI_CPHA)
+		reg |= SPI_CH_CPHA_B;
+
+	if (spi_slave->mode & SPI_CPOL)
+		reg |= SPI_CH_CPOL_L;
+
+	writel(reg, &regs->ch_cfg);
+	writel(SPI_FB_DELAY_180, &regs->fb_clk);
+
+	return 0;
+}
+
+
+It sets up the speed, mode, pinmux, feedback delay and clears the FIFOs.
+With DM these will happen in separate methods.
+
+
+Here is an example for the speed part:
+
+static int exynos_spi_set_speed(struct udevice *bus, uint speed)
+{
+	struct exynos_spi_platdata *plat = bus->platdata;
+	struct exynos_spi_priv *priv = dev_get_priv(bus);
+	int ret;
+
+	if (speed > plat->frequency)
+		speed = plat->frequency;
+	ret = set_spi_clk(priv->periph_id, speed);
+	if (ret)
+		return ret;
+	priv->freq = speed;
+	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
+
+	return 0;
+}
+
+
+12. Implement set_mode()
+
+This should adjust the SPI mode (polarity, etc.). Again this code probably
+comes from the old spi_claim_bus(). Here is an example:
+
+
+static int exynos_spi_set_mode(struct udevice *bus, uint mode)
+{
+	struct exynos_spi_priv *priv = dev_get_priv(bus);
+	uint32_t reg;
+
+	reg = readl(&priv->regs->ch_cfg);
+	reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
+
+	if (mode & SPI_CPHA)
+		reg |= SPI_CH_CPHA_B;
+
+	if (mode & SPI_CPOL)
+		reg |= SPI_CH_CPOL_L;
+
+	writel(reg, &priv->regs->ch_cfg);
+	priv->mode = mode;
+	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+
+	return 0;
+}
+
+
+13. Implement claim_bus()
+
+This is where a client wants to make use of the bus, so claims it first.
+At this point we need to make sure everything is set up ready for data
+transfer. Note that this function is wholly internal to the driver - at
+present the SPI uclass never calls it.
+
+Here again we look at the old claim function and see some code that is
+needed. It is anything unrelated to speed and mode:
+
+static int exynos_spi_claim_bus(struct udevice *bus)
+{
+	struct exynos_spi_priv *priv = dev_get_priv(bus);
+
+	exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE);
+	spi_flush_fifo(priv->regs);
+
+	writel(SPI_FB_DELAY_180, &priv->regs->fb_clk);
+
+	return 0;
+}
+
+The spi_flush_fifo() function is in the removed part of the code, so we
+need to expose it again (perhaps with an #endif before it and '#if 0'
+after it). It only needs access to priv->regs which is why we have
+passed that in:
+
+/**
+ * Flush spi tx, rx fifos and reset the SPI controller
+ *
+ * @param regs	Pointer to SPI registers
+ */
+static void spi_flush_fifo(struct exynos_spi *regs)
+{
+	clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
+	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
+	setbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
+}
+
+
+14. Implement release_bus()
+
+This releases the bus - in our example the old code in spi_release_bus()
+is a call to spi_flush_fifo, so we add:
+
+static int exynos_spi_release_bus(struct udevice *bus)
+{
+	struct exynos_spi_priv *priv = dev_get_priv(bus);
+
+	spi_flush_fifo(priv->regs);
+
+	return 0;
+}
+
+
+15. Implement xfer()
+
+This is the final method that we need to create, and it is where all the
+work happens. The method parameters are the same as the old spi_xfer() with
+the addition of a 'struct udevice' so conversion is pretty easy. Start
+by copying the contents of spi_xfer() to your new xfer() method and proceed
+from there.
+
+If (flags & SPI_XFER_BEGIN) is non-zero then xfer() normally calls an
+activate function, something like this:
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+
+	/* If it's too soon to do another transaction, wait */
+	if (spi_slave->bus->deactivate_delay_us &&
+	    spi_slave->last_transaction_us) {
+		ulong delay_us;		/* The delay completed so far */
+		delay_us = timer_get_us() - spi_slave->last_transaction_us;
+		if (delay_us < spi_slave->bus->deactivate_delay_us)
+			udelay(spi_slave->bus->deactivate_delay_us - delay_us);
+	}
+
+	clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
+	debug("Activate CS, bus %d\n", spi_slave->slave.bus);
+	spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
+}
+
+The new version looks like this:
+
+static void spi_cs_activate(struct udevice *dev)
+{
+	struct udevice *bus = dev->parent;
+	struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
+	struct exynos_spi_priv *priv = dev_get_priv(bus);
+
+	/* If it's too soon to do another transaction, wait */
+	if (pdata->deactivate_delay_us &&
+	    priv->last_transaction_us) {
+		ulong delay_us;		/* The delay completed so far */
+		delay_us = timer_get_us() - priv->last_transaction_us;
+		if (delay_us < pdata->deactivate_delay_us)
+			udelay(pdata->deactivate_delay_us - delay_us);
+	}
+
+	clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
+	debug("Activate CS, bus '%s'\n", bus->name);
+	priv->skip_preamble = priv->mode & SPI_PREAMBLE;
+}
+
+All we have really done here is change the pointers and print the device name
+instead of the bus number. Other local static functions can be treated in
+the same way.
+
+
+16. Set up the per-child data and child pre-probe function
+
+To minimise the pain and complexity of the SPI subsystem while the driver
+model change-over is in place, struct spi_slave is used to reference a
+SPI bus slave, even though that slave is actually a struct udevice. In fact
+struct spi_slave is the device's child data. We need to make sure this space
+is available. It is possible to allocate more space that struct spi_slave
+needs, but this is the minimum.
+
+U_BOOT_DRIVER(exynos_spi) = {
+...
+	.per_child_auto_alloc_size	= sizeof(struct spi_slave),
+}
+
+
+17. Optional: Set up cs_info() if you want it
+
+Sometimes it is useful to know whether a SPI chip select is valid, but this
+is not obvious from outside the driver. In this case you can provide a
+method for cs_info() to deal with this. If you don't provide it, then the
+device tree will be used to determine what chip selects are valid.
+
+Return -ENODEV if the supplied chip select is invalid, or 0 if it is valid.
+If you don't provide the cs_info() method, -ENODEV is assumed for all
+chip selects that do not appear in the device tree.
+
+
+18. Test it
+
+Now that you have the code written and it compiles, try testing it using
+the 'sf test' command. You may need to enable CONFIG_CMD_SF_TEST for your
+board.
+
+
+19. Prepare patches and send them to the mailing lists
+
+You can use 'tools/patman/patman' to prepare, check and send patches for
+your work. See the README for details.
diff --git a/doc/git-mailrc b/doc/git-mailrc
index 35f2eb2fc1f..ad22763960c 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -31,6 +31,7 @@ alias masahiro       Masahiro Yamada <yamada.m@jp.panasonic.com>
 alias monstr         Michal Simek <monstr@monstr.eu>
 alias panto          Pantelis Antoniou <panto@antoniou-consulting.com>
 alias prafulla       Prafulla Wadaskar <prafulla@marvell.com>
+alias bobenstein     Przemyslaw Marczak <p.marczak@samsung.com>
 alias prom           Minkyu Kang <mk7.kang@samsung.com>
 alias rbohmer        Remy Bohmer <linux@bohmer.net>
 alias reinhardm      Reinhard Meyer <u-boot@emk-elektronik.de>
@@ -122,3 +123,4 @@ alias usb            uboot, marex
 alias video          uboot, ag
 alias patman         uboot, sjg
 alias buildman       uboot, sjg
+alias pmic           uboot, bobenstein
diff --git a/doc/mkimage.1 b/doc/mkimage.1
index 14374da88af..b48f70bb3cc 100644
--- a/doc/mkimage.1
+++ b/doc/mkimage.1
@@ -115,7 +115,7 @@ FIT image.
 .TP
 .BI "\-F"
 Indicates that an existing FIT image should be modified. No dtc
-compilation is performed and the -f flag should not be given.
+compilation is performed and the \-f flag should not be given.
 This can be used to sign images with additional keys after initial image
 creation.
 
@@ -163,7 +163,8 @@ Create FIT image with compressed kernel and sign it with keys in the
 skipping those for which keys cannot be found. Also add a comment.
 .nf
 .B mkimage -f kernel.its -k /public/signing-keys -K u-boot.dtb \\\\
--c "Kernel 3.8 image for production devices" kernel.itb
+.br
+.B -c "Kernel 3.8 image for production devices" kernel.itb
 .fi
 
 .P
@@ -173,7 +174,8 @@ with keys that are available in the new directory. Images that request signing
 with unavailable keys are skipped.
 .nf
 .B mkimage -F -k /secret/signing-keys -K u-boot.dtb \\\\
--c "Kernel 3.8 image for production devices" kernel.itb
+.br
+.B -c "Kernel 3.8 image for production devices" kernel.itb
 .fi
 
 .SH HOMEPAGE
diff --git a/doc/uImage.FIT/kernel.its b/doc/uImage.FIT/kernel.its
index ef3ab8f726a..539cdbfafec 100644
--- a/doc/uImage.FIT/kernel.its
+++ b/doc/uImage.FIT/kernel.its
@@ -35,3 +35,53 @@
 		};
 	};
 };
+
+
+
+For x86 a setup node is also required: see x86-fit-boot.txt.
+
+/dts-v1/;
+
+/ {
+	description = "Simple image with single Linux kernel on x86";
+	#address-cells = <1>;
+
+	images {
+		kernel@1 {
+			description = "Vanilla Linux kernel";
+			data = /incbin/("./image.bin.lzo");
+			type = "kernel";
+			arch = "x86";
+			os = "linux";
+			compression = "lzo";
+			load = <0x01000000>;
+			entry = <0x00000000>;
+			hash@2 {
+				algo = "sha1";
+			};
+		};
+
+		setup@1 {
+			description = "Linux setup.bin";
+			data = /incbin/("./setup.bin");
+			type = "x86_setup";
+			arch = "x86";
+			os = "linux";
+			compression = "none";
+			load = <0x00090000>;
+			entry = <0x00090000>;
+			hash@2 {
+				algo = "sha1";
+			};
+		};
+	};
+
+	configurations {
+		default = "config@1";
+		config@1 {
+			description = "Boot Linux kernel";
+			kernel = "kernel@1";
+			setup = "setup@1";
+		};
+	};
+};
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt
index 9ed6f65e599..b47ce73b832 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -55,7 +55,7 @@ FIT is formally a flattened device tree (in the libfdt meaning), which
 conforms to bindings defined in this document.
 
 .its	- image tree source
-.itb	- image tree blob
+.fit	- flattened image tree blob
 
 c) Image building procedure
 
@@ -101,15 +101,15 @@ Root node of the uImage Tree should have the following layout:
     |
     o images
     | |
-    | o img@1 {...}
-    | o img@2 {...}
+    | o image@1 {...}
+    | o image@2 {...}
     | ...
     |
     o configurations
-      |- default = "cfg@1"
+      |- default = "conf@1"
       |
-      o cfg@1 {...}
-      o cfg@2 {...}
+      o conf@1 {...}
+      o conf@2 {...}
       ...
 
 
@@ -159,7 +159,7 @@ the '/images' node should have the following layout:
   - description : Textual description of the component sub-image
   - type : Name of component sub-image type, supported types are:
     "standalone", "kernel", "ramdisk", "firmware", "script", "filesystem",
-    "flat_dt".
+    "flat_dt" and others (see uimage_type in common/images.c).
   - data : Path to the external file which contains this node's binary data.
   - compression : Compression used by included data. Supported compressions
     are "gzip" and "bzip2". If no compression is used compression property
@@ -173,7 +173,8 @@ the '/images' node should have the following layout:
   - arch : Architecture name, mandatory for types: "standalone", "kernel",
     "firmware", "ramdisk" and "fdt". Valid architecture names are: "alpha",
     "arm", "i386", "ia64", "mips", "mips64", "ppc", "s390", "sh", "sparc",
-    "sparc64", "m68k", "microblaze", "nios2", "blackfin", "avr32", "st200".
+    "sparc64", "m68k", "microblaze", "nios2", "blackfin", "avr32", "st200",
+    "sandbox".
   - entry : entry point address, address size is determined by
     '#address-cells' property of the root node. Mandatory for for types:
     "standalone" and "kernel".
@@ -246,6 +247,8 @@ o config@1
     node of a "ramdisk" type).
   - fdt : Unit name of the corresponding fdt blob (component image node of a
     "fdt type").
+  - setup : Unit name of the corresponding setup binary (used for booting
+    an x86 kernel). This contains the setup.bin file built by the kernel.
 
 The FDT blob is required to properly boot FDT based kernel, so the minimal
 configuration for 2.6 FDT kernel is (kernel, fdt) pair.
diff --git a/doc/uImage.FIT/x86-fit-boot.txt b/doc/uImage.FIT/x86-fit-boot.txt
new file mode 100644
index 00000000000..61c10ff7c25
--- /dev/null
+++ b/doc/uImage.FIT/x86-fit-boot.txt
@@ -0,0 +1,276 @@
+Booting Linux on x86 with FIT
+=============================
+
+Background
+----------
+
+(corrections to the text below are welcome)
+
+Generally Linux x86 uses its own very complex booting method. There is a setup
+binary which contains all sorts of parameters and a compressed self-extracting
+binary for the kernel itself, often with a small built-in serial driver to
+display decompression progress.
+
+The x86 CPU has various processor modes. I am no expert on these, but my
+understanding is that an x86 CPU (even a really new one) starts up in a 16-bit
+'real' mode where only 1MB of memory is visible, moves to 32-bit 'protected'
+mode where 4GB is visible (or more with special memory access techniques) and
+then to 64-bit 'long' mode if 64-bit execution is required.
+
+Partly the self-extracting nature of Linux was introduced to cope with boot
+loaders that were barely capable of loading anything. Even changing to 32-bit
+mode was something of a challenge, so putting this logic in the kernel seemed
+to make sense.
+
+Bit by bit more and more logic has been added to this post-boot pre-Linux
+wrapper:
+
+- Changing to 32-bit mode
+- Decompression
+- Serial output (with drivers for various chips)
+- Load address randomisation
+- Elf loader complete with relocation (for the above)
+- Random number generator via 3 methods (again for the above)
+- Some sort of EFI mini-loader (1000+ glorious lines of code)
+- Locating and tacking on a device tree and ramdisk
+
+To my mind, if you sit back and look at things from first principles, this
+doesn't make a huge amount of sense. Any boot loader worth its salts already
+has most of the above features and more besides. The boot loader already knows
+the layout of memory, has a serial driver, can decompress things, includes an
+ELF loader and supports device tree and ramdisks. The decision to duplicate
+all these features in a Linux wrapper caters for the lowest common
+denominator: a boot loader which consists of a BIOS call to load something off
+disk, followed by a jmp instruction.
+
+(Aside: On ARM systems, we worry that the boot loader won't know where to load
+the kernel. It might be easier to just provide that information in the image,
+or in the boot loader rather than adding a self-relocator to put it in the
+right place. Or just use ELF?
+
+As a result, the x86 kernel boot process is needlessly complex. The file
+format is also complex, and obfuscates the contents to a degree that it is
+quite a challenge to extract anything from it. This bzImage format has become
+so prevalent that is actually isn't possible to produce the 'raw' kernel build
+outputs with the standard Makefile (as it is on ARM for example, at least at
+the time of writing).
+
+This document describes an alternative boot process which uses simple raw
+images which are loaded into the right place by the boot loader and then
+executed.
+
+
+Build the kernel
+----------------
+
+Note: these instructions assume a 32-bit kernel. U-Boot does not currently
+support booting a 64-bit kernel as it has no way of going into 64-bit mode on
+x86.
+
+You can build the kernel as normal with 'make'. This will create a file called
+'vmlinux'. This is a standard ELF file and you can look at it if you like:
+
+$ objdump -h vmlinux
+
+vmlinux:     file format elf32-i386
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00416850  81000000  01000000  00001000  2**5
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  1 .notes        00000024  81416850  01416850  00417850  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  2 __ex_table    00000c50  81416880  01416880  00417880  2**3
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+  3 .rodata       00154b9e  81418000  01418000  00419000  2**5
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+  4 __bug_table   0000597c  8156cba0  0156cba0  0056dba0  2**0
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+  5 .pci_fixup    00001b80  8157251c  0157251c  0057351c  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+  6 .tracedata    00000024  8157409c  0157409c  0057509c  2**0
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+  7 __ksymtab     00007ec0  815740c0  015740c0  005750c0  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+  8 __ksymtab_gpl 00004a28  8157bf80  0157bf80  0057cf80  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+  9 __ksymtab_strings 0001d6fc  815809a8  015809a8  005819a8  2**0
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 10 __init_rodata 00001c3c  8159e0a4  0159e0a4  0059f0a4  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 11 __param       00000ff0  8159fce0  0159fce0  005a0ce0  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 12 __modver      00000330  815a0cd0  015a0cd0  005a1cd0  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 13 .data         00063000  815a1000  015a1000  005a2000  2**12
+                  CONTENTS, ALLOC, LOAD, RELOC, DATA
+ 14 .init.text    0002f104  81604000  01604000  00605000  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 15 .init.data    00040cdc  81634000  01634000  00635000  2**12
+                  CONTENTS, ALLOC, LOAD, RELOC, DATA
+ 16 .x86_cpu_dev.init 0000001c  81674cdc  01674cdc  00675cdc  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 17 .altinstructions 0000267c  81674cf8  01674cf8  00675cf8  2**0
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 18 .altinstr_replacement 00000942  81677374  01677374  00678374  2**0
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 19 .iommu_table  00000014  81677cb8  01677cb8  00678cb8  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 20 .apicdrivers  00000004  81677cd0  01677cd0  00678cd0  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, DATA
+ 21 .exit.text    00001a80  81677cd8  01677cd8  00678cd8  2**0
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ 22 .data..percpu 00007880  8167a000  0167a000  0067b000  2**12
+                  CONTENTS, ALLOC, LOAD, RELOC, DATA
+ 23 .smp_locks    00003000  81682000  01682000  00683000  2**2
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
+ 24 .bss          000a1000  81685000  01685000  00686000  2**12
+                  ALLOC
+ 25 .brk          00424000  81726000  01726000  00686000  2**0
+                  ALLOC
+ 26 .comment      00000049  00000000  00000000  00686000  2**0
+                  CONTENTS, READONLY
+ 27 .GCC.command.line 0003e055  00000000  00000000  00686049  2**0
+                  CONTENTS, READONLY
+ 28 .debug_aranges 0000f4c8  00000000  00000000  006c40a0  2**3
+                  CONTENTS, RELOC, READONLY, DEBUGGING
+ 29 .debug_info   0440b0df  00000000  00000000  006d3568  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING
+ 30 .debug_abbrev 0022a83b  00000000  00000000  04ade647  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 31 .debug_line   004ead0d  00000000  00000000  04d08e82  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING
+ 32 .debug_frame  0010a960  00000000  00000000  051f3b90  2**2
+                  CONTENTS, RELOC, READONLY, DEBUGGING
+ 33 .debug_str    001b442d  00000000  00000000  052fe4f0  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 34 .debug_loc    007c7fa9  00000000  00000000  054b291d  2**0
+                  CONTENTS, RELOC, READONLY, DEBUGGING
+ 35 .debug_ranges 00098828  00000000  00000000  05c7a8c8  2**3
+                  CONTENTS, RELOC, READONLY, DEBUGGING
+
+There is also the setup binary mentioned earlier. This is at
+arch/x86/boot/setup.bin and is about 12KB in size. It includes the command
+line and various settings need by the kernel. Arguably the boot loader should
+provide all of this also, but setting it up is some complex that the kernel
+helps by providing a head start.
+
+As you can see the code loads to address 0x01000000 and everything else
+follows after that. We could load this image using the 'bootelf' command but
+we would still need to provide the setup binary. This is not supported by
+U-Boot although I suppose you could mostly script it. This would permit the
+use of a relocatable kernel.
+
+All we need to boot is the vmlinux file and the setup.bin file.
+
+
+Create a FIT
+------------
+
+To create a FIT you will need a source file describing what should go in the
+FIT. See kernel.its for an example for x86. Put this into a file called
+image.its.
+
+Note that setup is loaded to the special address of 0x90000 (a special address
+you just have to know) and the kernel is loaded to 0x01000000 (the address you
+saw above). This means that you will need to load your FIT to a different
+address so that U-Boot doesn't overwrite it when decompressing. Something like
+0x02000000 will do so you can set CONFIG_SYS_LOAD_ADDR to that.
+
+In that example the kernel is compressed with lzo. Also we need to provide a
+flat binary, not an ELF. So the steps needed to set things are are:
+
+   # Create a flat binary
+   objcopy -O binary vmlinux vmlinux.bin
+
+   # Compress it into LZO format
+   lzop vmlinux.bin
+
+   # Build a FIT image
+   mkimage -f image.its image.fit
+
+(be careful to run the mkimage from your U-Boot tools directory since it
+will have x86_setup support.)
+
+You can take a look at the resulting fit file if you like:
+
+$ dumpimage -l image.fit
+FIT description: Simple image with single Linux kernel on x86
+Created:         Tue Oct  7 10:57:24 2014
+ Image 0 (kernel@1)
+  Description:  Vanilla Linux kernel
+  Created:      Tue Oct  7 10:57:24 2014
+  Type:         Kernel Image
+  Compression:  lzo compressed
+  Data Size:    4591767 Bytes = 4484.15 kB = 4.38 MB
+  Architecture: Intel x86
+  OS:           Linux
+  Load Address: 0x01000000
+  Entry Point:  0x00000000
+  Hash algo:    sha1
+  Hash value:   446b5163ebfe0fb6ee20cbb7a8501b263cd92392
+ Image 1 (setup@1)
+  Description:  Linux setup.bin
+  Created:      Tue Oct  7 10:57:24 2014
+  Type:         x86 setup.bin
+  Compression:  uncompressed
+  Data Size:    12912 Bytes = 12.61 kB = 0.01 MB
+  Hash algo:    sha1
+  Hash value:   a1f2099cf47ff9816236cd534c77af86e713faad
+ Default Configuration: 'config@1'
+ Configuration 0 (config@1)
+  Description:  Boot Linux kernel
+  Kernel:       kernel@1
+
+
+Booting the FIT
+---------------
+
+To make it boot you need to load it and then use 'bootm' to boot it. A
+suitable script to do this from a network server is:
+
+   bootp
+   tftp image.fit
+   bootm
+
+This will load the image from the network and boot it. The command line (from
+the 'bootargs' environment variable) will be passed to the kernel.
+
+If you want a ramdisk you can add it as normal with FIT. If you want a device
+tree then x86 doesn't normally use those - it has ACPI instead.
+
+
+Why Bother?
+-----------
+
+1. It demystifies the process of booting an x86 kernel
+2. It allows use of the standard U-Boot boot file format
+3. It allows U-Boot to perform decompression - problems will provide an error
+message and you are still in the boot loader. It is possible to investigate.
+4. It avoids all the pre-loader code in the kernel which is quite complex to
+follow
+5. You can use verified/secure boot and other features which haven't yet been
+added to the pre-Linux
+6. It makes x86 more like other architectures in the way it boots a kernel.
+You can potentially use the same file format for the kernel, and the same
+procedure for building and packaging it.
+
+
+References
+----------
+
+In the Linux kernel, Documentation/x86/boot.txt defines the boot protocol for
+the kernel including the setup.bin format. This is handled in U-Boot in
+arch/x86/lib/zimage.c and arch/x86/lib/bootm.c.
+
+The procedure for entering 64-bit mode on x86 seems to be described here:
+
+   http://wiki.osdev.org/64-bit_Higher_Half_Kernel_with_GRUB_2
+
+Various files in the same directory as this file describe the FIT format.
+
+
+--
+Simon Glass
+sjg@chromium.org
+7-Oct-2014
diff --git a/drivers/Makefile b/drivers/Makefile
index d8361d95fd1..33227c8bd6d 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -19,3 +19,5 @@ obj-$(CONFIG_QE) += qe/
 obj-y += memory/
 obj-y += pwm/
 obj-y += input/
+# SOC specific infrastructure drivers.
+obj-y += soc/
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index 29f478bfbe0..c68fd2f2565 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -878,7 +878,7 @@ int sata_port_status(int dev, int port)
 	probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
 	port_mmio = (struct sata_port_regs *)probe_ent->port[port].port_mmio;
 
-	return readl(&(port_mmio->ssts)) && SATA_PORT_SSTS_DET_MASK;
+	return readl(&(port_mmio->ssts)) & SATA_PORT_SSTS_DET_MASK;
 }
 
 /*
diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
index 574bc40b10e..e54d564bf76 100644
--- a/drivers/block/mvsata_ide.c
+++ b/drivers/block/mvsata_ide.c
@@ -12,7 +12,7 @@
 #if defined(CONFIG_ORION5X)
 #include <asm/arch/orion5x.h>
 #elif defined(CONFIG_KIRKWOOD)
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #endif
 
 /* SATA port registers */
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index e69de29bb2d..d2799dc861f 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -0,0 +1,6 @@
+config DM
+	bool "Enable Driver Model"
+	depends on !SPL_BUILD
+	help
+	  This config option enables Driver Model.
+	  To use legacy drivers, say N.
diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index c7905b14409..151c2398a4d 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y := device.o lists.o root.o uclass.o util.o
+obj-$(CONFIG_OF_CONTROL) += simple-bus.o
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 32e80e82b59..49faa29dc1a 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -232,7 +232,7 @@ static void device_free(struct udevice *dev)
 	}
 }
 
-int device_probe(struct udevice *dev)
+int device_probe_child(struct udevice *dev, void *parent_priv)
 {
 	struct driver *drv;
 	int size = 0;
@@ -282,6 +282,8 @@ int device_probe(struct udevice *dev)
 				ret = -ENOMEM;
 				goto fail;
 			}
+			if (parent_priv)
+				memcpy(dev->parent_priv, parent_priv, size);
 		}
 
 		ret = device_probe(dev->parent);
@@ -335,6 +337,11 @@ fail:
 	return ret;
 }
 
+int device_probe(struct udevice *dev)
+{
+	return device_probe_child(dev, NULL);
+}
+
 int device_remove(struct udevice *dev)
 {
 	struct driver *drv;
@@ -514,3 +521,30 @@ int device_get_child_by_of_offset(struct udevice *parent, int seq,
 	ret = device_find_child_by_of_offset(parent, seq, &dev);
 	return device_get_device_tail(dev, ret, devp);
 }
+
+int device_find_first_child(struct udevice *parent, struct udevice **devp)
+{
+	if (list_empty(&parent->child_head)) {
+		*devp = NULL;
+	} else {
+		*devp = list_first_entry(&parent->child_head, struct udevice,
+					 sibling_node);
+	}
+
+	return 0;
+}
+
+int device_find_next_child(struct udevice **devp)
+{
+	struct udevice *dev = *devp;
+	struct udevice *parent = dev->parent;
+
+	if (list_is_last(&dev->sibling_node, &parent->child_head)) {
+		*devp = NULL;
+	} else {
+		*devp = list_entry(dev->sibling_node.next, struct udevice,
+				   sibling_node);
+	}
+
+	return 0;
+}
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index 699f94b435f..3a1ea856544 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -24,19 +24,12 @@ struct driver *lists_driver_lookup_name(const char *name)
 		ll_entry_start(struct driver, driver);
 	const int n_ents = ll_entry_count(struct driver, driver);
 	struct driver *entry;
-	int len;
 
 	if (!drv || !n_ents)
 		return NULL;
 
-	len = strlen(name);
-
 	for (entry = drv; entry != drv + n_ents; entry++) {
-		if (strncmp(name, entry->name, len))
-			continue;
-
-		/* Full match */
-		if (len == strlen(entry->name))
+		if (!strcmp(name, entry->name))
 			return entry;
 	}
 
diff --git a/drivers/core/simple-bus.c b/drivers/core/simple-bus.c
new file mode 100644
index 00000000000..3ea4d8230bd
--- /dev/null
+++ b/drivers/core/simple-bus.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/root.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int simple_bus_post_bind(struct udevice *dev)
+{
+	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+}
+
+UCLASS_DRIVER(simple_bus) = {
+	.id		= UCLASS_SIMPLE_BUS,
+	.name		= "simple_bus",
+	.post_bind	= simple_bus_post_bind,
+};
+
+static const struct udevice_id generic_simple_bus_ids[] = {
+	{ .compatible = "simple-bus" },
+	{ }
+};
+
+U_BOOT_DRIVER(simple_bus_drv) = {
+	.name	= "generic_simple_bus",
+	.id	= UCLASS_SIMPLE_BUS,
+	.of_match = generic_simple_bus_ids,
+};
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 61ca17e564a..901b06ed2ba 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -60,10 +60,6 @@ static int uclass_add(enum uclass_id id, struct uclass **ucp)
 			id);
 		return -ENOENT;
 	}
-	if (uc_drv->ops) {
-		dm_warn("No ops for uclass id %d\n", id);
-		return -EINVAL;
-	}
 	uc = calloc(1, sizeof(*uc));
 	if (!uc)
 		return -ENOMEM;
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index b8077953c56..7b792371811 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -6,3 +6,4 @@
 #
 
 obj-$(CONFIG_EXYNOS_ACE_SHA)	+= ace_sha.o
+obj-y += fsl/
diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
new file mode 100644
index 00000000000..cb13d2e0ae6
--- /dev/null
+++ b/drivers/crypto/fsl/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# Version 2 as published by the Free Software Foundation.
+#
+
+obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o
+obj-$(CONFIG_CMD_BLOB) += fsl_blob.o
diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h
new file mode 100644
index 00000000000..504f2b07d09
--- /dev/null
+++ b/drivers/crypto/fsl/desc.h
@@ -0,0 +1,651 @@
+/*
+ * CAAM descriptor composition header
+ * Definitions to support CAAM descriptor instruction generation
+ *
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Based on desc.h file in linux drivers/crypto/caam
+ */
+
+#ifndef DESC_H
+#define DESC_H
+
+/* Max size of any CAAM descriptor in 32-bit words, inclusive of header */
+#define MAX_CAAM_DESCSIZE	64
+
+/* Block size of any entity covered/uncovered with a KEK/TKEK */
+#define KEK_BLOCKSIZE		16
+/*
+ * Supported descriptor command types as they show up
+ * inside a descriptor command word.
+ */
+#define CMD_SHIFT		27
+#define CMD_MASK		0xf8000000
+
+#define CMD_KEY			(0x00 << CMD_SHIFT)
+#define CMD_SEQ_KEY		(0x01 << CMD_SHIFT)
+#define CMD_LOAD		(0x02 << CMD_SHIFT)
+#define CMD_SEQ_LOAD		(0x03 << CMD_SHIFT)
+#define CMD_FIFO_LOAD		(0x04 << CMD_SHIFT)
+#define CMD_SEQ_FIFO_LOAD	(0x05 << CMD_SHIFT)
+#define CMD_STORE		(0x0a << CMD_SHIFT)
+#define CMD_SEQ_STORE		(0x0b << CMD_SHIFT)
+#define CMD_FIFO_STORE		(0x0c << CMD_SHIFT)
+#define CMD_SEQ_FIFO_STORE	(0x0d << CMD_SHIFT)
+#define CMD_MOVE_LEN		(0x0e << CMD_SHIFT)
+#define CMD_MOVE		(0x0f << CMD_SHIFT)
+#define CMD_OPERATION		(0x10 << CMD_SHIFT)
+#define CMD_SIGNATURE		(0x12 << CMD_SHIFT)
+#define CMD_JUMP		(0x14 << CMD_SHIFT)
+#define CMD_MATH		(0x15 << CMD_SHIFT)
+#define CMD_DESC_HDR		(0x16 << CMD_SHIFT)
+#define CMD_SHARED_DESC_HDR	(0x17 << CMD_SHIFT)
+#define CMD_SEQ_IN_PTR		(0x1e << CMD_SHIFT)
+#define CMD_SEQ_OUT_PTR		(0x1f << CMD_SHIFT)
+
+/* General-purpose class selector for all commands */
+#define CLASS_SHIFT		25
+#define CLASS_MASK		(0x03 << CLASS_SHIFT)
+
+#define CLASS_NONE		(0x00 << CLASS_SHIFT)
+#define CLASS_1			(0x01 << CLASS_SHIFT)
+#define CLASS_2			(0x02 << CLASS_SHIFT)
+#define CLASS_BOTH		(0x03 << CLASS_SHIFT)
+
+/*
+ * Descriptor header command constructs
+ * Covers shared, job, and trusted descriptor headers
+ */
+
+/*
+ * Do Not Run - marks a descriptor inexecutable if there was
+ * a preceding error somewhere
+ */
+#define HDR_DNR			0x01000000
+
+/*
+ * ONE - should always be set. Combination of ONE (always
+ * set) and ZRO (always clear) forms an endianness sanity check
+ */
+#define HDR_ONE			0x00800000
+#define HDR_ZRO			0x00008000
+
+/* Start Index or SharedDesc Length */
+#define HDR_START_IDX_MASK	0x3f
+#define HDR_START_IDX_SHIFT	16
+
+/* If shared descriptor header, 6-bit length */
+#define HDR_DESCLEN_SHR_MASK	0x3f
+
+/* If non-shared header, 7-bit length */
+#define HDR_DESCLEN_MASK	0x7f
+
+/* This is a TrustedDesc (if not SharedDesc) */
+#define HDR_TRUSTED		0x00004000
+
+/* Make into TrustedDesc (if not SharedDesc) */
+#define HDR_MAKE_TRUSTED	0x00002000
+
+/* Save context if self-shared (if SharedDesc) */
+#define HDR_SAVECTX		0x00001000
+
+/* Next item points to SharedDesc */
+#define HDR_SHARED		0x00001000
+
+/*
+ * Reverse Execution Order - execute JobDesc first, then
+ * execute SharedDesc (normally SharedDesc goes first).
+ */
+#define HDR_REVERSE		0x00000800
+
+/* Propogate DNR property to SharedDesc */
+#define HDR_PROP_DNR		0x00000800
+
+/* JobDesc/SharedDesc share property */
+#define HDR_SD_SHARE_MASK	0x03
+#define HDR_SD_SHARE_SHIFT	8
+#define HDR_JD_SHARE_MASK	0x07
+#define HDR_JD_SHARE_SHIFT	8
+
+#define HDR_SHARE_NEVER		(0x00 << HDR_SD_SHARE_SHIFT)
+#define HDR_SHARE_WAIT		(0x01 << HDR_SD_SHARE_SHIFT)
+#define HDR_SHARE_SERIAL	(0x02 << HDR_SD_SHARE_SHIFT)
+#define HDR_SHARE_ALWAYS	(0x03 << HDR_SD_SHARE_SHIFT)
+#define HDR_SHARE_DEFER		(0x04 << HDR_SD_SHARE_SHIFT)
+
+/* JobDesc/SharedDesc descriptor length */
+#define HDR_JD_LENGTH_MASK	0x7f
+#define HDR_SD_LENGTH_MASK	0x3f
+
+/*
+ * KEY/SEQ_KEY Command Constructs
+ */
+
+/* Key Destination Class: 01 = Class 1, 02 - Class 2 */
+#define KEY_DEST_CLASS_SHIFT	25	/* use CLASS_1 or CLASS_2 */
+#define KEY_DEST_CLASS_MASK	(0x03 << KEY_DEST_CLASS_SHIFT)
+
+/* Scatter-Gather Table/Variable Length Field */
+#define KEY_SGF			0x01000000
+#define KEY_VLF			0x01000000
+
+/* Immediate - Key follows command in the descriptor */
+#define KEY_IMM			0x00800000
+
+/*
+ * Encrypted - Key is encrypted either with the KEK, or
+ * with the TDKEK if TK is set
+ */
+#define KEY_ENC			0x00400000
+
+/*
+ * No Write Back - Do not allow key to be FIFO STOREd
+ */
+#define KEY_NWB			0x00200000
+
+/*
+ * Enhanced Encryption of Key
+ */
+#define KEY_EKT			0x00100000
+
+/*
+ * Encrypted with Trusted Key
+ */
+#define KEY_TK			0x00008000
+
+/*
+ * KDEST - Key Destination: 0 - class key register,
+ * 1 - PKHA 'e', 2 - AFHA Sbox, 3 - MDHA split-key
+ */
+#define KEY_DEST_SHIFT		16
+#define KEY_DEST_MASK		(0x03 << KEY_DEST_SHIFT)
+
+#define KEY_DEST_CLASS_REG	(0x00 << KEY_DEST_SHIFT)
+#define KEY_DEST_PKHA_E		(0x01 << KEY_DEST_SHIFT)
+#define KEY_DEST_AFHA_SBOX	(0x02 << KEY_DEST_SHIFT)
+#define KEY_DEST_MDHA_SPLIT	(0x03 << KEY_DEST_SHIFT)
+
+/* Length in bytes */
+#define KEY_LENGTH_MASK		0x000003ff
+
+/*
+ * LOAD/SEQ_LOAD/STORE/SEQ_STORE Command Constructs
+ */
+
+/*
+ * Load/Store Destination: 0 = class independent CCB,
+ * 1 = class 1 CCB, 2 = class 2 CCB, 3 = DECO
+ */
+#define LDST_CLASS_SHIFT	25
+#define LDST_CLASS_MASK		(0x03 << LDST_CLASS_SHIFT)
+#define LDST_CLASS_IND_CCB	(0x00 << LDST_CLASS_SHIFT)
+#define LDST_CLASS_1_CCB	(0x01 << LDST_CLASS_SHIFT)
+#define LDST_CLASS_2_CCB	(0x02 << LDST_CLASS_SHIFT)
+#define LDST_CLASS_DECO		(0x03 << LDST_CLASS_SHIFT)
+
+/* Scatter-Gather Table/Variable Length Field */
+#define LDST_SGF		0x01000000
+#define LDST_VLF		LDST_SGF
+
+/* Immediate - Key follows this command in descriptor */
+#define LDST_IMM_MASK		1
+#define LDST_IMM_SHIFT		23
+#define LDST_IMM		(LDST_IMM_MASK << LDST_IMM_SHIFT)
+
+/* SRC/DST - Destination for LOAD, Source for STORE */
+#define LDST_SRCDST_SHIFT	16
+#define LDST_SRCDST_MASK	(0x7f << LDST_SRCDST_SHIFT)
+
+#define LDST_SRCDST_BYTE_CONTEXT	(0x20 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_BYTE_KEY		(0x40 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_BYTE_INFIFO		(0x7c << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_BYTE_OUTFIFO	(0x7e << LDST_SRCDST_SHIFT)
+
+#define LDST_SRCDST_WORD_MODE_REG	(0x00 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_KEYSZ_REG	(0x01 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DATASZ_REG	(0x02 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_ICVSZ_REG	(0x03 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_CHACTRL	(0x06 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DECOCTRL	(0x06 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_IRQCTRL	(0x07 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DECO_PCLOVRD	(0x07 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_CLRW		(0x08 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DECO_MATH0	(0x08 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_STAT		(0x09 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DECO_MATH1	(0x09 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DECO_MATH2	(0x0a << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DECO_AAD_SZ	(0x0b << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DECO_MATH3	(0x0b << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_CLASS1_ICV_SZ	(0x0c << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_ALTDS_CLASS1	(0x0f << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_PKHA_A_SZ	(0x10 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_PKHA_B_SZ	(0x11 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_PKHA_N_SZ	(0x12 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_PKHA_E_SZ	(0x13 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_CLASS_CTX	(0x20 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DESCBUF	(0x40 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DESCBUF_JOB	(0x41 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DESCBUF_SHARED	(0x42 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DESCBUF_JOB_WE	(0x45 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_DESCBUF_SHARED_WE (0x46 << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_INFO_FIFO	(0x7a << LDST_SRCDST_SHIFT)
+
+/* Offset in source/destination */
+#define LDST_OFFSET_SHIFT	8
+#define LDST_OFFSET_MASK	(0xff << LDST_OFFSET_SHIFT)
+
+/* LDOFF definitions used when DST = LDST_SRCDST_WORD_DECOCTRL */
+/* These could also be shifted by LDST_OFFSET_SHIFT - this reads better */
+#define LDOFF_CHG_SHARE_SHIFT		0
+#define LDOFF_CHG_SHARE_MASK		(0x3 << LDOFF_CHG_SHARE_SHIFT)
+#define LDOFF_CHG_SHARE_NEVER		(0x1 << LDOFF_CHG_SHARE_SHIFT)
+#define LDOFF_CHG_SHARE_OK_PROP		(0x2 << LDOFF_CHG_SHARE_SHIFT)
+#define LDOFF_CHG_SHARE_OK_NO_PROP	(0x3 << LDOFF_CHG_SHARE_SHIFT)
+
+#define LDOFF_ENABLE_AUTO_NFIFO		(1 << 2)
+#define LDOFF_DISABLE_AUTO_NFIFO	(1 << 3)
+
+#define LDOFF_CHG_NONSEQLIODN_SHIFT	4
+#define LDOFF_CHG_NONSEQLIODN_MASK	(0x3 << LDOFF_CHG_NONSEQLIODN_SHIFT)
+#define LDOFF_CHG_NONSEQLIODN_SEQ	(0x1 << LDOFF_CHG_NONSEQLIODN_SHIFT)
+#define LDOFF_CHG_NONSEQLIODN_NON_SEQ	(0x2 << LDOFF_CHG_NONSEQLIODN_SHIFT)
+#define LDOFF_CHG_NONSEQLIODN_TRUSTED	(0x3 << LDOFF_CHG_NONSEQLIODN_SHIFT)
+
+#define LDOFF_CHG_SEQLIODN_SHIFT	6
+#define LDOFF_CHG_SEQLIODN_MASK		(0x3 << LDOFF_CHG_SEQLIODN_SHIFT)
+#define LDOFF_CHG_SEQLIODN_SEQ		(0x1 << LDOFF_CHG_SEQLIODN_SHIFT)
+#define LDOFF_CHG_SEQLIODN_NON_SEQ	(0x2 << LDOFF_CHG_SEQLIODN_SHIFT)
+#define LDOFF_CHG_SEQLIODN_TRUSTED	(0x3 << LDOFF_CHG_SEQLIODN_SHIFT)
+
+/* Data length in bytes	*/
+#define LDST_LEN_SHIFT		0
+#define LDST_LEN_MASK		(0xff << LDST_LEN_SHIFT)
+
+/* Special Length definitions when dst=deco-ctrl */
+#define LDLEN_ENABLE_OSL_COUNT		(1 << 7)
+#define LDLEN_RST_CHA_OFIFO_PTR		(1 << 6)
+#define LDLEN_RST_OFIFO			(1 << 5)
+#define LDLEN_SET_OFIFO_OFF_VALID	(1 << 4)
+#define LDLEN_SET_OFIFO_OFF_RSVD	(1 << 3)
+#define LDLEN_SET_OFIFO_OFFSET_SHIFT	0
+#define LDLEN_SET_OFIFO_OFFSET_MASK	(3 << LDLEN_SET_OFIFO_OFFSET_SHIFT)
+
+/*
+ * FIFO_LOAD/FIFO_STORE/SEQ_FIFO_LOAD/SEQ_FIFO_STORE
+ * Command Constructs
+ */
+
+/*
+ * Load Destination: 0 = skip (SEQ_FIFO_LOAD only),
+ * 1 = Load for Class1, 2 = Load for Class2, 3 = Load both
+ * Store Source: 0 = normal, 1 = Class1key, 2 = Class2key
+ */
+#define FIFOLD_CLASS_SHIFT	25
+#define FIFOLD_CLASS_MASK	(0x03 << FIFOLD_CLASS_SHIFT)
+#define FIFOLD_CLASS_SKIP	(0x00 << FIFOLD_CLASS_SHIFT)
+#define FIFOLD_CLASS_CLASS1	(0x01 << FIFOLD_CLASS_SHIFT)
+#define FIFOLD_CLASS_CLASS2	(0x02 << FIFOLD_CLASS_SHIFT)
+#define FIFOLD_CLASS_BOTH	(0x03 << FIFOLD_CLASS_SHIFT)
+
+#define FIFOST_CLASS_SHIFT	25
+#define FIFOST_CLASS_MASK	(0x03 << FIFOST_CLASS_SHIFT)
+#define FIFOST_CLASS_NORMAL	(0x00 << FIFOST_CLASS_SHIFT)
+#define FIFOST_CLASS_CLASS1KEY	(0x01 << FIFOST_CLASS_SHIFT)
+#define FIFOST_CLASS_CLASS2KEY	(0x02 << FIFOST_CLASS_SHIFT)
+
+/*
+ * Scatter-Gather Table/Variable Length Field
+ * If set for FIFO_LOAD, refers to a SG table. Within
+ * SEQ_FIFO_LOAD, is variable input sequence
+ */
+#define FIFOLDST_SGF_SHIFT	24
+#define FIFOLDST_SGF_MASK	(1 << FIFOLDST_SGF_SHIFT)
+#define FIFOLDST_VLF_MASK	(1 << FIFOLDST_SGF_SHIFT)
+#define FIFOLDST_SGF		(1 << FIFOLDST_SGF_SHIFT)
+#define FIFOLDST_VLF		(1 << FIFOLDST_SGF_SHIFT)
+
+/* Immediate - Data follows command in descriptor */
+#define FIFOLD_IMM_SHIFT	23
+#define FIFOLD_IMM_MASK		(1 << FIFOLD_IMM_SHIFT)
+#define FIFOLD_IMM		(1 << FIFOLD_IMM_SHIFT)
+
+/* Continue - Not the last FIFO store to come */
+#define FIFOST_CONT_SHIFT	23
+#define FIFOST_CONT_MASK	(1 << FIFOST_CONT_SHIFT)
+
+/*
+ * Extended Length - use 32-bit extended length that
+ * follows the pointer field. Illegal with IMM set
+ */
+#define FIFOLDST_EXT_SHIFT	22
+#define FIFOLDST_EXT_MASK	(1 << FIFOLDST_EXT_SHIFT)
+#define FIFOLDST_EXT		(1 << FIFOLDST_EXT_SHIFT)
+
+/* Input data type.*/
+#define FIFOLD_TYPE_SHIFT	16
+#define FIFOLD_CONT_TYPE_SHIFT	19 /* shift past last-flush bits */
+#define FIFOLD_TYPE_MASK	(0x3f << FIFOLD_TYPE_SHIFT)
+
+/* PK types */
+#define FIFOLD_TYPE_PK		(0x00 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_MASK	(0x30 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_TYPEMASK (0x0f << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_A0	(0x00 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_A1	(0x01 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_A2	(0x02 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_A3	(0x03 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_B0	(0x04 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_B1	(0x05 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_B2	(0x06 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_B3	(0x07 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_N	(0x08 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_A	(0x0c << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_PK_B	(0x0d << FIFOLD_TYPE_SHIFT)
+
+/* Other types. Need to OR in last/flush bits as desired */
+#define FIFOLD_TYPE_MSG_MASK	(0x38 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_MSG		(0x10 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_MSG1OUT2	(0x18 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_IV		(0x20 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_BITDATA	(0x28 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_AAD		(0x30 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_ICV		(0x38 << FIFOLD_TYPE_SHIFT)
+
+/* Last/Flush bits for use with "other" types above */
+#define FIFOLD_TYPE_ACT_MASK	(0x07 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_NOACTION	(0x00 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_FLUSH1	(0x01 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_LAST1	(0x02 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_LAST2FLUSH	(0x03 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_LAST2	(0x04 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_LAST2FLUSH1 (0x05 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_LASTBOTH	(0x06 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_LASTBOTHFL	(0x07 << FIFOLD_TYPE_SHIFT)
+#define FIFOLD_TYPE_NOINFOFIFO	(0x0F << FIFOLD_TYPE_SHIFT)
+
+#define FIFOLDST_LEN_MASK	0xffff
+#define FIFOLDST_EXT_LEN_MASK	0xffffffff
+
+/* Output data types */
+#define FIFOST_TYPE_SHIFT	16
+#define FIFOST_TYPE_MASK	(0x3f << FIFOST_TYPE_SHIFT)
+
+#define FIFOST_TYPE_PKHA_A0	 (0x00 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_A1	 (0x01 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_A2	 (0x02 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_A3	 (0x03 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_B0	 (0x04 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_B1	 (0x05 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_B2	 (0x06 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_B3	 (0x07 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_N	 (0x08 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_A	 (0x0c << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_B	 (0x0d << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_AF_SBOX_JKEK (0x10 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_AF_SBOX_TKEK (0x21 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_E_JKEK	 (0x22 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_PKHA_E_TKEK	 (0x23 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_KEY_KEK	 (0x24 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_KEY_TKEK	 (0x25 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_SPLIT_KEK	 (0x26 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_SPLIT_TKEK	 (0x27 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_OUTFIFO_KEK	 (0x28 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_OUTFIFO_TKEK (0x29 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_MESSAGE_DATA (0x30 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_RNGSTORE	 (0x34 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_RNGFIFO	 (0x35 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_SKIP	 (0x3f << FIFOST_TYPE_SHIFT)
+
+/*
+ * OPERATION Command Constructs
+ */
+
+/* Operation type selectors - OP TYPE */
+#define OP_TYPE_SHIFT		24
+#define OP_TYPE_MASK		(0x07 << OP_TYPE_SHIFT)
+
+#define OP_TYPE_UNI_PROTOCOL	(0x00 << OP_TYPE_SHIFT)
+#define OP_TYPE_PK		(0x01 << OP_TYPE_SHIFT)
+#define OP_TYPE_CLASS1_ALG	(0x02 << OP_TYPE_SHIFT)
+#define OP_TYPE_CLASS2_ALG	(0x04 << OP_TYPE_SHIFT)
+#define OP_TYPE_DECAP_PROTOCOL	(0x06 << OP_TYPE_SHIFT)
+#define OP_TYPE_ENCAP_PROTOCOL	(0x07 << OP_TYPE_SHIFT)
+
+/* ProtocolID selectors - PROTID */
+#define OP_PCLID_SHIFT		16
+#define OP_PCLID_MASK		(0xff << 16)
+
+/* Assuming OP_TYPE = OP_TYPE_UNI_PROTOCOL */
+#define OP_PCLID_BLOB		(0x0d << OP_PCLID_SHIFT)
+#define OP_PCLID_SECRETKEY	(0x11 << OP_PCLID_SHIFT)
+#define OP_PCLID_PUBLICKEYPAIR	(0x14 << OP_PCLID_SHIFT)
+
+/* For non-protocol/alg-only op commands */
+#define OP_ALG_TYPE_SHIFT	24
+#define OP_ALG_TYPE_MASK	(0x7 << OP_ALG_TYPE_SHIFT)
+#define OP_ALG_TYPE_CLASS1	2
+#define OP_ALG_TYPE_CLASS2	4
+
+#define OP_ALG_ALGSEL_SHIFT	16
+#define OP_ALG_ALGSEL_MASK	(0xff << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SUBMASK	(0x0f << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_AES	(0x10 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_DES	(0x20 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_3DES	(0x21 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_ARC4	(0x30 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_MD5	(0x40 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SHA1	(0x41 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SHA224	(0x42 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SHA256	(0x43 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SHA384	(0x44 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SHA512	(0x45 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_RNG	(0x50 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SNOW	(0x60 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SNOW_F8	(0x60 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_KASUMI	(0x70 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_CRC	(0x90 << OP_ALG_ALGSEL_SHIFT)
+#define OP_ALG_ALGSEL_SNOW_F9	(0xA0 << OP_ALG_ALGSEL_SHIFT)
+
+#define OP_ALG_AAI_SHIFT	4
+#define OP_ALG_AAI_MASK		(0x1ff << OP_ALG_AAI_SHIFT)
+
+/* randomizer AAI set */
+#define OP_ALG_AAI_RNG		(0x00 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_RNG_NZB	(0x10 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_RNG_OBP	(0x20 << OP_ALG_AAI_SHIFT)
+
+/* RNG4 AAI set */
+#define OP_ALG_AAI_RNG4_SH_0	(0x00 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_RNG4_SH_1	(0x01 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_RNG4_PS	(0x40 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_RNG4_AI	(0x80 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_RNG4_SK	(0x100 << OP_ALG_AAI_SHIFT)
+
+/* hmac/smac AAI set */
+#define OP_ALG_AAI_HASH		(0x00 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_HMAC		(0x01 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_SMAC		(0x02 << OP_ALG_AAI_SHIFT)
+#define OP_ALG_AAI_HMAC_PRECOMP	(0x04 << OP_ALG_AAI_SHIFT)
+
+#define OP_ALG_AS_SHIFT		2
+#define OP_ALG_AS_MASK		(0x3 << OP_ALG_AS_SHIFT)
+#define OP_ALG_AS_UPDATE	(0 << OP_ALG_AS_SHIFT)
+#define OP_ALG_AS_INIT		(1 << OP_ALG_AS_SHIFT)
+#define OP_ALG_AS_FINALIZE	(2 << OP_ALG_AS_SHIFT)
+#define OP_ALG_AS_INITFINAL	(3 << OP_ALG_AS_SHIFT)
+
+#define OP_ALG_ICV_SHIFT	1
+#define OP_ALG_ICV_MASK		(1 << OP_ALG_ICV_SHIFT)
+#define OP_ALG_ICV_OFF		(0 << OP_ALG_ICV_SHIFT)
+#define OP_ALG_ICV_ON		(1 << OP_ALG_ICV_SHIFT)
+
+#define OP_ALG_DIR_SHIFT	0
+#define OP_ALG_DIR_MASK		1
+#define OP_ALG_DECRYPT		0
+#define OP_ALG_ENCRYPT		1
+
+/* PKHA algorithm type set */
+#define OP_ALG_PK		0x00800000
+#define OP_ALG_PK_FUN_MASK	0x3f /* clrmem, modmath, or cpymem */
+
+/* PKHA mode modular-arithmetic functions */
+#define OP_ALG_PKMODE_MOD_EXPO		0x006
+
+/*
+ * SEQ_IN_PTR Command Constructs
+ */
+
+/* Release Buffers */
+#define SQIN_RBS	0x04000000
+
+/* Sequence pointer is really a descriptor */
+#define SQIN_INL	0x02000000
+
+/* Sequence pointer is a scatter-gather table */
+#define SQIN_SGF	0x01000000
+
+/* Appends to a previous pointer */
+#define SQIN_PRE	0x00800000
+
+/* Use extended length following pointer */
+#define SQIN_EXT	0x00400000
+
+/* Restore sequence with pointer/length */
+#define SQIN_RTO	0x00200000
+
+/* Replace job descriptor */
+#define SQIN_RJD	0x00100000
+
+#define SQIN_LEN_SHIFT		 0
+#define SQIN_LEN_MASK		(0xffff << SQIN_LEN_SHIFT)
+
+/*
+ * SEQ_OUT_PTR Command Constructs
+ */
+
+/* Sequence pointer is a scatter-gather table */
+#define SQOUT_SGF	0x01000000
+
+/* Appends to a previous pointer */
+#define SQOUT_PRE	SQIN_PRE
+
+/* Restore sequence with pointer/length */
+#define SQOUT_RTO	 SQIN_RTO
+
+/* Use extended length following pointer */
+#define SQOUT_EXT	0x00400000
+
+#define SQOUT_LEN_SHIFT		0
+#define SQOUT_LEN_MASK		(0xffff << SQOUT_LEN_SHIFT)
+
+/*
+ * MOVE Command Constructs
+ */
+
+#define MOVE_AUX_SHIFT		25
+#define MOVE_AUX_MASK		(3 << MOVE_AUX_SHIFT)
+#define MOVE_AUX_MS		(2 << MOVE_AUX_SHIFT)
+#define MOVE_AUX_LS		(1 << MOVE_AUX_SHIFT)
+
+#define MOVE_WAITCOMP_SHIFT	24
+#define MOVE_WAITCOMP_MASK	(1 << MOVE_WAITCOMP_SHIFT)
+#define MOVE_WAITCOMP		(1 << MOVE_WAITCOMP_SHIFT)
+
+#define MOVE_SRC_SHIFT		20
+#define MOVE_SRC_MASK		(0x0f << MOVE_SRC_SHIFT)
+#define MOVE_SRC_CLASS1CTX	(0x00 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_CLASS2CTX	(0x01 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_OUTFIFO	(0x02 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_DESCBUF	(0x03 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_MATH0		(0x04 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_MATH1		(0x05 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_MATH2		(0x06 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_MATH3		(0x07 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_INFIFO		(0x08 << MOVE_SRC_SHIFT)
+#define MOVE_SRC_INFIFO_CL	(0x09 << MOVE_SRC_SHIFT)
+
+#define MOVE_DEST_SHIFT		16
+#define MOVE_DEST_MASK		(0x0f << MOVE_DEST_SHIFT)
+#define MOVE_DEST_CLASS1CTX	(0x00 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_CLASS2CTX	(0x01 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_OUTFIFO	(0x02 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_DESCBUF	(0x03 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_MATH0		(0x04 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_MATH1		(0x05 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_MATH2		(0x06 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_MATH3		(0x07 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_CLASS1INFIFO	(0x08 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_CLASS2INFIFO	(0x09 << MOVE_DEST_SHIFT)
+#define MOVE_DEST_INFIFO_NOINFO (0x0a << MOVE_DEST_SHIFT)
+#define MOVE_DEST_PK_A		(0x0c << MOVE_DEST_SHIFT)
+#define MOVE_DEST_CLASS1KEY	(0x0d << MOVE_DEST_SHIFT)
+#define MOVE_DEST_CLASS2KEY	(0x0e << MOVE_DEST_SHIFT)
+
+#define MOVE_OFFSET_SHIFT	8
+#define MOVE_OFFSET_MASK	(0xff << MOVE_OFFSET_SHIFT)
+
+#define MOVE_LEN_SHIFT		0
+#define MOVE_LEN_MASK		(0xff << MOVE_LEN_SHIFT)
+
+#define MOVELEN_MRSEL_SHIFT	0
+#define MOVELEN_MRSEL_MASK	(0x3 << MOVE_LEN_SHIFT)
+
+/*
+ * JUMP Command Constructs
+ */
+
+#define JUMP_CLASS_SHIFT	25
+#define JUMP_CLASS_MASK		(3 << JUMP_CLASS_SHIFT)
+#define JUMP_CLASS_NONE		0
+#define JUMP_CLASS_CLASS1	(1 << JUMP_CLASS_SHIFT)
+#define JUMP_CLASS_CLASS2	(2 << JUMP_CLASS_SHIFT)
+#define JUMP_CLASS_BOTH		(3 << JUMP_CLASS_SHIFT)
+
+#define JUMP_JSL_SHIFT		24
+#define JUMP_JSL_MASK		(1 << JUMP_JSL_SHIFT)
+#define JUMP_JSL		(1 << JUMP_JSL_SHIFT)
+
+#define JUMP_TYPE_SHIFT		22
+#define JUMP_TYPE_MASK		(0x03 << JUMP_TYPE_SHIFT)
+#define JUMP_TYPE_LOCAL		(0x00 << JUMP_TYPE_SHIFT)
+#define JUMP_TYPE_NONLOCAL	(0x01 << JUMP_TYPE_SHIFT)
+#define JUMP_TYPE_HALT		(0x02 << JUMP_TYPE_SHIFT)
+#define JUMP_TYPE_HALT_USER	(0x03 << JUMP_TYPE_SHIFT)
+
+#define JUMP_TEST_SHIFT		16
+#define JUMP_TEST_MASK		(0x03 << JUMP_TEST_SHIFT)
+#define JUMP_TEST_ALL		(0x00 << JUMP_TEST_SHIFT)
+#define JUMP_TEST_INVALL	(0x01 << JUMP_TEST_SHIFT)
+#define JUMP_TEST_ANY		(0x02 << JUMP_TEST_SHIFT)
+#define JUMP_TEST_INVANY	(0x03 << JUMP_TEST_SHIFT)
+
+/* Condition codes. JSL bit is factored in */
+#define JUMP_COND_SHIFT		8
+#define JUMP_COND_MASK		(0x100ff << JUMP_COND_SHIFT)
+#define JUMP_COND_PK_0		(0x80 << JUMP_COND_SHIFT)
+#define JUMP_COND_PK_GCD_1	(0x40 << JUMP_COND_SHIFT)
+#define JUMP_COND_PK_PRIME	(0x20 << JUMP_COND_SHIFT)
+#define JUMP_COND_MATH_N	(0x08 << JUMP_COND_SHIFT)
+#define JUMP_COND_MATH_Z	(0x04 << JUMP_COND_SHIFT)
+#define JUMP_COND_MATH_C	(0x02 << JUMP_COND_SHIFT)
+#define JUMP_COND_MATH_NV	(0x01 << JUMP_COND_SHIFT)
+
+#define JUMP_COND_JRP		((0x80 << JUMP_COND_SHIFT) | JUMP_JSL)
+#define JUMP_COND_SHRD		((0x40 << JUMP_COND_SHIFT) | JUMP_JSL)
+#define JUMP_COND_SELF		((0x20 << JUMP_COND_SHIFT) | JUMP_JSL)
+#define JUMP_COND_CALM		((0x10 << JUMP_COND_SHIFT) | JUMP_JSL)
+#define JUMP_COND_NIP		((0x08 << JUMP_COND_SHIFT) | JUMP_JSL)
+#define JUMP_COND_NIFP		((0x04 << JUMP_COND_SHIFT) | JUMP_JSL)
+#define JUMP_COND_NOP		((0x02 << JUMP_COND_SHIFT) | JUMP_JSL)
+#define JUMP_COND_NCP		((0x01 << JUMP_COND_SHIFT) | JUMP_JSL)
+
+#define JUMP_OFFSET_SHIFT	0
+#define JUMP_OFFSET_MASK	(0xff << JUMP_OFFSET_SHIFT)
+
+#define OP_ALG_RNG4_SHIFT      4
+#define OP_ALG_RNG4_MAS                (0x1f3 << OP_ALG_RNG4_SHIFT)
+#define OP_ALG_RNG4_SK         (0x100 << OP_ALG_RNG4_SHIFT)
+
+#endif /* DESC_H */
diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
new file mode 100644
index 00000000000..f9cae9144ac
--- /dev/null
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -0,0 +1,280 @@
+/*
+ * caam descriptor construction helper functions
+ *
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Based on desc_constr.h file in linux drivers/crypto/caam
+ */
+
+#include <linux/compat.h>
+#include "desc.h"
+
+#define IMMEDIATE (1 << 23)
+#define CAAM_CMD_SZ sizeof(u32)
+#define CAAM_PTR_SZ sizeof(dma_addr_t)
+#define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE)
+#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3)
+
+#ifdef DEBUG
+#define PRINT_POS do { printf("%02d: %s\n", desc_len(desc),\
+			      &__func__[sizeof("append")]); \
+		     } while (0)
+#else
+#define PRINT_POS
+#endif
+
+#define SET_OK_NO_PROP_ERRORS (IMMEDIATE | LDST_CLASS_DECO | \
+			       LDST_SRCDST_WORD_DECOCTRL | \
+			       (LDOFF_CHG_SHARE_OK_NO_PROP << \
+				LDST_OFFSET_SHIFT))
+#define DISABLE_AUTO_INFO_FIFO (IMMEDIATE | LDST_CLASS_DECO | \
+				LDST_SRCDST_WORD_DECOCTRL | \
+				(LDOFF_DISABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
+#define ENABLE_AUTO_INFO_FIFO (IMMEDIATE | LDST_CLASS_DECO | \
+			       LDST_SRCDST_WORD_DECOCTRL | \
+			       (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
+
+static inline int desc_len(u32 *desc)
+{
+	return *desc & HDR_DESCLEN_MASK;
+}
+
+static inline int desc_bytes(void *desc)
+{
+	return desc_len(desc) * CAAM_CMD_SZ;
+}
+
+static inline u32 *desc_end(u32 *desc)
+{
+	return desc + desc_len(desc);
+}
+
+static inline void init_desc(u32 *desc, u32 options)
+{
+	*desc = (options | HDR_ONE) + 1;
+}
+
+static inline void init_job_desc(u32 *desc, u32 options)
+{
+	init_desc(desc, CMD_DESC_HDR | options);
+}
+
+static inline void append_ptr(u32 *desc, dma_addr_t ptr)
+{
+	dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
+
+	*offset = ptr;
+
+	(*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ;
+}
+
+static inline void append_data(u32 *desc, void *data, int len)
+{
+	u32 *offset = desc_end(desc);
+
+	if (len) /* avoid sparse warning: memcpy with byte count of 0 */
+		memcpy(offset, data, len);
+
+	(*desc) += (len + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ;
+}
+
+static inline void append_cmd(u32 *desc, u32 command)
+{
+	u32 *cmd = desc_end(desc);
+
+	*cmd = command;
+
+	(*desc)++;
+}
+
+#define append_u32 append_cmd
+
+static inline void append_u64(u32 *desc, u64 data)
+{
+	u32 *offset = desc_end(desc);
+
+	*offset = upper_32_bits(data);
+	*(++offset) = lower_32_bits(data);
+
+	(*desc) += 2;
+}
+
+/* Write command without affecting header, and return pointer to next word */
+static inline u32 *write_cmd(u32 *desc, u32 command)
+{
+	*desc = command;
+
+	return desc + 1;
+}
+
+static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len,
+				  u32 command)
+{
+	append_cmd(desc, command | len);
+	append_ptr(desc, ptr);
+}
+
+/* Write length after pointer, rather than inside command */
+static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr,
+					 unsigned int len, u32 command)
+{
+	append_cmd(desc, command);
+	if (!(command & (SQIN_RTO | SQIN_PRE)))
+		append_ptr(desc, ptr);
+	append_cmd(desc, len);
+}
+
+static inline void append_cmd_data(u32 *desc, void *data, int len,
+				   u32 command)
+{
+	append_cmd(desc, command | IMMEDIATE | len);
+	append_data(desc, data, len);
+}
+
+#define APPEND_CMD_RET(cmd, op) \
+static inline u32 *append_##cmd(u32 *desc, u32 options) \
+{ \
+	u32 *cmd = desc_end(desc); \
+	PRINT_POS; \
+	append_cmd(desc, CMD_##op | options); \
+	return cmd; \
+}
+APPEND_CMD_RET(jump, JUMP)
+APPEND_CMD_RET(move, MOVE)
+
+static inline void set_jump_tgt_here(u32 *desc, u32 *jump_cmd)
+{
+	*jump_cmd = *jump_cmd | (desc_len(desc) - (jump_cmd - desc));
+}
+
+static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd)
+{
+	*move_cmd &= ~MOVE_OFFSET_MASK;
+	*move_cmd = *move_cmd | ((desc_len(desc) << (MOVE_OFFSET_SHIFT + 2)) &
+				 MOVE_OFFSET_MASK);
+}
+
+#define APPEND_CMD(cmd, op) \
+static inline void append_##cmd(u32 *desc, u32 options) \
+{ \
+	PRINT_POS; \
+	append_cmd(desc, CMD_##op | options); \
+}
+APPEND_CMD(operation, OPERATION)
+
+#define APPEND_CMD_LEN(cmd, op) \
+static inline void append_##cmd(u32 *desc, unsigned int len, u32 options) \
+{ \
+	PRINT_POS; \
+	append_cmd(desc, CMD_##op | len | options); \
+}
+APPEND_CMD_LEN(seq_store, SEQ_STORE)
+APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD)
+APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE)
+
+#define APPEND_CMD_PTR(cmd, op) \
+static inline void append_##cmd(u32 *desc, dma_addr_t ptr, unsigned int len, \
+				u32 options) \
+{ \
+	PRINT_POS; \
+	append_cmd_ptr(desc, ptr, len, CMD_##op | options); \
+}
+APPEND_CMD_PTR(key, KEY)
+APPEND_CMD_PTR(load, LOAD)
+APPEND_CMD_PTR(fifo_load, FIFO_LOAD)
+APPEND_CMD_PTR(fifo_store, FIFO_STORE)
+
+static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len,
+				u32 options)
+{
+	u32 cmd_src;
+
+	cmd_src = options & LDST_SRCDST_MASK;
+
+	append_cmd(desc, CMD_STORE | options | len);
+
+	/* The following options do not require pointer */
+	if (!(cmd_src == LDST_SRCDST_WORD_DESCBUF_SHARED ||
+	      cmd_src == LDST_SRCDST_WORD_DESCBUF_JOB    ||
+	      cmd_src == LDST_SRCDST_WORD_DESCBUF_JOB_WE ||
+	      cmd_src == LDST_SRCDST_WORD_DESCBUF_SHARED_WE))
+		append_ptr(desc, ptr);
+}
+
+#define APPEND_SEQ_PTR_INTLEN(cmd, op) \
+static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \
+						 unsigned int len, \
+						 u32 options) \
+{ \
+	PRINT_POS; \
+	if (options & (SQIN_RTO | SQIN_PRE)) \
+		append_cmd(desc, CMD_SEQ_##op##_PTR | len | options); \
+	else \
+		append_cmd_ptr(desc, ptr, len, CMD_SEQ_##op##_PTR | options); \
+}
+APPEND_SEQ_PTR_INTLEN(in, IN)
+APPEND_SEQ_PTR_INTLEN(out, OUT)
+
+#define APPEND_CMD_PTR_TO_IMM(cmd, op) \
+static inline void append_##cmd##_as_imm(u32 *desc, void *data, \
+					 unsigned int len, u32 options) \
+{ \
+	PRINT_POS; \
+	append_cmd_data(desc, data, len, CMD_##op | options); \
+}
+APPEND_CMD_PTR_TO_IMM(load, LOAD);
+APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD);
+
+#define APPEND_CMD_PTR_EXTLEN(cmd, op) \
+static inline void append_##cmd##_extlen(u32 *desc, dma_addr_t ptr, \
+					 unsigned int len, u32 options) \
+{ \
+	PRINT_POS; \
+	append_cmd_ptr_extlen(desc, ptr, len, CMD_##op | SQIN_EXT | options); \
+}
+APPEND_CMD_PTR_EXTLEN(seq_in_ptr, SEQ_IN_PTR)
+APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR)
+
+/*
+ * Determine whether to store length internally or externally depending on
+ * the size of its type
+ */
+#define APPEND_CMD_PTR_LEN(cmd, op, type) \
+static inline void append_##cmd(u32 *desc, dma_addr_t ptr, \
+				type len, u32 options) \
+{ \
+	PRINT_POS; \
+	if (sizeof(type) > sizeof(u16)) \
+		append_##cmd##_extlen(desc, ptr, len, options); \
+	else \
+		append_##cmd##_intlen(desc, ptr, len, options); \
+}
+APPEND_CMD_PTR_LEN(seq_in_ptr, SEQ_IN_PTR, u32)
+APPEND_CMD_PTR_LEN(seq_out_ptr, SEQ_OUT_PTR, u32)
+
+/*
+ * 2nd variant for commands whose specified immediate length differs
+ * from length of immediate data provided, e.g., split keys
+ */
+#define APPEND_CMD_PTR_TO_IMM2(cmd, op) \
+static inline void append_##cmd##_as_imm(u32 *desc, void *data, \
+					 unsigned int data_len, \
+					 unsigned int len, u32 options) \
+{ \
+	PRINT_POS; \
+	append_cmd(desc, CMD_##op | IMMEDIATE | len | options); \
+	append_data(desc, data, data_len); \
+}
+APPEND_CMD_PTR_TO_IMM2(key, KEY);
+
+#define APPEND_CMD_RAW_IMM(cmd, op, type) \
+static inline void append_##cmd##_imm_##type(u32 *desc, type immediate, \
+					     u32 options) \
+{ \
+	PRINT_POS; \
+	append_cmd(desc, CMD_##op | IMMEDIATE | options | sizeof(type)); \
+	append_cmd(desc, immediate); \
+}
+APPEND_CMD_RAW_IMM(load, LOAD, u32);
diff --git a/drivers/crypto/fsl/error.c b/drivers/crypto/fsl/error.c
new file mode 100644
index 00000000000..28cdcdd4cc3
--- /dev/null
+++ b/drivers/crypto/fsl/error.c
@@ -0,0 +1,258 @@
+/*
+ * CAAM Error Reporting
+ *
+ * Copyright 2009-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Derived from error.c file in linux drivers/crypto/caam
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include "desc.h"
+#include "jr.h"
+
+#define CAAM_ERROR_STR_MAX 302
+
+#define JRSTA_SSRC_SHIFT            28
+#define JRSTA_CCBERR_CHAID_MASK     0x00f0
+#define JRSTA_CCBERR_CHAID_SHIFT    4
+#define JRSTA_CCBERR_ERRID_MASK     0x000
+#define JRSTA_CCBERR_CHAID_RNG      (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
+
+#define JRSTA_DECOERR_JUMP          0x08000000
+#define JRSTA_DECOERR_INDEX_SHIFT   8
+#define JRSTA_DECOERR_INDEX_MASK    0xff00
+#define JRSTA_DECOERR_ERROR_MASK    0x00ff
+
+
+static const struct {
+	u8 value;
+	const char *error_text;
+} desc_error_list[] = {
+	{ 0x00, "No error." },
+	{ 0x01, "SGT Length Error. The descriptor is trying to read" \
+		" more data than is contained in the SGT table." },
+	{ 0x02, "SGT Null Entry Error." },
+	{ 0x03, "Job Ring Control Error. Bad value in Job Ring Control reg." },
+	{ 0x04, "Invalid Descriptor Command." },
+	{ 0x05, "Reserved." },
+	{ 0x06, "Invalid KEY Command" },
+	{ 0x07, "Invalid LOAD Command" },
+	{ 0x08, "Invalid STORE Command" },
+	{ 0x09, "Invalid OPERATION Command" },
+	{ 0x0A, "Invalid FIFO LOAD Command" },
+	{ 0x0B, "Invalid FIFO STORE Command" },
+	{ 0x0C, "Invalid MOVE/MOVE_LEN Command" },
+	{ 0x0D, "Invalid JUMP Command" },
+	{ 0x0E, "Invalid MATH Command" },
+	{ 0x0F, "Invalid SIGNATURE Command" },
+	{ 0x10, "Invalid Sequence Command" },
+	{ 0x11, "Skip data type invalid. The type must be 0xE or 0xF."},
+	{ 0x12, "Shared Descriptor Header Error" },
+	{ 0x13, "Header Error. Invalid length or parity, or other problems." },
+	{ 0x14, "Burster Error. Burster has gotten to an illegal state" },
+	{ 0x15, "Context Register Length Error" },
+	{ 0x16, "DMA Error" },
+	{ 0x17, "Reserved." },
+	{ 0x1A, "Job failed due to JR reset" },
+	{ 0x1B, "Job failed due to Fail Mode" },
+	{ 0x1C, "DECO Watchdog timer timeout error" },
+	{ 0x1D, "DECO tried to copy a key from another DECO but" \
+		" the other DECO's Key Registers were locked" },
+	{ 0x1E, "DECO attempted to copy data from a DECO" \
+		"that had an unmasked Descriptor error" },
+	{ 0x1F, "LIODN error" },
+	{ 0x20, "DECO has completed a reset initiated via the DRR register" },
+	{ 0x21, "Nonce error" },
+	{ 0x22, "Meta data is too large (> 511 bytes) for TLS decap" },
+	{ 0x23, "Read Input Frame error" },
+	{ 0x24, "JDKEK, TDKEK or TDSK not loaded error" },
+	{ 0x80, "DNR (do not run) error" },
+	{ 0x81, "undefined protocol command" },
+	{ 0x82, "invalid setting in PDB" },
+	{ 0x83, "Anti-replay LATE error" },
+	{ 0x84, "Anti-replay REPLAY error" },
+	{ 0x85, "Sequence number overflow" },
+	{ 0x86, "Sigver invalid signature" },
+	{ 0x87, "DSA Sign Illegal test descriptor" },
+	{ 0x88, "Protocol Format Error" },
+	{ 0x89, "Protocol Size Error" },
+	{ 0xC1, "Blob Command error: Undefined mode" },
+	{ 0xC2, "Blob Command error: Secure Memory Blob mode error" },
+	{ 0xC4, "Blob Command error: Black Blob key or input size error" },
+	{ 0xC5, "Blob Command error: Invalid key destination" },
+	{ 0xC8, "Blob Command error: Trusted/Secure mode error" },
+	{ 0xF0, "IPsec TTL or hop limit field is 0, or was decremented to 0" },
+	{ 0xF1, "3GPP HFN matches or exceeds the Threshold" },
+};
+
+static const char * const cha_id_list[] = {
+	"",
+	"AES",
+	"DES",
+	"ARC4",
+	"MDHA",
+	"RNG",
+	"SNOW f8",
+	"Kasumi f8/9",
+	"PKHA",
+	"CRCA",
+	"SNOW f9",
+	"ZUCE",
+	"ZUCA",
+};
+
+static const char * const err_id_list[] = {
+	"No error.",
+	"Mode error.",
+	"Data size error.",
+	"Key size error.",
+	"PKHA A memory size error.",
+	"PKHA B memory size error.",
+	"Data arrived out of sequence error.",
+	"PKHA divide-by-zero error.",
+	"PKHA modulus even error.",
+	"DES key parity error.",
+	"ICV check failed.",
+	"Hardware error.",
+	"Unsupported CCM AAD size.",
+	"Class 1 CHA is not reset",
+	"Invalid CHA combination was selected",
+	"Invalid CHA selected.",
+};
+
+static const char * const rng_err_id_list[] = {
+	"",
+	"",
+	"",
+	"Instantiate",
+	"Not instantiated",
+	"Test instantiate",
+	"Prediction resistance",
+	"Prediction resistance and test request",
+	"Uninstantiate",
+	"Secure key generation",
+};
+
+static void report_ccb_status(const u32 status,
+			      const char *error)
+{
+	u8 cha_id = (status & JRSTA_CCBERR_CHAID_MASK) >>
+		    JRSTA_CCBERR_CHAID_SHIFT;
+	u8 err_id = status & JRSTA_CCBERR_ERRID_MASK;
+	u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >>
+		  JRSTA_DECOERR_INDEX_SHIFT;
+	char *idx_str;
+	const char *cha_str = "unidentified cha_id value 0x";
+	char cha_err_code[3] = { 0 };
+	const char *err_str = "unidentified err_id value 0x";
+	char err_err_code[3] = { 0 };
+
+	if (status & JRSTA_DECOERR_JUMP)
+		idx_str = "jump tgt desc idx";
+	else
+		idx_str = "desc idx";
+
+	if (cha_id < ARRAY_SIZE(cha_id_list))
+		cha_str = cha_id_list[cha_id];
+	else
+		snprintf(cha_err_code, sizeof(cha_err_code), "%02x", cha_id);
+
+	if ((cha_id << JRSTA_CCBERR_CHAID_SHIFT) == JRSTA_CCBERR_CHAID_RNG &&
+	    err_id < ARRAY_SIZE(rng_err_id_list) &&
+	    strlen(rng_err_id_list[err_id])) {
+		/* RNG-only error */
+		err_str = rng_err_id_list[err_id];
+	} else if (err_id < ARRAY_SIZE(err_id_list)) {
+		err_str = err_id_list[err_id];
+	} else {
+		snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id);
+	}
+
+	debug("%08x: %s: %s %d: %s%s: %s%s\n",
+	       status, error, idx_str, idx,
+		cha_str, cha_err_code,
+		err_str, err_err_code);
+}
+
+static void report_jump_status(const u32 status,
+			       const char *error)
+{
+	debug("%08x: %s: %s() not implemented\n",
+	       status, error, __func__);
+}
+
+static void report_deco_status(const u32 status,
+			       const char *error)
+{
+	u8 err_id = status & JRSTA_DECOERR_ERROR_MASK;
+	u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >>
+		  JRSTA_DECOERR_INDEX_SHIFT;
+	char *idx_str;
+	const char *err_str = "unidentified error value 0x";
+	char err_err_code[3] = { 0 };
+	int i;
+
+	if (status & JRSTA_DECOERR_JUMP)
+		idx_str = "jump tgt desc idx";
+	else
+		idx_str = "desc idx";
+
+	for (i = 0; i < ARRAY_SIZE(desc_error_list); i++)
+		if (desc_error_list[i].value == err_id)
+			break;
+
+	if (i != ARRAY_SIZE(desc_error_list) && desc_error_list[i].error_text)
+		err_str = desc_error_list[i].error_text;
+	else
+		snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id);
+
+	debug("%08x: %s: %s %d: %s%s\n",
+	       status, error, idx_str, idx, err_str, err_err_code);
+}
+
+static void report_jr_status(const u32 status,
+			     const char *error)
+{
+	debug("%08x: %s: %s() not implemented\n",
+	       status, error, __func__);
+}
+
+static void report_cond_code_status(const u32 status,
+				    const char *error)
+{
+	debug("%08x: %s: %s() not implemented\n",
+	       status, error, __func__);
+}
+
+void caam_jr_strstatus(u32 status)
+{
+	static const struct stat_src {
+		void (*report_ssed)(const u32 status,
+				    const char *error);
+		const char *error;
+	} status_src[] = {
+		{ NULL, "No error" },
+		{ NULL, NULL },
+		{ report_ccb_status, "CCB" },
+		{ report_jump_status, "Jump" },
+		{ report_deco_status, "DECO" },
+		{ NULL, NULL },
+		{ report_jr_status, "Job Ring" },
+		{ report_cond_code_status, "Condition Code" },
+	};
+	u32 ssrc = status >> JRSTA_SSRC_SHIFT;
+	const char *error = status_src[ssrc].error;
+
+	/*
+	 * If there is no further error handling function, just
+	 * print the error code, error string and exit. Otherwise
+	 * call the handler function.
+	 */
+	if (!status_src[ssrc].report_ssed)
+		debug("%08x: %s:\n", status, status_src[ssrc].error);
+	else
+		status_src[ssrc].report_ssed(status, error);
+}
diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c
new file mode 100644
index 00000000000..bc0107521c5
--- /dev/null
+++ b/drivers/crypto/fsl/fsl_blob.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include "jobdesc.h"
+#include "desc.h"
+#include "jr.h"
+
+int blob_decrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len)
+{
+	int ret, i = 0;
+	u32 *desc;
+
+	printf("\nDecapsulating data to form blob\n");
+	desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
+	if (!desc) {
+		debug("Not enough memory for descriptor allocation\n");
+		return -1;
+	}
+
+	inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len);
+
+	for (i = 0; i < 14; i++)
+		printf("%x\n", *(desc + i));
+	ret = run_descriptor_jr(desc);
+
+	if (ret)
+		printf("Error in Decapsulation %d\n", ret);
+
+	free(desc);
+	return ret;
+}
+
+int blob_encrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len)
+{
+	int ret, i = 0;
+	u32 *desc;
+
+	printf("\nEncapsulating data to form blob\n");
+	desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
+	if (!desc) {
+		debug("Not enough memory for descriptor allocation\n");
+		return -1;
+	}
+
+	inline_cnstr_jobdesc_blob_encap(desc, key_mod, src, dst, len);
+	for (i = 0; i < 14; i++)
+		printf("%x\n", *(desc + i));
+	ret = run_descriptor_jr(desc);
+
+	if (ret)
+		printf("Error in Encapsulation %d\n", ret);
+
+	free(desc);
+	return ret;
+}
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
new file mode 100644
index 00000000000..d77f2573d0f
--- /dev/null
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include "jobdesc.h"
+#include "desc.h"
+#include "jr.h"
+
+#define CRYPTO_MAX_ALG_NAME	80
+#define SHA1_DIGEST_SIZE        20
+#define SHA256_DIGEST_SIZE      32
+
+struct caam_hash_template {
+	char name[CRYPTO_MAX_ALG_NAME];
+	unsigned int digestsize;
+	u32 alg_type;
+};
+
+enum caam_hash_algos {
+	SHA1 = 0,
+	SHA256
+};
+
+static struct caam_hash_template driver_hash[] = {
+	{
+		.name = "sha1",
+		.digestsize = SHA1_DIGEST_SIZE,
+		.alg_type = OP_ALG_ALGSEL_SHA1,
+	},
+	{
+		.name = "sha256",
+		.digestsize = SHA256_DIGEST_SIZE,
+		.alg_type = OP_ALG_ALGSEL_SHA256,
+	},
+};
+
+int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
+	      unsigned char *pout, enum caam_hash_algos algo)
+{
+	int ret = 0;
+	uint32_t *desc;
+
+	desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
+	if (!desc) {
+		debug("Not enough memory for descriptor allocation\n");
+		return -1;
+	}
+
+	inline_cnstr_jobdesc_hash(desc, pbuf, buf_len, pout,
+				  driver_hash[algo].alg_type,
+				  driver_hash[algo].digestsize,
+				  0);
+
+	ret = run_descriptor_jr(desc);
+
+	free(desc);
+	return ret;
+}
+
+void hw_sha256(const unsigned char *pbuf, unsigned int buf_len,
+			unsigned char *pout, unsigned int chunk_size)
+{
+	if (caam_hash(pbuf, buf_len, pout, SHA256))
+		printf("CAAM was not setup properly or it is faulty\n");
+}
+
+void hw_sha1(const unsigned char *pbuf, unsigned int buf_len,
+			unsigned char *pout, unsigned int chunk_size)
+{
+	if (caam_hash(pbuf, buf_len, pout, SHA1))
+		printf("CAAM was not setup properly or it is faulty\n");
+}
diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c
new file mode 100644
index 00000000000..1386baec0fd
--- /dev/null
+++ b/drivers/crypto/fsl/jobdesc.c
@@ -0,0 +1,125 @@
+/*
+ * SEC Descriptor Construction Library
+ * Basic job descriptor construction
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include "desc_constr.h"
+#include "jobdesc.h"
+
+#define KEY_BLOB_SIZE			32
+#define MAC_SIZE			16
+
+void inline_cnstr_jobdesc_hash(uint32_t *desc,
+			  const uint8_t *msg, uint32_t msgsz, uint8_t *digest,
+			  u32 alg_type, uint32_t alg_size, int sg_tbl)
+{
+	/* SHA 256 , output is of length 32 words */
+	uint32_t storelen = alg_size;
+	u32 options;
+	dma_addr_t dma_addr_in, dma_addr_out;
+
+	dma_addr_in = virt_to_phys((void *)msg);
+	dma_addr_out = virt_to_phys((void *)digest);
+
+	init_job_desc(desc, 0);
+	append_operation(desc, OP_TYPE_CLASS2_ALG |
+			 OP_ALG_AAI_HASH | OP_ALG_AS_INITFINAL |
+			 OP_ALG_ENCRYPT | OP_ALG_ICV_OFF | alg_type);
+
+	options = LDST_CLASS_2_CCB | FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST2;
+	if (sg_tbl)
+		options |= FIFOLDST_SGF;
+	if (msgsz > 0xffff) {
+		options |= FIFOLDST_EXT;
+		append_fifo_load(desc, dma_addr_in, 0, options);
+		append_cmd(desc, msgsz);
+	} else {
+		append_fifo_load(desc, dma_addr_in, msgsz, options);
+	}
+
+	append_store(desc, dma_addr_out, storelen,
+		     LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_CONTEXT);
+}
+
+void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr,
+				     uint8_t *plain_txt, uint8_t *enc_blob,
+				     uint32_t in_sz)
+{
+	dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
+	uint32_t key_sz = KEY_IDNFR_SZ_BYTES;
+	/* output blob will have 32 bytes key blob in beginning and
+	 * 16 byte HMAC identifier at end of data blob */
+	uint32_t out_sz = in_sz + KEY_BLOB_SIZE + MAC_SIZE;
+
+	dma_addr_key_idnfr = virt_to_phys((void *)key_idnfr);
+	dma_addr_in	= virt_to_phys((void *)plain_txt);
+	dma_addr_out	= virt_to_phys((void *)enc_blob);
+
+	init_job_desc(desc, 0);
+
+	append_key(desc, dma_addr_key_idnfr, key_sz, CLASS_2);
+
+	append_seq_in_ptr(desc, dma_addr_in, in_sz, 0);
+
+	append_seq_out_ptr(desc, dma_addr_out, out_sz, 0);
+
+	append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB);
+}
+
+void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr,
+				     uint8_t *enc_blob, uint8_t *plain_txt,
+				     uint32_t out_sz)
+{
+	dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
+	uint32_t key_sz = KEY_IDNFR_SZ_BYTES;
+	uint32_t in_sz = out_sz + KEY_BLOB_SIZE + MAC_SIZE;
+
+	dma_addr_key_idnfr = virt_to_phys((void *)key_idnfr);
+	dma_addr_in	= virt_to_phys((void *)enc_blob);
+	dma_addr_out	= virt_to_phys((void *)plain_txt);
+
+	init_job_desc(desc, 0);
+
+	append_key(desc, dma_addr_key_idnfr, key_sz, CLASS_2);
+
+	append_seq_in_ptr(desc, dma_addr_in, in_sz, 0);
+
+	append_seq_out_ptr(desc, dma_addr_out, out_sz, 0);
+
+	append_operation(desc, OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB);
+}
+
+/*
+ * Descriptor to instantiate RNG State Handle 0 in normal mode and
+ * load the JDKEK, TDKEK and TDSK registers
+ */
+void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc)
+{
+	u32 *jump_cmd;
+
+	init_job_desc(desc, 0);
+
+	/* INIT RNG in non-test mode */
+	append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
+			 OP_ALG_AS_INIT);
+
+	/* wait for done */
+	jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
+	set_jump_tgt_here(desc, jump_cmd);
+
+	/*
+	 * load 1 to clear written reg:
+	 * resets the done interrrupt and returns the RNG to idle.
+	 */
+	append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
+
+	/* generate secure keys (non-test) */
+	append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
+			 OP_ALG_RNG4_SK);
+}
diff --git a/drivers/crypto/fsl/jobdesc.h b/drivers/crypto/fsl/jobdesc.h
new file mode 100644
index 00000000000..3cf7226de23
--- /dev/null
+++ b/drivers/crypto/fsl/jobdesc.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef __JOBDESC_H
+#define __JOBDESC_H
+
+#include <common.h>
+#include <asm/io.h>
+
+#define KEY_IDNFR_SZ_BYTES		16
+
+void inline_cnstr_jobdesc_hash(uint32_t *desc,
+			  const uint8_t *msg, uint32_t msgsz, uint8_t *digest,
+			  u32 alg_type, uint32_t alg_size, int sg_tbl);
+
+void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr,
+				     uint8_t *plain_txt, uint8_t *enc_blob,
+				     uint32_t in_sz);
+
+void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr,
+				     uint8_t *enc_blob, uint8_t *plain_txt,
+				     uint32_t out_sz);
+
+void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc);
+#endif
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
new file mode 100644
index 00000000000..29681e18a6d
--- /dev/null
+++ b/drivers/crypto/fsl/jr.c
@@ -0,0 +1,462 @@
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Based on CAAM driver in drivers/crypto/caam in Linux
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include "fsl_sec.h"
+#include "jr.h"
+#include "jobdesc.h"
+
+#define CIRC_CNT(head, tail, size)	(((head) - (tail)) & (size - 1))
+#define CIRC_SPACE(head, tail, size)	CIRC_CNT((tail), (head) + 1, (size))
+
+struct jobring jr;
+
+static inline void start_jr0(void)
+{
+	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
+	u32 scfgr = sec_in32(&sec->scfgr);
+
+	if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
+		/* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
+		 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
+		 */
+		if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
+		    (!(ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) &&
+					(scfgr & SEC_SCFGR_VIRT_EN)))
+			sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
+	} else {
+		/* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
+		if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
+			sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
+	}
+}
+
+static inline void jr_reset_liodn(void)
+{
+	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	sec_out32(&sec->jrliodnr[0].ls, 0);
+}
+
+static inline void jr_disable_irq(void)
+{
+	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+	uint32_t jrcfg = sec_in32(&regs->jrcfg1);
+
+	jrcfg = jrcfg | JR_INTMASK;
+
+	sec_out32(&regs->jrcfg1, jrcfg);
+}
+
+static void jr_initregs(void)
+{
+	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+	phys_addr_t ip_base = virt_to_phys((void *)jr.input_ring);
+	phys_addr_t op_base = virt_to_phys((void *)jr.output_ring);
+
+#ifdef CONFIG_PHYS_64BIT
+	sec_out32(&regs->irba_h, ip_base >> 32);
+#else
+	sec_out32(&regs->irba_h, 0x0);
+#endif
+	sec_out32(&regs->irba_l, (uint32_t)ip_base);
+#ifdef CONFIG_PHYS_64BIT
+	sec_out32(&regs->orba_h, op_base >> 32);
+#else
+	sec_out32(&regs->orba_h, 0x0);
+#endif
+	sec_out32(&regs->orba_l, (uint32_t)op_base);
+	sec_out32(&regs->ors, JR_SIZE);
+	sec_out32(&regs->irs, JR_SIZE);
+
+	if (!jr.irq)
+		jr_disable_irq();
+}
+
+static int jr_init(void)
+{
+	memset(&jr, 0, sizeof(struct jobring));
+
+	jr.jq_id = DEFAULT_JR_ID;
+	jr.irq = DEFAULT_IRQ;
+
+#ifdef CONFIG_FSL_CORENET
+	jr.liodn = DEFAULT_JR_LIODN;
+#endif
+	jr.size = JR_SIZE;
+	jr.input_ring = (dma_addr_t *)malloc(JR_SIZE * sizeof(dma_addr_t));
+	if (!jr.input_ring)
+		return -1;
+	jr.output_ring =
+	    (struct op_ring *)malloc(JR_SIZE * sizeof(struct op_ring));
+	if (!jr.output_ring)
+		return -1;
+
+	memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
+	memset(jr.output_ring, 0, JR_SIZE * sizeof(struct op_ring));
+
+	start_jr0();
+
+	jr_initregs();
+
+	return 0;
+}
+
+static int jr_sw_cleanup(void)
+{
+	jr.head = 0;
+	jr.tail = 0;
+	jr.read_idx = 0;
+	jr.write_idx = 0;
+	memset(jr.info, 0, sizeof(jr.info));
+	memset(jr.input_ring, 0, jr.size * sizeof(dma_addr_t));
+	memset(jr.output_ring, 0, jr.size * sizeof(struct op_ring));
+
+	return 0;
+}
+
+static int jr_hw_reset(void)
+{
+	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+	uint32_t timeout = 100000;
+	uint32_t jrint, jrcr;
+
+	sec_out32(&regs->jrcr, JRCR_RESET);
+	do {
+		jrint = sec_in32(&regs->jrint);
+	} while (((jrint & JRINT_ERR_HALT_MASK) ==
+		  JRINT_ERR_HALT_INPROGRESS) && --timeout);
+
+	jrint = sec_in32(&regs->jrint);
+	if (((jrint & JRINT_ERR_HALT_MASK) !=
+	     JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
+		return -1;
+
+	timeout = 100000;
+	sec_out32(&regs->jrcr, JRCR_RESET);
+	do {
+		jrcr = sec_in32(&regs->jrcr);
+	} while ((jrcr & JRCR_RESET) && --timeout);
+
+	if (timeout == 0)
+		return -1;
+
+	return 0;
+}
+
+/* -1 --- error, can't enqueue -- no space available */
+static int jr_enqueue(uint32_t *desc_addr,
+	       void (*callback)(uint32_t desc, uint32_t status, void *arg),
+	       void *arg)
+{
+	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+	int head = jr.head;
+	dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
+
+	if (sec_in32(&regs->irsa) == 0 ||
+	    CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
+		return -1;
+
+	jr.input_ring[head] = desc_phys_addr;
+	jr.info[head].desc_phys_addr = desc_phys_addr;
+	jr.info[head].desc_addr = (uint32_t)desc_addr;
+	jr.info[head].callback = (void *)callback;
+	jr.info[head].arg = arg;
+	jr.info[head].op_done = 0;
+
+	jr.head = (head + 1) & (jr.size - 1);
+
+	sec_out32(&regs->irja, 1);
+
+	return 0;
+}
+
+static int jr_dequeue(void)
+{
+	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+	int head = jr.head;
+	int tail = jr.tail;
+	int idx, i, found;
+	void (*callback)(uint32_t desc, uint32_t status, void *arg);
+	void *arg = NULL;
+
+	while (sec_in32(&regs->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
+		found = 0;
+
+		dma_addr_t op_desc = jr.output_ring[jr.tail].desc;
+		uint32_t status = jr.output_ring[jr.tail].status;
+		uint32_t desc_virt;
+
+		for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) {
+			idx = (tail + i) & (jr.size - 1);
+			if (op_desc == jr.info[idx].desc_phys_addr) {
+				desc_virt = jr.info[idx].desc_addr;
+				found = 1;
+				break;
+			}
+		}
+
+		/* Error condition if match not found */
+		if (!found)
+			return -1;
+
+		jr.info[idx].op_done = 1;
+		callback = (void *)jr.info[idx].callback;
+		arg = jr.info[idx].arg;
+
+		/* When the job on tail idx gets done, increment
+		 * tail till the point where job completed out of oredr has
+		 * been taken into account
+		 */
+		if (idx == tail)
+			do {
+				tail = (tail + 1) & (jr.size - 1);
+			} while (jr.info[tail].op_done);
+
+		jr.tail = tail;
+		jr.read_idx = (jr.read_idx + 1) & (jr.size - 1);
+
+		sec_out32(&regs->orjr, 1);
+		jr.info[idx].op_done = 0;
+
+		callback(desc_virt, status, arg);
+	}
+
+	return 0;
+}
+
+static void desc_done(uint32_t desc, uint32_t status, void *arg)
+{
+	struct result *x = arg;
+	x->status = status;
+	caam_jr_strstatus(status);
+	x->done = 1;
+}
+
+int run_descriptor_jr(uint32_t *desc)
+{
+	unsigned long long timeval = get_ticks();
+	unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
+	struct result op;
+	int ret = 0;
+
+	memset(&op, sizeof(op), 0);
+
+	ret = jr_enqueue(desc, desc_done, &op);
+	if (ret) {
+		debug("Error in SEC enq\n");
+		ret = JQ_ENQ_ERR;
+		goto out;
+	}
+
+	timeval = get_ticks();
+	timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
+	while (op.done != 1) {
+		ret = jr_dequeue();
+		if (ret) {
+			debug("Error in SEC deq\n");
+			ret = JQ_DEQ_ERR;
+			goto out;
+		}
+
+		if ((get_ticks() - timeval) > timeout) {
+			debug("SEC Dequeue timed out\n");
+			ret = JQ_DEQ_TO_ERR;
+			goto out;
+		}
+	}
+
+	if (!op.status) {
+		debug("Error %x\n", op.status);
+		ret = op.status;
+	}
+out:
+	return ret;
+}
+
+int jr_reset(void)
+{
+	if (jr_hw_reset() < 0)
+		return -1;
+
+	/* Clean up the jobring structure maintained by software */
+	jr_sw_cleanup();
+
+	return 0;
+}
+
+int sec_reset(void)
+{
+	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	uint32_t mcfgr = sec_in32(&sec->mcfgr);
+	uint32_t timeout = 100000;
+
+	mcfgr |= MCFGR_SWRST;
+	sec_out32(&sec->mcfgr, mcfgr);
+
+	mcfgr |= MCFGR_DMA_RST;
+	sec_out32(&sec->mcfgr, mcfgr);
+	do {
+		mcfgr = sec_in32(&sec->mcfgr);
+	} while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
+
+	if (timeout == 0)
+		return -1;
+
+	timeout = 100000;
+	do {
+		mcfgr = sec_in32(&sec->mcfgr);
+	} while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
+
+	if (timeout == 0)
+		return -1;
+
+	return 0;
+}
+
+static int instantiate_rng(void)
+{
+	struct result op;
+	u32 *desc;
+	u32 rdsta_val;
+	int ret = 0;
+	ccsr_sec_t __iomem *sec =
+			(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+	struct rng4tst __iomem *rng =
+			(struct rng4tst __iomem *)&sec->rng;
+
+	memset(&op, 0, sizeof(struct result));
+
+	desc = malloc(sizeof(int) * 6);
+	if (!desc) {
+		printf("cannot allocate RNG init descriptor memory\n");
+		return -1;
+	}
+
+	inline_cnstr_jobdesc_rng_instantiation(desc);
+	ret = run_descriptor_jr(desc);
+
+	if (ret)
+		printf("RNG: Instantiation failed with error %x\n", ret);
+
+	rdsta_val = sec_in32(&rng->rdsta);
+	if (op.status || !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED))
+		return -1;
+
+	return ret;
+}
+
+static u8 get_rng_vid(void)
+{
+	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	u32 cha_vid = sec_in32(&sec->chavid_ls);
+
+	return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
+}
+
+/*
+ * By default, the TRNG runs for 200 clocks per sample;
+ * 1200 clocks per sample generates better entropy.
+ */
+static void kick_trng(int ent_delay)
+{
+	ccsr_sec_t __iomem *sec =
+			(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+	struct rng4tst __iomem *rng =
+			(struct rng4tst __iomem *)&sec->rng;
+	u32 val;
+
+	/* put RNG4 into program mode */
+	sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
+	/* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
+	 * length (in system clocks) of each Entropy sample taken
+	 * */
+	val = sec_in32(&rng->rtsdctl);
+	val = (val & ~RTSDCTL_ENT_DLY_MASK) |
+	      (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
+	sec_out32(&rng->rtsdctl, val);
+	/* min. freq. count, equal to 1/4 of the entropy sample length */
+	sec_out32(&rng->rtfreqmin, ent_delay >> 2);
+	/* max. freq. count, equal to 8 times the entropy sample length */
+	sec_out32(&rng->rtfreqmax, ent_delay << 3);
+	/* put RNG4 into run mode */
+	sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
+}
+
+static int rng_init(void)
+{
+	int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
+	ccsr_sec_t __iomem *sec =
+			(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+	struct rng4tst __iomem *rng =
+			(struct rng4tst __iomem *)&sec->rng;
+
+	u32 rdsta = sec_in32(&rng->rdsta);
+
+	/* Check if RNG state 0 handler is already instantiated */
+	if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED)
+		return 0;
+
+	do {
+		/*
+		 * If either of the SH's were instantiated by somebody else
+		 * then it is assumed that the entropy
+		 * parameters are properly set and thus the function
+		 * setting these (kick_trng(...)) is skipped.
+		 * Also, if a handle was instantiated, do not change
+		 * the TRNG parameters.
+		 */
+		kick_trng(ent_delay);
+		ent_delay += 400;
+		/*
+		 * if instantiate_rng(...) fails, the loop will rerun
+		 * and the kick_trng(...) function will modfiy the
+		 * upper and lower limits of the entropy sampling
+		 * interval, leading to a sucessful initialization of
+		 * the RNG.
+		 */
+		ret = instantiate_rng();
+	} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
+	if (ret) {
+		printf("RNG: Failed to instantiate RNG\n");
+		return ret;
+	}
+
+	 /* Enable RDB bit so that RNG works faster */
+	sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
+
+	return ret;
+}
+
+int sec_init(void)
+{
+	int ret = 0;
+
+#ifdef CONFIG_PHYS_64BIT
+	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	uint32_t mcr = sec_in32(&sec->mcfgr);
+
+	sec_out32(&sec->mcfgr, mcr | 1 << MCFGR_PS_SHIFT);
+#endif
+	ret = jr_init();
+	if (ret < 0) {
+		printf("SEC initialization failed\n");
+		return -1;
+	}
+
+	if (get_rng_vid() >= 4) {
+		if (rng_init() < 0) {
+			printf("RNG instantiation failed\n");
+			return -1;
+		}
+		printf("SEC: RNG instantiated\n");
+	}
+
+	return ret;
+}
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
new file mode 100644
index 00000000000..cce2c589ce0
--- /dev/null
+++ b/drivers/crypto/fsl/jr.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef __JR_H
+#define __JR_H
+
+#include <linux/compiler.h>
+
+#define JR_SIZE 4
+/* Timeout currently defined as 90 sec */
+#define CONFIG_SEC_DEQ_TIMEOUT	90000000U
+
+#define DEFAULT_JR_ID		0
+#define DEFAULT_JR_LIODN	0
+#define DEFAULT_IRQ		0	/* Interrupts not to be configured */
+
+#define MCFGR_SWRST       ((uint32_t)(1)<<31) /* Software Reset */
+#define MCFGR_DMA_RST     ((uint32_t)(1)<<28) /* DMA Reset */
+#define MCFGR_PS_SHIFT          16
+#define JR_INTMASK	  0x00000001
+#define JRCR_RESET                  0x01
+#define JRINT_ERR_HALT_INPROGRESS   0x4
+#define JRINT_ERR_HALT_MASK         0xc
+#define JRNSLIODN_SHIFT		16
+#define JRNSLIODN_MASK		0x0fff0000
+#define JRSLIODN_SHIFT		0
+#define JRSLIODN_MASK		0x00000fff
+
+#define JQ_DEQ_ERR		-1
+#define JQ_DEQ_TO_ERR		-2
+#define JQ_ENQ_ERR		-3
+
+struct op_ring {
+	dma_addr_t desc;
+	uint32_t status;
+} __packed;
+
+struct jr_info {
+	void (*callback)(dma_addr_t desc, uint32_t status, void *arg);
+	dma_addr_t desc_phys_addr;
+	uint32_t desc_addr;
+	uint32_t desc_len;
+	uint32_t op_done;
+	void *arg;
+};
+
+struct jobring {
+	int jq_id;
+	int irq;
+	int liodn;
+	/* Head is the index where software would enq the descriptor in
+	 * the i/p ring
+	 */
+	int head;
+	/* Tail index would be used by s/w ehile enqueuing to determine if
+	 * there is any space left in the s/w maintained i/p rings
+	 */
+	/* Also in case of deq tail will be incremented only in case of
+	 * in-order job completion
+	 */
+	int tail;
+	/* Read index of the output ring. It may not match with tail in case
+	 * of out of order completetion
+	 */
+	int read_idx;
+	/* Write index to input ring. Would be always equal to head */
+	int write_idx;
+	/* Size of the rings. */
+	int size;
+	/* The ip and output rings have to be accessed by SEC. So the
+	 * pointers will ahve to point to the housekeeping region provided
+	 * by SEC
+	 */
+	/*Circular  Ring of i/p descriptors */
+	dma_addr_t *input_ring;
+	/* Circular Ring of o/p descriptors */
+	/* Circula Ring containing info regarding descriptors in i/p
+	 * and o/p ring
+	 */
+	/* This ring can be on the stack */
+	struct jr_info info[JR_SIZE];
+	struct op_ring *output_ring;
+};
+
+struct result {
+	int done;
+	uint32_t status;
+};
+
+void caam_jr_strstatus(u32 status);
+int run_descriptor_jr(uint32_t *desc);
+
+#endif
diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c
index 91f6df220b1..c3d3c3bcd85 100644
--- a/drivers/dfu/dfu_sf.c
+++ b/drivers/dfu/dfu_sf.c
@@ -9,6 +9,7 @@
 #include <errno.h>
 #include <div64.h>
 #include <dfu.h>
+#include <spi.h>
 #include <spi_flash.h>
 
 static long dfu_get_medium_size_sf(struct dfu_entity *dfu)
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index a79c3919ddc..4c8fcc25756 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -8,3 +8,5 @@
 obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
 obj-$(CONFIG_APBH_DMA) += apbh_dma.o
 obj-$(CONFIG_FSL_DMA) += fsl_dma.o
+obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o
+obj-$(CONFIG_TI_EDMA3) += ti-edma3.o
diff --git a/arch/arm/cpu/armv7/keystone/keystone_nav.c b/drivers/dma/keystone_nav.c
index 39d6f995f7b..77707c21098 100644
--- a/arch/arm/cpu/armv7/keystone/keystone_nav.c
+++ b/drivers/dma/keystone_nav.c
@@ -8,28 +8,23 @@
  */
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/keystone_nav.h>
-
-static int soc_type =
-#ifdef CONFIG_SOC_K2HK
-	k2hk;
-#endif
-
-struct qm_config k2hk_qm_memmap = {
-	.stat_cfg	= 0x02a40000,
-	.queue		= (struct qm_reg_queue *)0x02a80000,
-	.mngr_vbusm	= 0x23a80000,
-	.i_lram		= 0x00100000,
-	.proxy		= (struct qm_reg_queue *)0x02ac0000,
-	.status_ram	= 0x02a06000,
-	.mngr_cfg	= (struct qm_cfg_reg *)0x02a02000,
-	.intd_cfg	= 0x02a0c000,
-	.desc_mem	= (struct descr_mem_setup_reg *)0x02a03000,
-	.region_num	= 64,
-	.pdsp_cmd	= 0x02a20000,
-	.pdsp_ctl	= 0x02a0f000,
-	.pdsp_iram	= 0x02a10000,
-	.qpool_num	= 4000,
+#include <asm/ti-common/keystone_nav.h>
+
+struct qm_config qm_memmap = {
+	.stat_cfg	= CONFIG_KSNAV_QM_QUEUE_STATUS_BASE,
+	.queue		= (void *)CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE,
+	.mngr_vbusm	= CONFIG_KSNAV_QM_BASE_ADDRESS,
+	.i_lram		= CONFIG_KSNAV_QM_LINK_RAM_BASE,
+	.proxy		= (void *)CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE,
+	.status_ram	= CONFIG_KSNAV_QM_STATUS_RAM_BASE,
+	.mngr_cfg	= (void *)CONFIG_KSNAV_QM_CONF_BASE,
+	.intd_cfg	= CONFIG_KSNAV_QM_INTD_CONF_BASE,
+	.desc_mem	= (void *)CONFIG_KSNAV_QM_DESC_SETUP_BASE,
+	.region_num	= CONFIG_KSNAV_QM_REGION_NUM,
+	.pdsp_cmd	= CONFIG_KSNAV_QM_PDSP1_CMD_BASE,
+	.pdsp_ctl	= CONFIG_KSNAV_QM_PDSP1_CTRL_BASE,
+	.pdsp_iram	= CONFIG_KSNAV_QM_PDSP1_IRAM_BASE,
+	.qpool_num	= CONFIG_KSNAV_QM_QPOOL_NUM,
 };
 
 /*
@@ -52,12 +47,9 @@ inline int num_of_desc_to_reg(int num_descr)
 	return 15;
 }
 
-static int _qm_init(struct qm_config *cfg)
+int _qm_init(struct qm_config *cfg)
 {
-	u32	j;
-
-	if (cfg == NULL)
-		return QM_ERR;
+	u32 j;
 
 	qm_cfg = cfg;
 
@@ -82,12 +74,7 @@ static int _qm_init(struct qm_config *cfg)
 
 int qm_init(void)
 {
-	switch (soc_type) {
-	case k2hk:
-		return _qm_init(&k2hk_qm_memmap);
-	}
-
-	return QM_ERR;
+	return _qm_init(&qm_memmap);
 }
 
 void qm_close(void)
@@ -166,39 +153,23 @@ void queue_close(u32 qnum)
 		;
 }
 
-/*
+/**
  * DMA API
  */
 
-struct pktdma_cfg k2hk_netcp_pktdma = {
-	.global		= (struct global_ctl_regs *)0x02004000,
-	.tx_ch		= (struct tx_chan_regs *)0x02004400,
-	.tx_ch_num	= 9,
-	.rx_ch		= (struct rx_chan_regs *)0x02004800,
-	.rx_ch_num	= 26,
-	.tx_sched	= (u32 *)0x02004c00,
-	.rx_flows	= (struct rx_flow_regs *)0x02005000,
-	.rx_flow_num	= 32,
-	.rx_free_q	= 4001,
-	.rx_rcv_q	= 4002,
-	.tx_snd_q	= 648,
-};
-
-struct pktdma_cfg *netcp;
-
-static int netcp_rx_disable(void)
+static int ksnav_rx_disable(struct pktdma_cfg *pktdma)
 {
 	u32 j, v, k;
 
-	for (j = 0; j < netcp->rx_ch_num; j++) {
-		v = readl(&netcp->rx_ch[j].cfg_a);
+	for (j = 0; j < pktdma->rx_ch_num; j++) {
+		v = readl(&pktdma->rx_ch[j].cfg_a);
 		if (!(v & CPDMA_CHAN_A_ENABLE))
 			continue;
 
-		writel(v | CPDMA_CHAN_A_TDOWN, &netcp->rx_ch[j].cfg_a);
+		writel(v | CPDMA_CHAN_A_TDOWN, &pktdma->rx_ch[j].cfg_a);
 		for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
 			udelay(100);
-			v = readl(&netcp->rx_ch[j].cfg_a);
+			v = readl(&pktdma->rx_ch[j].cfg_a);
 			if (!(v & CPDMA_CHAN_A_ENABLE))
 				continue;
 		}
@@ -206,33 +177,33 @@ static int netcp_rx_disable(void)
 	}
 
 	/* Clear all of the flow registers */
-	for (j = 0; j < netcp->rx_flow_num; j++) {
-		writel(0, &netcp->rx_flows[j].control);
-		writel(0, &netcp->rx_flows[j].tags);
-		writel(0, &netcp->rx_flows[j].tag_sel);
-		writel(0, &netcp->rx_flows[j].fdq_sel[0]);
-		writel(0, &netcp->rx_flows[j].fdq_sel[1]);
-		writel(0, &netcp->rx_flows[j].thresh[0]);
-		writel(0, &netcp->rx_flows[j].thresh[1]);
-		writel(0, &netcp->rx_flows[j].thresh[2]);
+	for (j = 0; j < pktdma->rx_flow_num; j++) {
+		writel(0, &pktdma->rx_flows[j].control);
+		writel(0, &pktdma->rx_flows[j].tags);
+		writel(0, &pktdma->rx_flows[j].tag_sel);
+		writel(0, &pktdma->rx_flows[j].fdq_sel[0]);
+		writel(0, &pktdma->rx_flows[j].fdq_sel[1]);
+		writel(0, &pktdma->rx_flows[j].thresh[0]);
+		writel(0, &pktdma->rx_flows[j].thresh[1]);
+		writel(0, &pktdma->rx_flows[j].thresh[2]);
 	}
 
 	return QM_OK;
 }
 
-static int netcp_tx_disable(void)
+static int ksnav_tx_disable(struct pktdma_cfg *pktdma)
 {
 	u32 j, v, k;
 
-	for (j = 0; j < netcp->tx_ch_num; j++) {
-		v = readl(&netcp->tx_ch[j].cfg_a);
+	for (j = 0; j < pktdma->tx_ch_num; j++) {
+		v = readl(&pktdma->tx_ch[j].cfg_a);
 		if (!(v & CPDMA_CHAN_A_ENABLE))
 			continue;
 
-		writel(v | CPDMA_CHAN_A_TDOWN, &netcp->tx_ch[j].cfg_a);
+		writel(v | CPDMA_CHAN_A_TDOWN, &pktdma->tx_ch[j].cfg_a);
 		for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
 			udelay(100);
-			v = readl(&netcp->tx_ch[j].cfg_a);
+			v = readl(&pktdma->tx_ch[j].cfg_a);
 			if (!(v & CPDMA_CHAN_A_ENABLE))
 				continue;
 		}
@@ -242,19 +213,17 @@ static int netcp_tx_disable(void)
 	return QM_OK;
 }
 
-static int _netcp_init(struct pktdma_cfg *netcp_cfg,
-		       struct rx_buff_desc *rx_buffers)
+int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers)
 {
 	u32 j, v;
 	struct qm_host_desc *hd;
 	u8 *rx_ptr;
 
-	if (netcp_cfg == NULL || rx_buffers == NULL ||
+	if (pktdma == NULL || rx_buffers == NULL ||
 	    rx_buffers->buff_ptr == NULL || qm_cfg == NULL)
 		return QM_ERR;
 
-	netcp = netcp_cfg;
-	netcp->rx_flow = rx_buffers->rx_flow;
+	pktdma->rx_flow = rx_buffers->rx_flow;
 
 	/* init rx queue */
 	rx_ptr = rx_buffers->buff_ptr;
@@ -264,77 +233,64 @@ static int _netcp_init(struct pktdma_cfg *netcp_cfg,
 		if (hd == NULL)
 			return QM_ERR;
 
-		qm_buff_push(hd, netcp->rx_free_q,
+		qm_buff_push(hd, pktdma->rx_free_q,
 			     rx_ptr, rx_buffers->buff_len);
 
 		rx_ptr += rx_buffers->buff_len;
 	}
 
-	netcp_rx_disable();
+	ksnav_rx_disable(pktdma);
 
 	/* configure rx channels */
-	v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, netcp->rx_rcv_q);
-	writel(v, &netcp->rx_flows[netcp->rx_flow].control);
-	writel(0, &netcp->rx_flows[netcp->rx_flow].tags);
-	writel(0, &netcp->rx_flows[netcp->rx_flow].tag_sel);
+	v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, pktdma->rx_rcv_q);
+	writel(v, &pktdma->rx_flows[pktdma->rx_flow].control);
+	writel(0, &pktdma->rx_flows[pktdma->rx_flow].tags);
+	writel(0, &pktdma->rx_flows[pktdma->rx_flow].tag_sel);
 
-	v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, netcp->rx_free_q, 0,
-					 netcp->rx_free_q);
+	v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, pktdma->rx_free_q, 0,
+					 pktdma->rx_free_q);
 
-	writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[0]);
-	writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[1]);
-	writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[0]);
-	writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[1]);
-	writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[2]);
+	writel(v, &pktdma->rx_flows[pktdma->rx_flow].fdq_sel[0]);
+	writel(v, &pktdma->rx_flows[pktdma->rx_flow].fdq_sel[1]);
+	writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[0]);
+	writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[1]);
+	writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[2]);
 
-	for (j = 0; j < netcp->rx_ch_num; j++)
-		writel(CPDMA_CHAN_A_ENABLE, &netcp->rx_ch[j].cfg_a);
+	for (j = 0; j < pktdma->rx_ch_num; j++)
+		writel(CPDMA_CHAN_A_ENABLE, &pktdma->rx_ch[j].cfg_a);
 
 	/* configure tx channels */
 	/* Disable loopback in the tx direction */
-	writel(0, &netcp->global->emulation_control);
+	writel(0, &pktdma->global->emulation_control);
 
-/* TODO: make it dependend on a soc type variable */
-#ifdef CONFIG_SOC_K2HK
 	/* Set QM base address, only for K2x devices */
-	writel(0x23a80000, &netcp->global->qm_base_addr[0]);
-#endif
+	writel(CONFIG_KSNAV_QM_BASE_ADDRESS, &pktdma->global->qm_base_addr[0]);
 
 	/* Enable all channels. The current state isn't important */
-	for (j = 0; j < netcp->tx_ch_num; j++)  {
-		writel(0, &netcp->tx_ch[j].cfg_b);
-		writel(CPDMA_CHAN_A_ENABLE, &netcp->tx_ch[j].cfg_a);
+	for (j = 0; j < pktdma->tx_ch_num; j++)  {
+		writel(0, &pktdma->tx_ch[j].cfg_b);
+		writel(CPDMA_CHAN_A_ENABLE, &pktdma->tx_ch[j].cfg_a);
 	}
 
 	return QM_OK;
 }
 
-int netcp_init(struct rx_buff_desc *rx_buffers)
-{
-	switch (soc_type) {
-	case k2hk:
-		_netcp_init(&k2hk_netcp_pktdma, rx_buffers);
-		return QM_OK;
-	}
-	return QM_ERR;
-}
-
-int netcp_close(void)
+int ksnav_close(struct pktdma_cfg *pktdma)
 {
-	if (!netcp)
+	if (!pktdma)
 		return QM_ERR;
 
-	netcp_tx_disable();
-	netcp_rx_disable();
+	ksnav_tx_disable(pktdma);
+	ksnav_rx_disable(pktdma);
 
-	queue_close(netcp->rx_free_q);
-	queue_close(netcp->rx_rcv_q);
-	queue_close(netcp->tx_snd_q);
+	queue_close(pktdma->rx_free_q);
+	queue_close(pktdma->rx_rcv_q);
+	queue_close(pktdma->tx_snd_q);
 
 	return QM_OK;
 }
 
-int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2)
+int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2)
 {
 	struct qm_host_desc *hd;
 
@@ -346,16 +302,16 @@ int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2)
 	hd->swinfo[2]	= swinfo2;
 	hd->packet_info = qm_cfg->qpool_num;
 
-	qm_buff_push(hd, netcp->tx_snd_q, pkt, num_bytes);
+	qm_buff_push(hd, pktdma->tx_snd_q, pkt, num_bytes);
 
 	return QM_OK;
 }
 
-void *netcp_recv(u32 **pkt, int *num_bytes)
+void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes)
 {
 	struct qm_host_desc *hd;
 
-	hd = qm_pop(netcp->rx_rcv_q);
+	hd = qm_pop(pktdma->rx_rcv_q);
 	if (!hd)
 		return NULL;
 
@@ -365,12 +321,12 @@ void *netcp_recv(u32 **pkt, int *num_bytes)
 	return hd;
 }
 
-void netcp_release_rxhd(void *hd)
+void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd)
 {
 	struct qm_host_desc *_hd = (struct qm_host_desc *)hd;
 
 	_hd->buff_len = _hd->orig_buff_len;
 	_hd->buff_ptr = _hd->orig_buff_ptr;
 
-	qm_push(_hd, netcp->rx_free_q);
+	qm_push(_hd, pktdma->rx_free_q);
 }
diff --git a/drivers/dma/keystone_nav_cfg.c b/drivers/dma/keystone_nav_cfg.c
new file mode 100644
index 00000000000..bdd30a02625
--- /dev/null
+++ b/drivers/dma/keystone_nav_cfg.c
@@ -0,0 +1,27 @@
+/*
+ * Multicore Navigator driver for TI Keystone 2 devices.
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <asm/ti-common/keystone_nav.h>
+
+#ifdef CONFIG_KSNAV_PKTDMA_NETCP
+/* NETCP Pktdma */
+struct pktdma_cfg netcp_pktdma = {
+	.global		= (void *)CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE,
+	.tx_ch		= (void *)CONFIG_KSNAV_NETCP_PDMA_TX_BASE,
+	.tx_ch_num	= CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM,
+	.rx_ch		= (void *)CONFIG_KSNAV_NETCP_PDMA_RX_BASE,
+	.rx_ch_num	= CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM,
+	.tx_sched	= (u32 *)CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE,
+	.rx_flows	= (void *)CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE,
+	.rx_flow_num	= CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM,
+	.rx_free_q	= CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE,
+	.rx_rcv_q	= CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE,
+	.tx_snd_q	= CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE,
+};
+#endif
diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c
new file mode 100644
index 00000000000..8184ded9fa8
--- /dev/null
+++ b/drivers/dma/ti-edma3.c
@@ -0,0 +1,384 @@
+/*
+ * Enhanced Direct Memory Access (EDMA3) Controller
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Author: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <asm/ti-common/ti-edma3.h>
+
+#define EDMA3_SL_BASE(slot)			(0x4000 + ((slot) << 5))
+#define EDMA3_SL_MAX_NUM			512
+#define EDMA3_SLOPT_FIFO_WIDTH_MASK		(0x7 << 8)
+
+#define EDMA3_QCHMAP(ch)			0x0200 + ((ch) << 2)
+#define EDMA3_CHMAP_PARSET_MASK			0x1ff
+#define EDMA3_CHMAP_PARSET_SHIFT		0x5
+#define EDMA3_CHMAP_TRIGWORD_SHIFT		0x2
+
+#define EDMA3_QEMCR				0x314
+#define EDMA3_IPR				0x1068
+#define EDMA3_IPRH				0x106c
+#define EDMA3_ICR				0x1070
+#define EDMA3_ICRH				0x1074
+#define EDMA3_QEECR				0x1088
+#define EDMA3_QEESR				0x108c
+#define EDMA3_QSECR				0x1094
+
+/**
+ * qedma3_start - start qdma on a channel
+ * @base: base address of edma
+ * @cfg: pinter to struct edma3_channel_config where you can set
+ * the slot number to associate with, the chnum, which corresponds
+ * your quick channel number 0-7, complete code - transfer complete code
+ * and trigger slot word - which has to correspond to the word number in
+ * edma3_slot_layout struct for generating event.
+ *
+ */
+void qedma3_start(u32 base, struct edma3_channel_config *cfg)
+{
+	u32 qchmap;
+
+	/* Clear the pending int bit */
+	if (cfg->complete_code < 32)
+		__raw_writel(1 << cfg->complete_code, base + EDMA3_ICR);
+	else
+		__raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH);
+
+	/* Map parameter set and trigger word 7 to quick channel */
+	qchmap = ((EDMA3_CHMAP_PARSET_MASK & cfg->slot)
+		  << EDMA3_CHMAP_PARSET_SHIFT) |
+		  (cfg->trigger_slot_word << EDMA3_CHMAP_TRIGWORD_SHIFT);
+
+	__raw_writel(qchmap, base + EDMA3_QCHMAP(cfg->chnum));
+
+	/* Clear missed event if set*/
+	__raw_writel(1 << cfg->chnum, base + EDMA3_QSECR);
+	__raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR);
+
+	/* Enable qdma channel event */
+	__raw_writel(1 << cfg->chnum, base + EDMA3_QEESR);
+}
+
+/**
+ * edma3_set_dest - set initial DMA destination address in parameter RAM slot
+ * @base: base address of edma
+ * @slot: parameter RAM slot being configured
+ * @dst: physical address of destination (memory, controller FIFO, etc)
+ * @addressMode: INCR, except in very rare cases
+ * @width: ignored unless @addressMode is FIFO, else specifies the
+ *	width to use when addressing the fifo (e.g. W8BIT, W32BIT)
+ *
+ * Note that the destination address is modified during the DMA transfer
+ * according to edma3_set_dest_index().
+ */
+void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode,
+		    enum edma3_fifo_width width)
+{
+	u32 opt;
+	struct edma3_slot_layout *rg;
+
+	rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
+
+	opt = __raw_readl(&rg->opt);
+	if (mode == FIFO)
+		opt = (opt & EDMA3_SLOPT_FIFO_WIDTH_MASK) |
+		       (EDMA3_SLOPT_DST_ADDR_CONST_MODE |
+			EDMA3_SLOPT_FIFO_WIDTH_SET(width));
+	else
+		opt &= ~EDMA3_SLOPT_DST_ADDR_CONST_MODE;
+
+	__raw_writel(opt, &rg->opt);
+	__raw_writel(dst, &rg->dst);
+}
+
+/**
+ * edma3_set_dest_index - configure DMA destination address indexing
+ * @base: base address of edma
+ * @slot: parameter RAM slot being configured
+ * @bidx: byte offset between destination arrays in a frame
+ * @cidx: byte offset between destination frames in a block
+ *
+ * Offsets are specified to support either contiguous or discontiguous
+ * memory transfers, or repeated access to a hardware register, as needed.
+ * When accessing hardware registers, both offsets are normally zero.
+ */
+void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx)
+{
+	u32 src_dst_bidx;
+	u32 src_dst_cidx;
+	struct edma3_slot_layout *rg;
+
+	rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
+
+	src_dst_bidx = __raw_readl(&rg->src_dst_bidx);
+	src_dst_cidx = __raw_readl(&rg->src_dst_cidx);
+
+	__raw_writel((src_dst_bidx & 0x0000ffff) | (bidx << 16),
+		     &rg->src_dst_bidx);
+	__raw_writel((src_dst_cidx & 0x0000ffff) | (cidx << 16),
+		     &rg->src_dst_cidx);
+}
+
+/**
+ * edma3_set_dest_addr - set destination address for slot only
+ */
+void edma3_set_dest_addr(u32 base, int slot, u32 dst)
+{
+	struct edma3_slot_layout *rg;
+
+	rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
+	__raw_writel(dst, &rg->dst);
+}
+
+/**
+ * edma3_set_src - set initial DMA source address in parameter RAM slot
+ * @base: base address of edma
+ * @slot: parameter RAM slot being configured
+ * @src_port: physical address of source (memory, controller FIFO, etc)
+ * @mode: INCR, except in very rare cases
+ * @width: ignored unless @addressMode is FIFO, else specifies the
+ *	width to use when addressing the fifo (e.g. W8BIT, W32BIT)
+ *
+ * Note that the source address is modified during the DMA transfer
+ * according to edma3_set_src_index().
+ */
+void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode,
+		   enum edma3_fifo_width width)
+{
+	u32 opt;
+	struct edma3_slot_layout *rg;
+
+	rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
+
+	opt = __raw_readl(&rg->opt);
+	if (mode == FIFO)
+		opt = (opt & EDMA3_SLOPT_FIFO_WIDTH_MASK) |
+		       (EDMA3_SLOPT_DST_ADDR_CONST_MODE |
+			EDMA3_SLOPT_FIFO_WIDTH_SET(width));
+	else
+		opt &= ~EDMA3_SLOPT_DST_ADDR_CONST_MODE;
+
+	__raw_writel(opt, &rg->opt);
+	__raw_writel(src, &rg->src);
+}
+
+/**
+ * edma3_set_src_index - configure DMA source address indexing
+ * @base: base address of edma
+ * @slot: parameter RAM slot being configured
+ * @bidx: byte offset between source arrays in a frame
+ * @cidx: byte offset between source frames in a block
+ *
+ * Offsets are specified to support either contiguous or discontiguous
+ * memory transfers, or repeated access to a hardware register, as needed.
+ * When accessing hardware registers, both offsets are normally zero.
+ */
+void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx)
+{
+	u32 src_dst_bidx;
+	u32 src_dst_cidx;
+	struct edma3_slot_layout *rg;
+
+	rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
+
+	src_dst_bidx = __raw_readl(&rg->src_dst_bidx);
+	src_dst_cidx = __raw_readl(&rg->src_dst_cidx);
+
+	__raw_writel((src_dst_bidx & 0xffff0000) | bidx,
+		     &rg->src_dst_bidx);
+	__raw_writel((src_dst_cidx & 0xffff0000) | cidx,
+		     &rg->src_dst_cidx);
+}
+
+/**
+ * edma3_set_src_addr - set source address for slot only
+ */
+void edma3_set_src_addr(u32 base, int slot, u32 src)
+{
+	struct edma3_slot_layout *rg;
+
+	rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
+	__raw_writel(src, &rg->src);
+}
+
+/**
+ * edma3_set_transfer_params - configure DMA transfer parameters
+ * @base: base address of edma
+ * @slot: parameter RAM slot being configured
+ * @acnt: how many bytes per array (at least one)
+ * @bcnt: how many arrays per frame (at least one)
+ * @ccnt: how many frames per block (at least one)
+ * @bcnt_rld: used only for A-Synchronized transfers; this specifies
+ *	the value to reload into bcnt when it decrements to zero
+ * @sync_mode: ASYNC or ABSYNC
+ *
+ * See the EDMA3 documentation to understand how to configure and link
+ * transfers using the fields in PaRAM slots.  If you are not doing it
+ * all at once with edma3_write_slot(), you will use this routine
+ * plus two calls each for source and destination, setting the initial
+ * address and saying how to index that address.
+ *
+ * An example of an A-Synchronized transfer is a serial link using a
+ * single word shift register.  In that case, @acnt would be equal to
+ * that word size; the serial controller issues a DMA synchronization
+ * event to transfer each word, and memory access by the DMA transfer
+ * controller will be word-at-a-time.
+ *
+ * An example of an AB-Synchronized transfer is a device using a FIFO.
+ * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
+ * The controller with the FIFO issues DMA synchronization events when
+ * the FIFO threshold is reached, and the DMA transfer controller will
+ * transfer one frame to (or from) the FIFO.  It will probably use
+ * efficient burst modes to access memory.
+ */
+void edma3_set_transfer_params(u32 base, int slot, int acnt,
+			       int bcnt, int ccnt, u16 bcnt_rld,
+			       enum edma3_sync_dimension sync_mode)
+{
+	u32 opt;
+	u32 link_bcntrld;
+	struct edma3_slot_layout *rg;
+
+	rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
+
+	link_bcntrld = __raw_readl(&rg->link_bcntrld);
+
+	__raw_writel((bcnt_rld << 16) | (0x0000ffff & link_bcntrld),
+		     &rg->link_bcntrld);
+
+	opt = __raw_readl(&rg->opt);
+	if (sync_mode == ASYNC)
+		__raw_writel(opt & ~EDMA3_SLOPT_AB_SYNC, &rg->opt);
+	else
+		__raw_writel(opt | EDMA3_SLOPT_AB_SYNC, &rg->opt);
+
+	/* Set the acount, bcount, ccount registers */
+	__raw_writel((bcnt << 16) | (acnt & 0xffff), &rg->a_b_cnt);
+	__raw_writel(0xffff & ccnt, &rg->ccnt);
+}
+
+/**
+ * edma3_write_slot - write parameter RAM data for slot
+ * @base: base address of edma
+ * @slot: number of parameter RAM slot being modified
+ * @param: data to be written into parameter RAM slot
+ *
+ * Use this to assign all parameters of a transfer at once.  This
+ * allows more efficient setup of transfers than issuing multiple
+ * calls to set up those parameters in small pieces, and provides
+ * complete control over all transfer options.
+ */
+void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param)
+{
+	int i;
+	u32 *p = (u32 *)param;
+	u32 *addr = (u32 *)(base + EDMA3_SL_BASE(slot));
+
+	for (i = 0; i < sizeof(struct edma3_slot_layout)/4; i += 4)
+		__raw_writel(*p++, addr++);
+}
+
+/**
+ * edma3_read_slot - read parameter RAM data from slot
+ * @base: base address of edma
+ * @slot: number of parameter RAM slot being copied
+ * @param: where to store copy of parameter RAM data
+ *
+ * Use this to read data from a parameter RAM slot, perhaps to
+ * save them as a template for later reuse.
+ */
+void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param)
+{
+	int i;
+	u32 *p = (u32 *)param;
+	u32 *addr = (u32 *)(base + EDMA3_SL_BASE(slot));
+
+	for (i = 0; i < sizeof(struct edma3_slot_layout)/4; i += 4)
+		*p++ = __raw_readl(addr++);
+}
+
+void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg)
+{
+	struct edma3_slot_layout *rg;
+
+	rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
+
+	__raw_writel(cfg->opt, &rg->opt);
+	__raw_writel(cfg->src, &rg->src);
+	__raw_writel((cfg->bcnt << 16) | (cfg->acnt & 0xffff), &rg->a_b_cnt);
+	__raw_writel(cfg->dst, &rg->dst);
+	__raw_writel((cfg->dst_bidx << 16) |
+		     (cfg->src_bidx & 0xffff), &rg->src_dst_bidx);
+	__raw_writel((cfg->bcntrld << 16) |
+		     (cfg->link & 0xffff), &rg->link_bcntrld);
+	__raw_writel((cfg->dst_cidx << 16) |
+		     (cfg->src_cidx & 0xffff), &rg->src_dst_cidx);
+	__raw_writel(0xffff & cfg->ccnt, &rg->ccnt);
+}
+
+/**
+ * edma3_check_for_transfer - check if transfer coplete by checking
+ * interrupt pending bit. Clear interrupt pending bit if complete.
+ * @base: base address of edma
+ * @cfg: pinter to struct edma3_channel_config which was passed
+ * to qedma3_start when you started qdma channel
+ *
+ * Return 0 if complete, 1 if not.
+ */
+int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg)
+{
+	u32 inum;
+	u32 ipr_base;
+	u32 icr_base;
+
+	if (cfg->complete_code < 32) {
+		ipr_base = base + EDMA3_IPR;
+		icr_base = base + EDMA3_ICR;
+		inum = 1 << cfg->complete_code;
+	} else {
+		ipr_base = base + EDMA3_IPRH;
+		icr_base = base + EDMA3_ICRH;
+		inum = 1 << (cfg->complete_code - 32);
+	}
+
+	/* check complete interrupt */
+	if (!(__raw_readl(ipr_base) & inum))
+		return 1;
+
+	/* clean up the pending int bit */
+	__raw_writel(inum, icr_base);
+
+	return 0;
+}
+
+/**
+ * qedma3_stop - stops dma on the channel passed
+ * @base: base address of edma
+ * @cfg: pinter to struct edma3_channel_config which was passed
+ * to qedma3_start when you started qdma channel
+ */
+void qedma3_stop(u32 base, struct edma3_channel_config *cfg)
+{
+	/* Disable qdma channel event */
+	__raw_writel(1 << cfg->chnum, base + EDMA3_QEECR);
+
+	/* clean up the interrupt indication */
+	if (cfg->complete_code < 32)
+		__raw_writel(1 << cfg->complete_code, base + EDMA3_ICR);
+	else
+		__raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH);
+
+	/* Clear missed event if set*/
+	__raw_writel(1 << cfg->chnum, base + EDMA3_QSECR);
+	__raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR);
+
+	/* Clear the channel map */
+	__raw_writel(0, base + EDMA3_QCHMAP(cfg->chnum));
+}
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e69de29bb2d..d21302f8da9 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -0,0 +1,6 @@
+config DM_GPIO
+	bool "Enable Driver Model for GPIO drivers"
+	depends on DM
+	help
+	  If you want to use driver model for GPIO drivers, say Y.
+	  To use legacy GPIO drivers, say N.
diff --git a/drivers/gpio/bcm2835_gpio.c b/drivers/gpio/bcm2835_gpio.c
index 97b51371145..0244c018828 100644
--- a/drivers/gpio/bcm2835_gpio.c
+++ b/drivers/gpio/bcm2835_gpio.c
@@ -6,73 +6,118 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 
-inline int gpio_is_valid(unsigned gpio)
-{
-	return (gpio < BCM2835_GPIO_COUNT);
-}
-
-int gpio_request(unsigned gpio, const char *label)
-{
-	return !gpio_is_valid(gpio);
-}
+struct bcm2835_gpios {
+	struct bcm2835_gpio_regs *reg;
+};
 
-int gpio_free(unsigned gpio)
+static int bcm2835_gpio_direction_input(struct udevice *dev, unsigned gpio)
 {
-	return 0;
-}
-
-int gpio_direction_input(unsigned gpio)
-{
-	struct bcm2835_gpio_regs *reg =
-		(struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE;
+	struct bcm2835_gpios *gpios = dev_get_priv(dev);
 	unsigned val;
 
-	val = readl(&reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
+	val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
 	val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio));
 	val |= (BCM2835_GPIO_INPUT << BCM2835_GPIO_FSEL_SHIFT(gpio));
-	writel(val, &reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
+	writel(val, &gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
 
 	return 0;
 }
 
-int gpio_direction_output(unsigned gpio, int value)
+static int bcm2835_gpio_direction_output(struct udevice *dev, unsigned gpio,
+					 int value)
 {
-	struct bcm2835_gpio_regs *reg =
-		(struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE;
+	struct bcm2835_gpios *gpios = dev_get_priv(dev);
 	unsigned val;
 
 	gpio_set_value(gpio, value);
 
-	val = readl(&reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
+	val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
 	val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio));
 	val |= (BCM2835_GPIO_OUTPUT << BCM2835_GPIO_FSEL_SHIFT(gpio));
-	writel(val, &reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
+	writel(val, &gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
 
 	return 0;
 }
 
-int gpio_get_value(unsigned gpio)
+static bool bcm2835_gpio_is_output(const struct bcm2835_gpios *gpios, int gpio)
+{
+	u32 val;
+
+	val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
+	val &= BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio);
+	return val ? true : false;
+}
+
+static int bcm2835_get_value(const struct bcm2835_gpios *gpios, unsigned gpio)
 {
-	struct bcm2835_gpio_regs *reg =
-		(struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE;
 	unsigned val;
 
-	val = readl(&reg->gplev[BCM2835_GPIO_COMMON_BANK(gpio)]);
+	val = readl(&gpios->reg->gplev[BCM2835_GPIO_COMMON_BANK(gpio)]);
 
 	return (val >> BCM2835_GPIO_COMMON_SHIFT(gpio)) & 0x1;
 }
 
-int gpio_set_value(unsigned gpio, int value)
+static int bcm2835_gpio_get_value(struct udevice *dev, unsigned gpio)
+{
+	const struct bcm2835_gpios *gpios = dev_get_priv(dev);
+
+	return bcm2835_get_value(gpios, gpio);
+}
+
+static int bcm2835_gpio_set_value(struct udevice *dev, unsigned gpio,
+				  int value)
 {
-	struct bcm2835_gpio_regs *reg =
-		(struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE;
-	u32 *output_reg = value ? reg->gpset : reg->gpclr;
+	struct bcm2835_gpios *gpios = dev_get_priv(dev);
+	u32 *output_reg = value ? gpios->reg->gpset : gpios->reg->gpclr;
 
 	writel(1 << BCM2835_GPIO_COMMON_SHIFT(gpio),
 				&output_reg[BCM2835_GPIO_COMMON_BANK(gpio)]);
 
 	return 0;
 }
+
+static int bcm2835_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+	struct bcm2835_gpios *gpios = dev_get_priv(dev);
+
+	/* GPIOF_FUNC is not implemented yet */
+	if (bcm2835_gpio_is_output(gpios, offset))
+		return GPIOF_OUTPUT;
+	else
+		return GPIOF_INPUT;
+}
+
+
+static const struct dm_gpio_ops gpio_bcm2835_ops = {
+	.direction_input	= bcm2835_gpio_direction_input,
+	.direction_output	= bcm2835_gpio_direction_output,
+	.get_value		= bcm2835_gpio_get_value,
+	.set_value		= bcm2835_gpio_set_value,
+	.get_function		= bcm2835_gpio_get_function,
+};
+
+static int bcm2835_gpio_probe(struct udevice *dev)
+{
+	struct bcm2835_gpios *gpios = dev_get_priv(dev);
+	struct bcm2835_gpio_platdata *plat = dev_get_platdata(dev);
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+	uc_priv->bank_name = "GPIO";
+	uc_priv->gpio_count = BCM2835_GPIO_COUNT;
+	gpios->reg = (struct bcm2835_gpio_regs *)plat->base;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(gpio_bcm2835) = {
+	.name	= "gpio_bcm2835",
+	.id	= UCLASS_GPIO,
+	.ops	= &gpio_bcm2835_ops,
+	.probe	= bcm2835_gpio_probe,
+	.priv_auto_alloc_size = sizeof(struct bcm2835_gpios),
+};
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index f1bbc587961..45e9a5ad227 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -7,7 +7,9 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
+#include <malloc.h>
 #include <asm/gpio.h>
+#include <linux/ctype.h>
 
 /**
  * gpio_to_device() - Convert global GPIO number to device, number
@@ -43,35 +45,47 @@ static int gpio_to_device(unsigned int gpio, struct udevice **devp,
 int gpio_lookup_name(const char *name, struct udevice **devp,
 		     unsigned int *offsetp, unsigned int *gpiop)
 {
-	struct gpio_dev_priv *uc_priv;
+	struct gpio_dev_priv *uc_priv = NULL;
 	struct udevice *dev;
+	ulong offset;
+	int numeric;
 	int ret;
 
 	if (devp)
 		*devp = NULL;
+	numeric = isdigit(*name) ? simple_strtoul(name, NULL, 10) : -1;
 	for (ret = uclass_first_device(UCLASS_GPIO, &dev);
 	     dev;
 	     ret = uclass_next_device(&dev)) {
-		ulong offset;
 		int len;
 
 		uc_priv = dev->uclass_priv;
+		if (numeric != -1) {
+			offset = numeric - uc_priv->gpio_base;
+			/* Allow GPIOs to be numbered from 0 */
+			if (offset >= 0 && offset < uc_priv->gpio_count)
+				break;
+		}
+
 		len = uc_priv->bank_name ? strlen(uc_priv->bank_name) : 0;
 
 		if (!strncasecmp(name, uc_priv->bank_name, len)) {
-			if (strict_strtoul(name + len, 10, &offset))
-				continue;
-			if (devp)
-				*devp = dev;
-			if (offsetp)
-				*offsetp = offset;
-			if (gpiop)
-				*gpiop = uc_priv->gpio_base + offset;
-			return 0;
+			if (!strict_strtoul(name + len, 10, &offset))
+				break;
 		}
 	}
 
-	return ret ? ret : -EINVAL;
+	if (!dev)
+		return ret ? ret : -EINVAL;
+
+	if (devp)
+		*devp = dev;
+	if (offsetp)
+		*offsetp = offset;
+	if (gpiop)
+		*gpiop = uc_priv->gpio_base + offset;
+
+	return 0;
 }
 
 /**
@@ -79,24 +93,62 @@ int gpio_lookup_name(const char *name, struct udevice **devp,
  * gpio:	GPIO number
  * label:	Name for the requested GPIO
  *
+ * The label is copied and allocated so the caller does not need to keep
+ * the pointer around.
+ *
  * This function implements the API that's compatible with current
  * GPIO API used in U-Boot. The request is forwarded to particular
  * GPIO driver. Returns 0 on success, negative value on error.
  */
 int gpio_request(unsigned gpio, const char *label)
 {
+	struct gpio_dev_priv *uc_priv;
 	unsigned int offset;
 	struct udevice *dev;
+	char *str;
 	int ret;
 
 	ret = gpio_to_device(gpio, &dev, &offset);
 	if (ret)
 		return ret;
 
-	if (!gpio_get_ops(dev)->request)
-		return 0;
+	uc_priv = dev->uclass_priv;
+	if (uc_priv->name[offset])
+		return -EBUSY;
+	str = strdup(label);
+	if (!str)
+		return -ENOMEM;
+	if (gpio_get_ops(dev)->request) {
+		ret = gpio_get_ops(dev)->request(dev, offset, label);
+		if (ret) {
+			free(str);
+			return ret;
+		}
+	}
+	uc_priv->name[offset] = str;
+
+	return 0;
+}
+
+/**
+ * gpio_requestf() - [COMPAT] Request GPIO
+ * @gpio:	GPIO number
+ * @fmt:	Format string for the requested GPIO
+ * @...:	Arguments for the printf() format string
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_requestf(unsigned gpio, const char *fmt, ...)
+{
+	va_list args;
+	char buf[40];
 
-	return gpio_get_ops(dev)->request(dev, offset, label);
+	va_start(args, fmt);
+	vscnprintf(buf, sizeof(buf), fmt, args);
+	va_end(args);
+	return gpio_request(gpio, buf);
 }
 
 /**
@@ -109,6 +161,7 @@ int gpio_request(unsigned gpio, const char *label)
  */
 int gpio_free(unsigned gpio)
 {
+	struct gpio_dev_priv *uc_priv;
 	unsigned int offset;
 	struct udevice *dev;
 	int ret;
@@ -117,9 +170,34 @@ int gpio_free(unsigned gpio)
 	if (ret)
 		return ret;
 
-	if (!gpio_get_ops(dev)->free)
-		return 0;
-	return gpio_get_ops(dev)->free(dev, offset);
+	uc_priv = dev->uclass_priv;
+	if (!uc_priv->name[offset])
+		return -ENXIO;
+	if (gpio_get_ops(dev)->free) {
+		ret = gpio_get_ops(dev)->free(dev, offset);
+		if (ret)
+			return ret;
+	}
+
+	free(uc_priv->name[offset]);
+	uc_priv->name[offset] = NULL;
+
+	return 0;
+}
+
+static int check_reserved(struct udevice *dev, unsigned offset,
+			  const char *func)
+{
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+	if (!uc_priv->name[offset]) {
+		printf("%s: %s: error: gpio %s%d not reserved\n",
+		       dev->name, func,
+		       uc_priv->bank_name ? uc_priv->bank_name : "", offset);
+		return -EBUSY;
+	}
+
+	return 0;
 }
 
 /**
@@ -139,8 +217,9 @@ int gpio_direction_input(unsigned gpio)
 	ret = gpio_to_device(gpio, &dev, &offset);
 	if (ret)
 		return ret;
+	ret = check_reserved(dev, offset, "dir_input");
 
-	return gpio_get_ops(dev)->direction_input(dev, offset);
+	return ret ? ret : gpio_get_ops(dev)->direction_input(dev, offset);
 }
 
 /**
@@ -161,8 +240,10 @@ int gpio_direction_output(unsigned gpio, int value)
 	ret = gpio_to_device(gpio, &dev, &offset);
 	if (ret)
 		return ret;
+	ret = check_reserved(dev, offset, "dir_output");
 
-	return gpio_get_ops(dev)->direction_output(dev, offset, value);
+	return ret ? ret :
+		gpio_get_ops(dev)->direction_output(dev, offset, value);
 }
 
 /**
@@ -183,8 +264,9 @@ int gpio_get_value(unsigned gpio)
 	ret = gpio_to_device(gpio, &dev, &offset);
 	if (ret)
 		return ret;
+	ret = check_reserved(dev, offset, "get_value");
 
-	return gpio_get_ops(dev)->get_value(dev, offset);
+	return ret ? ret : gpio_get_ops(dev)->get_value(dev, offset);
 }
 
 /**
@@ -205,8 +287,9 @@ int gpio_set_value(unsigned gpio, int value)
 	ret = gpio_to_device(gpio, &dev, &offset);
 	if (ret)
 		return ret;
+	ret = check_reserved(dev, offset, "set_value");
 
-	return gpio_get_ops(dev)->set_value(dev, offset, value);
+	return ret ? ret : gpio_get_ops(dev)->set_value(dev, offset, value);
 }
 
 const char *gpio_get_bank_info(struct udevice *dev, int *bit_count)
@@ -221,8 +304,94 @@ const char *gpio_get_bank_info(struct udevice *dev, int *bit_count)
 	return priv->bank_name;
 }
 
+static const char * const gpio_function[GPIOF_COUNT] = {
+	"input",
+	"output",
+	"unused",
+	"unknown",
+	"func",
+};
+
+int get_function(struct udevice *dev, int offset, bool skip_unused,
+		 const char **namep)
+{
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+	struct dm_gpio_ops *ops = gpio_get_ops(dev);
+
+	BUILD_BUG_ON(GPIOF_COUNT != ARRAY_SIZE(gpio_function));
+	if (!device_active(dev))
+		return -ENODEV;
+	if (offset < 0 || offset >= uc_priv->gpio_count)
+		return -EINVAL;
+	if (namep)
+		*namep = uc_priv->name[offset];
+	if (skip_unused && !uc_priv->name[offset])
+		return GPIOF_UNUSED;
+	if (ops->get_function) {
+		int ret;
+
+		ret = ops->get_function(dev, offset);
+		if (ret < 0)
+			return ret;
+		if (ret >= ARRAY_SIZE(gpio_function))
+			return -ENODATA;
+		return ret;
+	}
+
+	return GPIOF_UNKNOWN;
+}
+
+int gpio_get_function(struct udevice *dev, int offset, const char **namep)
+{
+	return get_function(dev, offset, true, namep);
+}
+
+int gpio_get_raw_function(struct udevice *dev, int offset, const char **namep)
+{
+	return get_function(dev, offset, false, namep);
+}
+
+int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize)
+{
+	struct dm_gpio_ops *ops = gpio_get_ops(dev);
+	struct gpio_dev_priv *priv;
+	char *str = buf;
+	int func;
+	int ret;
+	int len;
+
+	BUILD_BUG_ON(GPIOF_COUNT != ARRAY_SIZE(gpio_function));
+
+	*buf = 0;
+	priv = dev->uclass_priv;
+	ret = gpio_get_raw_function(dev, offset, NULL);
+	if (ret < 0)
+		return ret;
+	func = ret;
+	len = snprintf(str, buffsize, "%s%d: %s",
+		       priv->bank_name ? priv->bank_name : "",
+		       offset, gpio_function[func]);
+	if (func == GPIOF_INPUT || func == GPIOF_OUTPUT ||
+	    func == GPIOF_UNUSED) {
+		const char *label;
+		bool used;
+
+		ret = ops->get_value(dev, offset);
+		if (ret < 0)
+			return ret;
+		used = gpio_get_function(dev, offset, &label) != GPIOF_UNUSED;
+		snprintf(str + len, buffsize - len, ": %d [%c]%s%s",
+			 ret,
+			 used ? 'x' : ' ',
+			 used ? " " : "",
+			 label ? label : "");
+	}
+
+	return 0;
+}
+
 /* We need to renumber the GPIOs when any driver is probed/removed */
-static int gpio_renumber(void)
+static int gpio_renumber(struct udevice *removed_dev)
 {
 	struct gpio_dev_priv *uc_priv;
 	struct udevice *dev;
@@ -237,7 +406,7 @@ static int gpio_renumber(void)
 	/* Ensure that we have a base for each bank */
 	base = 0;
 	uclass_foreach_dev(dev, uc) {
-		if (device_active(dev)) {
+		if (device_active(dev) && dev != removed_dev) {
 			uc_priv = dev->uclass_priv;
 			uc_priv->gpio_base = base;
 			base += uc_priv->gpio_count;
@@ -249,12 +418,27 @@ static int gpio_renumber(void)
 
 static int gpio_post_probe(struct udevice *dev)
 {
-	return gpio_renumber();
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+	uc_priv->name = calloc(uc_priv->gpio_count, sizeof(char *));
+	if (!uc_priv->name)
+		return -ENOMEM;
+
+	return gpio_renumber(NULL);
 }
 
 static int gpio_pre_remove(struct udevice *dev)
 {
-	return gpio_renumber();
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+	int i;
+
+	for (i = 0; i < uc_priv->gpio_count; i++) {
+		if (uc_priv->name[i])
+			free(uc_priv->name[i]);
+	}
+	free(uc_priv->name);
+
+	return gpio_renumber(dev);
 }
 
 UCLASS_DRIVER(gpio) = {
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7d9fac72337..d3381b0369c 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -27,88 +27,46 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
 #include <pci.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 
+#define GPIO_PER_BANK	32
+
 /* Where in config space is the register that points to the GPIO registers? */
 #define PCI_CFG_GPIOBASE 0x48
 
-#define NUM_BANKS 3
-
-/* Within the I/O space, where are the registers to control the GPIOs? */
-static struct {
-	u8 use_sel;
-	u8 io_sel;
-	u8 lvl;
-} gpio_bank[NUM_BANKS] = {
-	{ 0x00, 0x04, 0x0c },		/* Bank 0 */
-	{ 0x30, 0x34, 0x38 },		/* Bank 1 */
-	{ 0x40, 0x44, 0x48 }		/* Bank 2 */
+struct ich6_bank_priv {
+	/* These are I/O addresses */
+	uint32_t use_sel;
+	uint32_t io_sel;
+	uint32_t lvl;
 };
 
-static pci_dev_t dev;			/* handle for 0:1f:0 */
-static u32 gpiobase;			/* offset into I/O space */
-static int found_it_once;		/* valid GPIO device? */
-static u32 lock[NUM_BANKS];		/* "lock" for access to pins */
-
-static int bad_arg(int num, int *bank, int *bitnum)
-{
-	int i = num / 32;
-	int j = num % 32;
-
-	if (num < 0 || i > NUM_BANKS) {
-		debug("%s: bogus gpio num: %d\n", __func__, num);
-		return -1;
-	}
-	*bank = i;
-	*bitnum = j;
-	return 0;
-}
-
-static int mark_gpio(int bank, int bitnum)
-{
-	if (lock[bank] & (1UL << bitnum)) {
-		debug("%s: %d.%d already marked\n", __func__, bank, bitnum);
-		return -1;
-	}
-	lock[bank] |= (1 << bitnum);
-	return 0;
-}
-
-static void clear_gpio(int bank, int bitnum)
-{
-	lock[bank] &= ~(1 << bitnum);
-}
-
-static int notmine(int num, int *bank, int *bitnum)
-{
-	if (bad_arg(num, bank, bitnum))
-		return -1;
-	return !(lock[*bank] & (1UL << *bitnum));
-}
-
-static int gpio_init(void)
+static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
 {
+	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
+	pci_dev_t pci_dev;			/* handle for 0:1f:0 */
 	u8 tmpbyte;
 	u16 tmpword;
 	u32 tmplong;
-
-	/* Have we already done this? */
-	if (found_it_once)
-		return 0;
+	u32 gpiobase;
+	int offset;
 
 	/* Where should it be? */
-	dev = PCI_BDF(0, 0x1f, 0);
+	pci_dev = PCI_BDF(0, 0x1f, 0);
 
 	/* Is the device present? */
-	pci_read_config_word(dev, PCI_VENDOR_ID, &tmpword);
+	pci_read_config_word(pci_dev, PCI_VENDOR_ID, &tmpword);
 	if (tmpword != PCI_VENDOR_ID_INTEL) {
 		debug("%s: wrong VendorID\n", __func__);
-		return -1;
+		return -ENODEV;
 	}
 
-	pci_read_config_word(dev, PCI_DEVICE_ID, &tmpword);
+	pci_read_config_word(pci_dev, PCI_DEVICE_ID, &tmpword);
 	debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword);
 	/*
 	 * We'd like to validate the Device ID too, but pretty much any
@@ -118,37 +76,37 @@ static int gpio_init(void)
 	 */
 
 	/* I/O should already be enabled (it's a RO bit). */
-	pci_read_config_word(dev, PCI_COMMAND, &tmpword);
+	pci_read_config_word(pci_dev, PCI_COMMAND, &tmpword);
 	if (!(tmpword & PCI_COMMAND_IO)) {
 		debug("%s: device IO not enabled\n", __func__);
-		return -1;
+		return -ENODEV;
 	}
 
 	/* Header Type must be normal (bits 6-0 only; see spec.) */
-	pci_read_config_byte(dev, PCI_HEADER_TYPE, &tmpbyte);
+	pci_read_config_byte(pci_dev, PCI_HEADER_TYPE, &tmpbyte);
 	if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) {
 		debug("%s: invalid Header type\n", __func__);
-		return -1;
+		return -ENODEV;
 	}
 
 	/* Base Class must be a bridge device */
-	pci_read_config_byte(dev, PCI_CLASS_CODE, &tmpbyte);
+	pci_read_config_byte(pci_dev, PCI_CLASS_CODE, &tmpbyte);
 	if (tmpbyte != PCI_CLASS_CODE_BRIDGE) {
 		debug("%s: invalid class\n", __func__);
-		return -1;
+		return -ENODEV;
 	}
 	/* Sub Class must be ISA */
-	pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &tmpbyte);
+	pci_read_config_byte(pci_dev, PCI_CLASS_SUB_CODE, &tmpbyte);
 	if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) {
 		debug("%s: invalid subclass\n", __func__);
-		return -1;
+		return -ENODEV;
 	}
 
 	/* Programming Interface must be 0x00 (no others exist) */
-	pci_read_config_byte(dev, PCI_CLASS_PROG, &tmpbyte);
+	pci_read_config_byte(pci_dev, PCI_CLASS_PROG, &tmpbyte);
 	if (tmpbyte != 0x00) {
 		debug("%s: invalid interface type\n", __func__);
-		return -1;
+		return -ENODEV;
 	}
 
 	/*
@@ -156,11 +114,11 @@ static int gpio_init(void)
 	 * that it was unused (or undocumented). Check that it looks
 	 * okay: not all ones or zeros, and mapped to I/O space (bit 0).
 	 */
-	pci_read_config_dword(dev, PCI_CFG_GPIOBASE, &tmplong);
+	pci_read_config_dword(pci_dev, PCI_CFG_GPIOBASE, &tmplong);
 	if (tmplong == 0x00000000 || tmplong == 0xffffffff ||
 	    !(tmplong & 0x00000001)) {
 		debug("%s: unexpected GPIOBASE value\n", __func__);
-		return -1;
+		return -ENODEV;
 	}
 
 	/*
@@ -170,105 +128,137 @@ static int gpio_init(void)
 	 * an I/O address, not a memory address, so mask that off.
 	 */
 	gpiobase = tmplong & 0xfffffffe;
+	offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
+	if (offset == -1) {
+		debug("%s: Invalid register offset %d\n", __func__, offset);
+		return -EINVAL;
+	}
+	plat->base_addr = gpiobase + offset;
+	plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+				      "bank-name", NULL);
 
-	/* Finally. These are the droids we're looking for. */
-	found_it_once = 1;
 	return 0;
 }
 
-int gpio_request(unsigned num, const char *label /* UNUSED */)
+int ich6_gpio_probe(struct udevice *dev)
 {
-	u32 tmplong;
-	int i = 0, j = 0;
+	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+	struct ich6_bank_priv *bank = dev_get_priv(dev);
+
+	uc_priv->gpio_count = GPIO_PER_BANK;
+	uc_priv->bank_name = plat->bank_name;
+	bank->use_sel = plat->base_addr;
+	bank->io_sel = plat->base_addr + 4;
+	bank->lvl = plat->base_addr + 8;
 
-	/* Is the hardware ready? */
-	if (gpio_init())
-		return -1;
+	return 0;
+}
 
-	if (bad_arg(num, &i, &j))
-		return -1;
+int ich6_gpio_request(struct udevice *dev, unsigned offset, const char *label)
+{
+	struct ich6_bank_priv *bank = dev_get_priv(dev);
+	u32 tmplong;
 
 	/*
 	 * Make sure that the GPIO pin we want isn't already in use for some
 	 * built-in hardware function. We have to check this for every
 	 * requested pin.
 	 */
-	tmplong = inl(gpiobase + gpio_bank[i].use_sel);
-	if (!(tmplong & (1UL << j))) {
+	tmplong = inl(bank->use_sel);
+	if (!(tmplong & (1UL << offset))) {
 		debug("%s: gpio %d is reserved for internal use\n", __func__,
-		      num);
-		return -1;
+		      offset);
+		return -EPERM;
 	}
 
-	return mark_gpio(i, j);
-}
-
-int gpio_free(unsigned num)
-{
-	int i = 0, j = 0;
-
-	if (notmine(num, &i, &j))
-		return -1;
-
-	clear_gpio(i, j);
 	return 0;
 }
 
-int gpio_direction_input(unsigned num)
+static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset)
 {
+	struct ich6_bank_priv *bank = dev_get_priv(dev);
 	u32 tmplong;
-	int i = 0, j = 0;
-
-	if (notmine(num, &i, &j))
-		return -1;
 
-	tmplong = inl(gpiobase + gpio_bank[i].io_sel);
-	tmplong |= (1UL << j);
-	outl(gpiobase + gpio_bank[i].io_sel, tmplong);
+	tmplong = inl(bank->io_sel);
+	tmplong |= (1UL << offset);
+	outl(bank->io_sel, tmplong);
 	return 0;
 }
 
-int gpio_direction_output(unsigned num, int value)
+static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
+				       int value)
 {
+	struct ich6_bank_priv *bank = dev_get_priv(dev);
 	u32 tmplong;
-	int i = 0, j = 0;
 
-	if (notmine(num, &i, &j))
-		return -1;
-
-	tmplong = inl(gpiobase + gpio_bank[i].io_sel);
-	tmplong &= ~(1UL << j);
-	outl(gpiobase + gpio_bank[i].io_sel, tmplong);
+	tmplong = inl(bank->io_sel);
+	tmplong &= ~(1UL << offset);
+	outl(bank->io_sel, tmplong);
 	return 0;
 }
 
-int gpio_get_value(unsigned num)
+static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
+
 {
+	struct ich6_bank_priv *bank = dev_get_priv(dev);
 	u32 tmplong;
-	int i = 0, j = 0;
 	int r;
 
-	if (notmine(num, &i, &j))
-		return -1;
-
-	tmplong = inl(gpiobase + gpio_bank[i].lvl);
-	r = (tmplong & (1UL << j)) ? 1 : 0;
+	tmplong = inl(bank->lvl);
+	r = (tmplong & (1UL << offset)) ? 1 : 0;
 	return r;
 }
 
-int gpio_set_value(unsigned num, int value)
+static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
+			       int value)
 {
+	struct ich6_bank_priv *bank = dev_get_priv(dev);
 	u32 tmplong;
-	int i = 0, j = 0;
 
-	if (notmine(num, &i, &j))
-		return -1;
-
-	tmplong = inl(gpiobase + gpio_bank[i].lvl);
+	tmplong = inl(bank->lvl);
 	if (value)
-		tmplong |= (1UL << j);
+		tmplong |= (1UL << offset);
 	else
-		tmplong &= ~(1UL << j);
-	outl(gpiobase + gpio_bank[i].lvl, tmplong);
+		tmplong &= ~(1UL << offset);
+	outl(bank->lvl, tmplong);
 	return 0;
 }
+
+static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+	struct ich6_bank_priv *bank = dev_get_priv(dev);
+	u32 mask = 1UL << offset;
+
+	if (!(inl(bank->use_sel) & mask))
+		return GPIOF_FUNC;
+	if (inl(bank->io_sel) & mask)
+		return GPIOF_INPUT;
+	else
+		return GPIOF_OUTPUT;
+}
+
+static const struct dm_gpio_ops gpio_ich6_ops = {
+	.request		= ich6_gpio_request,
+	.direction_input	= ich6_gpio_direction_input,
+	.direction_output	= ich6_gpio_direction_output,
+	.get_value		= ich6_gpio_get_value,
+	.set_value		= ich6_gpio_set_value,
+	.get_function		= ich6_gpio_get_function,
+};
+
+static const struct udevice_id intel_ich6_gpio_ids[] = {
+	{ .compatible = "intel,ich6-gpio" },
+	{ }
+};
+
+U_BOOT_DRIVER(gpio_ich6) = {
+	.name	= "gpio_ich6",
+	.id	= UCLASS_GPIO,
+	.of_match = intel_ich6_gpio_ids,
+	.ops	= &gpio_ich6_ops,
+	.ofdata_to_platdata	= gpio_ich6_ofdata_to_platdata,
+	.probe	= ich6_gpio_probe,
+	.priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
+	.platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),
+};
diff --git a/drivers/gpio/kw_gpio.c b/drivers/gpio/kw_gpio.c
index 0af75a84ea7..43b27e3fea1 100644
--- a/drivers/gpio/kw_gpio.c
+++ b/drivers/gpio/kw_gpio.c
@@ -16,7 +16,7 @@
 #include <common.h>
 #include <asm/bitops.h>
 #include <asm/io.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <asm/arch/gpio.h>
 
 static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
@@ -36,7 +36,7 @@ void __set_direction(unsigned pin, int input)
 	u = readl(GPIO_IO_CONF(pin));
 }
 
-void __set_level(unsigned pin, int high)
+static void __set_level(unsigned pin, int high)
 {
 	u32 u;
 
@@ -48,7 +48,7 @@ void __set_level(unsigned pin, int high)
 	writel(u, GPIO_OUT(pin));
 }
 
-void __set_blinking(unsigned pin, int blink)
+static void __set_blinking(unsigned pin, int blink)
 {
 	u32 u;
 
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 6a572d5454b..8bb9e39b723 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -8,16 +8,29 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <malloc.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
-#include <errno.h>
 
 enum mxc_gpio_direction {
 	MXC_GPIO_DIRECTION_IN,
 	MXC_GPIO_DIRECTION_OUT,
 };
 
+#define GPIO_PER_BANK			32
+
+struct mxc_gpio_plat {
+	struct gpio_regs *regs;
+};
+
+struct mxc_bank_info {
+	struct gpio_regs *regs;
+};
+
+#ifndef CONFIG_DM_GPIO
 #define GPIO_TO_PORT(n)		(n / 32)
 
 /* GPIO port description */
@@ -134,3 +147,176 @@ int gpio_direction_output(unsigned gpio, int value)
 
 	return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
 }
+#endif
+
+#ifdef CONFIG_DM_GPIO
+static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
+{
+	u32 val;
+
+	val = readl(&regs->gpio_dir);
+
+	return val & (1 << offset) ? 1 : 0;
+}
+
+static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
+				    enum mxc_gpio_direction direction)
+{
+	u32 l;
+
+	l = readl(&regs->gpio_dir);
+
+	switch (direction) {
+	case MXC_GPIO_DIRECTION_OUT:
+		l |= 1 << offset;
+		break;
+	case MXC_GPIO_DIRECTION_IN:
+		l &= ~(1 << offset);
+	}
+	writel(l, &regs->gpio_dir);
+}
+
+static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
+				    int value)
+{
+	u32 l;
+
+	l = readl(&regs->gpio_dr);
+	if (value)
+		l |= 1 << offset;
+	else
+		l &= ~(1 << offset);
+	writel(l, &regs->gpio_dr);
+}
+
+static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
+{
+	return (readl(&regs->gpio_psr) >> offset) & 0x01;
+}
+
+/* set GPIO pin 'gpio' as an input */
+static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+	struct mxc_bank_info *bank = dev_get_priv(dev);
+
+	/* Configure GPIO direction as input. */
+	mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
+
+	return 0;
+}
+
+/* set GPIO pin 'gpio' as an output, with polarity 'value' */
+static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
+				       int value)
+{
+	struct mxc_bank_info *bank = dev_get_priv(dev);
+
+	/* Configure GPIO output value. */
+	mxc_gpio_bank_set_value(bank->regs, offset, value);
+
+	/* Configure GPIO direction as output. */
+	mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);
+
+	return 0;
+}
+
+/* read GPIO IN value of pin 'gpio' */
+static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+	struct mxc_bank_info *bank = dev_get_priv(dev);
+
+	return mxc_gpio_bank_get_value(bank->regs, offset);
+}
+
+/* write GPIO OUT value to pin 'gpio' */
+static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
+				 int value)
+{
+	struct mxc_bank_info *bank = dev_get_priv(dev);
+
+	mxc_gpio_bank_set_value(bank->regs, offset, value);
+
+	return 0;
+}
+
+static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+	struct mxc_bank_info *bank = dev_get_priv(dev);
+
+	/* GPIOF_FUNC is not implemented yet */
+	if (mxc_gpio_is_output(bank->regs, offset))
+		return GPIOF_OUTPUT;
+	else
+		return GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops gpio_mxc_ops = {
+	.direction_input	= mxc_gpio_direction_input,
+	.direction_output	= mxc_gpio_direction_output,
+	.get_value		= mxc_gpio_get_value,
+	.set_value		= mxc_gpio_set_value,
+	.get_function		= mxc_gpio_get_function,
+};
+
+static const struct mxc_gpio_plat mxc_plat[] = {
+	{ (struct gpio_regs *)GPIO1_BASE_ADDR },
+	{ (struct gpio_regs *)GPIO2_BASE_ADDR },
+	{ (struct gpio_regs *)GPIO3_BASE_ADDR },
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+		defined(CONFIG_MX53) || defined(CONFIG_MX6)
+	{ (struct gpio_regs *)GPIO4_BASE_ADDR },
+#endif
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+	{ (struct gpio_regs *)GPIO5_BASE_ADDR },
+	{ (struct gpio_regs *)GPIO6_BASE_ADDR },
+#endif
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+	{ (struct gpio_regs *)GPIO7_BASE_ADDR },
+#endif
+};
+
+static int mxc_gpio_probe(struct udevice *dev)
+{
+	struct mxc_bank_info *bank = dev_get_priv(dev);
+	struct mxc_gpio_plat *plat = dev_get_platdata(dev);
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+	int banknum;
+	char name[18], *str;
+
+	banknum = plat - mxc_plat;
+	sprintf(name, "GPIO%d_", banknum + 1);
+	str = strdup(name);
+	if (!str)
+		return -ENOMEM;
+	uc_priv->bank_name = str;
+	uc_priv->gpio_count = GPIO_PER_BANK;
+	bank->regs = plat->regs;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(gpio_mxc) = {
+	.name	= "gpio_mxc",
+	.id	= UCLASS_GPIO,
+	.ops	= &gpio_mxc_ops,
+	.probe	= mxc_gpio_probe,
+	.priv_auto_alloc_size = sizeof(struct mxc_bank_info),
+};
+
+U_BOOT_DEVICES(mxc_gpios) = {
+	{ "gpio_mxc", &mxc_plat[0] },
+	{ "gpio_mxc", &mxc_plat[1] },
+	{ "gpio_mxc", &mxc_plat[2] },
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+		defined(CONFIG_MX53) || defined(CONFIG_MX6)
+	{ "gpio_mxc", &mxc_plat[3] },
+#endif
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+	{ "gpio_mxc", &mxc_plat[4] },
+	{ "gpio_mxc", &mxc_plat[5] },
+#endif
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+	{ "gpio_mxc", &mxc_plat[6] },
+#endif
+};
+#endif
diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c
index 13dcf798730..f3a7ccb51e9 100644
--- a/drivers/gpio/omap_gpio.c
+++ b/drivers/gpio/omap_gpio.c
@@ -19,6 +19,7 @@
  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
  */
 #include <common.h>
+#include <dm.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/errno.h>
@@ -26,10 +27,17 @@
 #define OMAP_GPIO_DIR_OUT	0
 #define OMAP_GPIO_DIR_IN	1
 
-static inline const struct gpio_bank *get_gpio_bank(int gpio)
-{
-	return &omap_gpio_bank[gpio >> 5];
-}
+#ifdef CONFIG_DM_GPIO
+
+#define GPIO_PER_BANK			32
+
+struct gpio_bank {
+	/* TODO(sjg@chromium.org): Can we use a struct here? */
+	void *base;	/* address of registers in physical memory */
+	enum gpio_method method;
+};
+
+#endif
 
 static inline int get_gpio_index(int gpio)
 {
@@ -41,15 +49,6 @@ int gpio_is_valid(int gpio)
 	return (gpio >= 0) && (gpio < OMAP_MAX_GPIO);
 }
 
-static int check_gpio(int gpio)
-{
-	if (!gpio_is_valid(gpio)) {
-		printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
-		return -1;
-	}
-	return 0;
-}
-
 static void _set_gpio_direction(const struct gpio_bank *bank, int gpio,
 				int is_input)
 {
@@ -118,6 +117,48 @@ static void _set_gpio_dataout(const struct gpio_bank *bank, int gpio,
 	__raw_writel(l, reg);
 }
 
+static int _get_gpio_value(const struct gpio_bank *bank, int gpio)
+{
+	void *reg = bank->base;
+	int input;
+
+	switch (bank->method) {
+	case METHOD_GPIO_24XX:
+		input = _get_gpio_direction(bank, gpio);
+		switch (input) {
+		case OMAP_GPIO_DIR_IN:
+			reg += OMAP_GPIO_DATAIN;
+			break;
+		case OMAP_GPIO_DIR_OUT:
+			reg += OMAP_GPIO_DATAOUT;
+			break;
+		default:
+			return -1;
+		}
+		break;
+	default:
+		return -1;
+	}
+
+	return (__raw_readl(reg) & (1 << gpio)) != 0;
+}
+
+#ifndef CONFIG_DM_GPIO
+
+static inline const struct gpio_bank *get_gpio_bank(int gpio)
+{
+	return &omap_gpio_bank[gpio >> 5];
+}
+
+static int check_gpio(int gpio)
+{
+	if (!gpio_is_valid(gpio)) {
+		printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
+		return -1;
+	}
+	return 0;
+}
+
 /**
  * Set value of the specified gpio
  */
@@ -139,32 +180,12 @@ int gpio_set_value(unsigned gpio, int value)
 int gpio_get_value(unsigned gpio)
 {
 	const struct gpio_bank *bank;
-	void *reg;
-	int input;
 
 	if (check_gpio(gpio) < 0)
 		return -1;
 	bank = get_gpio_bank(gpio);
-	reg = bank->base;
-	switch (bank->method) {
-	case METHOD_GPIO_24XX:
-		input = _get_gpio_direction(bank, get_gpio_index(gpio));
-		switch (input) {
-		case OMAP_GPIO_DIR_IN:
-			reg += OMAP_GPIO_DATAIN;
-			break;
-		case OMAP_GPIO_DIR_OUT:
-			reg += OMAP_GPIO_DATAOUT;
-			break;
-		default:
-			return -1;
-		}
-		break;
-	default:
-		return -1;
-	}
-	return (__raw_readl(reg)
-			& (1 << get_gpio_index(gpio))) != 0;
+
+	return _get_gpio_value(bank, get_gpio_index(gpio));
 }
 
 /**
@@ -220,3 +241,95 @@ int gpio_free(unsigned gpio)
 {
 	return 0;
 }
+
+#else /* new driver model interface CONFIG_DM_GPIO */
+
+/* set GPIO pin 'gpio' as an input */
+static int omap_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+	struct gpio_bank *bank = dev_get_priv(dev);
+
+	/* Configure GPIO direction as input. */
+	_set_gpio_direction(bank, offset, 1);
+
+	return 0;
+}
+
+/* set GPIO pin 'gpio' as an output, with polarity 'value' */
+static int omap_gpio_direction_output(struct udevice *dev, unsigned offset,
+				       int value)
+{
+	struct gpio_bank *bank = dev_get_priv(dev);
+
+	_set_gpio_dataout(bank, offset, value);
+	_set_gpio_direction(bank, offset, 0);
+
+	return 0;
+}
+
+/* read GPIO IN value of pin 'gpio' */
+static int omap_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+	struct gpio_bank *bank = dev_get_priv(dev);
+
+	return _get_gpio_value(bank, offset);
+}
+
+/* write GPIO OUT value to pin 'gpio' */
+static int omap_gpio_set_value(struct udevice *dev, unsigned offset,
+				 int value)
+{
+	struct gpio_bank *bank = dev_get_priv(dev);
+
+	_set_gpio_dataout(bank, offset, value);
+
+	return 0;
+}
+
+static int omap_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+	struct gpio_bank *bank = dev_get_priv(dev);
+
+	/* GPIOF_FUNC is not implemented yet */
+	if (_get_gpio_direction(bank->base, offset) == OMAP_GPIO_DIR_OUT)
+		return GPIOF_OUTPUT;
+	else
+		return GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops gpio_omap_ops = {
+	.direction_input	= omap_gpio_direction_input,
+	.direction_output	= omap_gpio_direction_output,
+	.get_value		= omap_gpio_get_value,
+	.set_value		= omap_gpio_set_value,
+	.get_function		= omap_gpio_get_function,
+};
+
+static int omap_gpio_probe(struct udevice *dev)
+{
+	struct gpio_bank *bank = dev_get_priv(dev);
+	struct omap_gpio_platdata *plat = dev_get_platdata(dev);
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+	char name[18], *str;
+
+	sprintf(name, "GPIO%d_", plat->bank_index);
+	str = strdup(name);
+	if (!str)
+		return -ENOMEM;
+	uc_priv->bank_name = str;
+	uc_priv->gpio_count = GPIO_PER_BANK;
+	bank->base = (void *)plat->base;
+	bank->method = plat->method;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(gpio_omap) = {
+	.name	= "gpio_omap",
+	.id	= UCLASS_GPIO,
+	.ops	= &gpio_omap_ops,
+	.probe	= omap_gpio_probe,
+	.priv_auto_alloc_size = sizeof(struct gpio_bank),
+};
+
+#endif /* CONFIG_DM_GPIO */
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index db7b6737310..6c41a42c177 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -6,120 +6,69 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
-#include <asm/arch/gpio.h>
+#include <dm/device-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #define S5P_GPIO_GET_PIN(x)	(x % GPIO_PER_BANK)
 
-#define CON_MASK(x)		(0xf << ((x) << 2))
-#define CON_SFR(x, v)		((v) << ((x) << 2))
+#define CON_MASK(val)			(0xf << ((val) << 2))
+#define CON_SFR(gpio, cfg)		((cfg) << ((gpio) << 2))
+#define CON_SFR_UNSHIFT(val, gpio)	((val) >> ((gpio) << 2))
+
+#define DAT_MASK(gpio)			(0x1 << (gpio))
+#define DAT_SET(gpio)			(0x1 << (gpio))
 
-#define DAT_MASK(x)		(0x1 << (x))
-#define DAT_SET(x)		(0x1 << (x))
+#define PULL_MASK(gpio)		(0x3 << ((gpio) << 1))
+#define PULL_MODE(gpio, pull)		((pull) << ((gpio) << 1))
 
-#define PULL_MASK(x)		(0x3 << ((x) << 1))
-#define PULL_MODE(x, v)		((v) << ((x) << 1))
+#define DRV_MASK(gpio)			(0x3 << ((gpio) << 1))
+#define DRV_SET(gpio, mode)		((mode) << ((gpio) << 1))
+#define RATE_MASK(gpio)		(0x1 << (gpio + 16))
+#define RATE_SET(gpio)			(0x1 << (gpio + 16))
 
-#define DRV_MASK(x)		(0x3 << ((x) << 1))
-#define DRV_SET(x, m)		((m) << ((x) << 1))
-#define RATE_MASK(x)		(0x1 << (x + 16))
-#define RATE_SET(x)		(0x1 << (x + 16))
+/* Platform data for each bank */
+struct exynos_gpio_platdata {
+	struct s5p_gpio_bank *bank;
+	const char *bank_name;	/* Name of port, e.g. 'gpa0" */
+};
 
-#define name_to_gpio(n) s5p_name_to_gpio(n)
-static inline int s5p_name_to_gpio(const char *name)
+/* Information about each bank at run-time */
+struct exynos_bank_info {
+	struct s5p_gpio_bank *bank;
+};
+
+static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
 {
-	unsigned num, irregular_set_number, irregular_bank_base;
-	const struct gpio_name_num_table *tabp;
-	char this_bank, bank_name, irregular_bank_name;
-	char *endp;
-
-	/*
-	 * The gpio name starts with either 'g' or 'gp' followed by the bank
-	 * name character. Skip one or two characters depending on the prefix.
-	 */
-	if (name[0] == 'g' && name[1] == 'p')
-		name += 2;
-	else if (name[0] == 'g')
-		name++;
-	else
-		return -1; /* Name must start with 'g' */
-
-	bank_name = *name++;
-	if (!*name)
-		return -1; /* At least one digit is required/expected. */
-
-	/*
-	 * On both exynos5 and exynos5420 architectures there is a bank of
-	 * GPIOs which does not fall into the regular address pattern. Those
-	 * banks are c4 on Exynos5 and y7 on Exynos5420. The rest of the below
-	 * assignments help to handle these irregularities.
-	 */
-#if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5)
-	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420()) {
-			tabp = exynos5420_gpio_table;
-			irregular_bank_name = 'y';
-			irregular_set_number = '7';
-			irregular_bank_base = EXYNOS5420_GPIO_Y70;
-		} else {
-			tabp = exynos5_gpio_table;
-			irregular_bank_name = 'c';
-			irregular_set_number = '4';
-			irregular_bank_base = EXYNOS5_GPIO_C40;
-		}
-	} else {
-		if (proid_is_exynos4412())
-			tabp = exynos4x12_gpio_table;
-		else
-			tabp = exynos4_gpio_table;
-		irregular_bank_name = 0;
-		irregular_set_number = 0;
-		irregular_bank_base = 0;
-	}
-#else
-	if (cpu_is_s5pc110())
-		tabp = s5pc110_gpio_table;
-	else
-		tabp = s5pc100_gpio_table;
-	irregular_bank_name = 0;
-	irregular_set_number = 0;
-	irregular_bank_base = 0;
-#endif
+	const struct gpio_info *data;
+	unsigned int upto;
+	int i, count;
+
+	data = get_gpio_data();
+	count = get_bank_num();
+	upto = 0;
 
-	this_bank = tabp->bank;
-	do {
-		if (bank_name == this_bank) {
-			unsigned pin_index; /* pin number within the bank */
-			if ((bank_name == irregular_bank_name) &&
-			    (name[0] == irregular_set_number)) {
-				pin_index = name[1] - '0';
-				/* Irregular sets have 8 pins. */
-				if (pin_index >= GPIO_PER_BANK)
-					return -1;
-				num = irregular_bank_base + pin_index;
-			} else {
-				pin_index = simple_strtoul(name, &endp, 8);
-				pin_index -= tabp->bank_offset;
-				/*
-				 * Sanity check: bunk 'z' has no set number,
-				 * for all other banks there must be exactly
-				 * two octal digits, and the resulting number
-				 * should not exceed the number of pins in the
-				 * bank.
-				 */
-				if (((bank_name != 'z') && !name[1]) ||
-				    *endp ||
-				    (pin_index >= tabp->bank_size))
-					return -1;
-				num = tabp->base + pin_index;
-			}
-			return num;
+	for (i = 0; i < count; i++) {
+		debug("i=%d, upto=%d\n", i, upto);
+		if (gpio < data->max_gpio) {
+			struct s5p_gpio_bank *bank;
+			bank = (struct s5p_gpio_bank *)data->reg_addr;
+			bank += (gpio - upto) / GPIO_PER_BANK;
+			debug("gpio=%d, bank=%p\n", gpio, bank);
+			return bank;
 		}
-		this_bank = (++tabp)->bank;
-	} while (this_bank);
 
-	return -1;
+		upto = data->max_gpio;
+		data++;
+	}
+
+	return NULL;
 }
 
 static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
@@ -143,16 +92,23 @@ static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
 	writel(value, &bank->dat);
 }
 
-static void s5p_gpio_direction_output(struct s5p_gpio_bank *bank,
-				      int gpio, int en)
+#ifdef CONFIG_SPL_BUILD
+/* Common GPIO API - SPL does not support driver model yet */
+int gpio_set_value(unsigned gpio, int value)
 {
-	s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_OUTPUT);
-	s5p_gpio_set_value(bank, gpio, en);
-}
+	s5p_gpio_set_value(s5p_gpio_get_bank(gpio),
+			   s5p_gpio_get_pin(gpio), value);
 
-static void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio)
+	return 0;
+}
+#else
+static int s5p_gpio_get_cfg_pin(struct s5p_gpio_bank *bank, int gpio)
 {
-	s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_INPUT);
+	unsigned int value;
+
+	value = readl(&bank->con);
+	value &= CON_MASK(gpio);
+	return CON_SFR_UNSHIFT(value, gpio);
 }
 
 static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
@@ -162,6 +118,7 @@ static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
 	value = readl(&bank->dat);
 	return !!(value & DAT_MASK(gpio));
 }
+#endif /* CONFIG_SPL_BUILD */
 
 static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
 {
@@ -222,78 +179,63 @@ static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
 	writel(value, &bank->drv);
 }
 
-struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
-{
-	const struct gpio_info *data;
-	unsigned int upto;
-	int i, count;
-
-	data = get_gpio_data();
-	count = get_bank_num();
-	upto = 0;
-
-	for (i = 0; i < count; i++) {
-		debug("i=%d, upto=%d\n", i, upto);
-		if (gpio < data->max_gpio) {
-			struct s5p_gpio_bank *bank;
-			bank = (struct s5p_gpio_bank *)data->reg_addr;
-			bank += (gpio - upto) / GPIO_PER_BANK;
-			debug("gpio=%d, bank=%p\n", gpio, bank);
-			return bank;
-		}
-
-		upto = data->max_gpio;
-		data++;
-	}
-
-	return NULL;
-}
-
 int s5p_gpio_get_pin(unsigned gpio)
 {
 	return S5P_GPIO_GET_PIN(gpio);
 }
 
-/* Common GPIO API */
-
-int gpio_request(unsigned gpio, const char *label)
+/* Driver model interface */
+#ifndef CONFIG_SPL_BUILD
+/* set GPIO pin 'gpio' as an input */
+static int exynos_gpio_direction_input(struct udevice *dev, unsigned offset)
 {
-	return 0;
-}
+	struct exynos_bank_info *state = dev_get_priv(dev);
 
-int gpio_free(unsigned gpio)
-{
-	return 0;
-}
+	/* Configure GPIO direction as input. */
+	s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_INPUT);
 
-int gpio_direction_input(unsigned gpio)
-{
-	s5p_gpio_direction_input(s5p_gpio_get_bank(gpio),
-				s5p_gpio_get_pin(gpio));
 	return 0;
 }
 
-int gpio_direction_output(unsigned gpio, int value)
+/* set GPIO pin 'gpio' as an output, with polarity 'value' */
+static int exynos_gpio_direction_output(struct udevice *dev, unsigned offset,
+				       int value)
 {
-	s5p_gpio_direction_output(s5p_gpio_get_bank(gpio),
-				 s5p_gpio_get_pin(gpio), value);
+	struct exynos_bank_info *state = dev_get_priv(dev);
+
+	/* Configure GPIO output value. */
+	s5p_gpio_set_value(state->bank, offset, value);
+
+	/* Configure GPIO direction as output. */
+	s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_OUTPUT);
+
 	return 0;
 }
 
-int gpio_get_value(unsigned gpio)
+/* read GPIO IN value of pin 'gpio' */
+static int exynos_gpio_get_value(struct udevice *dev, unsigned offset)
 {
-	return (int) s5p_gpio_get_value(s5p_gpio_get_bank(gpio),
-				       s5p_gpio_get_pin(gpio));
+	struct exynos_bank_info *state = dev_get_priv(dev);
+
+	return s5p_gpio_get_value(state->bank, offset);
 }
 
-int gpio_set_value(unsigned gpio, int value)
+/* write GPIO OUT value to pin 'gpio' */
+static int exynos_gpio_set_value(struct udevice *dev, unsigned offset,
+				 int value)
 {
-	s5p_gpio_set_value(s5p_gpio_get_bank(gpio),
-			  s5p_gpio_get_pin(gpio), value);
+	struct exynos_bank_info *state = dev_get_priv(dev);
+
+	s5p_gpio_set_value(state->bank, offset, value);
 
 	return 0;
 }
+#endif /* nCONFIG_SPL_BUILD */
 
+/*
+ * There is no common GPIO API for pull, drv, pin, rate (yet). These
+ * functions are kept here to preserve function ordering for review.
+ */
 void gpio_set_pull(int gpio, int mode)
 {
 	s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
@@ -317,3 +259,112 @@ void gpio_set_rate(int gpio, int mode)
 	s5p_gpio_set_rate(s5p_gpio_get_bank(gpio),
 			  s5p_gpio_get_pin(gpio), mode);
 }
+
+#ifndef CONFIG_SPL_BUILD
+static int exynos_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+	struct exynos_bank_info *state = dev_get_priv(dev);
+	int cfg;
+
+	cfg = s5p_gpio_get_cfg_pin(state->bank, offset);
+	if (cfg == S5P_GPIO_OUTPUT)
+		return GPIOF_OUTPUT;
+	else if (cfg == S5P_GPIO_INPUT)
+		return GPIOF_INPUT;
+	else
+		return GPIOF_FUNC;
+}
+
+static const struct dm_gpio_ops gpio_exynos_ops = {
+	.direction_input	= exynos_gpio_direction_input,
+	.direction_output	= exynos_gpio_direction_output,
+	.get_value		= exynos_gpio_get_value,
+	.set_value		= exynos_gpio_set_value,
+	.get_function		= exynos_gpio_get_function,
+};
+
+static int gpio_exynos_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+	struct exynos_bank_info *priv = dev->priv;
+	struct exynos_gpio_platdata *plat = dev->platdata;
+
+	/* Only child devices have ports */
+	if (!plat)
+		return 0;
+
+	priv->bank = plat->bank;
+
+	uc_priv->gpio_count = GPIO_PER_BANK;
+	uc_priv->bank_name = plat->bank_name;
+
+	return 0;
+}
+
+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child
+ * device for each Exynos GPIO bank.
+ */
+static int gpio_exynos_bind(struct udevice *parent)
+{
+	struct exynos_gpio_platdata *plat = parent->platdata;
+	struct s5p_gpio_bank *bank, *base;
+	const void *blob = gd->fdt_blob;
+	int node;
+
+	/* If this is a child device, there is nothing to do here */
+	if (plat)
+		return 0;
+
+	base = (struct s5p_gpio_bank *)fdtdec_get_addr(gd->fdt_blob,
+						   parent->of_offset, "reg");
+	for (node = fdt_first_subnode(blob, parent->of_offset), bank = base;
+	     node > 0;
+	     node = fdt_next_subnode(blob, node), bank++) {
+		struct exynos_gpio_platdata *plat;
+		struct udevice *dev;
+		fdt_addr_t reg;
+		int ret;
+
+		if (!fdtdec_get_bool(blob, node, "gpio-controller"))
+			continue;
+		plat = calloc(1, sizeof(*plat));
+		if (!plat)
+			return -ENOMEM;
+		reg = fdtdec_get_addr(blob, node, "reg");
+		if (reg != FDT_ADDR_T_NONE)
+			bank = (struct s5p_gpio_bank *)((ulong)base + reg);
+		plat->bank = bank;
+		plat->bank_name = fdt_get_name(blob, node, NULL);
+		debug("dev at %p: %s\n", bank, plat->bank_name);
+
+		ret = device_bind(parent, parent->driver,
+					plat->bank_name, plat, -1, &dev);
+		if (ret)
+			return ret;
+		dev->of_offset = parent->of_offset;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id exynos_gpio_ids[] = {
+	{ .compatible = "samsung,s5pc100-pinctrl" },
+	{ .compatible = "samsung,s5pc110-pinctrl" },
+	{ .compatible = "samsung,exynos4210-pinctrl" },
+	{ .compatible = "samsung,exynos4x12-pinctrl" },
+	{ .compatible = "samsung,exynos5250-pinctrl" },
+	{ .compatible = "samsung,exynos5420-pinctrl" },
+	{ }
+};
+
+U_BOOT_DRIVER(gpio_exynos) = {
+	.name	= "gpio_exynos",
+	.id	= UCLASS_GPIO,
+	.of_match = exynos_gpio_ids,
+	.bind	= gpio_exynos_bind,
+	.probe = gpio_exynos_probe,
+	.priv_auto_alloc_size = sizeof(struct exynos_bank_info),
+	.ops	= &gpio_exynos_ops,
+};
+#endif
diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c
index 75ada5d3871..53c80d5be65 100644
--- a/drivers/gpio/sandbox.c
+++ b/drivers/gpio/sandbox.c
@@ -14,7 +14,6 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Flags for each GPIO */
 #define GPIOF_OUTPUT	(1 << 0)	/* Currently set as an output */
 #define GPIOF_HIGH	(1 << 1)	/* Currently set high */
-#define GPIOF_RESERVED	(1 << 2)	/* Is in use / requested */
 
 struct gpio_state {
 	const char *label;	/* label given by requester */
@@ -54,18 +53,6 @@ static int set_gpio_flag(struct udevice *dev, unsigned offset, int flag,
 	return 0;
 }
 
-static int check_reserved(struct udevice *dev, unsigned offset,
-			  const char *func)
-{
-	if (!get_gpio_flag(dev, offset, GPIOF_RESERVED)) {
-		printf("sandbox_gpio: %s: error: offset %u not reserved\n",
-		       func, offset);
-		return -1;
-	}
-
-	return 0;
-}
-
 /*
  * Back-channel sandbox-internal-only access to GPIO state
  */
@@ -101,9 +88,6 @@ static int sb_gpio_direction_input(struct udevice *dev, unsigned offset)
 {
 	debug("%s: offset:%u\n", __func__, offset);
 
-	if (check_reserved(dev, offset, __func__))
-		return -1;
-
 	return sandbox_gpio_set_direction(dev, offset, 0);
 }
 
@@ -113,9 +97,6 @@ static int sb_gpio_direction_output(struct udevice *dev, unsigned offset,
 {
 	debug("%s: offset:%u, value = %d\n", __func__, offset, value);
 
-	if (check_reserved(dev, offset, __func__))
-		return -1;
-
 	return sandbox_gpio_set_direction(dev, offset, 1) |
 		sandbox_gpio_set_value(dev, offset, value);
 }
@@ -125,9 +106,6 @@ static int sb_gpio_get_value(struct udevice *dev, unsigned offset)
 {
 	debug("%s: offset:%u\n", __func__, offset);
 
-	if (check_reserved(dev, offset, __func__))
-		return -1;
-
 	return sandbox_gpio_get_value(dev, offset);
 }
 
@@ -136,9 +114,6 @@ static int sb_gpio_set_value(struct udevice *dev, unsigned offset, int value)
 {
 	debug("%s: offset:%u, value = %d\n", __func__, offset, value);
 
-	if (check_reserved(dev, offset, __func__))
-		return -1;
-
 	if (!sandbox_gpio_get_direction(dev, offset)) {
 		printf("sandbox_gpio: error: set_value on input gpio %u\n",
 		       offset);
@@ -148,69 +123,19 @@ static int sb_gpio_set_value(struct udevice *dev, unsigned offset, int value)
 	return sandbox_gpio_set_value(dev, offset, value);
 }
 
-static int sb_gpio_request(struct udevice *dev, unsigned offset,
-			   const char *label)
+static int sb_gpio_get_function(struct udevice *dev, unsigned offset)
 {
-	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
-	struct gpio_state *state = dev_get_priv(dev);
-
-	debug("%s: offset:%u, label:%s\n", __func__, offset, label);
-
-	if (offset >= uc_priv->gpio_count) {
-		printf("sandbox_gpio: error: invalid gpio %u\n", offset);
-		return -1;
-	}
-
-	if (get_gpio_flag(dev, offset, GPIOF_RESERVED)) {
-		printf("sandbox_gpio: error: gpio %u already reserved\n",
-		       offset);
-		return -1;
-	}
-
-	state[offset].label = label;
-	return set_gpio_flag(dev, offset, GPIOF_RESERVED, 1);
-}
-
-static int sb_gpio_free(struct udevice *dev, unsigned offset)
-{
-	struct gpio_state *state = dev_get_priv(dev);
-
-	debug("%s: offset:%u\n", __func__, offset);
-
-	if (check_reserved(dev, offset, __func__))
-		return -1;
-
-	state[offset].label = NULL;
-	return set_gpio_flag(dev, offset, GPIOF_RESERVED, 0);
-}
-
-static int sb_gpio_get_state(struct udevice *dev, unsigned int offset,
-			     char *buf, int bufsize)
-{
-	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
-	struct gpio_state *state = dev_get_priv(dev);
-	const char *label;
-
-	label = state[offset].label;
-	snprintf(buf, bufsize, "%s%d: %s: %d [%c]%s%s",
-		 uc_priv->bank_name ? uc_priv->bank_name : "", offset,
-		 sandbox_gpio_get_direction(dev, offset) ? "out" : " in",
-		 sandbox_gpio_get_value(dev, offset),
-		 get_gpio_flag(dev, offset, GPIOF_RESERVED) ? 'x' : ' ',
-		 label ? " " : "",
-		 label ? label : "");
-
-	return 0;
+	if (get_gpio_flag(dev, offset, GPIOF_OUTPUT))
+		return GPIOF_OUTPUT;
+	return GPIOF_INPUT;
 }
 
 static const struct dm_gpio_ops gpio_sandbox_ops = {
-	.request		= sb_gpio_request,
-	.free			= sb_gpio_free,
 	.direction_input	= sb_gpio_direction_input,
 	.direction_output	= sb_gpio_direction_output,
 	.get_value		= sb_gpio_get_value,
 	.set_value		= sb_gpio_set_value,
-	.get_state		= sb_gpio_get_state,
+	.get_function		= sb_gpio_get_function,
 };
 
 static int sandbox_gpio_ofdata_to_platdata(struct udevice *dev)
@@ -239,6 +164,13 @@ static int gpio_sandbox_probe(struct udevice *dev)
 	return 0;
 }
 
+static int gpio_sandbox_remove(struct udevice *dev)
+{
+	free(dev->priv);
+
+	return 0;
+}
+
 static const struct udevice_id sandbox_gpio_ids[] = {
 	{ .compatible = "sandbox,gpio" },
 	{ }
@@ -250,5 +182,6 @@ U_BOOT_DRIVER(gpio_sandbox) = {
 	.of_match = sandbox_gpio_ids,
 	.ofdata_to_platdata = sandbox_gpio_ofdata_to_platdata,
 	.probe	= gpio_sandbox_probe,
+	.remove	= gpio_sandbox_remove,
 	.ops	= &gpio_sandbox_ops,
 };
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 0c50a8f3326..44135e5bb74 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -11,9 +11,25 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
+#include <dm/device-internal.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SUNXI_GPIOS_PER_BANK	SUNXI_GPIO_A_NR
+
+struct sunxi_gpio_platdata {
+	struct sunxi_gpio *regs;
+	const char *bank_name;	/* Name of bank, e.g. "B" */
+	int gpio_count;
+};
+
+#ifndef CONFIG_DM_GPIO
 static int sunxi_gpio_output(u32 pin, u32 val)
 {
 	u32 dat;
@@ -100,3 +116,157 @@ int sunxi_name_to_gpio(const char *name)
 		return -1;
 	return group * 32 + pin;
 }
+#endif
+
+#ifdef CONFIG_DM_GPIO
+static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+
+	sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT);
+
+	return 0;
+}
+
+static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset,
+				       int value)
+{
+	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+	u32 num = GPIO_NUM(offset);
+
+	sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
+	clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
+
+	return 0;
+}
+
+static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+	u32 num = GPIO_NUM(offset);
+	unsigned dat;
+
+	dat = readl(&plat->regs->dat);
+	dat >>= num;
+
+	return dat & 0x1;
+}
+
+static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset,
+				int value)
+{
+	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+	u32 num = GPIO_NUM(offset);
+
+	clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
+	return 0;
+}
+
+static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+	int func;
+
+	func = sunxi_gpio_get_cfgbank(plat->regs, offset);
+	if (func == SUNXI_GPIO_OUTPUT)
+		return GPIOF_OUTPUT;
+	else if (func == SUNXI_GPIO_INPUT)
+		return GPIOF_INPUT;
+	else
+		return GPIOF_FUNC;
+}
+
+static const struct dm_gpio_ops gpio_sunxi_ops = {
+	.direction_input	= sunxi_gpio_direction_input,
+	.direction_output	= sunxi_gpio_direction_output,
+	.get_value		= sunxi_gpio_get_value,
+	.set_value		= sunxi_gpio_set_value,
+	.get_function		= sunxi_gpio_get_function,
+};
+
+/**
+ * Returns the name of a GPIO bank
+ *
+ * GPIO banks are named A, B, C, ...
+ *
+ * @bank:	Bank number (0, 1..n-1)
+ * @return allocated string containing the name
+ */
+static char *gpio_bank_name(int bank)
+{
+	char *name;
+
+	name = malloc(2);
+	if (name) {
+		name[0] = 'A' + bank;
+		name[1] = '\0';
+	}
+
+	return name;
+}
+
+static int gpio_sunxi_probe(struct udevice *dev)
+{
+	struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+	/* Tell the uclass how many GPIOs we have */
+	if (plat) {
+		uc_priv->gpio_count = plat->gpio_count;
+		uc_priv->bank_name = plat->bank_name;
+	}
+
+	return 0;
+}
+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child
+ * device for each Sunxi bank.
+ */
+static int gpio_sunxi_bind(struct udevice *parent)
+{
+	struct sunxi_gpio_platdata *plat = parent->platdata;
+	struct sunxi_gpio_reg *ctlr;
+	int bank;
+	int ret;
+
+	/* If this is a child device, there is nothing to do here */
+	if (plat)
+		return 0;
+
+	ctlr = (struct sunxi_gpio_reg *)fdtdec_get_addr(gd->fdt_blob,
+						   parent->of_offset, "reg");
+	for (bank = 0; bank < SUNXI_GPIO_BANKS; bank++) {
+		struct sunxi_gpio_platdata *plat;
+		struct udevice *dev;
+
+		plat = calloc(1, sizeof(*plat));
+		if (!plat)
+			return -ENOMEM;
+		plat->regs = &ctlr->gpio_bank[bank];
+		plat->bank_name = gpio_bank_name(bank);
+		plat->gpio_count = SUNXI_GPIOS_PER_BANK;
+
+		ret = device_bind(parent, parent->driver,
+					plat->bank_name, plat, -1, &dev);
+		if (ret)
+			return ret;
+		dev->of_offset = parent->of_offset;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id sunxi_gpio_ids[] = {
+	{ .compatible = "allwinner,sun7i-a20-pinctrl" },
+	{ }
+};
+
+U_BOOT_DRIVER(gpio_sunxi) = {
+	.name	= "gpio_sunxi",
+	.id	= UCLASS_GPIO,
+	.ops	= &gpio_sunxi_ops,
+	.of_match = sunxi_gpio_ids,
+	.bind	= gpio_sunxi_bind,
+	.probe	= gpio_sunxi_probe,
+};
+#endif
diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c
index 1cc4abb8a93..88f7ef5bf04 100644
--- a/drivers/gpio/tegra_gpio.c
+++ b/drivers/gpio/tegra_gpio.c
@@ -39,7 +39,6 @@ struct tegra_gpio_platdata {
 
 /* Information about each port at run-time */
 struct tegra_port_info {
-	char label[TEGRA_GPIOS_PER_PORT][GPIO_NAME_SIZE];
 	struct gpio_ctlr_bank *bank;
 	int base_gpio;		/* Port number for this port (0, 1,.., n-1) */
 };
@@ -132,21 +131,6 @@ static void set_level(unsigned gpio, int high)
 	writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
 }
 
-static int check_reserved(struct udevice *dev, unsigned offset,
-			  const char *func)
-{
-	struct tegra_port_info *state = dev_get_priv(dev);
-	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
-
-	if (!*state->label[offset]) {
-		printf("tegra_gpio: %s: error: gpio %s%d not reserved\n",
-		       func, uc_priv->bank_name, offset);
-		return -EBUSY;
-	}
-
-	return 0;
-}
-
 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
 int tegra_spl_gpio_direction_output(int gpio, int value)
 {
@@ -171,56 +155,16 @@ static int tegra_gpio_request(struct udevice *dev, unsigned offset,
 {
 	struct tegra_port_info *state = dev_get_priv(dev);
 
-	if (*state->label[offset])
-		return -EBUSY;
-
-	strncpy(state->label[offset], label, GPIO_NAME_SIZE);
-	state->label[offset][GPIO_NAME_SIZE - 1] = '\0';
-
 	/* Configure as a GPIO */
 	set_config(state->base_gpio + offset, 1);
 
 	return 0;
 }
 
-static int tegra_gpio_free(struct udevice *dev, unsigned offset)
-{
-	struct tegra_port_info *state = dev_get_priv(dev);
-	int ret;
-
-	ret = check_reserved(dev, offset, __func__);
-	if (ret)
-		return ret;
-	state->label[offset][0] = '\0';
-
-	return 0;
-}
-
-/* read GPIO OUT value of pin 'gpio' */
-static int tegra_gpio_get_output_value(unsigned gpio)
-{
-	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
-	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
-	int val;
-
-	debug("gpio_get_output_value: pin = %d (port %d:bit %d)\n",
-		gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
-
-	val = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
-
-	return (val >> GPIO_BIT(gpio)) & 1;
-}
-
-
 /* set GPIO pin 'gpio' as an input */
 static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
 {
 	struct tegra_port_info *state = dev_get_priv(dev);
-	int ret;
-
-	ret = check_reserved(dev, offset, __func__);
-	if (ret)
-		return ret;
 
 	/* Configure GPIO direction as input. */
 	set_direction(state->base_gpio + offset, 0);
@@ -234,11 +178,6 @@ static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
 {
 	struct tegra_port_info *state = dev_get_priv(dev);
 	int gpio = state->base_gpio + offset;
-	int ret;
-
-	ret = check_reserved(dev, offset, __func__);
-	if (ret)
-		return ret;
 
 	/* Configure GPIO output value. */
 	set_level(gpio, value);
@@ -254,13 +193,8 @@ static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
 {
 	struct tegra_port_info *state = dev_get_priv(dev);
 	int gpio = state->base_gpio + offset;
-	int ret;
 	int val;
 
-	ret = check_reserved(dev, offset, __func__);
-	if (ret)
-		return ret;
-
 	debug("%s: pin = %d (port %d:bit %d)\n", __func__,
 	      gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
 
@@ -274,11 +208,6 @@ static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
 {
 	struct tegra_port_info *state = dev_get_priv(dev);
 	int gpio = state->base_gpio + offset;
-	int ret;
-
-	ret = check_reserved(dev, offset, __func__);
-	if (ret)
-		return ret;
 
 	debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
 	      gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
@@ -314,8 +243,6 @@ static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
 	struct tegra_port_info *state = dev_get_priv(dev);
 	int gpio = state->base_gpio + offset;
 
-	if (!*state->label[offset])
-		return GPIOF_UNUSED;
 	if (!get_config(gpio))
 		return GPIOF_FUNC;
 	else if (get_direction(gpio))
@@ -324,50 +251,13 @@ static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
 		return GPIOF_INPUT;
 }
 
-static int tegra_gpio_get_state(struct udevice *dev, unsigned int offset,
-				char *buf, int bufsize)
-{
-	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
-	struct tegra_port_info *state = dev_get_priv(dev);
-	int gpio = state->base_gpio + offset;
-	const char *label;
-	int is_output;
-	int is_gpio;
-	int size;
-
-	label = state->label[offset];
-	is_gpio = get_config(gpio); /* GPIO, not SFPIO */
-	size = snprintf(buf, bufsize, "%s%d: ",
-			uc_priv->bank_name ? uc_priv->bank_name : "", offset);
-	buf += size;
-	bufsize -= size;
-	if (is_gpio) {
-		is_output = get_direction(gpio);
-
-		snprintf(buf, bufsize, "%s: %d [%c]%s%s",
-			 is_output ? "out" : " in",
-			 is_output ?
-				tegra_gpio_get_output_value(gpio) :
-				tegra_gpio_get_value(dev, offset),
-			 *label ? 'x' : ' ',
-			 *label ? " " : "",
-			 label);
-	} else {
-		snprintf(buf, bufsize, "sfpio");
-	}
-
-	return 0;
-}
-
 static const struct dm_gpio_ops gpio_tegra_ops = {
 	.request		= tegra_gpio_request,
-	.free			= tegra_gpio_free,
 	.direction_input	= tegra_gpio_direction_input,
 	.direction_output	= tegra_gpio_direction_output,
 	.get_value		= tegra_gpio_get_value,
 	.set_value		= tegra_gpio_set_value,
 	.get_function		= tegra_gpio_get_function,
-	.get_state		= tegra_gpio_get_state,
 };
 
 /**
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 416ea4f2c83..d067897244b 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -6,21 +6,21 @@
 #
 
 obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
-obj-$(CONFIG_DW_I2C) += designware_i2c.o
 obj-$(CONFIG_I2C_MV) += mv_i2c.o
-obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
 obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
 obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
 obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
 obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
 obj-$(CONFIG_SYS_I2C) += i2c_core.o
 obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
+obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
 obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
 obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
 obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
 obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
 obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
 obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
+obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
 obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
 obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
 obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index c891ebd39e2..e768cdedb0d 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -6,16 +6,33 @@
  */
 
 #include <common.h>
+#include <i2c.h>
 #include <asm/io.h>
 #include "designware_i2c.h"
 
-#ifdef CONFIG_I2C_MULTI_BUS
-static unsigned int bus_initialized[CONFIG_SYS_I2C_BUS_MAX];
-static unsigned int current_bus = 0;
+static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
+{
+	switch (adap->hwadapnr) {
+#if CONFIG_SYS_I2C_BUS_MAX >= 4
+	case 3:
+		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
+#endif
+#if CONFIG_SYS_I2C_BUS_MAX >= 3
+	case 2:
+		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
 #endif
+#if CONFIG_SYS_I2C_BUS_MAX >= 2
+	case 1:
+		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
+#endif
+	case 0:
+		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
+	default:
+		printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
+	}
 
-static struct i2c_regs *i2c_regs_p =
-    (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
+	return NULL;
+}
 
 /*
  * set_speed - Set the i2c speed mode (standard, high, fast)
@@ -23,51 +40,52 @@ static struct i2c_regs *i2c_regs_p =
  *
  * Set the i2c speed mode (standard, high, fast)
  */
-static void set_speed(int i2c_spd)
+static void set_speed(struct i2c_adapter *adap, int i2c_spd)
 {
+	struct i2c_regs *i2c_base = i2c_get_base(adap);
 	unsigned int cntl;
 	unsigned int hcnt, lcnt;
 	unsigned int enbl;
 
 	/* to set speed cltr must be disabled */
-	enbl = readl(&i2c_regs_p->ic_enable);
+	enbl = readl(&i2c_base->ic_enable);
 	enbl &= ~IC_ENABLE_0B;
-	writel(enbl, &i2c_regs_p->ic_enable);
+	writel(enbl, &i2c_base->ic_enable);
 
-	cntl = (readl(&i2c_regs_p->ic_con) & (~IC_CON_SPD_MSK));
+	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
 
 	switch (i2c_spd) {
 	case IC_SPEED_MODE_MAX:
 		cntl |= IC_CON_SPD_HS;
 		hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
-		writel(hcnt, &i2c_regs_p->ic_hs_scl_hcnt);
+		writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
 		lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
-		writel(lcnt, &i2c_regs_p->ic_hs_scl_lcnt);
+		writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
 		break;
 
 	case IC_SPEED_MODE_STANDARD:
 		cntl |= IC_CON_SPD_SS;
 		hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
-		writel(hcnt, &i2c_regs_p->ic_ss_scl_hcnt);
+		writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
 		lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
-		writel(lcnt, &i2c_regs_p->ic_ss_scl_lcnt);
+		writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
 		break;
 
 	case IC_SPEED_MODE_FAST:
 	default:
 		cntl |= IC_CON_SPD_FS;
 		hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
-		writel(hcnt, &i2c_regs_p->ic_fs_scl_hcnt);
+		writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
 		lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
-		writel(lcnt, &i2c_regs_p->ic_fs_scl_lcnt);
+		writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
 		break;
 	}
 
-	writel(cntl, &i2c_regs_p->ic_con);
+	writel(cntl, &i2c_base->ic_con);
 
 	/* Enable back i2c now speed set */
 	enbl |= IC_ENABLE_0B;
-	writel(enbl, &i2c_regs_p->ic_enable);
+	writel(enbl, &i2c_base->ic_enable);
 }
 
 /*
@@ -76,35 +94,20 @@ static void set_speed(int i2c_spd)
  *
  * Set the i2c speed.
  */
-int i2c_set_bus_speed(int speed)
+static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
+					 unsigned int speed)
 {
+	int i2c_spd;
+
 	if (speed >= I2C_MAX_SPEED)
-		set_speed(IC_SPEED_MODE_MAX);
+		i2c_spd = IC_SPEED_MODE_MAX;
 	else if (speed >= I2C_FAST_SPEED)
-		set_speed(IC_SPEED_MODE_FAST);
+		i2c_spd = IC_SPEED_MODE_FAST;
 	else
-		set_speed(IC_SPEED_MODE_STANDARD);
+		i2c_spd = IC_SPEED_MODE_STANDARD;
 
-	return 0;
-}
-
-/*
- * i2c_get_bus_speed - Gets the i2c speed
- *
- * Gets the i2c speed.
- */
-int i2c_get_bus_speed(void)
-{
-	u32 cntl;
-
-	cntl = (readl(&i2c_regs_p->ic_con) & IC_CON_SPD_MSK);
-
-	if (cntl == IC_CON_SPD_HS)
-		return I2C_MAX_SPEED;
-	else if (cntl == IC_CON_SPD_FS)
-		return I2C_FAST_SPEED;
-	else if (cntl == IC_CON_SPD_SS)
-		return I2C_STANDARD_SPEED;
+	set_speed(adap, i2c_spd);
+	adap->speed = speed;
 
 	return 0;
 }
@@ -112,34 +115,32 @@ int i2c_get_bus_speed(void)
 /*
  * i2c_init - Init function
  * @speed:	required i2c speed
- * @slaveadd:	slave address for the device
+ * @slaveaddr:	slave address for the device
  *
  * Initialization function.
  */
-void i2c_init(int speed, int slaveadd)
+static void dw_i2c_init(struct i2c_adapter *adap, int speed,
+			int slaveaddr)
 {
+	struct i2c_regs *i2c_base = i2c_get_base(adap);
 	unsigned int enbl;
 
 	/* Disable i2c */
-	enbl = readl(&i2c_regs_p->ic_enable);
+	enbl = readl(&i2c_base->ic_enable);
 	enbl &= ~IC_ENABLE_0B;
-	writel(enbl, &i2c_regs_p->ic_enable);
+	writel(enbl, &i2c_base->ic_enable);
 
-	writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_regs_p->ic_con);
-	writel(IC_RX_TL, &i2c_regs_p->ic_rx_tl);
-	writel(IC_TX_TL, &i2c_regs_p->ic_tx_tl);
-	i2c_set_bus_speed(speed);
-	writel(IC_STOP_DET, &i2c_regs_p->ic_intr_mask);
-	writel(slaveadd, &i2c_regs_p->ic_sar);
+	writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
+	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
+	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
+	dw_i2c_set_bus_speed(adap, speed);
+	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
+	writel(slaveaddr, &i2c_base->ic_sar);
 
 	/* Enable i2c */
-	enbl = readl(&i2c_regs_p->ic_enable);
+	enbl = readl(&i2c_base->ic_enable);
 	enbl |= IC_ENABLE_0B;
-	writel(enbl, &i2c_regs_p->ic_enable);
-
-#ifdef CONFIG_I2C_MULTI_BUS
-	bus_initialized[current_bus] = 1;
-#endif
+	writel(enbl, &i2c_base->ic_enable);
 }
 
 /*
@@ -148,21 +149,22 @@ void i2c_init(int speed, int slaveadd)
  *
  * Sets the target slave address.
  */
-static void i2c_setaddress(unsigned int i2c_addr)
+static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
 {
+	struct i2c_regs *i2c_base = i2c_get_base(adap);
 	unsigned int enbl;
 
 	/* Disable i2c */
-	enbl = readl(&i2c_regs_p->ic_enable);
+	enbl = readl(&i2c_base->ic_enable);
 	enbl &= ~IC_ENABLE_0B;
-	writel(enbl, &i2c_regs_p->ic_enable);
+	writel(enbl, &i2c_base->ic_enable);
 
-	writel(i2c_addr, &i2c_regs_p->ic_tar);
+	writel(i2c_addr, &i2c_base->ic_tar);
 
 	/* Enable i2c */
-	enbl = readl(&i2c_regs_p->ic_enable);
+	enbl = readl(&i2c_base->ic_enable);
 	enbl |= IC_ENABLE_0B;
-	writel(enbl, &i2c_regs_p->ic_enable);
+	writel(enbl, &i2c_base->ic_enable);
 }
 
 /*
@@ -170,10 +172,12 @@ static void i2c_setaddress(unsigned int i2c_addr)
  *
  * Flushes the i2c RX FIFO
  */
-static void i2c_flush_rxfifo(void)
+static void i2c_flush_rxfifo(struct i2c_adapter *adap)
 {
-	while (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE)
-		readl(&i2c_regs_p->ic_cmd_data);
+	struct i2c_regs *i2c_base = i2c_get_base(adap);
+
+	while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
+		readl(&i2c_base->ic_cmd_data);
 }
 
 /*
@@ -181,12 +185,13 @@ static void i2c_flush_rxfifo(void)
  *
  * Waits for bus busy
  */
-static int i2c_wait_for_bb(void)
+static int i2c_wait_for_bb(struct i2c_adapter *adap)
 {
+	struct i2c_regs *i2c_base = i2c_get_base(adap);
 	unsigned long start_time_bb = get_timer(0);
 
-	while ((readl(&i2c_regs_p->ic_status) & IC_STATUS_MA) ||
-	       !(readl(&i2c_regs_p->ic_status) & IC_STATUS_TFE)) {
+	while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
+	       !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 
 		/* Evaluate timeout */
 		if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
@@ -196,40 +201,44 @@ static int i2c_wait_for_bb(void)
 	return 0;
 }
 
-static int i2c_xfer_init(uchar chip, uint addr, int alen)
+static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
+			 int alen)
 {
-	if (i2c_wait_for_bb())
+	struct i2c_regs *i2c_base = i2c_get_base(adap);
+
+	if (i2c_wait_for_bb(adap))
 		return 1;
 
-	i2c_setaddress(chip);
+	i2c_setaddress(adap, chip);
 	while (alen) {
 		alen--;
 		/* high byte address going out first */
 		writel((addr >> (alen * 8)) & 0xff,
-		       &i2c_regs_p->ic_cmd_data);
+		       &i2c_base->ic_cmd_data);
 	}
 	return 0;
 }
 
-static int i2c_xfer_finish(void)
+static int i2c_xfer_finish(struct i2c_adapter *adap)
 {
+	struct i2c_regs *i2c_base = i2c_get_base(adap);
 	ulong start_stop_det = get_timer(0);
 
 	while (1) {
-		if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET)) {
-			readl(&i2c_regs_p->ic_clr_stop_det);
+		if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
+			readl(&i2c_base->ic_clr_stop_det);
 			break;
 		} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 			break;
 		}
 	}
 
-	if (i2c_wait_for_bb()) {
+	if (i2c_wait_for_bb(adap)) {
 		printf("Timed out waiting for bus\n");
 		return 1;
 	}
 
-	i2c_flush_rxfifo();
+	i2c_flush_rxfifo(adap);
 
 	return 0;
 }
@@ -244,8 +253,10 @@ static int i2c_xfer_finish(void)
  *
  * Read from i2c memory.
  */
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
+		       int alen, u8 *buffer, int len)
 {
+	struct i2c_regs *i2c_base = i2c_get_base(adap);
 	unsigned long start_time_rx;
 
 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
@@ -260,25 +271,25 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 	 * still be one byte because the extra address bits are
 	 * hidden in the chip address.
 	 */
-	chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+	dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 
-	debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip,
+	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 	      addr);
 #endif
 
-	if (i2c_xfer_init(chip, addr, alen))
+	if (i2c_xfer_init(adap, dev, addr, alen))
 		return 1;
 
 	start_time_rx = get_timer(0);
 	while (len) {
 		if (len == 1)
-			writel(IC_CMD | IC_STOP, &i2c_regs_p->ic_cmd_data);
+			writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 		else
-			writel(IC_CMD, &i2c_regs_p->ic_cmd_data);
+			writel(IC_CMD, &i2c_base->ic_cmd_data);
 
-		if (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) {
-			*buffer++ = (uchar)readl(&i2c_regs_p->ic_cmd_data);
+		if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
+			*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 			len--;
 			start_time_rx = get_timer(0);
 
@@ -287,7 +298,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 		}
 	}
 
-	return i2c_xfer_finish();
+	return i2c_xfer_finish(adap);
 }
 
 /*
@@ -300,8 +311,10 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
  *
  * Write to i2c memory.
  */
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
+			int alen, u8 *buffer, int len)
 {
+	struct i2c_regs *i2c_base = i2c_get_base(adap);
 	int nb = len;
 	unsigned long start_time_tx;
 
@@ -317,23 +330,25 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 	 * still be one byte because the extra address bits are
 	 * hidden in the chip address.
 	 */
-	chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+	dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 
-	debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip,
+	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 	      addr);
 #endif
 
-	if (i2c_xfer_init(chip, addr, alen))
+	if (i2c_xfer_init(adap, dev, addr, alen))
 		return 1;
 
 	start_time_tx = get_timer(0);
 	while (len) {
-		if (readl(&i2c_regs_p->ic_status) & IC_STATUS_TFNF) {
-			if (--len == 0)
-				writel(*buffer | IC_STOP, &i2c_regs_p->ic_cmd_data);
-			else
-				writel(*buffer, &i2c_regs_p->ic_cmd_data);
+		if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
+			if (--len == 0) {
+				writel(*buffer | IC_STOP,
+				       &i2c_base->ic_cmd_data);
+			} else {
+				writel(*buffer, &i2c_base->ic_cmd_data);
+			}
 			buffer++;
 			start_time_tx = get_timer(0);
 
@@ -343,13 +358,13 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 		}
 	}
 
-	return i2c_xfer_finish();
+	return i2c_xfer_finish(adap);
 }
 
 /*
  * i2c_probe - Probe the i2c chip
  */
-int i2c_probe(uchar chip)
+static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 {
 	u32 tmp;
 	int ret;
@@ -357,80 +372,31 @@ int i2c_probe(uchar chip)
 	/*
 	 * Try to read the first location of the chip.
 	 */
-	ret = i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
+	ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1);
 	if (ret)
-		i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+		dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 
 	return ret;
 }
 
-#ifdef CONFIG_I2C_MULTI_BUS
-int i2c_set_bus_num(unsigned int bus)
-{
-	switch (bus) {
-	case 0:
-		i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE;
-		break;
-#ifdef CONFIG_SYS_I2C_BASE1
-	case 1:
-		i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE1;
-		break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE2
-	case 2:
-		i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE2;
-		break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE3
-	case 3:
-		i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE3;
-		break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE4
-	case 4:
-		i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE4;
-		break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE5
-	case 5:
-		i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE5;
-		break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE6
-	case 6:
-		i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE6;
-		break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE7
-	case 7:
-		i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE7;
-		break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE8
-	case 8:
-		i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE8;
-		break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE9
-	case 9:
-		i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE9;
-		break;
-#endif
-	default:
-		printf("Bad bus: %d\n", bus);
-		return -1;
-	}
+U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
+			 dw_i2c_write, dw_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 
-	current_bus = bus;
-
-	if (!bus_initialized[current_bus])
-		i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#if CONFIG_SYS_I2C_BUS_MAX >= 2
+U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
+			 dw_i2c_write, dw_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
+#endif
 
-	return 0;
-}
+#if CONFIG_SYS_I2C_BUS_MAX >= 3
+U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
+			 dw_i2c_write, dw_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
+#endif
 
-int i2c_get_bus_num(void)
-{
-	return current_bus;
-}
+#if CONFIG_SYS_I2C_BUS_MAX >= 4
+U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
+			 dw_i2c_write, dw_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 #endif
diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 18d6736601c..d34b749a565 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -229,11 +229,9 @@ static void i2c_init_bus(unsigned int bus_no, int speed, int slaveaddr)
 }
 
 /* implement possible board specific board init */
-static void __def_i2c_init_board(void)
+__weak void i2c_init_board(void)
 {
 }
-void i2c_init_board(void)
-	__attribute__((weak, alias("__def_i2c_init_board")));
 
 /*
  * i2c_init_all():
@@ -395,9 +393,7 @@ void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val)
 	i2c_write(addr, reg, 1, &val, 1);
 }
 
-void __i2c_init(int speed, int slaveaddr)
+__weak void i2c_init(int speed, int slaveaddr)
 {
 	i2c_init_bus(i2c_get_bus_num(), speed, slaveaddr);
 }
-void i2c_init(int speed, int slaveaddr)
-	__attribute__((weak, alias("__i2c_init")));
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index ab3ffa0fc15..9b2ca1e81ba 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -20,8 +20,8 @@
 
 #if defined(CONFIG_ORION5X)
 #include <asm/arch/orion5x.h>
-#elif defined(CONFIG_KIRKWOOD)
-#include <asm/arch/kirkwood.h>
+#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARMADA_XP))
+#include <asm/arch/soc.h>
 #elif defined(CONFIG_SUNXI)
 #include <asm/arch/i2c.h>
 #else
diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c
index de3b19402b4..87e05c71254 100644
--- a/drivers/i2c/mxs_i2c.c
+++ b/drivers/i2c/mxs_i2c.c
@@ -24,11 +24,74 @@
 
 #define	MXS_I2C_MAX_TIMEOUT	1000000
 
-static void mxs_i2c_reset(void)
+static struct mxs_i2c_regs *mxs_i2c_get_base(struct i2c_adapter *adap)
 {
-	struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+	if (adap->hwadapnr == 0)
+		return (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+	else
+		return (struct mxs_i2c_regs *)MXS_I2C1_BASE;
+}
+
+static unsigned int mxs_i2c_get_bus_speed(struct i2c_adapter *adap)
+{
+	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
+	uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
+	uint32_t timing0;
+
+	timing0 = readl(&i2c_regs->hw_i2c_timing0);
+	/*
+	 * This is a reverse version of the algorithm presented in
+	 * i2c_set_bus_speed(). Please refer there for details.
+	 */
+	return clk / ((((timing0 >> 16) - 3) * 2) + 38);
+}
+
+static uint mxs_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
+{
+	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
+	/*
+	 * The timing derivation algorithm. There is no documentation for this
+	 * algorithm available, it was derived by using the scope and fiddling
+	 * with constants until the result observed on the scope was good enough
+	 * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
+	 * possible to assume the algorithm works for other frequencies as well.
+	 *
+	 * Note it was necessary to cap the frequency on both ends as it's not
+	 * possible to configure completely arbitrary frequency for the I2C bus
+	 * clock.
+	 */
+	uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
+	uint32_t base = ((clk / speed) - 38) / 2;
+	uint16_t high_count = base + 3;
+	uint16_t low_count = base - 3;
+	uint16_t rcv_count = (high_count * 3) / 4;
+	uint16_t xmit_count = low_count / 4;
+
+	if (speed > 540000) {
+		printf("MXS I2C: Speed too high (%d Hz)\n", speed);
+		return -EINVAL;
+	}
+
+	if (speed < 12000) {
+		printf("MXS I2C: Speed too low (%d Hz)\n", speed);
+		return -EINVAL;
+	}
+
+	writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0);
+	writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1);
+
+	writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
+		(0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
+		&i2c_regs->hw_i2c_timing2);
+
+	return 0;
+}
+
+static void mxs_i2c_reset(struct i2c_adapter *adap)
+{
+	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 	int ret;
-	int speed = i2c_get_bus_speed();
+	int speed = mxs_i2c_get_bus_speed(adap);
 
 	ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
 	if (ret) {
@@ -43,12 +106,12 @@ static void mxs_i2c_reset(void)
 
 	writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);
 
-	i2c_set_bus_speed(speed);
+	mxs_i2c_set_bus_speed(adap, speed);
 }
 
-static void mxs_i2c_setup_read(uint8_t chip, int len)
+static void mxs_i2c_setup_read(struct i2c_adapter *adap, uint8_t chip, int len)
 {
-	struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 
 	writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
 		I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
@@ -64,10 +127,10 @@ static void mxs_i2c_setup_read(uint8_t chip, int len)
 	writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
 }
 
-static int mxs_i2c_write(uchar chip, uint addr, int alen,
-			uchar *buf, int blen, int stop)
+static int mxs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+			 int alen, uchar *buf, int blen, int stop)
 {
-	struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 	uint32_t data, tmp;
 	int i, remain, off;
 	int timeout = MXS_I2C_MAX_TIMEOUT;
@@ -122,9 +185,9 @@ static int mxs_i2c_write(uchar chip, uint addr, int alen,
 	return 0;
 }
 
-static int mxs_i2c_wait_for_ack(void)
+static int mxs_i2c_wait_for_ack(struct i2c_adapter *adap)
 {
-	struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 	uint32_t tmp;
 	int timeout = MXS_I2C_MAX_TIMEOUT;
 
@@ -156,32 +219,34 @@ static int mxs_i2c_wait_for_ack(void)
 	return 0;
 
 err:
-	mxs_i2c_reset();
+	mxs_i2c_reset(adap);
 	return 1;
 }
 
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int mxs_i2c_if_read(struct i2c_adapter *adap, uint8_t chip,
+			   uint addr, int alen, uint8_t *buffer,
+			   int len)
 {
-	struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 	uint32_t tmp = 0;
 	int timeout = MXS_I2C_MAX_TIMEOUT;
 	int ret;
 	int i;
 
-	ret = mxs_i2c_write(chip, addr, alen, NULL, 0, 0);
+	ret = mxs_i2c_write(adap, chip, addr, alen, NULL, 0, 0);
 	if (ret) {
 		debug("MXS I2C: Failed writing address\n");
 		return ret;
 	}
 
-	ret = mxs_i2c_wait_for_ack();
+	ret = mxs_i2c_wait_for_ack(adap);
 	if (ret) {
 		debug("MXS I2C: Failed writing address\n");
 		return ret;
 	}
 
-	mxs_i2c_setup_read(chip, len);
-	ret = mxs_i2c_wait_for_ack();
+	mxs_i2c_setup_read(adap, chip, len);
+	ret = mxs_i2c_wait_for_ack(adap);
 	if (ret) {
 		debug("MXS I2C: Failed reading address\n");
 		return ret;
@@ -209,91 +274,47 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 	return 0;
 }
 
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int mxs_i2c_if_write(struct i2c_adapter *adap, uint8_t chip,
+			    uint addr, int alen, uint8_t *buffer,
+			    int len)
 {
 	int ret;
-	ret = mxs_i2c_write(chip, addr, alen, buffer, len, 1);
+	ret = mxs_i2c_write(adap, chip, addr, alen, buffer, len, 1);
 	if (ret) {
 		debug("MXS I2C: Failed writing address\n");
 		return ret;
 	}
 
-	ret = mxs_i2c_wait_for_ack();
+	ret = mxs_i2c_wait_for_ack(adap);
 	if (ret)
 		debug("MXS I2C: Failed writing address\n");
 
 	return ret;
 }
 
-int i2c_probe(uchar chip)
+static int mxs_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
 {
 	int ret;
-	ret = mxs_i2c_write(chip, 0, 1, NULL, 0, 1);
+	ret = mxs_i2c_write(adap, chip, 0, 1, NULL, 0, 1);
 	if (!ret)
-		ret = mxs_i2c_wait_for_ack();
-	mxs_i2c_reset();
+		ret = mxs_i2c_wait_for_ack(adap);
+	mxs_i2c_reset(adap);
 	return ret;
 }
 
-int i2c_set_bus_speed(unsigned int speed)
+static void mxs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 {
-	struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
-	/*
-	 * The timing derivation algorithm. There is no documentation for this
-	 * algorithm available, it was derived by using the scope and fiddling
-	 * with constants until the result observed on the scope was good enough
-	 * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
-	 * possible to assume the algorithm works for other frequencies as well.
-	 *
-	 * Note it was necessary to cap the frequency on both ends as it's not
-	 * possible to configure completely arbitrary frequency for the I2C bus
-	 * clock.
-	 */
-	uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
-	uint32_t base = ((clk / speed) - 38) / 2;
-	uint16_t high_count = base + 3;
-	uint16_t low_count = base - 3;
-	uint16_t rcv_count = (high_count * 3) / 4;
-	uint16_t xmit_count = low_count / 4;
-
-	if (speed > 540000) {
-		printf("MXS I2C: Speed too high (%d Hz)\n", speed);
-		return -EINVAL;
-	}
-
-	if (speed < 12000) {
-		printf("MXS I2C: Speed too low (%d Hz)\n", speed);
-		return -EINVAL;
-	}
-
-	writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0);
-	writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1);
-
-	writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
-		(0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
-		&i2c_regs->hw_i2c_timing2);
-
-	return 0;
-}
-
-unsigned int i2c_get_bus_speed(void)
-{
-	struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
-	uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
-	uint32_t timing0;
-
-	timing0 = readl(&i2c_regs->hw_i2c_timing0);
-	/*
-	 * This is a reverse version of the algorithm presented in
-	 * i2c_set_bus_speed(). Please refer there for details.
-	 */
-	return clk / ((((timing0 >> 16) - 3) * 2) + 38);
-}
-
-void i2c_init(int speed, int slaveadd)
-{
-	mxs_i2c_reset();
-	i2c_set_bus_speed(speed);
+	mxs_i2c_reset(adap);
+	mxs_i2c_set_bus_speed(adap, speed);
 
 	return;
 }
+
+U_BOOT_I2C_ADAP_COMPLETE(mxs0, mxs_i2c_init, mxs_i2c_probe,
+			 mxs_i2c_if_read, mxs_i2c_if_write,
+			 mxs_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_SPEED, 0, 0)
+U_BOOT_I2C_ADAP_COMPLETE(mxs1, mxs_i2c_init, mxs_i2c_probe,
+			 mxs_i2c_if_read, mxs_i2c_if_write,
+			 mxs_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_SPEED, 0, 1)
diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c
index 257b72f0f7c..562211e7deb 100644
--- a/drivers/i2c/tegra_i2c.c
+++ b/drivers/i2c/tegra_i2c.c
@@ -471,8 +471,8 @@ static void tegra_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 }
 
 /* i2c write version without the register address */
-int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len,
-		   bool end_with_repeated_start)
+static int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer,
+			  int len, bool end_with_repeated_start)
 {
 	int rc;
 
@@ -493,7 +493,8 @@ int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len,
 }
 
 /* i2c read version without the register address */
-int i2c_read_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len)
+static int i2c_read_data(struct i2c_bus *bus, uchar chip, uchar *buffer,
+				int len)
 {
 	int rc;
 
diff --git a/drivers/input/tegra-kbc.c b/drivers/input/tegra-kbc.c
index 7e36db0a71a..0ef94f7a00b 100644
--- a/drivers/input/tegra-kbc.c
+++ b/drivers/input/tegra-kbc.c
@@ -181,7 +181,7 @@ static void kbd_wait_for_fifo_init(struct keyb *config)
  * @param input		Input configuration
  * @return 1, to indicate that we have something to look at
  */
-int tegra_kbc_check(struct input_config *input)
+static int tegra_kbc_check(struct input_config *input)
 {
 	kbd_wait_for_fifo_init(&config);
 	check_for_keys(&config);
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 068373b9426..521edfd5de5 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -16,6 +16,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <dm.h>
 #include <i2c.h>
 #include <cros_ec.h>
 #include <fdtdec.h>
@@ -24,6 +25,8 @@
 #include <asm/errno.h>
 #include <asm/io.h>
 #include <asm-generic/gpio.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
 
 #ifdef DEBUG_TRACE
 #define debug_trace(fmt, b...)	debug(fmt, #b)
@@ -38,7 +41,9 @@ enum {
 	CROS_EC_CMD_HASH_TIMEOUT_MS = 2000,
 };
 
+#ifndef CONFIG_DM_CROS_EC
 static struct cros_ec_dev static_dev, *last_dev;
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -204,6 +209,9 @@ static int send_command_proto3(struct cros_ec_dev *dev,
 			       const void *dout, int dout_len,
 			       uint8_t **dinp, int din_len)
 {
+#ifdef CONFIG_DM_CROS_EC
+	struct dm_cros_ec_ops *ops;
+#endif
 	int out_bytes, in_bytes;
 	int rv;
 
@@ -218,6 +226,10 @@ static int send_command_proto3(struct cros_ec_dev *dev,
 	if (in_bytes < 0)
 		return in_bytes;
 
+#ifdef CONFIG_DM_CROS_EC
+	ops = dm_cros_ec_get_ops(dev->dev);
+	rv = ops->packet(dev->dev, out_bytes, in_bytes);
+#else
 	switch (dev->interface) {
 #ifdef CONFIG_CROS_EC_SPI
 	case CROS_EC_IF_SPI:
@@ -235,6 +247,7 @@ static int send_command_proto3(struct cros_ec_dev *dev,
 		debug("%s: Unsupported interface\n", __func__);
 		rv = -1;
 	}
+#endif
 	if (rv < 0)
 		return rv;
 
@@ -246,6 +259,9 @@ static int send_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 			const void *dout, int dout_len,
 			uint8_t **dinp, int din_len)
 {
+#ifdef CONFIG_DM_CROS_EC
+	struct dm_cros_ec_ops *ops;
+#endif
 	int ret = -1;
 
 	/* Handle protocol version 3 support */
@@ -254,6 +270,11 @@ static int send_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 					   dout, dout_len, dinp, din_len);
 	}
 
+#ifdef CONFIG_DM_CROS_EC
+	ops = dm_cros_ec_get_ops(dev->dev);
+	ret = ops->command(dev->dev, cmd, cmd_version,
+			   (const uint8_t *)dout, dout_len, dinp, din_len);
+#else
 	switch (dev->interface) {
 #ifdef CONFIG_CROS_EC_SPI
 	case CROS_EC_IF_SPI:
@@ -280,6 +301,7 @@ static int send_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 	default:
 		ret = -1;
 	}
+#endif
 
 	return ret;
 }
@@ -990,6 +1012,7 @@ int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state)
 	return 0;
 }
 
+#ifndef CONFIG_DM_CROS_EC
 /**
  * Decode EC interface details from the device tree and allocate a suitable
  * device.
@@ -1055,11 +1078,61 @@ static int cros_ec_decode_fdt(const void *blob, int node,
 
 	return 0;
 }
+#endif
 
-int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp)
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_register(struct udevice *dev)
 {
+	struct cros_ec_dev *cdev = dev->uclass_priv;
+	const void *blob = gd->fdt_blob;
+	int node = dev->of_offset;
 	char id[MSG_BYTES];
+
+	cdev->dev = dev;
+	fdtdec_decode_gpio(blob, node, "ec-interrupt", &cdev->ec_int);
+	cdev->optimise_flash_write = fdtdec_get_bool(blob, node,
+						     "optimise-flash-write");
+
+	/* we will poll the EC interrupt line */
+	fdtdec_setup_gpio(&cdev->ec_int);
+	if (fdt_gpio_isvalid(&cdev->ec_int)) {
+		gpio_request(cdev->ec_int.gpio, "cros-ec-irq");
+		gpio_direction_input(cdev->ec_int.gpio);
+	}
+
+	if (cros_ec_check_version(cdev)) {
+		debug("%s: Could not detect CROS-EC version\n", __func__);
+		return -CROS_EC_ERR_CHECK_VERSION;
+	}
+
+	if (cros_ec_read_id(cdev, id, sizeof(id))) {
+		debug("%s: Could not read KBC ID\n", __func__);
+		return -CROS_EC_ERR_READ_ID;
+	}
+
+	/* Remember this device for use by the cros_ec command */
+	debug("Google Chrome EC CROS-EC driver ready, id '%s'\n", id);
+
+	return 0;
+}
+#else
+int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp)
+{
 	struct cros_ec_dev *dev;
+	char id[MSG_BYTES];
+#ifdef CONFIG_DM_CROS_EC
+	struct udevice *udev;
+	int ret;
+
+	ret = uclass_find_device(UCLASS_CROS_EC, 0, &udev);
+	if (!ret)
+		device_remove(udev);
+	ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev);
+	if (ret)
+		return ret;
+	dev = udev->uclass_priv;
+	return 0;
+#else
 	int node = 0;
 
 	*cros_ecp = NULL;
@@ -1108,11 +1181,14 @@ int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp)
 	default:
 		return 0;
 	}
+#endif
 
 	/* we will poll the EC interrupt line */
 	fdtdec_setup_gpio(&dev->ec_int);
-	if (fdt_gpio_isvalid(&dev->ec_int))
+	if (fdt_gpio_isvalid(&dev->ec_int)) {
+		gpio_request(dev->ec_int.gpio, "cros-ec-irq");
 		gpio_direction_input(dev->ec_int.gpio);
+	}
 
 	if (cros_ec_check_version(dev)) {
 		debug("%s: Could not detect CROS-EC version\n", __func__);
@@ -1125,11 +1201,15 @@ int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp)
 	}
 
 	/* Remember this device for use by the cros_ec command */
-	last_dev = *cros_ecp = dev;
+	*cros_ecp = dev;
+#ifndef CONFIG_DM_CROS_EC
+	last_dev = dev;
+#endif
 	debug("Google Chrome EC CROS-EC driver ready, id '%s'\n", id);
 
 	return 0;
 }
+#endif
 
 int cros_ec_decode_region(int argc, char * const argv[])
 {
@@ -1147,15 +1227,10 @@ int cros_ec_decode_region(int argc, char * const argv[])
 	return -1;
 }
 
-int cros_ec_decode_ec_flash(const void *blob, struct fdt_cros_ec *config)
+int cros_ec_decode_ec_flash(const void *blob, int node,
+			    struct fdt_cros_ec *config)
 {
-	int flash_node, node;
-
-	node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC);
-	if (node < 0) {
-		debug("Failed to find chrome-ec node'\n");
-		return -1;
-	}
+	int flash_node;
 
 	flash_node = fdt_subnode_offset(blob, node, "flash");
 	if (flash_node < 0) {
@@ -1516,7 +1591,10 @@ static int cros_ec_i2c_passthrough(struct cros_ec_dev *dev, int flag,
 
 static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	struct cros_ec_dev *dev = last_dev;
+	struct cros_ec_dev *dev;
+#ifdef CONFIG_DM_CROS_EC
+	struct udevice *udev;
+#endif
 	const char *cmd;
 	int ret = 0;
 
@@ -1525,19 +1603,31 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	cmd = argv[1];
 	if (0 == strcmp("init", cmd)) {
+#ifndef CONFIG_DM_CROS_EC
 		ret = cros_ec_init(gd->fdt_blob, &dev);
 		if (ret) {
 			printf("Could not init cros_ec device (err %d)\n", ret);
 			return 1;
 		}
+#endif
 		return 0;
 	}
 
+#ifdef CONFIG_DM_CROS_EC
+	ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev);
+	if (ret) {
+		printf("Cannot get cros-ec device (err=%d)\n", ret);
+		return 1;
+	}
+	dev = udev->uclass_priv;
+#else
 	/* Just use the last allocated device; there should be only one */
 	if (!last_dev) {
 		printf("No CROS-EC device available\n");
 		return 1;
 	}
+	dev = last_dev;
+#endif
 	if (0 == strcmp("id", cmd)) {
 		char id[MSG_BYTES];
 
@@ -1794,3 +1884,11 @@ U_BOOT_CMD(
 	"crosec i2c mw chip address[.0, .1, .2] value [count] - write to I2C passthru (fill)"
 );
 #endif
+
+#ifdef CONFIG_DM_CROS_EC
+UCLASS_DRIVER(cros_ec) = {
+	.id		= UCLASS_CROS_EC,
+	.name		= "cros_ec",
+	.per_device_auto_alloc_size = sizeof(struct cros_ec_dev),
+};
+#endif
diff --git a/drivers/misc/cros_ec_lpc.c b/drivers/misc/cros_ec_lpc.c
index 0e02671c93d..07624a136fa 100644
--- a/drivers/misc/cros_ec_lpc.c
+++ b/drivers/misc/cros_ec_lpc.c
@@ -54,7 +54,7 @@ int cros_ec_lpc_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 	int csum;
 	int i;
 
-	if (dout_len > EC_HOST_PARAM_SIZE) {
+	if (dout_len > EC_PROTO2_MAX_PARAM_SIZE) {
 		debug("%s: Cannot send %d bytes\n", __func__, dout_len);
 		return -1;
 	}
@@ -159,7 +159,7 @@ int cros_ec_lpc_init(struct cros_ec_dev *dev, const void *blob)
 	byte = 0xff;
 	byte &= inb(EC_LPC_ADDR_HOST_CMD);
 	byte &= inb(EC_LPC_ADDR_HOST_DATA);
-	for (i = 0; i < EC_HOST_PARAM_SIZE && (byte == 0xff); i++)
+	for (i = 0; i < EC_PROTO2_MAX_PARAM_SIZE && (byte == 0xff); i++)
 		byte &= inb(EC_LPC_ADDR_HOST_PARAM + i);
 	if (byte == 0xff) {
 		debug("%s: CROS_EC device not found on LPC bus\n",
diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c
index 8a04af557d0..99cc5297cfb 100644
--- a/drivers/misc/cros_ec_sandbox.c
+++ b/drivers/misc/cros_ec_sandbox.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <cros_ec.h>
+#include <dm.h>
 #include <ec_commands.h>
 #include <errno.h>
 #include <hash.h>
@@ -85,7 +86,7 @@ struct ec_state {
 	struct ec_keymatrix_entry *matrix;	/* the key matrix info */
 	uint8_t keyscan[KEYBOARD_COLS];
 	bool recovery_req;
-} s_state, *state;
+} s_state, *g_state;
 
 /**
  * cros_ec_read_state() - read the sandbox EC state from the state file
@@ -138,7 +139,7 @@ static int cros_ec_read_state(const void *blob, int node)
  */
 static int cros_ec_write_state(void *blob, int node)
 {
-	struct ec_state *ec = &s_state;
+	struct ec_state *ec = g_state;
 
 	/* We are guaranteed enough space to write basic properties */
 	fdt_setprop_u32(blob, node, "current-image", ec->current_image);
@@ -369,7 +370,7 @@ static int process_cmd(struct ec_state *ec,
 		struct fmap_entry *entry;
 		int ret, size;
 
-		entry = &state->ec_config.region[EC_FLASH_REGION_RW];
+		entry = &ec->ec_config.region[EC_FLASH_REGION_RW];
 
 		switch (req->cmd) {
 		case EC_VBOOT_HASH_RECALC:
@@ -426,7 +427,7 @@ static int process_cmd(struct ec_state *ec,
 		case EC_FLASH_REGION_RO:
 		case EC_FLASH_REGION_RW:
 		case EC_FLASH_REGION_WP_RO:
-			entry = &state->ec_config.region[req->region];
+			entry = &ec->ec_config.region[req->region];
 			resp->offset = entry->offset;
 			resp->size = entry->length;
 			len = sizeof(*resp);
@@ -466,16 +467,24 @@ static int process_cmd(struct ec_state *ec,
 	return len;
 }
 
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_sandbox_packet(struct udevice *udev, int out_bytes, int in_bytes)
+{
+	struct cros_ec_dev *dev = udev->uclass_priv;
+	struct ec_state *ec = dev_get_priv(dev->dev);
+#else
 int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes,
 			   int in_bytes)
 {
+	struct ec_state *ec = &s_state;
+#endif
 	struct ec_host_request *req_hdr = (struct ec_host_request *)dev->dout;
 	const void *req_data = req_hdr + 1;
 	struct ec_host_response *resp_hdr = (struct ec_host_response *)dev->din;
 	void *resp_data = resp_hdr + 1;
 	int len;
 
-	len = process_cmd(&s_state, req_hdr, req_data, resp_hdr, resp_data);
+	len = process_cmd(ec, req_hdr, req_data, resp_hdr, resp_data);
 	if (len < 0)
 		return len;
 
@@ -498,7 +507,11 @@ int cros_ec_sandbox_decode_fdt(struct cros_ec_dev *dev, const void *blob)
 
 void cros_ec_check_keyboard(struct cros_ec_dev *dev)
 {
+#ifdef CONFIG_DM_CROS_EC
+	struct ec_state *ec = dev_get_priv(dev->dev);
+#else
 	struct ec_state *ec = &s_state;
+#endif
 	ulong start;
 
 	printf("Press keys for EC to detect on reset (ESC=recovery)...");
@@ -512,6 +525,52 @@ void cros_ec_check_keyboard(struct cros_ec_dev *dev)
 	}
 }
 
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_probe(struct udevice *dev)
+{
+	struct ec_state *ec = dev->priv;
+	struct cros_ec_dev *cdev = dev->uclass_priv;
+	const void *blob = gd->fdt_blob;
+	int node;
+	int err;
+
+	memcpy(ec, &s_state, sizeof(*ec));
+	err = cros_ec_decode_ec_flash(blob, dev->of_offset, &ec->ec_config);
+	if (err)
+		return err;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC_KEYB);
+	if (node < 0) {
+		debug("%s: No cros_ec keyboard found\n", __func__);
+	} else if (keyscan_read_fdt_matrix(ec, blob, node)) {
+		debug("%s: Could not read key matrix\n", __func__);
+		return -1;
+	}
+
+	/* If we loaded EC data, check that the length matches */
+	if (ec->flash_data &&
+	    ec->flash_data_len != ec->ec_config.flash.length) {
+		printf("EC data length is %x, expected %x, discarding data\n",
+		       ec->flash_data_len, ec->ec_config.flash.length);
+		os_free(ec->flash_data);
+		ec->flash_data = NULL;
+	}
+
+	/* Otherwise allocate the memory */
+	if (!ec->flash_data) {
+		ec->flash_data_len = ec->ec_config.flash.length;
+		ec->flash_data = os_malloc(ec->flash_data_len);
+		if (!ec->flash_data)
+			return -ENOMEM;
+	}
+
+	cdev->dev = dev;
+	g_state = ec;
+	return cros_ec_register(dev);
+}
+
+#else
+
 /**
  * Initialize sandbox EC emulation.
  *
@@ -525,8 +584,13 @@ int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob)
 	int node;
 	int err;
 
-	state = &s_state;
-	err = cros_ec_decode_ec_flash(blob, &ec->ec_config);
+	node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC);
+	if (node < 0) {
+		debug("Failed to find chrome-ec node'\n");
+		return -1;
+	}
+
+	err = cros_ec_decode_ec_flash(blob, node, &ec->ec_config);
 	if (err)
 		return err;
 
@@ -557,3 +621,24 @@ int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob)
 
 	return 0;
 }
+#endif
+
+#ifdef CONFIG_DM_CROS_EC
+struct dm_cros_ec_ops cros_ec_ops = {
+	.packet = cros_ec_sandbox_packet,
+};
+
+static const struct udevice_id cros_ec_ids[] = {
+	{ .compatible = "google,cros-ec" },
+	{ }
+};
+
+U_BOOT_DRIVER(cros_ec_sandbox) = {
+	.name		= "cros_ec",
+	.id		= UCLASS_CROS_EC,
+	.of_match	= cros_ec_ids,
+	.probe		= cros_ec_probe,
+	.priv_auto_alloc_size = sizeof(struct ec_state),
+	.ops		= &cros_ec_ops,
+};
+#endif
diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c
index 015333f139a..e403664bb56 100644
--- a/drivers/misc/cros_ec_spi.c
+++ b/drivers/misc/cros_ec_spi.c
@@ -15,23 +15,34 @@
 
 #include <common.h>
 #include <cros_ec.h>
+#include <dm.h>
+#include <errno.h>
 #include <spi.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_spi_packet(struct udevice *udev, int out_bytes, int in_bytes)
+{
+	struct cros_ec_dev *dev = udev->uclass_priv;
+#else
 int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes)
 {
+#endif
+	struct spi_slave *slave = dev_get_parentdata(dev->dev);
 	int rv;
 
 	/* Do the transfer */
-	if (spi_claim_bus(dev->spi)) {
+	if (spi_claim_bus(slave)) {
 		debug("%s: Cannot claim SPI bus\n", __func__);
 		return -1;
 	}
 
-	rv = spi_xfer(dev->spi, max(out_bytes, in_bytes) * 8,
+	rv = spi_xfer(slave, max(out_bytes, in_bytes) * 8,
 		      dev->dout, dev->din,
 		      SPI_XFER_BEGIN | SPI_XFER_END);
 
-	spi_release_bus(dev->spi);
+	spi_release_bus(slave);
 
 	if (rv) {
 		debug("%s: Cannot complete SPI transfer\n", __func__);
@@ -56,10 +67,19 @@ int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes)
  * @param din_len	Maximum size of response in bytes
  * @return number of bytes in response, or -1 on error
  */
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_spi_command(struct udevice *udev, uint8_t cmd, int cmd_version,
+		     const uint8_t *dout, int dout_len,
+		     uint8_t **dinp, int din_len)
+{
+	struct cros_ec_dev *dev = udev->uclass_priv;
+#else
 int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 		     const uint8_t *dout, int dout_len,
 		     uint8_t **dinp, int din_len)
 {
+#endif
+	struct spi_slave *slave = dev_get_parentdata(dev->dev);
 	int in_bytes = din_len + 4;	/* status, length, checksum, trailer */
 	uint8_t *out;
 	uint8_t *p;
@@ -92,7 +112,7 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 	 */
 	memset(dev->din, '\0', in_bytes);
 
-	if (spi_claim_bus(dev->spi)) {
+	if (spi_claim_bus(slave)) {
 		debug("%s: Cannot claim SPI bus\n", __func__);
 		return -1;
 	}
@@ -113,10 +133,10 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 	p = dev->din + sizeof(int64_t) - 2;
 	len = dout_len + 4;
 	cros_ec_dump_data("out", cmd, out, len);
-	rv = spi_xfer(dev->spi, max(len, in_bytes) * 8, out, p,
+	rv = spi_xfer(slave, max(len, in_bytes) * 8, out, p,
 		      SPI_XFER_BEGIN | SPI_XFER_END);
 
-	spi_release_bus(dev->spi);
+	spi_release_bus(slave);
 
 	if (rv) {
 		debug("%s: Cannot complete SPI transfer\n", __func__);
@@ -146,6 +166,7 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 	return len;
 }
 
+#ifndef CONFIG_DM_CROS_EC
 int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob)
 {
 	/* Decode interface-specific FDT params */
@@ -165,11 +186,59 @@ int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob)
  */
 int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob)
 {
-	dev->spi = spi_setup_slave_fdt(blob, dev->node, dev->parent_node);
-	if (!dev->spi) {
+	int ret;
+
+	ret = spi_setup_slave_fdt(blob, dev->node, dev->parent_node,
+				  &slave);
+	if (ret) {
 		debug("%s: Could not setup SPI slave\n", __func__);
-		return -1;
+		return ret;
 	}
 
 	return 0;
 }
+#endif
+
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_probe(struct udevice *dev)
+{
+	struct spi_slave *slave = dev_get_parentdata(dev);
+	int ret;
+
+	/*
+	 * TODO(sjg@chromium.org)
+	 *
+	 * This is really horrible at present. It is an artifact of removing
+	 * the child_pre_probe() method for SPI. Everything here could go in
+	 * an automatic function, except that spi_get_bus_and_cs() wants to
+	 * set it up manually and call device_probe_child().
+	 *
+	 * The solution may be to re-enable the child_pre_probe() method for
+	 * SPI and have it do nothing if the child is already passed in via
+	 * device_probe_child().
+	 */
+	slave->dev = dev;
+	ret = spi_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, slave);
+	if (ret)
+		return ret;
+	return cros_ec_register(dev);
+}
+
+struct dm_cros_ec_ops cros_ec_ops = {
+	.packet = cros_ec_spi_packet,
+	.command = cros_ec_spi_command,
+};
+
+static const struct udevice_id cros_ec_ids[] = {
+	{ .compatible = "google,cros-ec" },
+	{ }
+};
+
+U_BOOT_DRIVER(cros_ec_spi) = {
+	.name		= "cros_ec",
+	.id		= UCLASS_CROS_EC,
+	.of_match	= cros_ec_ids,
+	.probe		= cros_ec_probe,
+	.ops		= &cros_ec_ops,
+};
+#endif
diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c
index 82079d67cd8..92f7d8942f0 100644
--- a/drivers/mmc/bcm2835_sdhci.c
+++ b/drivers/mmc/bcm2835_sdhci.c
@@ -40,6 +40,7 @@
 #include <malloc.h>
 #include <sdhci.h>
 #include <asm/arch/timer.h>
+#include <asm/arch-bcm2835/sdhci.h>
 
 /* 400KHz is max freq for card ID etc. Use that as min */
 #define MIN_FREQ 400000
diff --git a/drivers/mmc/mvebu_mmc.c b/drivers/mmc/mvebu_mmc.c
index d34e74357f0..9f98c3f37c9 100644
--- a/drivers/mmc/mvebu_mmc.c
+++ b/drivers/mmc/mvebu_mmc.c
@@ -14,7 +14,7 @@
 #include <mmc.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <mvebu_mmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 5b0c3020693..ef2cbf9e2fa 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -67,14 +67,19 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 #ifdef OMAP_HSMMC_USE_GPIO
 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 {
-	if (!gpio_is_valid(gpio))
-		return -1;
+	int ret;
 
-	if (gpio_request(gpio, label) < 0)
+#ifndef CONFIG_DM_GPIO
+	if (!gpio_is_valid(gpio))
 		return -1;
+#endif
+	ret = gpio_request(gpio, label);
+	if (ret)
+		return ret;
 
-	if (gpio_direction_input(gpio) < 0)
-		return -1;
+	ret = gpio_direction_input(gpio);
+	if (ret)
+		return ret;
 
 	return gpio;
 }
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
index 637dd972a5b..a5d34876bbb 100644
--- a/drivers/mmc/s5p_sdhci.c
+++ b/drivers/mmc/s5p_sdhci.c
@@ -102,6 +102,7 @@ struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS];
 
 static int do_sdhci_init(struct sdhci_host *host)
 {
+	char str[20];
 	int dev_id, flag;
 	int err = 0;
 
@@ -109,6 +110,8 @@ static int do_sdhci_init(struct sdhci_host *host)
 	dev_id = host->index + PERIPH_ID_SDMMC0;
 
 	if (fdt_gpio_isvalid(&host->pwr_gpio)) {
+		sprintf(str, "sdhci%d_power", host->index & 0xf);
+		gpio_request(host->pwr_gpio.gpio, str);
 		gpio_direction_output(host->pwr_gpio.gpio, 1);
 		err = exynos_pinmux_config(dev_id, flag);
 		if (err) {
@@ -118,7 +121,9 @@ static int do_sdhci_init(struct sdhci_host *host)
 	}
 
 	if (fdt_gpio_isvalid(&host->cd_gpio)) {
-		gpio_direction_output(host->cd_gpio.gpio, 0xf);
+		sprintf(str, "sdhci%d_cd", host->index & 0xf);
+		gpio_request(host->cd_gpio.gpio, str);
+		gpio_direction_input(host->cd_gpio.gpio);
 		if (gpio_get_value(host->cd_gpio.gpio))
 			return -ENODEV;
 
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 3125d13ba3c..de88e19609f 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -124,7 +124,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
 #endif
 #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT	100
 
-int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
+static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 		       struct mmc_data *data)
 {
 	struct sdhci_host *host = mmc->priv;
@@ -355,7 +355,7 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 }
 
-void sdhci_set_ios(struct mmc *mmc)
+static void sdhci_set_ios(struct mmc *mmc)
 {
 	u32 ctrl;
 	struct sdhci_host *host = mmc->priv;
@@ -393,7 +393,7 @@ void sdhci_set_ios(struct mmc *mmc)
 	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 }
 
-int sdhci_init(struct mmc *mmc)
+static int sdhci_init(struct mmc *mmc)
 {
 	struct sdhci_host *host = mmc->priv;
 
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index d4e574fe191..231f0a0315d 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -14,12 +14,13 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
+#include <asm-generic/gpio.h>
 
 struct sunxi_mmc_host {
 	unsigned mmc_no;
 	uint32_t *mclkreg;
-	unsigned database;
 	unsigned fatal_err;
 	unsigned mod_clk;
 	struct sunxi_mmc *reg;
@@ -29,10 +30,22 @@ struct sunxi_mmc_host {
 /* support 4 mmc hosts */
 struct sunxi_mmc_host mmc_host[4];
 
+static int sunxi_mmc_getcd_gpio(int sdc_no)
+{
+	switch (sdc_no) {
+	case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
+	case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
+	case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
+	case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
+	}
+	return -1;
+}
+
 static int mmc_resource_init(int sdc_no)
 {
 	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
 	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	int cd_pin, ret = 0;
 
 	debug("init mmc %d resource\n", sdc_no);
 
@@ -57,10 +70,13 @@ static int mmc_resource_init(int sdc_no)
 		printf("Wrong mmc number %d\n", sdc_no);
 		return -1;
 	}
-	mmchost->database = (unsigned int)mmchost->reg + 0x100;
 	mmchost->mmc_no = sdc_no;
 
-	return 0;
+	cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
+	if (cd_pin != -1)
+		ret = gpio_request(cd_pin, "mmc_cd");
+
+	return ret;
 }
 
 static int mmc_clk_io_on(int sdc_no)
@@ -75,6 +91,11 @@ static int mmc_clk_io_on(int sdc_no)
 	/* config ahb clock */
 	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+	/* unassert reset */
+	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
+#endif
+
 	/* config mod clock */
 	pll_clk = clock_get_pll6();
 	/* should be close to 100 MHz but no more, so round up */
@@ -194,9 +215,9 @@ static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
 		}
 
 		if (reading)
-			buff[i] = readl(mmchost->database);
+			buff[i] = readl(&mmchost->reg->fifo);
 		else
-			writel(buff[i], mmchost->database);
+			writel(buff[i], &mmchost->reg->fifo);
 	}
 
 	return 0;
@@ -343,13 +364,26 @@ out:
 	return error;
 }
 
+static int sunxi_mmc_getcd(struct mmc *mmc)
+{
+	struct sunxi_mmc_host *mmchost = mmc->priv;
+	int cd_pin;
+
+	cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no);
+	if (cd_pin == -1)
+		return 1;
+
+	return !gpio_direction_input(cd_pin);
+}
+
 static const struct mmc_ops sunxi_mmc_ops = {
 	.send_cmd	= mmc_send_cmd,
 	.set_ios	= mmc_set_ios,
 	.init		= mmc_core_init,
+	.getcd		= sunxi_mmc_getcd,
 };
 
-int sunxi_mmc_init(int sdc_no)
+struct mmc *sunxi_mmc_init(int sdc_no)
 {
 	struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
 
@@ -361,16 +395,18 @@ int sunxi_mmc_init(int sdc_no)
 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 	cfg->host_caps = MMC_MODE_4BIT;
 	cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I)
+	cfg->host_caps |= MMC_MODE_HC;
+#endif
 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
 	cfg->f_min = 400000;
 	cfg->f_max = 52000000;
 
-	mmc_resource_init(sdc_no);
-	mmc_clk_io_on(sdc_no);
+	if (mmc_resource_init(sdc_no) != 0)
+		return NULL;
 
-	if (mmc_create(cfg, &mmc_host[sdc_no]) == NULL)
-		return -1;
+	mmc_clk_io_on(sdc_no);
 
-	return 0;
+	return mmc_create(cfg, &mmc_host[sdc_no]);
 }
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index ca9c4aa15fe..2bd36b0ee70 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -13,6 +13,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/mmc.h>
 #include <asm/arch-tegra/tegra_mmc.h>
 #include <mmc.h>
 
@@ -292,7 +293,7 @@ static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd,
 				/* Transfer Complete */
 				debug("r/w is done\n");
 				break;
-			} else if (get_timer(start) > 2000UL) {
+			} else if (get_timer(start) > 8000UL) {
 				writel(mask, &host->reg->norintsts);
 				printf("%s: MMC Timeout\n"
 				       "    Interrupt status        0x%08x\n"
@@ -508,7 +509,7 @@ static int tegra_mmc_core_init(struct mmc *mmc)
 	return 0;
 }
 
-int tegra_mmc_getcd(struct mmc *mmc)
+static int tegra_mmc_getcd(struct mmc *mmc)
 {
 	struct mmc_host *host = mmc->priv;
 
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 9b3175d87fb..50983b837b2 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -63,6 +63,12 @@ flash_info_t flash_info[CFI_MAX_FLASH_BANKS];	/* FLASH chips info */
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
 #endif
 
+#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define __maybe_weak __weak
+#else
+#define __maybe_weak static
+#endif
+
 /*
  * 0xffff is an undefined value for the configuration register. When
  * this value is returned, the configuration register shall not be
@@ -81,14 +87,12 @@ static u16 cfi_flash_config_reg(int i)
 int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
 #endif
 
-static phys_addr_t __cfi_flash_bank_addr(int i)
+__weak phys_addr_t cfi_flash_bank_addr(int i)
 {
 	return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i];
 }
-phys_addr_t cfi_flash_bank_addr(int i)
-	__attribute__((weak, alias("__cfi_flash_bank_addr")));
 
-static unsigned long __cfi_flash_bank_size(int i)
+__weak unsigned long cfi_flash_bank_size(int i)
 {
 #ifdef CONFIG_SYS_FLASH_BANKS_SIZES
 	return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i];
@@ -96,71 +100,49 @@ static unsigned long __cfi_flash_bank_size(int i)
 	return 0;
 #endif
 }
-unsigned long cfi_flash_bank_size(int i)
-	__attribute__((weak, alias("__cfi_flash_bank_size")));
 
-static void __flash_write8(u8 value, void *addr)
+__maybe_weak void flash_write8(u8 value, void *addr)
 {
 	__raw_writeb(value, addr);
 }
 
-static void __flash_write16(u16 value, void *addr)
+__maybe_weak void flash_write16(u16 value, void *addr)
 {
 	__raw_writew(value, addr);
 }
 
-static void __flash_write32(u32 value, void *addr)
+__maybe_weak void flash_write32(u32 value, void *addr)
 {
 	__raw_writel(value, addr);
 }
 
-static void __flash_write64(u64 value, void *addr)
+__maybe_weak void flash_write64(u64 value, void *addr)
 {
 	/* No architectures currently implement __raw_writeq() */
 	*(volatile u64 *)addr = value;
 }
 
-static u8 __flash_read8(void *addr)
+__maybe_weak u8 flash_read8(void *addr)
 {
 	return __raw_readb(addr);
 }
 
-static u16 __flash_read16(void *addr)
+__maybe_weak u16 flash_read16(void *addr)
 {
 	return __raw_readw(addr);
 }
 
-static u32 __flash_read32(void *addr)
+__maybe_weak u32 flash_read32(void *addr)
 {
 	return __raw_readl(addr);
 }
 
-static u64 __flash_read64(void *addr)
+__maybe_weak u64 flash_read64(void *addr)
 {
 	/* No architectures currently implement __raw_readq() */
 	return *(volatile u64 *)addr;
 }
 
-#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-void flash_write8(u8 value, void *addr)__attribute__((weak, alias("__flash_write8")));
-void flash_write16(u16 value, void *addr)__attribute__((weak, alias("__flash_write16")));
-void flash_write32(u32 value, void *addr)__attribute__((weak, alias("__flash_write32")));
-void flash_write64(u64 value, void *addr)__attribute__((weak, alias("__flash_write64")));
-u8 flash_read8(void *addr)__attribute__((weak, alias("__flash_read8")));
-u16 flash_read16(void *addr)__attribute__((weak, alias("__flash_read16")));
-u32 flash_read32(void *addr)__attribute__((weak, alias("__flash_read32")));
-u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64")));
-#else
-#define flash_write8	__flash_write8
-#define flash_write16	__flash_write16
-#define flash_write32	__flash_write32
-#define flash_write64	__flash_write64
-#define flash_read8	__flash_read8
-#define flash_read16	__flash_read16
-#define flash_read32	__flash_read32
-#define flash_read64	__flash_read64
-#endif
-
 /*-----------------------------------------------------------------------
  */
 #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c
index 3e5fb0cd65a..4fc34d6b9fc 100644
--- a/drivers/mtd/nand/kirkwood_nand.c
+++ b/drivers/mtd/nand/kirkwood_nand.c
@@ -8,7 +8,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <nand.h>
 
 /* NAND Flash Soc registers */
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index db1599e9a64..40d670563c1 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -75,7 +75,7 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
 
 #ifdef CONFIG_SPL_BUILD
 /* Check wait pin as dev ready indicator */
-int omap_spl_dev_ready(struct mtd_info *mtd)
+static int omap_spl_dev_ready(struct mtd_info *mtd)
 {
 	return gpmc_cfg->status & (1 << 8);
 }
@@ -162,23 +162,6 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 }
 
 /*
- * omap_reverse_list - re-orders list elements in reverse order [internal]
- * @list:	pointer to start of list
- * @length:	length of list
-*/
-void omap_reverse_list(u8 *list, unsigned int length)
-{
-	unsigned int i, j;
-	unsigned int half_length = length / 2;
-	u8 tmp;
-	for (i = 0, j = length - 1; i < half_length; i++, j--) {
-		tmp = list[i];
-		list[i] = list[j];
-		list[j] = tmp;
-	}
-}
-
-/*
  * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
  * @mtd:	MTD device structure
  * @mode:	Read/Write mode
@@ -351,6 +334,23 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 
 #ifdef CONFIG_NAND_OMAP_ELM
 /*
+ * omap_reverse_list - re-orders list elements in reverse order [internal]
+ * @list:	pointer to start of list
+ * @length:	length of list
+*/
+static void omap_reverse_list(u8 *list, unsigned int length)
+{
+	unsigned int i, j;
+	unsigned int half_length = length / 2;
+	u8 tmp;
+	for (i = 0, j = length - 1; i < half_length; i++, j--) {
+		tmp = list[i];
+		list[i] = list[j];
+		list[j] = tmp;
+	}
+}
+
+/*
  * omap_correct_data_bch - Compares the ecc read from nand spare area
  * with ECC registers values and corrects one bit error if it has occured
  *
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 9e18fb41de6..15789a07d8f 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -5,13 +5,18 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o
+
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_SPI_LOAD)	+= spi_spl_load.o
 obj-$(CONFIG_SPL_SPI_BOOT)	+= fsl_espi_spl.o
 endif
 
+#ifndef CONFIG_DM_SPI
+obj-$(CONFIG_SPI_FLASH) += sf_probe.o
+#endif
 obj-$(CONFIG_CMD_SF) += sf.o
-obj-$(CONFIG_SPI_FLASH) += sf_params.o sf_probe.o sf_ops.o
+obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o
 obj-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
 obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
 obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
diff --git a/drivers/mtd/spi/ramtron.c b/drivers/mtd/spi/ramtron.c
index d50da37c89a..a23032cca58 100644
--- a/drivers/mtd/spi/ramtron.c
+++ b/drivers/mtd/spi/ramtron.c
@@ -35,6 +35,7 @@
 
 #include <common.h>
 #include <malloc.h>
+#include <spi.h>
 #include <spi_flash.h>
 #include "sf_internal.h"
 
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 98e0a34d4e3..1cf2f98310a 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -9,6 +9,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <malloc.h>
 #include <spi.h>
 #include <os.h>
@@ -19,6 +20,11 @@
 #include <asm/getopt.h>
 #include <asm/spi.h>
 #include <asm/state.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * The different states that our SPI flash transitions between.
@@ -34,12 +40,14 @@ enum sandbox_sf_state {
 	SF_ERASE, /* erase the flash */
 	SF_READ_STATUS, /* read the flash's status register */
 	SF_READ_STATUS1, /* read the flash's status register upper 8 bits*/
+	SF_WRITE_STATUS, /* write the flash's status register */
 };
 
 static const char *sandbox_sf_state_name(enum sandbox_sf_state state)
 {
 	static const char * const states[] = {
 		"CMD", "ID", "ADDR", "READ", "WRITE", "ERASE", "READ_STATUS",
+		"READ_STATUS1", "WRITE_STATUS",
 	};
 	return states[state];
 }
@@ -58,6 +66,7 @@ static u8 sandbox_sf_0xff[0x1000];
 
 /* Internal state data for each SPI flash */
 struct sandbox_spi_flash {
+	unsigned int cs;	/* Chip select we are attached to */
 	/*
 	 * As we receive data over the SPI bus, our flash transitions
 	 * between states.  For example, we start off in the SF_CMD
@@ -84,71 +93,124 @@ struct sandbox_spi_flash {
 	int fd;
 };
 
-static int sandbox_sf_setup(void **priv, const char *spec)
+struct sandbox_spi_flash_plat_data {
+	const char *filename;
+	const char *device_name;
+	int bus;
+	int cs;
+};
+
+/**
+ * This is a very strange probe function. If it has platform data (which may
+ * have come from the device tree) then this function gets the filename and
+ * device type from there. Failing that it looks at the command line
+ * parameter.
+ */
+static int sandbox_sf_probe(struct udevice *dev)
 {
 	/* spec = idcode:file */
-	struct sandbox_spi_flash *sbsf;
+	struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
 	const char *file;
 	size_t len, idname_len;
 	const struct spi_flash_params *data;
-
-	file = strchr(spec, ':');
-	if (!file) {
-		printf("sandbox_sf: unable to parse file\n");
-		goto error;
+	struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
+	struct sandbox_state *state = state_get_current();
+	struct udevice *bus = dev->parent;
+	const char *spec = NULL;
+	int ret = 0;
+	int cs = -1;
+	int i;
+
+	debug("%s: bus %d, looking for emul=%p: ", __func__, bus->seq, dev);
+	if (bus->seq >= 0 && bus->seq < CONFIG_SANDBOX_SPI_MAX_BUS) {
+		for (i = 0; i < CONFIG_SANDBOX_SPI_MAX_CS; i++) {
+			if (state->spi[bus->seq][i].emul == dev)
+				cs = i;
+		}
+	}
+	if (cs == -1) {
+		printf("Error: Unknown chip select for device '%s'",
+		       dev->name);
+		return -EINVAL;
+	}
+	debug("found at cs %d\n", cs);
+
+	if (!pdata->filename) {
+		struct sandbox_state *state = state_get_current();
+
+		assert(bus->seq != -1);
+		if (bus->seq < CONFIG_SANDBOX_SPI_MAX_BUS)
+			spec = state->spi[bus->seq][cs].spec;
+		if (!spec)
+			return -ENOENT;
+
+		file = strchr(spec, ':');
+		if (!file) {
+			printf("sandbox_sf: unable to parse file\n");
+			ret = -EINVAL;
+			goto error;
+		}
+		idname_len = file - spec;
+		pdata->filename = file + 1;
+		pdata->device_name = spec;
+		++file;
+	} else {
+		spec = strchr(pdata->device_name, ',');
+		if (spec)
+			spec++;
+		else
+			spec = pdata->device_name;
+		idname_len = strlen(spec);
 	}
-	idname_len = file - spec;
-	++file;
+	debug("%s: device='%s'\n", __func__, spec);
 
 	for (data = spi_flash_params_table; data->name; data++) {
 		len = strlen(data->name);
 		if (idname_len != len)
 			continue;
-		if (!memcmp(spec, data->name, len))
+		if (!strncasecmp(spec, data->name, len))
 			break;
 	}
 	if (!data->name) {
 		printf("sandbox_sf: unknown flash '%*s'\n", (int)idname_len,
 		       spec);
+		ret = -EINVAL;
 		goto error;
 	}
 
 	if (sandbox_sf_0xff[0] == 0x00)
 		memset(sandbox_sf_0xff, 0xff, sizeof(sandbox_sf_0xff));
 
-	sbsf = calloc(sizeof(*sbsf), 1);
-	if (!sbsf) {
-		printf("sandbox_sf: out of memory\n");
-		goto error;
-	}
-
-	sbsf->fd = os_open(file, 02);
+	sbsf->fd = os_open(pdata->filename, 02);
 	if (sbsf->fd == -1) {
 		free(sbsf);
-		printf("sandbox_sf: unable to open file '%s'\n", file);
+		printf("sandbox_sf: unable to open file '%s'\n",
+		       pdata->filename);
+		ret = -EIO;
 		goto error;
 	}
 
 	sbsf->data = data;
+	sbsf->cs = cs;
 
-	*priv = sbsf;
 	return 0;
 
  error:
-	return 1;
+	return ret;
 }
 
-static void sandbox_sf_free(void *priv)
+static int sandbox_sf_remove(struct udevice *dev)
 {
-	struct sandbox_spi_flash *sbsf = priv;
+	struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
 
 	os_close(sbsf->fd);
-	free(sbsf);
+
+	return 0;
 }
 
-static void sandbox_sf_cs_activate(void *priv)
+static void sandbox_sf_cs_activate(struct udevice *dev)
 {
-	struct sandbox_spi_flash *sbsf = priv;
+	struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
 
 	debug("sandbox_sf: CS activated; state is fresh!\n");
 
@@ -160,11 +222,24 @@ static void sandbox_sf_cs_activate(void *priv)
 	sbsf->cmd = SF_CMD;
 }
 
-static void sandbox_sf_cs_deactivate(void *priv)
+static void sandbox_sf_cs_deactivate(struct udevice *dev)
 {
 	debug("sandbox_sf: CS deactivated; cmd done processing!\n");
 }
 
+/*
+ * There are times when the data lines are allowed to tristate.  What
+ * is actually sensed on the line depends on the hardware.  It could
+ * always be 0xFF/0x00 (if there are pull ups/downs), or things could
+ * float and so we'd get garbage back.  This func encapsulates that
+ * scenario so we can worry about the details here.
+ */
+static void sandbox_spi_tristate(u8 *buf, uint len)
+{
+	/* XXX: make this into a user config option ? */
+	memset(buf, 0xff, len);
+}
+
 /* Figure out what command this stream is telling us to do */
 static int sandbox_sf_process_cmd(struct sandbox_spi_flash *sbsf, const u8 *rx,
 				  u8 *tx)
@@ -172,7 +247,8 @@ static int sandbox_sf_process_cmd(struct sandbox_spi_flash *sbsf, const u8 *rx,
 	enum sandbox_sf_state oldstate = sbsf->state;
 
 	/* We need to output a byte for the cmd byte we just ate */
-	sandbox_spi_tristate(tx, 1);
+	if (tx)
+		sandbox_spi_tristate(tx, 1);
 
 	sbsf->cmd = rx[0];
 	switch (sbsf->cmd) {
@@ -200,6 +276,9 @@ static int sandbox_sf_process_cmd(struct sandbox_spi_flash *sbsf, const u8 *rx,
 		debug(" write enabled\n");
 		sbsf->status |= STAT_WEL;
 		break;
+	case CMD_WRITE_STATUS:
+		sbsf->state = SF_WRITE_STATUS;
+		break;
 	default: {
 		int flags = sbsf->data->flags;
 
@@ -216,7 +295,7 @@ static int sandbox_sf_process_cmd(struct sandbox_spi_flash *sbsf, const u8 *rx,
 			sbsf->erase_size = 64 << 10;
 		} else {
 			debug(" cmd unknown: %#x\n", sbsf->cmd);
-			return 1;
+			return -EIO;
 		}
 		sbsf->state = SF_ADDR;
 		break;
@@ -246,20 +325,27 @@ int sandbox_erase_part(struct sandbox_spi_flash *sbsf, int size)
 	return 0;
 }
 
-static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
-		uint bytes)
+static int sandbox_sf_xfer(struct udevice *dev, unsigned int bitlen,
+			   const void *rxp, void *txp, unsigned long flags)
 {
-	struct sandbox_spi_flash *sbsf = priv;
+	struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
+	const uint8_t *rx = rxp;
+	uint8_t *tx = txp;
 	uint cnt, pos = 0;
+	int bytes = bitlen / 8;
 	int ret;
 
 	debug("sandbox_sf: state:%x(%s) bytes:%u\n", sbsf->state,
 	      sandbox_sf_state_name(sbsf->state), bytes);
 
+	if ((flags & SPI_XFER_BEGIN))
+		sandbox_sf_cs_activate(dev);
+
 	if (sbsf->state == SF_CMD) {
 		/* Figure out the initial state */
-		if (sandbox_sf_process_cmd(sbsf, rx, tx))
-			return 1;
+		ret = sandbox_sf_process_cmd(sbsf, rx, tx);
+		if (ret)
+			return ret;
 		++pos;
 	}
 
@@ -290,7 +376,9 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
 				sbsf->off = (sbsf->off << 8) | rx[pos];
 			debug("addr:%06x\n", sbsf->off);
 
-			sandbox_spi_tristate(&tx[pos++], 1);
+			if (tx)
+				sandbox_spi_tristate(&tx[pos], 1);
+			pos++;
 
 			/* See if we're done processing */
 			if (sbsf->addr_bytes <
@@ -300,7 +388,7 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
 			/* Next state! */
 			if (os_lseek(sbsf->fd, sbsf->off, OS_SEEK_SET) < 0) {
 				puts("sandbox_sf: os_lseek() failed");
-				return 1;
+				return -EIO;
 			}
 			switch (sbsf->cmd) {
 			case CMD_READ_ARRAY_FAST:
@@ -326,10 +414,11 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
 
 			cnt = bytes - pos;
 			debug(" tx: read(%u)\n", cnt);
+			assert(tx);
 			ret = os_read(sbsf->fd, tx + pos, cnt);
 			if (ret < 0) {
-				puts("sandbox_spi: os_read() failed\n");
-				return 1;
+				puts("sandbox_sf: os_read() failed\n");
+				return -EIO;
 			}
 			pos += ret;
 			break;
@@ -345,6 +434,10 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
 			memset(tx + pos, sbsf->status >> 8, cnt);
 			pos += cnt;
 			break;
+		case SF_WRITE_STATUS:
+			debug(" write status: %#x (ignored)\n", rx[pos]);
+			pos = bytes;
+			break;
 		case SF_WRITE:
 			/*
 			 * XXX: need to handle exotic behavior:
@@ -359,11 +452,12 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
 
 			cnt = bytes - pos;
 			debug(" rx: write(%u)\n", cnt);
-			sandbox_spi_tristate(&tx[pos], cnt);
+			if (tx)
+				sandbox_spi_tristate(&tx[pos], cnt);
 			ret = os_write(sbsf->fd, rx + pos, cnt);
 			if (ret < 0) {
 				puts("sandbox_spi: os_write() failed\n");
-				return 1;
+				return -EIO;
 			}
 			pos += ret;
 			sbsf->status &= ~STAT_WEL;
@@ -388,7 +482,8 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
 			      sbsf->erase_size);
 
 			cnt = bytes - pos;
-			sandbox_spi_tristate(&tx[pos], cnt);
+			if (tx)
+				sandbox_spi_tristate(&tx[pos], cnt);
 			pos += cnt;
 
 			/*
@@ -410,17 +505,33 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
 	}
 
  done:
-	return pos == bytes ? 0 : 1;
+	if (flags & SPI_XFER_END)
+		sandbox_sf_cs_deactivate(dev);
+	return pos == bytes ? 0 : -EIO;
+}
+
+int sandbox_sf_ofdata_to_platdata(struct udevice *dev)
+{
+	struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
+	const void *blob = gd->fdt_blob;
+	int node = dev->of_offset;
+
+	pdata->filename = fdt_getprop(blob, node, "sandbox,filename", NULL);
+	pdata->device_name = fdt_getprop(blob, node, "compatible", NULL);
+	if (!pdata->filename || !pdata->device_name) {
+		debug("%s: Missing properties, filename=%s, device_name=%s\n",
+		      __func__, pdata->filename, pdata->device_name);
+		return -EINVAL;
+	}
+
+	return 0;
 }
 
-static const struct sandbox_spi_emu_ops sandbox_sf_ops = {
-	.setup         = sandbox_sf_setup,
-	.free          = sandbox_sf_free,
-	.cs_activate   = sandbox_sf_cs_activate,
-	.cs_deactivate = sandbox_sf_cs_deactivate,
+static const struct dm_spi_emul_ops sandbox_sf_emul_ops = {
 	.xfer          = sandbox_sf_xfer,
 };
 
+#ifdef CONFIG_SPI_FLASH
 static int sandbox_cmdline_cb_spi_sf(struct sandbox_state *state,
 				     const char *arg)
 {
@@ -438,8 +549,141 @@ static int sandbox_cmdline_cb_spi_sf(struct sandbox_state *state,
 	 * spec here, but the problem is that no U-Boot init has been done
 	 * yet. Perhaps we can figure something out.
 	 */
-	state->spi[bus][cs].ops = &sandbox_sf_ops;
 	state->spi[bus][cs].spec = spec;
 	return 0;
 }
 SANDBOX_CMDLINE_OPT(spi_sf, 1, "connect a SPI flash: <bus>:<cs>:<id>:<file>");
+
+int sandbox_sf_bind_emul(struct sandbox_state *state, int busnum, int cs,
+			 struct udevice *bus, int of_offset, const char *spec)
+{
+	struct udevice *emul;
+	char name[20], *str;
+	struct driver *drv;
+	int ret;
+
+	/* now the emulator */
+	strncpy(name, spec, sizeof(name) - 6);
+	name[sizeof(name) - 6] = '\0';
+	strcat(name, "-emul");
+	str = strdup(name);
+	if (!str)
+		return -ENOMEM;
+	drv = lists_driver_lookup_name("sandbox_sf_emul");
+	if (!drv) {
+		puts("Cannot find sandbox_sf_emul driver\n");
+		return -ENOENT;
+	}
+	ret = device_bind(bus, drv, str, NULL, of_offset, &emul);
+	if (ret) {
+		printf("Cannot create emul device for spec '%s' (err=%d)\n",
+		       spec, ret);
+		return ret;
+	}
+	state->spi[busnum][cs].emul = emul;
+
+	return 0;
+}
+
+void sandbox_sf_unbind_emul(struct sandbox_state *state, int busnum, int cs)
+{
+	state->spi[busnum][cs].emul = NULL;
+}
+
+static int sandbox_sf_bind_bus_cs(struct sandbox_state *state, int busnum,
+				  int cs, const char *spec)
+{
+	struct udevice *bus, *slave;
+	int ret;
+
+	ret = uclass_find_device_by_seq(UCLASS_SPI, busnum, true, &bus);
+	if (ret) {
+		printf("Invalid bus %d for spec '%s' (err=%d)\n", busnum,
+		       spec, ret);
+		return ret;
+	}
+	ret = device_find_child_by_seq(bus, cs, true, &slave);
+	if (!ret) {
+		printf("Chip select %d already exists for spec '%s'\n", cs,
+		       spec);
+		return -EEXIST;
+	}
+
+	ret = spi_bind_device(bus, cs, "spi_flash_std", spec, &slave);
+	if (ret)
+		return ret;
+
+	return sandbox_sf_bind_emul(state, busnum, cs, bus, -1, spec);
+}
+
+int sandbox_spi_get_emul(struct sandbox_state *state,
+			 struct udevice *bus, struct udevice *slave,
+			 struct udevice **emulp)
+{
+	struct sandbox_spi_info *info;
+	int busnum = bus->seq;
+	int cs = spi_chip_select(slave);
+	int ret;
+
+	info = &state->spi[busnum][cs];
+	if (!info->emul) {
+		/* Use the same device tree node as the SPI flash device */
+		debug("%s: busnum=%u, cs=%u: binding SPI flash emulation: ",
+		      __func__, busnum, cs);
+		ret = sandbox_sf_bind_emul(state, busnum, cs, bus,
+					   slave->of_offset, slave->name);
+		if (ret) {
+			debug("failed (err=%d)\n", ret);
+			return ret;
+		}
+		debug("OK\n");
+	}
+	*emulp = info->emul;
+
+	return 0;
+}
+
+int dm_scan_other(bool pre_reloc_only)
+{
+	struct sandbox_state *state = state_get_current();
+	int busnum, cs;
+
+	if (pre_reloc_only)
+		return 0;
+	for (busnum = 0; busnum < CONFIG_SANDBOX_SPI_MAX_BUS; busnum++) {
+		for (cs = 0; cs < CONFIG_SANDBOX_SPI_MAX_CS; cs++) {
+			const char *spec = state->spi[busnum][cs].spec;
+			int ret;
+
+			if (spec) {
+				ret = sandbox_sf_bind_bus_cs(state, busnum,
+							     cs, spec);
+				if (ret) {
+					debug("%s: Bind failed for bus %d, cs %d\n",
+					      __func__, busnum, cs);
+					return ret;
+				}
+			}
+		}
+	}
+
+	return 0;
+}
+#endif
+
+static const struct udevice_id sandbox_sf_ids[] = {
+	{ .compatible = "sandbox,spi-flash" },
+	{ }
+};
+
+U_BOOT_DRIVER(sandbox_sf_emul) = {
+	.name		= "sandbox_sf_emul",
+	.id		= UCLASS_SPI_EMUL,
+	.of_match	= sandbox_sf_ids,
+	.ofdata_to_platdata = sandbox_sf_ofdata_to_platdata,
+	.probe		= sandbox_sf_probe,
+	.remove		= sandbox_sf_remove,
+	.priv_auto_alloc_size = sizeof(struct sandbox_spi_flash),
+	.platdata_auto_alloc_size = sizeof(struct sandbox_spi_flash_plat_data),
+	.ops		= &sandbox_sf_emul_ops,
+};
diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c
new file mode 100644
index 00000000000..376d8150268
--- /dev/null
+++ b/drivers/mtd/spi/sf-uclass.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <dm/device-internal.h>
+#include "sf_internal.h"
+
+/*
+ * TODO(sjg@chromium.org): This is an old-style function. We should remove
+ * it when all SPI flash drivers use dm
+ */
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int spi_mode)
+{
+	struct udevice *dev;
+
+	if (spi_flash_probe_bus_cs(bus, cs, max_hz, spi_mode, &dev))
+		return NULL;
+
+	return dev->uclass_priv;
+}
+
+void spi_flash_free(struct spi_flash *flash)
+{
+	spi_flash_remove(flash->spi->dev);
+}
+
+int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
+			   unsigned int max_hz, unsigned int spi_mode,
+			   struct udevice **devp)
+{
+	struct spi_slave *slave;
+	struct udevice *bus;
+	char name[20], *str;
+	int ret;
+
+	snprintf(name, sizeof(name), "%d:%d", busnum, cs);
+	str = strdup(name);
+	ret = spi_get_bus_and_cs(busnum, cs, max_hz, spi_mode,
+				  "spi_flash_std", str, &bus, &slave);
+	if (ret)
+		return ret;
+
+	*devp = slave->dev;
+	return 0;
+}
+
+int spi_flash_remove(struct udevice *dev)
+{
+	return device_remove(dev);
+}
+
+UCLASS_DRIVER(spi_flash) = {
+	.id		= UCLASS_SPI_FLASH,
+	.name		= "spi_flash",
+	.per_device_auto_alloc_size = sizeof(struct spi_flash),
+};
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 19d49146ebd..5b7670c9aaf 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -10,6 +10,36 @@
 #ifndef _SF_INTERNAL_H_
 #define _SF_INTERNAL_H_
 
+#include <linux/types.h>
+#include <linux/compiler.h>
+
+/* Dual SPI flash memories - see SPI_COMM_DUAL_... */
+enum spi_dual_flash {
+	SF_SINGLE_FLASH	= 0,
+	SF_DUAL_STACKED_FLASH	= 1 << 0,
+	SF_DUAL_PARALLEL_FLASH	= 1 << 1,
+};
+
+/* Enum list - Full read commands */
+enum spi_read_cmds {
+	ARRAY_SLOW		= 1 << 0,
+	DUAL_OUTPUT_FAST	= 1 << 1,
+	DUAL_IO_FAST		= 1 << 2,
+	QUAD_OUTPUT_FAST	= 1 << 3,
+	QUAD_IO_FAST		= 1 << 4,
+};
+
+#define RD_EXTN	(ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
+#define RD_FULL	(RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
+
+/* sf param flags */
+enum {
+	SECT_4K		= 1 << 0,
+	SECT_32K	= 1 << 1,
+	E_FSR		= 1 << 2,
+	WR_QPP		= 1 << 3,
+};
+
 #define SPI_FLASH_3B_ADDR_LEN		3
 #define SPI_FLASH_CMD_LEN		(1 + SPI_FLASH_3B_ADDR_LEN)
 #define SPI_FLASH_16MB_BOUN		0x1000000
@@ -30,12 +60,12 @@
 #define CMD_WRITE_STATUS		0x01
 #define CMD_PAGE_PROGRAM		0x02
 #define CMD_WRITE_DISABLE		0x04
-#define CMD_READ_STATUS			0x05
+#define CMD_READ_STATUS		0x05
 #define CMD_QUAD_PAGE_PROGRAM		0x32
 #define CMD_READ_STATUS1		0x35
 #define CMD_WRITE_ENABLE		0x06
-#define CMD_READ_CONFIG			0x35
-#define CMD_FLAG_STATUS			0x70
+#define CMD_READ_CONFIG		0x35
+#define CMD_FLAG_STATUS		0x70
 
 /* Read commands */
 #define CMD_READ_ARRAY_SLOW		0x03
@@ -57,7 +87,7 @@
 /* Common status */
 #define STATUS_WIP			(1 << 0)
 #define STATUS_QEB_WINSPAN		(1 << 1)
-#define STATUS_QEB_MXIC			(1 << 6)
+#define STATUS_QEB_MXIC		(1 << 6)
 #define STATUS_PEC			(1 << 7)
 
 #ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
@@ -66,19 +96,42 @@
 
 /* Flash timeout values */
 #define SPI_FLASH_PROG_TIMEOUT		(2 * CONFIG_SYS_HZ)
-#define SPI_FLASH_PAGE_ERASE_TIMEOUT	(5 * CONFIG_SYS_HZ)
+#define SPI_FLASH_PAGE_ERASE_TIMEOUT		(5 * CONFIG_SYS_HZ)
 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT	(10 * CONFIG_SYS_HZ)
 
 /* SST specific */
 #ifdef CONFIG_SPI_FLASH_SST
-# define SST_WP			0x01	/* Supports AAI word program */
+# define SST_WP		0x01	/* Supports AAI word program */
 # define CMD_SST_BP		0x02    /* Byte Program */
-# define CMD_SST_AAI_WP		0xAD	/* Auto Address Incr Word Program */
+# define CMD_SST_AAI_WP	0xAD	/* Auto Address Incr Word Program */
 
 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
 		const void *buf);
 #endif
 
+/**
+ * struct spi_flash_params - SPI/QSPI flash device params structure
+ *
+ * @name:		Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
+ * @jedec:		Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
+ * @ext_jedec:		Device ext_jedec ID
+ * @sector_size:	Sector size of this device
+ * @nr_sectors:	No.of sectors on this device
+ * @e_rd_cmd:		Enum list for read commands
+ * @flags:		Important param, for flash specific behaviour
+ */
+struct spi_flash_params {
+	const char *name;
+	u32 jedec;
+	u16 ext_jedec;
+	u32 sector_size;
+	u32 nr_sectors;
+	u8 e_rd_cmd;
+	u16 flags;
+};
+
+extern const struct spi_flash_params spi_flash_params_table[];
+
 /* Send a single-byte command to the device and read the response */
 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
 
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 453edf01495..61545cacaab 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <spi.h>
 #include <spi_flash.h>
 
 #include "sf_internal.h"
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 4d148d1ace3..26364269be1 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -9,6 +9,8 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
 #include <fdtdec.h>
 #include <malloc.h>
 #include <spi.h>
@@ -95,15 +97,15 @@ static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
 	}
 }
 
-static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
-		u8 *idcode)
+static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode,
+				     struct spi_flash *flash)
 {
 	const struct spi_flash_params *params;
-	struct spi_flash *flash;
 	u8 cmd;
 	u16 jedec = idcode[1] << 8 | idcode[2];
 	u16 ext_jedec = idcode[3] << 8 | idcode[4];
 
+	/* Validate params from spi_flash_params table */
 	params = spi_flash_params_table;
 	for (; params->name != NULL; params++) {
 		if ((params->jedec >> 16) == idcode[0]) {
@@ -120,13 +122,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
 		printf("SF: Unsupported flash IDs: ");
 		printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
 		       idcode[0], jedec, ext_jedec);
-		return NULL;
-	}
-
-	flash = calloc(1, sizeof(*flash));
-	if (!flash) {
-		debug("SF: Failed to allocate spi_flash\n");
-		return NULL;
+		return -EPROTONOSUPPORT;
 	}
 
 	/* Assign spi data */
@@ -136,13 +132,15 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
 	flash->dual_flash = flash->spi->option;
 
 	/* Assign spi_flash ops */
+#ifndef CONFIG_DM_SPI_FLASH
 	flash->write = spi_flash_cmd_write_ops;
-#ifdef CONFIG_SPI_FLASH_SST
+#if defined(CONFIG_SPI_FLASH_SST)
 	if (params->flags & SST_WP)
 		flash->write = sst_write_wp;
 #endif
 	flash->erase = spi_flash_cmd_erase_ops;
 	flash->read = spi_flash_cmd_read_ops;
+#endif
 
 	/* Compute the flash size */
 	flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
@@ -227,15 +225,18 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
 #ifdef CONFIG_SPI_FLASH_BAR
 	u8 curr_bank = 0;
 	if (flash->size > SPI_FLASH_16MB_BOUN) {
+		int ret;
+
 		flash->bank_read_cmd = (idcode[0] == 0x01) ?
 					CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR;
 		flash->bank_write_cmd = (idcode[0] == 0x01) ?
 					CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR;
 
-		if (spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
-					  &curr_bank, 1)) {
+		ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
+					    &curr_bank, 1);
+		if (ret) {
 			debug("SF: fail to read bank addr register\n");
-			return NULL;
+			return ret;
 		}
 		flash->bank_curr = curr_bank;
 	} else {
@@ -250,7 +251,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
 		spi_flash_cmd_write_status(flash, 0);
 #endif
 
-	return flash;
+	return 0;
 }
 
 #ifdef CONFIG_OF_CONTROL
@@ -309,23 +310,29 @@ static int spi_enable_wp_pin(struct spi_flash *flash)
 }
 #endif
 
-static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
+/**
+ * spi_flash_probe_slave() - Probe for a SPI flash device on a bus
+ *
+ * @spi: Bus to probe
+ * @flashp: Pointer to place to put flash info, which may be NULL if the
+ * space should be allocated
+ */
+int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash)
 {
-	struct spi_flash *flash = NULL;
 	u8 idcode[5];
 	int ret;
 
 	/* Setup spi_slave */
 	if (!spi) {
 		printf("SF: Failed to set up slave\n");
-		return NULL;
+		return -ENODEV;
 	}
 
 	/* Claim spi bus */
 	ret = spi_claim_bus(spi);
 	if (ret) {
 		debug("SF: Failed to claim SPI bus: %d\n", ret);
-		goto err_claim_bus;
+		return ret;
 	}
 
 	/* Read the ID codes */
@@ -340,10 +347,10 @@ static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
 	print_buffer(0, idcode, 1, sizeof(idcode), 0);
 #endif
 
-	/* Validate params from spi_flash_params table */
-	flash = spi_flash_validate_params(spi, idcode);
-	if (!flash)
+	if (spi_flash_validate_params(spi, idcode, flash)) {
+		ret = -EINVAL;
 		goto err_read_id;
+	}
 
 	/* Set the quad enable bit - only for quad commands */
 	if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
@@ -351,13 +358,15 @@ static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
 	    (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
 		if (spi_flash_set_qeb(flash, idcode[0])) {
 			debug("SF: Fail to set QEB for %02x\n", idcode[0]);
-			return NULL;
+			ret = -EINVAL;
+			goto err_read_id;
 		}
 	}
 
 #ifdef CONFIG_OF_CONTROL
 	if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
 		debug("SF: FDT decode error\n");
+		ret = -EINVAL;
 		goto err_read_id;
 	}
 #endif
@@ -385,32 +394,51 @@ static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
 	/* Release spi bus */
 	spi_release_bus(spi);
 
-	return flash;
+	return 0;
 
 err_read_id:
 	spi_release_bus(spi);
-err_claim_bus:
-	spi_free_slave(spi);
-	return NULL;
+	return ret;
 }
 
-struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+#ifndef CONFIG_DM_SPI_FLASH
+struct spi_flash *spi_flash_probe_tail(struct spi_slave *bus)
+{
+	struct spi_flash *flash;
+
+	/* Allocate space if needed (not used by sf-uclass */
+	flash = calloc(1, sizeof(*flash));
+	if (!flash) {
+		debug("SF: Failed to allocate spi_flash\n");
+		return NULL;
+	}
+
+	if (spi_flash_probe_slave(bus, flash)) {
+		spi_free_slave(bus);
+		free(flash);
+		return NULL;
+	}
+
+	return flash;
+}
+
+struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs,
 		unsigned int max_hz, unsigned int spi_mode)
 {
-	struct spi_slave *spi;
+	struct spi_slave *bus;
 
-	spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
-	return spi_flash_probe_slave(spi);
+	bus = spi_setup_slave(busnum, cs, max_hz, spi_mode);
+	return spi_flash_probe_tail(bus);
 }
 
 #ifdef CONFIG_OF_SPI_FLASH
 struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,
 				      int spi_node)
 {
-	struct spi_slave *spi;
+	struct spi_slave *bus;
 
-	spi = spi_setup_slave_fdt(blob, slave_node, spi_node);
-	return spi_flash_probe_slave(spi);
+	bus = spi_setup_slave_fdt(blob, slave_node, spi_node);
+	return spi_flash_probe_tail(bus);
 }
 #endif
 
@@ -419,3 +447,61 @@ void spi_flash_free(struct spi_flash *flash)
 	spi_free_slave(flash->spi);
 	free(flash);
 }
+
+#else /* defined CONFIG_DM_SPI_FLASH */
+
+static int spi_flash_std_read(struct udevice *dev, u32 offset, size_t len,
+			      void *buf)
+{
+	struct spi_flash *flash = dev->uclass_priv;
+
+	return spi_flash_cmd_read_ops(flash, offset, len, buf);
+}
+
+int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len,
+			const void *buf)
+{
+	struct spi_flash *flash = dev->uclass_priv;
+
+	return spi_flash_cmd_write_ops(flash, offset, len, buf);
+}
+
+int spi_flash_std_erase(struct udevice *dev, u32 offset, size_t len)
+{
+	struct spi_flash *flash = dev->uclass_priv;
+
+	return spi_flash_cmd_erase_ops(flash, offset, len);
+}
+
+int spi_flash_std_probe(struct udevice *dev)
+{
+	struct spi_slave *slave = dev_get_parentdata(dev);
+	struct spi_flash *flash;
+
+	flash = dev->uclass_priv;
+	flash->dev = dev;
+	debug("%s: slave=%p, cs=%d\n", __func__, slave, slave->cs);
+	return spi_flash_probe_slave(slave, flash);
+}
+
+static const struct dm_spi_flash_ops spi_flash_std_ops = {
+	.read = spi_flash_std_read,
+	.write = spi_flash_std_write,
+	.erase = spi_flash_std_erase,
+};
+
+static const struct udevice_id spi_flash_std_ids[] = {
+	{ .compatible = "spi-flash" },
+	{ }
+};
+
+U_BOOT_DRIVER(spi_flash_std) = {
+	.name		= "spi_flash_std",
+	.id		= UCLASS_SPI_FLASH,
+	.of_match	= spi_flash_std_ids,
+	.probe		= spi_flash_std_probe,
+	.priv_auto_alloc_size = sizeof(struct spi_flash),
+	.ops		= &spi_flash_std_ops,
+};
+
+#endif /* CONFIG_DM_SPI_FLASH */
diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c
index 59cca0f4d99..2e0c871219b 100644
--- a/drivers/mtd/spi/spi_spl_load.c
+++ b/drivers/mtd/spi/spi_spl_load.c
@@ -10,6 +10,7 @@
  */
 
 #include <common.h>
+#include <spi.h>
 #include <spi_flash.h>
 #include <spl.h>
 
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 2c4dd7cb6ad..fb0cf8c1cf1 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
 obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
 obj-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
 obj-$(CONFIG_MVGBE) += mvgbe.o
+obj-$(CONFIG_MVNETA) += mvneta.o
 obj-$(CONFIG_NATSEMI) += natsemi.o
 obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
 obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 439f8ae99e3..08bc1afcf63 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -27,6 +27,7 @@
 #include <net.h>
 #include <miiphy.h>
 #include <malloc.h>
+#include <netdev.h>
 #include <linux/compiler.h>
 #include <asm/arch/emac_defs.h>
 #include <asm/io.h>
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 6e8765cf7b6..6531030463c 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -92,7 +92,10 @@ static struct pci_device_id e1000_supported[] = {
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED},
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED},
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER},
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER},
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS},
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES},
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS},
@@ -1112,8 +1115,11 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
 		if (e1000_get_hw_eeprom_semaphore(hw))
 			return -E1000_ERR_SWFW_SYNC;
 
-		swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
-		if ((swfw_sync & swmask) && !(swfw_sync & fwmask))
+		if (hw->mac_type == e1000_igb)
+			swfw_sync = E1000_READ_REG(hw, I210_SW_FW_SYNC);
+		else
+			swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
+		if (!(swfw_sync & (fwmask | swmask)))
 			break;
 
 		/* firmware currently using resource (fwmask) */
@@ -1374,7 +1380,10 @@ e1000_set_mac_type(struct e1000_hw *hw)
 	case E1000_DEV_ID_ICH8_IGP_M:
 		hw->mac_type = e1000_ich8lan;
 		break;
+	case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
+	case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
 	case PCI_DEVICE_ID_INTEL_I210_COPPER:
+	case PCI_DEVICE_ID_INTEL_I211_COPPER:
 	case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
 	case PCI_DEVICE_ID_INTEL_I210_SERDES:
 	case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
@@ -4429,7 +4438,6 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
 
 		if (hw->mac_type >= e1000_82571)
 			mdelay(10);
-
 	} else {
 		/* Read the Extended Device Control Register, assert the PHY_RESET_DIR
 		 * bit to put the PHY into reset. Then, take it out of reset.
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index b025ecc4fc5..6d110eb5d56 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -2497,6 +2497,7 @@ struct e1000_hw {
 #define ICH_GFPREG_BASE_MASK       0x1FFF
 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
 
+#define E1000_I210_SW_FW_SYNC 0x5B50 /* Software-Firmware Synchronization - RW */
 #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
 
 /* SPI EEPROM Status Register */
diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c
index 1e4ea0c8927..a23a5852ee1 100644
--- a/drivers/net/eepro100.c
+++ b/drivers/net/eepro100.c
@@ -230,7 +230,7 @@ static int eepro100_send(struct eth_device *dev, void *packet, int length);
 static int eepro100_recv (struct eth_device *dev);
 static void eepro100_halt (struct eth_device *dev);
 
-#if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460)
+#if defined(CONFIG_E500)
 #define bus_to_phys(a) (a)
 #define phys_to_bus(a) (a)
 #else
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 549d6486136..b57247032fa 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -11,6 +11,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <miiphy.h>
 #include "fec_mxc.h"
 
@@ -179,13 +180,14 @@ static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
 	return 0;
 }
 
-int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr)
+static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr,
+			int regAddr)
 {
 	return fec_mdio_read(bus->priv, phyAddr, regAddr);
 }
 
-int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
-		u16 data)
+static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr,
+			 int regAddr, u16 data)
 {
 	return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
 }
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index d22b722bc53..c8681d02234 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -10,15 +10,16 @@
 #include <command.h>
 
 #include <net.h>
+#include <phy.h>
+#include <errno.h>
 #include <miiphy.h>
 #include <malloc.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/arch/psc_defs.h>
-#include <asm/arch/keystone_nav.h>
-
-unsigned int emac_dbg;
+#include <asm/ti-common/keystone_nav.h>
+#include <asm/ti-common/keystone_net.h>
+#include <asm/ti-common/keystone_serdes.h>
 
 unsigned int emac_open;
+static struct mii_dev *mdio_bus;
 static unsigned int sys_has_mdio = 1;
 
 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
@@ -30,6 +31,7 @@ static unsigned int sys_has_mdio = 1;
 #define RX_BUFF_NUMS	24
 #define RX_BUFF_LEN	1520
 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
+#define SGMII_ANEG_TIMEOUT		4000
 
 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
 
@@ -40,15 +42,7 @@ struct rx_buff_desc net_rx_buffs = {
 	.rx_flow	= 22,
 };
 
-static void keystone2_eth_mdio_enable(void);
-
-static int gen_get_link_speed(int phy_addr);
-
-/* EMAC Addresses */
-static volatile struct emac_regs	*adap_emac =
-	(struct emac_regs *)EMAC_EMACSL_BASE_ADDR;
-static volatile struct mdio_regs	*adap_mdio =
-	(struct mdio_regs *)EMAC_MDIO_BASE_ADDR;
+static void keystone2_net_serdes_setup(void);
 
 int keystone2_eth_read_mac_addr(struct eth_device *dev)
 {
@@ -74,64 +68,67 @@ int keystone2_eth_read_mac_addr(struct eth_device *dev)
 	return 0;
 }
 
-static void keystone2_eth_mdio_enable(void)
+/* MDIO */
+
+static int keystone2_mdio_reset(struct mii_dev *bus)
 {
-	u_int32_t	clkdiv;
+	u_int32_t clkdiv;
+	struct mdio_regs *adap_mdio = bus->priv;
 
 	clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
 
-	writel((clkdiv & 0xffff) |
-	       MDIO_CONTROL_ENABLE |
-	       MDIO_CONTROL_FAULT |
-	       MDIO_CONTROL_FAULT_ENABLE,
+	writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE |
+	       MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
 	       &adap_mdio->control);
 
 	while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
 		;
+
+	return 0;
 }
 
-/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
-int keystone2_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
+/**
+ * keystone2_mdio_read - read a PHY register via MDIO interface.
+ * Blocks until operation is complete.
+ */
+static int keystone2_mdio_read(struct mii_dev *bus,
+			       int addr, int devad, int reg)
 {
-	int	tmp;
+	int tmp;
+	struct mdio_regs *adap_mdio = bus->priv;
 
 	while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
 		;
 
-	writel(MDIO_USERACCESS0_GO |
-	       MDIO_USERACCESS0_WRITE_READ |
-	       ((reg_num & 0x1f) << 21) |
-	       ((phy_addr & 0x1f) << 16),
+	writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
+	       ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
 	       &adap_mdio->useraccess0);
 
 	/* Wait for command to complete */
 	while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
 		;
 
-	if (tmp & MDIO_USERACCESS0_ACK) {
-		*data = tmp & 0xffff;
-		return 0;
-	}
+	if (tmp & MDIO_USERACCESS0_ACK)
+		return tmp & 0xffff;
 
-	*data = -1;
 	return -1;
 }
 
-/*
- * Write to a PHY register via MDIO inteface.
+/**
+ * keystone2_mdio_write - write to a PHY register via MDIO interface.
  * Blocks until operation is complete.
  */
-int keystone2_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
+static int keystone2_mdio_write(struct mii_dev *bus,
+				int addr, int devad, int reg, u16 val)
 {
+	struct mdio_regs *adap_mdio = bus->priv;
+
 	while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
 		;
 
-	writel(MDIO_USERACCESS0_GO |
-	       MDIO_USERACCESS0_WRITE_WRITE |
-	       ((reg_num & 0x1f) << 21) |
-	       ((phy_addr & 0x1f) << 16) |
-	       (data & 0xffff),
-	       &adap_mdio->useraccess0);
+	writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
+	       ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
+	       (val & 0xffff), &adap_mdio->useraccess0);
 
 	/* Wait for command to complete */
 	while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
@@ -140,19 +137,6 @@ int keystone2_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
 	return 0;
 }
 
-/* PHY functions for a generic PHY */
-static int gen_get_link_speed(int phy_addr)
-{
-	u_int16_t	tmp;
-
-	if ((!keystone2_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp)) &&
-	    (tmp & 0x04)) {
-		return 0;
-	}
-
-	return -1;
-}
-
 static void  __attribute__((unused))
 	keystone2_eth_gigabit_enable(struct eth_device *dev)
 {
@@ -160,8 +144,10 @@ static void  __attribute__((unused))
 	struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
 
 	if (sys_has_mdio) {
-		if (keystone2_eth_phy_read(eth_priv->phy_addr, 0, &data) ||
-		    !(data & (1 << 6))) /* speed selection MSB */
+		data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
+					   MDIO_DEVAD_NONE, 0);
+		/* speed selection MSB */
+		if (!(data & (1 << 6)))
 			return;
 	}
 
@@ -169,10 +155,10 @@ static void  __attribute__((unused))
 	 * Check if link detected is giga-bit
 	 * If Gigabit mode detected, enable gigbit in MAC
 	 */
-	writel(readl(&(adap_emac[eth_priv->slave_port - 1].maccontrol)) |
+	writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
+		     CPGMACSL_REG_CTL) |
 	       EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
-	       &(adap_emac[eth_priv->slave_port - 1].maccontrol))
-		;
+	       DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
 }
 
 int keystone_sgmii_link_status(int port)
@@ -181,38 +167,11 @@ int keystone_sgmii_link_status(int port)
 
 	status = __raw_readl(SGMII_STATUS_REG(port));
 
-	return status & SGMII_REG_STATUS_LINK;
+	return (status & SGMII_REG_STATUS_LOCK) &&
+	       (status & SGMII_REG_STATUS_LINK);
 }
 
-
-int keystone_get_link_status(struct eth_device *dev)
-{
-	struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
-	int sgmii_link;
-	int link_state = 0;
-#if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
-	int j;
-
-	for (j = 0; (j < CONFIG_GET_LINK_STATUS_ATTEMPTS) && (link_state == 0);
-	     j++) {
-#endif
-		sgmii_link =
-			keystone_sgmii_link_status(eth_priv->slave_port - 1);
-
-		if (sgmii_link) {
-			link_state = 1;
-
-			if (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY)
-				if (gen_get_link_speed(eth_priv->phy_addr))
-					link_state = 0;
-		}
-#if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
-	}
-#endif
-	return link_state;
-}
-
-int keystone_sgmii_config(int port, int interface)
+int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
 {
 	unsigned int i, status, mask;
 	unsigned int mr_adv_ability, control;
@@ -273,11 +232,35 @@ int keystone_sgmii_config(int port, int interface)
 	if (control & SGMII_REG_CONTROL_AUTONEG)
 		mask |= SGMII_REG_STATUS_AUTONEG;
 
-	for (i = 0; i < 1000; i++) {
+	status = __raw_readl(SGMII_STATUS_REG(port));
+	if ((status & mask) == mask)
+		return 0;
+
+	printf("\n%s Waiting for SGMII auto negotiation to complete",
+	       phy_dev->dev->name);
+	while ((status & mask) != mask) {
+		/*
+		 * Timeout reached ?
+		 */
+		if (i > SGMII_ANEG_TIMEOUT) {
+			puts(" TIMEOUT !\n");
+			phy_dev->link = 0;
+			return 0;
+		}
+
+		if (ctrlc()) {
+			puts("user interrupt!\n");
+			phy_dev->link = 0;
+			return -EINTR;
+		}
+
+		if ((i++ % 500) == 0)
+			printf(".");
+
+		udelay(1000);   /* 1 ms */
 		status = __raw_readl(SGMII_STATUS_REG(port));
-		if ((status & mask) == mask)
-			break;
 	}
+	puts(" done\n");
 
 	return 0;
 }
@@ -332,6 +315,11 @@ int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
 	writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
 	writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
 
+#ifdef CONFIG_K2E_EVM
+	/* Map RX packet flow priority to 0 */
+	writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
+#endif
+
 	return ret;
 }
 
@@ -393,15 +381,15 @@ int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
 	if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
 		num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
 
-	return netcp_send(buffer, num_bytes, (slave_port_num) << 16);
+	return ksnav_send(&netcp_pktdma, buffer,
+			  num_bytes, (slave_port_num) << 16);
 }
 
 /* Eth device open */
 static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
 {
-	u_int32_t clkdiv;
-	int link;
 	struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
+	struct phy_device *phy_dev = eth_priv->phy_dev;
 
 	debug("+ emac_open\n");
 
@@ -410,15 +398,9 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
 	sys_has_mdio =
 		(eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
 
-	psc_enable_module(KS2_LPSC_PA);
-	psc_enable_module(KS2_LPSC_CPGMAC);
-
-	sgmii_serdes_setup_156p25mhz();
-
-	if (sys_has_mdio)
-		keystone2_eth_mdio_enable();
+	keystone2_net_serdes_setup();
 
-	keystone_sgmii_config(eth_priv->slave_port - 1,
+	keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
 			      eth_priv->sgmii_link_type);
 
 	udelay(10000);
@@ -431,7 +413,7 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
 		printf("ERROR: qm_init()\n");
 		return -1;
 	}
-	if (netcp_init(&net_rx_buffs)) {
+	if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
 		qm_close();
 		printf("ERROR: netcp_init()\n");
 		return -1;
@@ -445,18 +427,11 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
 	hw_config_streaming_switch();
 
 	if (sys_has_mdio) {
-		/* Init MDIO & get link state */
-		clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
-		writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE |
-		       MDIO_CONTROL_FAULT, &adap_mdio->control)
-			;
-
-		/* We need to wait for MDIO to start */
-		udelay(1000);
-
-		link = keystone_get_link_status(dev);
-		if (link == 0) {
-			netcp_close();
+		keystone2_mdio_reset(mdio_bus);
+
+		phy_startup(phy_dev);
+		if (phy_dev->link == 0) {
+			ksnav_close(&netcp_pktdma);
 			qm_close();
 			return -1;
 		}
@@ -476,6 +451,9 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
 /* Eth device close */
 void keystone2_eth_close(struct eth_device *dev)
 {
+	struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
+	struct phy_device *phy_dev = eth_priv->phy_dev;
+
 	debug("+ emac_close\n");
 
 	if (!emac_open)
@@ -483,16 +461,15 @@ void keystone2_eth_close(struct eth_device *dev)
 
 	ethss_stop();
 
-	netcp_close();
+	ksnav_close(&netcp_pktdma);
 	qm_close();
+	phy_shutdown(phy_dev);
 
 	emac_open = 0;
 
 	debug("- emac_close\n");
 }
 
-static int tx_send_loop;
-
 /*
  * This function sends a single packet on the network and returns
  * positive number (number of bytes transmitted) or negative for error
@@ -502,22 +479,15 @@ static int keystone2_eth_send_packet(struct eth_device *dev,
 {
 	int ret_status = -1;
 	struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
+	struct phy_device *phy_dev = eth_priv->phy_dev;
 
-	tx_send_loop = 0;
-
-	if (keystone_get_link_status(dev) == 0)
+	genphy_update_link(phy_dev);
+	if (phy_dev->link == 0)
 		return -1;
 
-	emac_gigabit_enable(dev);
-
 	if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
 		return ret_status;
 
-	if (keystone_get_link_status(dev) == 0)
-		return -1;
-
-	emac_gigabit_enable(dev);
-
 	return length;
 }
 
@@ -530,13 +500,13 @@ static int keystone2_eth_rcv_packet(struct eth_device *dev)
 	int  pkt_size;
 	u32  *pkt;
 
-	hd = netcp_recv(&pkt, &pkt_size);
+	hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
 	if (hd == NULL)
 		return 0;
 
 	NetReceive((uchar *)pkt, pkt_size);
 
-	netcp_release_rxhd(hd);
+	ksnav_release_rxhd(&netcp_pktdma, hd);
 
 	return pkt_size;
 }
@@ -546,7 +516,9 @@ static int keystone2_eth_rcv_packet(struct eth_device *dev)
  */
 int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
 {
+	int res;
 	struct eth_device *dev;
+	struct phy_device *phy_dev;
 
 	dev = malloc(sizeof(struct eth_device));
 	if (dev == NULL)
@@ -567,145 +539,55 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
 
 	eth_register(dev);
 
-	return 0;
-}
-
-void sgmii_serdes_setup_156p25mhz(void)
-{
-	unsigned int cnt;
-
-	/*
-	 * configure Serializer/Deserializer (SerDes) hardware. SerDes IP
-	 * hardware vendor published only register addresses and their values
-	 * to be used for configuring SerDes. So had to use hardcoded values
-	 * below.
-	 */
-	clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000);
-	clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282);
-	clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438);
-	clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700);
-	clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000);
-
-	clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080);
-	clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000);
-	clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000);
-	clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000);
-	clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8);
-	clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4);
-	clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400);
-	clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800);
-	clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082);
-	clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385);
-
-	clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080);
-	clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000);
-	clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000);
-	clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000);
-	clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8);
-	clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4);
-	clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400);
-	clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800);
-	clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082);
-	clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385);
-
-	clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080);
-	clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000);
-	clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000);
-	clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000);
-	clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8);
-	clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4);
-	clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400);
-	clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800);
-	clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082);
-	clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385);
-
-	clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080);
-	clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000);
-	clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000);
-	clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000);
-	clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8);
-	clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4);
-	clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400);
-	clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800);
-	clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082);
-	clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385);
-
-	clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800);
-	clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000);
-	clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00);
-	clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600);
-	clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000);
-	clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000);
-	clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000);
-	clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b);
-	clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000);
-	clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e);
-	clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003);
-	clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f);
-
-	clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00);
-	clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72);
-	clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100);
-	clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060);
-	clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000);
-	clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220);
-	clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602);
-	clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1);
-	clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989);
-	clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001);
-	clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000);
-	clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000);
-	clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d);
-
-	/*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/
-	clrbits_le32(0x0232a010, 1 << 28);
-
-	/* Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */
-	clrbits_le32(0x0232a228, 1 << 29);
-	writel(0xF800F8C0, 0x0232bfe0);
-	clrbits_le32(0x0232a428, 1 << 29);
-	writel(0xF800F8C0, 0x0232bfe4);
-	clrbits_le32(0x0232a628, 1 << 29);
-	writel(0xF800F8C0, 0x0232bfe8);
-	clrbits_le32(0x0232a828, 1 << 29);
-	writel(0xF800F8C0, 0x0232bfec);
-
-	/*Enable pll via the pll_ctrl 0x0014*/
-	writel(0xe0000000, 0x0232bff4)
-		;
-
-	/*Waiting for SGMII Serdes PLL lock.*/
-	for (cnt = 10000; cnt > 0 && ((readl(0x02090114) & 0x10) == 0); cnt--)
-		;
-
-	for (cnt = 10000; cnt > 0 && ((readl(0x02090214) & 0x10) == 0); cnt--)
-		;
-
-	for (cnt = 10000; cnt > 0 && ((readl(0x02090414) & 0x10) == 0); cnt--)
-		;
+	/* Register MDIO bus if it's not registered yet */
+	if (!mdio_bus) {
+		mdio_bus	= mdio_alloc();
+		mdio_bus->read	= keystone2_mdio_read;
+		mdio_bus->write	= keystone2_mdio_write;
+		mdio_bus->reset	= keystone2_mdio_reset;
+		mdio_bus->priv	= (void *)EMAC_MDIO_BASE_ADDR;
+		sprintf(mdio_bus->name, "ethernet-mdio");
+
+		res = mdio_register(mdio_bus);
+		if (res)
+			return res;
+	}
 
-	for (cnt = 10000; cnt > 0 && ((readl(0x02090514) & 0x10) == 0); cnt--)
-		;
+	/* Create phy device and bind it with driver */
+#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
+	phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
+			      dev, PHY_INTERFACE_MODE_SGMII);
+	phy_config(phy_dev);
+#else
+	phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
+				   PHY_INTERFACE_MODE_SGMII);
+	phy_dev->dev = dev;
+#endif
+	eth_priv->phy_dev = phy_dev;
 
-	udelay(45000);
+	return 0;
 }
 
-void sgmii_serdes_shutdown(void)
+struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
+	.clk = SERDES_CLOCK_156P25M,
+	.rate = SERDES_RATE_5G,
+	.rate_mode = SERDES_QUARTER_RATE,
+	.intf = SERDES_PHY_SGMII,
+	.loopback = 0,
+};
+
+static void keystone2_net_serdes_setup(void)
 {
-	/*
-	 * shutdown SerDes hardware. SerDes hardware vendor published only
-	 * register addresses and their values. So had to use hardcoded
-	 * values below.
-	 */
-	clrbits_le32(0x0232bfe0, 3 << 29 | 3 << 13);
-	setbits_le32(0x02320228, 1 << 29);
-	clrbits_le32(0x0232bfe4, 3 << 29 | 3 << 13);
-	setbits_le32(0x02320428, 1 << 29);
-	clrbits_le32(0x0232bfe8, 3 << 29 | 3 << 13);
-	setbits_le32(0x02320628, 1 << 29);
-	clrbits_le32(0x0232bfec, 3 << 29 | 3 << 13);
-	setbits_le32(0x02320828, 1 << 29);
-
-	clrbits_le32(0x02320034, 3 << 29);
-	setbits_le32(0x02320010, 1 << 28);
+	ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
+			&ks2_serdes_sgmii_156p25mhz,
+			CONFIG_KSNET_SERDES_LANES_PER_SGMII);
+
+#ifdef CONFIG_SOC_K2E
+	ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
+			&ks2_serdes_sgmii_156p25mhz,
+			CONFIG_KSNET_SERDES_LANES_PER_SGMII);
+#endif
+
+	/* wait till setup */
+	udelay(5000);
 }
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 0cd06b6a69d..6ef6cacb6b8 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -24,7 +24,7 @@
 #include <asm/arch/cpu.h>
 
 #if defined(CONFIG_KIRKWOOD)
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #elif defined(CONFIG_ORION5X)
 #include <asm/arch/orion5x.h>
 #elif defined(CONFIG_DOVE)
diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
new file mode 100644
index 00000000000..a2a69b42190
--- /dev/null
+++ b/drivers/net/mvneta.c
@@ -0,0 +1,1653 @@
+/*
+ * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
+ *
+ * U-Boot version:
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * Based on the Linux version which is:
+ * Copyright (C) 2012 Marvell
+ *
+ * Rami Rosen <rosenr@marvell.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <config.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <phy.h>
+#include <miiphy.h>
+#include <watchdog.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/compat.h>
+#include <linux/mbus.h>
+
+#if !defined(CONFIG_PHYLIB)
+# error Marvell mvneta requires PHYLIB
+#endif
+
+/* Some linux -> U-Boot compatibility stuff */
+#define netdev_err(dev, fmt, args...)		\
+	printf(fmt, ##args)
+#define netdev_warn(dev, fmt, args...)		\
+	printf(fmt, ##args)
+#define netdev_info(dev, fmt, args...)		\
+	printf(fmt, ##args)
+
+#define CONFIG_NR_CPUS		1
+#define BIT(nr)			(1UL << (nr))
+#define ETH_HLEN		14	/* Total octets in header */
+
+/* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
+#define WRAP			(2 + ETH_HLEN + 4 + 32)
+#define MTU			1500
+#define RX_BUFFER_SIZE		(ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
+
+#define MVNETA_SMI_TIMEOUT			10000
+
+/* Registers */
+#define MVNETA_RXQ_CONFIG_REG(q)                (0x1400 + ((q) << 2))
+#define	     MVNETA_RXQ_HW_BUF_ALLOC            BIT(1)
+#define      MVNETA_RXQ_PKT_OFFSET_ALL_MASK     (0xf    << 8)
+#define      MVNETA_RXQ_PKT_OFFSET_MASK(offs)   ((offs) << 8)
+#define MVNETA_RXQ_THRESHOLD_REG(q)             (0x14c0 + ((q) << 2))
+#define      MVNETA_RXQ_NON_OCCUPIED(v)         ((v) << 16)
+#define MVNETA_RXQ_BASE_ADDR_REG(q)             (0x1480 + ((q) << 2))
+#define MVNETA_RXQ_SIZE_REG(q)                  (0x14a0 + ((q) << 2))
+#define      MVNETA_RXQ_BUF_SIZE_SHIFT          19
+#define      MVNETA_RXQ_BUF_SIZE_MASK           (0x1fff << 19)
+#define MVNETA_RXQ_STATUS_REG(q)                (0x14e0 + ((q) << 2))
+#define      MVNETA_RXQ_OCCUPIED_ALL_MASK       0x3fff
+#define MVNETA_RXQ_STATUS_UPDATE_REG(q)         (0x1500 + ((q) << 2))
+#define      MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT  16
+#define      MVNETA_RXQ_ADD_NON_OCCUPIED_MAX    255
+#define MVNETA_PORT_RX_RESET                    0x1cc0
+#define      MVNETA_PORT_RX_DMA_RESET           BIT(0)
+#define MVNETA_PHY_ADDR                         0x2000
+#define      MVNETA_PHY_ADDR_MASK               0x1f
+#define MVNETA_SMI                              0x2004
+#define      MVNETA_PHY_REG_MASK                0x1f
+/* SMI register fields */
+#define     MVNETA_SMI_DATA_OFFS		0	/* Data */
+#define     MVNETA_SMI_DATA_MASK		(0xffff << MVNETA_SMI_DATA_OFFS)
+#define     MVNETA_SMI_DEV_ADDR_OFFS		16	/* PHY device address */
+#define     MVNETA_SMI_REG_ADDR_OFFS		21	/* PHY device reg addr*/
+#define     MVNETA_SMI_OPCODE_OFFS		26	/* Write/Read opcode */
+#define     MVNETA_SMI_OPCODE_READ		(1 << MVNETA_SMI_OPCODE_OFFS)
+#define     MVNETA_SMI_READ_VALID		(1 << 27)	/* Read Valid */
+#define     MVNETA_SMI_BUSY			(1 << 28)	/* Busy */
+#define MVNETA_MBUS_RETRY                       0x2010
+#define MVNETA_UNIT_INTR_CAUSE                  0x2080
+#define MVNETA_UNIT_CONTROL                     0x20B0
+#define      MVNETA_PHY_POLLING_ENABLE          BIT(1)
+#define MVNETA_WIN_BASE(w)                      (0x2200 + ((w) << 3))
+#define MVNETA_WIN_SIZE(w)                      (0x2204 + ((w) << 3))
+#define MVNETA_WIN_REMAP(w)                     (0x2280 + ((w) << 2))
+#define MVNETA_BASE_ADDR_ENABLE                 0x2290
+#define MVNETA_PORT_CONFIG                      0x2400
+#define      MVNETA_UNI_PROMISC_MODE            BIT(0)
+#define      MVNETA_DEF_RXQ(q)                  ((q) << 1)
+#define      MVNETA_DEF_RXQ_ARP(q)              ((q) << 4)
+#define      MVNETA_TX_UNSET_ERR_SUM            BIT(12)
+#define      MVNETA_DEF_RXQ_TCP(q)              ((q) << 16)
+#define      MVNETA_DEF_RXQ_UDP(q)              ((q) << 19)
+#define      MVNETA_DEF_RXQ_BPDU(q)             ((q) << 22)
+#define      MVNETA_RX_CSUM_WITH_PSEUDO_HDR     BIT(25)
+#define      MVNETA_PORT_CONFIG_DEFL_VALUE(q)   (MVNETA_DEF_RXQ(q)       | \
+						 MVNETA_DEF_RXQ_ARP(q)	 | \
+						 MVNETA_DEF_RXQ_TCP(q)	 | \
+						 MVNETA_DEF_RXQ_UDP(q)	 | \
+						 MVNETA_DEF_RXQ_BPDU(q)	 | \
+						 MVNETA_TX_UNSET_ERR_SUM | \
+						 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
+#define MVNETA_PORT_CONFIG_EXTEND                0x2404
+#define MVNETA_MAC_ADDR_LOW                      0x2414
+#define MVNETA_MAC_ADDR_HIGH                     0x2418
+#define MVNETA_SDMA_CONFIG                       0x241c
+#define      MVNETA_SDMA_BRST_SIZE_16            4
+#define      MVNETA_RX_BRST_SZ_MASK(burst)       ((burst) << 1)
+#define      MVNETA_RX_NO_DATA_SWAP              BIT(4)
+#define      MVNETA_TX_NO_DATA_SWAP              BIT(5)
+#define      MVNETA_DESC_SWAP                    BIT(6)
+#define      MVNETA_TX_BRST_SZ_MASK(burst)       ((burst) << 22)
+#define MVNETA_PORT_STATUS                       0x2444
+#define      MVNETA_TX_IN_PRGRS                  BIT(1)
+#define      MVNETA_TX_FIFO_EMPTY                BIT(8)
+#define MVNETA_RX_MIN_FRAME_SIZE                 0x247c
+#define MVNETA_SERDES_CFG			 0x24A0
+#define      MVNETA_SGMII_SERDES_PROTO		 0x0cc7
+#define      MVNETA_QSGMII_SERDES_PROTO		 0x0667
+#define MVNETA_TYPE_PRIO                         0x24bc
+#define      MVNETA_FORCE_UNI                    BIT(21)
+#define MVNETA_TXQ_CMD_1                         0x24e4
+#define MVNETA_TXQ_CMD                           0x2448
+#define      MVNETA_TXQ_DISABLE_SHIFT            8
+#define      MVNETA_TXQ_ENABLE_MASK              0x000000ff
+#define MVNETA_ACC_MODE                          0x2500
+#define MVNETA_CPU_MAP(cpu)                      (0x2540 + ((cpu) << 2))
+#define      MVNETA_CPU_RXQ_ACCESS_ALL_MASK      0x000000ff
+#define      MVNETA_CPU_TXQ_ACCESS_ALL_MASK      0x0000ff00
+#define MVNETA_RXQ_TIME_COAL_REG(q)              (0x2580 + ((q) << 2))
+
+/* Exception Interrupt Port/Queue Cause register */
+
+#define MVNETA_INTR_NEW_CAUSE                    0x25a0
+#define MVNETA_INTR_NEW_MASK                     0x25a4
+
+/* bits  0..7  = TXQ SENT, one bit per queue.
+ * bits  8..15 = RXQ OCCUP, one bit per queue.
+ * bits 16..23 = RXQ FREE, one bit per queue.
+ * bit  29 = OLD_REG_SUM, see old reg ?
+ * bit  30 = TX_ERR_SUM, one bit for 4 ports
+ * bit  31 = MISC_SUM,   one bit for 4 ports
+ */
+#define      MVNETA_TX_INTR_MASK(nr_txqs)        (((1 << nr_txqs) - 1) << 0)
+#define      MVNETA_TX_INTR_MASK_ALL             (0xff << 0)
+#define      MVNETA_RX_INTR_MASK(nr_rxqs)        (((1 << nr_rxqs) - 1) << 8)
+#define      MVNETA_RX_INTR_MASK_ALL             (0xff << 8)
+
+#define MVNETA_INTR_OLD_CAUSE                    0x25a8
+#define MVNETA_INTR_OLD_MASK                     0x25ac
+
+/* Data Path Port/Queue Cause Register */
+#define MVNETA_INTR_MISC_CAUSE                   0x25b0
+#define MVNETA_INTR_MISC_MASK                    0x25b4
+#define MVNETA_INTR_ENABLE                       0x25b8
+
+#define MVNETA_RXQ_CMD                           0x2680
+#define      MVNETA_RXQ_DISABLE_SHIFT            8
+#define      MVNETA_RXQ_ENABLE_MASK              0x000000ff
+#define MVETH_TXQ_TOKEN_COUNT_REG(q)             (0x2700 + ((q) << 4))
+#define MVETH_TXQ_TOKEN_CFG_REG(q)               (0x2704 + ((q) << 4))
+#define MVNETA_GMAC_CTRL_0                       0x2c00
+#define      MVNETA_GMAC_MAX_RX_SIZE_SHIFT       2
+#define      MVNETA_GMAC_MAX_RX_SIZE_MASK        0x7ffc
+#define      MVNETA_GMAC0_PORT_ENABLE            BIT(0)
+#define MVNETA_GMAC_CTRL_2                       0x2c08
+#define      MVNETA_GMAC2_PCS_ENABLE             BIT(3)
+#define      MVNETA_GMAC2_PORT_RGMII             BIT(4)
+#define      MVNETA_GMAC2_PORT_RESET             BIT(6)
+#define MVNETA_GMAC_STATUS                       0x2c10
+#define      MVNETA_GMAC_LINK_UP                 BIT(0)
+#define      MVNETA_GMAC_SPEED_1000              BIT(1)
+#define      MVNETA_GMAC_SPEED_100               BIT(2)
+#define      MVNETA_GMAC_FULL_DUPLEX             BIT(3)
+#define      MVNETA_GMAC_RX_FLOW_CTRL_ENABLE     BIT(4)
+#define      MVNETA_GMAC_TX_FLOW_CTRL_ENABLE     BIT(5)
+#define      MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE     BIT(6)
+#define      MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE     BIT(7)
+#define MVNETA_GMAC_AUTONEG_CONFIG               0x2c0c
+#define      MVNETA_GMAC_FORCE_LINK_DOWN         BIT(0)
+#define      MVNETA_GMAC_FORCE_LINK_PASS         BIT(1)
+#define      MVNETA_GMAC_CONFIG_MII_SPEED        BIT(5)
+#define      MVNETA_GMAC_CONFIG_GMII_SPEED       BIT(6)
+#define      MVNETA_GMAC_AN_SPEED_EN             BIT(7)
+#define      MVNETA_GMAC_CONFIG_FULL_DUPLEX      BIT(12)
+#define      MVNETA_GMAC_AN_DUPLEX_EN            BIT(13)
+#define MVNETA_MIB_COUNTERS_BASE                 0x3080
+#define      MVNETA_MIB_LATE_COLLISION           0x7c
+#define MVNETA_DA_FILT_SPEC_MCAST                0x3400
+#define MVNETA_DA_FILT_OTH_MCAST                 0x3500
+#define MVNETA_DA_FILT_UCAST_BASE                0x3600
+#define MVNETA_TXQ_BASE_ADDR_REG(q)              (0x3c00 + ((q) << 2))
+#define MVNETA_TXQ_SIZE_REG(q)                   (0x3c20 + ((q) << 2))
+#define      MVNETA_TXQ_SENT_THRESH_ALL_MASK     0x3fff0000
+#define      MVNETA_TXQ_SENT_THRESH_MASK(coal)   ((coal) << 16)
+#define MVNETA_TXQ_UPDATE_REG(q)                 (0x3c60 + ((q) << 2))
+#define      MVNETA_TXQ_DEC_SENT_SHIFT           16
+#define MVNETA_TXQ_STATUS_REG(q)                 (0x3c40 + ((q) << 2))
+#define      MVNETA_TXQ_SENT_DESC_SHIFT          16
+#define      MVNETA_TXQ_SENT_DESC_MASK           0x3fff0000
+#define MVNETA_PORT_TX_RESET                     0x3cf0
+#define      MVNETA_PORT_TX_DMA_RESET            BIT(0)
+#define MVNETA_TX_MTU                            0x3e0c
+#define MVNETA_TX_TOKEN_SIZE                     0x3e14
+#define      MVNETA_TX_TOKEN_SIZE_MAX            0xffffffff
+#define MVNETA_TXQ_TOKEN_SIZE_REG(q)             (0x3e40 + ((q) << 2))
+#define      MVNETA_TXQ_TOKEN_SIZE_MAX           0x7fffffff
+
+/* Descriptor ring Macros */
+#define MVNETA_QUEUE_NEXT_DESC(q, index)	\
+	(((index) < (q)->last_desc) ? ((index) + 1) : 0)
+
+/* Various constants */
+
+/* Coalescing */
+#define MVNETA_TXDONE_COAL_PKTS		16
+#define MVNETA_RX_COAL_PKTS		32
+#define MVNETA_RX_COAL_USEC		100
+
+/* The two bytes Marvell header. Either contains a special value used
+ * by Marvell switches when a specific hardware mode is enabled (not
+ * supported by this driver) or is filled automatically by zeroes on
+ * the RX side. Those two bytes being at the front of the Ethernet
+ * header, they allow to have the IP header aligned on a 4 bytes
+ * boundary automatically: the hardware skips those two bytes on its
+ * own.
+ */
+#define MVNETA_MH_SIZE			2
+
+#define MVNETA_VLAN_TAG_LEN             4
+
+#define MVNETA_CPU_D_CACHE_LINE_SIZE    32
+#define MVNETA_TX_CSUM_MAX_SIZE		9800
+#define MVNETA_ACC_MODE_EXT		1
+
+/* Timeout constants */
+#define MVNETA_TX_DISABLE_TIMEOUT_MSEC	1000
+#define MVNETA_RX_DISABLE_TIMEOUT_MSEC	1000
+#define MVNETA_TX_FIFO_EMPTY_TIMEOUT	10000
+
+#define MVNETA_TX_MTU_MAX		0x3ffff
+
+/* Max number of Rx descriptors */
+#define MVNETA_MAX_RXD 16
+
+/* Max number of Tx descriptors */
+#define MVNETA_MAX_TXD 16
+
+/* descriptor aligned size */
+#define MVNETA_DESC_ALIGNED_SIZE	32
+
+struct mvneta_port {
+	void __iomem *base;
+	struct mvneta_rx_queue *rxqs;
+	struct mvneta_tx_queue *txqs;
+
+	u8 mcast_count[256];
+	u16 tx_ring_size;
+	u16 rx_ring_size;
+
+	phy_interface_t phy_interface;
+	unsigned int link;
+	unsigned int duplex;
+	unsigned int speed;
+
+	int init;
+	int phyaddr;
+	struct phy_device *phydev;
+	struct mii_dev *bus;
+};
+
+/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
+ * layout of the transmit and reception DMA descriptors, and their
+ * layout is therefore defined by the hardware design
+ */
+
+#define MVNETA_TX_L3_OFF_SHIFT	0
+#define MVNETA_TX_IP_HLEN_SHIFT	8
+#define MVNETA_TX_L4_UDP	BIT(16)
+#define MVNETA_TX_L3_IP6	BIT(17)
+#define MVNETA_TXD_IP_CSUM	BIT(18)
+#define MVNETA_TXD_Z_PAD	BIT(19)
+#define MVNETA_TXD_L_DESC	BIT(20)
+#define MVNETA_TXD_F_DESC	BIT(21)
+#define MVNETA_TXD_FLZ_DESC	(MVNETA_TXD_Z_PAD  | \
+				 MVNETA_TXD_L_DESC | \
+				 MVNETA_TXD_F_DESC)
+#define MVNETA_TX_L4_CSUM_FULL	BIT(30)
+#define MVNETA_TX_L4_CSUM_NOT	BIT(31)
+
+#define MVNETA_RXD_ERR_CRC		0x0
+#define MVNETA_RXD_ERR_SUMMARY		BIT(16)
+#define MVNETA_RXD_ERR_OVERRUN		BIT(17)
+#define MVNETA_RXD_ERR_LEN		BIT(18)
+#define MVNETA_RXD_ERR_RESOURCE		(BIT(17) | BIT(18))
+#define MVNETA_RXD_ERR_CODE_MASK	(BIT(17) | BIT(18))
+#define MVNETA_RXD_L3_IP4		BIT(25)
+#define MVNETA_RXD_FIRST_LAST_DESC	(BIT(26) | BIT(27))
+#define MVNETA_RXD_L4_CSUM_OK		BIT(30)
+
+struct mvneta_tx_desc {
+	u32  command;		/* Options used by HW for packet transmitting.*/
+	u16  reserverd1;	/* csum_l4 (for future use)		*/
+	u16  data_size;		/* Data size of transmitted packet in bytes */
+	u32  buf_phys_addr;	/* Physical addr of transmitted buffer	*/
+	u32  reserved2;		/* hw_cmd - (for future use, PMT)	*/
+	u32  reserved3[4];	/* Reserved - (for future use)		*/
+};
+
+struct mvneta_rx_desc {
+	u32  status;		/* Info about received packet		*/
+	u16  reserved1;		/* pnc_info - (for future use, PnC)	*/
+	u16  data_size;		/* Size of received packet in bytes	*/
+
+	u32  buf_phys_addr;	/* Physical address of the buffer	*/
+	u32  reserved2;		/* pnc_flow_id  (for future use, PnC)	*/
+
+	u32  buf_cookie;	/* cookie for access to RX buffer in rx path */
+	u16  reserved3;		/* prefetch_cmd, for future use		*/
+	u16  reserved4;		/* csum_l4 - (for future use, PnC)	*/
+
+	u32  reserved5;		/* pnc_extra PnC (for future use, PnC)	*/
+	u32  reserved6;		/* hw_cmd (for future use, PnC and HWF)	*/
+};
+
+struct mvneta_tx_queue {
+	/* Number of this TX queue, in the range 0-7 */
+	u8 id;
+
+	/* Number of TX DMA descriptors in the descriptor ring */
+	int size;
+
+	/* Index of last TX DMA descriptor that was inserted */
+	int txq_put_index;
+
+	/* Index of the TX DMA descriptor to be cleaned up */
+	int txq_get_index;
+
+	/* Virtual address of the TX DMA descriptors array */
+	struct mvneta_tx_desc *descs;
+
+	/* DMA address of the TX DMA descriptors array */
+	dma_addr_t descs_phys;
+
+	/* Index of the last TX DMA descriptor */
+	int last_desc;
+
+	/* Index of the next TX DMA descriptor to process */
+	int next_desc_to_proc;
+};
+
+struct mvneta_rx_queue {
+	/* rx queue number, in the range 0-7 */
+	u8 id;
+
+	/* num of rx descriptors in the rx descriptor ring */
+	int size;
+
+	/* Virtual address of the RX DMA descriptors array */
+	struct mvneta_rx_desc *descs;
+
+	/* DMA address of the RX DMA descriptors array */
+	dma_addr_t descs_phys;
+
+	/* Index of the last RX DMA descriptor */
+	int last_desc;
+
+	/* Index of the next RX DMA descriptor to process */
+	int next_desc_to_proc;
+};
+
+/* U-Boot doesn't use the queues, so set the number to 1 */
+static int rxq_number = 1;
+static int txq_number = 1;
+static int rxq_def;
+
+struct buffer_location {
+	struct mvneta_tx_desc *tx_descs;
+	struct mvneta_rx_desc *rx_descs;
+	u32 rx_buffers;
+};
+
+/*
+ * All 4 interfaces use the same global buffer, since only one interface
+ * can be enabled at once
+ */
+static struct buffer_location buffer_loc;
+
+/*
+ * Page table entries are set to 1MB, or multiples of 1MB
+ * (not < 1MB). driver uses less bd's so use 1MB bdspace.
+ */
+#define BD_SPACE	(1 << 20)
+
+/* Utility/helper methods */
+
+/* Write helper method */
+static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
+{
+	writel(data, pp->base + offset);
+}
+
+/* Read helper method */
+static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
+{
+	return readl(pp->base + offset);
+}
+
+/* Clear all MIB counters */
+static void mvneta_mib_counters_clear(struct mvneta_port *pp)
+{
+	int i;
+
+	/* Perform dummy reads from MIB counters */
+	for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
+		mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
+}
+
+/* Rx descriptors helper methods */
+
+/* Checks whether the RX descriptor having this status is both the first
+ * and the last descriptor for the RX packet. Each RX packet is currently
+ * received through a single RX descriptor, so not having each RX
+ * descriptor with its first and last bits set is an error
+ */
+static int mvneta_rxq_desc_is_first_last(u32 status)
+{
+	return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
+		MVNETA_RXD_FIRST_LAST_DESC;
+}
+
+/* Add number of descriptors ready to receive new packets */
+static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
+					  struct mvneta_rx_queue *rxq,
+					  int ndescs)
+{
+	/* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
+	 * be added at once
+	 */
+	while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
+		mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
+			    (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
+			     MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
+		ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
+	}
+
+	mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
+		    (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
+}
+
+/* Get number of RX descriptors occupied by received packets */
+static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
+					struct mvneta_rx_queue *rxq)
+{
+	u32 val;
+
+	val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
+	return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
+}
+
+/* Update num of rx desc called upon return from rx path or
+ * from mvneta_rxq_drop_pkts().
+ */
+static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
+				       struct mvneta_rx_queue *rxq,
+				       int rx_done, int rx_filled)
+{
+	u32 val;
+
+	if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
+		val = rx_done |
+		  (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
+		mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
+		return;
+	}
+
+	/* Only 255 descriptors can be added at once */
+	while ((rx_done > 0) || (rx_filled > 0)) {
+		if (rx_done <= 0xff) {
+			val = rx_done;
+			rx_done = 0;
+		} else {
+			val = 0xff;
+			rx_done -= 0xff;
+		}
+		if (rx_filled <= 0xff) {
+			val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
+			rx_filled = 0;
+		} else {
+			val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
+			rx_filled -= 0xff;
+		}
+		mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
+	}
+}
+
+/* Get pointer to next RX descriptor to be processed by SW */
+static struct mvneta_rx_desc *
+mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
+{
+	int rx_desc = rxq->next_desc_to_proc;
+
+	rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
+	return rxq->descs + rx_desc;
+}
+
+/* Tx descriptors helper methods */
+
+/* Update HW with number of TX descriptors to be sent */
+static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
+				     struct mvneta_tx_queue *txq,
+				     int pend_desc)
+{
+	u32 val;
+
+	/* Only 255 descriptors can be added at once ; Assume caller
+	 * process TX desriptors in quanta less than 256
+	 */
+	val = pend_desc;
+	mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
+}
+
+/* Get pointer to next TX descriptor to be processed (send) by HW */
+static struct mvneta_tx_desc *
+mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
+{
+	int tx_desc = txq->next_desc_to_proc;
+
+	txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
+	return txq->descs + tx_desc;
+}
+
+/* Set rxq buf size */
+static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
+				    struct mvneta_rx_queue *rxq,
+				    int buf_size)
+{
+	u32 val;
+
+	val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
+
+	val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
+	val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
+
+	mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
+}
+
+/* Start the Ethernet port RX and TX activity */
+static void mvneta_port_up(struct mvneta_port *pp)
+{
+	int queue;
+	u32 q_map;
+
+	/* Enable all initialized TXs. */
+	mvneta_mib_counters_clear(pp);
+	q_map = 0;
+	for (queue = 0; queue < txq_number; queue++) {
+		struct mvneta_tx_queue *txq = &pp->txqs[queue];
+		if (txq->descs != NULL)
+			q_map |= (1 << queue);
+	}
+	mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
+
+	/* Enable all initialized RXQs. */
+	q_map = 0;
+	for (queue = 0; queue < rxq_number; queue++) {
+		struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
+		if (rxq->descs != NULL)
+			q_map |= (1 << queue);
+	}
+	mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
+}
+
+/* Stop the Ethernet port activity */
+static void mvneta_port_down(struct mvneta_port *pp)
+{
+	u32 val;
+	int count;
+
+	/* Stop Rx port activity. Check port Rx activity. */
+	val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
+
+	/* Issue stop command for active channels only */
+	if (val != 0)
+		mvreg_write(pp, MVNETA_RXQ_CMD,
+			    val << MVNETA_RXQ_DISABLE_SHIFT);
+
+	/* Wait for all Rx activity to terminate. */
+	count = 0;
+	do {
+		if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
+			netdev_warn(pp->dev,
+				    "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
+				    val);
+			break;
+		}
+		mdelay(1);
+
+		val = mvreg_read(pp, MVNETA_RXQ_CMD);
+	} while (val & 0xff);
+
+	/* Stop Tx port activity. Check port Tx activity. Issue stop
+	 * command for active channels only
+	 */
+	val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
+
+	if (val != 0)
+		mvreg_write(pp, MVNETA_TXQ_CMD,
+			    (val << MVNETA_TXQ_DISABLE_SHIFT));
+
+	/* Wait for all Tx activity to terminate. */
+	count = 0;
+	do {
+		if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
+			netdev_warn(pp->dev,
+				    "TIMEOUT for TX stopped status=0x%08x\n",
+				    val);
+			break;
+		}
+		mdelay(1);
+
+		/* Check TX Command reg that all Txqs are stopped */
+		val = mvreg_read(pp, MVNETA_TXQ_CMD);
+
+	} while (val & 0xff);
+
+	/* Double check to verify that TX FIFO is empty */
+	count = 0;
+	do {
+		if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
+			netdev_warn(pp->dev,
+				    "TX FIFO empty timeout status=0x08%x\n",
+				    val);
+			break;
+		}
+		mdelay(1);
+
+		val = mvreg_read(pp, MVNETA_PORT_STATUS);
+	} while (!(val & MVNETA_TX_FIFO_EMPTY) &&
+		 (val & MVNETA_TX_IN_PRGRS));
+
+	udelay(200);
+}
+
+/* Enable the port by setting the port enable bit of the MAC control register */
+static void mvneta_port_enable(struct mvneta_port *pp)
+{
+	u32 val;
+
+	/* Enable port */
+	val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
+	val |= MVNETA_GMAC0_PORT_ENABLE;
+	mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
+}
+
+/* Disable the port and wait for about 200 usec before retuning */
+static void mvneta_port_disable(struct mvneta_port *pp)
+{
+	u32 val;
+
+	/* Reset the Enable bit in the Serial Control Register */
+	val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
+	val &= ~MVNETA_GMAC0_PORT_ENABLE;
+	mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
+
+	udelay(200);
+}
+
+/* Multicast tables methods */
+
+/* Set all entries in Unicast MAC Table; queue==-1 means reject all */
+static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
+{
+	int offset;
+	u32 val;
+
+	if (queue == -1) {
+		val = 0;
+	} else {
+		val = 0x1 | (queue << 1);
+		val |= (val << 24) | (val << 16) | (val << 8);
+	}
+
+	for (offset = 0; offset <= 0xc; offset += 4)
+		mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
+}
+
+/* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
+static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
+{
+	int offset;
+	u32 val;
+
+	if (queue == -1) {
+		val = 0;
+	} else {
+		val = 0x1 | (queue << 1);
+		val |= (val << 24) | (val << 16) | (val << 8);
+	}
+
+	for (offset = 0; offset <= 0xfc; offset += 4)
+		mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
+}
+
+/* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
+static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
+{
+	int offset;
+	u32 val;
+
+	if (queue == -1) {
+		memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
+		val = 0;
+	} else {
+		memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
+		val = 0x1 | (queue << 1);
+		val |= (val << 24) | (val << 16) | (val << 8);
+	}
+
+	for (offset = 0; offset <= 0xfc; offset += 4)
+		mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
+}
+
+/* This method sets defaults to the NETA port:
+ *	Clears interrupt Cause and Mask registers.
+ *	Clears all MAC tables.
+ *	Sets defaults to all registers.
+ *	Resets RX and TX descriptor rings.
+ *	Resets PHY.
+ * This method can be called after mvneta_port_down() to return the port
+ *	settings to defaults.
+ */
+static void mvneta_defaults_set(struct mvneta_port *pp)
+{
+	int cpu;
+	int queue;
+	u32 val;
+
+	/* Clear all Cause registers */
+	mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
+	mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
+	mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
+
+	/* Mask all interrupts */
+	mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
+	mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
+	mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
+	mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
+
+	/* Enable MBUS Retry bit16 */
+	mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
+
+	/* Set CPU queue access map - all CPUs have access to all RX
+	 * queues and to all TX queues
+	 */
+	for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
+		mvreg_write(pp, MVNETA_CPU_MAP(cpu),
+			    (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
+			     MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
+
+	/* Reset RX and TX DMAs */
+	mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
+	mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
+
+	/* Disable Legacy WRR, Disable EJP, Release from reset */
+	mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
+	for (queue = 0; queue < txq_number; queue++) {
+		mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
+		mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
+	}
+
+	mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
+	mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
+
+	/* Set Port Acceleration Mode */
+	val = MVNETA_ACC_MODE_EXT;
+	mvreg_write(pp, MVNETA_ACC_MODE, val);
+
+	/* Update val of portCfg register accordingly with all RxQueue types */
+	val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
+	mvreg_write(pp, MVNETA_PORT_CONFIG, val);
+
+	val = 0;
+	mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
+	mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
+
+	/* Build PORT_SDMA_CONFIG_REG */
+	val = 0;
+
+	/* Default burst size */
+	val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
+	val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
+	val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
+
+	/* Assign port SDMA configuration */
+	mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
+
+	/* Enable PHY polling in hardware for U-Boot */
+	val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
+	val |= MVNETA_PHY_POLLING_ENABLE;
+	mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
+
+	mvneta_set_ucast_table(pp, -1);
+	mvneta_set_special_mcast_table(pp, -1);
+	mvneta_set_other_mcast_table(pp, -1);
+}
+
+/* Set unicast address */
+static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
+				  int queue)
+{
+	unsigned int unicast_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the Unicast table entry */
+	last_nibble = (0xf & last_nibble);
+
+	/* offset from unicast tbl base */
+	tbl_offset = (last_nibble / 4) * 4;
+
+	/* offset within the above reg  */
+	reg_offset = last_nibble % 4;
+
+	unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
+
+	if (queue == -1) {
+		/* Clear accepts frame bit at specified unicast DA tbl entry */
+		unicast_reg &= ~(0xff << (8 * reg_offset));
+	} else {
+		unicast_reg &= ~(0xff << (8 * reg_offset));
+		unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
+	}
+
+	mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
+}
+
+/* Set mac address */
+static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
+				int queue)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+
+	if (queue != -1) {
+		mac_l = (addr[4] << 8) | (addr[5]);
+		mac_h = (addr[0] << 24) | (addr[1] << 16) |
+			(addr[2] << 8) | (addr[3] << 0);
+
+		mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
+		mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
+	}
+
+	/* Accept frames of this address */
+	mvneta_set_ucast_addr(pp, addr[5], queue);
+}
+
+/* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
+static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
+				u32 phys_addr, u32 cookie)
+{
+	rx_desc->buf_cookie = cookie;
+	rx_desc->buf_phys_addr = phys_addr;
+}
+
+/* Decrement sent descriptors counter */
+static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
+				     struct mvneta_tx_queue *txq,
+				     int sent_desc)
+{
+	u32 val;
+
+	/* Only 255 TX descriptors can be updated at once */
+	while (sent_desc > 0xff) {
+		val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
+		mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
+		sent_desc = sent_desc - 0xff;
+	}
+
+	val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
+	mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
+}
+
+/* Get number of TX descriptors already sent by HW */
+static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
+					struct mvneta_tx_queue *txq)
+{
+	u32 val;
+	int sent_desc;
+
+	val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
+	sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
+		MVNETA_TXQ_SENT_DESC_SHIFT;
+
+	return sent_desc;
+}
+
+/* Display more error info */
+static void mvneta_rx_error(struct mvneta_port *pp,
+			    struct mvneta_rx_desc *rx_desc)
+{
+	u32 status = rx_desc->status;
+
+	if (!mvneta_rxq_desc_is_first_last(status)) {
+		netdev_err(pp->dev,
+			   "bad rx status %08x (buffer oversize), size=%d\n",
+			   status, rx_desc->data_size);
+		return;
+	}
+
+	switch (status & MVNETA_RXD_ERR_CODE_MASK) {
+	case MVNETA_RXD_ERR_CRC:
+		netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
+			   status, rx_desc->data_size);
+		break;
+	case MVNETA_RXD_ERR_OVERRUN:
+		netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
+			   status, rx_desc->data_size);
+		break;
+	case MVNETA_RXD_ERR_LEN:
+		netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
+			   status, rx_desc->data_size);
+		break;
+	case MVNETA_RXD_ERR_RESOURCE:
+		netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
+			   status, rx_desc->data_size);
+		break;
+	}
+}
+
+static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp,
+						     int rxq)
+{
+	return &pp->rxqs[rxq];
+}
+
+
+/* Drop packets received by the RXQ and free buffers */
+static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
+				 struct mvneta_rx_queue *rxq)
+{
+	int rx_done;
+
+	rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
+	if (rx_done)
+		mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
+}
+
+/* Handle rxq fill: allocates rxq skbs; called when initializing a port */
+static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
+			   int num)
+{
+	int i;
+
+	for (i = 0; i < num; i++) {
+		u32 addr;
+
+		/* U-Boot special: Fill in the rx buffer addresses */
+		addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE);
+		mvneta_rx_desc_fill(rxq->descs + i, addr, addr);
+	}
+
+	/* Add this number of RX descriptors as non occupied (ready to
+	 * get packets)
+	 */
+	mvneta_rxq_non_occup_desc_add(pp, rxq, i);
+
+	return 0;
+}
+
+/* Rx/Tx queue initialization/cleanup methods */
+
+/* Create a specified RX queue */
+static int mvneta_rxq_init(struct mvneta_port *pp,
+			   struct mvneta_rx_queue *rxq)
+
+{
+	rxq->size = pp->rx_ring_size;
+
+	/* Allocate memory for RX descriptors */
+	rxq->descs_phys = (dma_addr_t)rxq->descs;
+	if (rxq->descs == NULL)
+		return -ENOMEM;
+
+	rxq->last_desc = rxq->size - 1;
+
+	/* Set Rx descriptors queue starting address */
+	mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
+	mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
+
+	/* Fill RXQ with buffers from RX pool */
+	mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE);
+	mvneta_rxq_fill(pp, rxq, rxq->size);
+
+	return 0;
+}
+
+/* Cleanup Rx queue */
+static void mvneta_rxq_deinit(struct mvneta_port *pp,
+			      struct mvneta_rx_queue *rxq)
+{
+	mvneta_rxq_drop_pkts(pp, rxq);
+
+	rxq->descs             = NULL;
+	rxq->last_desc         = 0;
+	rxq->next_desc_to_proc = 0;
+	rxq->descs_phys        = 0;
+}
+
+/* Create and initialize a tx queue */
+static int mvneta_txq_init(struct mvneta_port *pp,
+			   struct mvneta_tx_queue *txq)
+{
+	txq->size = pp->tx_ring_size;
+
+	/* Allocate memory for TX descriptors */
+	txq->descs_phys = (u32)txq->descs;
+	if (txq->descs == NULL)
+		return -ENOMEM;
+
+	txq->last_desc = txq->size - 1;
+
+	/* Set maximum bandwidth for enabled TXQs */
+	mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
+	mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
+
+	/* Set Tx descriptors queue starting address */
+	mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
+	mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
+
+	return 0;
+}
+
+/* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
+static void mvneta_txq_deinit(struct mvneta_port *pp,
+			      struct mvneta_tx_queue *txq)
+{
+	txq->descs             = NULL;
+	txq->last_desc         = 0;
+	txq->next_desc_to_proc = 0;
+	txq->descs_phys        = 0;
+
+	/* Set minimum bandwidth for disabled TXQs */
+	mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
+	mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
+
+	/* Set Tx descriptors queue starting address and size */
+	mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
+	mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
+}
+
+/* Cleanup all Tx queues */
+static void mvneta_cleanup_txqs(struct mvneta_port *pp)
+{
+	int queue;
+
+	for (queue = 0; queue < txq_number; queue++)
+		mvneta_txq_deinit(pp, &pp->txqs[queue]);
+}
+
+/* Cleanup all Rx queues */
+static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
+{
+	int queue;
+
+	for (queue = 0; queue < rxq_number; queue++)
+		mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
+}
+
+
+/* Init all Rx queues */
+static int mvneta_setup_rxqs(struct mvneta_port *pp)
+{
+	int queue;
+
+	for (queue = 0; queue < rxq_number; queue++) {
+		int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
+		if (err) {
+			netdev_err(pp->dev, "%s: can't create rxq=%d\n",
+				   __func__, queue);
+			mvneta_cleanup_rxqs(pp);
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+/* Init all tx queues */
+static int mvneta_setup_txqs(struct mvneta_port *pp)
+{
+	int queue;
+
+	for (queue = 0; queue < txq_number; queue++) {
+		int err = mvneta_txq_init(pp, &pp->txqs[queue]);
+		if (err) {
+			netdev_err(pp->dev, "%s: can't create txq=%d\n",
+				   __func__, queue);
+			mvneta_cleanup_txqs(pp);
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+static void mvneta_start_dev(struct mvneta_port *pp)
+{
+	/* start the Rx/Tx activity */
+	mvneta_port_enable(pp);
+}
+
+static void mvneta_adjust_link(struct eth_device *dev)
+{
+	struct mvneta_port *pp = dev->priv;
+	struct phy_device *phydev = pp->phydev;
+	int status_change = 0;
+
+	if (phydev->link) {
+		if ((pp->speed != phydev->speed) ||
+		    (pp->duplex != phydev->duplex)) {
+			u32 val;
+
+			val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
+			val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
+				 MVNETA_GMAC_CONFIG_GMII_SPEED |
+				 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
+				 MVNETA_GMAC_AN_SPEED_EN |
+				 MVNETA_GMAC_AN_DUPLEX_EN);
+
+			if (phydev->duplex)
+				val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
+
+			if (phydev->speed == SPEED_1000)
+				val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
+			else
+				val |= MVNETA_GMAC_CONFIG_MII_SPEED;
+
+			mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
+
+			pp->duplex = phydev->duplex;
+			pp->speed  = phydev->speed;
+		}
+	}
+
+	if (phydev->link != pp->link) {
+		if (!phydev->link) {
+			pp->duplex = -1;
+			pp->speed = 0;
+		}
+
+		pp->link = phydev->link;
+		status_change = 1;
+	}
+
+	if (status_change) {
+		if (phydev->link) {
+			u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
+			val |= (MVNETA_GMAC_FORCE_LINK_PASS |
+				MVNETA_GMAC_FORCE_LINK_DOWN);
+			mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
+			mvneta_port_up(pp);
+		} else {
+			mvneta_port_down(pp);
+		}
+	}
+}
+
+static int mvneta_open(struct eth_device *dev)
+{
+	struct mvneta_port *pp = dev->priv;
+	int ret;
+
+	ret = mvneta_setup_rxqs(pp);
+	if (ret)
+		return ret;
+
+	ret = mvneta_setup_txqs(pp);
+	if (ret)
+		return ret;
+
+	mvneta_adjust_link(dev);
+
+	mvneta_start_dev(pp);
+
+	return 0;
+}
+
+/* Initialize hw */
+static int mvneta_init(struct mvneta_port *pp)
+{
+	int queue;
+
+	/* Disable port */
+	mvneta_port_disable(pp);
+
+	/* Set port default values */
+	mvneta_defaults_set(pp);
+
+	pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
+			   GFP_KERNEL);
+	if (!pp->txqs)
+		return -ENOMEM;
+
+	/* U-Boot special: use preallocated area */
+	pp->txqs[0].descs = buffer_loc.tx_descs;
+
+	/* Initialize TX descriptor rings */
+	for (queue = 0; queue < txq_number; queue++) {
+		struct mvneta_tx_queue *txq = &pp->txqs[queue];
+		txq->id = queue;
+		txq->size = pp->tx_ring_size;
+	}
+
+	pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
+			   GFP_KERNEL);
+	if (!pp->rxqs) {
+		kfree(pp->txqs);
+		return -ENOMEM;
+	}
+
+	/* U-Boot special: use preallocated area */
+	pp->rxqs[0].descs = buffer_loc.rx_descs;
+
+	/* Create Rx descriptor rings */
+	for (queue = 0; queue < rxq_number; queue++) {
+		struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
+		rxq->id = queue;
+		rxq->size = pp->rx_ring_size;
+	}
+
+	return 0;
+}
+
+/* platform glue : initialize decoding windows */
+static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
+{
+	const struct mbus_dram_target_info *dram;
+	u32 win_enable;
+	u32 win_protect;
+	int i;
+
+	dram = mvebu_mbus_dram_info();
+	for (i = 0; i < 6; i++) {
+		mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
+		mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
+
+		if (i < 4)
+			mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
+	}
+
+	win_enable = 0x3f;
+	win_protect = 0;
+
+	for (i = 0; i < dram->num_cs; i++) {
+		const struct mbus_dram_window *cs = dram->cs + i;
+		mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
+			    (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
+
+		mvreg_write(pp, MVNETA_WIN_SIZE(i),
+			    (cs->size - 1) & 0xffff0000);
+
+		win_enable &= ~(1 << i);
+		win_protect |= 3 << (2 * i);
+	}
+
+	mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
+}
+
+/* Power up the port */
+static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
+{
+	u32 ctrl;
+
+	/* MAC Cause register should be cleared */
+	mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
+
+	ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
+
+	/* Even though it might look weird, when we're configured in
+	 * SGMII or QSGMII mode, the RGMII bit needs to be set.
+	 */
+	switch (phy_mode) {
+	case PHY_INTERFACE_MODE_QSGMII:
+		mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
+		ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
+		break;
+	case PHY_INTERFACE_MODE_SGMII:
+		mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
+		ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
+		break;
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+		ctrl |= MVNETA_GMAC2_PORT_RGMII;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Cancel Port Reset */
+	ctrl &= ~MVNETA_GMAC2_PORT_RESET;
+	mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
+
+	while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
+		MVNETA_GMAC2_PORT_RESET) != 0)
+		continue;
+
+	return 0;
+}
+
+/* Device initialization routine */
+static int mvneta_probe(struct eth_device *dev)
+{
+	struct mvneta_port *pp = dev->priv;
+	int err;
+
+	pp->tx_ring_size = MVNETA_MAX_TXD;
+	pp->rx_ring_size = MVNETA_MAX_RXD;
+
+	err = mvneta_init(pp);
+	if (err < 0) {
+		dev_err(&pdev->dev, "can't init eth hal\n");
+		return err;
+	}
+
+	mvneta_conf_mbus_windows(pp);
+
+	mvneta_mac_addr_set(pp, dev->enetaddr, rxq_def);
+
+	err = mvneta_port_power_up(pp, pp->phy_interface);
+	if (err < 0) {
+		dev_err(&pdev->dev, "can't power up port\n");
+		return err;
+	}
+
+	/* Call open() now as it needs to be done before runing send() */
+	mvneta_open(dev);
+
+	return 0;
+}
+
+/* U-Boot only functions follow here */
+
+/* SMI / MDIO functions */
+
+static int smi_wait_ready(struct mvneta_port *pp)
+{
+	u32 timeout = MVNETA_SMI_TIMEOUT;
+	u32 smi_reg;
+
+	/* wait till the SMI is not busy */
+	do {
+		/* read smi register */
+		smi_reg = mvreg_read(pp, MVNETA_SMI);
+		if (timeout-- == 0) {
+			printf("Error: SMI busy timeout\n");
+			return -EFAULT;
+		}
+	} while (smi_reg & MVNETA_SMI_BUSY);
+
+	return 0;
+}
+
+/*
+ * smi_reg_read - miiphy_read callback function.
+ *
+ * Returns 16bit phy register value, or 0xffff on error
+ */
+static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data)
+{
+	struct eth_device *dev = eth_get_dev_by_name(devname);
+	struct mvneta_port *pp = dev->priv;
+	u32 smi_reg;
+	u32 timeout;
+
+	/* check parameters */
+	if (phy_adr > MVNETA_PHY_ADDR_MASK) {
+		printf("Error: Invalid PHY address %d\n", phy_adr);
+		return -EFAULT;
+	}
+
+	if (reg_ofs > MVNETA_PHY_REG_MASK) {
+		printf("Err: Invalid register offset %d\n", reg_ofs);
+		return -EFAULT;
+	}
+
+	/* wait till the SMI is not busy */
+	if (smi_wait_ready(pp) < 0)
+		return -EFAULT;
+
+	/* fill the phy address and regiser offset and read opcode */
+	smi_reg = (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS)
+		| (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS)
+		| MVNETA_SMI_OPCODE_READ;
+
+	/* write the smi register */
+	mvreg_write(pp, MVNETA_SMI, smi_reg);
+
+	/*wait till read value is ready */
+	timeout = MVNETA_SMI_TIMEOUT;
+
+	do {
+		/* read smi register */
+		smi_reg = mvreg_read(pp, MVNETA_SMI);
+		if (timeout-- == 0) {
+			printf("Err: SMI read ready timeout\n");
+			return -EFAULT;
+		}
+	} while (!(smi_reg & MVNETA_SMI_READ_VALID));
+
+	/* Wait for the data to update in the SMI register */
+	for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++)
+		;
+
+	*data = (u16)(mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK);
+
+	return 0;
+}
+
+/*
+ * smi_reg_write - imiiphy_write callback function.
+ *
+ * Returns 0 if write succeed, -EINVAL on bad parameters
+ * -ETIME on timeout
+ */
+static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
+{
+	struct eth_device *dev = eth_get_dev_by_name(devname);
+	struct mvneta_port *pp = dev->priv;
+	u32 smi_reg;
+
+	/* check parameters */
+	if (phy_adr > MVNETA_PHY_ADDR_MASK) {
+		printf("Error: Invalid PHY address %d\n", phy_adr);
+		return -EFAULT;
+	}
+
+	if (reg_ofs > MVNETA_PHY_REG_MASK) {
+		printf("Err: Invalid register offset %d\n", reg_ofs);
+		return -EFAULT;
+	}
+
+	/* wait till the SMI is not busy */
+	if (smi_wait_ready(pp) < 0)
+		return -EFAULT;
+
+	/* fill the phy addr and reg offset and write opcode and data */
+	smi_reg = (data << MVNETA_SMI_DATA_OFFS);
+	smi_reg |= (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS)
+		| (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS);
+	smi_reg &= ~MVNETA_SMI_OPCODE_READ;
+
+	/* write the smi register */
+	mvreg_write(pp, MVNETA_SMI, smi_reg);
+
+	return 0;
+}
+
+static int mvneta_init_u_boot(struct eth_device *dev, bd_t *bis)
+{
+	struct mvneta_port *pp = dev->priv;
+	struct phy_device *phydev;
+
+	mvneta_port_power_up(pp, pp->phy_interface);
+
+	if (!pp->init || pp->link == 0) {
+		/* Set phy address of the port */
+		mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
+		phydev = phy_connect(pp->bus, pp->phyaddr, dev,
+				     pp->phy_interface);
+
+		pp->phydev = phydev;
+		phy_config(phydev);
+		phy_startup(phydev);
+		if (!phydev->link) {
+			printf("%s: No link.\n", phydev->dev->name);
+			return -1;
+		}
+
+		/* Full init on first call */
+		mvneta_probe(dev);
+		pp->init = 1;
+	} else {
+		/* Upon all following calls, this is enough */
+		mvneta_port_up(pp);
+		mvneta_port_enable(pp);
+	}
+
+	return 0;
+}
+
+static int mvneta_send(struct eth_device *dev, void *ptr, int len)
+{
+	struct mvneta_port *pp = dev->priv;
+	struct mvneta_tx_queue *txq = &pp->txqs[0];
+	struct mvneta_tx_desc *tx_desc;
+	int sent_desc;
+	u32 timeout = 0;
+
+	/* Get a descriptor for the first part of the packet */
+	tx_desc = mvneta_txq_next_desc_get(txq);
+
+	tx_desc->buf_phys_addr = (u32)ptr;
+	tx_desc->data_size = len;
+	flush_dcache_range((u32)ptr, (u32)ptr + len);
+
+	/* First and Last descriptor */
+	tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
+	mvneta_txq_pend_desc_add(pp, txq, 1);
+
+	/* Wait for packet to be sent (queue might help with speed here) */
+	sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
+	while (!sent_desc) {
+		if (timeout++ > 10000) {
+			printf("timeout: packet not sent\n");
+			return -1;
+		}
+		sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
+	}
+
+	/* txDone has increased - hw sent packet */
+	mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
+	return 0;
+
+	return 0;
+}
+
+static int mvneta_recv(struct eth_device *dev)
+{
+	struct mvneta_port *pp = dev->priv;
+	int rx_done;
+	int packets_done;
+	struct mvneta_rx_queue *rxq;
+
+	/* get rx queue */
+	rxq = mvneta_rxq_handle_get(pp, rxq_def);
+	rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
+	packets_done = rx_done;
+
+	while (packets_done--) {
+		struct mvneta_rx_desc *rx_desc;
+		unsigned char *data;
+		u32 rx_status;
+		int rx_bytes;
+
+		/*
+		 * No cache invalidation needed here, since the desc's are
+		 * located in a uncached memory region
+		 */
+		rx_desc = mvneta_rxq_next_desc_get(rxq);
+
+		rx_status = rx_desc->status;
+		if (!mvneta_rxq_desc_is_first_last(rx_status) ||
+		    (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
+			mvneta_rx_error(pp, rx_desc);
+			/* leave the descriptor untouched */
+			continue;
+		}
+
+		/* 2 bytes for marvell header. 4 bytes for crc */
+		rx_bytes = rx_desc->data_size - 6;
+
+		/* give packet to stack - skip on first 2 bytes */
+		data = (u8 *)rx_desc->buf_cookie + 2;
+		/*
+		 * No cache invalidation needed here, since the rx_buffer's are
+		 * located in a uncached memory region
+		 */
+		NetReceive(data, rx_bytes);
+	}
+
+	/* Update rxq management counters */
+	if (rx_done)
+		mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
+
+	return 0;
+}
+
+static void mvneta_halt(struct eth_device *dev)
+{
+	struct mvneta_port *pp = dev->priv;
+
+	mvneta_port_down(pp);
+	mvneta_port_disable(pp);
+}
+
+int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr)
+{
+	struct eth_device *dev;
+	struct mvneta_port *pp;
+	void *bd_space;
+
+	dev = calloc(1, sizeof(*dev));
+	if (dev == NULL)
+		return -ENOMEM;
+
+	pp = calloc(1, sizeof(*pp));
+	if (pp == NULL)
+		return -ENOMEM;
+
+	dev->priv = pp;
+
+	/*
+	 * Allocate buffer area for descs and rx_buffers. This is only
+	 * done once for all interfaces. As only one interface can
+	 * be active. Make this area DMA save by disabling the D-cache
+	 */
+	if (!buffer_loc.tx_descs) {
+		/* Align buffer area for descs and rx_buffers to 1MiB */
+		bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
+		mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE,
+						DCACHE_OFF);
+		buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
+		buffer_loc.rx_descs = (struct mvneta_rx_desc *)
+			((u32)bd_space +
+			 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc));
+		buffer_loc.rx_buffers = (u32)
+			(bd_space +
+			 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) +
+			 MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc));
+	}
+
+	sprintf(dev->name, "neta%d", devnum);
+
+	pp->base = (void __iomem *)base_addr;
+	dev->iobase = base_addr;
+	dev->init = mvneta_init_u_boot;
+	dev->halt = mvneta_halt;
+	dev->send = mvneta_send;
+	dev->recv = mvneta_recv;
+	dev->write_hwaddr = NULL;
+
+	/*
+	 * The PHY interface type is configured via the
+	 * board specific CONFIG_SYS_NETA_INTERFACE_TYPE
+	 * define.
+	 */
+	pp->phy_interface = CONFIG_SYS_NETA_INTERFACE_TYPE;
+
+	eth_register(dev);
+
+	pp->phyaddr = phy_addr;
+	miiphy_register(dev->name, smi_reg_read, smi_reg_write);
+	pp->bus = miiphy_get_dev_by_name(dev->name);
+
+	return 1;
+}
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 1d6c14f2ade..467c9722431 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -575,7 +575,7 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
  * Description: Reads the ID registers of the PHY at @addr on the
  *   @bus, stores it in @phy_id and returns zero on success.
  */
-int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
+static int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
 {
 	int phy_reg;
 
@@ -648,7 +648,7 @@ static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus,
 		if (phydev)
 			return phydev;
 	}
-	printf("Phy not found\n");
+	printf("Phy %d not found\n", ffs(phy_mask) - 1);
 	return phy_device_create(bus, ffs(phy_mask) - 1, 0xffffffff, interface);
 }
 
@@ -785,16 +785,13 @@ int phy_startup(struct phy_device *phydev)
 	return 0;
 }
 
-static int __board_phy_config(struct phy_device *phydev)
+__weak int board_phy_config(struct phy_device *phydev)
 {
 	if (phydev->drv->config)
 		return phydev->drv->config(phydev);
 	return 0;
 }
 
-int board_phy_config(struct phy_device *phydev)
-	__attribute__((weak, alias("__board_phy_config")));
-
 int phy_config(struct phy_device *phydev)
 {
 	/* Invoke an optional board-specific helper */
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 451c33e1a19..4bf493ed453 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -2,9 +2,9 @@
  * sh_eth.c - Driver for Renesas ethernet controler.
  *
  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
- * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
+ * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
- * Copyright (C) 2013  Renesas Electronics Corporation
+ * Copyright (C) 2013, 2014 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -83,6 +83,8 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len)
 	else
 		port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
 
+	flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
+
 	/* Restart the transmitter if disabled */
 	if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
 		sh_eth_write(eth, EDTRR_TRNS, EDTRR);
@@ -133,6 +135,10 @@ int sh_eth_recv(struct eth_device *dev)
 			port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
 		else
 			port_info->rx_desc_cur->rd0 = RD_RACT;
+
+		flush_cache_wback(port_info->rx_desc_cur,
+				  sizeof(struct rx_desc_s));
+
 		/* Point to the next descriptor */
 		port_info->rx_desc_cur++;
 		if (port_info->rx_desc_cur >=
@@ -181,27 +187,27 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 {
 	int port = eth->port, i, ret = 0;
-	u32 tmp_addr;
+	u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
 	struct sh_eth_info *port_info = &eth->port_info[port];
 	struct tx_desc_s *cur_tx_desc;
 
 	/*
-	 * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
+	 * Allocate rx descriptors. They must be aligned to size of struct
+	 * tx_desc_s.
 	 */
-	port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
-						 sizeof(struct tx_desc_s) +
-						 TX_DESC_SIZE - 1);
-	if (!port_info->tx_desc_malloc) {
-		printf(SHETHER_NAME ": malloc failed\n");
+	port_info->tx_desc_alloc =
+		memalign(sizeof(struct tx_desc_s), alloc_desc_size);
+	if (!port_info->tx_desc_alloc) {
+		printf(SHETHER_NAME ": memalign failed\n");
 		ret = -ENOMEM;
 		goto err;
 	}
 
-	tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
-			  ~(TX_DESC_SIZE - 1));
-	flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
+	flush_cache_wback((u32)port_info->tx_desc_alloc, alloc_desc_size);
+
 	/* Make sure we use a P2 address (non-cacheable) */
-	port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
+	port_info->tx_desc_base =
+		(struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
 	port_info->tx_desc_cur = port_info->tx_desc_base;
 
 	/* Initialize all descriptors */
@@ -232,47 +238,44 @@ err:
 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 {
 	int port = eth->port, i , ret = 0;
+	u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
 	struct sh_eth_info *port_info = &eth->port_info[port];
 	struct rx_desc_s *cur_rx_desc;
-	u32 tmp_addr;
 	u8 *rx_buf;
 
 	/*
-	 * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
+	 * Allocate rx descriptors. They must be aligned to size of struct
+	 * rx_desc_s.
 	 */
-	port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
-						 sizeof(struct rx_desc_s) +
-						 RX_DESC_SIZE - 1);
-	if (!port_info->rx_desc_malloc) {
-		printf(SHETHER_NAME ": malloc failed\n");
+	port_info->rx_desc_alloc =
+		memalign(sizeof(struct rx_desc_s), alloc_desc_size);
+	if (!port_info->rx_desc_alloc) {
+		printf(SHETHER_NAME ": memalign failed\n");
 		ret = -ENOMEM;
 		goto err;
 	}
 
-	tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
-			  ~(RX_DESC_SIZE - 1));
-	flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
+	flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
+
 	/* Make sure we use a P2 address (non-cacheable) */
-	port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
+	port_info->rx_desc_base =
+		(struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
 
 	port_info->rx_desc_cur = port_info->rx_desc_base;
 
 	/*
-	 * Allocate rx data buffers. They must be 32 bytes aligned  and in
-	 * P2 area
+	 * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
+	 * aligned and in P2 area.
 	 */
-	port_info->rx_buf_malloc = malloc(
-		NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1);
-	if (!port_info->rx_buf_malloc) {
-		printf(SHETHER_NAME ": malloc failed\n");
+	port_info->rx_buf_alloc =
+		memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
+	if (!port_info->rx_buf_alloc) {
+		printf(SHETHER_NAME ": alloc failed\n");
 		ret = -ENOMEM;
-		goto err_buf_malloc;
+		goto err_buf_alloc;
 	}
 
-	tmp_addr = (u32)(((int)port_info->rx_buf_malloc
-			  + (RX_BUF_ALIGNE_SIZE - 1)) &
-			  ~(RX_BUF_ALIGNE_SIZE - 1));
-	port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
+	port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
 
 	/* Initialize all descriptors */
 	for (cur_rx_desc = port_info->rx_desc_base,
@@ -297,9 +300,9 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 
 	return ret;
 
-err_buf_malloc:
-	free(port_info->rx_desc_malloc);
-	port_info->rx_desc_malloc = NULL;
+err_buf_alloc:
+	free(port_info->rx_desc_alloc);
+	port_info->rx_desc_alloc = NULL;
 
 err:
 	return ret;
@@ -310,9 +313,9 @@ static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
 	int port = eth->port;
 	struct sh_eth_info *port_info = &eth->port_info[port];
 
-	if (port_info->tx_desc_malloc) {
-		free(port_info->tx_desc_malloc);
-		port_info->tx_desc_malloc = NULL;
+	if (port_info->tx_desc_alloc) {
+		free(port_info->tx_desc_alloc);
+		port_info->tx_desc_alloc = NULL;
 	}
 }
 
@@ -321,14 +324,14 @@ static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
 	int port = eth->port;
 	struct sh_eth_info *port_info = &eth->port_info[port];
 
-	if (port_info->rx_desc_malloc) {
-		free(port_info->rx_desc_malloc);
-		port_info->rx_desc_malloc = NULL;
+	if (port_info->rx_desc_alloc) {
+		free(port_info->rx_desc_alloc);
+		port_info->rx_desc_alloc = NULL;
 	}
 
-	if (port_info->rx_buf_malloc) {
-		free(port_info->rx_buf_malloc);
-		port_info->rx_buf_malloc = NULL;
+	if (port_info->rx_buf_alloc) {
+		free(port_info->rx_buf_alloc);
+		port_info->rx_buf_alloc = NULL;
 	}
 }
 
@@ -414,7 +417,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 	sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
-	defined(CONFIG_R8A7794)
+	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 	sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
 #endif
 	/* Configure phy */
@@ -440,7 +443,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 		sh_eth_write(eth, 1, RTRATE);
 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
-		defined(CONFIG_R8A7791) || defined(CONFIG_R8A7794)
+		defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
+		defined(CONFIG_R8A7794)
 		val = ECMR_RTM;
 #endif
 	} else if (phy->speed == 10) {
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index e325a39aac0..5cb520c63ec 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -51,8 +51,6 @@
 /* The size of the tx descriptor is determined by how much padding is used.
    4, 20, or 52 bytes of padding can be used */
 #define TX_DESC_PADDING	(CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
-/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
-#define TX_DESC_SIZE	(12 + TX_DESC_PADDING)
 
 /* Tx descriptor. We always use 3 bytes of padding */
 struct tx_desc_s {
@@ -68,8 +66,6 @@ struct tx_desc_s {
 /* The size of the rx descriptor is determined by how much padding is used.
    4, 20, or 52 bytes of padding can be used */
 #define RX_DESC_PADDING	(CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
-/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
-#define RX_DESC_SIZE		(12 + RX_DESC_PADDING)
 /* aligned cache line size */
 #define RX_BUF_ALIGNE_SIZE	(CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
 
@@ -82,13 +78,13 @@ struct rx_desc_s {
 };
 
 struct sh_eth_info {
-	struct tx_desc_s *tx_desc_malloc;
+	struct tx_desc_s *tx_desc_alloc;
 	struct tx_desc_s *tx_desc_base;
 	struct tx_desc_s *tx_desc_cur;
-	struct rx_desc_s *rx_desc_malloc;
+	struct rx_desc_s *rx_desc_alloc;
 	struct rx_desc_s *rx_desc_base;
 	struct rx_desc_s *rx_desc_cur;
-	u8 *rx_buf_malloc;
+	u8 *rx_buf_alloc;
 	u8 *rx_buf_base;
 	u8 mac_addr[6];
 	u8 phy_addr;
@@ -359,7 +355,7 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 #define SH_ETH_TYPE_GETHER
 #define BASE_IO_ADDR	0xE9A00000
 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
-	defined(CONFIG_R8A7794)
+	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 #define SH_ETH_TYPE_ETHER
 #define BASE_IO_ADDR	0xEE700200
 #elif defined(CONFIG_R7S72100)
@@ -571,7 +567,7 @@ enum FELIC_MODE_BIT {
 #ifdef CONFIG_CPU_SH7724
 	ECMR_RTM = 0x00000010,
 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
-	defined(CONFIG_R8A7794)
+	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 	ECMR_RTM = 0x00000004,
 #endif
 
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 28859f31612..60c333e2c01 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -572,7 +572,7 @@ const char * pci_class_str(u8 class)
 }
 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
 
-int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
+__weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 {
 	/*
 	 * Check if pci device should be skipped in configuration
@@ -591,19 +591,15 @@ int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 
 	return 0;
 }
-int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
-	__attribute__((weak, alias("__pci_skip_dev")));
 
 #ifdef CONFIG_PCI_SCAN_SHOW
-int __pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
+__weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
 {
 	if (dev == PCI_BDF(hose->first_busno, 0, 0))
 		return 0;
 
 	return 1;
 }
-int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
-	__attribute__((weak, alias("__pci_print_dev")));
 #endif /* CONFIG_PCI_SCAN_SHOW */
 
 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c
index 3e50310464a..e578ae63429 100644
--- a/drivers/power/twl4030.c
+++ b/drivers/power/twl4030.c
@@ -98,4 +98,10 @@ void twl4030_power_mmc_init(void)
 				TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
 				TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
 				TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+	/* Set VMMC2 to 3.15 Volts */
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
+				TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
+				TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
+				TWL4030_PM_RECEIVER_DEV_GRP_P1);
 }
diff --git a/drivers/rtc/mvrtc.h b/drivers/rtc/mvrtc.h
index ce7a69bab57..ebddc124c3d 100644
--- a/drivers/rtc/mvrtc.h
+++ b/drivers/rtc/mvrtc.h
@@ -12,7 +12,7 @@
 #ifndef _MVRTC_H_
 #define _MVRTC_H_
 
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #include <compiler.h>
 
 /* RTC registers */
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index e69de29bb2d..a0b6e02b546 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -0,0 +1,12 @@
+config DM_SERIAL
+	bool "Enable Driver Model for serial drivers"
+	depends on DM
+	help
+	  If you want to use driver model for serial drivers, say Y.
+	  To use legacy serial drivers, say N.
+
+config UNIPHIER_SERIAL
+	bool "UniPhier on-chip UART support"
+	depends on ARCH_UNIPHIER && DM_SERIAL
+	help
+	  Support for the on-chip UARTs on the Panasonic UniPhier platform.
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index b4f299bb0ed..8c849427611 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -7,8 +7,11 @@
 
 ifdef CONFIG_DM_SERIAL
 obj-y += serial-uclass.o
+obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
 else
 obj-y += serial.o
+obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
+obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
 obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
 endif
 
@@ -16,6 +19,7 @@ obj-$(CONFIG_ALTERA_UART) += altera_uart.o
 obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
 obj-$(CONFIG_ARM_DCC) += arm_dcc.o
 obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
+obj-$(CONFIG_DW_SERIAL) += serial_dw.o
 obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
 obj-$(CONFIG_MCFUART) += mcfuart.o
 obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
@@ -25,8 +29,6 @@ obj-$(CONFIG_IMX_SERIAL) += serial_imx.o
 obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
 obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
 obj-$(CONFIG_MXC_UART) += serial_mxc.o
-obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
-obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
 obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
 obj-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o
 obj-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
@@ -40,6 +42,8 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
+obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
+obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 63a9ef68444..8f051914f54 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -61,13 +61,13 @@ static void ns16550_writeb(NS16550_t port, int offset, int value)
 	unsigned char *addr;
 
 	offset *= 1 << plat->reg_shift;
-	addr = plat->base + offset;
+	addr = map_sysmem(plat->base, 0) + offset;
 	/*
 	 * As far as we know it doesn't make sense to support selection of
 	 * these options at run-time, so use the existing CONFIG options.
 	 */
 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
-	outb(value, addr);
+	outb(value, (ulong)addr);
 #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN)
 	out_le32(addr, value);
 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
@@ -85,9 +85,9 @@ static int ns16550_readb(NS16550_t port, int offset)
 	unsigned char *addr;
 
 	offset *= 1 << plat->reg_shift;
-	addr = plat->base + offset;
+	addr = map_sysmem(plat->base, 0) + offset;
 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
-	return inb(addr);
+	return inb((ulong)addr);
 #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN)
 	return in_le32(addr);
 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
@@ -253,7 +253,7 @@ static int ns16550_serial_getc(struct udevice *dev)
 {
 	struct NS16550 *const com_port = dev_get_priv(dev);
 
-	if (!serial_in(&com_port->lsr) & UART_LSR_DR)
+	if (!(serial_in(&com_port->lsr) & UART_LSR_DR))
 		return -EAGAIN;
 
 	return serial_in(&com_port->rbr);
@@ -276,14 +276,15 @@ int ns16550_serial_probe(struct udevice *dev)
 {
 	struct NS16550 *const com_port = dev_get_priv(dev);
 
+	com_port->plat = dev_get_platdata(dev);
 	NS16550_init(com_port, -1);
 
 	return 0;
 }
 
+#ifdef CONFIG_OF_CONTROL
 int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 {
-	struct NS16550 *const com_port = dev_get_priv(dev);
 	struct ns16550_platdata *plat = dev->platdata;
 	fdt_addr_t addr;
 
@@ -291,13 +292,13 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	plat->base = (unsigned char *)addr;
+	plat->base = addr;
 	plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
 					 "reg-shift", 1);
-	com_port->plat = plat;
 
 	return 0;
 }
+#endif
 
 const struct dm_serial_ops ns16550_serial_ops = {
 	.putc = ns16550_serial_putc,
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 6dde4eaf472..71f1a5cb910 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -11,9 +11,12 @@
 #include <os.h>
 #include <serial.h>
 #include <stdio_dev.h>
+#include <watchdog.h>
 #include <dm/lists.h>
 #include <dm/device-internal.h>
 
+#include <ns16550.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /* The currently-selected console serial device */
@@ -47,13 +50,22 @@ static void serial_find_console_or_panic(void)
 	}
 #endif
 	/*
+	 * Try to use CONFIG_CONS_INDEX if available (it is numbered from 1!).
+	 *
 	 * Failing that, get the device with sequence number 0, or in extremis
 	 * just the first serial device we can find. But we insist on having
 	 * a console (even if it is silent).
 	 */
-	if (uclass_get_device_by_seq(UCLASS_SERIAL, 0, &cur_dev) &&
+#ifdef CONFIG_CONS_INDEX
+#define INDEX (CONFIG_CONS_INDEX - 1)
+#else
+#define INDEX 0
+#endif
+	if (uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &cur_dev) &&
+	    uclass_get_device(UCLASS_SERIAL, INDEX, &cur_dev) &&
 	    (uclass_first_device(UCLASS_SERIAL, &cur_dev) || !cur_dev))
 		panic("No serial driver found");
+#undef INDEX
 }
 
 /* Called prior to relocation */
@@ -71,95 +83,98 @@ void serial_initialize(void)
 	serial_find_console_or_panic();
 }
 
-void serial_putc(char ch)
+static void _serial_putc(struct udevice *dev, char ch)
 {
-	struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+	struct dm_serial_ops *ops = serial_get_ops(dev);
 	int err;
 
 	do {
-		err = ops->putc(cur_dev, ch);
+		err = ops->putc(dev, ch);
 	} while (err == -EAGAIN);
 	if (ch == '\n')
-		serial_putc('\r');
+		_serial_putc(dev, '\r');
 }
 
-void serial_setbrg(void)
+static void _serial_puts(struct udevice *dev, const char *str)
 {
-	struct dm_serial_ops *ops = serial_get_ops(cur_dev);
-
-	if (ops->setbrg)
-		ops->setbrg(cur_dev, gd->baudrate);
+	while (*str)
+		_serial_putc(dev, *str++);
 }
 
-void serial_puts(const char *str)
+static int _serial_getc(struct udevice *dev)
 {
-	while (*str)
-		serial_putc(*str++);
+	struct dm_serial_ops *ops = serial_get_ops(dev);
+	int err;
+
+	do {
+		err = ops->getc(dev);
+		if (err == -EAGAIN)
+			WATCHDOG_RESET();
+	} while (err == -EAGAIN);
+
+	return err >= 0 ? err : 0;
 }
 
-int serial_tstc(void)
+static int _serial_tstc(struct udevice *dev)
 {
-	struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+	struct dm_serial_ops *ops = serial_get_ops(dev);
 
 	if (ops->pending)
-		return ops->pending(cur_dev, true);
+		return ops->pending(dev, true);
 
 	return 1;
 }
 
+void serial_putc(char ch)
+{
+	_serial_putc(cur_dev, ch);
+}
+
+void serial_puts(const char *str)
+{
+	_serial_puts(cur_dev, str);
+}
+
 int serial_getc(void)
 {
-	struct dm_serial_ops *ops = serial_get_ops(cur_dev);
-	int err;
+	return _serial_getc(cur_dev);
+}
 
-	do {
-		err = ops->getc(cur_dev);
-	} while (err == -EAGAIN);
+int serial_tstc(void)
+{
+	return _serial_tstc(cur_dev);
+}
 
-	return err >= 0 ? err : 0;
+void serial_setbrg(void)
+{
+	struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+
+	if (ops->setbrg)
+		ops->setbrg(cur_dev, gd->baudrate);
 }
 
 void serial_stdio_init(void)
 {
 }
 
-void serial_stub_putc(struct stdio_dev *sdev, const char ch)
+static void serial_stub_putc(struct stdio_dev *sdev, const char ch)
 {
-	struct udevice *dev = sdev->priv;
-	struct dm_serial_ops *ops = serial_get_ops(dev);
-
-	ops->putc(dev, ch);
+	_serial_putc(sdev->priv, ch);
 }
 
 void serial_stub_puts(struct stdio_dev *sdev, const char *str)
 {
-	while (*str)
-		serial_stub_putc(sdev, *str++);
+	_serial_puts(sdev->priv, str);
 }
 
 int serial_stub_getc(struct stdio_dev *sdev)
 {
-	struct udevice *dev = sdev->priv;
-	struct dm_serial_ops *ops = serial_get_ops(dev);
-
-	int err;
-
-	do {
-		err = ops->getc(dev);
-	} while (err == -EAGAIN);
-
-	return err >= 0 ? err : 0;
+	return _serial_getc(sdev->priv);
 }
 
 int serial_stub_tstc(struct stdio_dev *sdev)
 {
-	struct udevice *dev = sdev->priv;
-	struct dm_serial_ops *ops = serial_get_ops(dev);
-
-	if (ops->pending)
-		return ops->pending(dev, true);
-
-	return 1;
+	return _serial_tstc(sdev->priv);
 }
 
 static int serial_post_probe(struct udevice *dev)
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 82fbbd92e2b..95c992a5a30 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -109,55 +109,54 @@ U_BOOT_ENV_CALLBACK(baudrate, on_baudrate);
 	void name(void)						\
 		__attribute__((weak, alias("serial_null")));
 
-serial_initfunc(mpc8xx_serial_initialize);
-serial_initfunc(ns16550_serial_initialize);
-serial_initfunc(pxa_serial_initialize);
-serial_initfunc(s3c24xx_serial_initialize);
-serial_initfunc(s5p_serial_initialize);
-serial_initfunc(zynq_serial_initialize);
-serial_initfunc(bfin_serial_initialize);
-serial_initfunc(bfin_jtag_initialize);
-serial_initfunc(mpc512x_serial_initialize);
-serial_initfunc(uartlite_serial_initialize);
-serial_initfunc(au1x00_serial_initialize);
-serial_initfunc(asc_serial_initialize);
-serial_initfunc(jz_serial_initialize);
-serial_initfunc(mpc5xx_serial_initialize);
-serial_initfunc(mpc8260_scc_serial_initialize);
-serial_initfunc(mpc8260_smc_serial_initialize);
-serial_initfunc(mpc85xx_serial_initialize);
-serial_initfunc(iop480_serial_initialize);
-serial_initfunc(leon2_serial_initialize);
-serial_initfunc(leon3_serial_initialize);
-serial_initfunc(marvell_serial_initialize);
+serial_initfunc(altera_jtag_serial_initialize);
+serial_initfunc(altera_serial_initialize);
 serial_initfunc(amirix_serial_initialize);
+serial_initfunc(arc_serial_initialize);
+serial_initfunc(arm_dcc_initialize);
+serial_initfunc(asc_serial_initialize);
+serial_initfunc(atmel_serial_initialize);
+serial_initfunc(au1x00_serial_initialize);
+serial_initfunc(bfin_jtag_initialize);
+serial_initfunc(bfin_serial_initialize);
 serial_initfunc(bmw_serial_initialize);
+serial_initfunc(clps7111_serial_initialize);
 serial_initfunc(cogent_serial_initialize);
 serial_initfunc(cpci750_serial_initialize);
 serial_initfunc(evb64260_serial_initialize);
-serial_initfunc(ml2_serial_initialize);
-serial_initfunc(sconsole_serial_initialize);
-serial_initfunc(p3mx_serial_initialize);
-serial_initfunc(altera_jtag_serial_initialize);
-serial_initfunc(altera_serial_initialize);
-serial_initfunc(atmel_serial_initialize);
-serial_initfunc(lpc32xx_serial_initialize);
-serial_initfunc(mcf_serial_initialize);
-serial_initfunc(oc_serial_initialize);
-serial_initfunc(sandbox_serial_initialize);
-serial_initfunc(clps7111_serial_initialize);
 serial_initfunc(imx_serial_initialize);
+serial_initfunc(iop480_serial_initialize);
+serial_initfunc(jz_serial_initialize);
 serial_initfunc(ks8695_serial_initialize);
+serial_initfunc(leon2_serial_initialize);
+serial_initfunc(leon3_serial_initialize);
 serial_initfunc(lh7a40x_serial_initialize);
+serial_initfunc(lpc32xx_serial_initialize);
+serial_initfunc(marvell_serial_initialize);
 serial_initfunc(max3100_serial_initialize);
+serial_initfunc(mcf_serial_initialize);
+serial_initfunc(ml2_serial_initialize);
+serial_initfunc(mpc512x_serial_initialize);
+serial_initfunc(mpc5xx_serial_initialize);
+serial_initfunc(mpc8260_scc_serial_initialize);
+serial_initfunc(mpc8260_smc_serial_initialize);
+serial_initfunc(mpc85xx_serial_initialize);
+serial_initfunc(mpc8xx_serial_initialize);
 serial_initfunc(mxc_serial_initialize);
+serial_initfunc(mxs_auart_initialize);
+serial_initfunc(ns16550_serial_initialize);
+serial_initfunc(oc_serial_initialize);
+serial_initfunc(p3mx_serial_initialize);
 serial_initfunc(pl01x_serial_initialize);
+serial_initfunc(pxa_serial_initialize);
+serial_initfunc(s3c24xx_serial_initialize);
+serial_initfunc(s5p_serial_initialize);
 serial_initfunc(sa1100_serial_initialize);
+serial_initfunc(sandbox_serial_initialize);
+serial_initfunc(sconsole_serial_initialize);
 serial_initfunc(sh_serial_initialize);
-serial_initfunc(arm_dcc_initialize);
-serial_initfunc(mxs_auart_initialize);
-serial_initfunc(arc_serial_initialize);
-serial_initfunc(uniphier_serial_initialize);
+serial_initfunc(uartlite_serial_initialize);
+serial_initfunc(zynq_serial_initialize);
 
 /**
  * serial_register() - Register serial driver with serial driver core
@@ -203,81 +202,80 @@ void serial_register(struct serial_device *dev)
  */
 void serial_initialize(void)
 {
-	mpc8xx_serial_initialize();
-	ns16550_serial_initialize();
-	pxa_serial_initialize();
-	s3c24xx_serial_initialize();
-	s5p_serial_initialize();
-	mpc512x_serial_initialize();
-	bfin_serial_initialize();
-	bfin_jtag_initialize();
-	uartlite_serial_initialize();
-	zynq_serial_initialize();
-	au1x00_serial_initialize();
-	asc_serial_initialize();
-	jz_serial_initialize();
-	mpc5xx_serial_initialize();
-	mpc8260_scc_serial_initialize();
-	mpc8260_smc_serial_initialize();
-	mpc85xx_serial_initialize();
-	iop480_serial_initialize();
-	leon2_serial_initialize();
-	leon3_serial_initialize();
-	marvell_serial_initialize();
+	altera_jtag_serial_initialize();
+	altera_serial_initialize();
 	amirix_serial_initialize();
+	arc_serial_initialize();
+	arm_dcc_initialize();
+	asc_serial_initialize();
+	atmel_serial_initialize();
+	au1x00_serial_initialize();
+	bfin_jtag_initialize();
+	bfin_serial_initialize();
 	bmw_serial_initialize();
+	clps7111_serial_initialize();
 	cogent_serial_initialize();
 	cpci750_serial_initialize();
 	evb64260_serial_initialize();
-	ml2_serial_initialize();
-	sconsole_serial_initialize();
-	p3mx_serial_initialize();
-	altera_jtag_serial_initialize();
-	altera_serial_initialize();
-	atmel_serial_initialize();
-	lpc32xx_serial_initialize();
-	mcf_serial_initialize();
-	oc_serial_initialize();
-	sandbox_serial_initialize();
-	clps7111_serial_initialize();
 	imx_serial_initialize();
+	iop480_serial_initialize();
+	jz_serial_initialize();
 	ks8695_serial_initialize();
+	leon2_serial_initialize();
+	leon3_serial_initialize();
 	lh7a40x_serial_initialize();
+	lpc32xx_serial_initialize();
+	marvell_serial_initialize();
 	max3100_serial_initialize();
+	mcf_serial_initialize();
+	ml2_serial_initialize();
+	mpc512x_serial_initialize();
+	mpc5xx_serial_initialize();
+	mpc8260_scc_serial_initialize();
+	mpc8260_smc_serial_initialize();
+	mpc85xx_serial_initialize();
+	mpc8xx_serial_initialize();
 	mxc_serial_initialize();
+	mxs_auart_initialize();
+	ns16550_serial_initialize();
+	oc_serial_initialize();
+	p3mx_serial_initialize();
 	pl01x_serial_initialize();
+	pxa_serial_initialize();
+	s3c24xx_serial_initialize();
+	s5p_serial_initialize();
 	sa1100_serial_initialize();
+	sandbox_serial_initialize();
+	sconsole_serial_initialize();
 	sh_serial_initialize();
-	arm_dcc_initialize();
-	mxs_auart_initialize();
-	arc_serial_initialize();
-	uniphier_serial_initialize();
+	uartlite_serial_initialize();
+	zynq_serial_initialize();
 
 	serial_assign(default_serial_console()->name);
 }
 
-int serial_stub_start(struct stdio_dev *sdev)
+static int serial_stub_start(struct stdio_dev *sdev)
 {
 	struct serial_device *dev = sdev->priv;
 
 	return dev->start();
 }
 
-int serial_stub_stop(struct stdio_dev *sdev)
+static int serial_stub_stop(struct stdio_dev *sdev)
 {
 	struct serial_device *dev = sdev->priv;
 
 	return dev->stop();
 }
 
-void serial_stub_putc(struct stdio_dev *sdev, const char ch)
+static void serial_stub_putc(struct stdio_dev *sdev, const char ch)
 {
 	struct serial_device *dev = sdev->priv;
 
 	dev->putc(ch);
 }
 
-void serial_stub_puts(struct stdio_dev *sdev, const char *str)
+static void serial_stub_puts(struct stdio_dev *sdev, const char *str)
 {
 	struct serial_device *dev = sdev->priv;
 
diff --git a/drivers/serial/serial_coreboot.c b/drivers/serial/serial_coreboot.c
new file mode 100644
index 00000000000..5c6a76c59c0
--- /dev/null
+++ b/drivers/serial/serial_coreboot.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+
+static const struct udevice_id coreboot_serial_ids[] = {
+	{ .compatible = "coreboot-uart" },
+	{ }
+};
+
+static int coreboot_serial_ofdata_to_platdata(struct udevice *dev)
+{
+	struct ns16550_platdata *plat = dev_get_platdata(dev);
+	int ret;
+
+	ret = ns16550_serial_ofdata_to_platdata(dev);
+	if (ret)
+		return ret;
+	plat->clock = 1843200;
+
+	return 0;
+}
+U_BOOT_DRIVER(serial_ns16550) = {
+	.name	= "serial_coreboot",
+	.id	= UCLASS_SERIAL,
+	.of_match = coreboot_serial_ids,
+	.ofdata_to_platdata = coreboot_serial_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+	.priv_auto_alloc_size = sizeof(struct NS16550),
+	.probe = ns16550_serial_probe,
+	.ops	= &ns16550_serial_ops,
+};
diff --git a/drivers/serial/serial_dw.c b/drivers/serial/serial_dw.c
new file mode 100644
index 00000000000..a348f2956ac
--- /dev/null
+++ b/drivers/serial/serial_dw.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+
+static const struct udevice_id dw_serial_ids[] = {
+	{ .compatible = "snps,dw-apb-uart" },
+	{ }
+};
+
+static int dw_serial_ofdata_to_platdata(struct udevice *dev)
+{
+	struct ns16550_platdata *plat = dev_get_platdata(dev);
+	int ret;
+
+	ret = ns16550_serial_ofdata_to_platdata(dev);
+	if (ret)
+		return ret;
+	plat->clock = CONFIG_SYS_NS16550_CLK;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(serial_ns16550) = {
+	.name	= "serial_dw",
+	.id	= UCLASS_SERIAL,
+	.of_match = dw_serial_ids,
+	.ofdata_to_platdata = dw_serial_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+	.priv_auto_alloc_size = sizeof(struct NS16550),
+	.probe = ns16550_serial_probe,
+	.ops	= &ns16550_serial_ops,
+};
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 313d560afce..d6cf1d874a6 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -5,37 +5,15 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
 #include <watchdog.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
+#include <dm/platform_data/serial_mxc.h>
 #include <serial.h>
 #include <linux/compiler.h>
 
-#define __REG(x)     (*((volatile u32 *)(x)))
-
-#ifndef CONFIG_MXC_UART_BASE
-#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
-#endif
-
-#define UART_PHYS	CONFIG_MXC_UART_BASE
-
-/* Register definitions */
-#define URXD  0x0  /* Receiver Register */
-#define UTXD  0x40 /* Transmitter Register */
-#define UCR1  0x80 /* Control Register 1 */
-#define UCR2  0x84 /* Control Register 2 */
-#define UCR3  0x88 /* Control Register 3 */
-#define UCR4  0x8c /* Control Register 4 */
-#define UFCR  0x90 /* FIFO Control Register */
-#define USR1  0x94 /* Status Register 1 */
-#define USR2  0x98 /* Status Register 2 */
-#define UESC  0x9c /* Escape Character Register */
-#define UTIM  0xa0 /* Escape Timer Register */
-#define UBIR  0xa4 /* BRM Incremental Register */
-#define UBMR  0xa8 /* BRM Modulator Register */
-#define UBRC  0xac /* Baud Rate Count Register */
-#define UTS   0xb4 /* UART Test Register (mx31) */
-
 /* UART Control Register Bit Fields.*/
 #define  URXD_CHARRDY    (1<<15)
 #define  URXD_ERR        (1<<14)
@@ -128,6 +106,33 @@
 #define  UTS_RXFULL	 (1<<3)	 /* RxFIFO full */
 #define  UTS_SOFTRST	 (1<<0)	 /* Software reset */
 
+#ifndef CONFIG_DM_SERIAL
+
+#ifndef CONFIG_MXC_UART_BASE
+#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
+#endif
+
+#define UART_PHYS	CONFIG_MXC_UART_BASE
+
+#define __REG(x)     (*((volatile u32 *)(x)))
+
+/* Register definitions */
+#define URXD  0x0  /* Receiver Register */
+#define UTXD  0x40 /* Transmitter Register */
+#define UCR1  0x80 /* Control Register 1 */
+#define UCR2  0x84 /* Control Register 2 */
+#define UCR3  0x88 /* Control Register 3 */
+#define UCR4  0x8c /* Control Register 4 */
+#define UFCR  0x90 /* FIFO Control Register */
+#define USR1  0x94 /* Status Register 1 */
+#define USR2  0x98 /* Status Register 2 */
+#define UESC  0x9c /* Escape Character Register */
+#define UTIM  0xa0 /* Escape Timer Register */
+#define UBIR  0xa4 /* BRM Incremental Register */
+#define UBMR  0xa8 /* BRM Modulator Register */
+#define UBRC  0xac /* Baud Rate Count Register */
+#define UTS   0xb4 /* UART Test Register (mx31) */
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static void mxc_serial_setbrg(void)
@@ -222,3 +227,118 @@ __weak struct serial_device *default_serial_console(void)
 {
 	return &mxc_serial_drv;
 }
+#endif
+
+#ifdef CONFIG_DM_SERIAL
+
+struct mxc_uart {
+	u32 rxd;
+	u32 spare0[15];
+
+	u32 txd;
+	u32 spare1[15];
+
+	u32 cr1;
+	u32 cr2;
+	u32 cr3;
+	u32 cr4;
+
+	u32 fcr;
+	u32 sr1;
+	u32 sr2;
+	u32 esc;
+
+	u32 tim;
+	u32 bir;
+	u32 bmr;
+	u32 brc;
+
+	u32 onems;
+	u32 ts;
+};
+
+int mxc_serial_setbrg(struct udevice *dev, int baudrate)
+{
+	struct mxc_serial_platdata *plat = dev->platdata;
+	struct mxc_uart *const uart = plat->reg;
+	u32 clk = imx_get_uartclk();
+
+	writel(4 << 7, &uart->fcr); /* divide input clock by 2 */
+	writel(0xf, &uart->bir);
+	writel(clk / (2 * baudrate), &uart->bmr);
+
+	writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
+	       &uart->cr2);
+	writel(UCR1_UARTEN, &uart->cr1);
+
+	return 0;
+}
+
+static int mxc_serial_probe(struct udevice *dev)
+{
+	struct mxc_serial_platdata *plat = dev->platdata;
+	struct mxc_uart *const uart = plat->reg;
+
+	writel(0, &uart->cr1);
+	writel(0, &uart->cr2);
+	while (!(readl(&uart->cr2) & UCR2_SRST));
+	writel(0x704 | UCR3_ADNIMP, &uart->cr3);
+	writel(0x8000, &uart->cr4);
+	writel(0x2b, &uart->esc);
+	writel(0, &uart->tim);
+	writel(0, &uart->ts);
+
+	return 0;
+}
+
+static int mxc_serial_getc(struct udevice *dev)
+{
+	struct mxc_serial_platdata *plat = dev->platdata;
+	struct mxc_uart *const uart = plat->reg;
+
+	if (readl(&uart->ts) & UTS_RXEMPTY)
+		return -EAGAIN;
+
+	return readl(&uart->rxd) & URXD_RX_DATA;
+}
+
+static int mxc_serial_putc(struct udevice *dev, const char ch)
+{
+	struct mxc_serial_platdata *plat = dev->platdata;
+	struct mxc_uart *const uart = plat->reg;
+
+	if (!(readl(&uart->ts) & UTS_TXEMPTY))
+		return -EAGAIN;
+
+	writel(ch, &uart->txd);
+
+	return 0;
+}
+
+static int mxc_serial_pending(struct udevice *dev, bool input)
+{
+	struct mxc_serial_platdata *plat = dev->platdata;
+	struct mxc_uart *const uart = plat->reg;
+	uint32_t sr2 = readl(&uart->sr2);
+
+	if (input)
+		return sr2 & USR2_RDR ? 1 : 0;
+	else
+		return sr2 & USR2_TXDC ? 0 : 1;
+}
+
+static const struct dm_serial_ops mxc_serial_ops = {
+	.putc = mxc_serial_putc,
+	.pending = mxc_serial_pending,
+	.getc = mxc_serial_getc,
+	.setbrg = mxc_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_mxc) = {
+	.name	= "serial_mxc",
+	.id	= UCLASS_SERIAL,
+	.probe = mxc_serial_probe,
+	.ops	= &mxc_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+#endif
diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 632da4cf70b..799ef6a667d 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -119,8 +119,7 @@ static NS16550_t serial_ports[6] = {
 	.puts	= eserial##port##_puts,		\
 }
 
-void
-_serial_putc(const char c,const int port)
+static void _serial_putc(const char c, const int port)
 {
 	if (c == '\n')
 		NS16550_putc(PORT, '\r');
@@ -128,35 +127,29 @@ _serial_putc(const char c,const int port)
 	NS16550_putc(PORT, c);
 }
 
-void
-_serial_putc_raw(const char c,const int port)
+static void _serial_putc_raw(const char c, const int port)
 {
 	NS16550_putc(PORT, c);
 }
 
-void
-_serial_puts (const char *s,const int port)
+static void _serial_puts(const char *s, const int port)
 {
 	while (*s) {
-		_serial_putc (*s++,port);
+		_serial_putc(*s++, port);
 	}
 }
 
-
-int
-_serial_getc(const int port)
+static int _serial_getc(const int port)
 {
 	return NS16550_getc(PORT);
 }
 
-int
-_serial_tstc(const int port)
+static int _serial_tstc(const int port)
 {
 	return NS16550_tstc(PORT);
 }
 
-void
-_serial_setbrg (const int port)
+static void _serial_setbrg(const int port)
 {
 	int clock_divisor;
 
diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c
new file mode 100644
index 00000000000..265fe007a06
--- /dev/null
+++ b/drivers/serial/serial_omap.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ns16550.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_OF_CONTROL
+static const struct udevice_id omap_serial_ids[] = {
+	{ .compatible = "ti,omap3-uart" },
+	{ }
+};
+
+static int omap_serial_ofdata_to_platdata(struct udevice *dev)
+{
+	struct ns16550_platdata *plat = dev_get_platdata(dev);
+	int ret;
+
+	ret = ns16550_serial_ofdata_to_platdata(dev);
+	if (ret)
+		return ret;
+	plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+				     "clock-frequency", -1);
+	plat->reg_shift = 2;
+
+	return 0;
+}
+#endif
+
+U_BOOT_DRIVER(serial_omap_ns16550) = {
+	.name	= "serial_omap",
+	.id	= UCLASS_SERIAL,
+	.of_match = of_match_ptr(omap_serial_ids),
+	.ofdata_to_platdata = of_match_ptr(omap_serial_ofdata_to_platdata),
+	.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+	.priv_auto_alloc_size = sizeof(struct NS16550),
+	.probe = ns16550_serial_probe,
+	.ops	= &ns16550_serial_ops,
+	.flags	= DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index dfb610e1a9d..38dda910217 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -12,125 +12,90 @@
 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
 
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
 #include <watchdog.h>
 #include <asm/io.h>
 #include <serial.h>
+#include <dm/platform_data/serial_pl01x.h>
 #include <linux/compiler.h>
-#include "serial_pl01x.h"
+#include "serial_pl01x_internal.h"
+
+#ifndef CONFIG_DM_SERIAL
 
-/*
- * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
- * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
- * Versatile PB has four UARTs.
- */
-#define CONSOLE_PORT CONFIG_CONS_INDEX
 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
+static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
+static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
 
-static void pl01x_putc (int portnum, char c);
-static int pl01x_getc (int portnum);
-static int pl01x_tstc (int portnum);
-unsigned int baudrate = CONFIG_BAUDRATE;
 DECLARE_GLOBAL_DATA_PTR;
+#endif
 
-static struct pl01x_regs *pl01x_get_regs(int portnum)
-{
-	return (struct pl01x_regs *) port[portnum];
-}
-
-#ifdef CONFIG_PL010_SERIAL
-
-static int pl01x_serial_init(void)
+static int pl01x_putc(struct pl01x_regs *regs, char c)
 {
-	struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
-	unsigned int divisor;
-
-	/* First, disable everything */
-	writel(0, &regs->pl010_cr);
+	/* Wait until there is space in the FIFO */
+	if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
+		return -EAGAIN;
 
-	/* Set baud rate */
-	switch (baudrate) {
-	case 9600:
-		divisor = UART_PL010_BAUD_9600;
-		break;
+	/* Send the character */
+	writel(c, &regs->dr);
 
-	case 19200:
-		divisor = UART_PL010_BAUD_9600;
-		break;
+	return 0;
+}
 
-	case 38400:
-		divisor = UART_PL010_BAUD_38400;
-		break;
+static int pl01x_getc(struct pl01x_regs *regs)
+{
+	unsigned int data;
 
-	case 57600:
-		divisor = UART_PL010_BAUD_57600;
-		break;
+	/* Wait until there is data in the FIFO */
+	if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
+		return -EAGAIN;
 
-	case 115200:
-		divisor = UART_PL010_BAUD_115200;
-		break;
+	data = readl(&regs->dr);
 
-	default:
-		divisor = UART_PL010_BAUD_38400;
+	/* Check for an error flag */
+	if (data & 0xFFFFFF00) {
+		/* Clear the error */
+		writel(0xFFFFFFFF, &regs->ecr);
+		return -1;
 	}
 
-	writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
-	writel(divisor & 0xff, &regs->pl010_lcrl);
-
-	/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
-	writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, &regs->pl010_lcrh);
-
-	/* Finally, enable the UART */
-	writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
-
-	return 0;
+	return (int) data;
 }
 
-#endif /* CONFIG_PL010_SERIAL */
-
-#ifdef CONFIG_PL011_SERIAL
+static int pl01x_tstc(struct pl01x_regs *regs)
+{
+	WATCHDOG_RESET();
+	return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
+}
 
-static int pl01x_serial_init(void)
+static int pl01x_generic_serial_init(struct pl01x_regs *regs,
+				     enum pl01x_type type)
 {
-	struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
-	unsigned int temp;
-	unsigned int divider;
-	unsigned int remainder;
-	unsigned int fraction;
 	unsigned int lcr;
 
 #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
-	/* Empty RX fifo if necessary */
-	if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
-		while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
-			readl(&regs->dr);
+	if (type == TYPE_PL011) {
+		/* Empty RX fifo if necessary */
+		if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
+			while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
+				readl(&regs->dr);
+		}
 	}
 #endif
 
 	/* First, disable everything */
-	writel(0, &regs->pl011_cr);
-
-	/*
-	 * Set baud rate
-	 *
-	 * IBRD = UART_CLK / (16 * BAUD_RATE)
-	 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
-	 */
-	temp = 16 * baudrate;
-	divider = CONFIG_PL011_CLOCK / temp;
-	remainder = CONFIG_PL011_CLOCK % temp;
-	temp = (8 * remainder) / baudrate;
-	fraction = (temp >> 1) + (temp & 1);
-
-	writel(divider, &regs->pl011_ibrd);
-	writel(fraction, &regs->pl011_fbrd);
+	writel(0, &regs->pl010_cr);
 
 	/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
 	lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
 	writel(lcr, &regs->pl011_lcrh);
 
+	switch (type) {
+	case TYPE_PL010:
+		break;
+	case TYPE_PL011: {
 #ifdef CONFIG_PL011_SERIAL_RLCR
-	{
 		int i;
 
 		/*
@@ -144,90 +109,151 @@ static int pl01x_serial_init(void)
 		writel(lcr, &regs->pl011_rlcr);
 		/* lcrh needs to be set again for change to be effective */
 		writel(lcr, &regs->pl011_lcrh);
-	}
 #endif
-	/* Finally, enable the UART */
-	writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE |
-	       UART_PL011_CR_RTS, &regs->pl011_cr);
+		break;
+	}
+	default:
+		return -EINVAL;
+	}
 
 	return 0;
 }
 
-#endif /* CONFIG_PL011_SERIAL */
-
-static void pl01x_serial_putc(const char c)
+static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
+				int clock, int baudrate)
 {
-	if (c == '\n')
-		pl01x_putc (CONSOLE_PORT, '\r');
+	switch (type) {
+	case TYPE_PL010: {
+		unsigned int divisor;
+
+		switch (baudrate) {
+		case 9600:
+			divisor = UART_PL010_BAUD_9600;
+			break;
+		case 19200:
+			divisor = UART_PL010_BAUD_9600;
+			break;
+		case 38400:
+			divisor = UART_PL010_BAUD_38400;
+			break;
+		case 57600:
+			divisor = UART_PL010_BAUD_57600;
+			break;
+		case 115200:
+			divisor = UART_PL010_BAUD_115200;
+			break;
+		default:
+			divisor = UART_PL010_BAUD_38400;
+		}
+
+		writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
+		writel(divisor & 0xff, &regs->pl010_lcrl);
+
+		/* Finally, enable the UART */
+		writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
+		break;
+	}
+	case TYPE_PL011: {
+		unsigned int temp;
+		unsigned int divider;
+		unsigned int remainder;
+		unsigned int fraction;
 
-	pl01x_putc (CONSOLE_PORT, c);
-}
+		/*
+		* Set baud rate
+		*
+		* IBRD = UART_CLK / (16 * BAUD_RATE)
+		* FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
+		*		/ (16 * BAUD_RATE))
+		*/
+		temp = 16 * baudrate;
+		divider = clock / temp;
+		remainder = clock % temp;
+		temp = (8 * remainder) / baudrate;
+		fraction = (temp >> 1) + (temp & 1);
+
+		writel(divider, &regs->pl011_ibrd);
+		writel(fraction, &regs->pl011_fbrd);
+
+		/* Finally, enable the UART */
+		writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
+		       UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
+		break;
+	}
+	default:
+		return -EINVAL;
+	}
 
-static int pl01x_serial_getc(void)
-{
-	return pl01x_getc (CONSOLE_PORT);
+	return 0;
 }
 
-static int pl01x_serial_tstc(void)
+#ifndef CONFIG_DM_SERIAL
+static void pl01x_serial_init_baud(int baudrate)
 {
-	return pl01x_tstc (CONSOLE_PORT);
+	int clock = 0;
+
+#if defined(CONFIG_PL010_SERIAL)
+	pl01x_type = TYPE_PL010;
+#elif defined(CONFIG_PL011_SERIAL)
+	pl01x_type = TYPE_PL011;
+	clock = CONFIG_PL011_CLOCK;
+#endif
+	base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
+
+	pl01x_generic_serial_init(base_regs, pl01x_type);
+	pl01x_generic_setbrg(base_regs, TYPE_PL010, clock, baudrate);
 }
 
-static void pl01x_serial_setbrg(void)
+/*
+ * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
+ * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
+ * Versatile PB has four UARTs.
+ */
+int pl01x_serial_init(void)
 {
-	struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
+	pl01x_serial_init_baud(CONFIG_BAUDRATE);
 
-	baudrate = gd->baudrate;
-	/*
-	 * Flush FIFO and wait for non-busy before changing baudrate to avoid
-	 * crap in console
-	 */
-	while (!(readl(&regs->fr) & UART_PL01x_FR_TXFE))
-		WATCHDOG_RESET();
-	while (readl(&regs->fr) & UART_PL01x_FR_BUSY)
-		WATCHDOG_RESET();
-	serial_init();
+	return 0;
 }
 
-static void pl01x_putc (int portnum, char c)
+static void pl01x_serial_putc(const char c)
 {
-	struct pl01x_regs *regs = pl01x_get_regs(portnum);
-
-	/* Wait until there is space in the FIFO */
-	while (readl(&regs->fr) & UART_PL01x_FR_TXFF)
-		WATCHDOG_RESET();
+	if (c == '\n')
+		while (pl01x_putc(base_regs, '\r') == -EAGAIN);
 
-	/* Send the character */
-	writel(c, &regs->dr);
+	while (pl01x_putc(base_regs, c) == -EAGAIN);
 }
 
-static int pl01x_getc (int portnum)
+static int pl01x_serial_getc(void)
 {
-	struct pl01x_regs *regs = pl01x_get_regs(portnum);
-	unsigned int data;
+	while (1) {
+		int ch = pl01x_getc(base_regs);
 
-	/* Wait until there is data in the FIFO */
-	while (readl(&regs->fr) & UART_PL01x_FR_RXFE)
-		WATCHDOG_RESET();
-
-	data = readl(&regs->dr);
+		if (ch == -EAGAIN) {
+			WATCHDOG_RESET();
+			continue;
+		}
 
-	/* Check for an error flag */
-	if (data & 0xFFFFFF00) {
-		/* Clear the error */
-		writel(0xFFFFFFFF, &regs->ecr);
-		return -1;
+		return ch;
 	}
-
-	return (int) data;
 }
 
-static int pl01x_tstc (int portnum)
+static int pl01x_serial_tstc(void)
 {
-	struct pl01x_regs *regs = pl01x_get_regs(portnum);
+	return pl01x_tstc(base_regs);
+}
 
-	WATCHDOG_RESET();
-	return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
+static void pl01x_serial_setbrg(void)
+{
+	/*
+	 * Flush FIFO and wait for non-busy before changing baudrate to avoid
+	 * crap in console
+	 */
+	while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
+		WATCHDOG_RESET();
+	while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
+		WATCHDOG_RESET();
+	pl01x_serial_init_baud(gd->baudrate);
 }
 
 static struct serial_device pl01x_serial_drv = {
@@ -250,3 +276,74 @@ __weak struct serial_device *default_serial_console(void)
 {
 	return &pl01x_serial_drv;
 }
+
+#endif /* nCONFIG_DM_SERIAL */
+
+#ifdef CONFIG_DM_SERIAL
+
+struct pl01x_priv {
+	struct pl01x_regs *regs;
+	enum pl01x_type type;
+};
+
+static int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
+{
+	struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
+	struct pl01x_priv *priv = dev_get_priv(dev);
+
+	pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate);
+
+	return 0;
+}
+
+static int pl01x_serial_probe(struct udevice *dev)
+{
+	struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
+	struct pl01x_priv *priv = dev_get_priv(dev);
+
+	priv->regs = (struct pl01x_regs *)plat->base;
+	priv->type = plat->type;
+	return pl01x_generic_serial_init(priv->regs, priv->type);
+}
+
+static int pl01x_serial_getc(struct udevice *dev)
+{
+	struct pl01x_priv *priv = dev_get_priv(dev);
+
+	return pl01x_getc(priv->regs);
+}
+
+static int pl01x_serial_putc(struct udevice *dev, const char ch)
+{
+	struct pl01x_priv *priv = dev_get_priv(dev);
+
+	return pl01x_putc(priv->regs, ch);
+}
+
+static int pl01x_serial_pending(struct udevice *dev, bool input)
+{
+	struct pl01x_priv *priv = dev_get_priv(dev);
+	unsigned int fr = readl(&priv->regs->fr);
+
+	if (input)
+		return pl01x_tstc(priv->regs);
+	else
+		return fr & UART_PL01x_FR_TXFF ? 0 : 1;
+}
+
+static const struct dm_serial_ops pl01x_serial_ops = {
+	.putc = pl01x_serial_putc,
+	.pending = pl01x_serial_pending,
+	.getc = pl01x_serial_getc,
+	.setbrg = pl01x_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_pl01x) = {
+	.name	= "serial_pl01x",
+	.id	= UCLASS_SERIAL,
+	.probe = pl01x_serial_probe,
+	.ops	= &pl01x_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+#endif
diff --git a/drivers/serial/serial_pl01x.h b/drivers/serial/serial_pl01x_internal.h
index 288a4f19f56..288a4f19f56 100644
--- a/drivers/serial/serial_pl01x.h
+++ b/drivers/serial/serial_pl01x_internal.h
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c
index c07f4c9b473..7afc5044a8c 100644
--- a/drivers/serial/serial_s3c24x0.c
+++ b/drivers/serial/serial_s3c24x0.c
@@ -69,7 +69,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static int hwflow;
 #endif
 
-void _serial_setbrg(const int dev_index)
+static void _serial_setbrg(const int dev_index)
 {
 	struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
 	unsigned int reg = 0;
@@ -131,7 +131,7 @@ static int serial_init_dev(const int dev_index)
  * otherwise. When the function is succesfull, the character read is
  * written into its argument c.
  */
-int _serial_getc(const int dev_index)
+static int _serial_getc(const int dev_index)
 {
 	struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
 
@@ -181,7 +181,7 @@ void enable_putc(void)
 /*
  * Output a single byte to the serial port.
  */
-void _serial_putc(const char c, const int dev_index)
+static void _serial_putc(const char c, const int dev_index)
 {
 	struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
 #ifdef CONFIG_MODEM_SUPPORT
@@ -212,7 +212,7 @@ static inline void serial_putc_dev(unsigned int dev_index, const char c)
 /*
  * Test whether a character is in the RX buffer
  */
-int _serial_tstc(const int dev_index)
+static int _serial_tstc(const int dev_index)
 {
 	struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
 
@@ -224,7 +224,7 @@ static inline int serial_tstc_dev(unsigned int dev_index)
 	return _serial_tstc(dev_index);
 }
 
-void _serial_puts(const char *s, const int dev_index)
+static void _serial_puts(const char *s, const int dev_index)
 {
 	while (*s) {
 		_serial_putc(*s++, dev_index);
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 98c62b4c147..8469afdaae9 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -9,6 +9,8 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
 #include <fdtdec.h>
 #include <linux/compiler.h>
 #include <asm/io.h>
@@ -18,26 +20,18 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define RX_FIFO_COUNT_MASK	0xff
-#define RX_FIFO_FULL_MASK	(1 << 8)
-#define TX_FIFO_FULL_MASK	(1 << 24)
+#define RX_FIFO_COUNT_SHIFT	0
+#define RX_FIFO_COUNT_MASK	(0xff << RX_FIFO_COUNT_SHIFT)
+#define RX_FIFO_FULL		(1 << 8)
+#define TX_FIFO_COUNT_SHIFT	16
+#define TX_FIFO_COUNT_MASK	(0xff << TX_FIFO_COUNT_SHIFT)
+#define TX_FIFO_FULL		(1 << 24)
 
 /* Information about a serial port */
-struct fdt_serial {
-	u32 base_addr;  /* address of registers in physical memory */
+struct s5p_serial_platdata {
+	struct s5p_uart *reg;  /* address of registers in physical memory */
 	u8 port_id;     /* uart port number */
-	u8 enabled;     /* 1 if enabled, 0 if disabled */
-} config __attribute__ ((section(".data")));
-
-static inline struct s5p_uart *s5p_get_base_uart(int dev_index)
-{
-#ifdef CONFIG_OF_CONTROL
-	return (struct s5p_uart *)(config.base_addr);
-#else
-	u32 offset = dev_index * sizeof(struct s5p_uart);
-	return (struct s5p_uart *)(samsung_get_base_uart() + offset);
-#endif
-}
+};
 
 /*
  * The coefficient, used to calculate the baudrate on S5P UARTs is
@@ -65,23 +59,13 @@ static const int udivslot[] = {
 	0xffdf,
 };
 
-static void serial_setbrg_dev(const int dev_index)
+int s5p_serial_setbrg(struct udevice *dev, int baudrate)
 {
-	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
-	u32 uclk = get_uart_clk(dev_index);
-	u32 baudrate = gd->baudrate;
+	struct s5p_serial_platdata *plat = dev->platdata;
+	struct s5p_uart *const uart = plat->reg;
+	u32 uclk = get_uart_clk(plat->port_id);
 	u32 val;
 
-#if defined(CONFIG_SILENT_CONSOLE) && \
-		defined(CONFIG_OF_CONTROL) && \
-		!defined(CONFIG_SPL_BUILD)
-	if (fdtdec_get_config_int(gd->fdt_blob, "silent_console", 0))
-		gd->flags |= GD_FLG_SILENT;
-#endif
-
-	if (!config.enabled)
-		return;
-
 	val = uclk / baudrate;
 
 	writel(val / 16 - 1, &uart->ubrdiv);
@@ -90,15 +74,14 @@ static void serial_setbrg_dev(const int dev_index)
 		writew(udivslot[val % 16], &uart->rest.slot);
 	else
 		writeb(val % 16, &uart->rest.value);
+
+	return 0;
 }
 
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- */
-static int serial_init_dev(const int dev_index)
+static int s5p_serial_probe(struct udevice *dev)
 {
-	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
+	struct s5p_serial_platdata *plat = dev->platdata;
+	struct s5p_uart *const uart = plat->reg;
 
 	/* enable FIFOs, auto clear Rx FIFO */
 	writel(0x3, &uart->ufcon);
@@ -108,14 +91,11 @@ static int serial_init_dev(const int dev_index)
 	/* No interrupts, no DMA, pure polling */
 	writel(0x245, &uart->ucon);
 
-	serial_setbrg_dev(dev_index);
-
 	return 0;
 }
 
-static int serial_err_check(const int dev_index, int op)
+static int serial_err_check(const struct s5p_uart *const uart, int op)
 {
-	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
 	unsigned int mask;
 
 	/*
@@ -133,169 +113,78 @@ static int serial_err_check(const int dev_index, int op)
 	return readl(&uart->uerstat) & mask;
 }
 
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int serial_getc_dev(const int dev_index)
+static int s5p_serial_getc(struct udevice *dev)
 {
-	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
-
-	if (!config.enabled)
-		return 0;
+	struct s5p_serial_platdata *plat = dev->platdata;
+	struct s5p_uart *const uart = plat->reg;
 
-	/* wait for character to arrive */
-	while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
-					 RX_FIFO_FULL_MASK))) {
-		if (serial_err_check(dev_index, 0))
-			return 0;
-	}
+	if (!(readl(&uart->ufstat) & RX_FIFO_COUNT_MASK))
+		return -EAGAIN;
 
+	serial_err_check(uart, 0);
 	return (int)(readb(&uart->urxh) & 0xff);
 }
 
-/*
- * Output a single byte to the serial port.
- */
-static void serial_putc_dev(const char c, const int dev_index)
+static int s5p_serial_putc(struct udevice *dev, const char ch)
 {
-	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
-
-	if (!config.enabled)
-		return;
-
-	/* wait for room in the tx FIFO */
-	while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) {
-		if (serial_err_check(dev_index, 1))
-			return;
-	}
+	struct s5p_serial_platdata *plat = dev->platdata;
+	struct s5p_uart *const uart = plat->reg;
 
-	writeb(c, &uart->utxh);
+	if (readl(&uart->ufstat) & TX_FIFO_FULL)
+		return -EAGAIN;
 
-	/* If \n, also do \r */
-	if (c == '\n')
-		serial_putc('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-static int serial_tstc_dev(const int dev_index)
-{
-	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
+	writeb(ch, &uart->utxh);
+	serial_err_check(uart, 1);
 
-	if (!config.enabled)
-		return 0;
-
-	return (int)(readl(&uart->utrstat) & 0x1);
+	return 0;
 }
 
-static void serial_puts_dev(const char *s, const int dev_index)
+static int s5p_serial_pending(struct udevice *dev, bool input)
 {
-	while (*s)
-		serial_putc_dev(*s++, dev_index);
-}
+	struct s5p_serial_platdata *plat = dev->platdata;
+	struct s5p_uart *const uart = plat->reg;
+	uint32_t ufstat = readl(&uart->ufstat);
 
-/* Multi serial device functions */
-#define DECLARE_S5P_SERIAL_FUNCTIONS(port) \
-static int s5p_serial##port##_init(void) { return serial_init_dev(port); } \
-static void s5p_serial##port##_setbrg(void) { serial_setbrg_dev(port); } \
-static int s5p_serial##port##_getc(void) { return serial_getc_dev(port); } \
-static int s5p_serial##port##_tstc(void) { return serial_tstc_dev(port); } \
-static void s5p_serial##port##_putc(const char c) { serial_putc_dev(c, port); } \
-static void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); }
-
-#define INIT_S5P_SERIAL_STRUCTURE(port, __name) {	\
-	.name	= __name,				\
-	.start	= s5p_serial##port##_init,		\
-	.stop	= NULL,					\
-	.setbrg	= s5p_serial##port##_setbrg,		\
-	.getc	= s5p_serial##port##_getc,		\
-	.tstc	= s5p_serial##port##_tstc,		\
-	.putc	= s5p_serial##port##_putc,		\
-	.puts	= s5p_serial##port##_puts,		\
+	if (input)
+		return (ufstat & RX_FIFO_COUNT_MASK) >> RX_FIFO_COUNT_SHIFT;
+	else
+		return (ufstat & TX_FIFO_COUNT_MASK) >> TX_FIFO_COUNT_SHIFT;
 }
 
-DECLARE_S5P_SERIAL_FUNCTIONS(0);
-struct serial_device s5p_serial0_device =
-	INIT_S5P_SERIAL_STRUCTURE(0, "s5pser0");
-DECLARE_S5P_SERIAL_FUNCTIONS(1);
-struct serial_device s5p_serial1_device =
-	INIT_S5P_SERIAL_STRUCTURE(1, "s5pser1");
-DECLARE_S5P_SERIAL_FUNCTIONS(2);
-struct serial_device s5p_serial2_device =
-	INIT_S5P_SERIAL_STRUCTURE(2, "s5pser2");
-DECLARE_S5P_SERIAL_FUNCTIONS(3);
-struct serial_device s5p_serial3_device =
-	INIT_S5P_SERIAL_STRUCTURE(3, "s5pser3");
-
-#ifdef CONFIG_OF_CONTROL
-int fdtdec_decode_console(int *index, struct fdt_serial *uart)
+static int s5p_serial_ofdata_to_platdata(struct udevice *dev)
 {
-	const void *blob = gd->fdt_blob;
-	int node;
+	struct s5p_serial_platdata *plat = dev->platdata;
+	fdt_addr_t addr;
 
-	node = fdt_path_offset(blob, "console");
-	if (node < 0)
-		return node;
+	addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
 
-	uart->base_addr = fdtdec_get_addr(blob, node, "reg");
-	if (uart->base_addr == FDT_ADDR_T_NONE)
-		return -FDT_ERR_NOTFOUND;
-
-	uart->port_id = fdtdec_get_int(blob, node, "id", -1);
-	uart->enabled = fdtdec_get_is_enabled(blob, node);
+	plat->reg = (struct s5p_uart *)addr;
+	plat->port_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "id", -1);
 
 	return 0;
 }
-#endif
 
-__weak struct serial_device *default_serial_console(void)
-{
-#ifdef CONFIG_OF_CONTROL
-	int index = 0;
-
-	if ((!config.base_addr) && (fdtdec_decode_console(&index, &config))) {
-		debug("Cannot decode default console node\n");
-		return NULL;
-	}
-
-	switch (config.port_id) {
-	case 0:
-		return &s5p_serial0_device;
-	case 1:
-		return &s5p_serial1_device;
-	case 2:
-		return &s5p_serial2_device;
-	case 3:
-		return &s5p_serial3_device;
-	default:
-		debug("Unknown config.port_id: %d", config.port_id);
-		break;
-	}
-
-	return NULL;
-#else
-	config.enabled = 1;
-#if defined(CONFIG_SERIAL0)
-	return &s5p_serial0_device;
-#elif defined(CONFIG_SERIAL1)
-	return &s5p_serial1_device;
-#elif defined(CONFIG_SERIAL2)
-	return &s5p_serial2_device;
-#elif defined(CONFIG_SERIAL3)
-	return &s5p_serial3_device;
-#else
-#error "CONFIG_SERIAL? missing."
-#endif
-#endif
-}
+static const struct dm_serial_ops s5p_serial_ops = {
+	.putc = s5p_serial_putc,
+	.pending = s5p_serial_pending,
+	.getc = s5p_serial_getc,
+	.setbrg = s5p_serial_setbrg,
+};
 
-void s5p_serial_initialize(void)
-{
-	serial_register(&s5p_serial0_device);
-	serial_register(&s5p_serial1_device);
-	serial_register(&s5p_serial2_device);
-	serial_register(&s5p_serial3_device);
-}
+static const struct udevice_id s5p_serial_ids[] = {
+	{ .compatible = "samsung,exynos4210-uart" },
+	{ }
+};
+
+U_BOOT_DRIVER(serial_s5p) = {
+	.name	= "serial_s5p",
+	.id	= UCLASS_SERIAL,
+	.of_match = s5p_serial_ids,
+	.ofdata_to_platdata = s5p_serial_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct s5p_serial_platdata),
+	.probe = s5p_serial_probe,
+	.ops	= &s5p_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 144a9253945..7c1f2713761 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -122,7 +122,7 @@ static void handle_error(void)
 	sci_out(&sh_sci, SCLSR, 0x00);
 }
 
-void serial_raw_putc(const char c)
+static void serial_raw_putc(const char c)
 {
 	while (1) {
 		/* Tx fifo is empty */
@@ -152,7 +152,7 @@ static int sh_serial_tstc(void)
 }
 
 
-int serial_getc_check(void)
+static int serial_getc_check(void)
 {
 	unsigned short status;
 
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index fe8cde4dedb..53406e58554 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -227,7 +227,7 @@ struct uart_port {
 # define SCIF_ORER 0x0001		/* Overrun error bit */
 # define SCSCR_INIT(port)	0x38	/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
-	defined(CONFIG_R8A7794)
+	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 # define SCIF_ORER	0x0001
 # define SCSCR_INIT(port)	0x32	/* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
 #else
@@ -304,7 +304,8 @@ struct uart_port {
 /* SH7763 SCIF2 support */
 # define SCIF2_RFDC_MASK 0x001f
 # define SCIF2_TXROOM_MAX 16
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 # define SCIF_RFDC_MASK	0x003f
 #else
@@ -589,7 +590,7 @@ SCIF_FNS(SCSPTR,                        0,  0, 0, 0)
 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 #endif
 #if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
-	defined(CONFIG_R8A7794)
+	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 SCIF_FNS(DL,				0,  0, 0x30, 16)
 SCIF_FNS(CKS,				0,  0, 0x34, 16)
 #endif
@@ -734,7 +735,8 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk)
 #define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
 #elif defined(__H8300H__) || defined(__H8300S__)
 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */
 #else /* Generic SH */
diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
index f8c9d921e28..3f3d4152134 100644
--- a/drivers/serial/serial_uniphier.c
+++ b/drivers/serial/serial_uniphier.c
@@ -2,14 +2,14 @@
  * Copyright (C) 2012-2014 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
- * Based on serial_ns16550.c
- * (C) Copyright 2000
- * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
- *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <dm/device.h>
+#include <dm/platform_data/serial-uniphier.h>
 #include <serial.h>
 
 #define UART_REG(x)					\
@@ -48,157 +48,115 @@ struct uniphier_serial {
 #define UART_LSR_DR	0x01		/* Data ready */
 #define UART_LSR_THRE	0x20		/* Xmit holding register empty */
 
-DECLARE_GLOBAL_DATA_PTR;
+struct uniphier_serial_private_data {
+	struct uniphier_serial __iomem *membase;
+};
+
+#define uniphier_serial_port(dev)	\
+	((struct uniphier_serial_private_data *)dev_get_priv(dev))->membase
 
-static void uniphier_serial_init(struct uniphier_serial *port)
+static int uniphier_serial_setbrg(struct udevice *dev, int baudrate)
 {
+	struct uniphier_serial_platform_data *plat = dev_get_platdata(dev);
+	struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
 	const unsigned int mode_x_div = 16;
 	unsigned int divisor;
 
 	writeb(UART_LCR_WLS_8, &port->lcr);
 
-	divisor = DIV_ROUND_CLOSEST(CONFIG_SYS_UNIPHIER_UART_CLK,
-						mode_x_div * gd->baudrate);
+	divisor = DIV_ROUND_CLOSEST(plat->uartclk, mode_x_div * baudrate);
 
 	writew(divisor, &port->dlr);
-}
 
-static void uniphier_serial_setbrg(struct uniphier_serial *port)
-{
-	uniphier_serial_init(port);
+	return 0;
 }
 
-static int uniphier_serial_tstc(struct uniphier_serial *port)
+static int uniphier_serial_getc(struct udevice *dev)
 {
-	return (readb(&port->lsr) & UART_LSR_DR) != 0;
-}
+	struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
 
-static int uniphier_serial_getc(struct uniphier_serial *port)
-{
-	while (!uniphier_serial_tstc(port))
-		;
+	if (!(readb(&port->lsr) & UART_LSR_DR))
+		return -EAGAIN;
 
 	return readb(&port->rbr);
 }
 
-static void uniphier_serial_putc(struct uniphier_serial *port, const char c)
+static int uniphier_serial_putc(struct udevice *dev, const char c)
 {
-	if (c == '\n')
-		uniphier_serial_putc(port, '\r');
+	struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
 
-	while (!(readb(&port->lsr) & UART_LSR_THRE))
-		;
+	if (!(readb(&port->lsr) & UART_LSR_THRE))
+		return -EAGAIN;
 
 	writeb(c, &port->thr);
+
+	return 0;
 }
 
-static struct uniphier_serial *serial_ports[4] = {
-#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE0
-	(struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE0,
-#else
-	NULL,
-#endif
-#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE1
-	(struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE1,
-#else
-	NULL,
-#endif
-#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE2
-	(struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE2,
-#else
-	NULL,
-#endif
-#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE3
-	(struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE3,
-#else
-	NULL,
-#endif
-};
+static int uniphier_serial_pending(struct udevice *dev, bool input)
+{
+	struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
 
-/* Multi serial device functions */
-#define DECLARE_ESERIAL_FUNCTIONS(port) \
-	static int  eserial##port##_init(void) \
-	{ \
-		uniphier_serial_init(serial_ports[port]); \
-		return 0 ; \
-	} \
-	static void eserial##port##_setbrg(void) \
-	{ \
-		uniphier_serial_setbrg(serial_ports[port]); \
-	} \
-	static int  eserial##port##_getc(void) \
-	{ \
-		return uniphier_serial_getc(serial_ports[port]); \
-	} \
-	static int  eserial##port##_tstc(void) \
-	{ \
-		return uniphier_serial_tstc(serial_ports[port]); \
-	} \
-	static void eserial##port##_putc(const char c) \
-	{ \
-		uniphier_serial_putc(serial_ports[port], c); \
-	}
-
-/* Serial device descriptor */
-#define INIT_ESERIAL_STRUCTURE(port, __name) {	\
-	.name	= __name,			\
-	.start	= eserial##port##_init,		\
-	.stop	= NULL,				\
-	.setbrg	= eserial##port##_setbrg,	\
-	.getc	= eserial##port##_getc,		\
-	.tstc	= eserial##port##_tstc,		\
-	.putc	= eserial##port##_putc,		\
-	.puts	= default_serial_puts,		\
+	if (input)
+		return readb(&port->lsr) & UART_LSR_DR;
+	else
+		return !(readb(&port->lsr) & UART_LSR_THRE);
 }
 
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0)
-DECLARE_ESERIAL_FUNCTIONS(0);
-struct serial_device uniphier_serial0_device =
-	INIT_ESERIAL_STRUCTURE(0, "ttyS0");
-#endif
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1)
-DECLARE_ESERIAL_FUNCTIONS(1);
-struct serial_device uniphier_serial1_device =
-	INIT_ESERIAL_STRUCTURE(1, "ttyS1");
-#endif
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2)
-DECLARE_ESERIAL_FUNCTIONS(2);
-struct serial_device uniphier_serial2_device =
-	INIT_ESERIAL_STRUCTURE(2, "ttyS2");
-#endif
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3)
-DECLARE_ESERIAL_FUNCTIONS(3);
-struct serial_device uniphier_serial3_device =
-	INIT_ESERIAL_STRUCTURE(3, "ttyS3");
-#endif
+static int uniphier_serial_probe(struct udevice *dev)
+{
+	struct uniphier_serial_private_data *priv = dev_get_priv(dev);
+	struct uniphier_serial_platform_data *plat = dev_get_platdata(dev);
+
+	priv->membase = map_sysmem(plat->base, sizeof(struct uniphier_serial));
+
+	if (!priv->membase)
+		return -ENOMEM;
+
+	return 0;
+}
 
-__weak struct serial_device *default_serial_console(void)
+static int uniphier_serial_remove(struct udevice *dev)
 {
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0)
-	return &uniphier_serial0_device;
-#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1)
-	return &uniphier_serial1_device;
-#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2)
-	return &uniphier_serial2_device;
-#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3)
-	return &uniphier_serial3_device;
-#else
-#error "No uniphier serial ports configured."
-#endif
+	unmap_sysmem(uniphier_serial_port(dev));
+
+	return 0;
 }
 
-void uniphier_serial_initialize(void)
+#ifdef CONFIG_OF_CONTROL
+static const struct udevice_id uniphier_uart_of_match = {
+	{ .compatible = "panasonic,uniphier-uart"},
+	{},
+};
+
+static int uniphier_serial_ofdata_to_platdata(struct udevice *dev)
 {
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0)
-	serial_register(&uniphier_serial0_device);
-#endif
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1)
-	serial_register(&uniphier_serial1_device);
-#endif
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2)
-	serial_register(&uniphier_serial2_device);
-#endif
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3)
-	serial_register(&uniphier_serial3_device);
-#endif
+	/*
+	 * TODO: Masahiro Yamada (yamada.m@jp.panasonic.com)
+	 *
+	 * Implement conversion code from DTB to platform data
+	 * when supporting CONFIG_OF_CONTROL on UniPhir platform.
+	 */
 }
+#endif
+
+static const struct dm_serial_ops uniphier_serial_ops = {
+	.setbrg = uniphier_serial_setbrg,
+	.getc = uniphier_serial_getc,
+	.putc = uniphier_serial_putc,
+	.pending = uniphier_serial_pending,
+};
+
+U_BOOT_DRIVER(uniphier_serial) = {
+	.name = DRIVER_NAME,
+	.id = UCLASS_SERIAL,
+	.of_match = of_match_ptr(uniphier_uart_of_match),
+	.ofdata_to_platdata = of_match_ptr(uniphier_serial_ofdata_to_platdata),
+	.probe = uniphier_serial_probe,
+	.remove = uniphier_serial_remove,
+	.priv_auto_alloc_size = sizeof(struct uniphier_serial_private_data),
+	.platdata_auto_alloc_size =
+				sizeof(struct uniphier_serial_platform_data),
+	.ops = &uniphier_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
new file mode 100644
index 00000000000..3d4baa51d62
--- /dev/null
+++ b/drivers/soc/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the U-boot SOC specific device drivers.
+#
+
+obj-$(CONFIG_ARCH_KEYSTONE)	+= keystone/
diff --git a/drivers/soc/keystone/Makefile b/drivers/soc/keystone/Makefile
new file mode 100644
index 00000000000..c000ecac760
--- /dev/null
+++ b/drivers/soc/keystone/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_TI_KEYSTONE_SERDES) += keystone_serdes.o
diff --git a/drivers/soc/keystone/keystone_serdes.c b/drivers/soc/keystone/keystone_serdes.c
new file mode 100644
index 00000000000..dd5eac9bb3e
--- /dev/null
+++ b/drivers/soc/keystone/keystone_serdes.c
@@ -0,0 +1,210 @@
+/*
+ * TI serdes driver for keystone2.
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <errno.h>
+#include <common.h>
+#include <asm/ti-common/keystone_serdes.h>
+
+#define SERDES_CMU_REGS(x)		(0x0000 + (0x0c00 * (x)))
+#define SERDES_LANE_REGS(x)		(0x0200 + (0x200 * (x)))
+#define SERDES_COMLANE_REGS		0x0a00
+#define SERDES_WIZ_REGS			0x1fc0
+
+#define SERDES_CMU_REG_000(x)		(SERDES_CMU_REGS(x) + 0x000)
+#define SERDES_CMU_REG_010(x)		(SERDES_CMU_REGS(x) + 0x010)
+#define SERDES_COMLANE_REG_000		(SERDES_COMLANE_REGS + 0x000)
+#define SERDES_LANE_REG_000(x)		(SERDES_LANE_REGS(x) + 0x000)
+#define SERDES_LANE_REG_028(x)		(SERDES_LANE_REGS(x) + 0x028)
+#define SERDES_LANE_CTL_STATUS_REG(x)	(SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
+#define SERDES_PLL_CTL_REG		(SERDES_WIZ_REGS + 0x0034)
+
+#define SERDES_RESET			BIT(28)
+#define SERDES_LANE_RESET		BIT(29)
+#define SERDES_LANE_LOOPBACK		BIT(30)
+#define SERDES_LANE_EN_VAL(x, y, z)	(x[y] | (z << 26) | (z << 10))
+
+#define SERDES_CMU_CFG_NUM		5
+#define SERDES_COMLANE_CFG_NUM		10
+#define SERDES_LANE_CFG_NUM		10
+
+struct serdes_cfg {
+	u32 ofs;
+	u32 val;
+	u32 mask;
+};
+
+struct cfg_entry {
+	enum ks2_serdes_clock clk;
+	enum ks2_serdes_rate rate;
+	struct serdes_cfg cmu[SERDES_CMU_CFG_NUM];
+	struct serdes_cfg comlane[SERDES_COMLANE_CFG_NUM];
+	struct serdes_cfg lane[SERDES_LANE_CFG_NUM];
+};
+
+/* SERDES PHY lane enable configuration value, indexed by PHY interface */
+static u32 serdes_cfg_lane_enable[] = {
+	0xf000f0c0,     /* SGMII */
+	0xf0e9f038,     /* PCSR */
+};
+
+/* SERDES PHY PLL enable configuration value, indexed by PHY interface  */
+static u32 serdes_cfg_pll_enable[] = {
+	0xe0000000,     /* SGMII */
+	0xee000000,     /* PCSR */
+};
+
+/**
+ * Array to hold all possible serdes configurations.
+ * Combination for 5 clock settings and 6 baud rates.
+ */
+static struct cfg_entry cfgs[] = {
+	{
+		.clk = SERDES_CLOCK_156P25M,
+		.rate = SERDES_RATE_5G,
+		.cmu = {
+			{0x0000, 0x00800000, 0xffff0000},
+			{0x0014, 0x00008282, 0x0000ffff},
+			{0x0060, 0x00142438, 0x00ffffff},
+			{0x0064, 0x00c3c700, 0x00ffff00},
+			{0x0078, 0x0000c000, 0x0000ff00}
+		},
+		.comlane = {
+			{0x0a00, 0x00000800, 0x0000ff00},
+			{0x0a08, 0x38a20000, 0xffff0000},
+			{0x0a30, 0x008a8a00, 0x00ffff00},
+			{0x0a84, 0x00000600, 0x0000ff00},
+			{0x0a94, 0x10000000, 0xff000000},
+			{0x0aa0, 0x81000000, 0xff000000},
+			{0x0abc, 0xff000000, 0xff000000},
+			{0x0ac0, 0x0000008b, 0x000000ff},
+			{0x0b08, 0x583f0000, 0xffff0000},
+			{0x0b0c, 0x0000004e, 0x000000ff}
+		},
+		.lane = {
+			{0x0004, 0x38000080, 0xff0000ff},
+			{0x0008, 0x00000000, 0x000000ff},
+			{0x000c, 0x02000000, 0xff000000},
+			{0x0010, 0x1b000000, 0xff000000},
+			{0x0014, 0x00006fb8, 0x0000ffff},
+			{0x0018, 0x758000e4, 0xffff00ff},
+			{0x00ac, 0x00004400, 0x0000ff00},
+			{0x002c, 0x00100800, 0x00ffff00},
+			{0x0080, 0x00820082, 0x00ff00ff},
+			{0x0084, 0x1d0f0385, 0xffffffff}
+		},
+	},
+};
+
+static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask)
+{
+	writel(((readl(addr) & (~mask)) | (value & mask)), addr);
+}
+
+static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size)
+{
+	u32 i;
+
+	for (i = 0; i < size; i++)
+		ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask);
+}
+
+static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane,
+				   u32 size, u32 lane)
+{
+	u32 i;
+
+	for (i = 0; i < size; i++)
+		ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane),
+			       cfg_lane[i].val, cfg_lane[i].mask);
+}
+
+static int ks2_serdes_init_cfg(u32 base, struct cfg_entry *cfg, u32 num_lanes)
+{
+	u32 i;
+
+	ks2_serdes_cfg_setup(base, cfg->cmu, SERDES_CMU_CFG_NUM);
+	ks2_serdes_cfg_setup(base, cfg->comlane, SERDES_COMLANE_CFG_NUM);
+
+	for (i = 0; i < num_lanes; i++)
+		ks2_serdes_lane_config(base, cfg->lane, SERDES_LANE_CFG_NUM, i);
+
+	return 0;
+}
+
+static void ks2_serdes_cmu_comlane_enable(u32 base, struct ks2_serdes *serdes)
+{
+	/* Bring SerDes out of Reset */
+	ks2_serdes_rmw(base + SERDES_CMU_REG_010(0), 0x0, SERDES_RESET);
+	if (serdes->intf == SERDES_PHY_PCSR)
+		ks2_serdes_rmw(base + SERDES_CMU_REG_010(1), 0x0, SERDES_RESET);
+
+	/* Enable CMU and COMLANE */
+	ks2_serdes_rmw(base + SERDES_CMU_REG_000(0), 0x03, 0x000000ff);
+	if (serdes->intf == SERDES_PHY_PCSR)
+		ks2_serdes_rmw(base + SERDES_CMU_REG_000(1), 0x03, 0x000000ff);
+
+	ks2_serdes_rmw(base + SERDES_COMLANE_REG_000, 0x5f, 0x000000ff);
+}
+
+static void ks2_serdes_pll_enable(u32 base, struct ks2_serdes *serdes)
+{
+	writel(serdes_cfg_pll_enable[serdes->intf],
+	       base + SERDES_PLL_CTL_REG);
+}
+
+static void ks2_serdes_lane_reset(u32 base, u32 reset, u32 lane)
+{
+	if (reset)
+		ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane),
+			       0x1, SERDES_LANE_RESET);
+	else
+		ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane),
+			       0x0, SERDES_LANE_RESET);
+}
+
+static void ks2_serdes_lane_enable(u32 base,
+				   struct ks2_serdes *serdes, u32 lane)
+{
+	/* Bring lane out of reset */
+	ks2_serdes_lane_reset(base, 0, lane);
+
+	writel(SERDES_LANE_EN_VAL(serdes_cfg_lane_enable, serdes->intf,
+				  serdes->rate_mode),
+	       base + SERDES_LANE_CTL_STATUS_REG(lane));
+
+	/* Set NES bit if Loopback Enabled */
+	if (serdes->loopback)
+		ks2_serdes_rmw(base + SERDES_LANE_REG_000(lane),
+			       0x1, SERDES_LANE_LOOPBACK);
+}
+
+int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes)
+{
+	int i;
+	int ret = 0;
+
+	for (i = 0; i < ARRAY_SIZE(cfgs); i++)
+		if (serdes->clk == cfgs[i].clk && serdes->rate == cfgs[i].rate)
+			break;
+
+	if (i >= ARRAY_SIZE(cfgs)) {
+		puts("Cannot find keystone SerDes configuration");
+		return -EINVAL;
+	}
+
+	ks2_serdes_init_cfg(base, &cfgs[i], num_lanes);
+
+	ks2_serdes_cmu_comlane_enable(base, serdes);
+	for (i = 0; i < num_lanes; i++)
+		ks2_serdes_lane_enable(base, serdes, i);
+
+	ks2_serdes_pll_enable(base, serdes);
+
+	return ret;
+}
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index e69de29bb2d..e1678e63e6a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -0,0 +1,6 @@
+config DM_SPI
+	bool "Enable Driver Model for SPI drivers"
+	depends on DM
+	help
+	  If you want to use driver model for SPI drivers, say Y.
+	  To use legacy SPI drivers, say N.
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index f02c35a52c0..eabbf27d4d0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -6,7 +6,14 @@
 #
 
 # There are many options which enable SPI, so make this library available
+ifdef CONFIG_DM_SPI
+obj-y += spi-uclass.o
+obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
+obj-$(CONFIG_SOFT_SPI) += soft_spi.o
+else
 obj-y += spi.o
+obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o
+endif
 
 obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o
 obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
@@ -30,11 +37,9 @@ obj-$(CONFIG_MXS_SPI) += mxs_spi.o
 obj-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
 obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
-obj-$(CONFIG_SOFT_SPI) += soft_spi.o
 obj-$(CONFIG_SH_SPI) += sh_spi.o
 obj-$(CONFIG_SH_QSPI) += sh_qspi.o
 obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
-obj-$(CONFIG_FDT_SPI) += fdt_spi.o
 obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
 obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c
index 5accbb5c22c..a4d03d97cfc 100644
--- a/drivers/spi/altera_spi.c
+++ b/drivers/spi/altera_spi.c
@@ -12,58 +12,62 @@
 #include <malloc.h>
 #include <spi.h>
 
-#define ALTERA_SPI_RXDATA	0
-#define ALTERA_SPI_TXDATA	4
-#define ALTERA_SPI_STATUS	8
-#define ALTERA_SPI_CONTROL	12
-#define ALTERA_SPI_SLAVE_SEL	20
-
-#define ALTERA_SPI_STATUS_ROE_MSK	(0x8)
-#define ALTERA_SPI_STATUS_TOE_MSK	(0x10)
-#define ALTERA_SPI_STATUS_TMT_MSK	(0x20)
-#define ALTERA_SPI_STATUS_TRDY_MSK	(0x40)
-#define ALTERA_SPI_STATUS_RRDY_MSK	(0x80)
-#define ALTERA_SPI_STATUS_E_MSK	(0x100)
-
-#define ALTERA_SPI_CONTROL_IROE_MSK	(0x8)
-#define ALTERA_SPI_CONTROL_ITOE_MSK	(0x10)
-#define ALTERA_SPI_CONTROL_ITRDY_MSK	(0x40)
-#define ALTERA_SPI_CONTROL_IRRDY_MSK	(0x80)
-#define ALTERA_SPI_CONTROL_IE_MSK	(0x100)
-#define ALTERA_SPI_CONTROL_SSO_MSK	(0x400)
+#ifndef CONFIG_ALTERA_SPI_IDLE_VAL
+#define CONFIG_ALTERA_SPI_IDLE_VAL 0xff
+#endif
 
 #ifndef CONFIG_SYS_ALTERA_SPI_LIST
 #define CONFIG_SYS_ALTERA_SPI_LIST { CONFIG_SYS_SPI_BASE }
 #endif
 
+struct altera_spi_regs {
+	u32	rxdata;
+	u32	txdata;
+	u32	status;
+	u32	control;
+	u32	_reserved;
+	u32	slave_sel;
+};
+
+#define ALTERA_SPI_STATUS_ROE_MSK	(1 << 3)
+#define ALTERA_SPI_STATUS_TOE_MSK	(1 << 4)
+#define ALTERA_SPI_STATUS_TMT_MSK	(1 << 5)
+#define ALTERA_SPI_STATUS_TRDY_MSK	(1 << 6)
+#define ALTERA_SPI_STATUS_RRDY_MSK	(1 << 7)
+#define ALTERA_SPI_STATUS_E_MSK		(1 << 8)
+
+#define ALTERA_SPI_CONTROL_IROE_MSK	(1 << 3)
+#define ALTERA_SPI_CONTROL_ITOE_MSK	(1 << 4)
+#define ALTERA_SPI_CONTROL_ITRDY_MSK	(1 << 6)
+#define ALTERA_SPI_CONTROL_IRRDY_MSK	(1 << 7)
+#define ALTERA_SPI_CONTROL_IE_MSK	(1 << 8)
+#define ALTERA_SPI_CONTROL_SSO_MSK	(1 << 10)
+
 static ulong altera_spi_base_list[] = CONFIG_SYS_ALTERA_SPI_LIST;
 
 struct altera_spi_slave {
-	struct spi_slave slave;
-	ulong base;
+	struct spi_slave	slave;
+	struct altera_spi_regs	*regs;
 };
 #define to_altera_spi_slave(s) container_of(s, struct altera_spi_slave, slave)
 
-__attribute__((weak))
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+__weak int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
 	return bus < ARRAY_SIZE(altera_spi_base_list) && cs < 32;
 }
 
-__attribute__((weak))
-void spi_cs_activate(struct spi_slave *slave)
+__weak void spi_cs_activate(struct spi_slave *slave)
 {
 	struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
-	writel(1 << slave->cs, altspi->base + ALTERA_SPI_SLAVE_SEL);
-	writel(ALTERA_SPI_CONTROL_SSO_MSK, altspi->base + ALTERA_SPI_CONTROL);
+	writel(1 << slave->cs, &altspi->regs->slave_sel);
+	writel(ALTERA_SPI_CONTROL_SSO_MSK, &altspi->regs->control);
 }
 
-__attribute__((weak))
-void spi_cs_deactivate(struct spi_slave *slave)
+__weak void spi_cs_deactivate(struct spi_slave *slave)
 {
 	struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
-	writel(0, altspi->base + ALTERA_SPI_CONTROL);
-	writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL);
+	writel(0, &altspi->regs->control);
+	writel(0, &altspi->regs->slave_sel);
 }
 
 void spi_init(void)
@@ -87,9 +91,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	if (!altspi)
 		return NULL;
 
-	altspi->base = altera_spi_base_list[bus];
-	debug("%s: bus:%i cs:%i base:%lx\n", __func__,
-		bus, cs, altspi->base);
+	altspi->regs = (struct altera_spi_regs *)altera_spi_base_list[bus];
+	debug("%s: bus:%i cs:%i base:%p\n", __func__, bus, cs, altspi->regs);
 
 	return &altspi->slave;
 }
@@ -105,8 +108,8 @@ int spi_claim_bus(struct spi_slave *slave)
 	struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
 
 	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
-	writel(0, altspi->base + ALTERA_SPI_CONTROL);
-	writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL);
+	writel(0, &altspi->regs->control);
+	writel(0, &altspi->regs->slave_sel);
 	return 0;
 }
 
@@ -115,24 +118,22 @@ void spi_release_bus(struct spi_slave *slave)
 	struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
 
 	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
-	writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL);
+	writel(0, &altspi->regs->slave_sel);
 }
 
-#ifndef CONFIG_ALTERA_SPI_IDLE_VAL
-# define CONFIG_ALTERA_SPI_IDLE_VAL 0xff
-#endif
-
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	     void *din, unsigned long flags)
 {
 	struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
 	/* assume spi core configured to do 8 bit transfers */
-	uint bytes = bitlen / 8;
-	const uchar *txp = dout;
-	uchar *rxp = din;
+	unsigned int bytes = bitlen / 8;
+	const unsigned char *txp = dout;
+	unsigned char *rxp = din;
+	uint32_t reg, data, start;
 
 	debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
-		slave->bus, slave->cs, bitlen, bytes, flags);
+	      slave->bus, slave->cs, bitlen, bytes, flags);
+
 	if (bitlen == 0)
 		goto done;
 
@@ -142,25 +143,40 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	}
 
 	/* empty read buffer */
-	if (readl(altspi->base + ALTERA_SPI_STATUS) &
-	    ALTERA_SPI_STATUS_RRDY_MSK)
-		readl(altspi->base + ALTERA_SPI_RXDATA);
+	if (readl(&altspi->regs->status) & ALTERA_SPI_STATUS_RRDY_MSK)
+		readl(&altspi->regs->rxdata);
+
 	if (flags & SPI_XFER_BEGIN)
 		spi_cs_activate(slave);
 
 	while (bytes--) {
-		uchar d = txp ? *txp++ : CONFIG_ALTERA_SPI_IDLE_VAL;
-		debug("%s: tx:%x ", __func__, d);
-		writel(d, altspi->base + ALTERA_SPI_TXDATA);
-		while (!(readl(altspi->base + ALTERA_SPI_STATUS) &
-			 ALTERA_SPI_STATUS_RRDY_MSK))
-			;
-		d = readl(altspi->base + ALTERA_SPI_RXDATA);
+		if (txp)
+			data = *txp++;
+		else
+			data = CONFIG_ALTERA_SPI_IDLE_VAL;
+
+		debug("%s: tx:%x ", __func__, data);
+		writel(data, &altspi->regs->txdata);
+
+		start = get_timer(0);
+		while (1) {
+			reg = readl(&altspi->regs->status);
+			if (reg & ALTERA_SPI_STATUS_RRDY_MSK)
+				break;
+			if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
+				printf("%s: Transmission timed out!\n", __func__);
+				goto done;
+			}
+		}
+
+		data = readl(&altspi->regs->rxdata);
 		if (rxp)
-			*rxp++ = d;
-		debug("rx:%x\n", d);
+			*rxp++ = data & 0xff;
+
+		debug("rx:%x\n", data);
 	}
- done:
+
+done:
 	if (flags & SPI_XFER_END)
 		spi_cs_deactivate(slave);
 
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index 2969184ee87..f078973531c 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -6,6 +6,8 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
 #include <malloc.h>
 #include <spi.h>
 #include <fdtdec.h>
@@ -19,176 +21,35 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* Information about each SPI controller */
-struct spi_bus {
+struct exynos_spi_platdata {
 	enum periph_id periph_id;
 	s32 frequency;		/* Default clock frequency, -1 for none */
 	struct exynos_spi *regs;
-	int inited;		/* 1 if this bus is ready for use */
-	int node;
 	uint deactivate_delay_us;	/* Delay to wait after deactivate */
 };
 
-/* A list of spi buses that we know about */
-static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS];
-static unsigned int bus_count;
-
-struct exynos_spi_slave {
-	struct spi_slave slave;
+struct exynos_spi_priv {
 	struct exynos_spi *regs;
 	unsigned int freq;		/* Default frequency */
 	unsigned int mode;
 	enum periph_id periph_id;	/* Peripheral ID for this device */
 	unsigned int fifo_size;
 	int skip_preamble;
-	struct spi_bus *bus;		/* Pointer to our SPI bus info */
 	ulong last_transaction_us;	/* Time of last transaction end */
 };
 
-static struct spi_bus *spi_get_bus(unsigned dev_index)
-{
-	if (dev_index < bus_count)
-		return &spi_bus[dev_index];
-	debug("%s: invalid bus %d", __func__, dev_index);
-
-	return NULL;
-}
-
-static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave)
-{
-	return container_of(slave, struct exynos_spi_slave, slave);
-}
-
-/**
- * Setup the driver private data
- *
- * @param bus		ID of the bus that the slave is attached to
- * @param cs		ID of the chip select connected to the slave
- * @param max_hz	Required spi frequency
- * @param mode		Required spi mode (clk polarity, clk phase and
- *			master or slave)
- * @return new device or NULL
- */
-struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
-			unsigned int max_hz, unsigned int mode)
-{
-	struct exynos_spi_slave *spi_slave;
-	struct spi_bus *bus;
-
-	if (!spi_cs_is_valid(busnum, cs)) {
-		debug("%s: Invalid bus/chip select %d, %d\n", __func__,
-		      busnum, cs);
-		return NULL;
-	}
-
-	spi_slave = spi_alloc_slave(struct exynos_spi_slave, busnum, cs);
-	if (!spi_slave) {
-		debug("%s: Could not allocate spi_slave\n", __func__);
-		return NULL;
-	}
-
-	bus = &spi_bus[busnum];
-	spi_slave->bus = bus;
-	spi_slave->regs = bus->regs;
-	spi_slave->mode = mode;
-	spi_slave->periph_id = bus->periph_id;
-	if (bus->periph_id == PERIPH_ID_SPI1 ||
-	    bus->periph_id == PERIPH_ID_SPI2)
-		spi_slave->fifo_size = 64;
-	else
-		spi_slave->fifo_size = 256;
-
-	spi_slave->skip_preamble = 0;
-	spi_slave->last_transaction_us = timer_get_us();
-
-	spi_slave->freq = bus->frequency;
-	if (max_hz)
-		spi_slave->freq = min(max_hz, spi_slave->freq);
-
-	return &spi_slave->slave;
-}
-
-/**
- * Free spi controller
- *
- * @param slave	Pointer to spi_slave to which controller has to
- *		communicate with
- */
-void spi_free_slave(struct spi_slave *slave)
-{
-	struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
-
-	free(spi_slave);
-}
-
 /**
  * Flush spi tx, rx fifos and reset the SPI controller
  *
- * @param slave	Pointer to spi_slave to which controller has to
- *		communicate with
+ * @param regs	Pointer to SPI registers
  */
-static void spi_flush_fifo(struct spi_slave *slave)
+static void spi_flush_fifo(struct exynos_spi *regs)
 {
-	struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
-	struct exynos_spi *regs = spi_slave->regs;
-
 	clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
 	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
 	setbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
 }
 
-/**
- * Initialize the spi base registers, set the required clock frequency and
- * initialize the gpios
- *
- * @param slave	Pointer to spi_slave to which controller has to
- *		communicate with
- * @return zero on success else a negative value
- */
-int spi_claim_bus(struct spi_slave *slave)
-{
-	struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
-	struct exynos_spi *regs = spi_slave->regs;
-	u32 reg = 0;
-	int ret;
-
-	ret = set_spi_clk(spi_slave->periph_id,
-					spi_slave->freq);
-	if (ret < 0) {
-		debug("%s: Failed to setup spi clock\n", __func__);
-		return ret;
-	}
-
-	exynos_pinmux_config(spi_slave->periph_id, PINMUX_FLAG_NONE);
-
-	spi_flush_fifo(slave);
-
-	reg = readl(&regs->ch_cfg);
-	reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
-
-	if (spi_slave->mode & SPI_CPHA)
-		reg |= SPI_CH_CPHA_B;
-
-	if (spi_slave->mode & SPI_CPOL)
-		reg |= SPI_CH_CPOL_L;
-
-	writel(reg, &regs->ch_cfg);
-	writel(SPI_FB_DELAY_180, &regs->fb_clk);
-
-	return 0;
-}
-
-/**
- * Reset the spi H/W and flush the tx and rx fifos
- *
- * @param slave	Pointer to spi_slave to which controller has to
- *		communicate with
- */
-void spi_release_bus(struct spi_slave *slave)
-{
-	spi_flush_fifo(slave);
-}
-
 static void spi_get_fifo_levels(struct exynos_spi *regs,
 	int *rx_lvl, int *tx_lvl)
 {
@@ -208,6 +69,8 @@ static void spi_get_fifo_levels(struct exynos_spi *regs,
  */
 static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
 {
+	debug("%s: regs=%p, count=%d, step=%d\n", __func__, regs, count, step);
+
 	/* For word address we need to swap bytes */
 	if (step == 4) {
 		setbits_le32(&regs->mode_cfg,
@@ -230,10 +93,10 @@ static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
 	writel(count | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
 }
 
-static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
+static int spi_rx_tx(struct exynos_spi_priv *priv, int todo,
 			void **dinp, void const **doutp, unsigned long flags)
 {
-	struct exynos_spi *regs = spi_slave->regs;
+	struct exynos_spi *regs = priv->regs;
 	uchar *rxp = *dinp;
 	const uchar *txp = *doutp;
 	int rx_lvl, tx_lvl;
@@ -245,8 +108,8 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
 
 	out_bytes = in_bytes = todo;
 
-	stopping = spi_slave->skip_preamble && (flags & SPI_XFER_END) &&
-					!(spi_slave->mode & SPI_SLAVE);
+	stopping = priv->skip_preamble && (flags & SPI_XFER_END) &&
+					!(priv->mode & SPI_SLAVE);
 
 	/*
 	 * Try to transfer words if we can. This helps read performance at
@@ -254,7 +117,7 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
 	 */
 	step = 1;
 	if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) &&
-	    !spi_slave->skip_preamble)
+	    !priv->skip_preamble)
 		step = 4;
 
 	/*
@@ -279,7 +142,7 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
 		 * Don't completely fill the txfifo, since we don't want our
 		 * rxfifo to overflow, and it may already contain data.
 		 */
-		while (tx_lvl < spi_slave->fifo_size/2 && out_bytes) {
+		while (tx_lvl < priv->fifo_size/2 && out_bytes) {
 			if (!txp)
 				temp = -1;
 			else if (step == 4)
@@ -295,9 +158,9 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
 		if (rx_lvl >= step) {
 			while (rx_lvl >= step) {
 				temp = readl(&regs->rx_data);
-				if (spi_slave->skip_preamble) {
+				if (priv->skip_preamble) {
 					if (temp == SPI_PREAMBLE_END_BYTE) {
-						spi_slave->skip_preamble = 0;
+						priv->skip_preamble = 0;
 						stopping = 0;
 					}
 				} else {
@@ -326,7 +189,7 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
 			txp = NULL;
 			spi_request_bytes(regs, toread, step);
 		}
-		if (spi_slave->skip_preamble && get_timer(start) > 100) {
+		if (priv->skip_preamble && get_timer(start) > 100) {
 			printf("SPI timeout: in_bytes=%d, out_bytes=%d, ",
 			       in_bytes, out_bytes);
 			return -1;
@@ -340,94 +203,29 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
 }
 
 /**
- * Transfer and receive data
- *
- * @param slave		Pointer to spi_slave to which controller has to
- *			communicate with
- * @param bitlen	No of bits to tranfer or receive
- * @param dout		Pointer to transfer buffer
- * @param din		Pointer to receive buffer
- * @param flags		Flags for transfer begin and end
- * @return zero on success else a negative value
- */
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
-	     void *din, unsigned long flags)
-{
-	struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
-	int upto, todo;
-	int bytelen;
-	int ret = 0;
-
-	/* spi core configured to do 8 bit transfers */
-	if (bitlen % 8) {
-		debug("Non byte aligned SPI transfer.\n");
-		return -1;
-	}
-
-	/* Start the transaction, if necessary. */
-	if ((flags & SPI_XFER_BEGIN))
-		spi_cs_activate(slave);
-
-	/*
-	 * Exynos SPI limits each transfer to 65535 transfers. To keep
-	 * things simple, allow a maximum of 65532 bytes. We could allow
-	 * more in word mode, but the performance difference is small.
-	 */
-	bytelen =  bitlen / 8;
-	for (upto = 0; !ret && upto < bytelen; upto += todo) {
-		todo = min(bytelen - upto, (1 << 16) - 4);
-		ret = spi_rx_tx(spi_slave, todo, &din, &dout, flags);
-		if (ret)
-			break;
-	}
-
-	/* Stop the transaction, if necessary. */
-	if ((flags & SPI_XFER_END) && !(spi_slave->mode & SPI_SLAVE)) {
-		spi_cs_deactivate(slave);
-		if (spi_slave->skip_preamble) {
-			assert(!spi_slave->skip_preamble);
-			debug("Failed to complete premable transaction\n");
-			ret = -1;
-		}
-	}
-
-	return ret;
-}
-
-/**
- * Validates the bus and chip select numbers
- *
- * @param bus	ID of the bus that the slave is attached to
- * @param cs	ID of the chip select connected to the slave
- * @return one on success else zero
- */
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return spi_get_bus(bus) && cs == 0;
-}
-
-/**
  * Activate the CS by driving it LOW
  *
  * @param slave	Pointer to spi_slave to which controller has to
  *		communicate with
  */
-void spi_cs_activate(struct spi_slave *slave)
+static void spi_cs_activate(struct udevice *dev)
 {
-	struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+	struct udevice *bus = dev->parent;
+	struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
+	struct exynos_spi_priv *priv = dev_get_priv(bus);
 
 	/* If it's too soon to do another transaction, wait */
-	if (spi_slave->bus->deactivate_delay_us &&
-	    spi_slave->last_transaction_us) {
+	if (pdata->deactivate_delay_us &&
+	    priv->last_transaction_us) {
 		ulong delay_us;		/* The delay completed so far */
-		delay_us = timer_get_us() - spi_slave->last_transaction_us;
-		if (delay_us < spi_slave->bus->deactivate_delay_us)
-			udelay(spi_slave->bus->deactivate_delay_us - delay_us);
+		delay_us = timer_get_us() - priv->last_transaction_us;
+		if (delay_us < pdata->deactivate_delay_us)
+			udelay(pdata->deactivate_delay_us - delay_us);
 	}
 
-	clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
-	debug("Activate CS, bus %d\n", spi_slave->slave.bus);
-	spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
+	clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
+	debug("Activate CS, bus '%s'\n", bus->name);
+	priv->skip_preamble = priv->mode & SPI_PREAMBLE;
 }
 
 /**
@@ -436,148 +234,197 @@ void spi_cs_activate(struct spi_slave *slave)
  * @param slave	Pointer to spi_slave to which controller has to
  *		communicate with
  */
-void spi_cs_deactivate(struct spi_slave *slave)
+static void spi_cs_deactivate(struct udevice *dev)
 {
-	struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+	struct udevice *bus = dev->parent;
+	struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
+	struct exynos_spi_priv *priv = dev_get_priv(bus);
 
-	setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
+	setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
 
 	/* Remember time of this transaction so we can honour the bus delay */
-	if (spi_slave->bus->deactivate_delay_us)
-		spi_slave->last_transaction_us = timer_get_us();
+	if (pdata->deactivate_delay_us)
+		priv->last_transaction_us = timer_get_us();
 
-	debug("Deactivate CS, bus %d\n", spi_slave->slave.bus);
+	debug("Deactivate CS, bus '%s'\n", bus->name);
 }
 
-static inline struct exynos_spi *get_spi_base(int dev_index)
+static int exynos_spi_ofdata_to_platdata(struct udevice *bus)
 {
-	if (dev_index < 3)
-		return (struct exynos_spi *)samsung_get_base_spi() + dev_index;
-	else
-		return (struct exynos_spi *)samsung_get_base_spi_isp() +
-					(dev_index - 3);
-}
+	struct exynos_spi_platdata *plat = bus->platdata;
+	const void *blob = gd->fdt_blob;
+	int node = bus->of_offset;
 
-/*
- * Read the SPI config from the device tree node.
- *
- * @param blob  FDT blob to read from
- * @param node  Node offset to read from
- * @param bus   SPI bus structure to fill with information
- * @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing
- */
-#ifdef CONFIG_OF_CONTROL
-static int spi_get_config(const void *blob, int node, struct spi_bus *bus)
-{
-	bus->node = node;
-	bus->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
-	bus->periph_id = pinmux_decode_periph_id(blob, node);
+	plat->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
+	plat->periph_id = pinmux_decode_periph_id(blob, node);
 
-	if (bus->periph_id == PERIPH_ID_NONE) {
+	if (plat->periph_id == PERIPH_ID_NONE) {
 		debug("%s: Invalid peripheral ID %d\n", __func__,
-			bus->periph_id);
+			plat->periph_id);
 		return -FDT_ERR_NOTFOUND;
 	}
 
 	/* Use 500KHz as a suitable default */
-	bus->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
 					500000);
-	bus->deactivate_delay_us = fdtdec_get_int(blob, node,
+	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
 					"spi-deactivate-delay", 0);
+	debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+	      __func__, plat->regs, plat->periph_id, plat->frequency,
+	      plat->deactivate_delay_us);
 
 	return 0;
 }
 
-/*
- * Process a list of nodes, adding them to our list of SPI ports.
- *
- * @param blob          fdt blob
- * @param node_list     list of nodes to process (any <=0 are ignored)
- * @param count         number of nodes to process
- * @param is_dvc        1 if these are DVC ports, 0 if standard I2C
- * @return 0 if ok, -1 on error
- */
-static int process_nodes(const void *blob, int node_list[], int count)
+static int exynos_spi_probe(struct udevice *bus)
 {
-	int i;
+	struct exynos_spi_platdata *plat = dev_get_platdata(bus);
+	struct exynos_spi_priv *priv = dev_get_priv(bus);
 
-	/* build the i2c_controllers[] for each controller */
-	for (i = 0; i < count; i++) {
-		int node = node_list[i];
-		struct spi_bus *bus;
+	priv->regs = plat->regs;
+	if (plat->periph_id == PERIPH_ID_SPI1 ||
+	    plat->periph_id == PERIPH_ID_SPI2)
+		priv->fifo_size = 64;
+	else
+		priv->fifo_size = 256;
 
-		if (node <= 0)
-			continue;
+	priv->skip_preamble = 0;
+	priv->last_transaction_us = timer_get_us();
+	priv->freq = plat->frequency;
+	priv->periph_id = plat->periph_id;
 
-		bus = &spi_bus[i];
-		if (spi_get_config(blob, node, bus)) {
-			printf("exynos spi_init: failed to decode bus %d\n",
-				i);
-			return -1;
-		}
+	return 0;
+}
 
-		debug("spi: controller bus %d at %p, periph_id %d\n",
-		      i, bus->regs, bus->periph_id);
-		bus->inited = 1;
-		bus_count++;
-	}
+static int exynos_spi_claim_bus(struct udevice *bus)
+{
+	struct exynos_spi_priv *priv = dev_get_priv(bus);
+
+	exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE);
+	spi_flush_fifo(priv->regs);
+
+	writel(SPI_FB_DELAY_180, &priv->regs->fb_clk);
 
 	return 0;
 }
-#endif
 
-/**
- * Set up a new SPI slave for an fdt node
- *
- * @param blob		Device tree blob
- * @param node		SPI peripheral node to use
- * @return 0 if ok, -1 on error
- */
-struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
-				      int spi_node)
+static int exynos_spi_release_bus(struct udevice *bus)
 {
-	struct spi_bus *bus;
-	unsigned int i;
+	struct exynos_spi_priv *priv = dev_get_priv(bus);
+
+	spi_flush_fifo(priv->regs);
+
+	return 0;
+}
+
+static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
+			   const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev->parent;
+	struct exynos_spi_priv *priv = dev_get_priv(bus);
+	int upto, todo;
+	int bytelen;
+	int ret = 0;
+
+	/* spi core configured to do 8 bit transfers */
+	if (bitlen % 8) {
+		debug("Non byte aligned SPI transfer.\n");
+		return -1;
+	}
+
+	/* Start the transaction, if necessary. */
+	if ((flags & SPI_XFER_BEGIN))
+		spi_cs_activate(dev);
+
+	/*
+	 * Exynos SPI limits each transfer to 65535 transfers. To keep
+	 * things simple, allow a maximum of 65532 bytes. We could allow
+	 * more in word mode, but the performance difference is small.
+	 */
+	bytelen = bitlen / 8;
+	for (upto = 0; !ret && upto < bytelen; upto += todo) {
+		todo = min(bytelen - upto, (1 << 16) - 4);
+		ret = spi_rx_tx(priv, todo, &din, &dout, flags);
+		if (ret)
+			break;
+	}
 
-	for (i = 0, bus = spi_bus; i < bus_count; i++, bus++) {
-		if (bus->node == spi_node)
-			return spi_base_setup_slave_fdt(blob, i, slave_node);
+	/* Stop the transaction, if necessary. */
+	if ((flags & SPI_XFER_END) && !(priv->mode & SPI_SLAVE)) {
+		spi_cs_deactivate(dev);
+		if (priv->skip_preamble) {
+			assert(!priv->skip_preamble);
+			debug("Failed to complete premable transaction\n");
+			ret = -1;
+		}
 	}
 
-	debug("%s: Failed to find bus node %d\n", __func__, spi_node);
-	return NULL;
+	return ret;
 }
 
-/* Sadly there is no error return from this function */
-void spi_init(void)
+static int exynos_spi_set_speed(struct udevice *bus, uint speed)
 {
-	int count;
+	struct exynos_spi_platdata *plat = bus->platdata;
+	struct exynos_spi_priv *priv = dev_get_priv(bus);
+	int ret;
 
-#ifdef CONFIG_OF_CONTROL
-	int node_list[EXYNOS5_SPI_NUM_CONTROLLERS];
-	const void *blob = gd->fdt_blob;
+	if (speed > plat->frequency)
+		speed = plat->frequency;
+	ret = set_spi_clk(priv->periph_id, speed);
+	if (ret)
+		return ret;
+	priv->freq = speed;
+	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
+
+	return 0;
+}
 
-	count = fdtdec_find_aliases_for_id(blob, "spi",
-			COMPAT_SAMSUNG_EXYNOS_SPI, node_list,
-			EXYNOS5_SPI_NUM_CONTROLLERS);
-	if (process_nodes(blob, node_list, count))
-		return;
+static int exynos_spi_set_mode(struct udevice *bus, uint mode)
+{
+	struct exynos_spi_priv *priv = dev_get_priv(bus);
+	uint32_t reg;
 
-#else
-	struct spi_bus *bus;
+	reg = readl(&priv->regs->ch_cfg);
+	reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
 
-	for (count = 0; count < EXYNOS5_SPI_NUM_CONTROLLERS; count++) {
-		bus = &spi_bus[count];
-		bus->regs = get_spi_base(count);
-		bus->periph_id = PERIPH_ID_SPI0 + count;
+	if (mode & SPI_CPHA)
+		reg |= SPI_CH_CPHA_B;
 
-		/* Although Exynos5 supports upto 50Mhz speed,
-		 * we are setting it to 10Mhz for safe side
-		 */
-		bus->frequency = 10000000;
-		bus->inited = 1;
-		bus->node = 0;
-		bus_count = EXYNOS5_SPI_NUM_CONTROLLERS;
-	}
-#endif
+	if (mode & SPI_CPOL)
+		reg |= SPI_CH_CPOL_L;
+
+	writel(reg, &priv->regs->ch_cfg);
+	priv->mode = mode;
+	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+
+	return 0;
 }
+
+static const struct dm_spi_ops exynos_spi_ops = {
+	.claim_bus	= exynos_spi_claim_bus,
+	.release_bus	= exynos_spi_release_bus,
+	.xfer		= exynos_spi_xfer,
+	.set_speed	= exynos_spi_set_speed,
+	.set_mode	= exynos_spi_set_mode,
+	/*
+	 * cs_info is not needed, since we require all chip selects to be
+	 * in the device tree explicitly
+	 */
+};
+
+static const struct udevice_id exynos_spi_ids[] = {
+	{ .compatible = "samsung,exynos-spi" },
+	{ }
+};
+
+U_BOOT_DRIVER(exynos_spi) = {
+	.name	= "exynos_spi",
+	.id	= UCLASS_SPI,
+	.of_match = exynos_spi_ids,
+	.ops	= &exynos_spi_ops,
+	.ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata),
+	.priv_auto_alloc_size = sizeof(struct exynos_spi_priv),
+	.per_child_auto_alloc_size	= sizeof(struct spi_slave),
+	.probe	= exynos_spi_probe,
+};
diff --git a/drivers/spi/fdt_spi.c b/drivers/spi/fdt_spi.c
deleted file mode 100644
index 58f139a54ea..00000000000
--- a/drivers/spi/fdt_spi.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * Common fdt based SPI driver front end
- *
- * Copyright (c) 2013 NVIDIA Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/clock.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra20/tegra20_sflash.h>
-#include <asm/arch-tegra20/tegra20_slink.h>
-#include <asm/arch-tegra114/tegra114_spi.h>
-#include <spi.h>
-#include <fdtdec.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct fdt_spi_driver {
-	int compat;
-	int max_ctrls;
-	int (*init)(int *node_list, int count);
-	int (*claim_bus)(struct spi_slave *slave);
-	int (*release_bus)(struct spi_slave *slave);
-	int (*cs_is_valid)(unsigned int bus, unsigned int cs);
-	struct spi_slave *(*setup_slave)(unsigned int bus, unsigned int cs,
-					unsigned int max_hz, unsigned int mode);
-	void (*free_slave)(struct spi_slave *slave);
-	void (*cs_activate)(struct spi_slave *slave);
-	void (*cs_deactivate)(struct spi_slave *slave);
-	int (*xfer)(struct spi_slave *slave, unsigned int bitlen,
-		    const void *data_out, void *data_in, unsigned long flags);
-};
-
-static struct fdt_spi_driver fdt_spi_drivers[] = {
-#ifdef CONFIG_TEGRA20_SFLASH
-	{
-		.compat		= COMPAT_NVIDIA_TEGRA20_SFLASH,
-		.max_ctrls	= 1,
-		.init		= tegra20_spi_init,
-		.claim_bus	= tegra20_spi_claim_bus,
-		.cs_is_valid	= tegra20_spi_cs_is_valid,
-		.setup_slave	= tegra20_spi_setup_slave,
-		.free_slave	= tegra20_spi_free_slave,
-		.cs_activate	= tegra20_spi_cs_activate,
-		.cs_deactivate	= tegra20_spi_cs_deactivate,
-		.xfer		= tegra20_spi_xfer,
-	},
-#endif
-#ifdef CONFIG_TEGRA20_SLINK
-	{
-		.compat		= COMPAT_NVIDIA_TEGRA20_SLINK,
-		.max_ctrls	= CONFIG_TEGRA_SLINK_CTRLS,
-		.init		= tegra30_spi_init,
-		.claim_bus	= tegra30_spi_claim_bus,
-		.cs_is_valid	= tegra30_spi_cs_is_valid,
-		.setup_slave	= tegra30_spi_setup_slave,
-		.free_slave	= tegra30_spi_free_slave,
-		.cs_activate	= tegra30_spi_cs_activate,
-		.cs_deactivate	= tegra30_spi_cs_deactivate,
-		.xfer		= tegra30_spi_xfer,
-	},
-#endif
-#ifdef CONFIG_TEGRA114_SPI
-	{
-		.compat		= COMPAT_NVIDIA_TEGRA114_SPI,
-		.max_ctrls	= CONFIG_TEGRA114_SPI_CTRLS,
-		.init		= tegra114_spi_init,
-		.claim_bus	= tegra114_spi_claim_bus,
-		.cs_is_valid	= tegra114_spi_cs_is_valid,
-		.setup_slave	= tegra114_spi_setup_slave,
-		.free_slave	= tegra114_spi_free_slave,
-		.cs_activate	= tegra114_spi_cs_activate,
-		.cs_deactivate	= tegra114_spi_cs_deactivate,
-		.xfer		= tegra114_spi_xfer,
-	},
-#endif
-};
-
-static struct fdt_spi_driver *driver;
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	if (!driver)
-		return 0;
-	else if (!driver->cs_is_valid)
-		return 1;
-	else
-		return driver->cs_is_valid(bus, cs);
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-		unsigned int max_hz, unsigned int mode)
-{
-	if (!driver || !driver->setup_slave)
-		return NULL;
-
-	return driver->setup_slave(bus, cs, max_hz, mode);
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-	if (driver && driver->free_slave)
-		return driver->free_slave(slave);
-}
-
-static int spi_init_driver(struct fdt_spi_driver *driver)
-{
-	int count;
-	int node_list[driver->max_ctrls];
-
-	count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi",
-					   driver->compat,
-					   node_list,
-					   driver->max_ctrls);
-	return driver->init(node_list, count);
-}
-
-void spi_init(void)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(fdt_spi_drivers); i++) {
-		driver = &fdt_spi_drivers[i];
-		if (!spi_init_driver(driver))
-			break;
-	}
-	if (i == ARRAY_SIZE(fdt_spi_drivers))
-		driver = NULL;
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-	if (!driver)
-		return 1;
-	if (!driver->claim_bus)
-		return 0;
-
-	return driver->claim_bus(slave);
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-	if (driver && driver->release_bus)
-		driver->release_bus(slave);
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	if (driver && driver->cs_activate)
-		driver->cs_activate(slave);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	if (driver && driver->cs_deactivate)
-		driver->cs_deactivate(slave);
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-	     const void *data_out, void *data_in, unsigned long flags)
-{
-	if (!driver || !driver->xfer)
-		return -1;
-
-	return driver->xfer(slave, bitlen, data_out, data_in, flags);
-}
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index 3d58bcc1b95..e7b0982fb65 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -12,23 +12,30 @@
 #include <malloc.h>
 #include <spi.h>
 #include <asm/io.h>
-#include <asm/arch/kirkwood.h>
-#include <asm/arch/spi.h>
+#include <asm/arch/soc.h>
+#ifdef CONFIG_KIRKWOOD
 #include <asm/arch/mpp.h>
+#endif
+#include <asm/arch-mvebu/spi.h>
 
-static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE;
+static struct kwspi_registers *spireg =
+	(struct kwspi_registers *)MVEBU_SPI_BASE;
 
+#ifdef CONFIG_KIRKWOOD
 static u32 cs_spi_mpp_back[2];
+#endif
 
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 				unsigned int max_hz, unsigned int mode)
 {
 	struct spi_slave *slave;
 	u32 data;
+#ifdef CONFIG_KIRKWOOD
 	static const u32 kwspi_mpp_config[2][2] = {
 		{ MPP0_SPI_SCn, 0 }, /* if cs == 0 */
 		{ MPP7_SPI_SCn, 0 } /* if cs != 0 */
 	};
+#endif
 
 	if (!spi_cs_is_valid(bus, cs))
 		return NULL;
@@ -51,15 +58,19 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
 	writel(KWSPI_IRQMASK, &spireg->irq_mask);
 
+#ifdef CONFIG_KIRKWOOD
 	/* program mpp registers to select  SPI_CSn */
 	kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
+#endif
 
 	return slave;
 }
 
 void spi_free_slave(struct spi_slave *slave)
 {
+#ifdef CONFIG_KIRKWOOD
 	kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
+#endif
 	free(slave);
 }
 
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index be102692d44..23f2ba6223d 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -49,6 +49,8 @@ struct mxc_spi_slave {
 #endif
 	int		gpio;
 	int		ss_pol;
+	unsigned int	max_hz;
+	unsigned int	mode;
 };
 
 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
@@ -83,12 +85,13 @@ u32 get_cspi_div(u32 div)
 }
 
 #ifdef MXC_CSPI
-static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
-		unsigned int max_hz, unsigned int mode)
+static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
 {
 	unsigned int ctrl_reg;
 	u32 clk_src;
 	u32 div;
+	unsigned int max_hz = mxcs->max_hz;
+	unsigned int mode = mxcs->mode;
 
 	clk_src = mxc_get_clock(MXC_CSPI_CLK);
 
@@ -120,19 +123,15 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 #endif
 
 #ifdef MXC_ECSPI
-static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
-		unsigned int max_hz, unsigned int mode)
+static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
 {
 	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
 	s32 reg_ctrl, reg_config;
 	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
 	u32 pre_div = 0, post_div = 0;
 	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
-
-	if (max_hz == 0) {
-		printf("Error: desired clock is 0\n");
-		return -1;
-	}
+	unsigned int max_hz = mxcs->max_hz;
+	unsigned int mode = mxcs->mode;
 
 	/*
 	 * Reset SPI and set all CSs to master mode, if toggling
@@ -169,9 +168,6 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
 		MXC_CSPICTRL_POSTDIV(post_div);
 
-	/* We need to disable SPI before changing registers */
-	reg_ctrl &= ~MXC_CSPICTRL_EN;
-
 	if (mode & SPI_CS_HIGH)
 		ss_pol = 1;
 
@@ -412,6 +408,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	if (bus >= ARRAY_SIZE(spi_bases))
 		return NULL;
 
+	if (max_hz == 0) {
+		printf("Error: desired clock is 0\n");
+		return NULL;
+	}
+
 	mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
 	if (!mxcs) {
 		puts("mxc_spi: SPI Slave not allocated !\n");
@@ -427,13 +428,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	}
 
 	mxcs->base = spi_bases[bus];
+	mxcs->max_hz = max_hz;
+	mxcs->mode = mode;
 
-	ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
-	if (ret) {
-		printf("mxc_spi: cannot setup SPI controller\n");
-		free(mxcs);
-		return NULL;
-	}
 	return &mxcs->slave;
 }
 
@@ -446,12 +443,17 @@ void spi_free_slave(struct spi_slave *slave)
 
 int spi_claim_bus(struct spi_slave *slave)
 {
+	int ret;
 	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
 	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
 
 	reg_write(&regs->rxdata, 1);
 	udelay(1);
-	reg_write(&regs->ctrl, mxcs->ctrl_reg);
+	ret = spi_cfg_mxc(mxcs, slave->cs);
+	if (ret) {
+		printf("mxc_spi: cannot setup SPI controller\n");
+		return ret;
+	}
 	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
 	reg_write(&regs->intr, 0);
 
diff --git a/drivers/spi/sandbox_spi.c b/drivers/spi/sandbox_spi.c
index 12e9bdad38d..e717424db83 100644
--- a/drivers/spi/sandbox_spi.c
+++ b/drivers/spi/sandbox_spi.c
@@ -9,26 +9,23 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <malloc.h>
 #include <spi.h>
+#include <spi_flash.h>
 #include <os.h>
 
 #include <asm/errno.h>
 #include <asm/spi.h>
 #include <asm/state.h>
+#include <dm/device-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_SPI_IDLE_VAL
 # define CONFIG_SPI_IDLE_VAL 0xFF
 #endif
 
-struct sandbox_spi_slave {
-	struct spi_slave slave;
-	const struct sandbox_spi_emu_ops *ops;
-	void *priv;
-};
-
-#define to_sandbox_spi_slave(s) container_of(s, struct sandbox_spi_slave, slave)
-
 const char *sandbox_spi_parse_spec(const char *arg, unsigned long *bus,
 				   unsigned long *cs)
 {
@@ -45,120 +42,52 @@ const char *sandbox_spi_parse_spec(const char *arg, unsigned long *bus,
 	return endp + 1;
 }
 
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus < CONFIG_SANDBOX_SPI_MAX_BUS &&
-		cs < CONFIG_SANDBOX_SPI_MAX_CS;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
-
-	debug("sandbox_spi: activating CS\n");
-	if (sss->ops->cs_activate)
-		sss->ops->cs_activate(sss->priv);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
-
-	debug("sandbox_spi: deactivating CS\n");
-	if (sss->ops->cs_deactivate)
-		sss->ops->cs_deactivate(sss->priv);
-}
-
-void spi_init(void)
-{
-}
-
-void spi_set_speed(struct spi_slave *slave, uint hz)
+__weak int sandbox_spi_get_emul(struct sandbox_state *state,
+				struct udevice *bus, struct udevice *slave,
+				struct udevice **emulp)
 {
+	return -ENOENT;
 }
 
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-		unsigned int max_hz, unsigned int mode)
+static int sandbox_spi_xfer(struct udevice *slave, unsigned int bitlen,
+			    const void *dout, void *din, unsigned long flags)
 {
-	struct sandbox_spi_slave *sss;
+	struct udevice *bus = slave->parent;
 	struct sandbox_state *state = state_get_current();
-	const char *spec;
-
-	if (!spi_cs_is_valid(bus, cs)) {
-		debug("sandbox_spi: Invalid SPI bus/cs\n");
-		return NULL;
-	}
-
-	sss = spi_alloc_slave(struct sandbox_spi_slave, bus, cs);
-	if (!sss) {
-		debug("sandbox_spi: Out of memory\n");
-		return NULL;
-	}
-
-	spec = state->spi[bus][cs].spec;
-	sss->ops = state->spi[bus][cs].ops;
-	if (!spec || !sss->ops || sss->ops->setup(&sss->priv, spec)) {
-		free(sss);
-		printf("sandbox_spi: unable to locate a slave client\n");
-		return NULL;
-	}
-
-	return &sss->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-	struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
-
-	debug("sandbox_spi: releasing slave\n");
-
-	if (sss->ops->free)
-		sss->ops->free(sss->priv);
-
-	free(sss);
-}
-
-static int spi_bus_claim_cnt[CONFIG_SANDBOX_SPI_MAX_BUS];
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-	if (spi_bus_claim_cnt[slave->bus]++) {
-		printf("sandbox_spi: error: bus already claimed: %d!\n",
-		       spi_bus_claim_cnt[slave->bus]);
-	}
-
-	return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-	if (--spi_bus_claim_cnt[slave->bus]) {
-		printf("sandbox_spi: error: bus freed too often: %d!\n",
-		       spi_bus_claim_cnt[slave->bus]);
-	}
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
-		void *din, unsigned long flags)
-{
-	struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
+	struct dm_spi_emul_ops *ops;
+	struct udevice *emul;
 	uint bytes = bitlen / 8, i;
-	int ret = 0;
+	int ret;
 	u8 *tx = (void *)dout, *rx = din;
+	uint busnum, cs;
 
 	if (bitlen == 0)
-		goto done;
+		return 0;
 
 	/* we can only do 8 bit transfers */
 	if (bitlen % 8) {
 		printf("sandbox_spi: xfer: invalid bitlen size %u; needs to be 8bit\n",
 		       bitlen);
-		flags |= SPI_XFER_END;
-		goto done;
+		return -EINVAL;
 	}
 
-	if (flags & SPI_XFER_BEGIN)
-		spi_cs_activate(slave);
+	busnum = bus->seq;
+	cs = spi_chip_select(slave);
+	if (busnum >= CONFIG_SANDBOX_SPI_MAX_BUS ||
+	    cs >= CONFIG_SANDBOX_SPI_MAX_CS) {
+		printf("%s: busnum=%u, cs=%u: out of range\n", __func__,
+		       busnum, cs);
+		return -ENOENT;
+	}
+	ret = sandbox_spi_get_emul(state, bus, slave, &emul);
+	if (ret) {
+		printf("%s: busnum=%u, cs=%u: no emulation available (err=%d)\n",
+		       __func__, busnum, cs, ret);
+		return -ENOENT;
+	}
+	ret = device_probe(emul);
+	if (ret)
+		return ret;
 
 	/* make sure rx/tx buffers are full so clients can assume */
 	if (!tx) {
@@ -178,12 +107,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 		}
 	}
 
-	debug("sandbox_spi: xfer: bytes = %u\n tx:", bytes);
-	for (i = 0; i < bytes; ++i)
-		debug(" %u:%02x", i, tx[i]);
-	debug("\n");
-
-	ret = sss->ops->xfer(sss->priv, tx, rx, bytes);
+	ops = spi_emul_get_ops(emul);
+	ret = ops->xfer(emul, bitlen, dout, din, flags);
 
 	debug("sandbox_spi: xfer: got back %i (that's %s)\n rx:",
 	      ret, ret ? "bad" : "good");
@@ -196,22 +121,45 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	if (rx != din)
 		free(rx);
 
- done:
-	if (flags & SPI_XFER_END)
-		spi_cs_deactivate(slave);
-
 	return ret;
 }
 
-/**
- * Set up a new SPI slave for an fdt node
- *
- * @param blob		Device tree blob
- * @param node		SPI peripheral node to use
- * @return 0 if ok, -1 on error
- */
-struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
-				      int spi_node)
+static int sandbox_spi_set_speed(struct udevice *bus, uint speed)
+{
+	return 0;
+}
+
+static int sandbox_spi_set_mode(struct udevice *bus, uint mode)
+{
+	return 0;
+}
+
+static int sandbox_cs_info(struct udevice *bus, uint cs,
+			   struct spi_cs_info *info)
 {
-	return NULL;
+	/* Always allow activity on CS 0 */
+	if (cs >= 1)
+		return -ENODEV;
+
+	return 0;
 }
+
+static const struct dm_spi_ops sandbox_spi_ops = {
+	.xfer		= sandbox_spi_xfer,
+	.set_speed	= sandbox_spi_set_speed,
+	.set_mode	= sandbox_spi_set_mode,
+	.cs_info	= sandbox_cs_info,
+};
+
+static const struct udevice_id sandbox_spi_ids[] = {
+	{ .compatible = "sandbox,spi" },
+	{ }
+};
+
+U_BOOT_DRIVER(spi_sandbox) = {
+	.name	= "spi_sandbox",
+	.id	= UCLASS_SPI,
+	.of_match = sandbox_spi_ids,
+	.per_child_auto_alloc_size	= sizeof(struct spi_slave),
+	.ops	= &sandbox_spi_ops,
+};
diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
index c969be31eb3..558803618a2 100644
--- a/drivers/spi/soft_spi.c
+++ b/drivers/spi/soft_spi.c
@@ -1,4 +1,6 @@
 /*
+ * Copyright (c) 2014 Google, Inc
+ *
  * (C) Copyright 2002
  * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
  *
@@ -9,94 +11,81 @@
  */
 
 #include <common.h>
-#include <spi.h>
-
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
 #include <malloc.h>
+#include <spi.h>
+#include <asm/gpio.h>
 
-/*-----------------------------------------------------------------------
- * Definitions
- */
+DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef DEBUG_SPI
-#define PRINTD(fmt,args...)	printf (fmt ,##args)
-#else
-#define PRINTD(fmt,args...)
-#endif
+struct soft_spi_platdata {
+	struct fdt_gpio_state cs;
+	struct fdt_gpio_state sclk;
+	struct fdt_gpio_state mosi;
+	struct fdt_gpio_state miso;
+	int spi_delay_us;
+};
 
-struct soft_spi_slave {
-	struct spi_slave slave;
+struct soft_spi_priv {
 	unsigned int mode;
 };
 
-static inline struct soft_spi_slave *to_soft_spi(struct spi_slave *slave)
+static int soft_spi_scl(struct udevice *dev, int bit)
 {
-	return container_of(slave, struct soft_spi_slave, slave);
-}
+	struct soft_spi_platdata *plat = dev->platdata;
+	struct soft_spi_priv *priv = dev_get_priv(dev);
 
-/*=====================================================================*/
-/*                         Public Functions                            */
-/*=====================================================================*/
+	gpio_set_value(plat->sclk.gpio, priv->mode & SPI_CPOL ? bit : !bit);
 
-/*-----------------------------------------------------------------------
- * Initialization
- */
-void spi_init (void)
-{
-#ifdef	SPI_INIT
-	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
-	SPI_INIT;
-#endif
+	return 0;
 }
 
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-		unsigned int max_hz, unsigned int mode)
+static int soft_spi_sda(struct udevice *dev, int bit)
 {
-	struct soft_spi_slave *ss;
+	struct soft_spi_platdata *plat = dev->platdata;
 
-	if (!spi_cs_is_valid(bus, cs))
-		return NULL;
+	gpio_set_value(plat->mosi.gpio, bit);
 
-	ss = spi_alloc_slave(struct soft_spi_slave, bus, cs);
-	if (!ss)
-		return NULL;
+	return 0;
+}
 
-	ss->mode = mode;
+static int soft_spi_cs_activate(struct udevice *dev)
+{
+	struct soft_spi_platdata *plat = dev->platdata;
+	struct soft_spi_priv *priv = dev_get_priv(dev);
 
-	/* TODO: Use max_hz to limit the SCK rate */
+	gpio_set_value(plat->cs.gpio, !(priv->mode & SPI_CS_HIGH));
+	gpio_set_value(plat->sclk.gpio, priv->mode & SPI_CPOL);
+	gpio_set_value(plat->cs.gpio, priv->mode & SPI_CS_HIGH);
 
-	return &ss->slave;
+	return 0;
 }
 
-void spi_free_slave(struct spi_slave *slave)
+static int soft_spi_cs_deactivate(struct udevice *dev)
 {
-	struct soft_spi_slave *ss = to_soft_spi(slave);
+	struct soft_spi_platdata *plat = dev->platdata;
+	struct soft_spi_priv *priv = dev_get_priv(dev);
 
-	free(ss);
+	gpio_set_value(plat->cs.gpio, !(priv->mode & SPI_CS_HIGH));
+
+	return 0;
 }
 
-int spi_claim_bus(struct spi_slave *slave)
+static int soft_spi_claim_bus(struct udevice *dev)
 {
-#ifdef CONFIG_SYS_IMMR
-	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-#endif
-	struct soft_spi_slave *ss = to_soft_spi(slave);
-
 	/*
 	 * Make sure the SPI clock is in idle state as defined for
 	 * this slave.
 	 */
-	if (ss->mode & SPI_CPOL)
-		SPI_SCL(1);
-	else
-		SPI_SCL(0);
-
-	return 0;
+	return soft_spi_scl(dev, 0);
 }
 
-void spi_release_bus(struct spi_slave *slave)
+static int soft_spi_release_bus(struct udevice *dev)
 {
 	/* Nothing to do */
+	return 0;
 }
 
 /*-----------------------------------------------------------------------
@@ -111,28 +100,27 @@ void spi_release_bus(struct spi_slave *slave)
  * input data overwrites the output data (since both are buffered by
  * temporary variables, this is OK).
  */
-int  spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-		const void *dout, void *din, unsigned long flags)
+static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen,
+			 const void *dout, void *din, unsigned long flags)
 {
-#ifdef CONFIG_SYS_IMMR
-	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-#endif
-	struct soft_spi_slave *ss = to_soft_spi(slave);
+	struct soft_spi_priv *priv = dev_get_priv(dev);
+	struct soft_spi_platdata *plat = dev->platdata;
 	uchar		tmpdin  = 0;
 	uchar		tmpdout = 0;
 	const u8	*txd = dout;
 	u8		*rxd = din;
-	int		cpol = ss->mode & SPI_CPOL;
-	int		cpha = ss->mode & SPI_CPHA;
+	int		cpol = priv->mode & SPI_CPOL;
+	int		cpha = priv->mode & SPI_CPHA;
 	unsigned int	j;
 
-	PRINTD("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
-		slave->bus, slave->cs, *(uint *)txd, *(uint *)rxd, bitlen);
+	debug("spi_xfer: slave %s:%s dout %08X din %08X bitlen %u\n",
+	      dev->parent->name, dev->name, *(uint *)txd, *(uint *)rxd,
+	      bitlen);
 
 	if (flags & SPI_XFER_BEGIN)
-		spi_cs_activate(slave);
+		soft_spi_cs_activate(dev);
 
-	for(j = 0; j < bitlen; j++) {
+	for (j = 0; j < bitlen; j++) {
 		/*
 		 * Check if it is time to work on a new byte.
 		 */
@@ -141,7 +129,7 @@ int  spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 				tmpdout = *txd++;
 			else
 				tmpdout = 0;
-			if(j != 0) {
+			if (j != 0) {
 				if (rxd)
 					*rxd++ = tmpdin;
 			}
@@ -149,19 +137,19 @@ int  spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 		}
 
 		if (!cpha)
-			SPI_SCL(!cpol);
-		SPI_SDA(tmpdout & 0x80);
-		SPI_DELAY;
+			soft_spi_scl(dev, !cpol);
+		soft_spi_sda(dev, tmpdout & 0x80);
+		udelay(plat->spi_delay_us);
 		if (cpha)
-			SPI_SCL(!cpol);
+			soft_spi_scl(dev, !cpol);
 		else
-			SPI_SCL(cpol);
+			soft_spi_scl(dev, cpol);
 		tmpdin	<<= 1;
-		tmpdin	|= SPI_READ;
+		tmpdin	|= gpio_get_value(plat->miso.gpio);
 		tmpdout	<<= 1;
-		SPI_DELAY;
+		udelay(plat->spi_delay_us);
 		if (cpha)
-			SPI_SCL(cpol);
+			soft_spi_scl(dev, cpol);
 	}
 	/*
 	 * If the number of bits isn't a multiple of 8, shift the last
@@ -175,7 +163,90 @@ int  spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 	}
 
 	if (flags & SPI_XFER_END)
-		spi_cs_deactivate(slave);
+		soft_spi_cs_deactivate(dev);
 
-	return(0);
+	return 0;
 }
+
+static int soft_spi_set_speed(struct udevice *dev, unsigned int speed)
+{
+	/* Accept any speed */
+	return 0;
+}
+
+static int soft_spi_set_mode(struct udevice *dev, unsigned int mode)
+{
+	struct soft_spi_priv *priv = dev_get_priv(dev);
+
+	priv->mode = mode;
+
+	return 0;
+}
+
+static int soft_spi_child_pre_probe(struct udevice *dev)
+{
+	struct spi_slave *slave = dev_get_parentdata(dev);
+
+	slave->dev = dev;
+	return spi_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, slave);
+}
+
+static const struct dm_spi_ops soft_spi_ops = {
+	.claim_bus	= soft_spi_claim_bus,
+	.release_bus	= soft_spi_release_bus,
+	.xfer		= soft_spi_xfer,
+	.set_speed	= soft_spi_set_speed,
+	.set_mode	= soft_spi_set_mode,
+};
+
+static int soft_spi_ofdata_to_platdata(struct udevice *dev)
+{
+	struct soft_spi_platdata *plat = dev->platdata;
+	const void *blob = gd->fdt_blob;
+	int node = dev->of_offset;
+
+	if (fdtdec_decode_gpio(blob, node, "cs-gpio", &plat->cs) ||
+	    fdtdec_decode_gpio(blob, node, "sclk-gpio", &plat->sclk) ||
+	    fdtdec_decode_gpio(blob, node, "mosi-gpio", &plat->mosi) ||
+	    fdtdec_decode_gpio(blob, node, "miso-gpio", &plat->miso))
+		return -EINVAL;
+	plat->spi_delay_us = fdtdec_get_int(blob, node, "spi-delay-us", 0);
+
+	return 0;
+}
+
+static int soft_spi_probe(struct udevice *dev)
+{
+	struct spi_slave *slave = dev_get_parentdata(dev);
+	struct soft_spi_platdata *plat = dev->platdata;
+
+	gpio_request(plat->cs.gpio, "soft_spi_cs");
+	gpio_request(plat->sclk.gpio, "soft_spi_sclk");
+	gpio_request(plat->mosi.gpio, "soft_spi_mosi");
+	gpio_request(plat->miso.gpio, "soft_spi_miso");
+
+	gpio_direction_output(plat->sclk.gpio, slave->mode & SPI_CPOL);
+	gpio_direction_output(plat->mosi.gpio, 1);
+	gpio_direction_input(plat->miso.gpio);
+	gpio_direction_output(plat->cs.gpio, !(slave->mode & SPI_CS_HIGH));
+
+	return 0;
+}
+
+static const struct udevice_id soft_spi_ids[] = {
+	{ .compatible = "u-boot,soft-spi" },
+	{ }
+};
+
+U_BOOT_DRIVER(soft_spi) = {
+	.name	= "soft_spi",
+	.id	= UCLASS_SPI,
+	.of_match = soft_spi_ids,
+	.ops	= &soft_spi_ops,
+	.ofdata_to_platdata = soft_spi_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct soft_spi_platdata),
+	.priv_auto_alloc_size = sizeof(struct soft_spi_priv),
+	.per_child_auto_alloc_size	= sizeof(struct spi_slave),
+	.probe	= soft_spi_probe,
+	.child_pre_probe	= soft_spi_child_pre_probe,
+};
diff --git a/drivers/spi/soft_spi_legacy.c b/drivers/spi/soft_spi_legacy.c
new file mode 100644
index 00000000000..941daa730b0
--- /dev/null
+++ b/drivers/spi/soft_spi_legacy.c
@@ -0,0 +1,176 @@
+/*
+ * (C) Copyright 2002
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
+ *
+ * Influenced by code from:
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+
+#include <malloc.h>
+
+/*-----------------------------------------------------------------------
+ * Definitions
+ */
+
+#ifdef DEBUG_SPI
+#define PRINTD(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTD(fmt,args...)
+#endif
+
+struct soft_spi_slave {
+	struct spi_slave slave;
+	unsigned int mode;
+};
+
+static inline struct soft_spi_slave *to_soft_spi(struct spi_slave *slave)
+{
+	return container_of(slave, struct soft_spi_slave, slave);
+}
+
+/*=====================================================================*/
+/*                         Public Functions                            */
+/*=====================================================================*/
+
+/*-----------------------------------------------------------------------
+ * Initialization
+ */
+void spi_init (void)
+{
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int mode)
+{
+	struct soft_spi_slave *ss;
+
+	if (!spi_cs_is_valid(bus, cs))
+		return NULL;
+
+	ss = spi_alloc_slave(struct soft_spi_slave, bus, cs);
+	if (!ss)
+		return NULL;
+
+	ss->mode = mode;
+
+	/* TODO: Use max_hz to limit the SCK rate */
+
+	return &ss->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	struct soft_spi_slave *ss = to_soft_spi(slave);
+
+	free(ss);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+#ifdef CONFIG_SYS_IMMR
+	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+#endif
+	struct soft_spi_slave *ss = to_soft_spi(slave);
+
+	/*
+	 * Make sure the SPI clock is in idle state as defined for
+	 * this slave.
+	 */
+	if (ss->mode & SPI_CPOL)
+		SPI_SCL(1);
+	else
+		SPI_SCL(0);
+
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	/* Nothing to do */
+}
+
+/*-----------------------------------------------------------------------
+ * SPI transfer
+ *
+ * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
+ * "bitlen" bits in the SPI MISO port.  That's just the way SPI works.
+ *
+ * The source of the outgoing bits is the "dout" parameter and the
+ * destination of the input bits is the "din" parameter.  Note that "dout"
+ * and "din" can point to the same memory location, in which case the
+ * input data overwrites the output data (since both are buffered by
+ * temporary variables, this is OK).
+ */
+int  spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+		const void *dout, void *din, unsigned long flags)
+{
+#ifdef CONFIG_SYS_IMMR
+	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+#endif
+	struct soft_spi_slave *ss = to_soft_spi(slave);
+	uchar		tmpdin  = 0;
+	uchar		tmpdout = 0;
+	const u8	*txd = dout;
+	u8		*rxd = din;
+	int		cpol = ss->mode & SPI_CPOL;
+	int		cpha = ss->mode & SPI_CPHA;
+	unsigned int	j;
+
+	PRINTD("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
+		slave->bus, slave->cs, *(uint *)txd, *(uint *)rxd, bitlen);
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(slave);
+
+	for(j = 0; j < bitlen; j++) {
+		/*
+		 * Check if it is time to work on a new byte.
+		 */
+		if ((j % 8) == 0) {
+			if (txd)
+				tmpdout = *txd++;
+			else
+				tmpdout = 0;
+			if(j != 0) {
+				if (rxd)
+					*rxd++ = tmpdin;
+			}
+			tmpdin  = 0;
+		}
+
+		if (!cpha)
+			SPI_SCL(!cpol);
+		SPI_SDA(tmpdout & 0x80);
+		SPI_DELAY;
+		if (cpha)
+			SPI_SCL(!cpol);
+		else
+			SPI_SCL(cpol);
+		tmpdin	<<= 1;
+		tmpdin	|= SPI_READ;
+		tmpdout	<<= 1;
+		SPI_DELAY;
+		if (cpha)
+			SPI_SCL(cpol);
+	}
+	/*
+	 * If the number of bits isn't a multiple of 8, shift the last
+	 * bits over to left-justify them.  Then store the last byte
+	 * read in.
+	 */
+	if (rxd) {
+		if ((bitlen % 8) != 0)
+			tmpdin <<= 8 - (bitlen % 8);
+		*rxd++ = tmpdin;
+	}
+
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(slave);
+
+	return(0);
+}
diff --git a/drivers/spi/spi-emul-uclass.c b/drivers/spi/spi-emul-uclass.c
new file mode 100644
index 00000000000..b436a0e99f9
--- /dev/null
+++ b/drivers/spi/spi-emul-uclass.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spi.h>
+#include <spi_flash.h>
+
+UCLASS_DRIVER(spi_emul) = {
+	.id		= UCLASS_SPI_EMUL,
+	.name		= "spi_emul",
+};
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
new file mode 100644
index 00000000000..13c6b77d73d
--- /dev/null
+++ b/drivers/spi/spi-uclass.c
@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <spi.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+#include <dm/root.h>
+#include <dm/lists.h>
+#include <dm/util.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int spi_set_speed_mode(struct udevice *bus, int speed, int mode)
+{
+	struct dm_spi_ops *ops;
+	int ret;
+
+	ops = spi_get_ops(bus);
+	if (ops->set_speed)
+		ret = ops->set_speed(bus, speed);
+	else
+		ret = -EINVAL;
+	if (ret) {
+		printf("Cannot set speed (err=%d)\n", ret);
+		return ret;
+	}
+
+	if (ops->set_mode)
+		ret = ops->set_mode(bus, mode);
+	else
+		ret = -EINVAL;
+	if (ret) {
+		printf("Cannot set mode (err=%d)\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	struct udevice *dev = slave->dev;
+	struct udevice *bus = dev->parent;
+	struct dm_spi_ops *ops = spi_get_ops(bus);
+	struct dm_spi_bus *spi = bus->uclass_priv;
+	int speed;
+	int ret;
+
+	speed = slave->max_hz;
+	if (spi->max_hz) {
+		if (speed)
+			speed = min(speed, spi->max_hz);
+		else
+			speed = spi->max_hz;
+	}
+	if (!speed)
+		speed = 100000;
+	ret = spi_set_speed_mode(bus, speed, slave->mode);
+	if (ret)
+		return ret;
+
+	return ops->claim_bus ? ops->claim_bus(bus) : 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	struct udevice *dev = slave->dev;
+	struct udevice *bus = dev->parent;
+	struct dm_spi_ops *ops = spi_get_ops(bus);
+
+	if (ops->release_bus)
+		ops->release_bus(bus);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+	     const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *dev = slave->dev;
+	struct udevice *bus = dev->parent;
+
+	if (bus->uclass->uc_drv->id != UCLASS_SPI)
+		return -EOPNOTSUPP;
+
+	return spi_get_ops(bus)->xfer(dev, bitlen, dout, din, flags);
+}
+
+int spi_post_bind(struct udevice *dev)
+{
+	/* Scan the bus for devices */
+	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+}
+
+int spi_post_probe(struct udevice *dev)
+{
+	struct dm_spi_bus *spi = dev->uclass_priv;
+
+	spi->max_hz = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+				     "spi-max-frequency", 0);
+
+	return 0;
+}
+
+int spi_chip_select(struct udevice *dev)
+{
+	struct spi_slave *slave = dev_get_parentdata(dev);
+
+	return slave ? slave->cs : -ENOENT;
+}
+
+/**
+ * spi_find_chip_select() - Find the slave attached to chip select
+ *
+ * @bus:	SPI bus to search
+ * @cs:		Chip select to look for
+ * @devp:	Returns the slave device if found
+ * @return 0 if found, -ENODEV on error
+ */
+static int spi_find_chip_select(struct udevice *bus, int cs,
+				struct udevice **devp)
+{
+	struct udevice *dev;
+
+	for (device_find_first_child(bus, &dev); dev;
+	     device_find_next_child(&dev)) {
+		struct spi_slave store;
+		struct spi_slave *slave = dev_get_parentdata(dev);
+
+		if (!slave)  {
+			slave = &store;
+			spi_ofdata_to_platdata(gd->fdt_blob, dev->of_offset,
+					       slave);
+		}
+		debug("%s: slave=%p, cs=%d\n", __func__, slave,
+		      slave ? slave->cs : -1);
+		if (slave && slave->cs == cs) {
+			*devp = dev;
+			return 0;
+		}
+	}
+
+	return -ENODEV;
+}
+
+int spi_cs_is_valid(unsigned int busnum, unsigned int cs)
+{
+	struct spi_cs_info info;
+	struct udevice *bus;
+	int ret;
+
+	ret = uclass_find_device_by_seq(UCLASS_SPI, busnum, false, &bus);
+	if (ret) {
+		debug("%s: No bus %d\n", __func__, busnum);
+		return ret;
+	}
+
+	return spi_cs_info(bus, cs, &info);
+}
+
+int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info)
+{
+	struct spi_cs_info local_info;
+	struct dm_spi_ops *ops;
+	int ret;
+
+	if (!info)
+		info = &local_info;
+
+	/* If there is a device attached, return it */
+	info->dev = NULL;
+	ret = spi_find_chip_select(bus, cs, &info->dev);
+	if (!ret)
+		return 0;
+
+	/*
+	 * Otherwise ask the driver. For the moment we don't have CS info.
+	 * When we do we could provide the driver with a helper function
+	 * to figure out what chip selects are valid, or just handle the
+	 * request.
+	 */
+	ops = spi_get_ops(bus);
+	if (ops->cs_info)
+		return ops->cs_info(bus, cs, info);
+
+	/*
+	 * We could assume there is at least one valid chip select, but best
+	 * to be sure and return an error in this case. The driver didn't
+	 * care enough to tell us.
+	 */
+	return -ENODEV;
+}
+
+int spi_bind_device(struct udevice *bus, int cs, const char *drv_name,
+		    const char *dev_name, struct udevice **devp)
+{
+	struct driver *drv;
+	int ret;
+
+	drv = lists_driver_lookup_name(drv_name);
+	if (!drv) {
+		printf("Cannot find driver '%s'\n", drv_name);
+		return -ENOENT;
+	}
+	ret = device_bind(bus, drv, dev_name, NULL, -1, devp);
+	if (ret) {
+		printf("Cannot create device named '%s' (err=%d)\n",
+		       dev_name, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp,
+			struct udevice **devp)
+{
+	struct udevice *bus, *dev;
+	int ret;
+
+	ret = uclass_find_device_by_seq(UCLASS_SPI, busnum, false, &bus);
+	if (ret) {
+		debug("%s: No bus %d\n", __func__, busnum);
+		return ret;
+	}
+	ret = spi_find_chip_select(bus, cs, &dev);
+	if (ret) {
+		debug("%s: No cs %d\n", __func__, cs);
+		return ret;
+	}
+	*busp = bus;
+	*devp = dev;
+
+	return ret;
+}
+
+int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
+		       const char *drv_name, const char *dev_name,
+		       struct udevice **busp, struct spi_slave **devp)
+{
+	struct udevice *bus, *dev;
+	struct spi_slave *slave;
+	bool created = false;
+	int ret;
+
+	ret = uclass_get_device_by_seq(UCLASS_SPI, busnum, &bus);
+	if (ret) {
+		printf("Invalid bus %d (err=%d)\n", busnum, ret);
+		return ret;
+	}
+	ret = spi_find_chip_select(bus, cs, &dev);
+
+	/*
+	 * If there is no such device, create one automatically. This means
+	 * that we don't need a device tree node or platform data for the
+	 * SPI flash chip - we will bind to the correct driver.
+	 */
+	if (ret == -ENODEV && drv_name) {
+		debug("%s: Binding new device '%s', busnum=%d, cs=%d, driver=%s\n",
+		      __func__, dev_name, busnum, cs, drv_name);
+		ret = spi_bind_device(bus, cs, drv_name, dev_name, &dev);
+		if (ret)
+			return ret;
+		created = true;
+	} else if (ret) {
+		printf("Invalid chip select %d:%d (err=%d)\n", busnum, cs,
+		       ret);
+		return ret;
+	}
+
+	if (!device_active(dev)) {
+		slave = (struct spi_slave *)calloc(1,
+						   sizeof(struct spi_slave));
+		if (!slave) {
+			ret = -ENOMEM;
+			goto err;
+		}
+
+		ret = spi_ofdata_to_platdata(gd->fdt_blob, dev->of_offset,
+					     slave);
+		if (ret)
+			goto err;
+		slave->cs = cs;
+		slave->dev = dev;
+		ret = device_probe_child(dev, slave);
+		free(slave);
+		if (ret)
+			goto err;
+	}
+
+	ret = spi_set_speed_mode(bus, speed, mode);
+	if (ret)
+		goto err;
+
+	*busp = bus;
+	*devp = dev_get_parentdata(dev);
+	debug("%s: bus=%p, slave=%p\n", __func__, bus, *devp);
+
+	return 0;
+
+err:
+	if (created) {
+		device_remove(dev);
+		device_unbind(dev);
+	}
+
+	return ret;
+}
+
+/* Compatibility function - to be removed */
+struct spi_slave *spi_setup_slave_fdt(const void *blob, int node,
+				      int bus_node)
+{
+	struct udevice *bus, *dev;
+	int ret;
+
+	ret = uclass_get_device_by_of_offset(UCLASS_SPI, bus_node, &bus);
+	if (ret)
+		return NULL;
+	ret = device_get_child_by_of_offset(bus, node, &dev);
+	if (ret)
+		return NULL;
+	return dev_get_parentdata(dev);
+}
+
+/* Compatibility function - to be removed */
+struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
+				  unsigned int speed, unsigned int mode)
+{
+	struct spi_slave *slave;
+	struct udevice *dev;
+	int ret;
+
+	ret = spi_get_bus_and_cs(busnum, cs, speed, mode, NULL, 0, &dev,
+				  &slave);
+	if (ret)
+		return NULL;
+
+	return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	device_remove(slave->dev);
+	slave->dev = NULL;
+}
+
+int spi_ofdata_to_platdata(const void *blob, int node,
+			   struct spi_slave *spi)
+{
+	int mode = 0;
+
+	spi->cs = fdtdec_get_int(blob, node, "reg", -1);
+	spi->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 0);
+	if (fdtdec_get_bool(blob, node, "spi-cpol"))
+		mode |= SPI_CPOL;
+	if (fdtdec_get_bool(blob, node, "spi-cpha"))
+		mode |= SPI_CPHA;
+	if (fdtdec_get_bool(blob, node, "spi-cs-high"))
+		mode |= SPI_CS_HIGH;
+	if (fdtdec_get_bool(blob, node, "spi-half-duplex"))
+		mode |= SPI_PREAMBLE;
+	spi->mode = mode;
+
+	return 0;
+}
+
+UCLASS_DRIVER(spi) = {
+	.id		= UCLASS_SPI,
+	.name		= "spi",
+	.post_bind	= spi_post_bind,
+	.post_probe	= spi_post_probe,
+	.per_device_auto_alloc_size = sizeof(struct dm_spi_bus),
+};
+
+UCLASS_DRIVER(spi_generic) = {
+	.id		= UCLASS_SPI_GENERIC,
+	.name		= "spi_generic",
+};
+
+U_BOOT_DRIVER(spi_generic_drv) = {
+	.name		= "spi_generic_drv",
+	.id		= UCLASS_SPI_GENERIC,
+};
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index 810fa4718ce..2d97625fba7 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -22,14 +22,13 @@
  */
 
 #include <common.h>
-#include <malloc.h>
+#include <dm.h>
 #include <asm/io.h>
-#include <asm/gpio.h>
 #include <asm/arch/clock.h>
 #include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra114/tegra114_spi.h>
 #include <spi.h>
 #include <fdtdec.h>
+#include "tegra_spi.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -104,130 +103,63 @@ struct spi_regs {
 	u32 spare_ctl;	/* 18c:SPI_SPARE_CTRL register */
 };
 
-struct tegra_spi_ctrl {
+struct tegra114_spi_priv {
 	struct spi_regs *regs;
 	unsigned int freq;
 	unsigned int mode;
 	int periph_id;
 	int valid;
+	int last_transaction_us;
 };
 
-struct tegra_spi_slave {
-	struct spi_slave slave;
-	struct tegra_spi_ctrl *ctrl;
-};
-
-static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA114_SPI_CTRLS];
-
-static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
+static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
 {
-	return container_of(slave, struct tegra_spi_slave, slave);
-}
+	struct tegra_spi_platdata *plat = bus->platdata;
+	const void *blob = gd->fdt_blob;
+	int node = bus->of_offset;
 
-int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	if (bus >= CONFIG_TEGRA114_SPI_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
-		return 0;
-	else
-		return 1;
-}
+	plat->base = fdtdec_get_addr(blob, node, "reg");
+	plat->periph_id = clock_decode_periph_id(blob, node);
 
-struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs,
-		unsigned int max_hz, unsigned int mode)
-{
-	struct tegra_spi_slave *spi;
-
-	debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
-		bus, cs, max_hz, mode);
-
-	if (!spi_cs_is_valid(bus, cs)) {
-		printf("SPI error: unsupported bus %d / chip select %d\n",
-		       bus, cs);
-		return NULL;
-	}
-
-	if (max_hz > TEGRA_SPI_MAX_FREQ) {
-		printf("SPI error: unsupported frequency %d Hz. Max frequency"
-			" is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
-		return NULL;
+	if (plat->periph_id == PERIPH_ID_NONE) {
+		debug("%s: could not decode periph id %d\n", __func__,
+		      plat->periph_id);
+		return -FDT_ERR_NOTFOUND;
 	}
 
-	spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
-	if (!spi) {
-		printf("SPI error: malloc of SPI structure failed\n");
-		return NULL;
-	}
-	spi->ctrl = &spi_ctrls[bus];
-	if (!spi->ctrl) {
-		printf("SPI error: could not find controller for bus %d\n",
-		       bus);
-		return NULL;
-	}
+	/* Use 500KHz as a suitable default */
+	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+					500000);
+	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
+					"spi-deactivate-delay", 0);
+	debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+	      __func__, plat->base, plat->periph_id, plat->frequency,
+	      plat->deactivate_delay_us);
 
-	if (max_hz < spi->ctrl->freq) {
-		debug("%s: limiting frequency from %u to %u\n", __func__,
-		      spi->ctrl->freq, max_hz);
-		spi->ctrl->freq = max_hz;
-	}
-	spi->ctrl->mode = mode;
-
-	return &spi->slave;
-}
-
-void tegra114_spi_free_slave(struct spi_slave *slave)
-{
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
-	free(spi);
+	return 0;
 }
 
-int tegra114_spi_init(int *node_list, int count)
+static int tegra114_spi_probe(struct udevice *bus)
 {
-	struct tegra_spi_ctrl *ctrl;
-	int i;
-	int node = 0;
-	int found = 0;
-
-	for (i = 0; i < count; i++) {
-		ctrl = &spi_ctrls[i];
-		node = node_list[i];
-
-		ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
-								 node, "reg");
-		if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
-			debug("%s: no spi register found\n", __func__);
-			continue;
-		}
-		ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
-					    "spi-max-frequency", 0);
-		if (!ctrl->freq) {
-			debug("%s: no spi max frequency found\n", __func__);
-			continue;
-		}
+	struct tegra_spi_platdata *plat = dev_get_platdata(bus);
+	struct tegra114_spi_priv *priv = dev_get_priv(bus);
 
-		ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
-		if (ctrl->periph_id == PERIPH_ID_NONE) {
-			debug("%s: could not decode periph id\n", __func__);
-			continue;
-		}
-		ctrl->valid = 1;
-		found = 1;
+	priv->regs = (struct spi_regs *)plat->base;
 
-		debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
-		      __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
-	}
+	priv->last_transaction_us = timer_get_us();
+	priv->freq = plat->frequency;
+	priv->periph_id = plat->periph_id;
 
-	return !found;
+	return 0;
 }
 
-int tegra114_spi_claim_bus(struct spi_slave *slave)
+static int tegra114_spi_claim_bus(struct udevice *bus)
 {
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_regs *regs = spi->ctrl->regs;
+	struct tegra114_spi_priv *priv = dev_get_priv(bus);
+	struct spi_regs *regs = priv->regs;
 
 	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
-	clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
-			       spi->ctrl->freq);
+	clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
 
 	/* Clear stale status here */
 	setbits_le32(&regs->fifo_status,
@@ -244,33 +176,64 @@ int tegra114_spi_claim_bus(struct spi_slave *slave)
 
 	/* Set master mode and sw controlled CS */
 	setbits_le32(&regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
-		     (spi->ctrl->mode << SPI_CMD1_MODE_SHIFT));
+		     (priv->mode << SPI_CMD1_MODE_SHIFT));
 	debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
 
 	return 0;
 }
 
-void tegra114_spi_cs_activate(struct spi_slave *slave)
+/**
+ * Activate the CS by driving it LOW
+ *
+ * @param slave	Pointer to spi_slave to which controller has to
+ *		communicate with
+ */
+static void spi_cs_activate(struct udevice *dev)
 {
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_regs *regs = spi->ctrl->regs;
+	struct udevice *bus = dev->parent;
+	struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+	struct tegra114_spi_priv *priv = dev_get_priv(bus);
+
+	/* If it's too soon to do another transaction, wait */
+	if (pdata->deactivate_delay_us &&
+	    priv->last_transaction_us) {
+		ulong delay_us;		/* The delay completed so far */
+		delay_us = timer_get_us() - priv->last_transaction_us;
+		if (delay_us < pdata->deactivate_delay_us)
+			udelay(pdata->deactivate_delay_us - delay_us);
+	}
 
-	clrbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL);
+	clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
 }
 
-void tegra114_spi_cs_deactivate(struct spi_slave *slave)
+/**
+ * Deactivate the CS by driving it HIGH
+ *
+ * @param slave	Pointer to spi_slave to which controller has to
+ *		communicate with
+ */
+static void spi_cs_deactivate(struct udevice *dev)
 {
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_regs *regs = spi->ctrl->regs;
+	struct udevice *bus = dev->parent;
+	struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+	struct tegra114_spi_priv *priv = dev_get_priv(bus);
+
+	setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
 
-	setbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL);
+	/* Remember time of this transaction so we can honour the bus delay */
+	if (pdata->deactivate_delay_us)
+		priv->last_transaction_us = timer_get_us();
+
+	debug("Deactivate CS, bus '%s'\n", bus->name);
 }
 
-int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-		const void *data_out, void *data_in, unsigned long flags)
+static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
+			     const void *data_out, void *data_in,
+			     unsigned long flags)
 {
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_regs *regs = spi->ctrl->regs;
+	struct udevice *bus = dev->parent;
+	struct tegra114_spi_priv *priv = dev_get_priv(bus);
+	struct spi_regs *regs = priv->regs;
 	u32 reg, tmpdout, tmpdin = 0;
 	const u8 *dout = data_out;
 	u8 *din = data_in;
@@ -278,7 +241,7 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 	int ret;
 
 	debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
-	      __func__, slave->bus, slave->cs, dout, din, bitlen);
+	      __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
 	if (bitlen % 8)
 		return -1;
 	num_bytes = bitlen / 8;
@@ -291,13 +254,13 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 
 	clrsetbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL,
 			SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
-			(slave->cs << SPI_CMD1_CS_SEL_SHIFT));
+			(spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT));
 
 	/* set xfer size to 1 block (32 bits) */
 	writel(0, &regs->dma_blk);
 
 	if (flags & SPI_XFER_BEGIN)
-		spi_cs_activate(slave);
+		spi_cs_activate(dev);
 
 	/* handle data in 32-bit chunks */
 	while (num_bytes > 0) {
@@ -383,7 +346,7 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 	}
 
 	if (flags & SPI_XFER_END)
-		spi_cs_deactivate(slave);
+		spi_cs_deactivate(dev);
 
 	debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
 	      __func__, tmpdin, readl(&regs->fifo_status));
@@ -394,5 +357,56 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 		return -1;
 	}
 
+	return ret;
+}
+
+static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
+{
+	struct tegra_spi_platdata *plat = bus->platdata;
+	struct tegra114_spi_priv *priv = dev_get_priv(bus);
+
+	if (speed > plat->frequency)
+		speed = plat->frequency;
+	priv->freq = speed;
+	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
+
 	return 0;
 }
+
+static int tegra114_spi_set_mode(struct udevice *bus, uint mode)
+{
+	struct tegra114_spi_priv *priv = dev_get_priv(bus);
+
+	priv->mode = mode;
+	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+
+	return 0;
+}
+
+static const struct dm_spi_ops tegra114_spi_ops = {
+	.claim_bus	= tegra114_spi_claim_bus,
+	.xfer		= tegra114_spi_xfer,
+	.set_speed	= tegra114_spi_set_speed,
+	.set_mode	= tegra114_spi_set_mode,
+	/*
+	 * cs_info is not needed, since we require all chip selects to be
+	 * in the device tree explicitly
+	 */
+};
+
+static const struct udevice_id tegra114_spi_ids[] = {
+	{ .compatible = "nvidia,tegra114-spi" },
+	{ }
+};
+
+U_BOOT_DRIVER(tegra114_spi) = {
+	.name	= "tegra114_spi",
+	.id	= UCLASS_SPI,
+	.of_match = tegra114_spi_ids,
+	.ops	= &tegra114_spi_ops,
+	.ofdata_to_platdata = tegra114_spi_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
+	.priv_auto_alloc_size = sizeof(struct tegra114_spi_priv),
+	.per_child_auto_alloc_size	= sizeof(struct spi_slave),
+	.probe	= tegra114_spi_probe,
+};
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index b5d561be341..7d0d0f37fc7 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -7,15 +7,16 @@
  */
 
 #include <common.h>
-#include <malloc.h>
+#include <dm.h>
+#include <errno.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra20/tegra20_sflash.h>
 #include <spi.h>
 #include <fdtdec.h>
+#include "tegra_spi.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -64,129 +65,75 @@ struct spi_regs {
 	u32 rx_fifo;	/* SPI_RX_FIFO_0 register */
 };
 
-struct tegra_spi_ctrl {
+struct tegra20_sflash_priv {
 	struct spi_regs *regs;
 	unsigned int freq;
 	unsigned int mode;
 	int periph_id;
 	int valid;
+	int last_transaction_us;
 };
 
-struct tegra_spi_slave {
-	struct spi_slave slave;
-	struct tegra_spi_ctrl *ctrl;
-};
-
-/* tegra20 only supports one SFLASH controller */
-static struct tegra_spi_ctrl spi_ctrls[1];
-
-static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
-{
-	return container_of(slave, struct tegra_spi_slave, slave);
-}
-
-int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs)
+int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs,
+			   struct spi_cs_info *info)
 {
 	/* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
-	if (bus != 0 || cs != 0)
-		return 0;
+	if (cs != 0)
+		return -ENODEV;
 	else
-		return 1;
+		return 0;
 }
 
-struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs,
-				  unsigned int max_hz, unsigned int mode)
+static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
 {
-	struct tegra_spi_slave *spi;
+	struct tegra_spi_platdata *plat = bus->platdata;
+	const void *blob = gd->fdt_blob;
+	int node = bus->of_offset;
 
-	if (!spi_cs_is_valid(bus, cs)) {
-		printf("SPI error: unsupported bus %d / chip select %d\n",
-		       bus, cs);
-		return NULL;
-	}
+	plat->base = fdtdec_get_addr(blob, node, "reg");
+	plat->periph_id = clock_decode_periph_id(blob, node);
 
-	if (max_hz > TEGRA_SPI_MAX_FREQ) {
-		printf("SPI error: unsupported frequency %d Hz. Max frequency"
-			" is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
-		return NULL;
+	if (plat->periph_id == PERIPH_ID_NONE) {
+		debug("%s: could not decode periph id %d\n", __func__,
+		      plat->periph_id);
+		return -FDT_ERR_NOTFOUND;
 	}
 
-	spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
-	if (!spi) {
-		printf("SPI error: malloc of SPI structure failed\n");
-		return NULL;
-	}
-	spi->ctrl = &spi_ctrls[bus];
-	if (!spi->ctrl) {
-		printf("SPI error: could not find controller for bus %d\n",
-		       bus);
-		return NULL;
-	}
+	/* Use 500KHz as a suitable default */
+	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+					500000);
+	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
+					"spi-deactivate-delay", 0);
+	debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+	      __func__, plat->base, plat->periph_id, plat->frequency,
+	      plat->deactivate_delay_us);
 
-	if (max_hz < spi->ctrl->freq) {
-		debug("%s: limiting frequency from %u to %u\n", __func__,
-		      spi->ctrl->freq, max_hz);
-		spi->ctrl->freq = max_hz;
-	}
-	spi->ctrl->mode = mode;
-
-	return &spi->slave;
+	return 0;
 }
 
-void tegra20_spi_free_slave(struct spi_slave *slave)
+static int tegra20_sflash_probe(struct udevice *bus)
 {
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
-	free(spi);
-}
+	struct tegra_spi_platdata *plat = dev_get_platdata(bus);
+	struct tegra20_sflash_priv *priv = dev_get_priv(bus);
 
-int tegra20_spi_init(int *node_list, int count)
-{
-	struct tegra_spi_ctrl *ctrl;
-	int i;
-	int node = 0;
-	int found = 0;
-
-	for (i = 0; i < count; i++) {
-		ctrl = &spi_ctrls[i];
-		node = node_list[i];
-
-		ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
-								node, "reg");
-		if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
-			debug("%s: no slink register found\n", __func__);
-			continue;
-		}
-		ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
-					    "spi-max-frequency", 0);
-		if (!ctrl->freq) {
-			debug("%s: no slink max frequency found\n", __func__);
-			continue;
-		}
+	priv->regs = (struct spi_regs *)plat->base;
 
-		ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
-		if (ctrl->periph_id == PERIPH_ID_NONE) {
-			debug("%s: could not decode periph id\n", __func__);
-			continue;
-		}
-		ctrl->valid = 1;
-		found = 1;
+	priv->last_transaction_us = timer_get_us();
+	priv->freq = plat->frequency;
+	priv->periph_id = plat->periph_id;
 
-		debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
-		      __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
-	}
-	return !found;
+	return 0;
 }
 
-int tegra20_spi_claim_bus(struct spi_slave *slave)
+static int tegra20_sflash_claim_bus(struct udevice *bus)
 {
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_regs *regs = spi->ctrl->regs;
+	struct tegra20_sflash_priv *priv = dev_get_priv(bus);
+	struct spi_regs *regs = priv->regs;
 	u32 reg;
 
 	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
-	clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
-			       spi->ctrl->freq);
+	clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+			       priv->freq);
 
 	/* Clear stale status here */
 	reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
@@ -197,8 +144,8 @@ int tegra20_spi_claim_bus(struct spi_slave *slave)
 	/*
 	 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
 	 */
-	reg = (spi->ctrl->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
-	if (spi->ctrl->mode & 2)
+	reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
+	if (priv->mode & 2)
 		reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
 	clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
 		SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
@@ -215,37 +162,54 @@ int tegra20_spi_claim_bus(struct spi_slave *slave)
 	return 0;
 }
 
-void tegra20_spi_cs_activate(struct spi_slave *slave)
+static void spi_cs_activate(struct udevice *dev)
 {
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_regs *regs = spi->ctrl->regs;
+	struct udevice *bus = dev->parent;
+	struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+	struct tegra20_sflash_priv *priv = dev_get_priv(bus);
+
+	/* If it's too soon to do another transaction, wait */
+	if (pdata->deactivate_delay_us &&
+	    priv->last_transaction_us) {
+		ulong delay_us;		/* The delay completed so far */
+		delay_us = timer_get_us() - priv->last_transaction_us;
+		if (delay_us < pdata->deactivate_delay_us)
+			udelay(pdata->deactivate_delay_us - delay_us);
+	}
 
 	/* CS is negated on Tegra, so drive a 1 to get a 0 */
-	setbits_le32(&regs->command, SPI_CMD_CS_VAL);
+	setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
 }
 
-void tegra20_spi_cs_deactivate(struct spi_slave *slave)
+static void spi_cs_deactivate(struct udevice *dev)
 {
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_regs *regs = spi->ctrl->regs;
+	struct udevice *bus = dev->parent;
+	struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+	struct tegra20_sflash_priv *priv = dev_get_priv(bus);
 
 	/* CS is negated on Tegra, so drive a 0 to get a 1 */
-	clrbits_le32(&regs->command, SPI_CMD_CS_VAL);
+	clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
+
+	/* Remember time of this transaction so we can honour the bus delay */
+	if (pdata->deactivate_delay_us)
+		priv->last_transaction_us = timer_get_us();
 }
 
-int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-		const void *data_out, void *data_in, unsigned long flags)
+static int tegra20_sflash_xfer(struct udevice *dev, unsigned int bitlen,
+			     const void *data_out, void *data_in,
+			     unsigned long flags)
 {
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_regs *regs = spi->ctrl->regs;
+	struct udevice *bus = dev->parent;
+	struct tegra20_sflash_priv *priv = dev_get_priv(bus);
+	struct spi_regs *regs = priv->regs;
 	u32 reg, tmpdout, tmpdin = 0;
 	const u8 *dout = data_out;
 	u8 *din = data_in;
 	int num_bytes;
 	int ret;
 
-	debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
-	      slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
+	debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
+	      __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
 	if (bitlen % 8)
 		return -1;
 	num_bytes = bitlen / 8;
@@ -262,7 +226,7 @@ int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 	debug("spi_xfer: COMMAND = %08x\n", readl(&regs->command));
 
 	if (flags & SPI_XFER_BEGIN)
-		spi_cs_activate(slave);
+		spi_cs_activate(dev);
 
 	/* handle data in 32-bit chunks */
 	while (num_bytes > 0) {
@@ -327,7 +291,7 @@ int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 	}
 
 	if (flags & SPI_XFER_END)
-		spi_cs_deactivate(slave);
+		spi_cs_deactivate(dev);
 
 	debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
 		tmpdin, readl(&regs->status));
@@ -339,3 +303,51 @@ int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 
 	return 0;
 }
+
+static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
+{
+	struct tegra_spi_platdata *plat = bus->platdata;
+	struct tegra20_sflash_priv *priv = dev_get_priv(bus);
+
+	if (speed > plat->frequency)
+		speed = plat->frequency;
+	priv->freq = speed;
+	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
+
+	return 0;
+}
+
+static int tegra20_sflash_set_mode(struct udevice *bus, uint mode)
+{
+	struct tegra20_sflash_priv *priv = dev_get_priv(bus);
+
+	priv->mode = mode;
+	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+
+	return 0;
+}
+
+static const struct dm_spi_ops tegra20_sflash_ops = {
+	.claim_bus	= tegra20_sflash_claim_bus,
+	.xfer		= tegra20_sflash_xfer,
+	.set_speed	= tegra20_sflash_set_speed,
+	.set_mode	= tegra20_sflash_set_mode,
+	.cs_info	= tegra20_sflash_cs_info,
+};
+
+static const struct udevice_id tegra20_sflash_ids[] = {
+	{ .compatible = "nvidia,tegra20-sflash" },
+	{ }
+};
+
+U_BOOT_DRIVER(tegra20_sflash) = {
+	.name	= "tegra20_sflash",
+	.id	= UCLASS_SPI,
+	.of_match = tegra20_sflash_ids,
+	.ops	= &tegra20_sflash_ops,
+	.ofdata_to_platdata = tegra20_sflash_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
+	.priv_auto_alloc_size = sizeof(struct tegra20_sflash_priv),
+	.per_child_auto_alloc_size	= sizeof(struct spi_slave),
+	.probe	= tegra20_sflash_probe,
+};
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index 664de6e9166..213fa5f7939 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -22,14 +22,13 @@
  */
 
 #include <common.h>
-#include <malloc.h>
+#include <dm.h>
 #include <asm/io.h>
-#include <asm/gpio.h>
 #include <asm/arch/clock.h>
 #include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra20/tegra20_slink.h>
 #include <spi.h>
 #include <fdtdec.h>
+#include "tegra_spi.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -87,130 +86,70 @@ struct spi_regs {
 	u32 rx_fifo;	/* SLINK_RX_FIFO_0 reg off 180h */
 };
 
-struct tegra_spi_ctrl {
+struct tegra30_spi_priv {
 	struct spi_regs *regs;
 	unsigned int freq;
 	unsigned int mode;
 	int periph_id;
 	int valid;
+	int last_transaction_us;
 };
 
 struct tegra_spi_slave {
 	struct spi_slave slave;
-	struct tegra_spi_ctrl *ctrl;
+	struct tegra30_spi_priv *ctrl;
 };
 
-static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA_SLINK_CTRLS];
-
-static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
-{
-	return container_of(slave, struct tegra_spi_slave, slave);
-}
-
-int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static int tegra30_spi_ofdata_to_platdata(struct udevice *bus)
 {
-	if (bus >= CONFIG_TEGRA_SLINK_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
-		return 0;
-	else
-		return 1;
-}
+	struct tegra_spi_platdata *plat = bus->platdata;
+	const void *blob = gd->fdt_blob;
+	int node = bus->of_offset;
 
-struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs,
-		unsigned int max_hz, unsigned int mode)
-{
-	struct tegra_spi_slave *spi;
+	plat->base = fdtdec_get_addr(blob, node, "reg");
+	plat->periph_id = clock_decode_periph_id(blob, node);
 
-	debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
-		bus, cs, max_hz, mode);
-
-	if (!spi_cs_is_valid(bus, cs)) {
-		printf("SPI error: unsupported bus %d / chip select %d\n",
-		       bus, cs);
-		return NULL;
-	}
-
-	if (max_hz > TEGRA_SPI_MAX_FREQ) {
-		printf("SPI error: unsupported frequency %d Hz. Max frequency"
-			" is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
-		return NULL;
+	if (plat->periph_id == PERIPH_ID_NONE) {
+		debug("%s: could not decode periph id %d\n", __func__,
+		      plat->periph_id);
+		return -FDT_ERR_NOTFOUND;
 	}
 
-	spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
-	if (!spi) {
-		printf("SPI error: malloc of SPI structure failed\n");
-		return NULL;
-	}
-	spi->ctrl = &spi_ctrls[bus];
-	if (!spi->ctrl) {
-		printf("SPI error: could not find controller for bus %d\n",
-		       bus);
-		return NULL;
-	}
+	/* Use 500KHz as a suitable default */
+	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+					500000);
+	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
+					"spi-deactivate-delay", 0);
+	debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+	      __func__, plat->base, plat->periph_id, plat->frequency,
+	      plat->deactivate_delay_us);
 
-	if (max_hz < spi->ctrl->freq) {
-		debug("%s: limiting frequency from %u to %u\n", __func__,
-		      spi->ctrl->freq, max_hz);
-		spi->ctrl->freq = max_hz;
-	}
-	spi->ctrl->mode = mode;
-
-	return &spi->slave;
+	return 0;
 }
 
-void tegra30_spi_free_slave(struct spi_slave *slave)
+static int tegra30_spi_probe(struct udevice *bus)
 {
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
-	free(spi);
-}
+	struct tegra_spi_platdata *plat = dev_get_platdata(bus);
+	struct tegra30_spi_priv *priv = dev_get_priv(bus);
 
-int tegra30_spi_init(int *node_list, int count)
-{
-	struct tegra_spi_ctrl *ctrl;
-	int i;
-	int node = 0;
-	int found = 0;
-
-	for (i = 0; i < count; i++) {
-		ctrl = &spi_ctrls[i];
-		node = node_list[i];
-
-		ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
-								node, "reg");
-		if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
-			debug("%s: no slink register found\n", __func__);
-			continue;
-		}
-		ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
-					    "spi-max-frequency", 0);
-		if (!ctrl->freq) {
-			debug("%s: no slink max frequency found\n", __func__);
-			continue;
-		}
+	priv->regs = (struct spi_regs *)plat->base;
 
-		ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
-		if (ctrl->periph_id == PERIPH_ID_NONE) {
-			debug("%s: could not decode periph id\n", __func__);
-			continue;
-		}
-		ctrl->valid = 1;
-		found = 1;
+	priv->last_transaction_us = timer_get_us();
+	priv->freq = plat->frequency;
+	priv->periph_id = plat->periph_id;
 
-		debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
-		      __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
-	}
-	return !found;
+	return 0;
 }
 
-int tegra30_spi_claim_bus(struct spi_slave *slave)
+static int tegra30_spi_claim_bus(struct udevice *bus)
 {
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_regs *regs = spi->ctrl->regs;
+	struct tegra30_spi_priv *priv = dev_get_priv(bus);
+	struct spi_regs *regs = priv->regs;
 	u32 reg;
 
 	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
-	clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
-			       spi->ctrl->freq);
+	clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+			       priv->freq);
 
 	/* Clear stale status here */
 	reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
@@ -227,29 +166,46 @@ int tegra30_spi_claim_bus(struct spi_slave *slave)
 	return 0;
 }
 
-void tegra30_spi_cs_activate(struct spi_slave *slave)
+static void spi_cs_activate(struct udevice *dev)
 {
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_regs *regs = spi->ctrl->regs;
+	struct udevice *bus = dev->parent;
+	struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+	struct tegra30_spi_priv *priv = dev_get_priv(bus);
+
+	/* If it's too soon to do another transaction, wait */
+	if (pdata->deactivate_delay_us &&
+	    priv->last_transaction_us) {
+		ulong delay_us;		/* The delay completed so far */
+		delay_us = timer_get_us() - priv->last_transaction_us;
+		if (delay_us < pdata->deactivate_delay_us)
+			udelay(pdata->deactivate_delay_us - delay_us);
+	}
 
 	/* CS is negated on Tegra, so drive a 1 to get a 0 */
-	setbits_le32(&regs->command, SLINK_CMD_CS_VAL);
+	setbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
 }
 
-void tegra30_spi_cs_deactivate(struct spi_slave *slave)
+static void spi_cs_deactivate(struct udevice *dev)
 {
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_regs *regs = spi->ctrl->regs;
+	struct udevice *bus = dev->parent;
+	struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+	struct tegra30_spi_priv *priv = dev_get_priv(bus);
 
 	/* CS is negated on Tegra, so drive a 0 to get a 1 */
-	clrbits_le32(&regs->command, SLINK_CMD_CS_VAL);
+	clrbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
+
+	/* Remember time of this transaction so we can honour the bus delay */
+	if (pdata->deactivate_delay_us)
+		priv->last_transaction_us = timer_get_us();
 }
 
-int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-		const void *data_out, void *data_in, unsigned long flags)
+static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen,
+			    const void *data_out, void *data_in,
+			    unsigned long flags)
 {
-	struct tegra_spi_slave *spi = to_tegra_spi(slave);
-	struct spi_regs *regs = spi->ctrl->regs;
+	struct udevice *bus = dev->parent;
+	struct tegra30_spi_priv *priv = dev_get_priv(bus);
+	struct spi_regs *regs = priv->regs;
 	u32 reg, tmpdout, tmpdin = 0;
 	const u8 *dout = data_out;
 	u8 *din = data_in;
@@ -257,7 +213,7 @@ int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 	int ret;
 
 	debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
-	      __func__, slave->bus, slave->cs, dout, din, bitlen);
+	      __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
 	if (bitlen % 8)
 		return -1;
 	num_bytes = bitlen / 8;
@@ -276,11 +232,11 @@ int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 
 	clrsetbits_le32(&regs->command2, SLINK_CMD2_SS_EN_MASK,
 			SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
-			(slave->cs << SLINK_CMD2_SS_EN_SHIFT));
+			(spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT));
 	debug("%s entry: COMMAND2 = %08x\n", __func__, readl(&regs->command2));
 
 	if (flags & SPI_XFER_BEGIN)
-		spi_cs_activate(slave);
+		spi_cs_activate(dev);
 
 	/* handle data in 32-bit chunks */
 	while (num_bytes > 0) {
@@ -344,7 +300,7 @@ int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 	}
 
 	if (flags & SPI_XFER_END)
-		spi_cs_deactivate(slave);
+		spi_cs_deactivate(dev);
 
 	debug("%s: transfer ended. Value=%08x, status = %08x\n",
 	      __func__, tmpdin, readl(&regs->status));
@@ -357,3 +313,54 @@ int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 
 	return 0;
 }
+
+static int tegra30_spi_set_speed(struct udevice *bus, uint speed)
+{
+	struct tegra_spi_platdata *plat = bus->platdata;
+	struct tegra30_spi_priv *priv = dev_get_priv(bus);
+
+	if (speed > plat->frequency)
+		speed = plat->frequency;
+	priv->freq = speed;
+	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
+
+	return 0;
+}
+
+static int tegra30_spi_set_mode(struct udevice *bus, uint mode)
+{
+	struct tegra30_spi_priv *priv = dev_get_priv(bus);
+
+	priv->mode = mode;
+	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+
+	return 0;
+}
+
+static const struct dm_spi_ops tegra30_spi_ops = {
+	.claim_bus	= tegra30_spi_claim_bus,
+	.xfer		= tegra30_spi_xfer,
+	.set_speed	= tegra30_spi_set_speed,
+	.set_mode	= tegra30_spi_set_mode,
+	/*
+	 * cs_info is not needed, since we require all chip selects to be
+	 * in the device tree explicitly
+	 */
+};
+
+static const struct udevice_id tegra30_spi_ids[] = {
+	{ .compatible = "nvidia,tegra20-slink" },
+	{ }
+};
+
+U_BOOT_DRIVER(tegra30_spi) = {
+	.name	= "tegra20_slink",
+	.id	= UCLASS_SPI,
+	.of_match = tegra30_spi_ids,
+	.ops	= &tegra30_spi_ops,
+	.ofdata_to_platdata = tegra30_spi_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
+	.priv_auto_alloc_size = sizeof(struct tegra30_spi_priv),
+	.per_child_auto_alloc_size	= sizeof(struct spi_slave),
+	.probe	= tegra30_spi_probe,
+};
diff --git a/drivers/spi/tegra_spi.h b/drivers/spi/tegra_spi.h
new file mode 100644
index 00000000000..fb2b50f0bc7
--- /dev/null
+++ b/drivers/spi/tegra_spi.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+struct tegra_spi_platdata {
+	enum periph_id periph_id;
+	int frequency;		/* Default clock frequency, -1 for none */
+	ulong base;
+	uint deactivate_delay_us;	/* Delay to wait after deactivate */
+};
diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c
index 6557055e02b..11811094ede 100644
--- a/drivers/usb/eth/asix.c
+++ b/drivers/usb/eth/asix.c
@@ -580,6 +580,7 @@ static const struct asix_dongle asix_dongles[] = {
 	{ 0x2001, 0x3c05, FLAG_TYPE_AX88772 },
 	/* ASIX 88772B */
 	{ 0x0b95, 0x772b, FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC },
+	{ 0x0b95, 0x7e2b, FLAG_TYPE_AX88772B },
 	{ 0x0000, 0x0000, FLAG_NONE }	/* END - Do not remove */
 };
 
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index c4f5157a843..1c3592914dc 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -43,5 +43,9 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
 
 # xhci
 obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
+obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
 obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
 obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
+
+# designware
+obj-$(CONFIG_USB_DWC2) += dwc2.o
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
new file mode 100644
index 00000000000..2a5bbf5ac0e
--- /dev/null
+++ b/drivers/usb/host/dwc2.c
@@ -0,0 +1,1053 @@
+/*
+ * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <usb.h>
+#include <malloc.h>
+#include <usbroothubdes.h>
+#include <asm/io.h>
+
+#include "dwc2.h"
+
+/* Use only HC channel 0. */
+#define DWC2_HC_CHANNEL			0
+
+#define DWC2_STATUS_BUF_SIZE		64
+#define DWC2_DATA_BUF_SIZE		(64 * 1024)
+
+/* We need doubleword-aligned buffers for DMA transfers */
+DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer, DWC2_DATA_BUF_SIZE, 8);
+DEFINE_ALIGN_BUFFER(uint8_t, status_buffer, DWC2_STATUS_BUF_SIZE, 8);
+
+#define MAX_DEVICE			16
+#define MAX_ENDPOINT			16
+static int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
+static int control_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
+
+static int root_hub_devnum;
+
+static struct dwc2_core_regs *regs =
+	(struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
+
+/*
+ * DWC2 IP interface
+ */
+static int wait_for_bit(void *reg, const uint32_t mask, bool set)
+{
+	unsigned int timeout = 1000000;
+	uint32_t val;
+
+	while (--timeout) {
+		val = readl(reg);
+		if (!set)
+			val = ~val;
+
+		if ((val & mask) == mask)
+			return 0;
+
+		udelay(1);
+	}
+
+	debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
+	      __func__, reg, mask, set);
+
+	return -ETIMEDOUT;
+}
+
+/*
+ * Initializes the FSLSPClkSel field of the HCFG register
+ * depending on the PHY type.
+ */
+static void init_fslspclksel(struct dwc2_core_regs *regs)
+{
+	uint32_t phyclk;
+
+#if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
+	phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;	/* Full speed PHY */
+#else
+	/* High speed PHY running at full speed or high speed */
+	phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
+#endif
+
+#ifdef CONFIG_DWC2_ULPI_FS_LS
+	uint32_t hwcfg2 = readl(&regs->ghwcfg2);
+	uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
+			DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
+	uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
+			DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
+
+	if (hval == 2 && fval == 1)
+		phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;	/* Full speed PHY */
+#endif
+
+	clrsetbits_le32(&regs->host_regs.hcfg,
+			DWC2_HCFG_FSLSPCLKSEL_MASK,
+			phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
+}
+
+/*
+ * Flush a Tx FIFO.
+ *
+ * @param regs Programming view of DWC_otg controller.
+ * @param num Tx FIFO to flush.
+ */
+static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
+{
+	int ret;
+
+	writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
+	       &regs->grstctl);
+	ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
+	if (ret)
+		printf("%s: Timeout!\n", __func__);
+
+	/* Wait for 3 PHY Clocks */
+	udelay(1);
+}
+
+/*
+ * Flush Rx FIFO.
+ *
+ * @param regs Programming view of DWC_otg controller.
+ */
+static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
+{
+	int ret;
+
+	writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
+	ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
+	if (ret)
+		printf("%s: Timeout!\n", __func__);
+
+	/* Wait for 3 PHY Clocks */
+	udelay(1);
+}
+
+/*
+ * Do core a soft reset of the core.  Be careful with this because it
+ * resets all the internal state machines of the core.
+ */
+static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
+{
+	int ret;
+
+	/* Wait for AHB master IDLE state. */
+	ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
+	if (ret)
+		printf("%s: Timeout!\n", __func__);
+
+	/* Core Soft Reset */
+	writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
+	ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
+	if (ret)
+		printf("%s: Timeout!\n", __func__);
+
+	/*
+	 * Wait for core to come out of reset.
+	 * NOTE: This long sleep is _very_ important, otherwise the core will
+	 *       not stay in host mode after a connector ID change!
+	 */
+	mdelay(100);
+}
+
+/*
+ * This function initializes the DWC_otg controller registers for
+ * host mode.
+ *
+ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
+ * request queues. Host channels are reset to ensure that they are ready for
+ * performing transfers.
+ *
+ * @param regs Programming view of DWC_otg controller
+ *
+ */
+static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
+{
+	uint32_t nptxfifosize = 0;
+	uint32_t ptxfifosize = 0;
+	uint32_t hprt0 = 0;
+	int i, ret, num_channels;
+
+	/* Restart the Phy Clock */
+	writel(0, &regs->pcgcctl);
+
+	/* Initialize Host Configuration Register */
+	init_fslspclksel(regs);
+#ifdef CONFIG_DWC2_DFLT_SPEED_FULL
+	setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
+#endif
+
+	/* Configure data FIFO sizes */
+#ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
+	if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
+		/* Rx FIFO */
+		writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
+
+		/* Non-periodic Tx FIFO */
+		nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
+				DWC2_FIFOSIZE_DEPTH_OFFSET;
+		nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
+				DWC2_FIFOSIZE_STARTADDR_OFFSET;
+		writel(nptxfifosize, &regs->gnptxfsiz);
+
+		/* Periodic Tx FIFO */
+		ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
+				DWC2_FIFOSIZE_DEPTH_OFFSET;
+		ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
+				CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
+				DWC2_FIFOSIZE_STARTADDR_OFFSET;
+		writel(ptxfifosize, &regs->hptxfsiz);
+	}
+#endif
+
+	/* Clear Host Set HNP Enable in the OTG Control Register */
+	clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
+
+	/* Make sure the FIFOs are flushed. */
+	dwc_otg_flush_tx_fifo(regs, 0x10);	/* All Tx FIFOs */
+	dwc_otg_flush_rx_fifo(regs);
+
+	/* Flush out any leftover queued requests. */
+	num_channels = readl(&regs->ghwcfg2);
+	num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
+	num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
+	num_channels += 1;
+
+	for (i = 0; i < num_channels; i++)
+		clrsetbits_le32(&regs->hc_regs[i].hcchar,
+				DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
+				DWC2_HCCHAR_CHDIS);
+
+	/* Halt all channels to put them into a known state. */
+	for (i = 0; i < num_channels; i++) {
+		clrsetbits_le32(&regs->hc_regs[i].hcchar,
+				DWC2_HCCHAR_EPDIR,
+				DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
+		ret = wait_for_bit(&regs->hc_regs[i].hcchar,
+				   DWC2_HCCHAR_CHEN, 0);
+		if (ret)
+			printf("%s: Timeout!\n", __func__);
+	}
+
+	/* Turn on the vbus power. */
+	if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
+		hprt0 = readl(&regs->hprt0);
+		hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
+		hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
+		if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
+			hprt0 |= DWC2_HPRT0_PRTPWR;
+			writel(hprt0, &regs->hprt0);
+		}
+	}
+}
+
+/*
+ * This function initializes the DWC_otg controller registers and
+ * prepares the core for device mode or host mode operation.
+ *
+ * @param regs Programming view of the DWC_otg controller
+ */
+static void dwc_otg_core_init(struct dwc2_core_regs *regs)
+{
+	uint32_t ahbcfg = 0;
+	uint32_t usbcfg = 0;
+	uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
+
+	/* Common Initialization */
+	usbcfg = readl(&regs->gusbcfg);
+
+	/* Program the ULPI External VBUS bit if needed */
+#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
+	usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
+#else
+	usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
+#endif
+
+	/* Set external TS Dline pulsing */
+#ifdef CONFIG_DWC2_TS_DLINE
+	usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
+#else
+	usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
+#endif
+	writel(usbcfg, &regs->gusbcfg);
+
+	/* Reset the Controller */
+	dwc_otg_core_reset(regs);
+
+	/*
+	 * This programming sequence needs to happen in FS mode before
+	 * any other programming occurs
+	 */
+#if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
+	(CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
+	/* If FS mode with FS PHY */
+	setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
+
+	/* Reset after a PHY select */
+	dwc_otg_core_reset(regs);
+
+	/*
+	 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
+	 * Also do this on HNP Dev/Host mode switches (done in dev_init
+	 * and host_init).
+	 */
+	if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
+		init_fslspclksel(regs);
+
+#ifdef CONFIG_DWC2_I2C_ENABLE
+	/* Program GUSBCFG.OtgUtmifsSel to I2C */
+	setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
+
+	/* Program GI2CCTL.I2CEn */
+	clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
+			DWC2_GI2CCTL_I2CDEVADDR_MASK,
+			1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
+	setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
+#endif
+
+#else
+	/* High speed PHY. */
+
+	/*
+	 * HS PHY parameters. These parameters are preserved during
+	 * soft reset so only program the first time. Do a soft reset
+	 * immediately after setting phyif.
+	 */
+	usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
+	usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
+
+	if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) {	/* ULPI interface */
+#ifdef CONFIG_DWC2_PHY_ULPI_DDR
+		usbcfg |= DWC2_GUSBCFG_DDRSEL;
+#else
+		usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
+#endif
+	} else {	/* UTMI+ interface */
+#if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
+		usbcfg |= DWC2_GUSBCFG_PHYIF;
+#endif
+	}
+
+	writel(usbcfg, &regs->gusbcfg);
+
+	/* Reset after setting the PHY parameters */
+	dwc_otg_core_reset(regs);
+#endif
+
+	usbcfg = readl(&regs->gusbcfg);
+	usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
+#ifdef CONFIG_DWC2_ULPI_FS_LS
+	uint32_t hwcfg2 = readl(&regs->ghwcfg2);
+	uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
+			DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
+	uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
+			DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
+	if (hval == 2 && fval == 1) {
+		usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
+		usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
+	}
+#endif
+	writel(usbcfg, &regs->gusbcfg);
+
+	/* Program the GAHBCFG Register. */
+	switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
+	case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
+		break;
+	case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
+		while (brst_sz > 1) {
+			ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
+			ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
+			brst_sz >>= 1;
+		}
+
+#ifdef CONFIG_DWC2_DMA_ENABLE
+		ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
+#endif
+		break;
+
+	case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
+		ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
+#ifdef CONFIG_DWC2_DMA_ENABLE
+		ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
+#endif
+		break;
+	}
+
+	writel(ahbcfg, &regs->gahbcfg);
+
+	/* Program the GUSBCFG register for HNP/SRP. */
+	setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
+
+#ifdef CONFIG_DWC2_IC_USB_CAP
+	setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
+#endif
+}
+
+/*
+ * Prepares a host channel for transferring packets to/from a specific
+ * endpoint. The HCCHARn register is set up with the characteristics specified
+ * in _hc. Host channel interrupts that may need to be serviced while this
+ * transfer is in progress are enabled.
+ *
+ * @param regs Programming view of DWC_otg controller
+ * @param hc Information needed to initialize the host channel
+ */
+static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
+		uint8_t dev_addr, uint8_t ep_num, uint8_t ep_is_in,
+		uint8_t ep_type, uint16_t max_packet)
+{
+	struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
+	const uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
+				(ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
+				(ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
+				(ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
+				(max_packet << DWC2_HCCHAR_MPS_OFFSET);
+
+	/* Clear old interrupt conditions for this host channel. */
+	writel(0x3fff, &hc_regs->hcint);
+
+	/*
+	 * Program the HCCHARn register with the endpoint characteristics
+	 * for the current transfer.
+	 */
+	writel(hcchar, &hc_regs->hcchar);
+
+	/* Program the HCSPLIT register for SPLITs */
+	writel(0, &hc_regs->hcsplt);
+}
+
+/*
+ * DWC2 to USB API interface
+ */
+/* Direction: In ; Request: Status */
+static int dwc_otg_submit_rh_msg_in_status(struct usb_device *dev, void *buffer,
+					   int txlen, struct devrequest *cmd)
+{
+	uint32_t hprt0 = 0;
+	uint32_t port_status = 0;
+	uint32_t port_change = 0;
+	int len = 0;
+	int stat = 0;
+
+	switch (cmd->requesttype & ~USB_DIR_IN) {
+	case 0:
+		*(uint16_t *)buffer = cpu_to_le16(1);
+		len = 2;
+		break;
+	case USB_RECIP_INTERFACE:
+	case USB_RECIP_ENDPOINT:
+		*(uint16_t *)buffer = cpu_to_le16(0);
+		len = 2;
+		break;
+	case USB_TYPE_CLASS:
+		*(uint32_t *)buffer = cpu_to_le32(0);
+		len = 4;
+		break;
+	case USB_RECIP_OTHER | USB_TYPE_CLASS:
+		hprt0 = readl(&regs->hprt0);
+		if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
+			port_status |= USB_PORT_STAT_CONNECTION;
+		if (hprt0 & DWC2_HPRT0_PRTENA)
+			port_status |= USB_PORT_STAT_ENABLE;
+		if (hprt0 & DWC2_HPRT0_PRTSUSP)
+			port_status |= USB_PORT_STAT_SUSPEND;
+		if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
+			port_status |= USB_PORT_STAT_OVERCURRENT;
+		if (hprt0 & DWC2_HPRT0_PRTRST)
+			port_status |= USB_PORT_STAT_RESET;
+		if (hprt0 & DWC2_HPRT0_PRTPWR)
+			port_status |= USB_PORT_STAT_POWER;
+
+		port_status |= USB_PORT_STAT_HIGH_SPEED;
+
+		if (hprt0 & DWC2_HPRT0_PRTENCHNG)
+			port_change |= USB_PORT_STAT_C_ENABLE;
+		if (hprt0 & DWC2_HPRT0_PRTCONNDET)
+			port_change |= USB_PORT_STAT_C_CONNECTION;
+		if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
+			port_change |= USB_PORT_STAT_C_OVERCURRENT;
+
+		*(uint32_t *)buffer = cpu_to_le32(port_status |
+					(port_change << 16));
+		len = 4;
+		break;
+	default:
+		puts("unsupported root hub command\n");
+		stat = USB_ST_STALLED;
+	}
+
+	dev->act_len = min(len, txlen);
+	dev->status = stat;
+
+	return stat;
+}
+
+/* Direction: In ; Request: Descriptor */
+static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
+					       void *buffer, int txlen,
+					       struct devrequest *cmd)
+{
+	unsigned char data[32];
+	uint32_t dsc;
+	int len = 0;
+	int stat = 0;
+	uint16_t wValue = cpu_to_le16(cmd->value);
+	uint16_t wLength = cpu_to_le16(cmd->length);
+
+	switch (cmd->requesttype & ~USB_DIR_IN) {
+	case 0:
+		switch (wValue & 0xff00) {
+		case 0x0100:	/* device descriptor */
+			len = min3(txlen, sizeof(root_hub_dev_des), wLength);
+			memcpy(buffer, root_hub_dev_des, len);
+			break;
+		case 0x0200:	/* configuration descriptor */
+			len = min3(txlen, sizeof(root_hub_config_des), wLength);
+			memcpy(buffer, root_hub_config_des, len);
+			break;
+		case 0x0300:	/* string descriptors */
+			switch (wValue & 0xff) {
+			case 0x00:
+				len = min3(txlen, sizeof(root_hub_str_index0),
+					   wLength);
+				memcpy(buffer, root_hub_str_index0, len);
+				break;
+			case 0x01:
+				len = min3(txlen, sizeof(root_hub_str_index1),
+					   wLength);
+				memcpy(buffer, root_hub_str_index1, len);
+				break;
+			}
+			break;
+		default:
+			stat = USB_ST_STALLED;
+		}
+		break;
+
+	case USB_TYPE_CLASS:
+		/* Root port config, set 1 port and nothing else. */
+		dsc = 0x00000001;
+
+		data[0] = 9;		/* min length; */
+		data[1] = 0x29;
+		data[2] = dsc & RH_A_NDP;
+		data[3] = 0;
+		if (dsc & RH_A_PSM)
+			data[3] |= 0x1;
+		if (dsc & RH_A_NOCP)
+			data[3] |= 0x10;
+		else if (dsc & RH_A_OCPM)
+			data[3] |= 0x8;
+
+		/* corresponds to data[4-7] */
+		data[5] = (dsc & RH_A_POTPGT) >> 24;
+		data[7] = dsc & RH_B_DR;
+		if (data[2] < 7) {
+			data[8] = 0xff;
+		} else {
+			data[0] += 2;
+			data[8] = (dsc & RH_B_DR) >> 8;
+			data[9] = 0xff;
+			data[10] = data[9];
+		}
+
+		len = min3(txlen, data[0], wLength);
+		memcpy(buffer, data, len);
+		break;
+	default:
+		puts("unsupported root hub command\n");
+		stat = USB_ST_STALLED;
+	}
+
+	dev->act_len = min(len, txlen);
+	dev->status = stat;
+
+	return stat;
+}
+
+/* Direction: In ; Request: Configuration */
+static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
+						  void *buffer, int txlen,
+						  struct devrequest *cmd)
+{
+	int len = 0;
+	int stat = 0;
+
+	switch (cmd->requesttype & ~USB_DIR_IN) {
+	case 0:
+		*(uint8_t *)buffer = 0x01;
+		len = 1;
+		break;
+	default:
+		puts("unsupported root hub command\n");
+		stat = USB_ST_STALLED;
+	}
+
+	dev->act_len = min(len, txlen);
+	dev->status = stat;
+
+	return stat;
+}
+
+/* Direction: In */
+static int dwc_otg_submit_rh_msg_in(struct usb_device *dev,
+				 void *buffer, int txlen,
+				 struct devrequest *cmd)
+{
+	switch (cmd->request) {
+	case USB_REQ_GET_STATUS:
+		return dwc_otg_submit_rh_msg_in_status(dev, buffer,
+						       txlen, cmd);
+	case USB_REQ_GET_DESCRIPTOR:
+		return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
+							   txlen, cmd);
+	case USB_REQ_GET_CONFIGURATION:
+		return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
+							      txlen, cmd);
+	default:
+		puts("unsupported root hub command\n");
+		return USB_ST_STALLED;
+	}
+}
+
+/* Direction: Out */
+static int dwc_otg_submit_rh_msg_out(struct usb_device *dev,
+				 void *buffer, int txlen,
+				 struct devrequest *cmd)
+{
+	int len = 0;
+	int stat = 0;
+	uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
+	uint16_t wValue = cpu_to_le16(cmd->value);
+
+	switch (bmrtype_breq & ~USB_DIR_IN) {
+	case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
+	case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
+		break;
+
+	case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
+		switch (wValue) {
+		case USB_PORT_FEAT_C_CONNECTION:
+			setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
+			break;
+		}
+		break;
+
+	case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
+		switch (wValue) {
+		case USB_PORT_FEAT_SUSPEND:
+			break;
+
+		case USB_PORT_FEAT_RESET:
+			clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
+					DWC2_HPRT0_PRTCONNDET |
+					DWC2_HPRT0_PRTENCHNG |
+					DWC2_HPRT0_PRTOVRCURRCHNG,
+					DWC2_HPRT0_PRTRST);
+			mdelay(50);
+			clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
+			break;
+
+		case USB_PORT_FEAT_POWER:
+			clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
+					DWC2_HPRT0_PRTCONNDET |
+					DWC2_HPRT0_PRTENCHNG |
+					DWC2_HPRT0_PRTOVRCURRCHNG,
+					DWC2_HPRT0_PRTRST);
+			break;
+
+		case USB_PORT_FEAT_ENABLE:
+			break;
+		}
+		break;
+	case (USB_REQ_SET_ADDRESS << 8):
+		root_hub_devnum = wValue;
+		break;
+	case (USB_REQ_SET_CONFIGURATION << 8):
+		break;
+	default:
+		puts("unsupported root hub command\n");
+		stat = USB_ST_STALLED;
+	}
+
+	len = min(len, txlen);
+
+	dev->act_len = len;
+	dev->status = stat;
+
+	return stat;
+}
+
+static int dwc_otg_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+				 void *buffer, int txlen,
+				 struct devrequest *cmd)
+{
+	int stat = 0;
+
+	if (usb_pipeint(pipe)) {
+		puts("Root-Hub submit IRQ: NOT implemented\n");
+		return 0;
+	}
+
+	if (cmd->requesttype & USB_DIR_IN)
+		stat = dwc_otg_submit_rh_msg_in(dev, buffer, txlen, cmd);
+	else
+		stat = dwc_otg_submit_rh_msg_out(dev, buffer, txlen, cmd);
+
+	mdelay(1);
+
+	return stat;
+}
+
+/* U-Boot USB transmission interface */
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		    int len)
+{
+	int devnum = usb_pipedevice(pipe);
+	int ep = usb_pipeendpoint(pipe);
+	int max = usb_maxpacket(dev, pipe);
+	int done = 0;
+	uint32_t hctsiz, sub, tmp;
+	struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
+	uint32_t hcint;
+	uint32_t xfer_len;
+	uint32_t num_packets;
+	int stop_transfer = 0;
+	unsigned int timeout = 1000000;
+
+	if (devnum == root_hub_devnum) {
+		dev->status = 0;
+		return -EINVAL;
+	}
+
+	if (len > DWC2_DATA_BUF_SIZE) {
+		printf("%s: %d is more then available buffer size (%d)\n",
+		       __func__, len, DWC2_DATA_BUF_SIZE);
+		dev->status = 0;
+		dev->act_len = 0;
+		return -EINVAL;
+	}
+
+	while ((done < len) && !stop_transfer) {
+		/* Initialize channel */
+		dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep,
+				usb_pipein(pipe), DWC2_HCCHAR_EPTYPE_BULK, max);
+
+		xfer_len = len - done;
+		/* Make sure that xfer_len is a multiple of max packet size. */
+		if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
+			xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
+
+		if (xfer_len > 0) {
+			num_packets = (xfer_len + max - 1) / max;
+			if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
+				num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
+				xfer_len = num_packets * max;
+			}
+		} else {
+			num_packets = 1;
+		}
+
+		if (usb_pipein(pipe))
+			xfer_len = num_packets * max;
+
+		writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
+		       (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
+		       (bulk_data_toggle[devnum][ep] <<
+				DWC2_HCTSIZ_PID_OFFSET),
+		       &hc_regs->hctsiz);
+
+		memcpy(aligned_buffer, (char *)buffer + done, len - done);
+		writel((uint32_t)aligned_buffer, &hc_regs->hcdma);
+
+		/* Set host channel enable after all other setup is complete. */
+		clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
+				DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
+				(1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
+				DWC2_HCCHAR_CHEN);
+
+		while (1) {
+			hcint = readl(&hc_regs->hcint);
+
+			if (!(hcint & DWC2_HCINT_CHHLTD))
+				continue;
+
+			if (hcint & DWC2_HCINT_XFERCOMP) {
+				hctsiz = readl(&hc_regs->hctsiz);
+				done += xfer_len;
+
+				sub = hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK;
+				sub >>= DWC2_HCTSIZ_XFERSIZE_OFFSET;
+
+				if (usb_pipein(pipe)) {
+					done -= sub;
+					if (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK)
+						stop_transfer = 1;
+				}
+
+				tmp = hctsiz & DWC2_HCTSIZ_PID_MASK;
+				tmp >>= DWC2_HCTSIZ_PID_OFFSET;
+				if (tmp == DWC2_HC_PID_DATA1) {
+					bulk_data_toggle[devnum][ep] =
+						DWC2_HC_PID_DATA1;
+				} else {
+					bulk_data_toggle[devnum][ep] =
+						DWC2_HC_PID_DATA0;
+				}
+				break;
+			}
+
+			if (hcint & DWC2_HCINT_STALL) {
+				puts("DWC OTG: Channel halted\n");
+				bulk_data_toggle[devnum][ep] =
+					DWC2_HC_PID_DATA0;
+
+				stop_transfer = 1;
+				break;
+			}
+
+			if (!--timeout) {
+				printf("%s: Timeout!\n", __func__);
+				break;
+			}
+		}
+	}
+
+	if (done && usb_pipein(pipe))
+		memcpy(buffer, aligned_buffer, done);
+
+	writel(0, &hc_regs->hcintmsk);
+	writel(0xFFFFFFFF, &hc_regs->hcint);
+
+	dev->status = 0;
+	dev->act_len = done;
+
+	return 0;
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		       int len, struct devrequest *setup)
+{
+	struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
+	int done = 0;
+	int devnum = usb_pipedevice(pipe);
+	int ep = usb_pipeendpoint(pipe);
+	int max = usb_maxpacket(dev, pipe);
+	uint32_t hctsiz = 0, sub, tmp, ret;
+	uint32_t hcint;
+	const uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP |
+		DWC2_HCINT_CHHLTD | DWC2_HCINT_ACK;
+	unsigned int timeout = 1000000;
+
+	/* For CONTROL endpoint pid should start with DATA1 */
+	int status_direction;
+
+	if (devnum == root_hub_devnum) {
+		dev->status = 0;
+		dev->speed = USB_SPEED_HIGH;
+		return dwc_otg_submit_rh_msg(dev, pipe, buffer, len, setup);
+	}
+
+	if (len > DWC2_DATA_BUF_SIZE) {
+		printf("%s: %d is more then available buffer size(%d)\n",
+		       __func__, len, DWC2_DATA_BUF_SIZE);
+		dev->status = 0;
+		dev->act_len = 0;
+		return -EINVAL;
+	}
+
+	/* Initialize channel, OUT for setup buffer */
+	dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep, 0,
+			DWC2_HCCHAR_EPTYPE_CONTROL, max);
+
+	/* SETUP stage  */
+	writel((8 << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
+	       (1 << DWC2_HCTSIZ_PKTCNT_OFFSET) |
+	       (DWC2_HC_PID_SETUP << DWC2_HCTSIZ_PID_OFFSET),
+	       &hc_regs->hctsiz);
+
+	writel((uint32_t)setup, &hc_regs->hcdma);
+
+	/* Set host channel enable after all other setup is complete. */
+	clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
+			DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
+			(1 << DWC2_HCCHAR_MULTICNT_OFFSET) | DWC2_HCCHAR_CHEN);
+
+	ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, 1);
+	if (ret)
+		printf("%s: Timeout!\n", __func__);
+
+	hcint = readl(&hc_regs->hcint);
+
+	if (!(hcint & DWC2_HCINT_CHHLTD) || !(hcint & DWC2_HCINT_XFERCOMP)) {
+		printf("%s: Error (HCINT=%08x)\n", __func__, hcint);
+		dev->status = 0;
+		dev->act_len = 0;
+		return -EINVAL;
+	}
+
+	/* Clear interrupts */
+	writel(0, &hc_regs->hcintmsk);
+	writel(0xFFFFFFFF, &hc_regs->hcint);
+
+	if (buffer) {
+		/* DATA stage */
+		dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep,
+				usb_pipein(pipe),
+				DWC2_HCCHAR_EPTYPE_CONTROL, max);
+
+		/* TODO: check if len < 64 */
+		control_data_toggle[devnum][ep] = DWC2_HC_PID_DATA1;
+		writel((len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
+		       (1 << DWC2_HCTSIZ_PKTCNT_OFFSET) |
+		       (control_data_toggle[devnum][ep] <<
+				DWC2_HCTSIZ_PID_OFFSET),
+		       &hc_regs->hctsiz);
+
+		writel((uint32_t)buffer, &hc_regs->hcdma);
+
+		/* Set host channel enable after all other setup is complete */
+		clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
+				DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
+				(1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
+				DWC2_HCCHAR_CHEN);
+
+		while (1) {
+			hcint = readl(&hc_regs->hcint);
+			if (!(hcint & DWC2_HCINT_CHHLTD))
+				continue;
+
+			if (hcint & DWC2_HCINT_XFERCOMP) {
+				hctsiz = readl(&hc_regs->hctsiz);
+				done = len;
+
+				sub = hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK;
+				sub >>= DWC2_HCTSIZ_XFERSIZE_OFFSET;
+
+				if (usb_pipein(pipe))
+					done -= sub;
+			}
+
+			if (hcint & DWC2_HCINT_ACK) {
+				tmp = hctsiz & DWC2_HCTSIZ_PID_MASK;
+				tmp >>= DWC2_HCTSIZ_PID_OFFSET;
+				if (tmp == DWC2_HC_PID_DATA0) {
+					control_data_toggle[devnum][ep] =
+						DWC2_HC_PID_DATA0;
+				} else {
+					control_data_toggle[devnum][ep] =
+						DWC2_HC_PID_DATA1;
+				}
+			}
+
+			if (hcint != hcint_comp_hlt_ack) {
+				printf("%s: Error (HCINT=%08x)\n",
+				       __func__, hcint);
+				goto out;
+			}
+
+			if (!--timeout) {
+				printf("%s: Timeout!\n", __func__);
+				goto out;
+			}
+
+			break;
+		}
+	} /* End of DATA stage */
+
+	/* STATUS stage */
+	if ((len == 0) || usb_pipeout(pipe))
+		status_direction = 1;
+	else
+		status_direction = 0;
+
+	dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep,
+			status_direction, DWC2_HCCHAR_EPTYPE_CONTROL, max);
+
+	writel((1 << DWC2_HCTSIZ_PKTCNT_OFFSET) |
+	       (DWC2_HC_PID_DATA1 << DWC2_HCTSIZ_PID_OFFSET),
+	       &hc_regs->hctsiz);
+
+	writel((uint32_t)status_buffer, &hc_regs->hcdma);
+
+	/* Set host channel enable after all other setup is complete. */
+	clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
+			DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
+			(1 << DWC2_HCCHAR_MULTICNT_OFFSET) | DWC2_HCCHAR_CHEN);
+
+	while (1) {
+		hcint = readl(&hc_regs->hcint);
+		if (hcint & DWC2_HCINT_CHHLTD)
+			break;
+	}
+
+	if (hcint != hcint_comp_hlt_ack)
+		printf("%s: Error (HCINT=%08x)\n", __func__, hcint);
+
+out:
+	dev->act_len = done;
+	dev->status = 0;
+
+	return done;
+}
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		   int len, int interval)
+{
+	printf("dev = %p pipe = %#lx buf = %p size = %d int = %d\n",
+	       dev, pipe, buffer, len, interval);
+	return -ENOSYS;
+}
+
+/* U-Boot USB control interface */
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
+{
+	uint32_t snpsid;
+	int i, j;
+
+	root_hub_devnum = 0;
+
+	snpsid = readl(&regs->gsnpsid);
+	printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
+
+	if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx) {
+		printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
+		return -ENODEV;
+	}
+
+	dwc_otg_core_init(regs);
+	dwc_otg_core_host_init(regs);
+
+	clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
+			DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
+			DWC2_HPRT0_PRTOVRCURRCHNG,
+			DWC2_HPRT0_PRTRST);
+	mdelay(50);
+	clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
+		     DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
+		     DWC2_HPRT0_PRTRST);
+
+	for (i = 0; i < MAX_DEVICE; i++) {
+		for (j = 0; j < MAX_ENDPOINT; j++) {
+			control_data_toggle[i][j] = DWC2_HC_PID_DATA1;
+			bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
+		}
+	}
+
+	return 0;
+}
+
+int usb_lowlevel_stop(int index)
+{
+	/* Put everything in reset. */
+	clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
+			DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
+			DWC2_HPRT0_PRTOVRCURRCHNG,
+			DWC2_HPRT0_PRTRST);
+	return 0;
+}
diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h
new file mode 100644
index 00000000000..ba08fd554f1
--- /dev/null
+++ b/drivers/usb/host/dwc2.h
@@ -0,0 +1,782 @@
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __DWC2_H__
+#define __DWC2_H__
+
+struct dwc2_hc_regs {
+	u32			hcchar;		/* 0x00 */
+	u32			hcsplt;
+	u32			hcint;
+	u32			hcintmsk;
+	u32			hctsiz;		/* 0x10 */
+	u32			hcdma;
+	u32			reserved;
+	u32			hcdmab;
+};
+
+struct dwc2_host_regs {
+	u32			hcfg;		/* 0x00 */
+	u32			hfir;
+	u32			hfnum;
+	u32			_pad_0x40c;
+	u32			hptxsts;	/* 0x10 */
+	u32			haint;
+	u32			haintmsk;
+	u32			hflbaddr;
+};
+
+struct dwc2_core_regs {
+	u32			gotgctl;	/* 0x000 */
+	u32			gotgint;
+	u32			gahbcfg;
+	u32			gusbcfg;
+	u32			grstctl;	/* 0x010 */
+	u32			gintsts;
+	u32			gintmsk;
+	u32			grxstsr;
+	u32			grxstsp;	/* 0x020 */
+	u32			grxfsiz;
+	u32			gnptxfsiz;
+	u32			gnptxsts;
+	u32			gi2cctl;	/* 0x030 */
+	u32			gpvndctl;
+	u32			ggpio;
+	u32			guid;
+	u32			gsnpsid;	/* 0x040 */
+	u32			ghwcfg1;
+	u32			ghwcfg2;
+	u32			ghwcfg3;
+	u32			ghwcfg4;	/* 0x050 */
+	u32			glpmcfg;
+	u32			_pad_0x58_0x9c[42];
+	u32			hptxfsiz;	/* 0x100 */
+	u32			dptxfsiz_dieptxf[15];
+	u32			_pad_0x140_0x3fc[176];
+	struct dwc2_host_regs	host_regs;	/* 0x400 */
+	u32			_pad_0x420_0x43c[8];
+	u32			hprt0;		/* 0x440 */
+	u32			_pad_0x444_0x4fc[47];
+	struct dwc2_hc_regs	hc_regs[16];	/* 0x500 */
+	u32			_pad_0x700_0xe00[448];
+	u32			pcgcctl;	/* 0xe00 */
+};
+
+#define DWC2_GOTGCTL_SESREQSCS				(1 << 0)
+#define DWC2_GOTGCTL_SESREQSCS_OFFSET			0
+#define DWC2_GOTGCTL_SESREQ				(1 << 1)
+#define DWC2_GOTGCTL_SESREQ_OFFSET			1
+#define DWC2_GOTGCTL_HSTNEGSCS				(1 << 8)
+#define DWC2_GOTGCTL_HSTNEGSCS_OFFSET			8
+#define DWC2_GOTGCTL_HNPREQ				(1 << 9)
+#define DWC2_GOTGCTL_HNPREQ_OFFSET			9
+#define DWC2_GOTGCTL_HSTSETHNPEN			(1 << 10)
+#define DWC2_GOTGCTL_HSTSETHNPEN_OFFSET			10
+#define DWC2_GOTGCTL_DEVHNPEN				(1 << 11)
+#define DWC2_GOTGCTL_DEVHNPEN_OFFSET			11
+#define DWC2_GOTGCTL_CONIDSTS				(1 << 16)
+#define DWC2_GOTGCTL_CONIDSTS_OFFSET			16
+#define DWC2_GOTGCTL_DBNCTIME				(1 << 17)
+#define DWC2_GOTGCTL_DBNCTIME_OFFSET			17
+#define DWC2_GOTGCTL_ASESVLD				(1 << 18)
+#define DWC2_GOTGCTL_ASESVLD_OFFSET			18
+#define DWC2_GOTGCTL_BSESVLD				(1 << 19)
+#define DWC2_GOTGCTL_BSESVLD_OFFSET			19
+#define DWC2_GOTGCTL_OTGVER				(1 << 20)
+#define DWC2_GOTGCTL_OTGVER_OFFSET			20
+#define DWC2_GOTGINT_SESENDDET				(1 << 2)
+#define DWC2_GOTGINT_SESENDDET_OFFSET			2
+#define DWC2_GOTGINT_SESREQSUCSTSCHNG			(1 << 8)
+#define DWC2_GOTGINT_SESREQSUCSTSCHNG_OFFSET		8
+#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG			(1 << 9)
+#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET		9
+#define DWC2_GOTGINT_RESERVER10_16_MASK			(0x7F << 10)
+#define DWC2_GOTGINT_RESERVER10_16_OFFSET		10
+#define DWC2_GOTGINT_HSTNEGDET				(1 << 17)
+#define DWC2_GOTGINT_HSTNEGDET_OFFSET			17
+#define DWC2_GOTGINT_ADEVTOUTCHNG			(1 << 18)
+#define DWC2_GOTGINT_ADEVTOUTCHNG_OFFSET		18
+#define DWC2_GOTGINT_DEBDONE				(1 << 19)
+#define DWC2_GOTGINT_DEBDONE_OFFSET			19
+#define DWC2_GAHBCFG_GLBLINTRMSK			(1 << 0)
+#define DWC2_GAHBCFG_GLBLINTRMSK_OFFSET			0
+#define DWC2_GAHBCFG_HBURSTLEN_SINGLE			(0 << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_INCR			(1 << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_INCR4			(3 << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_INCR8			(5 << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_INCR16			(7 << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_MASK			(0xF << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_OFFSET			1
+#define DWC2_GAHBCFG_DMAENABLE				(1 << 5)
+#define DWC2_GAHBCFG_DMAENABLE_OFFSET			5
+#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL		(1 << 7)
+#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL_OFFSET	7
+#define DWC2_GAHBCFG_PTXFEMPLVL				(1 << 8)
+#define DWC2_GAHBCFG_PTXFEMPLVL_OFFSET			8
+#define DWC2_GUSBCFG_TOUTCAL_MASK			(0x7 << 0)
+#define DWC2_GUSBCFG_TOUTCAL_OFFSET			0
+#define DWC2_GUSBCFG_PHYIF				(1 << 3)
+#define DWC2_GUSBCFG_PHYIF_OFFSET			3
+#define DWC2_GUSBCFG_ULPI_UTMI_SEL			(1 << 4)
+#define DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET		4
+#define DWC2_GUSBCFG_FSINTF				(1 << 5)
+#define DWC2_GUSBCFG_FSINTF_OFFSET			5
+#define DWC2_GUSBCFG_PHYSEL				(1 << 6)
+#define DWC2_GUSBCFG_PHYSEL_OFFSET			6
+#define DWC2_GUSBCFG_DDRSEL				(1 << 7)
+#define DWC2_GUSBCFG_DDRSEL_OFFSET			7
+#define DWC2_GUSBCFG_SRPCAP				(1 << 8)
+#define DWC2_GUSBCFG_SRPCAP_OFFSET			8
+#define DWC2_GUSBCFG_HNPCAP				(1 << 9)
+#define DWC2_GUSBCFG_HNPCAP_OFFSET			9
+#define DWC2_GUSBCFG_USBTRDTIM_MASK			(0xF << 10)
+#define DWC2_GUSBCFG_USBTRDTIM_OFFSET			10
+#define DWC2_GUSBCFG_NPTXFRWNDEN			(1 << 14)
+#define DWC2_GUSBCFG_NPTXFRWNDEN_OFFSET			14
+#define DWC2_GUSBCFG_PHYLPWRCLKSEL			(1 << 15)
+#define DWC2_GUSBCFG_PHYLPWRCLKSEL_OFFSET		15
+#define DWC2_GUSBCFG_OTGUTMIFSSEL			(1 << 16)
+#define DWC2_GUSBCFG_OTGUTMIFSSEL_OFFSET		16
+#define DWC2_GUSBCFG_ULPI_FSLS				(1 << 17)
+#define DWC2_GUSBCFG_ULPI_FSLS_OFFSET			17
+#define DWC2_GUSBCFG_ULPI_AUTO_RES			(1 << 18)
+#define DWC2_GUSBCFG_ULPI_AUTO_RES_OFFSET		18
+#define DWC2_GUSBCFG_ULPI_CLK_SUS_M			(1 << 19)
+#define DWC2_GUSBCFG_ULPI_CLK_SUS_M_OFFSET		19
+#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV			(1 << 20)
+#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV_OFFSET		20
+#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR		(1 << 21)
+#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR_OFFSET	21
+#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE			(1 << 22)
+#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE_OFFSET		22
+#define DWC2_GUSBCFG_IC_USB_CAP				(1 << 26)
+#define DWC2_GUSBCFG_IC_USB_CAP_OFFSET			26
+#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE		(1 << 27)
+#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE_OFFSET	27
+#define DWC2_GUSBCFG_TX_END_DELAY			(1 << 28)
+#define DWC2_GUSBCFG_TX_END_DELAY_OFFSET		28
+#define DWC2_GUSBCFG_FORCEHOSTMODE			(1 << 29)
+#define DWC2_GUSBCFG_FORCEHOSTMODE_OFFSET		29
+#define DWC2_GUSBCFG_FORCEDEVMODE			(1 << 30)
+#define DWC2_GUSBCFG_FORCEDEVMODE_OFFSET		30
+#define DWC2_GLPMCTL_LPM_CAP_EN				(1 << 0)
+#define DWC2_GLPMCTL_LPM_CAP_EN_OFFSET			0
+#define DWC2_GLPMCTL_APPL_RESP				(1 << 1)
+#define DWC2_GLPMCTL_APPL_RESP_OFFSET			1
+#define DWC2_GLPMCTL_HIRD_MASK				(0xF << 2)
+#define DWC2_GLPMCTL_HIRD_OFFSET			2
+#define DWC2_GLPMCTL_REM_WKUP_EN			(1 << 6)
+#define DWC2_GLPMCTL_REM_WKUP_EN_OFFSET			6
+#define DWC2_GLPMCTL_EN_UTMI_SLEEP			(1 << 7)
+#define DWC2_GLPMCTL_EN_UTMI_SLEEP_OFFSET		7
+#define DWC2_GLPMCTL_HIRD_THRES_MASK			(0x1F << 8)
+#define DWC2_GLPMCTL_HIRD_THRES_OFFSET			8
+#define DWC2_GLPMCTL_LPM_RESP_MASK			(0x3 << 13)
+#define DWC2_GLPMCTL_LPM_RESP_OFFSET			13
+#define DWC2_GLPMCTL_PRT_SLEEP_STS			(1 << 15)
+#define DWC2_GLPMCTL_PRT_SLEEP_STS_OFFSET		15
+#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK		(1 << 16)
+#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK_OFFSET	16
+#define DWC2_GLPMCTL_LPM_CHAN_INDEX_MASK		(0xF << 17)
+#define DWC2_GLPMCTL_LPM_CHAN_INDEX_OFFSET		17
+#define DWC2_GLPMCTL_RETRY_COUNT_MASK			(0x7 << 21)
+#define DWC2_GLPMCTL_RETRY_COUNT_OFFSET			21
+#define DWC2_GLPMCTL_SEND_LPM				(1 << 24)
+#define DWC2_GLPMCTL_SEND_LPM_OFFSET			24
+#define DWC2_GLPMCTL_RETRY_COUNT_STS_MASK		(0x7 << 25)
+#define DWC2_GLPMCTL_RETRY_COUNT_STS_OFFSET		25
+#define DWC2_GLPMCTL_HSIC_CONNECT			(1 << 30)
+#define DWC2_GLPMCTL_HSIC_CONNECT_OFFSET		30
+#define DWC2_GLPMCTL_INV_SEL_HSIC			(1 << 31)
+#define DWC2_GLPMCTL_INV_SEL_HSIC_OFFSET		31
+#define DWC2_GRSTCTL_CSFTRST				(1 << 0)
+#define DWC2_GRSTCTL_CSFTRST_OFFSET			0
+#define DWC2_GRSTCTL_HSFTRST				(1 << 1)
+#define DWC2_GRSTCTL_HSFTRST_OFFSET			1
+#define DWC2_GRSTCTL_HSTFRM				(1 << 2)
+#define DWC2_GRSTCTL_HSTFRM_OFFSET			2
+#define DWC2_GRSTCTL_INTKNQFLSH				(1 << 3)
+#define DWC2_GRSTCTL_INTKNQFLSH_OFFSET			3
+#define DWC2_GRSTCTL_RXFFLSH				(1 << 4)
+#define DWC2_GRSTCTL_RXFFLSH_OFFSET			4
+#define DWC2_GRSTCTL_TXFFLSH				(1 << 5)
+#define DWC2_GRSTCTL_TXFFLSH_OFFSET			5
+#define DWC2_GRSTCTL_TXFNUM_MASK			(0x1F << 6)
+#define DWC2_GRSTCTL_TXFNUM_OFFSET			6
+#define DWC2_GRSTCTL_DMAREQ				(1 << 30)
+#define DWC2_GRSTCTL_DMAREQ_OFFSET			30
+#define DWC2_GRSTCTL_AHBIDLE				(1 << 31)
+#define DWC2_GRSTCTL_AHBIDLE_OFFSET			31
+#define DWC2_GINTMSK_MODEMISMATCH			(1 << 1)
+#define DWC2_GINTMSK_MODEMISMATCH_OFFSET		1
+#define DWC2_GINTMSK_OTGINTR				(1 << 2)
+#define DWC2_GINTMSK_OTGINTR_OFFSET			2
+#define DWC2_GINTMSK_SOFINTR				(1 << 3)
+#define DWC2_GINTMSK_SOFINTR_OFFSET			3
+#define DWC2_GINTMSK_RXSTSQLVL				(1 << 4)
+#define DWC2_GINTMSK_RXSTSQLVL_OFFSET			4
+#define DWC2_GINTMSK_NPTXFEMPTY				(1 << 5)
+#define DWC2_GINTMSK_NPTXFEMPTY_OFFSET			5
+#define DWC2_GINTMSK_GINNAKEFF				(1 << 6)
+#define DWC2_GINTMSK_GINNAKEFF_OFFSET			6
+#define DWC2_GINTMSK_GOUTNAKEFF				(1 << 7)
+#define DWC2_GINTMSK_GOUTNAKEFF_OFFSET			7
+#define DWC2_GINTMSK_I2CINTR				(1 << 9)
+#define DWC2_GINTMSK_I2CINTR_OFFSET			9
+#define DWC2_GINTMSK_ERLYSUSPEND			(1 << 10)
+#define DWC2_GINTMSK_ERLYSUSPEND_OFFSET			10
+#define DWC2_GINTMSK_USBSUSPEND				(1 << 11)
+#define DWC2_GINTMSK_USBSUSPEND_OFFSET			11
+#define DWC2_GINTMSK_USBRESET				(1 << 12)
+#define DWC2_GINTMSK_USBRESET_OFFSET			12
+#define DWC2_GINTMSK_ENUMDONE				(1 << 13)
+#define DWC2_GINTMSK_ENUMDONE_OFFSET			13
+#define DWC2_GINTMSK_ISOOUTDROP				(1 << 14)
+#define DWC2_GINTMSK_ISOOUTDROP_OFFSET			14
+#define DWC2_GINTMSK_EOPFRAME				(1 << 15)
+#define DWC2_GINTMSK_EOPFRAME_OFFSET			15
+#define DWC2_GINTMSK_EPMISMATCH				(1 << 17)
+#define DWC2_GINTMSK_EPMISMATCH_OFFSET			17
+#define DWC2_GINTMSK_INEPINTR				(1 << 18)
+#define DWC2_GINTMSK_INEPINTR_OFFSET			18
+#define DWC2_GINTMSK_OUTEPINTR				(1 << 19)
+#define DWC2_GINTMSK_OUTEPINTR_OFFSET			19
+#define DWC2_GINTMSK_INCOMPLISOIN			(1 << 20)
+#define DWC2_GINTMSK_INCOMPLISOIN_OFFSET		20
+#define DWC2_GINTMSK_INCOMPLISOOUT			(1 << 21)
+#define DWC2_GINTMSK_INCOMPLISOOUT_OFFSET		21
+#define DWC2_GINTMSK_PORTINTR				(1 << 24)
+#define DWC2_GINTMSK_PORTINTR_OFFSET			24
+#define DWC2_GINTMSK_HCINTR				(1 << 25)
+#define DWC2_GINTMSK_HCINTR_OFFSET			25
+#define DWC2_GINTMSK_PTXFEMPTY				(1 << 26)
+#define DWC2_GINTMSK_PTXFEMPTY_OFFSET			26
+#define DWC2_GINTMSK_LPMTRANRCVD			(1 << 27)
+#define DWC2_GINTMSK_LPMTRANRCVD_OFFSET			27
+#define DWC2_GINTMSK_CONIDSTSCHNG			(1 << 28)
+#define DWC2_GINTMSK_CONIDSTSCHNG_OFFSET		28
+#define DWC2_GINTMSK_DISCONNECT				(1 << 29)
+#define DWC2_GINTMSK_DISCONNECT_OFFSET			29
+#define DWC2_GINTMSK_SESSREQINTR			(1 << 30)
+#define DWC2_GINTMSK_SESSREQINTR_OFFSET			30
+#define DWC2_GINTMSK_WKUPINTR				(1 << 31)
+#define DWC2_GINTMSK_WKUPINTR_OFFSET			31
+#define DWC2_GINTSTS_CURMODE_DEVICE			(0 << 0)
+#define DWC2_GINTSTS_CURMODE_HOST			(1 << 0)
+#define DWC2_GINTSTS_CURMODE				(1 << 0)
+#define DWC2_GINTSTS_CURMODE_OFFSET			0
+#define DWC2_GINTSTS_MODEMISMATCH			(1 << 1)
+#define DWC2_GINTSTS_MODEMISMATCH_OFFSET		1
+#define DWC2_GINTSTS_OTGINTR				(1 << 2)
+#define DWC2_GINTSTS_OTGINTR_OFFSET			2
+#define DWC2_GINTSTS_SOFINTR				(1 << 3)
+#define DWC2_GINTSTS_SOFINTR_OFFSET			3
+#define DWC2_GINTSTS_RXSTSQLVL				(1 << 4)
+#define DWC2_GINTSTS_RXSTSQLVL_OFFSET			4
+#define DWC2_GINTSTS_NPTXFEMPTY				(1 << 5)
+#define DWC2_GINTSTS_NPTXFEMPTY_OFFSET			5
+#define DWC2_GINTSTS_GINNAKEFF				(1 << 6)
+#define DWC2_GINTSTS_GINNAKEFF_OFFSET			6
+#define DWC2_GINTSTS_GOUTNAKEFF				(1 << 7)
+#define DWC2_GINTSTS_GOUTNAKEFF_OFFSET			7
+#define DWC2_GINTSTS_I2CINTR				(1 << 9)
+#define DWC2_GINTSTS_I2CINTR_OFFSET			9
+#define DWC2_GINTSTS_ERLYSUSPEND			(1 << 10)
+#define DWC2_GINTSTS_ERLYSUSPEND_OFFSET			10
+#define DWC2_GINTSTS_USBSUSPEND				(1 << 11)
+#define DWC2_GINTSTS_USBSUSPEND_OFFSET			11
+#define DWC2_GINTSTS_USBRESET				(1 << 12)
+#define DWC2_GINTSTS_USBRESET_OFFSET			12
+#define DWC2_GINTSTS_ENUMDONE				(1 << 13)
+#define DWC2_GINTSTS_ENUMDONE_OFFSET			13
+#define DWC2_GINTSTS_ISOOUTDROP				(1 << 14)
+#define DWC2_GINTSTS_ISOOUTDROP_OFFSET			14
+#define DWC2_GINTSTS_EOPFRAME				(1 << 15)
+#define DWC2_GINTSTS_EOPFRAME_OFFSET			15
+#define DWC2_GINTSTS_INTOKENRX				(1 << 16)
+#define DWC2_GINTSTS_INTOKENRX_OFFSET			16
+#define DWC2_GINTSTS_EPMISMATCH				(1 << 17)
+#define DWC2_GINTSTS_EPMISMATCH_OFFSET			17
+#define DWC2_GINTSTS_INEPINT				(1 << 18)
+#define DWC2_GINTSTS_INEPINT_OFFSET			18
+#define DWC2_GINTSTS_OUTEPINTR				(1 << 19)
+#define DWC2_GINTSTS_OUTEPINTR_OFFSET			19
+#define DWC2_GINTSTS_INCOMPLISOIN			(1 << 20)
+#define DWC2_GINTSTS_INCOMPLISOIN_OFFSET		20
+#define DWC2_GINTSTS_INCOMPLISOOUT			(1 << 21)
+#define DWC2_GINTSTS_INCOMPLISOOUT_OFFSET		21
+#define DWC2_GINTSTS_PORTINTR				(1 << 24)
+#define DWC2_GINTSTS_PORTINTR_OFFSET			24
+#define DWC2_GINTSTS_HCINTR				(1 << 25)
+#define DWC2_GINTSTS_HCINTR_OFFSET			25
+#define DWC2_GINTSTS_PTXFEMPTY				(1 << 26)
+#define DWC2_GINTSTS_PTXFEMPTY_OFFSET			26
+#define DWC2_GINTSTS_LPMTRANRCVD			(1 << 27)
+#define DWC2_GINTSTS_LPMTRANRCVD_OFFSET			27
+#define DWC2_GINTSTS_CONIDSTSCHNG			(1 << 28)
+#define DWC2_GINTSTS_CONIDSTSCHNG_OFFSET		28
+#define DWC2_GINTSTS_DISCONNECT				(1 << 29)
+#define DWC2_GINTSTS_DISCONNECT_OFFSET			29
+#define DWC2_GINTSTS_SESSREQINTR			(1 << 30)
+#define DWC2_GINTSTS_SESSREQINTR_OFFSET			30
+#define DWC2_GINTSTS_WKUPINTR				(1 << 31)
+#define DWC2_GINTSTS_WKUPINTR_OFFSET			31
+#define DWC2_GRXSTS_EPNUM_MASK				(0xF << 0)
+#define DWC2_GRXSTS_EPNUM_OFFSET			0
+#define DWC2_GRXSTS_BCNT_MASK				(0x7FF << 4)
+#define DWC2_GRXSTS_BCNT_OFFSET				4
+#define DWC2_GRXSTS_DPID_MASK				(0x3 << 15)
+#define DWC2_GRXSTS_DPID_OFFSET				15
+#define DWC2_GRXSTS_PKTSTS_MASK				(0xF << 17)
+#define DWC2_GRXSTS_PKTSTS_OFFSET			17
+#define DWC2_GRXSTS_FN_MASK				(0xF << 21)
+#define DWC2_GRXSTS_FN_OFFSET				21
+#define DWC2_FIFOSIZE_STARTADDR_MASK			(0xFFFF << 0)
+#define DWC2_FIFOSIZE_STARTADDR_OFFSET			0
+#define DWC2_FIFOSIZE_DEPTH_MASK			(0xFFFF << 16)
+#define DWC2_FIFOSIZE_DEPTH_OFFSET			16
+#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_MASK		(0xFFFF << 0)
+#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_OFFSET		0
+#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_MASK		(0xFF << 16)
+#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_OFFSET		16
+#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE		(1 << 24)
+#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE_OFFSET		24
+#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_MASK		(0x3 << 25)
+#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_OFFSET		25
+#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_MASK		(0xF << 27)
+#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_OFFSET		27
+#define DWC2_DTXFSTS_TXFSPCAVAIL_MASK			(0xFFFF << 0)
+#define DWC2_DTXFSTS_TXFSPCAVAIL_OFFSET			0
+#define DWC2_GI2CCTL_RWDATA_MASK			(0xFF << 0)
+#define DWC2_GI2CCTL_RWDATA_OFFSET			0
+#define DWC2_GI2CCTL_REGADDR_MASK			(0xFF << 8)
+#define DWC2_GI2CCTL_REGADDR_OFFSET			8
+#define DWC2_GI2CCTL_ADDR_MASK				(0x7F << 16)
+#define DWC2_GI2CCTL_ADDR_OFFSET			16
+#define DWC2_GI2CCTL_I2CEN				(1 << 23)
+#define DWC2_GI2CCTL_I2CEN_OFFSET			23
+#define DWC2_GI2CCTL_ACK				(1 << 24)
+#define DWC2_GI2CCTL_ACK_OFFSET				24
+#define DWC2_GI2CCTL_I2CSUSPCTL				(1 << 25)
+#define DWC2_GI2CCTL_I2CSUSPCTL_OFFSET			25
+#define DWC2_GI2CCTL_I2CDEVADDR_MASK			(0x3 << 26)
+#define DWC2_GI2CCTL_I2CDEVADDR_OFFSET			26
+#define DWC2_GI2CCTL_RW					(1 << 30)
+#define DWC2_GI2CCTL_RW_OFFSET				30
+#define DWC2_GI2CCTL_BSYDNE				(1 << 31)
+#define DWC2_GI2CCTL_BSYDNE_OFFSET			31
+#define DWC2_HWCFG1_EP_DIR0_MASK			(0x3 << 0)
+#define DWC2_HWCFG1_EP_DIR0_OFFSET			0
+#define DWC2_HWCFG1_EP_DIR1_MASK			(0x3 << 2)
+#define DWC2_HWCFG1_EP_DIR1_OFFSET			2
+#define DWC2_HWCFG1_EP_DIR2_MASK			(0x3 << 4)
+#define DWC2_HWCFG1_EP_DIR2_OFFSET			4
+#define DWC2_HWCFG1_EP_DIR3_MASK			(0x3 << 6)
+#define DWC2_HWCFG1_EP_DIR3_OFFSET			6
+#define DWC2_HWCFG1_EP_DIR4_MASK			(0x3 << 8)
+#define DWC2_HWCFG1_EP_DIR4_OFFSET			8
+#define DWC2_HWCFG1_EP_DIR5_MASK			(0x3 << 10)
+#define DWC2_HWCFG1_EP_DIR5_OFFSET			10
+#define DWC2_HWCFG1_EP_DIR6_MASK			(0x3 << 12)
+#define DWC2_HWCFG1_EP_DIR6_OFFSET			12
+#define DWC2_HWCFG1_EP_DIR7_MASK			(0x3 << 14)
+#define DWC2_HWCFG1_EP_DIR7_OFFSET			14
+#define DWC2_HWCFG1_EP_DIR8_MASK			(0x3 << 16)
+#define DWC2_HWCFG1_EP_DIR8_OFFSET			16
+#define DWC2_HWCFG1_EP_DIR9_MASK			(0x3 << 18)
+#define DWC2_HWCFG1_EP_DIR9_OFFSET			18
+#define DWC2_HWCFG1_EP_DIR10_MASK			(0x3 << 20)
+#define DWC2_HWCFG1_EP_DIR10_OFFSET			20
+#define DWC2_HWCFG1_EP_DIR11_MASK			(0x3 << 22)
+#define DWC2_HWCFG1_EP_DIR11_OFFSET			22
+#define DWC2_HWCFG1_EP_DIR12_MASK			(0x3 << 24)
+#define DWC2_HWCFG1_EP_DIR12_OFFSET			24
+#define DWC2_HWCFG1_EP_DIR13_MASK			(0x3 << 26)
+#define DWC2_HWCFG1_EP_DIR13_OFFSET			26
+#define DWC2_HWCFG1_EP_DIR14_MASK			(0x3 << 28)
+#define DWC2_HWCFG1_EP_DIR14_OFFSET			28
+#define DWC2_HWCFG1_EP_DIR15_MASK			(0x3 << 30)
+#define DWC2_HWCFG1_EP_DIR15_OFFSET			30
+#define DWC2_HWCFG2_OP_MODE_MASK			(0x7 << 0)
+#define DWC2_HWCFG2_OP_MODE_OFFSET			0
+#define DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY		(0x0 << 3)
+#define DWC2_HWCFG2_ARCHITECTURE_EXT_DMA		(0x1 << 3)
+#define DWC2_HWCFG2_ARCHITECTURE_INT_DMA		(0x2 << 3)
+#define DWC2_HWCFG2_ARCHITECTURE_MASK			(0x3 << 3)
+#define DWC2_HWCFG2_ARCHITECTURE_OFFSET			3
+#define DWC2_HWCFG2_POINT2POINT				(1 << 5)
+#define DWC2_HWCFG2_POINT2POINT_OFFSET			5
+#define DWC2_HWCFG2_HS_PHY_TYPE_MASK			(0x3 << 6)
+#define DWC2_HWCFG2_HS_PHY_TYPE_OFFSET			6
+#define DWC2_HWCFG2_FS_PHY_TYPE_MASK			(0x3 << 8)
+#define DWC2_HWCFG2_FS_PHY_TYPE_OFFSET			8
+#define DWC2_HWCFG2_NUM_DEV_EP_MASK			(0xF << 10)
+#define DWC2_HWCFG2_NUM_DEV_EP_OFFSET			10
+#define DWC2_HWCFG2_NUM_HOST_CHAN_MASK			(0xF << 14)
+#define DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET		14
+#define DWC2_HWCFG2_PERIO_EP_SUPPORTED			(1 << 18)
+#define DWC2_HWCFG2_PERIO_EP_SUPPORTED_OFFSET		18
+#define DWC2_HWCFG2_DYNAMIC_FIFO			(1 << 19)
+#define DWC2_HWCFG2_DYNAMIC_FIFO_OFFSET			19
+#define DWC2_HWCFG2_MULTI_PROC_INT			(1 << 20)
+#define DWC2_HWCFG2_MULTI_PROC_INT_OFFSET		20
+#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_MASK		(0x3 << 22)
+#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_OFFSET		22
+#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK		(0x3 << 24)
+#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_OFFSET	24
+#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_MASK		(0x1F << 26)
+#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_OFFSET		26
+#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_MASK		(0xF << 0)
+#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_OFFSET		0
+#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK		(0x7 << 4)
+#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_OFFSET	4
+#define DWC2_HWCFG3_OTG_FUNC				(1 << 7)
+#define DWC2_HWCFG3_OTG_FUNC_OFFSET			7
+#define DWC2_HWCFG3_I2C					(1 << 8)
+#define DWC2_HWCFG3_I2C_OFFSET				8
+#define DWC2_HWCFG3_VENDOR_CTRL_IF			(1 << 9)
+#define DWC2_HWCFG3_VENDOR_CTRL_IF_OFFSET		9
+#define DWC2_HWCFG3_OPTIONAL_FEATURES			(1 << 10)
+#define DWC2_HWCFG3_OPTIONAL_FEATURES_OFFSET		10
+#define DWC2_HWCFG3_SYNCH_RESET_TYPE			(1 << 11)
+#define DWC2_HWCFG3_SYNCH_RESET_TYPE_OFFSET		11
+#define DWC2_HWCFG3_OTG_ENABLE_IC_USB			(1 << 12)
+#define DWC2_HWCFG3_OTG_ENABLE_IC_USB_OFFSET		12
+#define DWC2_HWCFG3_OTG_ENABLE_HSIC			(1 << 13)
+#define DWC2_HWCFG3_OTG_ENABLE_HSIC_OFFSET		13
+#define DWC2_HWCFG3_OTG_LPM_EN				(1 << 15)
+#define DWC2_HWCFG3_OTG_LPM_EN_OFFSET			15
+#define DWC2_HWCFG3_DFIFO_DEPTH_MASK			(0xFFFF << 16)
+#define DWC2_HWCFG3_DFIFO_DEPTH_OFFSET			16
+#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_MASK		(0xF << 0)
+#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_OFFSET		0
+#define DWC2_HWCFG4_POWER_OPTIMIZ			(1 << 4)
+#define DWC2_HWCFG4_POWER_OPTIMIZ_OFFSET		4
+#define DWC2_HWCFG4_MIN_AHB_FREQ_MASK			(0x1FF << 5)
+#define DWC2_HWCFG4_MIN_AHB_FREQ_OFFSET			5
+#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_MASK		(0x3 << 14)
+#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_OFFSET		14
+#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_MASK		(0xF << 16)
+#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_OFFSET		16
+#define DWC2_HWCFG4_IDDIG_FILT_EN			(1 << 20)
+#define DWC2_HWCFG4_IDDIG_FILT_EN_OFFSET		20
+#define DWC2_HWCFG4_VBUS_VALID_FILT_EN			(1 << 21)
+#define DWC2_HWCFG4_VBUS_VALID_FILT_EN_OFFSET		21
+#define DWC2_HWCFG4_A_VALID_FILT_EN			(1 << 22)
+#define DWC2_HWCFG4_A_VALID_FILT_EN_OFFSET		22
+#define DWC2_HWCFG4_B_VALID_FILT_EN			(1 << 23)
+#define DWC2_HWCFG4_B_VALID_FILT_EN_OFFSET		23
+#define DWC2_HWCFG4_SESSION_END_FILT_EN			(1 << 24)
+#define DWC2_HWCFG4_SESSION_END_FILT_EN_OFFSET		24
+#define DWC2_HWCFG4_DED_FIFO_EN				(1 << 25)
+#define DWC2_HWCFG4_DED_FIFO_EN_OFFSET			25
+#define DWC2_HWCFG4_NUM_IN_EPS_MASK			(0xF << 26)
+#define DWC2_HWCFG4_NUM_IN_EPS_OFFSET			26
+#define DWC2_HWCFG4_DESC_DMA				(1 << 30)
+#define DWC2_HWCFG4_DESC_DMA_OFFSET			30
+#define DWC2_HWCFG4_DESC_DMA_DYN			(1 << 31)
+#define DWC2_HWCFG4_DESC_DMA_DYN_OFFSET			31
+#define DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ			0
+#define DWC2_HCFG_FSLSPCLKSEL_48_MHZ			1
+#define DWC2_HCFG_FSLSPCLKSEL_6_MHZ			2
+#define DWC2_HCFG_FSLSPCLKSEL_MASK			(0x3 << 0)
+#define DWC2_HCFG_FSLSPCLKSEL_OFFSET			0
+#define DWC2_HCFG_FSLSSUPP				(1 << 2)
+#define DWC2_HCFG_FSLSSUPP_OFFSET			2
+#define DWC2_HCFG_DESCDMA				(1 << 23)
+#define DWC2_HCFG_DESCDMA_OFFSET			23
+#define DWC2_HCFG_FRLISTEN_MASK				(0x3 << 24)
+#define DWC2_HCFG_FRLISTEN_OFFSET			24
+#define DWC2_HCFG_PERSCHEDENA				(1 << 26)
+#define DWC2_HCFG_PERSCHEDENA_OFFSET			26
+#define DWC2_HCFG_PERSCHEDSTAT				(1 << 27)
+#define DWC2_HCFG_PERSCHEDSTAT_OFFSET			27
+#define DWC2_HFIR_FRINT_MASK				(0xFFFF << 0)
+#define DWC2_HFIR_FRINT_OFFSET				0
+#define DWC2_HFNUM_FRNUM_MASK				(0xFFFF << 0)
+#define DWC2_HFNUM_FRNUM_OFFSET				0
+#define DWC2_HFNUM_FRREM_MASK				(0xFFFF << 16)
+#define DWC2_HFNUM_FRREM_OFFSET				16
+#define DWC2_HPTXSTS_PTXFSPCAVAIL_MASK			(0xFFFF << 0)
+#define DWC2_HPTXSTS_PTXFSPCAVAIL_OFFSET		0
+#define DWC2_HPTXSTS_PTXQSPCAVAIL_MASK			(0xFF << 16)
+#define DWC2_HPTXSTS_PTXQSPCAVAIL_OFFSET		16
+#define DWC2_HPTXSTS_PTXQTOP_TERMINATE			(1 << 24)
+#define DWC2_HPTXSTS_PTXQTOP_TERMINATE_OFFSET		24
+#define DWC2_HPTXSTS_PTXQTOP_TOKEN_MASK			(0x3 << 25)
+#define DWC2_HPTXSTS_PTXQTOP_TOKEN_OFFSET		25
+#define DWC2_HPTXSTS_PTXQTOP_CHNUM_MASK			(0xF << 27)
+#define DWC2_HPTXSTS_PTXQTOP_CHNUM_OFFSET		27
+#define DWC2_HPTXSTS_PTXQTOP_ODD			(1 << 31)
+#define DWC2_HPTXSTS_PTXQTOP_ODD_OFFSET			31
+#define DWC2_HPRT0_PRTCONNSTS				(1 << 0)
+#define DWC2_HPRT0_PRTCONNSTS_OFFSET			0
+#define DWC2_HPRT0_PRTCONNDET				(1 << 1)
+#define DWC2_HPRT0_PRTCONNDET_OFFSET			1
+#define DWC2_HPRT0_PRTENA				(1 << 2)
+#define DWC2_HPRT0_PRTENA_OFFSET			2
+#define DWC2_HPRT0_PRTENCHNG				(1 << 3)
+#define DWC2_HPRT0_PRTENCHNG_OFFSET			3
+#define DWC2_HPRT0_PRTOVRCURRACT			(1 << 4)
+#define DWC2_HPRT0_PRTOVRCURRACT_OFFSET			4
+#define DWC2_HPRT0_PRTOVRCURRCHNG			(1 << 5)
+#define DWC2_HPRT0_PRTOVRCURRCHNG_OFFSET		5
+#define DWC2_HPRT0_PRTRES				(1 << 6)
+#define DWC2_HPRT0_PRTRES_OFFSET			6
+#define DWC2_HPRT0_PRTSUSP				(1 << 7)
+#define DWC2_HPRT0_PRTSUSP_OFFSET			7
+#define DWC2_HPRT0_PRTRST				(1 << 8)
+#define DWC2_HPRT0_PRTRST_OFFSET			8
+#define DWC2_HPRT0_PRTLNSTS_MASK			(0x3 << 10)
+#define DWC2_HPRT0_PRTLNSTS_OFFSET			10
+#define DWC2_HPRT0_PRTPWR				(1 << 12)
+#define DWC2_HPRT0_PRTPWR_OFFSET			12
+#define DWC2_HPRT0_PRTTSTCTL_MASK			(0xF << 13)
+#define DWC2_HPRT0_PRTTSTCTL_OFFSET			13
+#define DWC2_HPRT0_PRTSPD_MASK				(0x3 << 17)
+#define DWC2_HPRT0_PRTSPD_OFFSET			17
+#define DWC2_HAINT_CH0					(1 << 0)
+#define DWC2_HAINT_CH0_OFFSET				0
+#define DWC2_HAINT_CH1					(1 << 1)
+#define DWC2_HAINT_CH1_OFFSET				1
+#define DWC2_HAINT_CH2					(1 << 2)
+#define DWC2_HAINT_CH2_OFFSET				2
+#define DWC2_HAINT_CH3					(1 << 3)
+#define DWC2_HAINT_CH3_OFFSET				3
+#define DWC2_HAINT_CH4					(1 << 4)
+#define DWC2_HAINT_CH4_OFFSET				4
+#define DWC2_HAINT_CH5					(1 << 5)
+#define DWC2_HAINT_CH5_OFFSET				5
+#define DWC2_HAINT_CH6					(1 << 6)
+#define DWC2_HAINT_CH6_OFFSET				6
+#define DWC2_HAINT_CH7					(1 << 7)
+#define DWC2_HAINT_CH7_OFFSET				7
+#define DWC2_HAINT_CH8					(1 << 8)
+#define DWC2_HAINT_CH8_OFFSET				8
+#define DWC2_HAINT_CH9					(1 << 9)
+#define DWC2_HAINT_CH9_OFFSET				9
+#define DWC2_HAINT_CH10					(1 << 10)
+#define DWC2_HAINT_CH10_OFFSET				10
+#define DWC2_HAINT_CH11					(1 << 11)
+#define DWC2_HAINT_CH11_OFFSET				11
+#define DWC2_HAINT_CH12					(1 << 12)
+#define DWC2_HAINT_CH12_OFFSET				12
+#define DWC2_HAINT_CH13					(1 << 13)
+#define DWC2_HAINT_CH13_OFFSET				13
+#define DWC2_HAINT_CH14					(1 << 14)
+#define DWC2_HAINT_CH14_OFFSET				14
+#define DWC2_HAINT_CH15					(1 << 15)
+#define DWC2_HAINT_CH15_OFFSET				15
+#define DWC2_HAINT_CHINT_MASK				0xffff
+#define DWC2_HAINT_CHINT_OFFSET				0
+#define DWC2_HAINTMSK_CH0				(1 << 0)
+#define DWC2_HAINTMSK_CH0_OFFSET			0
+#define DWC2_HAINTMSK_CH1				(1 << 1)
+#define DWC2_HAINTMSK_CH1_OFFSET			1
+#define DWC2_HAINTMSK_CH2				(1 << 2)
+#define DWC2_HAINTMSK_CH2_OFFSET			2
+#define DWC2_HAINTMSK_CH3				(1 << 3)
+#define DWC2_HAINTMSK_CH3_OFFSET			3
+#define DWC2_HAINTMSK_CH4				(1 << 4)
+#define DWC2_HAINTMSK_CH4_OFFSET			4
+#define DWC2_HAINTMSK_CH5				(1 << 5)
+#define DWC2_HAINTMSK_CH5_OFFSET			5
+#define DWC2_HAINTMSK_CH6				(1 << 6)
+#define DWC2_HAINTMSK_CH6_OFFSET			6
+#define DWC2_HAINTMSK_CH7				(1 << 7)
+#define DWC2_HAINTMSK_CH7_OFFSET			7
+#define DWC2_HAINTMSK_CH8				(1 << 8)
+#define DWC2_HAINTMSK_CH8_OFFSET			8
+#define DWC2_HAINTMSK_CH9				(1 << 9)
+#define DWC2_HAINTMSK_CH9_OFFSET			9
+#define DWC2_HAINTMSK_CH10				(1 << 10)
+#define DWC2_HAINTMSK_CH10_OFFSET			10
+#define DWC2_HAINTMSK_CH11				(1 << 11)
+#define DWC2_HAINTMSK_CH11_OFFSET			11
+#define DWC2_HAINTMSK_CH12				(1 << 12)
+#define DWC2_HAINTMSK_CH12_OFFSET			12
+#define DWC2_HAINTMSK_CH13				(1 << 13)
+#define DWC2_HAINTMSK_CH13_OFFSET			13
+#define DWC2_HAINTMSK_CH14				(1 << 14)
+#define DWC2_HAINTMSK_CH14_OFFSET			14
+#define DWC2_HAINTMSK_CH15				(1 << 15)
+#define DWC2_HAINTMSK_CH15_OFFSET			15
+#define DWC2_HAINTMSK_CHINT_MASK			0xffff
+#define DWC2_HAINTMSK_CHINT_OFFSET			0
+#define DWC2_HCCHAR_MPS_MASK				(0x7FF << 0)
+#define DWC2_HCCHAR_MPS_OFFSET				0
+#define DWC2_HCCHAR_EPNUM_MASK				(0xF << 11)
+#define DWC2_HCCHAR_EPNUM_OFFSET			11
+#define DWC2_HCCHAR_EPDIR				(1 << 15)
+#define DWC2_HCCHAR_EPDIR_OFFSET			15
+#define DWC2_HCCHAR_LSPDDEV				(1 << 17)
+#define DWC2_HCCHAR_LSPDDEV_OFFSET			17
+#define DWC2_HCCHAR_EPTYPE_CONTROL			0
+#define DWC2_HCCHAR_EPTYPE_ISOC				1
+#define DWC2_HCCHAR_EPTYPE_BULK				2
+#define DWC2_HCCHAR_EPTYPE_INTR				3
+#define DWC2_HCCHAR_EPTYPE_MASK				(0x3 << 18)
+#define DWC2_HCCHAR_EPTYPE_OFFSET			18
+#define DWC2_HCCHAR_MULTICNT_MASK			(0x3 << 20)
+#define DWC2_HCCHAR_MULTICNT_OFFSET			20
+#define DWC2_HCCHAR_DEVADDR_MASK			(0x7F << 22)
+#define DWC2_HCCHAR_DEVADDR_OFFSET			22
+#define DWC2_HCCHAR_ODDFRM				(1 << 29)
+#define DWC2_HCCHAR_ODDFRM_OFFSET			29
+#define DWC2_HCCHAR_CHDIS				(1 << 30)
+#define DWC2_HCCHAR_CHDIS_OFFSET			30
+#define DWC2_HCCHAR_CHEN				(1 << 31)
+#define DWC2_HCCHAR_CHEN_OFFSET				31
+#define DWC2_HCSPLT_PRTADDR_MASK			(0x7F << 0)
+#define DWC2_HCSPLT_PRTADDR_OFFSET			0
+#define DWC2_HCSPLT_HUBADDR_MASK			(0x7F << 7)
+#define DWC2_HCSPLT_HUBADDR_OFFSET			7
+#define DWC2_HCSPLT_XACTPOS_MASK			(0x3 << 14)
+#define DWC2_HCSPLT_XACTPOS_OFFSET			14
+#define DWC2_HCSPLT_COMPSPLT				(1 << 16)
+#define DWC2_HCSPLT_COMPSPLT_OFFSET			16
+#define DWC2_HCSPLT_SPLTENA				(1 << 31)
+#define DWC2_HCSPLT_SPLTENA_OFFSET			31
+#define DWC2_HCINT_XFERCOMP				(1 << 0)
+#define DWC2_HCINT_XFERCOMP_OFFSET			0
+#define DWC2_HCINT_CHHLTD				(1 << 1)
+#define DWC2_HCINT_CHHLTD_OFFSET			1
+#define DWC2_HCINT_AHBERR				(1 << 2)
+#define DWC2_HCINT_AHBERR_OFFSET			2
+#define DWC2_HCINT_STALL				(1 << 3)
+#define DWC2_HCINT_STALL_OFFSET				3
+#define DWC2_HCINT_NAK					(1 << 4)
+#define DWC2_HCINT_NAK_OFFSET				4
+#define DWC2_HCINT_ACK					(1 << 5)
+#define DWC2_HCINT_ACK_OFFSET				5
+#define DWC2_HCINT_NYET					(1 << 6)
+#define DWC2_HCINT_NYET_OFFSET				6
+#define DWC2_HCINT_XACTERR				(1 << 7)
+#define DWC2_HCINT_XACTERR_OFFSET			7
+#define DWC2_HCINT_BBLERR				(1 << 8)
+#define DWC2_HCINT_BBLERR_OFFSET			8
+#define DWC2_HCINT_FRMOVRUN				(1 << 9)
+#define DWC2_HCINT_FRMOVRUN_OFFSET			9
+#define DWC2_HCINT_DATATGLERR				(1 << 10)
+#define DWC2_HCINT_DATATGLERR_OFFSET			10
+#define DWC2_HCINT_BNA					(1 << 11)
+#define DWC2_HCINT_BNA_OFFSET				11
+#define DWC2_HCINT_XCS_XACT				(1 << 12)
+#define DWC2_HCINT_XCS_XACT_OFFSET			12
+#define DWC2_HCINT_FRM_LIST_ROLL			(1 << 13)
+#define DWC2_HCINT_FRM_LIST_ROLL_OFFSET			13
+#define DWC2_HCINTMSK_XFERCOMPL				(1 << 0)
+#define DWC2_HCINTMSK_XFERCOMPL_OFFSET			0
+#define DWC2_HCINTMSK_CHHLTD				(1 << 1)
+#define DWC2_HCINTMSK_CHHLTD_OFFSET			1
+#define DWC2_HCINTMSK_AHBERR				(1 << 2)
+#define DWC2_HCINTMSK_AHBERR_OFFSET			2
+#define DWC2_HCINTMSK_STALL				(1 << 3)
+#define DWC2_HCINTMSK_STALL_OFFSET			3
+#define DWC2_HCINTMSK_NAK				(1 << 4)
+#define DWC2_HCINTMSK_NAK_OFFSET			4
+#define DWC2_HCINTMSK_ACK				(1 << 5)
+#define DWC2_HCINTMSK_ACK_OFFSET			5
+#define DWC2_HCINTMSK_NYET				(1 << 6)
+#define DWC2_HCINTMSK_NYET_OFFSET			6
+#define DWC2_HCINTMSK_XACTERR				(1 << 7)
+#define DWC2_HCINTMSK_XACTERR_OFFSET			7
+#define DWC2_HCINTMSK_BBLERR				(1 << 8)
+#define DWC2_HCINTMSK_BBLERR_OFFSET			8
+#define DWC2_HCINTMSK_FRMOVRUN				(1 << 9)
+#define DWC2_HCINTMSK_FRMOVRUN_OFFSET			9
+#define DWC2_HCINTMSK_DATATGLERR			(1 << 10)
+#define DWC2_HCINTMSK_DATATGLERR_OFFSET			10
+#define DWC2_HCINTMSK_BNA				(1 << 11)
+#define DWC2_HCINTMSK_BNA_OFFSET			11
+#define DWC2_HCINTMSK_XCS_XACT				(1 << 12)
+#define DWC2_HCINTMSK_XCS_XACT_OFFSET			12
+#define DWC2_HCINTMSK_FRM_LIST_ROLL			(1 << 13)
+#define DWC2_HCINTMSK_FRM_LIST_ROLL_OFFSET		13
+#define DWC2_HCTSIZ_XFERSIZE_MASK			0x7ffff
+#define DWC2_HCTSIZ_XFERSIZE_OFFSET			0
+#define DWC2_HCTSIZ_SCHINFO_MASK			0xff
+#define DWC2_HCTSIZ_SCHINFO_OFFSET			0
+#define DWC2_HCTSIZ_NTD_MASK				(0xff << 8)
+#define DWC2_HCTSIZ_NTD_OFFSET				8
+#define DWC2_HCTSIZ_PKTCNT_MASK				(0x3ff << 19)
+#define DWC2_HCTSIZ_PKTCNT_OFFSET			19
+#define DWC2_HCTSIZ_PID_MASK				(0x3 << 29)
+#define DWC2_HCTSIZ_PID_OFFSET				29
+#define DWC2_HCTSIZ_DOPNG				(1 << 31)
+#define DWC2_HCTSIZ_DOPNG_OFFSET			31
+#define DWC2_HCDMA_CTD_MASK				(0xFF << 3)
+#define DWC2_HCDMA_CTD_OFFSET				3
+#define DWC2_HCDMA_DMA_ADDR_MASK			(0x1FFFFF << 11)
+#define DWC2_HCDMA_DMA_ADDR_OFFSET			11
+#define DWC2_PCGCCTL_STOPPCLK				(1 << 0)
+#define DWC2_PCGCCTL_STOPPCLK_OFFSET			0
+#define DWC2_PCGCCTL_GATEHCLK				(1 << 1)
+#define DWC2_PCGCCTL_GATEHCLK_OFFSET			1
+#define DWC2_PCGCCTL_PWRCLMP				(1 << 2)
+#define DWC2_PCGCCTL_PWRCLMP_OFFSET			2
+#define DWC2_PCGCCTL_RSTPDWNMODULE			(1 << 3)
+#define DWC2_PCGCCTL_RSTPDWNMODULE_OFFSET		3
+#define DWC2_PCGCCTL_PHYSUSPENDED			(1 << 4)
+#define DWC2_PCGCCTL_PHYSUSPENDED_OFFSET		4
+#define DWC2_PCGCCTL_ENBL_SLEEP_GATING			(1 << 5)
+#define DWC2_PCGCCTL_ENBL_SLEEP_GATING_OFFSET		5
+#define DWC2_PCGCCTL_PHY_IN_SLEEP			(1 << 6)
+#define DWC2_PCGCCTL_PHY_IN_SLEEP_OFFSET		6
+#define DWC2_PCGCCTL_DEEP_SLEEP				(1 << 7)
+#define DWC2_PCGCCTL_DEEP_SLEEP_OFFSET			7
+#define DWC2_SNPSID_DEVID_VER_2xx			(0x4f542 << 12)
+#define DWC2_SNPSID_DEVID_MASK				(0xfffff << 12)
+#define DWC2_SNPSID_DEVID_OFFSET			12
+
+/* Host controller specific */
+#define DWC2_HC_PID_DATA0		0
+#define DWC2_HC_PID_DATA2		1
+#define DWC2_HC_PID_DATA1		2
+#define DWC2_HC_PID_MDATA		3
+#define DWC2_HC_PID_SETUP		3
+
+/* roothub.a masks */
+#define RH_A_NDP	(0xff << 0)	/* number of downstream ports */
+#define RH_A_PSM	(1 << 8)	/* power switching mode */
+#define RH_A_NPS	(1 << 9)	/* no power switching */
+#define RH_A_DT		(1 << 10)	/* device type (mbz) */
+#define RH_A_OCPM	(1 << 11)	/* over current protection mode */
+#define RH_A_NOCP	(1 << 12)	/* no over current protection */
+#define RH_A_POTPGT	(0xff << 24)	/* power on to power good time */
+
+/* roothub.b masks */
+#define RH_B_DR		0x0000ffff	/* device removable flags */
+#define RH_B_PPCM	0xffff0000	/* port power control mask */
+
+/* Default driver configuration */
+#define CONFIG_DWC2_DMA_ENABLE
+#define CONFIG_DWC2_DMA_BURST_SIZE		32	/* DMA burst len */
+#undef CONFIG_DWC2_DFLT_SPEED_FULL		/* Do not force DWC2 to FS */
+#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO		/* Runtime FIFO size detect */
+#define CONFIG_DWC2_MAX_CHANNELS		16	/* Max # of EPs */
+#define CONFIG_DWC2_HOST_RX_FIFO_SIZE		(516 + CONFIG_DWC2_MAX_CHANNELS)
+#define CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE	0x100	/* nPeriodic TX FIFO */
+#define CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE	0x200	/* Periodic TX FIFO */
+#define CONFIG_DWC2_MAX_TRANSFER_SIZE		65535
+#define CONFIG_DWC2_MAX_PACKET_COUNT		511
+
+#define DWC2_PHY_TYPE_FS		0
+#define DWC2_PHY_TYPE_UTMI		1
+#define DWC2_PHY_TYPE_ULPI		2
+#define CONFIG_DWC2_PHY_TYPE		DWC2_PHY_TYPE_UTMI	/* PHY type */
+#define CONFIG_DWC2_UTMI_WIDTH		8	/* UTMI bus width (8/16) */
+
+#undef CONFIG_DWC2_PHY_ULPI_DDR			/* ULPI PHY uses DDR mode */
+#define CONFIG_DWC2_PHY_ULPI_EXT_VBUS		/* ULPI PHY controls VBUS */
+#undef CONFIG_DWC2_I2C_ENABLE			/* Enable I2C */
+#undef CONFIG_DWC2_ULPI_FS_LS			/* ULPI is FS/LS */
+#undef CONFIG_DWC2_TS_DLINE			/* External DLine pulsing */
+#undef CONFIG_DWC2_THR_CTL			/* Threshold control */
+#define CONFIG_DWC2_TX_THR_LENGTH		64
+#undef CONFIG_DWC2_IC_USB_CAP			/* IC Cap */
+
+#endif	/* __DWC2_H__ */
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 6323c508375..c671c72cb1c 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -119,15 +119,12 @@ static struct descriptor {
 #define ehci_is_TDI()	(0)
 #endif
 
-int __ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
+__weak int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
 {
 	return PORTSC_PSPD(reg);
 }
 
-int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
-	__attribute__((weak, alias("__ehci_get_port_speed")));
-
-void __ehci_set_usbmode(int index)
+__weak void ehci_set_usbmode(int index)
 {
 	uint32_t tmp;
 	uint32_t *reg_ptr;
@@ -141,17 +138,11 @@ void __ehci_set_usbmode(int index)
 	ehci_writel(reg_ptr, tmp);
 }
 
-void ehci_set_usbmode(int index)
-	__attribute__((weak, alias("__ehci_set_usbmode")));
-
-void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
+__weak void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
 {
 	mdelay(50);
 }
 
-void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
-	__attribute__((weak, alias("__ehci_powerup_fixup")));
-
 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
 {
 	uint32_t result;
@@ -1106,6 +1097,7 @@ submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 }
 
 struct int_queue {
+	int elementsize;
 	struct QH *first;
 	struct QH *current;
 	struct QH *last;
@@ -1163,6 +1155,23 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize,
 	struct int_queue *result = NULL;
 	int i;
 
+	/*
+	 * Interrupt transfers requiring several transactions are not supported
+	 * because bInterval is ignored.
+	 *
+	 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
+	 * <= PKT_ALIGN if several qTDs are required, while the USB
+	 * specification does not constrain this for interrupt transfers. That
+	 * means that ehci_submit_async() would support interrupt transfers
+	 * requiring several transactions only as long as the transfer size does
+	 * not require more than a single qTD.
+	 */
+	if (elementsize > usb_maxpacket(dev, pipe)) {
+		printf("%s: xfers requiring several transactions are not supported.\n",
+		       __func__);
+		return NULL;
+	}
+
 	debug("Enter create_int_queue\n");
 	if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
 		debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
@@ -1183,6 +1192,7 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize,
 		debug("ehci intr queue: out of memory\n");
 		goto fail1;
 	}
+	result->elementsize = elementsize;
 	result->first = memalign(USB_DMA_MINALIGN,
 				 sizeof(struct QH) * queuesize);
 	if (!result->first) {
@@ -1258,9 +1268,11 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize,
 			   ALIGN_END_ADDR(struct qTD, result->tds,
 					  queuesize));
 
-	if (disable_periodic(ctrl) < 0) {
-		debug("FATAL: periodic should never fail, but did");
-		goto fail3;
+	if (ctrl->periodic_schedules > 0) {
+		if (disable_periodic(ctrl) < 0) {
+			debug("FATAL: periodic should never fail, but did");
+			goto fail3;
+		}
 	}
 
 	/* hook up to periodic list */
@@ -1317,6 +1329,11 @@ void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
 		queue->current++;
 	else
 		queue->current = NULL;
+
+	invalidate_dcache_range((uint32_t)cur->buffer,
+				ALIGN_END_ADDR(char, cur->buffer,
+					       queue->elementsize));
+
 	debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
 	      hc32_to_cpu(cur_td->qt_token), cur, queue->first);
 	return cur->buffer;
@@ -1382,24 +1399,9 @@ submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 	debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
 	      dev, pipe, buffer, length, interval);
 
-	/*
-	 * Interrupt transfers requiring several transactions are not supported
-	 * because bInterval is ignored.
-	 *
-	 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
-	 * <= PKT_ALIGN if several qTDs are required, while the USB
-	 * specification does not constrain this for interrupt transfers. That
-	 * means that ehci_submit_async() would support interrupt transfers
-	 * requiring several transactions only as long as the transfer size does
-	 * not require more than a single qTD.
-	 */
-	if (length > usb_maxpacket(dev, pipe)) {
-		printf("%s: Interrupt transfers requiring several "
-			"transactions are not supported.\n", __func__);
-		return -1;
-	}
-
 	queue = create_int_queue(dev, pipe, 1, length, buffer);
+	if (!queue)
+		return -1;
 
 	timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
 	while ((backbuffer = poll_int_queue(dev, queue)) == NULL)
@@ -1415,9 +1417,6 @@ submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 		return -EINVAL;
 	}
 
-	invalidate_dcache_range((uint32_t)buffer,
-				ALIGN_END_ADDR(char, buffer, length));
-
 	ret = destroy_int_queue(dev, queue);
 	if (ret < 0)
 		return ret;
diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index 52c43fdc5aa..1a5fd6eefc2 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -13,7 +13,7 @@
 #include <asm/arch/cpu.h>
 
 #if defined(CONFIG_KIRKWOOD)
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #elif defined(CONFIG_ORION5X)
 #include <asm/arch/orion5x.h>
 #endif
diff --git a/drivers/usb/host/ehci-rmobile.c b/drivers/usb/host/ehci-rmobile.c
index 0d1a726d35f..b4330876f83 100644
--- a/drivers/usb/host/ehci-rmobile.c
+++ b/drivers/usb/host/ehci-rmobile.c
@@ -22,12 +22,8 @@ static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
 	0xEE0A0000,	/* USB1 */
 	0xEE0C0000,	/* USB2 */
 };
-#elif defined(CONFIG_R8A7791)
-static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
-	0xEE080000,	/* USB0 (EHCI) */
-	0xEE0C0000,	/* USB1 */
-};
-#elif defined(CONFIG_R8A7794)
+#elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
+	defined(CONFIG_R8A7794)
 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
 	0xEE080000,	/* USB0 (EHCI) */
 	0xEE0C0000,	/* USB1 */
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index 23617b7adc1..4befd574541 100644
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -105,7 +105,7 @@ static void sunxi_usb_phy_init(struct sunxi_ehci_hcd *sunxi_ehci)
 	usb_phy_write(sunxi_ehci, 0x20, 0x14, 5);
 
 	/* threshold adjustment disconnect */
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
 	usb_phy_write(sunxi_ehci, 0x2a, 3, 2);
 #else
 	usb_phy_write(sunxi_ehci, 0x2a, 2, 2);
@@ -163,11 +163,16 @@ int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
 {
 	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
+	int err;
 
 	/* enable common PHY only once */
 	if (index == 0)
 		setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
 
+	err = gpio_request(sunxi_ehci->gpio_vbus, "ehci_vbus");
+	if (err)
+		return err;
+
 	sunxi_ehci_enable(sunxi_ehci);
 
 	*hccr = get_io_base(sunxi_ehci->id);
@@ -188,9 +193,14 @@ int ehci_hcd_stop(int index)
 {
 	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
+	int err;
 
 	sunxi_ehci_disable(sunxi_ehci);
 
+	err = gpio_free(sunxi_ehci->gpio_vbus);
+	if (err)
+		return err;
+
 	/* disable common PHY only once, for the last enabled hcd */
 	if (enabled_hcd_count == 1)
 		clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
diff --git a/drivers/usb/host/xhci-keystone.c b/drivers/usb/host/xhci-keystone.c
new file mode 100644
index 00000000000..05d338f261c
--- /dev/null
+++ b/drivers/usb/host/xhci-keystone.c
@@ -0,0 +1,329 @@
+/*
+ * USB 3.0 DRD Controller
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <usb.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/io.h>
+#include <linux/usb/dwc3.h>
+#include <asm/arch/xhci-keystone.h>
+#include <asm-generic/errno.h>
+#include <linux/list.h>
+#include "xhci.h"
+
+struct kdwc3_irq_regs {
+	u32 revision;	/* 0x000 */
+	u32 rsvd0[3];
+	u32 sysconfig;	/* 0x010 */
+	u32 rsvd1[1];
+	u32 irq_eoi;
+	u32 rsvd2[1];
+	struct {
+		u32 raw_status;
+		u32 status;
+		u32 enable_set;
+		u32 enable_clr;
+	} irqs[16];
+};
+
+struct keystone_xhci {
+	struct xhci_hccr *hcd;
+	struct dwc3 *dwc3_reg;
+	struct xhci_hcor *hcor;
+	struct kdwc3_irq_regs *usbss;
+	struct keystone_xhci_phy *phy;
+};
+
+struct keystone_xhci keystone;
+
+static void keystone_xhci_phy_set(struct keystone_xhci_phy *phy)
+{
+	u32 val;
+
+	/*
+	 * VBUSVLDEXTSEL has a default value of 1 in BootCfg but shouldn't.
+	 * It should always be cleared because our USB PHY has an onchip VBUS
+	 * analog comparator.
+	 */
+	val = readl(&phy->phy_clock);
+	/* quit selecting the vbusvldextsel by default! */
+	val &= ~USB3_PHY_OTG_VBUSVLDECTSEL;
+	writel(val, &phy->phy_clock);
+}
+
+static void keystone_xhci_phy_unset(struct keystone_xhci_phy *phy)
+{
+	u32 val;
+
+	/* Disable the PHY REFCLK clock gate */
+	val = readl(&phy->phy_clock);
+	val &= ~USB3_PHY_REF_SSP_EN;
+	writel(val, &phy->phy_clock);
+}
+
+static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
+{
+	clrsetbits_le32(&dwc3_reg->g_ctl,
+			DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
+			DWC3_GCTL_PRTCAPDIR(mode));
+}
+
+static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
+{
+	/* Before Resetting PHY, put Core in Reset */
+	setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
+
+	/* Assert USB3 PHY reset */
+	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+	/* Assert USB2 PHY reset */
+	setbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+	mdelay(100);
+
+	/* Clear USB3 PHY reset */
+	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+	/* Clear USB2 PHY reset */
+	clrbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+	/* After PHYs are stable we can take Core out of reset state */
+	clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
+}
+
+static int dwc3_core_init(struct dwc3 *dwc3_reg)
+{
+	u32 revision, val;
+	unsigned long t_rst;
+	unsigned int dwc3_hwparams1;
+
+	revision = readl(&dwc3_reg->g_snpsid);
+	/* This should read as U3 followed by revision number */
+	if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
+		puts("this is not a DesignWare USB3 DRD Core\n");
+		return -EINVAL;
+	}
+
+	/* issue device SoftReset too */
+	writel(DWC3_DCTL_CSFTRST, &dwc3_reg->d_ctl);
+
+	t_rst = get_timer(0);
+	do {
+		val = readl(&dwc3_reg->d_ctl);
+		if (!(val & DWC3_DCTL_CSFTRST))
+			break;
+		WATCHDOG_RESET();
+	} while (get_timer(t_rst) < 500);
+
+	if (val & DWC3_DCTL_CSFTRST) {
+		debug("Reset timed out\n");
+		return -2;
+	}
+
+	dwc3_core_soft_reset(dwc3_reg);
+
+	dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
+
+	val = readl(&dwc3_reg->g_ctl);
+	val &= ~DWC3_GCTL_SCALEDOWN_MASK;
+	val &= ~DWC3_GCTL_DISSCRAMBLE;
+	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
+	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
+		val &= ~DWC3_GCTL_DSBLCLKGTNG;
+		break;
+	default:
+		printf("No power optimization available\n");
+	}
+
+	/*
+	 * WORKAROUND: DWC3 revisions <1.90a have a bug
+	 * where the device can fail to connect at SuperSpeed
+	 * and falls back to high-speed mode which causes
+	 * the device to enter a Connect/Disconnect loop
+	 */
+	if ((revision & DWC3_REVISION_MASK) < 0x190a)
+		val |= DWC3_GCTL_U2RSTECN;
+
+	writel(val, &dwc3_reg->g_ctl);
+
+	return 0;
+}
+
+static int keystone_xhci_core_init(struct dwc3 *dwc3_reg)
+{
+	int ret;
+
+	ret = dwc3_core_init(dwc3_reg);
+	if (ret) {
+		debug("failed to initialize core\n");
+		return -EINVAL;
+	}
+
+	/* We are hard-coding DWC3 core to Host Mode */
+	dwc3_set_mode(dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+	return 0;
+}
+
+int xhci_hcd_init(int index,
+		  struct xhci_hccr **ret_hccr, struct xhci_hcor **ret_hcor)
+{
+	u32 val;
+	int ret;
+	struct xhci_hccr *hcd;
+	struct xhci_hcor *hcor;
+	struct kdwc3_irq_regs *usbss;
+	struct keystone_xhci_phy *phy;
+
+	usbss = (struct kdwc3_irq_regs *)CONFIG_USB_SS_BASE;
+	phy = (struct keystone_xhci_phy *)CONFIG_DEV_USB_PHY_BASE;
+
+	/* Enable the PHY REFCLK clock gate with phy_ref_ssp_en = 1 */
+	val = readl(&(phy->phy_clock));
+	val |= USB3_PHY_REF_SSP_EN;
+	writel(val, &phy->phy_clock);
+
+	mdelay(100);
+
+	/* Release USB from reset */
+	ret = psc_enable_module(KS2_LPSC_USB);
+	if (ret) {
+		puts("Cannot enable USB module");
+		return -1;
+	}
+
+	mdelay(100);
+
+	/* Initialize usb phy */
+	keystone_xhci_phy_set(phy);
+
+	/* soft reset usbss */
+	writel(1, &usbss->sysconfig);
+	while (readl(&usbss->sysconfig) & 1)
+		;
+
+	val = readl(&usbss->revision);
+	debug("usbss revision %x\n", val);
+
+	/* Initialize usb core */
+	hcd = (struct xhci_hccr *)CONFIG_USB_HOST_XHCI_BASE;
+	keystone.dwc3_reg = (struct dwc3 *)(CONFIG_USB_HOST_XHCI_BASE +
+					    DWC3_REG_OFFSET);
+
+	keystone_xhci_core_init(keystone.dwc3_reg);
+
+	/* set register addresses */
+	hcor = (struct xhci_hcor *)((uint32_t)hcd +
+		HC_LENGTH(readl(&hcd->cr_capbase)));
+
+	debug("Keystone2-xhci: init hccr %08x and hcor %08x hc_length %d\n",
+	      (u32)hcd, (u32)hcor,
+	      (u32)HC_LENGTH(xhci_readl(&hcd->cr_capbase)));
+
+	keystone.usbss = usbss;
+	keystone.phy = phy;
+	keystone.hcd = hcd;
+	keystone.hcor = hcor;
+
+	*ret_hccr = hcd;
+	*ret_hcor = hcor;
+
+	return 0;
+}
+
+static int keystone_xhci_phy_suspend(void)
+{
+	int loop_cnt = 0;
+	struct xhci_hcor *hcor;
+	uint32_t *portsc_1 = NULL;
+	uint32_t *portsc_2 = NULL;
+	u32 val, usb2_pls, usb3_pls, event_q;
+	struct dwc3 *dwc3_reg = keystone.dwc3_reg;
+
+	/* set register addresses */
+	hcor = keystone.hcor;
+
+	/* Bypass Scrambling and Set Shorter Training sequence for simulation */
+	val = DWC3_GCTL_PWRDNSCALE(0x4b0) | DWC3_GCTL_PRTCAPDIR(0x2);
+	writel(val, &dwc3_reg->g_ctl);
+
+	/* GUSB2PHYCFG */
+	val = readl(&dwc3_reg->g_usb2phycfg[0]);
+
+	/* assert bit 6 (SusPhy) */
+	val |= DWC3_GUSB2PHYCFG_SUSPHY;
+	writel(val, &dwc3_reg->g_usb2phycfg[0]);
+
+	/* GUSB3PIPECTL */
+	val = readl(&dwc3_reg->g_usb3pipectl[0]);
+
+	/*
+	 * assert bit 29 to allow PHY to go to suspend when idle
+	 * and cause the USB3 SS PHY to enter suspend mode
+	 */
+	val |= (BIT(29) | DWC3_GUSB3PIPECTL_SUSPHY);
+	writel(val, &dwc3_reg->g_usb3pipectl[0]);
+
+	/*
+	 * Steps necessary to allow controller to suspend even when
+	 * VBUS is HIGH:
+	 * - Init DCFG[2:0] (DevSpd) to: 1=FS
+	 * - Init GEVNTADR0 to point to an eventQ
+	 * - Init GEVNTSIZ0 to 0x0100 to specify the size of the eventQ
+	 * - Init DCTL::Run_nStop = 1
+	 */
+	writel(0x00020001, &dwc3_reg->d_cfg);
+	/* TODO: local2global( (Uint32) eventQ )? */
+	writel((u32)&event_q, &dwc3_reg->g_evnt_buf[0].g_evntadrlo);
+	writel(0, &dwc3_reg->g_evnt_buf[0].g_evntadrhi);
+	writel(0x4, &dwc3_reg->g_evnt_buf[0].g_evntsiz);
+	/* Run */
+	writel(DWC3_DCTL_RUN_STOP, &dwc3_reg->d_ctl);
+
+	mdelay(100);
+
+	/* Wait for USB2 & USB3 PORTSC::PortLinkState to indicate suspend */
+	portsc_1 = (uint32_t *)(&hcor->portregs[0].or_portsc);
+	portsc_2 = (uint32_t *)(&hcor->portregs[1].or_portsc);
+	usb2_pls = 0;
+	usb3_pls = 0;
+	do {
+		++loop_cnt;
+		usb2_pls = (readl(portsc_1) & PORT_PLS_MASK) >> 5;
+		usb3_pls = (readl(portsc_2) & PORT_PLS_MASK) >> 5;
+	} while (((usb2_pls != 0x4) || (usb3_pls != 0x4)) && loop_cnt < 1000);
+
+	if (usb2_pls != 0x4 || usb3_pls != 0x4) {
+		debug("USB suspend failed - PLS USB2=%02x, USB3=%02x\n",
+		      usb2_pls, usb3_pls);
+		return -1;
+	}
+
+	debug("USB2 and USB3 PLS - Disabled, loop_cnt=%d\n", loop_cnt);
+	return 0;
+}
+
+void xhci_hcd_stop(int index)
+{
+	/* Disable USB */
+	if (keystone_xhci_phy_suspend())
+		return;
+
+	if (psc_disable_module(KS2_LPSC_USB)) {
+		debug("PSC disable module USB failed!\n");
+		return;
+	}
+
+	/* Disable PHY */
+	keystone_xhci_phy_unset(keystone.phy);
+
+/*	memset(&keystone, 0, sizeof(struct keystone_xhci)); */
+	debug("xhci_hcd_stop OK.\n");
+}
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 92319278799..6aa50cb4f96 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -944,7 +944,7 @@ static void parse_putc(const char c)
 		CURSOR_SET;
 }
 
-void video_putc(struct stdio_dev *dev, const char c)
+static void video_putc(struct stdio_dev *dev, const char c)
 {
 #ifdef CONFIG_CFB_CONSOLE_ANSI
 	int i;
@@ -1158,7 +1158,7 @@ void video_putc(struct stdio_dev *dev, const char c)
 		flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE);
 }
 
-void video_puts(struct stdio_dev *dev, const char *s)
+static void video_puts(struct stdio_dev *dev, const char *s)
 {
 	int count = strlen(s);
 
@@ -1171,14 +1171,11 @@ void video_puts(struct stdio_dev *dev, const char *s)
  * video_set_lut() if they do not support 8 bpp format.
  * Implement weak default function instead.
  */
-void __video_set_lut(unsigned int index, unsigned char r,
+__weak void video_set_lut(unsigned int index, unsigned char r,
 		     unsigned char g, unsigned char b)
 {
 }
 
-void video_set_lut(unsigned int, unsigned char, unsigned char, unsigned char)
-	__attribute__ ((weak, alias("__video_set_lut")));
-
 #if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
 
 #define FILL_8BIT_332RGB(r,g,b)	{			\
@@ -2240,15 +2237,12 @@ static int video_init(void)
  * Implement a weak default function for boards that optionally
  * need to skip the video initialization.
  */
-int __board_video_skip(void)
+__weak int board_video_skip(void)
 {
 	/* As default, don't skip test */
 	return 0;
 }
 
-int board_video_skip(void)
-	__attribute__ ((weak, alias("__board_video_skip")));
-
 int drv_video_init(void)
 {
 	int skip_dev_init;
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
index 180a3b41499..be35b982acd 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -58,54 +58,38 @@ static void exynos_lcd_init(vidinfo_t *vid)
 	lcd_set_flush_dcache(1);
 }
 
-void __exynos_cfg_lcd_gpio(void)
+__weak void exynos_cfg_lcd_gpio(void)
 {
 }
-void exynos_cfg_lcd_gpio(void)
-	__attribute__((weak, alias("__exynos_cfg_lcd_gpio")));
 
-void __exynos_backlight_on(unsigned int onoff)
+__weak void exynos_backlight_on(unsigned int onoff)
 {
 }
-void exynos_backlight_on(unsigned int onoff)
-	__attribute__((weak, alias("__exynos_cfg_lcd_gpio")));
 
-void __exynos_reset_lcd(void)
+__weak void exynos_reset_lcd(void)
 {
 }
-void exynos_reset_lcd(void)
-	__attribute__((weak, alias("__exynos_reset_lcd")));
 
-void __exynos_lcd_power_on(void)
+__weak void exynos_lcd_power_on(void)
 {
 }
-void exynos_lcd_power_on(void)
-	__attribute__((weak, alias("__exynos_lcd_power_on")));
 
-void __exynos_cfg_ldo(void)
+__weak void exynos_cfg_ldo(void)
 {
 }
-void exynos_cfg_ldo(void)
-	__attribute__((weak, alias("__exynos_cfg_ldo")));
 
-void __exynos_enable_ldo(unsigned int onoff)
+__weak void exynos_enable_ldo(unsigned int onoff)
 {
 }
-void exynos_enable_ldo(unsigned int onoff)
-	__attribute__((weak, alias("__exynos_enable_ldo")));
 
-void __exynos_backlight_reset(void)
+__weak void exynos_backlight_reset(void)
 {
 }
-void exynos_backlight_reset(void)
-	__attribute__((weak, alias("__exynos_backlight_reset")));
 
-int __exynos_lcd_misc_init(vidinfo_t *vid)
+__weak int exynos_lcd_misc_init(vidinfo_t *vid)
 {
 	return 0;
 }
-int exynos_lcd_misc_init(vidinfo_t *vid)
-	__attribute__((weak, alias("__exynos_lcd_misc_init")));
 
 static void lcd_panel_on(vidinfo_t *vid)
 {
diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
index 8d4e9254784..58735319533 100644
--- a/drivers/video/ipu_common.c
+++ b/drivers/video/ipu_common.c
@@ -379,7 +379,7 @@ static struct clk pixel_clk[] = {
 /*
  * This function resets IPU
  */
-void ipu_reset(void)
+static void ipu_reset(void)
 {
 	u32 *reg;
 	u32 value;
diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c
index 948e1fc401f..4faeafb6351 100644
--- a/drivers/video/ipu_disp.c
+++ b/drivers/video/ipu_disp.c
@@ -377,7 +377,7 @@ static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
 static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE;
 static int color_key_4rgb = 1;
 
-void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,
+static void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,
 			unsigned char srm_mode_update)
 {
 	u32 reg;
@@ -605,17 +605,6 @@ void ipu_dc_uninit(int dc_chan)
 	}
 }
 
-int ipu_chan_is_interlaced(ipu_channel_t channel)
-{
-	if (channel == MEM_DC_SYNC)
-		return !!(__raw_readl(DC_WR_CH_CONF_1) &
-			  DC_WR_CH_CONF_FIELD_MODE);
-	else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
-		return !!(__raw_readl(DC_WR_CH_CONF_5) &
-			  DC_WR_CH_CONF_FIELD_MODE);
-	return 0;
-}
-
 void ipu_dp_dc_enable(ipu_channel_t channel)
 {
 	int di;
@@ -782,7 +771,7 @@ void ipu_init_dc_mappings(void)
 	ipu_dc_map_config(4, 2, 21, 0xFC);
 }
 
-int ipu_pixfmt_to_map(uint32_t fmt)
+static int ipu_pixfmt_to_map(uint32_t fmt)
 {
 	switch (fmt) {
 	case IPU_PIX_FMT_GENERIC:
@@ -802,28 +791,6 @@ int ipu_pixfmt_to_map(uint32_t fmt)
 }
 
 /*
- * This function is called to adapt synchronous LCD panel to IPU restriction.
- */
-void adapt_panel_to_ipu_restricitions(uint32_t *pixel_clk,
-				      uint16_t width, uint16_t height,
-				      uint16_t h_start_width,
-				      uint16_t h_end_width,
-				      uint16_t v_start_width,
-				      uint16_t *v_end_width)
-{
-	if (*v_end_width < 2) {
-		uint16_t total_width = width + h_start_width + h_end_width;
-		uint16_t total_height_old = height + v_start_width +
-			(*v_end_width);
-		uint16_t total_height_new = height + v_start_width + 2;
-		*v_end_width = 2;
-		*pixel_clk = (*pixel_clk) * total_width * total_height_new /
-			(total_width * total_height_old);
-		printf("WARNING: adapt panel end blank lines\n");
-	}
-}
-
-/*
  * This function is called to initialize a synchronous LCD panel.
  *
  * @param       disp            The DI the panel is attached to.
@@ -880,14 +847,17 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
 	if ((v_sync_width == 0) || (h_sync_width == 0))
 		return -EINVAL;
 
-	adapt_panel_to_ipu_restricitions(&pixel_clk, width, height,
-					 h_start_width, h_end_width,
-					 v_start_width, &v_end_width);
+	/* adapt panel to ipu restricitions */
+	if (v_end_width < 2) {
+		v_end_width = 2;
+		puts("WARNING: v_end_width (lower_margin) must be >= 2, adjusted\n");
+	}
+
 	h_total = width + h_sync_width + h_start_width + h_end_width;
 	v_total = height + v_sync_width + v_start_width + v_end_width;
 
 	/* Init clocking */
-	debug("pixel clk = %d\n", pixel_clk);
+	debug("pixel clk = %dHz\n", pixel_clk);
 
 	if (sig.ext_clk) {
 		if (!(g_di1_tvout && (disp == 1))) { /*not round div for tvout*/
diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c
index f75d77064ea..1fa95314fc4 100644
--- a/drivers/video/mxc_ipuv3_fb.c
+++ b/drivers/video/mxc_ipuv3_fb.c
@@ -36,7 +36,7 @@ static struct fb_videomode const *gmode;
 static uint8_t gdisp;
 static uint32_t gpixfmt;
 
-void fb_videomode_to_var(struct fb_var_screeninfo *var,
+static void fb_videomode_to_var(struct fb_var_screeninfo *var,
 			 const struct fb_videomode *mode)
 {
 	var->xres = mode->xres;
@@ -258,8 +258,7 @@ static int mxcfb_set_par(struct fb_info *fbi)
 	if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
 		sig_cfg.clkidle_en = 1;
 
-	debug("pixclock = %ul Hz\n",
-		(u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
+	debug("pixclock = %lu Hz\n", PICOS2KHZ(fbi->var.pixclock) * 1000UL);
 
 	if (ipu_init_sync_panel(mxc_fbi->ipu_di,
 				(PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
@@ -486,7 +485,7 @@ static struct fb_info *mxcfb_init_fbinfo(void)
 
 /*
  * Probe routine for the framebuffer driver. It is called during the
- * driver binding process.      The following functions are performed in
+ * driver binding process. The following functions are performed in
  * this routine: Framebuffer initialization, Memory allocation and
  * mapping, Framebuffer registration, IPU initialization.
  *
@@ -542,7 +541,7 @@ static int mxcfb_probe(u32 interface_pix_fmt, uint8_t disp,
 
 	mxcfb_set_fix(fbi);
 
-	/* alocate fb first */
+	/* allocate fb first */
 	if (mxcfb_map_video_memory(fbi) < 0)
 		return -ENOMEM;
 
diff --git a/dts/Kconfig b/dts/Kconfig
index 83ba7a6e981..5fe63f80258 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -49,7 +49,7 @@ config DEFAULT_DEVICE_TREE
 	string "Default Device Tree for DT control"
 	help
 	  This option specifies the default Device Tree used for DT control.
-	  It can be overrided from the command line:
+	  It can be overridden from the command line:
 	  $ make DEVICE_TREE=<device-tree-name>
 
 endmenu
diff --git a/fs/Makefile b/fs/Makefile
index 18221658fcb..51d06fccb61 100644
--- a/fs/Makefile
+++ b/fs/Makefile
@@ -8,6 +8,7 @@
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_FAT_SUPPORT) += fat/
+obj-$(CONFIG_SPL_EXT_SUPPORT) += ext4/
 else
 obj-y				+= fs.o
 
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 33d69c9c71f..cccc06a8889 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -22,6 +22,7 @@
 #include <common.h>
 #include <ext_common.h>
 #include <ext4fs.h>
+#include <inttypes.h>
 #include <malloc.h>
 #include <stddef.h>
 #include <linux/stat.h>
@@ -73,7 +74,7 @@ void put_ext4(uint64_t off, void *buf, uint32_t size)
 	if ((startblock + (size >> log2blksz)) >
 	    (part_offset + fs->total_sect)) {
 		printf("part_offset is " LBAFU "\n", part_offset);
-		printf("total_sector is %llu\n", fs->total_sect);
+		printf("total_sector is %" PRIu64 "\n", fs->total_sect);
 		printf("error: overflow occurs\n");
 		return;
 	}
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 60539d8a9d2..f81b51aa301 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -26,8 +26,11 @@
  */
 
 /**
- * Request a gpio. This should be called before any of the other functions
- * are used on this gpio.
+ * Request a GPIO. This should be called before any of the other functions
+ * are used on this GPIO.
+ *
+ * Note: With driver model, the label is allocated so there is no need for
+ * the caller to preserve it.
  *
  * @param gp	GPIO number
  * @param label	User label for this GPIO
@@ -80,7 +83,7 @@ int gpio_get_value(unsigned gpio);
 int gpio_set_value(unsigned gpio, int value);
 
 /* State of a GPIO, as reported by get_function() */
-enum {
+enum gpio_func_t {
 	GPIOF_INPUT = 0,
 	GPIOF_OUTPUT,
 	GPIOF_UNUSED,		/* Not claimed */
@@ -93,6 +96,66 @@ enum {
 struct udevice;
 
 /**
+ * gpio_get_status() - get the current GPIO status as a string
+ *
+ * Obtain the current GPIO status as a string which can be presented to the
+ * user. A typical string is:
+ *
+ * "b4:  in: 1 [x] sdmmc_cd"
+ *
+ * which means this is GPIO bank b, offset 4, currently set to input, current
+ * value 1, [x] means that it is requested and the owner is 'sdmmc_cd'
+ *
+ * @dev:	Device to check
+ * @offset:	Offset of device GPIO to check
+ * @buf:	Place to put string
+ * @buffsize:	Size of string including \0
+ */
+int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize);
+
+/**
+ * gpio_get_function() - get the current function for a GPIO pin
+ *
+ * Note this returns GPIOF_UNUSED if the GPIO is not requested.
+ *
+ * @dev:	Device to check
+ * @offset:	Offset of device GPIO to check
+ * @namep:	If non-NULL, this is set to the nane given when the GPIO
+ *		was requested, or -1 if it has not been requested
+ * @return  -ENODATA if the driver returned an unknown function,
+ * -ENODEV if the device is not active, -EINVAL if the offset is invalid.
+ * GPIOF_UNUSED if the GPIO has not been requested. Otherwise returns the
+ * function from enum gpio_func_t.
+ */
+int gpio_get_function(struct udevice *dev, int offset, const char **namep);
+
+/**
+ * gpio_get_raw_function() - get the current raw function for a GPIO pin
+ *
+ * Note this does not return GPIOF_UNUSED - it will always return the GPIO
+ * driver's view of a pin function, even if it is not correctly set up.
+ *
+ * @dev:	Device to check
+ * @offset:	Offset of device GPIO to check
+ * @namep:	If non-NULL, this is set to the nane given when the GPIO
+ *		was requested, or -1 if it has not been requested
+ * @return  -ENODATA if the driver returned an unknown function,
+ * -ENODEV if the device is not active, -EINVAL if the offset is invalid.
+ * Otherwise returns the function from enum gpio_func_t.
+ */
+int gpio_get_raw_function(struct udevice *dev, int offset, const char **namep);
+
+/**
+ * gpio_requestf() - request a GPIO using a format string for the owner
+ *
+ * This is a helper function for gpio_request(). It allows you to provide
+ * a printf()-format string for the GPIO owner. It calls gpio_request() with
+ * the string that is created
+ */
+int gpio_requestf(unsigned gpio, const char *fmt, ...)
+		__attribute__ ((format (__printf__, 2, 3)));
+
+/**
  * struct struct dm_gpio_ops - Driver model GPIO operations
  *
  * Refer to functions above for description. These function largely copy
@@ -102,7 +165,7 @@ struct udevice;
  * new DM GPIO API, this should be really easy to flip over to the Linux
  * GPIO API-alike interface.
  *
- * Akso it would be useful to standardise additional functions like
+ * Also it would be useful to standardise additional functions like
  * pullup, slew rate and drive strength.
  *
  * gpio_request)( and gpio_free() are optional - if NULL then they will
@@ -115,7 +178,7 @@ struct udevice;
  * SoCs there may be many banks and therefore many devices all referring
  * to the different IO addresses within the SoC.
  *
- * The uclass combines all GPIO devices togther to provide a consistent
+ * The uclass combines all GPIO devices together to provide a consistent
  * numbering from 0 to n-1, where n is the number of GPIOs in total across
  * all devices. Be careful not to confuse offset with gpio in the parameters.
  */
@@ -135,15 +198,13 @@ struct dm_gpio_ops {
 	 * @return current function - GPIOF_...
 	 */
 	int (*get_function)(struct udevice *dev, unsigned offset);
-	int (*get_state)(struct udevice *dev, unsigned offset, char *state,
-			 int maxlen);
 };
 
 /**
  * struct gpio_dev_priv - information about a device used by the uclass
  *
  * The uclass combines all active GPIO devices into a unified numbering
- * scheme. To do this it maintains some private information aobut each
+ * scheme. To do this it maintains some private information about each
  * device.
  *
  * To implement driver model support in your GPIO driver, add a probe
@@ -157,11 +218,14 @@ struct dm_gpio_ops {
  * @gpio_base: Base GPIO number for this device. For the first active device
  * this will be 0; the numbering for others will follow sequentially so that
  * @gpio_base for device 1 will equal the number of GPIOs in device 0.
+ * @name: Array of pointers to the name for each GPIO in this bank. The
+ * value of the pointer will be NULL if the GPIO has not been claimed.
  */
 struct gpio_dev_priv {
 	const char *bank_name;
 	unsigned gpio_count;
 	unsigned gpio_base;
+	char **name;
 };
 
 /* Access the GPIO operations for a device */
@@ -193,4 +257,6 @@ const char *gpio_get_bank_info(struct udevice *dev, int *offset_count);
 int gpio_lookup_name(const char *name, struct udevice **devp,
 		     unsigned int *offsetp, unsigned int *gpiop);
 
+int name_to_gpio(const char *name);
+
 #endif	/* _ASM_GENERIC_GPIO_H_ */
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index 62cb1eabc1f..aef39d78846 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -79,9 +79,6 @@ typedef struct bd_info {
 	unsigned int	bi_pci_busfreq;	/* PCI Bus speed, in Hz */
 	unsigned char	bi_pci_enetaddr[6];	/* PCI Ethernet MAC address */
 #endif
-#if defined(CONFIG_HYMOD)
-	hymod_conf_t	bi_hymod_conf;	/* hymod configuration information */
-#endif
 
 #ifdef CONFIG_HAS_ETH1
 	unsigned char   bi_enet1addr[6];	/* OLD: see README.enetaddr */
diff --git a/include/bootm.h b/include/bootm.h
index 694d6fc080f..b3d1a620dae 100644
--- a/include/bootm.h
+++ b/include/bootm.h
@@ -54,4 +54,6 @@ int bootm_find_ramdisk_fdt(int flag, int argc, char * const argv[]);
 int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
 		    int states, bootm_headers_t *images, int boot_progress);
 
+void arch_preboot_os(void);
+
 #endif
diff --git a/include/bootstage.h b/include/bootstage.h
index 87bf906b263..df13ab2f63e 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -159,6 +159,9 @@ enum bootstage_id {
 	/* Next 10 IDs used by BOOTSTAGE_SUB_... */
 	BOOTSTAGE_ID_FIT_RD_START = 120,	/* Ramdisk stages */
 
+	/* Next 10 IDs used by BOOTSTAGE_SUB_... */
+	BOOTSTAGE_ID_FIT_SETUP_START = 130,	/* x86 setup stages */
+
 	BOOTSTAGE_ID_IDE_FIT_READ = 140,
 	BOOTSTAGE_ID_IDE_FIT_READ_OK,
 
diff --git a/include/cli_hush.h b/include/cli_hush.h
index 4951eef5724..57c870dfe99 100644
--- a/include/cli_hush.h
+++ b/include/cli_hush.h
@@ -11,6 +11,7 @@
 #define FLAG_EXIT_FROM_LOOP 1
 #define FLAG_PARSE_SEMICOLON (1 << 1)	  /* symbol ';' is special for parser */
 #define FLAG_REPARSING       (1 << 2)	  /* >=2nd pass */
+#define FLAG_CONT_ON_NEWLINE (1 << 3)	  /* continue when we see \n */
 
 extern int u_boot_hush_start(void);
 extern int parse_string_outer(const char *, int);
diff --git a/include/command.h b/include/command.h
index 6f06db1cc30..bd3fc049eca 100644
--- a/include/command.h
+++ b/include/command.h
@@ -147,6 +147,7 @@ int cmd_process(int flag, int argc, char * const argv[],
  */
 #define CMD_FLAG_REPEAT		0x0001	/* repeat last command		*/
 #define CMD_FLAG_BOOTD		0x0002	/* command is from bootd	*/
+#define CMD_FLAG_ENV		0x0004	/* command is from the environment */
 
 #ifdef CONFIG_AUTO_COMPLETE
 # define _CMD_COMPLETE(x) x,
diff --git a/include/common.h b/include/common.h
index d5020c8c45d..ecf7fcaf7b6 100644
--- a/include/common.h
+++ b/include/common.h
@@ -69,9 +69,6 @@ typedef volatile unsigned char	vu_char;
 #ifdef	CONFIG_4xx
 #include <asm/ppc4xx.h>
 #endif
-#ifdef CONFIG_HYMOD
-#include <board/hymod/hymod.h>
-#endif
 #ifdef CONFIG_ARM
 #define asmlinkage	/* nothing */
 #endif
@@ -86,6 +83,9 @@ typedef volatile unsigned char	vu_char;
 #include <flash.h>
 #include <image.h>
 
+/* Bring in printf format macros if inttypes.h is included */
+#define __STDC_FORMAT_MACROS
+
 #ifdef __LP64__
 #define CONFIG_SYS_SUPPORT_64BIT_DATA
 #endif
@@ -253,7 +253,19 @@ int	cpu_init(void);
 /* */
 phys_size_t initdram (int);
 int	display_options (void);
-void	print_size(unsigned long long, const char *);
+
+/**
+ * print_size() - Print a size with a suffic
+ *
+ * print sizes as "xxx KiB", "xxx.y KiB", "xxx MiB", "xxx.y MiB",
+ * xxx GiB, xxx.y GiB, etc as needed; allow for optional trailing string
+ * (like "\n")
+ *
+ * @size:	Size to print
+ * @suffix	String to print after the size
+ */
+void print_size(uint64_t size, const char *suffix);
+
 int print_buffer(ulong addr, const void *data, uint width, uint count,
 		 uint linelen);
 
@@ -636,13 +648,6 @@ struct stdio_dev;
 int serial_stub_getc(struct stdio_dev *sdev);
 int serial_stub_tstc(struct stdio_dev *sdev);
 
-void	_serial_setbrg (const int);
-void	_serial_putc   (const char, const int);
-void	_serial_putc_raw(const char, const int);
-void	_serial_puts   (const char *, const int);
-int	_serial_getc   (const int);
-int	_serial_tstc   (const int);
-
 /* $(CPU)/speed.c */
 int	get_clocks (void);
 int	get_clocks_866 (void);
@@ -773,7 +778,7 @@ void	invalidate_dcache_all(void);
 void	invalidate_icache_all(void);
 
 /* arch/$(ARCH)/lib/ticks.S */
-unsigned long long get_ticks(void);
+uint64_t get_ticks(void);
 void	wait_ticks    (unsigned long);
 
 /* arch/$(ARCH)/lib/time.c */
diff --git a/include/commproc.h b/include/commproc.h
index 82a1a985b23..d78ab0081c2 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -563,16 +563,6 @@ typedef struct scc_enet {
 
 #endif	/* CONFIG_HERMES */
 
-/*** ICU862  **********************************************************/
-
-#if defined(CONFIG_ICU862)
-
-#ifdef CONFIG_FEC_ENET
-#define FEC_ENET	/* use FEC for EThernet */
-#endif  /* CONFIG_FEC_ETHERNET */
-
-#endif /* CONFIG_ICU862 */
-
 /***  IP860  **********************************************************/
 
 #if defined(CONFIG_IP860)
@@ -713,28 +703,6 @@ typedef struct scc_enet {
 #define SICR_ENET_CLKRT	((uint)0x00250000)
 #endif	/* CONFIG_KM8XX */
 
-
-/***  MHPC  ********************************************************/
-
-#if defined(CONFIG_MHPC)
-/* This ENET stuff is for the MHPC with ethernet on SCC2.
- * Note TENA is on Port B.
- */
-#define	PROFF_ENET	PROFF_SCC2
-#define	CPM_CR_ENET	CPM_CR_CH_SCC2
-#define	SCC_ENET	1
-#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
-#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
-#define PA_ENET_RCLK	((ushort)0x0200)	/* PA 6 */
-#define PA_ENET_TCLK	((ushort)0x0400)	/* PA 5 */
-#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
-#define PC_ENET_CLSN	((ushort)0x0040)	/* PC 9 */
-#define PC_ENET_RENA	((ushort)0x0080)	/* PC 8 */
-
-#define SICR_ENET_MASK	((uint)0x0000ff00)
-#define SICR_ENET_CLKRT	((uint)0x00002e00)	/* RCLK-CLK2, TCLK-CLK3 */
-#endif	/* CONFIG_MHPC */
-
 /***  NETVIA  *******************************************************/
 
 #if defined(CONFIG_NETVIA)
diff --git a/include/compiler.h b/include/compiler.h
index 21036022d7a..47c296e202d 100644
--- a/include/compiler.h
+++ b/include/compiler.h
@@ -112,6 +112,14 @@ typedef unsigned int uint;
 
 #else /* !USE_HOSTCC */
 
+#ifdef CONFIG_USE_STDINT
+/* Provided by gcc. */
+#include <stdint.h>
+#else
+/* Type for `void *' pointers. */
+typedef unsigned long int uintptr_t;
+#endif
+
 #include <linux/string.h>
 #include <linux/types.h>
 #include <asm/byteorder.h>
@@ -128,9 +136,6 @@ typedef unsigned int uint;
 #define __WORDSIZE	32
 #endif
 
-/* Type for `void *' pointers. */
-typedef unsigned long int uintptr_t;
-
 #endif /* USE_HOSTCC */
 
 #define likely(x)	__builtin_expect(!!(x), 1)
diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
index 5d18a4b903a..1ecc0bb0a99 100644
--- a/include/config_distro_defaults.h
+++ b/include/config_distro_defaults.h
@@ -10,7 +10,7 @@
 /*
  * List of all commands and options that when defined enables support for
  * features required by distros to support boards in a standardised and
- * consitant manner.
+ * consistent manner.
  */
 
 #define CONFIG_BOOTP_BOOTPATH
diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h
index 76818f673f2..7d8daa2b8e5 100644
--- a/include/config_fallbacks.h
+++ b/include/config_fallbacks.h
@@ -79,10 +79,6 @@
 #define CONFIG_SYS_PROMPT	"=> "
 #endif
 
-#ifndef CONFIG_SYS_HZ
-#define CONFIG_SYS_HZ		1000
-#endif
-
 #ifndef CONFIG_FIT_SIGNATURE
 #define CONFIG_IMAGE_FORMAT_LEGACY
 #endif
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 9063c57b409..dc1a9bc1ef9 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -82,6 +82,7 @@
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
 #define CONFIG_PCIE1			/* PCIE controler 1 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
@@ -759,6 +760,12 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_NET
 #endif
 
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 /*
 * USB
 */
@@ -913,4 +920,8 @@ unsigned long get_board_ddr_clk(void);
 
 #include <asm/fsl_secure_boot.h>
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index 56a3e948685..bc5af526c5f 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -55,6 +55,7 @@
 #define CONFIG_BOOKE			/* BOOKE */
 #define CONFIG_E500			/* BOOKE e500 family */
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 
 #define CONFIG_FSL_LAW			/* Use common FSL init code */
 #define CONFIG_TSEC_ENET
@@ -382,6 +383,12 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 #define CONFIG_USB_EHCI
 
 #ifdef CONFIG_USB_EHCI
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index aeded6d85b4..989363c0fbc 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -78,6 +78,7 @@
 #define CONFIG_BOOKE			/* BOOKE */
 #define CONFIG_E500			/* BOOKE e500 family */
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
 
 #define CONFIG_PCI			/* Enable PCI/PCIE */
@@ -598,6 +599,12 @@ combinations. this should be removed later
 #define CONFIG_DOS_PARTITION
 #endif
 
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 /*
  * Miscellaneous configurable options
  */
@@ -704,4 +711,8 @@ combinations. this should be removed later
 
 #include <asm/fsl_secure_boot.h>
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 715616d5445..5d11278f036 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -86,6 +86,7 @@
 #define CONFIG_BOOKE			/* BOOKE */
 #define CONFIG_E500			/* BOOKE e500 family */
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
 
 #define CONFIG_PCI			/* Enable PCI/PCIE */
@@ -506,6 +507,12 @@
 #define CONFIG_CMD_SETEXPR
 #define CONFIG_CMD_REGINFO
 
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
deleted file mode 100644
index 304a12bea9c..00000000000
--- a/include/configs/CPCI750.h
+++ /dev/null
@@ -1,609 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-/*************************************************************************
- * (c) 2004 esd gmbh Hannover
- *
- *
- * from db64360.h file
- * by Reinhard Arlt reinhard.arlt@esd-electronics.com
- *
-  ************************************************************************/
-
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* This define must be before the core.h include */
-#define CONFIG_CPCI750		1	/* this is an CPCI750 board	*/
-
-#ifndef __ASSEMBLY__
-#include <../board/Marvell/include/core.h>
-#endif
-/*-----------------------------------------------------*/
-
-#include "../board/esd/cpci750/local.h"
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_750FX			/* we have a 750FX (override local.h) */
-
-#define CONFIG_CPCI750		1	/* this is an CPCI750 board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600	*/
-
-#define CONFIG_MV64360_ECC		/* enable ECC support */
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/* which initialization functions to call for this board */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_BOARD_PRE_INIT
-#define CONFIG_BOARD_EARLY_INIT_F 1
-
-#define CONFIG_SYS_BOARD_NAME		"CPCI750"
-#define CONFIG_IDENT_STRING	"Marvell 64360 + IBM750FX"
-
-/*#define CONFIG_SYS_HUSH_PARSER*/
-#define CONFIG_SYS_HUSH_PARSER
-
-
-#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
-#define CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/
-
-/* Define which ETH port will be used for connecting the network */
-#define CONFIG_SYS_ETH_PORT		ETH_0
-
-/*
- * The following defines let you select what serial you want to use
- * for your console driver.
- *
- * what to do:
- * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
- * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
- * to 0 below.
- *
- * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
- * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
- */
-#define CONFIG_MPSC
-#define CONFIG_MPSC_PORT	0
-
-/* to change the default ethernet port, use this define (options: 0, 1, 2) */
-#define MV_ETH_DEVS		1
-#define CONFIG_ETHER_PORT	0
-
-#undef CONFIG_ETHER_PORT_MII	/* use RMII */
-
-#define CONFIG_BOOTDELAY	5	/* autoboot disabled		*/
-
-#define CONFIG_RTC_M48T35A	1	/* ST Electronics M48 timekeeper */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-
-#undef	CONFIG_BOOTARGS
-
-/* -----------------------------------------------------------------------------
- * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus
- */
-
-#define CONFIG_IPADDR		"192.168.0.185"
-
-#define CONFIG_SERIAL		"AA000001"
-#define CONFIG_SERVERIP		"10.0.0.79"
-#define CONFIG_ROOTPATH		"/export/nfs_cpci750/%s"
-
-#define CONFIG_TESTDRAMDATA	y
-#define CONFIG_TESTDRAMADDRESS	n
-#define CONFIG_TESETDRAMWALK	n
-
-/* ----------------------------------------------------------------------------- */
-
-
-#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#undef	CONFIG_ALTIVEC			/* undef to disable		*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-
-
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_USE_CPCIDVI
-
-#ifdef	CONFIG_USE_CPCIDVI
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_CT69000
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_I8042_KBD
-#define CONFIG_SYS_ISA_IO 0
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_SPEED	80000		/* I2C speed default */
-
-#define CONFIG_PRAM 0
-
-#define CONFIG_SYS_GT_DUAL_CPU			/* also for JTAG even with one cpu */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-/*#define CONFIG_SYS_MEMTEST_START	0x00400000*/	/* memtest works on	*/
-/*#define CONFIG_SYS_MEMTEST_END		0x00C00000*/	/* 4 ... 12 MB in DRAM	*/
-/*#define CONFIG_SYS_MEMTEST_END		0x07c00000*/	/* 4 ... 124 MB in DRAM */
-
-/*
-#define CONFIG_SYS_DRAM_TEST
- * DRAM tests
- *   CONFIG_SYS_DRAM_TEST - enables the following tests.
- *
- *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
- *			  Environment variable 'test_dram_data' must be
- *			  set to 'y'.
- *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
- *			  addressable. Environment variable
- *			  'test_dram_address' must be set to 'y'.
- *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
- *			  This test takes about 6 minutes to test 64 MB.
- *			  Environment variable 'test_dram_walk' must be
- *			  set to 'y'.
- */
-#define CONFIG_SYS_DRAM_TEST
-#if defined(CONFIG_SYS_DRAM_TEST)
-#define CONFIG_SYS_MEMTEST_START		0x00400000	/* memtest works on	*/
-/*#define CONFIG_SYS_MEMTEST_END		0x00C00000*/	/* 4 ... 12 MB in DRAM	*/
-#define CONFIG_SYS_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
-#define CONFIG_SYS_DRAM_TEST_DATA
-#define CONFIG_SYS_DRAM_TEST_ADDRESS
-#define CONFIG_SYS_DRAM_TEST_WALK
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-#define CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
-#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
-
-#define CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address */
-
-#define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_TCLK		133000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
- /*
- * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
- * To an unused memory region. The stack will remain in cache until RAM
- * is initialized
-*/
-#undef	  CONFIG_SYS_INIT_RAM_LOCK
-/* #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000*/ /* unused memory region */
-/* #define CONFIG_SYS_INIT_RAM_ADDR	0xfba00000*/ /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_ADDR	0xf1080000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define RELOCATE_INTERNAL_RAM_ADDR
-#ifdef RELOCATE_INTERNAL_RAM_ADDR
-/*#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xfba00000*/
-#define CONFIG_SYS_INTERNAL_RAM_ADDR	0xf1080000
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-/* Dummies for BAT 4-7 */
-#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte */
-#define CONFIG_SYS_SDRAM2_BASE		0x20000000
-#define CONFIG_SYS_SDRAM3_BASE		0x30000000
-#define CONFIG_SYS_SDRAM4_BASE		0x40000000
-#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE	0xfff00000
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 256 kB for malloc */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI		1	   /* Flash is CFI conformant		*/
-#define CONFIG_SYS_FLASH_PROTECTION	1	   /* use hardware protection		*/
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	   /* use buffered writes (20x faster)	*/
-#define CONFIG_SYS_FLASH_BASE		0xfc000000 /* start of flash banks		*/
-#define CONFIG_SYS_MAX_FLASH_BANKS	4	   /* max number of memory banks	*/
-#define CONFIG_SYS_FLASH_INCREMENT	0x01000000 /* size of  flash bank		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128	   /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_BANKS_LIST  { CONFIG_SYS_FLASH_BASE,				   \
-				CONFIG_SYS_FLASH_BASE + 1*CONFIG_SYS_FLASH_INCREMENT,	   \
-				CONFIG_SYS_FLASH_BASE + 2*CONFIG_SYS_FLASH_INCREMENT,	   \
-				CONFIG_SYS_FLASH_BASE + 3*CONFIG_SYS_FLASH_INCREMENT }
-#define CONFIG_SYS_FLASH_EMPTY_INFO	1	   /* show if bank is empty		*/
-
-/* areas to map different things with the GT in physical space */
-#define CONFIG_SYS_DRAM_BANKS		4
-
-/* What to put in the bats. */
-#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
-
-/* Peripheral Device section */
-
-/*******************************************************/
-/* We have on the cpci750 Board :		       */
-/* GT-Chipset Register Area			       */
-/* GT-Chipset internal SRAM 256k		       */
-/* SRAM on external device module		       */
-/* Real time clock on external device module	       */
-/* dobble UART on external device module	       */
-/* Data flash on external device module		       */
-/* Boot flash on external device module		       */
-/*******************************************************/
-#define CONFIG_SYS_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
-#define	 CONFIG_SYS_CPCI750_RESET_ADDR 0x14000000				/* After power on Reset the CPCI750 is here */
-
-#undef	MARVEL_STANDARD_CFG
-#ifndef		MARVEL_STANDARD_CFG
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-#define CONFIG_SYS_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
-/*#define CONFIG_SYS_DEV_BASE		0xfc000000*/				/* GT Devices CS start here */
-#define CONFIG_SYS_INT_SRAM_BASE	0xf1080000				/* GT offers 256k internal fast SRAM */
-
-#define CONFIG_SYS_BOOT_SPACE		0xff000000				/* BOOT_CS0 flash 0    */
-#define CONFIG_SYS_DEV0_SPACE		0xfc000000				/* DEV_CS0 flash 1     */
-#define CONFIG_SYS_DEV1_SPACE		0xfd000000				/* DEV_CS1 flash 2     */
-#define CONFIG_SYS_DEV2_SPACE		0xfe000000				/* DEV_CS2 flash 3     */
-#define CONFIG_SYS_DEV3_SPACE		0xf0000000				/* DEV_CS3 nvram/can   */
-
-#define CONFIG_SYS_BOOT_SIZE		_16M					/* cpci750 flash 0     */
-#define CONFIG_SYS_DEV0_SIZE		_16M					/* cpci750 flash 1     */
-#define CONFIG_SYS_DEV1_SIZE		_16M					/* cpci750 flash 2     */
-#define CONFIG_SYS_DEV2_SIZE		_16M					/* cpci750 flash 3     */
-#define CONFIG_SYS_DEV3_SIZE		_16M					/* cpci750 nvram/can   */
-
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-#endif
-
-/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
-#define CONFIG_SYS_DEV0_PAR		0x8FDFFFFF				/* 16 bit flash */
-#define CONFIG_SYS_DEV1_PAR		0x8FDFFFFF				/* 16 bit flash */
-#define CONFIG_SYS_DEV2_PAR		0x8FDFFFFF				/* 16 bit flash */
-#define CONFIG_SYS_DEV3_PAR		0x8FCFFFFF				/* nvram/can	*/
-#define CONFIG_SYS_BOOT_PAR		0x8FDFFFFF				/* 16 bit flash */
-
-	/*   c	  4    a      8	    2	  4    1      c		*/
-	/* 33 22|2222|22 22|111 1|11 11|1 1  |	  |		*/
-	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
-	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
-	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
-
-
-/* MPP Control MV64360 Appendix P P. 632*/
-#define CONFIG_SYS_MPP_CONTROL_0	0x00002222	/*				     */
-#define CONFIG_SYS_MPP_CONTROL_1	0x11110000	/*				     */
-#define CONFIG_SYS_MPP_CONTROL_2	0x11111111	/*				     */
-#define CONFIG_SYS_MPP_CONTROL_3	0x00001111	/*				     */
-/* #define CONFIG_SYS_SERIAL_PORT_MUX	0x00000102*/	/*				     */
-
-
-#define CONFIG_SYS_GPP_LEVEL_CONTROL	0xffffffff	/* 1111 1111 1111 1111 1111 1111 1111 1111*/
-
-/* setup new config_value for MV64360 DDR-RAM To_do !! */
-/*# define CONFIG_SYS_SDRAM_CONFIG	0xd8e18200*/	/* 0x448 */
-/*# define CONFIG_SYS_SDRAM_CONFIG	0xd8e14400*/	/* 0x1400 */
-				/* GB has high prio.
-				   idma has low prio
-				   MPSC has low prio
-				   pci has low prio 1 and 2
-				   cpu has high prio
-				   Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices
-				   ECC disable
-				   non registered DRAM */
-				/* 31:26   25:22  21:20 19 18 17 16 */
-				/* 100001 0000	 010   0   0   0  0 */
-				/* refresh_count=0x400
-				   phisical interleaving disable
-				   virtual interleaving enable */
-				/* 15 14 13:0 */
-				/* 0  1	 0x400 */
-# define CONFIG_SYS_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-
-#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-#define CONFIG_PCI_SCAN_SHOW		/* show devices on bus		*/
-
-/* PCI MEMORY MAP section */
-#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
-#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
-#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
-
-#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
-#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
-
-/* PCI I/O MAP section */
-#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
-#define CONFIG_SYS_PCI0_IO_SIZE	_16M
-#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
-#define CONFIG_SYS_PCI1_IO_SIZE	_16M
-
-#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
-#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
-#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
-
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
-
-#if defined (CONFIG_750CX)
-#define CONFIG_SYS_PCI_IDSEL 0x0
-#else
-#define CONFIG_SYS_PCI_IDSEL 0x30
-#endif
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#define CONFIG_IDE_RESET		/* no reset for ide supported	*/
-#define CONFIG_IDE_PREINIT		/* check for units		*/
-
-#define CONFIG_SYS_IDE_MAXBUS		2		/* max. 1 IDE busses	*/
-#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR	0
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0
-#define CONFIG_SYS_ATA_IDE1_OFFSET	0
-
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
-#ifndef __ASSEMBLY__
-int ata_device(int dev);
-#endif
-#define ATA_DEVICE(dev)                 ata_device(dev)
-#define CONFIG_ATAPI                    1
-
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* init ram */
-#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-
-/* PCI0, PCI1 in one BAT */
-#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7)
- * IBAT4 and DBAT4
- * FIXME: ingo disable BATs for Linux Kernel
- */
-/* #undef SETUP_HIGH_BATS_FX750	*/	/* don't initialize BATS 4-7 */
-#define SETUP_HIGH_BATS_FX750		/* initialize BATS 4-7 */
-
-#ifdef SETUP_HIGH_BATS_FX750
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* IBAT5 and DBAT5 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-/* IBAT6 and DBAT6 */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-/* IBAT7 and DBAT7 */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-#else		/* set em out of range for Linux !!!!!!!!!!! */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* IBAT5 and DBAT5 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT4U
-
-/* IBAT6 and DBAT6 */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT4U
-
-/* IBAT7 and DBAT7 */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT4U
-
-#endif
-/* FIXME: ingo end: disable BATs for Linux Kernel */
-
-/* I2C addresses for the two DIMM SPD chips */
-#define DIMM0_I2C_ADDR	0x51
-#define DIMM1_I2C_ADDR	0x52
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_BOOT_FLASH_WIDTH	2	/* 16 bit */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
-
-#if 0
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_ADDR		0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
-/* #define CONFIG_ENV_ADDR	   (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
-#endif
-
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x050
-#define CONFIG_ENV_OFFSET		0x200	/* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		0x600	/* 2048 bytes may be used for env vars*/
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000		/* NVRAM base address	*/
-#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CONFIG_SYS_VXWORKS_MAC_PTR	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-0x40)
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
- */
-
-/*#define CONFIG_SYS_L2*/
-#undef CONFIG_SYS_L2
-
-/*    #ifdef CONFIG_750CX*/
-#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
-#define L2_INIT 0
-#else
-#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-#endif
-
-#define L2_ENABLE	(L2_INIT | L2CR_L2E)
-
-#define CONFIG_SYS_BOARD_ASM_INIT	1
-
-#define CPCI750_SLAVE_TEST	(((in8(0xf0300000) & 0x80) == 0) ? 0 : 1)
-#define CPCI750_ECC_TEST	(((in8(0xf0300000) & 0x02) == 0) ? 1 : 0)
-#define CONFIG_SYS_PLD_VER	0xf0e00000
-
-#define CONFIG_OF_LIBFDT 1
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h
deleted file mode 100644
index b77c8b28943..00000000000
--- a/include/configs/DB64360.h
+++ /dev/null
@@ -1,579 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-/*************************************************************************
- * (c) 2002 Datentechnik AG - Project: Dino
- *
- *
- * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $
- *
-  ************************************************************************/
-
-/*************************************************************************
- *
- * History:
- *
- *	$Log: DB64360.h,v $
- *	Revision 1.3  2003/04/26 04:58:13  brad
- *	Cosmetic changes and compiler warning cleanups
- *
- *	Revision 1.2  2003/04/23 15:48:15  ingo
- *	mem. map output added
- *
- *	Revision 1.1  2003/04/17 09:31:42  ias
- *	keymile changes 17_04_2003
- *
- *	Revision 1.10  2003/03/06 12:25:04  ias
- *	750 FX CPU HID settings updated
- *
- *	Revision 1.9  2003/03/03 16:14:36  ias
- *	cleanup compiler warnings of printf fuctions
- *
- *	Revision 1.8  2003/03/03 15:11:44  ias
- *	Marvell MPSC-UART is working
- *
- *	Revision 1.7  2003/02/26 12:15:45  ssu
- *	adapted default parameters to new board flash address
- *
- *	Revision 1.6  2003/02/25 14:55:42  ssu
- *	changed default environment parameters
- *
- *	Revision 1.5  2003/02/21 17:14:23  ias
- *	added extended SPD handling
- *
- *	Revision 1.4  2003/01/14 09:16:08  ias
- *	PPCBoot for Marvel Beta 0.9
- *
- *	Revision 1.3  2002/12/03 13:56:26  ias
- *	Environment in flash support added
- *
- *	Revision 1.2  2002/11/29 16:53:29  ias
- *	Flash support for STM added
- *
- *	Revision 1.1  2002/11/29 13:36:31  ias
- *	Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board
- *	- working DDRRAM (only 32MByte of 128MB Modul)
- *	- working I2C Driver for SPD EEPROM read
- *	- working DUART 16650 for Serial Console
- *	- working "console"
- *
- *
- *
- ************************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* This define must be before the core.h include */
-#define CONFIG_DB64360		1	/* this is an DB64360 board	*/
-
-#ifndef __ASSEMBLY__
-#include "../board/Marvell/include/core.h"
-#endif
-
-/*-----------------------------------------------------*/
-/*    #include "../board/db64360/local.h"	      */
-#ifndef __LOCAL_H
-#define __LOCAL_H
-
-/* first ethernet */
-#define CONFIG_ETHADDR		64:36:00:00:00:01
-											     /* next two ethernet hwaddrs */
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		64:36:00:00:00:02
-/* in the atlantis 64360 we have only 2 ETH port on the board,
-if we use PCI it has its own MAC addr */
-
-#define CONFIG_ENV_OVERWRITE
-#endif	/* __CONFIG_H */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_74xx			/* we have a 750FX (override local.h) */
-
-#define CONFIG_DB64360		1	/* this is an DB64360 board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115000	*/
-/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
-	DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
-	so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
-	see sdram_init.c   */
-#undef CONFIG_ECC	 /* enable ECC support */
-#define CONFIG_MV64360_ECC
-
-/* which initialization functions to call for this board */
-#define CONFIG_MISC_INIT_R     /* initialize the icache L1 */
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_SYS_BOARD_NAME		"DB64360"
-#define CONFIG_IDENT_STRING	"Marvell DB64360 (1.1)"
-
-/*#define CONFIG_SYS_HUSH_PARSER */
-#undef CONFIG_SYS_HUSH_PARSER
-
-
-/*
- * The following defines let you select what serial you want to use
- * for your console driver.
- *
- * what to do:
- * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
- * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
- * to 0 below.
- *
- * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
- * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
- */
-
-#define CONFIG_MPSC_PORT	0
-
-/* to change the default ethernet port, use this define (options: 0, 1, 2) */
-#define MV_ETH_DEVS 2
-
-/* #undef CONFIG_ETHER_PORT_MII	 */
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
-#endif
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-
-#undef	CONFIG_BOOTARGS
-/*#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
-
-/* ronen - autoboot using tftp */
-#if (CONFIG_BOOTDELAY >= 0)
-#define CONFIG_BOOTCOMMAND	"tftpboot 0x400000 uImage;\
- setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
- ip=${ipaddr}:${serverip}${bootargs_end};  bootm 0x400000; "
-
-#define CONFIG_BOOTARGS "console=ttyS0,115200"
-
-#endif
-
-/* ronen - the u-boot.bin should be ~0x30000 bytes */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-     "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
-cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
-      "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
-cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
-      "bootargs_root=root=/dev/nfs rw\0" \
-      "bootargs_end=:::DB64360:eth0:none \0"\
-      "ethprime=mv_enet0\0"\
-      "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
-ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
-
-/* --------------------------------------------------------------------------------------------------------------- */
-/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */
-
-#define CONFIG_IPADDR		10.2.40.90
-
-#define CONFIG_SERIAL		"No. 1"
-#define CONFIG_SERVERIP		10.2.1.126
-#define CONFIG_ROOTPATH		"/mnt/yellow_dog_mini"
-
-
-#define CONFIG_TESTDRAMDATA	y
-#define CONFIG_TESTDRAMADDRESS	n
-#define CONFIG_TESETDRAMWALK	n
-
-/* --------------------------------------------------------------------------------------------------------------- */
-
-#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#undef	CONFIG_ALTIVEC			/* undef to disable		*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nor1"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"nor1=db64360-1"
-#define MTDPARTS_DEFAULT	"mtdparts=db64360-1:-(jffs2)"
-*/
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NET
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_SPEED	40000		/* I2C speed default */
-
-/* #define CONFIG_SYS_GT_DUAL_CPU	 also for JTAG even with one cpu */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-/*#define CONFIG_SYS_MEMTEST_START	0x00400000	 memtest works on	*/
-/*#define CONFIG_SYS_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
-/*#define CONFIG_SYS_MEMTEST_END		0x07c00000	 4 ... 124 MB in DRAM	*/
-
-/*
-#define CONFIG_SYS_DRAM_TEST
- * DRAM tests
- *   CONFIG_SYS_DRAM_TEST - enables the following tests.
- *
- *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
- *			  Environment variable 'test_dram_data' must be
- *			  set to 'y'.
- *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
- *			  addressable. Environment variable
- *			  'test_dram_address' must be set to 'y'.
- *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
- *			  This test takes about 6 minutes to test 64 MB.
- *			  Environment variable 'test_dram_walk' must be
- *			  set to 'y'.
- */
-#define CONFIG_SYS_DRAM_TEST
-#if defined(CONFIG_SYS_DRAM_TEST)
-#define CONFIG_SYS_MEMTEST_START		0x00400000	/* memtest works on	*/
-/* #define CONFIG_SYS_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
-#define CONFIG_SYS_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
-#define CONFIG_SYS_DRAM_TEST_DATA
-#define CONFIG_SYS_DRAM_TEST_ADDRESS
-#define CONFIG_SYS_DRAM_TEST_WALK
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-#undef CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
-#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
-
-#define CONFIG_SYS_LOAD_ADDR		0x00400000	/* default load address */
-
-/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
-#define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
-
-#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
-#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */
-
-/*ronen - this is the Tclk (MV64360 core) */
-#define CONFIG_SYS_TCLK		133000000
-
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_750FX_HID0		0x8000c084
-#define CONFIG_SYS_750FX_HID1		0x54800000
-#define CONFIG_SYS_750FX_HID2		0x00000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/*
- * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
- * To an unused memory region. The stack will remain in cache until RAM
- * is initialized
-*/
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define RELOCATE_INTERNAL_RAM_ADDR
-#ifdef RELOCATE_INTERNAL_RAM_ADDR
-	#define CONFIG_SYS_INTERNAL_RAM_ADDR	0xf8000000
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-/* Dummies for BAT 4-7 */
-#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte */
-#define CONFIG_SYS_SDRAM2_BASE		0x20000000
-#define CONFIG_SYS_SDRAM3_BASE		0x30000000
-#define CONFIG_SYS_SDRAM4_BASE		0x40000000
-#define CONFIG_SYS_FLASH_BASE			0xfff00000
-
-#define CONFIG_SYS_DFL_BOOTCS_BASE	0xff800000
-#define CONFIG_VERY_BIG_RAM		/* we will use up to 256M memory for cause we are short of BATS*/
-
-#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
-#define UART_BASE_BOOTM	      0xfbb00000 /* in order to be sync with the kernel parameters. */
-#define PCI0_IO_BASE_BOOTM    0xfd000000
-
-#define CONFIG_SYS_RESET_ADDRESS		0xfff00100
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
-
-/* areas to map different things with the GT in physical space */
-#define CONFIG_SYS_DRAM_BANKS		4
-
-/* What to put in the bats. */
-#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
-
-/* Peripheral Device section */
-
-/*******************************************************/
-/* We have on the db64360 Board :		   */
-/* GT-Chipset Register Area				*/
-/* GT-Chipset internal SRAM 256k		    */
-/* SRAM on external device module		   */
-/* Real time clock on external device module	  */
-/* dobble UART on external device module	 */
-/* Data flash on external device module		    */
-/* Boot flash on external device module		    */
-/*******************************************************/
-#define CONFIG_SYS_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
-#define	 CONFIG_SYS_DB64360_RESET_ADDR 0x14000000				/* After power on Reset the DB64360 is here */
-
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-#define CONFIG_SYS_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
-#define CONFIG_SYS_DEV_BASE		0xfc000000				/* GT Devices CS start here */
-
-#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE				/* DEV_CS0 device modul sram */
-#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)	/* DEV_CS1 device modul real time clock (rtc) */
-#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)	/* DEV_CS2 device modul doubel uart (duart) */
-#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)	/* DEV_CS3 device modul large flash */
-
-#define CONFIG_SYS_DEV0_SIZE		 _8M					/* db64360 sram	 @ 0xfc00.0000 */
-#define CONFIG_SYS_DEV1_SIZE		 _8M					/* db64360 rtc	 @ 0xfc80.0000 */
-#define CONFIG_SYS_DEV2_SIZE		_16M					/* db64360 duart @ 0xfd00.0000 */
-#define CONFIG_SYS_DEV3_SIZE		_16M					/* db64360 flash @ 0xfe00.0000 */
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-
-/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
-#define CONFIG_SYS_DEV0_PAR		0x8FEFFFFF				/* 32Bit  sram */
-#define CONFIG_SYS_DEV1_PAR		0x8FCFFFFF				/* 8Bit	 rtc */
-#define CONFIG_SYS_DEV2_PAR		0x8FCFFFFF				/* 8Bit duart */
-#define CONFIG_SYS_8BIT_BOOT_PAR	0x8FCFFFFF				/* 8Bit flash */
-#define CONFIG_SYS_32BIT_BOOT_PAR	0x8FEFFFFF				/* 32Bit flash */
-
-	/*   c	  4    a      8	    2	  4    1      c		*/
-	/* 33 22|2222|22 22|111 1|11 11|1 1  |	  |		*/
-	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
-	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
-	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
-
-
-/* ronen - update MPP Control MV64360*/
-#define CONFIG_SYS_MPP_CONTROL_0	0x02222222
-#define CONFIG_SYS_MPP_CONTROL_1	0x11333011
-#define CONFIG_SYS_MPP_CONTROL_2	0x40431111
-#define CONFIG_SYS_MPP_CONTROL_3	0x00000044
-
-/*# define CONFIG_SYS_SERIAL_PORT_MUX	0x00000102	 0=hiZ	1=MPSC0 2=ETH 0 and 2 RMII */
-
-
-# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x2c600000	/* 1111 1001 0000 1111 1100 0000 0000 0000*/
-							/* gpp[31]		gpp[30]		gpp[29]		gpp[28] */
-				/* gpp[27]			gpp[24]*/
-							/* gpp[19:14] */
-
-/* setup new config_value for MV64360 DDR-RAM !! */
-# define CONFIG_SYS_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
-
-#define CONFIG_SYS_DUART_IO		CONFIG_SYS_DEV2_SPACE
-#define CONFIG_SYS_DUART_CHAN		1		/* channel to use for console */
-#define CONFIG_SYS_INIT_CHAN1
-#define CONFIG_SYS_INIT_CHAN2
-
-#define SRAM_BASE		CONFIG_SYS_DEV0_SPACE
-#define SRAM_SIZE		0x00100000		/* 1 MB of sram */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-
-#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-#define CONFIG_EEPRO100			/* ronen - Support for Intel 82557/82559/82559ER chips */
-
-/* PCI MEMORY MAP section */
-#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
-#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
-#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
-
-#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
-#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
-
-/* PCI I/O MAP section */
-#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
-#define CONFIG_SYS_PCI0_IO_SIZE	_16M
-#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
-#define CONFIG_SYS_PCI1_IO_SIZE	_16M
-
-#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI0_IO_SPACE_PCI	(CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
-#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
-#define CONFIG_SYS_PCI1_IO_SPACE_PCI	(CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
-
-#if defined (CONFIG_750CX)
-#define CONFIG_SYS_PCI_IDSEL 0x0
-#else
-#define CONFIG_SYS_PCI_IDSEL 0x30
-#endif
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* init ram */
-#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-
-/* PCI0, PCI1 in one BAT */
-#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* I2C addresses for the two DIMM SPD chips */
-#define DIMM0_I2C_ADDR	0x56
-#define DIMM1_I2C_ADDR	0x54
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
-
-#define CONFIG_SYS_EXTRA_FLASH_DEVICE	DEVICE3 /* extra flash at device 3 */
-#define CONFIG_SYS_EXTRA_FLASH_WIDTH	4	/* 32 bit */
-#define CONFIG_SYS_BOOT_FLASH_WIDTH	1	/* 8 bit */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
-#define CONFIG_SYS_FLASH_CFI		1
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_ADDR	      0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
-/* #define CONFIG_ENV_ADDR	   (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
- */
-
-#define CONFIG_SYS_L2
-
-
-#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
-#define L2_INIT 0
-#else
-
-#define L2_INIT		0
-/*
-#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-*/
-#endif
-
-#define L2_ENABLE	(L2_INIT | L2CR_L2E)
-
-#define CONFIG_SYS_BOARD_ASM_INIT	1
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h
deleted file mode 100644
index abc443499c2..00000000000
--- a/include/configs/DB64460.h
+++ /dev/null
@@ -1,517 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* This define must be before the core.h include */
-#define CONFIG_DB64460		1	/* this is an DB64460 board	*/
-
-#ifndef __ASSEMBLY__
-#include "../board/Marvell/include/core.h"
-#endif
-
-/*-----------------------------------------------------*/
-/*    #include "../board/db64460/local.h"	      */
-#ifndef __LOCAL_H
-#define __LOCAL_H
-
-#define CONFIG_ETHADDR		64:46:00:00:00:01
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		64:46:00:00:00:02
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR		64:46:00:00:00:03
-
-#define CONFIG_ENV_OVERWRITE
-#endif	/* __CONFIG_H */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_74xx			/* we have a 750FX (override local.h) */
-
-#define CONFIG_DB64460		1	/* this is an DB64460 board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115000	*/
-/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
-	DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
-	so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
-	see sdram_init.c   */
-#undef CONFIG_ECC	 /* enable ECC support */
-#define CONFIG_MV64460_ECC
-
-/* which initialization functions to call for this board */
-#define CONFIG_MISC_INIT_R     /* initialize the icache L1 */
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_SYS_BOARD_NAME		"DB64460"
-#define CONFIG_IDENT_STRING	"Marvell DB64460 (1.0)"
-
-/*#define CONFIG_SYS_HUSH_PARSER */
-#undef CONFIG_SYS_HUSH_PARSER
-
-
-/*
- * The following defines let you select what serial you want to use
- * for your console driver.
- *
- * what to do:
- * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
- * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
- * to 0 below.
- *
- * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
- * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
- */
-
-#define CONFIG_MPSC_PORT	0
-
-/* to change the default ethernet port, use this define (options: 0, 1, 2) */
-#define MV_ETH_DEVS 3
-
-/* #undef CONFIG_ETHER_PORT_MII	 */
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
-#endif
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-
-#undef	CONFIG_BOOTARGS
-/*#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
-
-/* ronen - autoboot using tftp */
-#if (CONFIG_BOOTDELAY >= 0)
-#define CONFIG_BOOTCOMMAND	"tftpboot 0x400000 uImage;\
- setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
- ip=${ipaddr}:${serverip}${bootargs_end};  bootm 0x400000; "
-
-#define CONFIG_BOOTARGS "console=ttyS0,115200"
-
-#endif
-
-/* ronen - the u-boot.bin should be ~0x30000 bytes */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-     "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
-cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
-      "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
-cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
-      "bootargs_root=root=/dev/nfs rw\0" \
-      "bootargs_end=:::DB64460:eth0:none \0"\
-      "ethprime=mv_enet0\0"\
-      "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
-ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
-
-/* --------------------------------------------------------------------------------------------------------------- */
-/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */
-
-#define CONFIG_IPADDR		10.2.40.90
-
-#define CONFIG_SERIAL		"No. 1"
-#define CONFIG_SERVERIP		10.2.1.126
-#define CONFIG_ROOTPATH		"/mnt/yellow_dog_mini"
-
-
-#define CONFIG_TESTDRAMDATA	y
-#define CONFIG_TESTDRAMADDRESS	n
-#define CONFIG_TESETDRAMWALK	n
-
-/* --------------------------------------------------------------------------------------------------------------- */
-
-#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#undef	CONFIG_ALTIVEC			/* undef to disable		*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nor1"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"nor1=db64460-1"
-#define MTDPARTS_DEFAULT	"mtdparts=db64460-1:-(jffs2)"
-*/
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NET
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_SPEED	40000		/* I2C speed default */
-
-/* #define CONFIG_SYS_GT_DUAL_CPU	 also for JTAG even with one cpu */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-/*#define CONFIG_SYS_MEMTEST_START	0x00400000	 memtest works on	*/
-/*#define CONFIG_SYS_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
-/*#define CONFIG_SYS_MEMTEST_END		0x07c00000	 4 ... 124 MB in DRAM	*/
-
-/*
-#define CONFIG_SYS_DRAM_TEST
- * DRAM tests
- *   CONFIG_SYS_DRAM_TEST - enables the following tests.
- *
- *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
- *			  Environment variable 'test_dram_data' must be
- *			  set to 'y'.
- *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
- *			  addressable. Environment variable
- *			  'test_dram_address' must be set to 'y'.
- *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
- *			  This test takes about 6 minutes to test 64 MB.
- *			  Environment variable 'test_dram_walk' must be
- *			  set to 'y'.
- */
-#define CONFIG_SYS_DRAM_TEST
-#if defined(CONFIG_SYS_DRAM_TEST)
-#define CONFIG_SYS_MEMTEST_START		0x00400000	/* memtest works on	*/
-/* #define CONFIG_SYS_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
-#define CONFIG_SYS_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
-#define CONFIG_SYS_DRAM_TEST_DATA
-#define CONFIG_SYS_DRAM_TEST_ADDRESS
-#define CONFIG_SYS_DRAM_TEST_WALK
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-#undef CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
-#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
-
-#define CONFIG_SYS_LOAD_ADDR		0x00400000	/* default load address */
-
-/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
-#define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
-
-#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
-#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */
-
-/*ronen - this is the Tclk (MV64460 core) */
-#define CONFIG_SYS_TCLK		133000000
-
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_750FX_HID0		0x8000c084
-#define CONFIG_SYS_750FX_HID1		0x54800000
-#define CONFIG_SYS_750FX_HID2		0x00000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/*
- * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
- * To an unused memory region. The stack will remain in cache until RAM
- * is initialized
-*/
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define RELOCATE_INTERNAL_RAM_ADDR
-#ifdef RELOCATE_INTERNAL_RAM_ADDR
-	#define CONFIG_SYS_INTERNAL_RAM_ADDR	0xf8000000
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-/* Dummies for BAT 4-7 */
-#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte */
-#define CONFIG_SYS_SDRAM2_BASE		0x20000000
-#define CONFIG_SYS_SDRAM3_BASE		0x30000000
-#define CONFIG_SYS_SDRAM4_BASE		0x40000000
-#define CONFIG_SYS_FLASH_BASE			0xfff00000
-
-#define CONFIG_SYS_DFL_BOOTCS_BASE	0xff800000
-#define CONFIG_VERY_BIG_RAM		/* we will use up to 256M memory for cause we are short of BATS*/
-
-#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
-#define UART_BASE_BOOTM	      0xfbb00000 /* in order to be sync with the kernel parameters. */
-#define PCI0_IO_BASE_BOOTM    0xfd000000
-
-#define CONFIG_SYS_RESET_ADDRESS		0xfff00100
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
-
-/* areas to map different things with the GT in physical space */
-#define CONFIG_SYS_DRAM_BANKS		4
-
-/* What to put in the bats. */
-#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
-
-/* Peripheral Device section */
-
-/*******************************************************/
-/* We have on the db64460 Board :		   */
-/* GT-Chipset Register Area				*/
-/* GT-Chipset internal SRAM 256k		    */
-/* SRAM on external device module		   */
-/* Real time clock on external device module	  */
-/* dobble UART on external device module	 */
-/* Data flash on external device module		    */
-/* Boot flash on external device module		    */
-/*******************************************************/
-#define CONFIG_SYS_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
-#define	 CONFIG_SYS_DB64460_RESET_ADDR 0x14000000				/* After power on Reset the DB64460 is here */
-
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-#define CONFIG_SYS_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
-#define CONFIG_SYS_DEV_BASE		0xfc000000				/* GT Devices CS start here */
-
-#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE				/* DEV_CS0 device modul sram */
-#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)	/* DEV_CS1 device modul real time clock (rtc) */
-#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)	/* DEV_CS2 device modul doubel uart (duart) */
-#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)	/* DEV_CS3 device modul large flash */
-
-#define CONFIG_SYS_DEV0_SIZE		 _8M					/* db64460 sram	 @ 0xfc00.0000 */
-#define CONFIG_SYS_DEV1_SIZE		 _8M					/* db64460 rtc	 @ 0xfc80.0000 */
-#define CONFIG_SYS_DEV2_SIZE		_16M					/* db64460 duart @ 0xfd00.0000 */
-#define CONFIG_SYS_DEV3_SIZE		_16M					/* db64460 flash @ 0xfe00.0000 */
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-
-/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
-#define CONFIG_SYS_DEV0_PAR		0x8FEFFFFF				/* 32Bit  sram */
-#define CONFIG_SYS_DEV1_PAR		0x8FCFFFFF				/* 8Bit	 rtc */
-#define CONFIG_SYS_DEV2_PAR		0x8FCFFFFF				/* 8Bit duart */
-#define CONFIG_SYS_8BIT_BOOT_PAR	0x8FCFFFFF				/* 8Bit flash */
-#define CONFIG_SYS_32BIT_BOOT_PAR	0x8FEFFFFF				/* 32Bit flash */
-
-	/*   c	  4    a      8	    2	  4    1      c		*/
-	/* 33 22|2222|22 22|111 1|11 11|1 1  |	  |		*/
-	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
-	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
-	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
-
-
-/* ronen - update MPP Control MV64460*/
-#define CONFIG_SYS_MPP_CONTROL_0	0x02222222
-#define CONFIG_SYS_MPP_CONTROL_1	0x11333011
-#define CONFIG_SYS_MPP_CONTROL_2	0x40431111
-#define CONFIG_SYS_MPP_CONTROL_3	0x00000044
-
-/*# define CONFIG_SYS_SERIAL_PORT_MUX	0x00000102	 0=hiZ	1=MPSC0 2=ETH 0 and 2 RMII */
-
-
-# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x2c600000	/* 1111 1001 0000 1111 1100 0000 0000 0000*/
-							/* gpp[31]		gpp[30]		gpp[29]		gpp[28] */
-				/* gpp[27]			gpp[24]*/
-							/* gpp[19:14] */
-
-/* setup new config_value for MV64460 DDR-RAM !! */
-# define CONFIG_SYS_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
-
-#define CONFIG_SYS_DUART_IO		CONFIG_SYS_DEV2_SPACE
-#define CONFIG_SYS_DUART_CHAN		1		/* channel to use for console */
-#define CONFIG_SYS_INIT_CHAN1
-#define CONFIG_SYS_INIT_CHAN2
-
-#define SRAM_BASE		CONFIG_SYS_DEV0_SPACE
-#define SRAM_SIZE		0x00100000		/* 1 MB of sram */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-
-#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-#define CONFIG_EEPRO100			/* ronen - Support for Intel 82557/82559/82559ER chips */
-
-/* PCI MEMORY MAP section */
-#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
-#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
-#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
-
-#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
-#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
-
-/* PCI I/O MAP section */
-#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
-#define CONFIG_SYS_PCI0_IO_SIZE	_16M
-#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
-#define CONFIG_SYS_PCI1_IO_SIZE	_16M
-
-#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI0_IO_SPACE_PCI	(CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
-#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
-#define CONFIG_SYS_PCI1_IO_SPACE_PCI	(CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
-
-#if defined (CONFIG_750CX)
-#define CONFIG_SYS_PCI_IDSEL 0x0
-#else
-#define CONFIG_SYS_PCI_IDSEL 0x30
-#endif
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* init ram */
-#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-
-/* PCI0, PCI1 in one BAT */
-#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* I2C addresses for the two DIMM SPD chips */
-#define DIMM0_I2C_ADDR	0x56
-#define DIMM1_I2C_ADDR	0x54
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
-
-#define CONFIG_SYS_EXTRA_FLASH_DEVICE	DEVICE3 /* extra flash at device 3 */
-#define CONFIG_SYS_EXTRA_FLASH_WIDTH	4	/* 32 bit */
-#define CONFIG_SYS_BOOT_FLASH_WIDTH	1	/* 8 bit */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
-#define CONFIG_SYS_FLASH_CFI		1
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_ADDR	      0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
-/* #define CONFIG_ENV_ADDR	   (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
- */
-
-#define CONFIG_SYS_L2
-
-
-#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
-#define L2_INIT 0
-#else
-
-#define L2_INIT		0
-/*
-#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-*/
-#endif
-
-#define L2_ENABLE	(L2_INIT | L2CR_L2E)
-
-#define CONFIG_SYS_BOARD_ASM_INIT	1
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h
deleted file mode 100644
index 6a3a11cb7f4..00000000000
--- a/include/configs/HWW1U1A.h
+++ /dev/null
@@ -1,460 +0,0 @@
-/*
- * Copyright 2009-2010 eXMeritus, A Boeing Company
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * HardwareWall HWW-1U-1A airborne unit configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High-level system configuration options */
-#define CONFIG_BOOKE		/* Power/PowerPC Book-E			*/
-#define CONFIG_E500		/* e500 (Power ISA v2.03 with SPE)	*/
-#define CONFIG_FSL_ELBC		/* FreeScale Enhanced LocalBus Cntlr	*/
-#define CONFIG_FSL_LAW		/* FreeScale Local Access Window	*/
-#define CONFIG_P2020		/* FreeScale P2020			*/
-#define CONFIG_HWW1U1A		/* eXMeritus HardwareWall HWW-1U-1A	*/
-#define CONFIG_MP		/* Multiprocessing support		*/
-#define CONFIG_HWCONFIG		/* Use hwconfig from environment	*/
-
-#define CONFIG_L2_CACHE			/* L2 cache enabled		*/
-#define CONFIG_BTB			/* Branch predition enabled	*/
-
-#define CONFIG_PANIC_HANG		/* No board reset on panic	*/
-#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_early_init_r()	*/
-#define CONFIG_CMD_REGINFO		/* Dump various CPU regs	*/
-
-/*
- * Allow the use of 36-bit physical addresses.  Device-trees with 64-bit
- * addresses have known compatibility issues with some existing kernels.
- */
-#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */
-
-/* Reserve plenty of RAM for malloc (we have 2GB+) */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
-
-/* How much L2 cache do we map so we can use it as RAM */
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-/* This is our temporary global data area just above the stack */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/* The stack grows down from the global data area */
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* Enable IRQs and watchdog with a 1000Hz system decrementer */
-#define CONFIG_CMD_IRQ
-
-/* -------------------------------------------------------------------- */
-
-/*
- * Clock crystal configuration:
- *  (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR)
- *  (2) CCB: Multiplier from SYS_CLK
- *  (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock)
- */
-#define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/
-#define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/
-
-
-/* -------------------------------------------------------------------- */
-
-/*
- * Memory map
- *
- * 0x0000_0000  0x7fff_ffff    2G  DDR2 ECC SDRAM
- * 0x8000_0000  0x9fff_ffff  512M  PCI-E Bus 1
- * 0xa000_0000  0xbfff_ffff  512M  PCI-E Bus 2 (unused)
- * 0xc000_0000  0xdfff_ffff  512M  PCI-E Bus 3
- * 0xe000_0000  0xe7ff_ffff  128M  Spansion FLASH
- * 0xe800_0000  0xefff_ffff  128M  Spansion FLASH
- * 0xffd0_0000  0xffd0_3fff   16K  L1 boot stack (TLB0)
- * 0xffe0_0000  0xffef_ffff    1M  CCSR
- * 0xffe0_5000  0xffe0_5fff    4K    Enhanced LocalBus Controller
- */
-
-/* Virtual Memory Map */
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
-#define CONFIG_SYS_FLASH_BASE		0xe0000000
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
-#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
-#define CONFIG_SYS_CCSRBAR		0xffe00000 /* CCSRBAR @ runtime */
-
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000 /* 64k */
-
-/* Physical Memory Map */
-#define CONFIG_SYS_PCIE3_MEM_PHYS     0xc00000000ull
-#define CONFIG_SYS_PCIE2_MEM_PHYS     0xc20000000ull
-#define CONFIG_SYS_PCIE1_MEM_PHYS     0xc40000000ull
-#define CONFIG_SYS_FLASH_BASE_PHYS    0xfe0000000ull
-#define CONFIG_SYS_PCIE3_IO_PHYS      0xfffc00000ull
-#define CONFIG_SYS_PCIE2_IO_PHYS      0xfffc10000ull
-#define CONFIG_SYS_PCIE1_IO_PHYS      0xfffc20000ull
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfffd00000ull
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf		/* for ASM code */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xffd00000	/* for ASM code */
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH       0xf		/* for ASM code */
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW        0xffe00000	/* for ASM code */
-
-
-/* -------------------------------------------------------------------- */
-
-/* U-Boot image (MONITOR_BASE == TEXT_BASE) */
-#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc /* Top address in flash */
-#define CONFIG_SYS_TEXT_BASE		0xeff80000 /* Start of U-Boot image */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		0x80000 /* 512kB (4 flash sectors) */
-
-/*
- * U-Boot Environment Image:  The two sectors immediately below U-Boot
- * form the U-Boot environment (regular and redundant).
- */
-#define CONFIG_ENV_IS_IN_FLASH	/* The environment image is stored in FLASH */
-#define CONFIG_ENV_OVERWRITE	/* Allow "protected" variables to be erased */
-#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128kB (1 flash sector) */
-#define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR         - CONFIG_ENV_SECT_SIZE)
-
-/* Only use 8kB of each environment sector for data */
-#define CONFIG_ENV_SIZE		0x2000 /* 8kB */
-#define CONFIG_ENV_SIZE_REDUND	0x2000 /* 8kB */
-
-
-/* -------------------------------------------------------------------- */
-
-/* Serial Console Configuration */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
-
-/* Echo back characters received during a serial download */
-#define CONFIG_LOADS_ECHO
-
-/* Allow a serial-download to temporarily change baud */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-
-/* -------------------------------------------------------------------- */
-
-/* PCI and PCI-Express Support */
-#define CONFIG_PCI		/* Enable PCI/PCIE			*/
-#define CONFIG_PCI_PNP		/* Scan PCI busses			*/
-#define CONFIG_CMD_PCI		/* Enable the "pci" command		*/
-#define CONFIG_FSL_PCI_INIT	/* Common FreeScale PCI initialization	*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET	/* We have PCI-E reset errata		*/
-#define CONFIG_SYS_PCI_64BIT	/* PCI resources are 64-bit		*/
-#define CONFIG_PCI_SCAN_SHOW	/* Display PCI scan during boot		*/
-
-/* Enable 2 of the 3 PCI-E controllers */
-#define CONFIG_PCIE3
-#undef  CONFIG_PCIE2
-#define CONFIG_PCIE1
-
-/* Display human-readable names when initializing */
-#define CONFIG_SYS_PCIE3_NAME "Intel 82571EB"
-#define CONFIG_SYS_PCIE2_NAME "Unused"
-#define CONFIG_SYS_PCIE1_NAME "Silicon Image SIL3531"
-
-/*
- * PCI bus addresses
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_SYS_PCIE3_IO_BUS  0x00000000
-#define CONFIG_SYS_PCIE2_IO_BUS  0x00000000
-#define CONFIG_SYS_PCIE1_IO_BUS  0x00000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-
-
-/* -------------------------------------------------------------------- */
-
-/* Generic FreeScale hardware I2C support */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
-#define CONFIG_CMD_I2C
-
-/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x51
-
-/* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */
-#define CONFIG_CMD_DATE
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_RTC_BUS_NUM 0
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-/* Turn off RTC square-wave output to save battery */
-#define CONFIG_SYS_RTC_DS1337_NOOSC
-
-/*
- * AT24C128N EEPROM at I2C0-0x53.
- *
- * That Atmel EEPROM has 128kbit of memory (16kByte) divided into 256 pages
- * of 64 bytes per page.  The chip uses 2-byte addresses and has a max write
- * cycle time of 20ms according to the datasheet.
- *
- * NOTE: Our environment is stored on regular direct-attached FLASH, this
- * chip is only used as a write-protected backup for certain key settings
- * such as the serial# and macaddr values.  (EG: "env import")
- */
-#define CONFIG_CMD_EEPROM
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 1 << 6 == 64 byte pages */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 21
-
-/*
- * PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554).  You
- * must first select the I2C1 bus with "i2c dev 1" or the "pca953x" command
- * will not be able to access the chip.
- */
-#define CONFIG_PCA953X
-#define CONFIG_CMD_PCA953X
-#define CONFIG_CMD_PCA953X_INFO
-#define CONFIG_SYS_I2C_PCA953X_ADDR 0x3f
-
-
-/* -------------------------------------------------------------------- */
-
-/* FreeScale DDR2/3 SDRAM Controller */
-#define CONFIG_SYS_FSL_DDR2		/* Our SDRAM slot is DDR2		*/
-#define CONFIG_DDR_ECC		/* Enable ECC by default		*/
-#define CONFIG_DDR_SPD		/* Detect DDR config from SPD EEPROM	*/
-#define CONFIG_SPD_EEPROM	/* ...why 2 config variables for this?	*/
-#define CONFIG_VERY_BIG_RAM	/* Allow 2GB+ of RAM			*/
-#define CONFIG_CMD_SDRAM
-
-/* Standard P2020 DDR controller parameters */
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/* Make sure to tell the DDR controller to preinitialze all of RAM */
-#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-
-
-/* -------------------------------------------------------------------- */
-
-/* FLASH Memory Configuration (2x 128MB SPANSION FLASH) */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-
-/* Flash banks (2x 128MB) */
-#define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull)
-#define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull)
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_SYS_MAX_FLASH_SECT 1024
-#define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS }
-
-/*
- * Flash access modes and timings (values are the defaults after a RESET).
- *
- * NOTE: These could probably be optimized but are more than sufficient for
- * this particular system for the moment.
- */
-#define FLASH_BRx (BR_PS_16 | BR_MS_GPCM | BR_V)
-#define FLASH_ORx (OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
-		| OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
-
-/* Configure both flash banks */
-#define CONFIG_SYS_BR0_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH0_PHYS))
-#define CONFIG_SYS_BR1_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH1_PHYS))
-#define CONFIG_SYS_OR0_PRELIM (FLASH_ORx | OR_AM_128MB)
-#define CONFIG_SYS_OR1_PRELIM (FLASH_ORx | OR_AM_128MB)
-
-/* Flash timeouts (in ms) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT   500UL /* Write (0.5s)	*/
-
-/* Quiet flash testing */
-#define CONFIG_SYS_FLASH_QUIET_TEST
-
-/* Make program/erase count down from 45/5 (9....8....7....) */
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-
-
-/* -------------------------------------------------------------------- */
-
-/* Ethernet Device Support */
-#define CONFIG_MII			/* Enable MII PHY code		*/
-#define CONFIG_MII_DEFAULT_TSEC		/* ??? Copied from P2020DS	*/
-#define CONFIG_PHY_GIGE			/* Support Gigabit PHYs		*/
-#define CONFIG_ETHPRIME "e1000#0"	/* Default to external ports	*/
-
-/* Turn on various helpful networking commands */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-
-/* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */
-#define CONFIG_TSEC_ENET
-#define CONFIG_TSEC1
-#define CONFIG_TSEC2
-#define CONFIG_TSEC3
-#define CONFIG_TSEC1_NAME "owt0"
-#define CONFIG_TSEC2_NAME "owt1"
-#define CONFIG_TSEC3_NAME "peer"
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-#define TSEC1_PHY_ADDR      2
-#define TSEC2_PHY_ADDR      3
-#define TSEC3_PHY_ADDR      4
-#define TSEC3_PHY_ADDR_CPUA 4
-#define TSEC3_PHY_ADDR_CPUB 5
-
-/* PCI-E dual-port E1000 (external ethernet ports) */
-#define CONFIG_E1000
-#define CONFIG_E1000_SPI
-#define CONFIG_E1000_SPI_GENERIC
-#define CONFIG_CMD_E1000
-
-/* We need the SPI infrastructure to poke the E1000's EEPROM */
-#define CONFIG_SPI
-#define CONFIG_SPI_X
-#define CONFIG_CMD_SPI
-#define MAX_SPI_BYTES 32
-
-
-/* -------------------------------------------------------------------- */
-
-/* USB Thumbdrive Device Support */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_USB_STORAGE
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_USB
-
-/* Partition and Filesystem support */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_ISO_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-
-
-/* -------------------------------------------------------------------- */
-
-/* Command line configuration. */
-#define CONFIG_CMDLINE_EDITING		/* Enable command editing	*/
-#define CONFIG_COMMAND_HISTORY		/* Enable command history	*/
-#define CONFIG_AUTO_COMPLETE		/* Enable command completion	*/
-#define CONFIG_SYS_LONGHELP		/* Enable detailed command help	*/
-#define CONFIG_SYS_MAXARGS 128		/* Up to 128 command-line args	*/
-#define CONFIG_SYS_PBSIZE 8192		/* Allow up to 8k printed lines	*/
-#define CONFIG_SYS_CBSIZE 4096		/* Allow up to 4k command lines	*/
-#define CONFIG_SYS_BARGSIZE 4096	/* Allow up to 4k boot args	*/
-#define CONFIG_SYS_HUSH_PARSER		/* Enable a fancier shell	*/
-
-/* A little extra magic here for the prompt */
-#define CONFIG_SYS_PROMPT hww1u1a_get_ps1()
-#ifndef __ASSEMBLY__
-const char *hww1u1a_get_ps1(void);
-#endif
-
-/* Include a bunch of default commands we probably want */
-#include <config_cmd_default.h>
-
-/* Other helpful shell-like commands */
-#define CONFIG_MD5
-#define CONFIG_SHA1
-#define CONFIG_CMD_MD5SUM
-#define CONFIG_CMD_SHA1SUM
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_SETEXPR
-
-
-/* -------------------------------------------------------------------- */
-
-/* Image manipulation and booting */
-
-/* We use the OpenFirmware-esque "Flattened Device Tree" */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMD_ELF
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20)	/* Maximum kernel memory map	*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20)	/* Maximum kernel size of 64MB	*/
-
-/* This is the default address for commands with an optional address arg */
-#define CONFIG_LOADADDR		  100000
-#define CONFIG_SYS_LOAD_ADDR	0x100000
-
-/* Test memory starting from the default load address to just below 2GB */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_LOAD_ADDR
-#define CONFIG_SYS_MEMTEST_END		0x7f000000
-
-#define CONFIG_BOOTDELAY 20
-#define CONFIG_BOOTCOMMAND "echo Not yet flashed"
-#define CONFIG_BOOTARGS ""
-#define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1"
-
-/* Extra environment parameters */
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"ethprime=e1000#0\0"						\
-	"ethrotate=no\0"						\
-	"setbootargs=setenv bootargs "					\
-			"\"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0"	\
-	"perf_mode=performance\0"					\
-	"hwconfig="	"fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;"	\
-			"usb1:dr_mode=host,phy_type=ulpi\0"		\
-	"flkernel=0xe8000000\0"						\
-	"flinitramfs=0xe8800000\0"					\
-	"fldevicetree=0xeff20000\0"					\
-	"flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0"	\
-	"flboot=run preboot; run flbootm\0"				\
-	"restore_eeprom=i2c dev 0 && "					\
-			"eeprom read $loadaddr 0x0000 0x2000 && "	\
-			"env import -c $loadaddr 0x2000\0"
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h
deleted file mode 100644
index 16af4bbcadf..00000000000
--- a/include/configs/ICU862.h
+++ /dev/null
@@ -1,443 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <mpc8xx_irq.h>
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC860		1
-#define CONFIG_MPC860T		1
-#define CONFIG_ICU862		1
-#define CONFIG_MPC862		1
-
-#define	CONFIG_SYS_TEXT_BASE	0x40F00000
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-
-#ifdef CONFIG_100MHz
-#define MPC8XX_FACT		24		/* Multiply by 24	*/
-#define MPC8XX_XIN		4165000		/* 4.165 MHz in		*/
-#define CONFIG_8xx_GCLK_FREQ	(MPC8XX_FACT * MPC8XX_XIN)
-				    /* define if cant' use get_gclk_freq */
-#else
-#if 1				/* for 50MHz version of processor	*/
-#define MPC8XX_FACT		12		/* Multiply by 12	*/
-#define MPC8XX_XIN		4000000		/* 4 MHz in		*/
-#define CONFIG_8xx_GCLK_FREQ	48000000 /* define if cant use get_gclk_freq */
-#else				/* for 80MHz version of processor	*/
-#define MPC8XX_FACT		20		/* Multiply by 20	*/
-#define MPC8XX_XIN		4000000		/* 4 MHz in		*/
-#define CONFIG_8xx_GCLK_FREQ    80000000 /* define if cant use get_gclk_freq */
-#endif
-#endif
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp;"								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
-	"bootm"
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#undef	CONFIG_SCC1_ENET		/* disable SCC1 ethernet */
-#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
-#define	CONFIG_MII		1
-#if 1
-#define CONFIG_SYS_DISCOVER_PHY	1
-#else
-#undef	CONFIG_SYS_DISCOVER_PHY
-#endif
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL		0x00000020	/* PB 26 */
-#define PB_SDA		0x00000010	/* PB 27 */
-
-#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
-#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
-#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#define CONFIG_SYS_EEPROM_X40430		/* Use a Xicor X40430 EEPROM	*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS  4	/* 16 bytes page write mode	*/
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x00100000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xF0000000
-#define CONFIG_SYS_IMMR_SIZE		((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define	CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0x40000000
-#define CONFIG_SYS_FLASH_SIZE		((uint)(16 * 1024 * 1024))	/* max 16Mbyte */
-
-#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
-
-#if 0
-#if defined(DEBUG)
-#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#else
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
-
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET		0x00F40000
-
-#define CONFIG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment sector	*/
-#define	CONFIG_ENV_SIZE		0x4000	/* Used Size of Environment Sector	*/
-#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control					11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration					11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control					11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
- *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control (15-29)
- */
-#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
-				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#ifdef CONFIG_100MHz	/* for 100 MHz, external bus is half CPU clock */
-#define SCCR_MASK	0
-#define CONFIG_SYS_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
-			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
-			 SCCR_DFLCD000	|SCCR_DFALCD00	| SCCR_EBDF01)
-#else			/* up to 50 MHz we use a 1:1 clock */
-#define SCCR_MASK	SCCR_EBDF11
-#define CONFIG_SYS_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
-			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
-			 SCCR_DFLCD000	|SCCR_DFALCD00	)
-#endif	/* CONFIG_100MHz */
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register		19-4
- *-----------------------------------------------------------------------
- */
-/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
-#define CONFIG_SYS_RCCR 0x0020
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * PCMCIA Power Switch
- *
- * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to
- * control the voltages on the PCMCIA slot which is connected to Port B
- *-----------------------------------------------------------------------
- */
-			/* Output pins */
-#define TPS2205_VCC5	0x00008000	/* PB.16:  5V Voltage Control	*/
-#define TPS2205_VCC3	0x00004000	/* PB.17:  3V Voltage Control	*/
-#define TPS2205_VPP_PGM	0x00002000	/* PB.18: PGM Voltage Control	*/
-#define TPS2205_VPP_VCC	0x00001000	/* PB.19: VPP Voltage Control	*/
-#define TPS2205_SHDN	0x00000200	/* PB.22: Shutdown		*/
-#define TPS2205_OUTPUTS ( TPS2205_VCC5    | TPS2205_VCC3    | \
-			  TPS2205_VPP_PGM | TPS2205_VPP_VCC | \
-			  TPS2205_SHDN)
-
-			/* Input pins */
-#define TPS2205_OC	0x00000100	/* PB.23: Over-Current		*/
-#define TPS2205_INPUTS	( TPS2205_OC )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
-#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
-
-
- /*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER		0
-
-/* Because of the way the 860 starts up and assigns CS0 the
-* entire address space, we have to set the memory controller
-* differently.  Normally, you write the option register
-* first, and then enable the chip select by writing the
-* base register.  For CS0, you must write the base register
-* first, followed by the option register.
-*/
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0x0		/* FLASH bank #1	*/
-
-#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
-#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-
-#define CONFIG_SYS_OR0_PRELIM	0xFF000954		/* Real values for the board */
-#define CONFIG_SYS_BR0_PRELIM	0x40000001		/* Real values for the board */
-
-/*
- * BR1 and OR1 (SDRAM)
- */
-#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank		*/
-#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000800	/* BIH is not set	*/
-
-#define CONFIG_SYS_OR1_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
-#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA		97	/* start with divider for 100 MHz	*/
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-#define CONFIG_SYS_MAMR		0x13a01114
-
-#ifdef CONFIG_MPC860T
-
-/* Interrupt level assignments.
-*/
-#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
-
-#endif /* CONFIG_MPC860T */
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
deleted file mode 100644
index 8ccb0ff9d89..00000000000
--- a/include/configs/IDS8247.h
+++ /dev/null
@@ -1,462 +0,0 @@
-/*
- * (C) Copyright 2005
- * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8272_FAMILY	1
-#define CONFIG_IDS8247		1
-#define CPU_ID_STR		"MPC8247"
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define	CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw "			\
-	"console=ttyS0,115200\0"					\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_82xx\0"					\
-	"bootfile=/tftpboot/IDS8247/uImage\0"				\
-	"kernel_addr=ff800000\0"					\
-	"ramdisk_addr=ffa00000\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_MISC_INIT_R	1
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
-/*
- * Software (bit-bang) I2C driver configuration
- */
-
-#define I2C_PORT	0		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00000080)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00000080)
-#define I2C_READ	((iop->pdat & 0x00000080) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00000080; \
-			else    iop->pdat &= ~0x00000080
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00000100; \
-			else    iop->pdat &= ~0x00000100
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#if 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CONFIG_I2C_X
-#endif
-
-/*
- * select serial console configuration
- * use the extern UART for the console
- */
-#define	CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		115200
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE    1
-
-#define CONFIG_SYS_NS16550_CLK         14745600
-
-#define	CONFIG_SYS_UART_BASE	0xE0000000
-#define CONFIG_SYS_UART_SIZE	0x10000
-
-#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_UART_BASE + 0x8000)
-
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
-#define OF_TBCLK	(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH	"/soc@f0000000/serial8250@e0008000"
-
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define	CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
-#define CONFIG_ETHER_ON_FCC1
-#define FCC_ENET
-
-/*
- * - Rx-CLK is CLK10
- * - Tx-CLK is CLK9
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN	66666666	/* in Hz */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR		0x51
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
-
-#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
-#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ 0xFF800000 }
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CONFIG_SYS_FLASH0_BASE 0xFFF00000
-#define CONFIG_SYS_FLASH0_SIZE 8
-
-/* Flash bank size (for preliminary settings)
- */
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-/* Environment in flash */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x60000)
-#define CONFIG_ENV_SIZE		0x20000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_NAND)
-
-#define CONFIG_SYS_NAND0_BASE 0xE1000000
-#define CONFIG_SYS_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
-
-#endif /* CONFIG_CMD_NAND */
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1		0
-#define CONFIG_SYS_HRCW_SLAVE2		0
-#define CONFIG_SYS_HRCW_SLAVE3		0
-#define CONFIG_SYS_HRCW_SLAVE4		0
-#define CONFIG_SYS_HRCW_SLAVE5		0
-#define CONFIG_SYS_HRCW_SLAVE6		0
-#define CONFIG_SYS_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2000  /* Size of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers                    2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-
-#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
-#define CONFIG_SYS_HID0_FINAL  0
-#define CONFIG_SYS_HID2        0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register                                     5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR         0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                                       4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR		0
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                             4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                             4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control                     4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control                 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                                   9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR        (0x00000028 | SCCR_DFBRG01)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                         13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR        0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus     Machine PortSz  Device
- * ---- ---     ------- ------  ------
- *  0   60x     GPCM    16 bit  FLASH
- *  1   60x     GPCM     8 bit  NAND
- *  2   60x     SDRAM   32 bit  SDRAM
- *  3   60x     GPCM     8 bit  UART
- *
- */
-
-#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(32<<20)	/* less than 32 MB */
-
-#define CONFIG_SYS_MPTPR       0x6600
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_MRS_OFFS	0x00000110
-
-
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_8                       |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
-			 ORxG_SCY_6_CLK                 )
-
-#if defined(CONFIG_CMD_NAND)
-/* Bank 1 - NAND Flash
-*/
-#define	CONFIG_SYS_NAND_BASE		CONFIG_SYS_NAND0_BASE
-#define	CONFIG_SYS_NAND_SIZE		0x8000
-
-#define CONFIG_SYS_OR_TIMING_NAND	0x000036
-
-#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
-#define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND )
-#endif
-
-/* Bank 2 - 60x bus SDRAM
- */
-#define CONFIG_SYS_PSRT        0x20
-#define CONFIG_SYS_LSRT        0x20
-
-#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_32                      |\
-			 BRx_MS_SDRAM_P                 |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_OR2
-
-
-/* SDRAM initialization values
-*/
-#define CONFIG_SYS_OR2    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI0_A9		|\
-			 ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR  (PSDMR_SDAM_A14_IS_A5 |\
-			 PSDMR_BSMA_A15_A17           |\
-			 PSDMR_SDA10_PBI0_A10		|\
-			 PSDMR_RFRC_5_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_BL                       |\
-			 PSDMR_LDOTOPRE_2C              |\
-			 PSDMR_WRC_3C                   |\
-			 PSDMR_CL_3)
-
-/* Bank 3 - UART
-*/
-
-#define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
-#define CONFIG_SYS_OR3_PRELIM  (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h
deleted file mode 100644
index d45be0f609a..00000000000
--- a/include/configs/MHPC.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * (C) Copyright 2001
- * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Configuation settings for the miniHiPerCam.
- *
- * -----------------------------------------------------------------
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
-#define CONFIG_MHPC		1	/* on a miniHiPerCam		*/
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* do special hardware init.	*/
-#define CONFIG_MISC_INIT_R	1
-
-#define	CONFIG_SYS_TEXT_BASE	0xfe000000
-
-#define CONFIG_8xx_GCLK_FREQ	MPC8XX_SPEED
-#undef	CONFIG_8xx_CONS_SMC1
-#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_ENV_OVERWRITE	1
-#define CONFIG_ETHADDR		00:00:5b:ee:de:ad
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND	\
-	"bootp;"								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#define CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#undef	CONFIG_UCODE_PATCH
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL		0x00000020	/* PB 26 */
-#define PB_SDA		0x00000010	/* PB 27 */
-
-#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
-#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
-#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* EEPROM X24C04		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-
-#define LCD_VIDEO_ADDR		(SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
-#define LCD_VIDEO_SIZE		SDRAM_RES_SIZE	/* 2MB */
-#define LCD_VIDEO_COLS		640
-#define LCD_VIDEO_ROWS		480
-#define LCD_VIDEO_FG		255
-#define LCD_VIDEO_BG		0
-
-#undef	CONFIG_VIDEO				/* test only ! s.a devices.c and 8xx */
-#define CONFIG_CFB_CONSOLE			/* framebuffer console with std input */
-#define CONFIG_VIDEO_LOGO
-
-#define VIDEO_KBD_INIT_FCT	0		/* no KBD dev on MHPC - use serial */
-#define VIDEO_TSTC_FCT		serial_stub_tstc
-#define VIDEO_GETC_FCT		serial_stub_getc
-
-#define CONFIG_BR0_WORKAROUND	1
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_REGINFO
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x300000	/* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Physical memory map
- */
-#define CONFIG_SYS_IMMR		0xFFF00000 /* Internal Memory Mapped Register*/
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xfe000000
-
-#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256 kB for Monitor	*/
-#undef	CONFIG_SYS_MONITOR_BASE		    /* to run U-Boot from RAM */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"nor0=mhpc-0"
-#define MTDPARTS_DEFAULT	"mtdparts=mhpc-0:-(jffs2)"
-*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map- for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET		CONFIG_SYS_MONITOR_LEN /* Offset of Environment */
-#define CONFIG_ENV_SIZE		0x20000 /* Total Size of Environment	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_SEME)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		12-18
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define MPC8XX_SPEED	50000000L
-#define MPC8XX_XIN	5000000L      /* ref clk */
-#define MPC8XX_FACT	(MPC8XX_SPEED/MPC8XX_XIN)
-#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
-			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-
-#define SCCR_MASK	(SCCR_RTDIV | SCCR_RTSEL)     /* SCCR_EBDF11 */
-#define CONFIG_SYS_SCCR	(SCCR_TBS | SCCR_DFLCD001)
-
-
-/*-----------------------------------------------------------------------
- * MAMR settings for SDRAM	- 16-14
- * => 0xC080200F
- *-----------------------------------------------------------------------
- * periodic timer for refresh
- */
-#define CONFIG_SYS_MAMR_PTA	0xC0
-#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
-
-/*
- * BR0 and OR0 (FLASH) used to re-map FLASH
- */
-
-/* allow for max 8 MB of Flash */
-#define FLASH_BASE		0xFE000000	/* FLASH bank #0*/
-#define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0*/
-#define CONFIG_SYS_REMAP_OR_AM		0xFF800000	/* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
-
-#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
-
-#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
-
-/*
- * BR1 and OR1 (SDRAM)
- */
-#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define SDRAM_MAX_SIZE		0x01000000	/* max 16 MB		*/
-#define SDRAM_RES_SIZE		0x00200000	/* 2 MB for framebuffer */
-
-/* SDRAM timing: drive GPL5 high on first cycle */
-#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_G5LS)
-
-#define CONFIG_SYS_OR1_PRELIM	((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR2/OR2 - DIMM
- */
-#define CONFIG_SYS_OR2		(OR_ACS_DIV4)
-#define CONFIG_SYS_BR2		(BR_MS_UPMA)
-
-/*
- * BR3/OR3 - DIMM
- */
-#define CONFIG_SYS_OR3		(OR_ACS_DIV4)
-#define CONFIG_SYS_BR3		(BR_MS_UPMA)
-
-/*
- * BR4/OR4
- */
-#define CONFIG_SYS_OR4		0
-#define CONFIG_SYS_BR4		0
-
-/*
- * BR5/OR5
- */
-#define CONFIG_SYS_OR5		0
-#define CONFIG_SYS_BR5		0
-
-/*
- * BR6/OR6
- */
-#define CONFIG_SYS_OR6		0
-#define CONFIG_SYS_BR6		0
-
-/*
- * BR7/OR7
- */
-#define CONFIG_SYS_OR7		0
-#define CONFIG_SYS_BR7		0
-
-
-/*-----------------------------------------------------------------------
- * Debug Entry Mode
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index a373990e5d0..d378dbd1a1e 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -53,7 +53,7 @@
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_RAMBOOT_SPIFLASH
 #define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
 #else
 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
@@ -170,6 +170,7 @@
 #define CONFIG_BOOKE			/* BOOKE */
 #define CONFIG_E500			/* BOOKE e500 family */
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
 
 #define CONFIG_PCI			/* Enable PCI/PCIE */
@@ -832,6 +833,12 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_DOS_PARTITION
 #endif
 
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 /*
  * Miscellaneous configurable options
  */
@@ -956,4 +963,8 @@ extern unsigned long get_sdram_size(void);
 
 #include <asm/fsl_secure_boot.h>
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 16f7525def4..2e11aaa13cd 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -49,6 +49,7 @@
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
 #define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
 #define CONFIG_PCIE1			/* PCIE controler 1 */
 #define CONFIG_PCIE2			/* PCIE controler 2 */
@@ -647,6 +648,12 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_DOS_PARTITION
 #endif
 
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 /*
  * Miscellaneous configurable options
  */
@@ -743,4 +750,8 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 
 #include <asm/fsl_secure_boot.h>
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index c5e2f164ce0..c29429d368a 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -29,6 +29,9 @@
 #define CONFIG_SYS_TEXT_BASE	0xFFF90000
 #endif
 
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
 #define CONFIG_SYS_CLK_FREQ	33333400
 
 #if 0 /* temporary disabled because OS/9 does not like dcache on startup */
@@ -133,6 +136,7 @@
 #endif
 
 #ifdef CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_I2C_ENV_EEPROM_BUS	0
 #define CONFIG_ENV_OFFSET		0	/* environment starts at the beginning of the EEPROM */
 #define CONFIG_ENV_SIZE		0x1000	/* 4096 bytes may be used for env vars */
 #endif
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index a781ba327a2..1d0664ddf6e 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -58,6 +58,7 @@
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCIE1			/* PCIE controler 1 */
@@ -716,6 +717,12 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_NET
 #endif
 
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 /*
  * Miscellaneous configurable options
  */
@@ -818,6 +825,7 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_SECURE_BOOT
 #include <asm/fsl_secure_boot.h>
+#define CONFIG_CMD_BLOB
 #endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 5e2c100d930..2bb86e40caf 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -113,6 +113,7 @@
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCIE1			/* PCIE controler 1 */
@@ -731,6 +732,12 @@
 #define CONFIG_CMD_NET
 #endif
 
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 /*
  * Miscellaneous configurable options
  */
@@ -865,6 +872,7 @@
 
 #ifdef CONFIG_SECURE_BOOT
 #include <asm/fsl_secure_boot.h>
+#define CONFIG_CMD_BLOB
 #endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 395472be2bc..27333589afe 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -44,6 +44,7 @@
 #define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC	CONFIG_NUM_DDR_CONTROLLERS
 #define CONFIG_FSL_IFC		/* Enable IFC Support */
+#define CONFIG_FSL_CAAM		/* Enable SEC/CAAM */
 #define CONFIG_FSL_LAW		/* Use common FSL init code */
 #define CONFIG_ENV_OVERWRITE
 
@@ -777,6 +778,12 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_NET
 #endif
 
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 /*
  * Miscellaneous configurable options
  */
@@ -909,6 +916,7 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_SECURE_BOOT
 #include <asm/fsl_secure_boot.h>
+#define CONFIG_CMD_BLOB
 #undef CONFIG_CMD_USB
 #endif
 
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index e5936c78176..400d979643c 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -37,6 +37,7 @@
 #define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC	CONFIG_NUM_DDR_CONTROLLERS
 #define CONFIG_FSL_IFC		/* Enable IFC Support */
+#define CONFIG_FSL_CAAM		/* Enable SEC/CAAM */
 #define CONFIG_FSL_LAW		/* Use common FSL init code */
 #define CONFIG_ENV_OVERWRITE
 
@@ -736,6 +737,12 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_NET
 #endif
 
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 /*
  * Miscellaneous configurable options
  */
@@ -868,6 +875,7 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_SECURE_BOOT
 #include <asm/fsl_secure_boot.h>
+#define CONFIG_CMD_BLOB
 #undef CONFIG_CMD_USB
 #endif
 
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index ca9724720d9..1e0f5ece092 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -15,6 +15,7 @@
 
 #define CONFIG_FSL_SATA_V2
 #define CONFIG_PCIE4
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 
 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
 
@@ -506,6 +507,12 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
 #endif
 
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 /*
 * USB
 */
@@ -625,4 +632,8 @@ unsigned long get_board_ddr_clk(void);
 
 #include <asm/fsl_secure_boot.h>
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 183255d2831..13f4bd3c539 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -47,6 +47,7 @@
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
 #define CONFIG_PCIE1			/* PCIE controler 1 */
 #define CONFIG_PCIE2			/* PCIE controler 2 */
@@ -668,6 +669,12 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_DOS_PARTITION
 #endif
 
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 #define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define __USB_PHY_TYPE	utmi
@@ -751,6 +758,7 @@ unsigned long get_board_ddr_clk(void);
  * which is anyways not used in Secure Environment.
  */
 #undef CONFIG_CMD_USB
+#define CONFIG_CMD_BLOB
 #endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
deleted file mode 100644
index 92128b95884..00000000000
--- a/include/configs/TOP5200.h
+++ /dev/null
@@ -1,402 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
- *
- * TOP5200 differences from IceCube:
- * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
- *   bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
- * 1 SDRAM/DDRAM Bank up to 256 MB
- * local VPD I2C Bus is software driven and uses
- *   GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
- * FLASH is re-located at 0xff000000
- * Internal regs are at 0xf0000000
- * Reset jumps to 0x00000100
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
-#define CONFIG_TOP5200		1	/* ... on TOP5200 board - we need this for FEC.C */
-
-/*
- * allowed and functional CONFIG_SYS_TEXT_BASE values:
- * 0xff000000	low boot at 0x00000100 (default board setting)
- * 0xfff00000	high boot at 0xfff00100 (board needs modification)
- * 0x00100000	RAM load and test
- */
-#define	CONFIG_SYS_TEXT_BASE	0xff000000
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-
-#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#  define CONFIG_PCI		1
-#  define CONFIG_PCI_PNP		1
-#  define CONFIG_PCI_SCAN_SHOW	1
-#  define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-
-#  define CONFIG_PCI_MEM_BUS	0x40000000
-#  define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#  define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#  define CONFIG_PCI_IO_BUS	0x50000000
-#  define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#  define CONFIG_PCI_IO_SIZE	0x01000000
-
-#endif
-
-/* USB */
-#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
-
-#  define CONFIG_USB_OHCI
-#  define CONFIG_USB_CLOCK	0x0001bbbb
-#  if defined (CONFIG_EVAL5200)
-#    define CONFIG_USB_CONFIG	0x00005100
-#  else
-#    define CONFIG_USB_CONFIG	0x00001000
-#  endif
-#  define CONFIG_DOS_PARTITION
-#  define CONFIG_USB_STORAGE
-
-#endif
-
-/* IDE */
-#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
-#  define CONFIG_DOS_PARTITION
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_REGINFO
-
-#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_PCI
-#endif
-
-
-/*
- * MUST be low boot - HIGHBOOT is not supported anymore
- */
-#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
-#   define CONFIG_SYS_LOWBOOT		1
-#   define CONFIG_SYS_LOWBOOT16	1
-#else
-#   error "CONFIG_SYS_TEXT_BASE must be 0xff000000"
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_82xx\0"					\
-	"bootfile=/tftpboot/MPC5200/uImage\0"				\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-
-/*
- * I2C configuration
- */
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_SIZE 0x2000
-
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-
-#if defined(CONFIG_SYS_I2C_SOFT)
-#  define CONFIG_SYS_I2C
-#  define CONFIG_SYS_I2C_SOFT_SPEED	100000
-#  define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
-/**/
-#  define SDA0			0x40
-#  define SCL0			0x80
-#  define GPIOE0		*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00))
-#  define DDR0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08))
-#  define DVO0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c))
-#  define DVI0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20))
-#  define ODE0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04))
-#  define I2C_INIT		{GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
-#  define I2C_READ		((DVI0&SDA0)?1:0)
-#  define I2C_SDA(x)	{if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
-#  define I2C_SCL(x)	{if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
-#  define I2C_DELAY		{udelay(5);}
-#  define I2C_ACTIVE	{DDR0|=SDA0;}
-#  define I2C_TRISTATE	{DDR0&=~SDA0;}
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_FACT_ADDR	0x57
-#endif
-
-#if defined (CONFIG_HARD_I2C)
-#  define CONFIG_SYS_I2C_MODULE	2		/* Select I2C module #1 or #2 */
-#  define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
-#  define CONFIG_SYS_I2C_SLAVE		0x7F
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
-#define CONFIG_SYS_I2C_FACT_ADDR	0x54
-#endif
-
-/*
- * Flash configuration, expect one 16 Megabyte Bank at most
- */
-#define CONFIG_SYS_FLASH_BASE		0xff000000
-#define CONFIG_SYS_FLASH_SIZE		0x01000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0)
-
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */
-
-/*
- * DRAM configuration - will be read from VPD later... TODO!
- */
-#if 0
-/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
-#define	CONFIG_SYS_DRAM_DDR		0
-#define CONFIG_SYS_DRAM_EMODE		0
-#define CONFIG_SYS_DRAM_MODE		0x008D
-#define CONFIG_SYS_DRAM_CONTROL	0x514F0000
-#define CONFIG_SYS_DRAM_CONFIG1	0xC2233A00
-#define CONFIG_SYS_DRAM_CONFIG2	0x88B70004
-#define	CONFIG_SYS_DRAM_TAP_DEL	0x08
-#define CONFIG_SYS_DRAM_RAM_SIZE	0x19
-#endif
-#if 1
-/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
-#define	CONFIG_SYS_DRAM_DDR		0
-#define CONFIG_SYS_DRAM_EMODE		0
-#define CONFIG_SYS_DRAM_MODE		0x00CD
-#define CONFIG_SYS_DRAM_CONTROL	0x514F0000
-#define CONFIG_SYS_DRAM_CONFIG1	0xD2333A00
-#define CONFIG_SYS_DRAM_CONFIG2	0x8AD70004
-#define	CONFIG_SYS_DRAM_TAP_DEL	0x08
-#define CONFIG_SYS_DRAM_RAM_SIZE	0x19
-#endif
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* turn on EEPROM env feature */
-#define CONFIG_ENV_OFFSET		0x1000
-#define CONFIG_ENV_SIZE		0x0700
-
-/*
- * VPD settings
- */
-#define CONFIG_SYS_FACT_OFFSET		0x1800
-#define CONFIG_SYS_FACT_SIZE		0x0800
-
-/*
- * Memory map
- *
- * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
- */
-#define CONFIG_SYS_MBAR			0xf0000000	/* DO NOT CHANGE this */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII10	/* Workaround for FEC 100Mbit problem */
-#define	CONFIG_PHY_ADDR		0x1f
-#define	CONFIG_PHY_TYPE		0x79c874
-/*
- * GPIO configuration:
- * PSC1,2,3 predefined as UART
- * PCI disabled
- * Ethernet 100 with MD
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058044
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-
-#ifdef CONFIG_EVAL5200		/* M48T08 is available with the Evaluation board only */
-  #define CONFIG_RTC_MK48T59	1	/* use M48T08 on EVAL5200 */
-  #define RTC(reg)		(0xf0010000+reg)
-  /* setup CS2 for M48T08. Must MAP 64kB */
-  #define CONFIG_SYS_CS2_START	RTC(0)
-  #define CONFIG_SYS_CS2_SIZE	0x10000
-  /* setup CS2 configuration register: */
-  /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
-  /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
-  #define CONFIG_SYS_CS2_CFG	0x00047800
-#else
-  #define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047801
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS	0x7f000000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-
-#define CONFIG_IDE_RESET	1
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-
-/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005c)
-
-/* Interval between registers                                                */
-#define CONFIG_SYS_ATA_STRIDE          4
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h
deleted file mode 100644
index da68503a694..00000000000
--- a/include/configs/TOP860.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * (C) Copyright 2003
- * EMK Elektronik GmbH <www.emk-elektronik.de>
- * Reinhard Meyer <r.meyer@emk-elektronik.de>
- *
- * Configuation settings for the TOP860 board.
- *
- * -----------------------------------------------------------------
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/*
- * TOP860 is a simple module:
- * 16-bit wide FLASH on CS0	(2MB or more)
- * 32-bit wide DRAM on CS2 (either 4MB or 16MB)
- * FEC with Am79C874 100-Base-T and Fiber Optic
- * Ports available, but we choose SMC1 for Console
- * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
- * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
- *
- * This config has been copied from MBX.h / MBX860T.h
- */
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/*-----------------------------------------------------------------------
- * CPU and BOARD type
- */
-#define CONFIG_MPC860	1	/* This is a MPC860 CPU		*/
-#define CONFIG_MPC860T	1	/* even better... an FEC!	*/
-#define CONFIG_TOP860	1	/* ...on a TOP860 module	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0x80000000
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#define	CONFIG_IDENT_STRING " EMK TOP860"
-
-/*-----------------------------------------------------------------------
- * CLOCK settings
- */
-#define	CONFIG_SYSCLK	49152000
-#define	CONFIG_SYS_XTAL		32768
-#define	CONFIG_EBDF		1
-#define	CONFIG_COM		3
-#define	CONFIG_RTC_MPC8xx
-
-/*-----------------------------------------------------------------------
- * Physical memory map as defined by EMK
- */
-#define CONFIG_SYS_IMMR		0xFFF00000	/* Internal Memory Mapped Register */
-#define	CONFIG_SYS_FLASH_BASE	0x80000000	/* FLASH in final mapping */
-#define	CONFIG_SYS_DRAM_BASE	0x00000000	/* DRAM in final mapping */
-#define	CONFIG_SYS_FLASH_MAX	0x00400000	/* max FLASH to expect */
-#define	CONFIG_SYS_DRAM_MAX	0x01000000	/* max DRAM to expect */
-
-/*-----------------------------------------------------------------------
- * derived values
- */
-#define	CONFIG_SYS_MF			(CONFIG_SYSCLK/CONFIG_SYS_XTAL)
-#define	CONFIG_SYS_CPUCLOCK	CONFIG_SYSCLK
-#define	CONFIG_SYS_BRGCLOCK	CONFIG_SYSCLK
-#define	CONFIG_SYS_BUSCLOCK	(CONFIG_SYSCLK >> CONFIG_EBDF)
-#define	CONFIG_8xx_GCLK_FREQ	CONFIG_SYSCLK
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CONFIG_SYS_FLASH_CFI
-
-/*-----------------------------------------------------------------------
- * Command interpreter
- */
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#define CONFIG_BAUDRATE		9600
-
-/*
- * Allow partial commands to be matched to uniqueness.
- */
-#define CONFIG_SYS_MATCH_PARTIAL_CMD
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_BEDBUG
-
-
-#define	CONFIG_SOURCE			1
-#define	CONFIG_SYS_LOADS_BAUD_CHANGE	1
-#undef	CONFIG_LOADS_ECHO			/* NO echo on for serial download	*/
-
-
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-
-#undef	CONFIG_SYS_HUSH_PARSER			/* Hush parse for U-Boot	*/
-
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
- #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-/*-----------------------------------------------------------------------
- * Memory Test Command
- */
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-/*-----------------------------------------------------------------------
- * Environment handler
- * only the first 6k in EEPROM are available for user. Of that we use 256b
- */
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* turn on EEPROM env feature */
-#define CONFIG_ENV_OFFSET		0x1000
-#define CONFIG_ENV_SIZE		0x0700
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_FACT_OFFSET		0x1800
-#define CONFIG_SYS_FACT_SIZE		0x0800
-#define CONFIG_SYS_I2C_FACT_ADDR	0x57
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_SIZE 0x2000
-#define	CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	100000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
-/**/
-#define	SDA	0x00010
-#define	SCL	0x00020
-#define __I2C_DIR	immr->im_cpm.cp_pbdir
-#define __I2C_DAT	immr->im_cpm.cp_pbdat
-#define __I2C_PAR	immr->im_cpm.cp_pbpar
-#define	__I2C_ODR	immr->im_cpm.cp_pbodr
-#define	I2C_INIT	{ __I2C_PAR &= ~(SDA|SCL);	\
-			  __I2C_ODR &= ~(SDA|SCL);	\
-			  __I2C_DAT |= (SDA|SCL);	\
-			  __I2C_DIR|=(SDA|SCL);	}
-#define	I2C_READ	((__I2C_DAT & SDA) ? 1 : 0)
-#define	I2C_SDA(x)	{ if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
-#define	I2C_SCL(x)	{ if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
-#define	I2C_DELAY	{ udelay(5); }
-#define	I2C_ACTIVE	{ __I2C_DIR |= SDA; }
-#define	I2C_TRISTATE	{ __I2C_DIR &= ~SDA; }
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*-----------------------------------------------------------------------
- * defines we need to get FEC running
- */
-#define CONFIG_FEC_ENET		1	/* Ethernet only via FEC	*/
-#define	FEC_ENET		1	/* eth.c needs it that way... */
-#define CONFIG_SYS_DISCOVER_PHY	1
-#define CONFIG_MII		1
-#define CONFIG_MII_INIT		1
-#define CONFIG_PHY_ADDR		31
-
-/*-----------------------------------------------------------------------
- * adresses
- */
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0x80000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2f00	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
-#define CONFIG_SYS_INIT_VPD_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_VPD_OFFSET-8)
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/* Interrupt level assignments.
-*/
-#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
-
-/*-----------------------------------------------------------------------
- * Debug Enable Register
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0					/* used in start.S */
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * set up PLPRCR (PLL, Low-Power, and Reset Control Register)
- *	12	MF		calculated	Multiplication factor
- *	4	0		0000
- *	1	SPLSS	0			System PLL lock status sticky
- *	1	TEXPS	1			Timer expired status
- *	1	0		0
- *	1	TMIST	0			Timers interrupt status
- *	1	0		0
- *	1	CSRC	0			Clock source (0=DFNH, 1=DFNL)
- *	2	LPM		00			Low-power modes
- *	1	CSR		0			Checkstop reset enable
- *	1	LOLRE	0			Loss-of-lock reset enable
- *	1	FIOPD	0			Force I/O pull down
- *	5	0		00000
- */
-#define CONFIG_SYS_PLPRCR	(PLPRCR_TEXPS | ((CONFIG_SYS_MF-1)<<20))
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * set up SYPCR:
- *	16	SWTC	0xffff		Software watchdog timer count
- *	8	BMT		0xff		Bus monitor timing
- *	1	BME		1			Bus monitor enable
- *	3	0		000
- *	1	SWF		1			Software watchdog freeze
- *	1	SWE		0/1			Software watchdog enable
- *	1	SWRI	0/1			Software watchdog reset/interrupt select (1=HRESET)
- *	1	SWP		0/1			Software watchdog prescale (1=/2048)
- */
-#if defined (CONFIG_WATCHDOG)
- #define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-					 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
- #define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * set up SIUMCR
- *	1	EARB	0			External arbitration
- *	3	EARP	000			External arbitration request priority
- *	4	0		0000
- *	1	DSHW	0			Data show cycles
- *	2	DBGC	00			Debug pin configuration
- *	2	DBPC	00			Debug port pins configuration
- *	1	0		0
- *	1	FRC		0			FRZ pin configuration
- *	1	DLK		0			Debug register lock
- *	1	OPAR	0			Odd parity
- *	1	PNCS	0			Parity enable for non memory controller regions
- *	1	DPC		0			Data parity pins configuration
- *	1	MPRE	0			Multiprocessor reservation enable
- *	2	MLRC	11			Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
- *	1	AEME	0			Async external master enable
- *	1	SEME	0			Sync external master enable
- *	1	BSC		0			Byte strobe configuration
- *	1	GB5E	0			GPL_B5 enable
- *	1	B2DD	0			Bank 2 double drive
- *	1	B3DD	0			Bank 3 double drive
- *	4	0		0000
- */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_MLRC11)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * set up SCCR (System Clock and Reset Control Register)
- *	1	0		0
- *	2	COM		11			Clock output module (00=full, 01=half, 11=off)
- *	3	0		000
- *	1	TBS		1			Timebase source (0=OSCCLK, 1=GCLK2)
- *	1	RTDIV	0			Real-time clock divide (0=/4, 1=/512)
- *	1	RTSEL	0			Real-time clock select (0=OSCM, 1=EXTCLK)
- *	1	CRQEN	0			CPM request enable
- *	1	PRQEN	0			Power management request enable
- *	2	0		00
- *	2	EBDF	xx			External bus division factor
- *	2	0		00
- *	2	DFSYNC	00			Division factor for SYNCLK
- *	2	DFBRG	00			Division factor for BRGCLK
- *	3	DFNL	000			Division factor low frequency
- *	3	DFNH	000			Division factor high frequency
- *	5	0		00000
- */
-#define SCCR_MASK	0
-#ifdef CONFIG_EBDF
- #define CONFIG_SYS_SCCR	(SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
-#else
- #define CONFIG_SYS_SCCR	(SCCR_COM11 | SCCR_TBS)
-#endif
-
-/*-----------------------------------------------------------------------
- * Chip Select 0 - FLASH
- *-----------------------------------------------------------------------
- * Preliminary Values
- */
-/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1	*/
-#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
-#define CONFIG_SYS_OR0_PRELIM	(-CONFIG_SYS_FLASH_MAX | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V )
-
-/*-----------------------------------------------------------------------
- * misc
- *-----------------------------------------------------------------------
- *
- */
-/*
- * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
- */
-#define CONFIG_BOOTDELAY				5
-
-/*
- * Pass the clock frequency to the Linux kernel in units of MHz
- */
-#define	CONFIG_CLOCKS_IN_MHZ
-
-#define CONFIG_PREBOOT		\
-	"echo;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND	\
-	"bootp;" \
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
-	"bootm"
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Set default IP stuff just to get bootstrap entries into the
- * environment so that we can source the full default environment.
- */
-#define CONFIG_ETHADDR					9a:52:63:15:85:25
-#define CONFIG_SERVERIP					10.0.4.200
-#define CONFIG_IPADDR					10.0.4.111
-
-#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 69c0336caee..cdccbef1f63 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2003-2005
+ * (C) Copyright 2003-2014
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * (C) Copyright 2004-2006
@@ -19,6 +19,8 @@
 #define CONFIG_MPC5200		1	/* This is an MPC5200 CPU		*/
 #define CONFIG_TQM5200		1	/* ... on TQM5200 module		*/
 #undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules	*/
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
 
 /*
  * Valid values for CONFIG_SYS_TEXT_BASE are:
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index cc2204586ec..0d5a2b96f15 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -19,6 +19,8 @@
 
 #define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
 #define CONFIG_TQM823L		1	/* ...on a TQM8xxL module	*/
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
 
 #define	CONFIG_SYS_TEXT_BASE	0x40000000
 
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index 4fd070f27d5..e765a03cfb0 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -19,6 +19,8 @@
 
 #define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
 #define CONFIG_TQM823M		1	/* ...on a TQM8xxM module	*/
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
 
 #define	CONFIG_SYS_TEXT_BASE	0x40000000
 
diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h
deleted file mode 100644
index 7fd12d3fbc6..00000000000
--- a/include/configs/TQM8260.h
+++ /dev/null
@@ -1,620 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Imported from global configuration:
- *	CONFIG_MPC8255
- *	CONFIG_MPC8265
- *	CONFIG_200MHz
- *	CONFIG_266MHz
- *	CONFIG_300MHz
- *	CONFIG_L2_CACHE
- *	CONFIG_BUSMODE_60x
- */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define	CONFIG_SYS_TEXT_BASE	0x40000000
-
-
-#if 0
-#define CONFIG_TQM8260		100	/* ...on a TQM8260 module Rev.100	*/
-#else
-#define CONFIG_TQM8260		200	/* ...on a TQM8260 module Rev.200	*/
-#endif
-
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define CONFIG_82xx_CONS_SMC1	1	/* console on SMC1			*/
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define	CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"bootfile=tqm8260/uImage\0"				\
-	"kernel_addr=400C0000\0"					\
-	"ramdisk_addr=40240000\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-
-/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
-#if (CONFIG_TQM8260 <= 100)
-
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00020000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00020000)
-#define I2C_READ	((iop->pdat & 0x00020000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#else
-
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-#endif
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CONFIG_I2C_X
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef  CONFIG_CONS_NONE		/* define if console on something else*/
-#ifdef CONFIG_82xx_CONS_SMC1
-#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
-#endif
-#ifdef CONFIG_82xx_CONS_SMC2
-#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
-#endif
-
-#undef  CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
-#define CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9 */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- *
- * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
- * X.29 connector, and FCC2 is hardwired to the X.1 connector)
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define	CONFIG_ETHER_INDEX    2		/* which SCC/FCC channel for ethernet */
-
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- *  - RX clk is CLK11
- *  - TX clk is CLK12
- */
-# define CONFIG_SYS_CMXSCR_VALUE1	(CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
-#  define CONFIG_8260_CLKIN	66666666	/* in Hz */
-#else	/* !CONFIG_MPC8255 && !CONFIG_MPC8265 */
-# ifndef CONFIG_300MHz
-#  define CONFIG_8260_CLKIN	66666666	/* in Hz */
-# else
-#  define CONFIG_8260_CLKIN	83333000	/* in Hz */
-# endif
-#endif	/* CONFIG_MPC8255 */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
-
-#define	CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC	/* "bad" address		*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
-
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CONFIG_SYS_FLASH0_BASE 0x40000000
-#define CONFIG_SYS_FLASH1_BASE 0x60000000
-#define CONFIG_SYS_FLASH0_SIZE 32
-#define CONFIG_SYS_FLASH1_SIZE 32
-
-/* Flash bank size (for preliminary settings)
- */
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-/* use CFI flash driver */
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER		1	/* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_FLASH_EMPTY_INFO	1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
-#define CONFIG_ENV_SIZE		0x08000
-#define CONFIG_ENV_SECT_SIZE	0x40000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#define	__HRCW__ALL__		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
-
-#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
-#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
-#else	/* ! MPC8255 && !MPC8265 */
-# if defined(CONFIG_266MHz)
-#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
-# elif defined(CONFIG_300MHz)
-#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0110)
-# else
-#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__)
-# endif
-#endif	/* CONFIG_MPC8255 */
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1		0
-#define CONFIG_SYS_HRCW_SLAVE2		0
-#define CONFIG_SYS_HRCW_SLAVE3		0
-#define CONFIG_SYS_HRCW_SLAVE4		0
-#define CONFIG_SYS_HRCW_SLAVE5		0
-#define CONFIG_SYS_HRCW_SLAVE6		0
-#define CONFIG_SYS_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000  /* Size of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
- * is mapped at SDRAM_BASE2_PRELIM.
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers                    2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-				HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2        0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register                                     5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR         RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                                       4-25
- *-----------------------------------------------------------------------
- */
-#ifdef	CONFIG_BUSMODE_60x
-#define CONFIG_SYS_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
-			 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2)	/* 60x mode  */
-#else
-#define BCR_APD01	0x10000000
-#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                             4-31
- *-----------------------------------------------------------------------
- */
-#if 0
-#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
-#else
-#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
-#endif
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                             4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control                     4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control                 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                                   9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR        0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                         13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR        0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus     Machine PortSz  Device
- * ---- ---     ------- ------  ------
- *  0   60x     GPCM    64 bit  FLASH
- *  1   60x     SDRAM   64 bit  SDRAM
- *  2   Local   SDRAM   32 bit  SDRAM
- *
- */
-
-	/* Initialize SDRAM on local bus
-	 */
-#define CONFIG_SYS_INIT_LOCAL_SDRAM
-
-#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
-#define CONFIG_SYS_LOCAL_SDRAM_LIMIT	(128<<20)	/* less than 128 MB */
-
-#define CONFIG_SYS_MPTPR       0x4000
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- * In fact, the address is rather configuration data presented to the SDRAM on
- * its address lines. Because the address lines may be mux'ed externally either
- * for 8 column or 9 column devices, some bits appear twice in the 8260's
- * address:
- *
- * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
- * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
- *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
- *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
- *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_MRS_OFFS	0x00000110
-
-
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_3_CLK                 |\
-			 ORxG_EHTR                      |\
-			 ORxG_TRLX)
-
-	/* SDRAM on TQM8260 can have either 8 or 9 columns.
-	 * The number affects configuration values.
-	 */
-
-/* Bank 1 - 60x bus SDRAM
- */
-#define CONFIG_SYS_PSRT        0x20
-#define CONFIG_SYS_LSRT        0x20
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_SDRAM_P                 |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1_8COL
-
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A7             |\
-			 ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A15_IS_A5           |\
-			 PSDMR_BSMA_A12_A14             |\
-			 PSDMR_SDA10_PBI1_A8            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_EAMUX                    |\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A5             |\
-			 ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A16_IS_A5           |\
-			 PSDMR_BSMA_A12_A14             |\
-			 PSDMR_SDA10_PBI1_A7            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_EAMUX                    |\
-			 PSDMR_CL_2)
-
-/* Bank 2 - Local bus SDRAM
- */
-#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
-#define CONFIG_SYS_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
-			 BRx_PS_32                      |\
-			 BRx_MS_SDRAM_L                 |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_OR2_8COL
-
-#define SDRAM_BASE2_PRELIM	0x80000000
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CONFIG_SYS_OR2_8COL    ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A8             |\
-			 ORxS_NUMR_12)
-
-#define CONFIG_SYS_LSDMR_8COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A15_IS_A5           |\
-			 PSDMR_BSMA_A13_A15             |\
-			 PSDMR_SDA10_PBI1_A9            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_BL                       |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CONFIG_SYS_OR2_9COL    ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A6             |\
-			 ORxS_NUMR_13)
-
-#define CONFIG_SYS_LSDMR_9COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A16_IS_A5           |\
-			 PSDMR_BSMA_A13_A15             |\
-			 PSDMR_SDA10_PBI1_A8            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_BL                       |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_CL_2)
-
-#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h
deleted file mode 100644
index 9c7e16305d1..00000000000
--- a/include/configs/TQM8272.h
+++ /dev/null
@@ -1,735 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8272_FAMILY   1
-#define CONFIG_TQM8272		1
-
-#define	CONFIG_SYS_TEXT_BASE	0x40000000
-
-#define	CONFIG_GET_CPU_STR_F	1	/* Get the CPU ID STR */
-#define CONFIG_BOARD_GET_CPU_CLK_F	1 /* Get the CLKIN from board fct */
-
-#define	STK82xx_150		1	/* on a STK82xx.150 */
-
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define CONFIG_82xx_CONS_SMC1	1	/* console on SMC1		*/
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_BOARD_EARLY_INIT_R	1
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		230400
-#else
-#define CONFIG_BAUDRATE		115200
-#endif
-
-#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"consdev=ttyCPM0\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"hostname=tqm8272\0"						\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addcons=setenv bootargs ${bootargs} "				\
-		"console=$(consdev),$(baudrate)\0"			\
-	"flash_nfs=run nfsargs addip addcons;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addcons;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 300000 ${bootfile};"				\
-		"run nfsargs addip addcons;bootm\0"			\
-	"rootpath=/opt/eldk/ppc_82xx\0"					\
-	"bootfile=/tftpboot/tqm8272/uImage\0"				\
-	"kernel_addr=40080000\0"					\
-	"ramdisk_addr=40100000\0"					\
-	"load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0"		\
-	"update=protect off 40000000 4003ffff;era 40000000 4003ffff;"	\
-		"cp.b 300000 40000000 40000;"			        \
-		"setenv filesize;saveenv\0"				\
-	"cphwib=cp.b 4003fc00 33fc00 400\0"				\
-	"upd=run load cphwib update\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_I2C	1
-
-#if CONFIG_I2C
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#define CONFIG_I2C_X
-
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS		1	/* more than one eeprom */
-
-/* I2C RTC */
-#define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
-
-/* I2C SYSMON (LM75) */
-#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
-#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
-#define CONFIG_SYS_DTT_MAX_TEMP	70
-#define CONFIG_SYS_DTT_LOW_TEMP	-30
-#define CONFIG_SYS_DTT_HYSTERESIS	3
-
-#else
-#undef CONFIG_SYS_I2C
-#undef CONFIG_HARD_I2C
-#undef CONFIG_SYS_I2C_SOFT
-#endif
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef  CONFIG_CONS_NONE		/* define if console on something else*/
-#ifdef CONFIG_82xx_CONS_SMC1
-#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
-#endif
-#ifdef CONFIG_82xx_CONS_SMC2
-#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
-#endif
-
-#undef  CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
-#define CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9 */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- *
- * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
- * X.29 connector, and FCC2 is hardwired to the X.1 connector)
- */
-#define CONFIG_SYS_FCC_ETHERNET
-
-#if defined(CONFIG_SYS_FCC_ETHERNET)
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define	CONFIG_ETHER_INDEX    2		/* which SCC/FCC channel for ethernet */
-#else
-#define	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#undef	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define	CONFIG_ETHER_INDEX    1		/* which SCC/FCC channel for ethernet */
-#endif
-
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- *  - RX clk is CLK11
- *  - TX clk is CLK12
- */
-# define CONFIG_SYS_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-#define CONFIG_MII			/* MII PHY management		*/
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT	2		/* Port C */
-#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
-				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE	MDIO_DECLARE
-
-#if STK82xx_150
-#define CONFIG_SYS_MDIO_PIN	0x00008000	/* PC16 */
-#define CONFIG_SYS_MDC_PIN	0x00004000	/* PC17 */
-#endif
-
-#if STK82xx_100
-#define CONFIG_SYS_MDIO_PIN	0x00000002	/* PC30 */
-#define CONFIG_SYS_MDC_PIN	0x00000001	/* PC31 */
-#endif
-
-#if 1
-#define MDIO_ACTIVE	(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
-#define MDIO_TRISTATE	(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
-#define MDIO_READ	((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
-
-#define MDIO(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
-			else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN
-
-#define MDC(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
-			else	iop->pdat &= ~CONFIG_SYS_MDC_PIN
-#else
-#define MDIO_ACTIVE	({unsigned long tmp; tmp = iop->pdir; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
-#define MDIO_TRISTATE	({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
-#define MDIO_READ	((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
-
-#define MDIO(bit)	if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\
-			else	{unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}
-
-#define MDC(bit)	if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\
-			else	{unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}
-#endif
-
-#define MIIDELAY	udelay(1)
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN	66666666	/* in Hz */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SNTP
-
-#if CONFIG_I2C
-    #define CONFIG_CMD_I2C
-    #define CONFIG_CMD_DATE
-    #define CONFIG_CMD_DTT
-    #define CONFIG_CMD_EEPROM
-#endif
-
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-
-#if 0
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR	0x300000	/* default load address	*/
-
-#define	CONFIG_SYS_RESET_ADDRESS 0x40000104	/* "bad" address		*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * CAN stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_CAN_BASE	0x51000000
-#define	CONFIG_SYS_CAN_SIZE	1
-#define CONFIG_SYS_CAN_BR	((CONFIG_SYS_CAN_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_8			|\
-			 BRx_MS_UPMC			|\
-			 BRx_V)
-
-#define CONFIG_SYS_CAN_OR	(MEG_TO_AM(CONFIG_SYS_CAN_SIZE)	|\
-			 ORxU_BI)
-
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8272/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CONFIG_SYS_FLASH0_BASE 0x40000000
-#define CONFIG_SYS_FLASH0_SIZE 32	/* 32 MB */
-
-/* Flash bank size (for preliminary settings)
- */
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_CFI				/* flash is CFI compat.	*/
-#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver*/
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
-#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-#define CONFIG_SYS_UPDATE_FLASH_SIZE
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
-#define CONFIG_ENV_SIZE		0x20000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	0x20000
-
-/* Where is the Hardwareinformation Block (from Monitor Sources) */
-#define MON_RES_LENGTH		(0x0003FC00)
-#define HWIB_INFO_START_ADDR    (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH)
-#define HWIB_INFO_LEN           512
-#define CIB_INFO_START_ADDR     (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
-#define CIB_INFO_LEN            512
-
-#define CONFIG_SYS_HWINFO_OFFSET	0x3fc00	/* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE		0x00000060	/* size   of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_NAND)
-
-#define CONFIG_SYS_NAND_CS_DIST		0x80
-#define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS	0x20
-#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS	0x40
-
-#define CONFIG_SYS_NAND_BR	((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_8			|\
-			 BRx_MS_UPMB			|\
-			 BRx_V)
-
-#define CONFIG_SYS_NAND_OR	(MEG_TO_AM(CONFIG_SYS_NAND_SIZE)	|\
-			 ORxU_BI			|\
-			 ORxU_EHTR_8IDLE)
-
-#define CONFIG_SYS_NAND_SIZE	1
-#define CONFIG_SYS_NAND0_BASE 0x50000000
-#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
-#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
-#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
-
-#define CONFIG_SYS_MAX_NAND_DEVICE     4       /* Max number of NAND devices           */
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
-			     CONFIG_SYS_NAND1_BASE, \
-			     CONFIG_SYS_NAND2_BASE, \
-			     CONFIG_SYS_NAND3_BASE, \
-			   }
-
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
-#define WRITE_NAND_UPM(d, adr, off) do \
-{ \
-	volatile unsigned char *addr = (unsigned char *) (adr + off); \
-	WRITE_NAND(d, addr); \
-} while(0)
-
-#endif /* CONFIG_CMD_NAND */
-
-#define	CONFIG_PCI
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
-#define CONFIG_PCI_PNP
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#if 0
-#define	__HRCW__ALL__		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
-
-#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
-#else
-#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
-#endif
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1		0
-#define CONFIG_SYS_HRCW_SLAVE2		0
-#define CONFIG_SYS_HRCW_SLAVE3		0
-#define CONFIG_SYS_HRCW_SLAVE4		0
-#define CONFIG_SYS_HRCW_SLAVE5		0
-#define CONFIG_SYS_HRCW_SLAVE6		0
-#define CONFIG_SYS_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2000  /* Size of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers                    2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-				HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2        0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register                                     5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR         RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                                       4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR_60x         (BCR_EBM|BCR_NPQM0|BCR_NPQM2)	/* 60x mode  */
-#define BCR_APD01	0x10000000
-#define CONFIG_SYS_BCR_SINGLE		(BCR_APD01|BCR_ETM)	/* 8260 mode */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                             4-31
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
-#define CONFIG_SYS_SIUMCR_LOW		(SIUMCR_DPPC00)
-#define CONFIG_SYS_SIUMCR_HIGH		(SIUMCR_DPPC00 | SIUMCR_ABE)
-#else
-#define CONFIG_SYS_SIUMCR		(SIUMCR_DPPC00)
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                             4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control                     4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control                 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                                   9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR        SCCR_DFBRG01
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                         13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR        0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus     Machine PortSz  Device
- * ---- ---     ------- ------  ------
- *  0   60x     GPCM    32 bit  FLASH
- *  1   60x     SDRAM   64 bit  SDRAM
- *  2   60x	UPMB	 8 bit	NAND
- *  3   60x	UPMC	 8 bit	CAN
- *
- */
-
-/* Initialize SDRAM
-	 */
-#undef CONFIG_SYS_INIT_LOCAL_SDRAM		/* No SDRAM on Local Bus */
-
-#define SDRAM_MAX_SIZE	0x20000000	/* max. 512 MB		*/
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
-
-#define CONFIG_SYS_MPTPR       0x4000
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- * In fact, the address is rather configuration data presented to the SDRAM on
- * its address lines. Because the address lines may be mux'ed externally either
- * for 8 column or 9 column devices, some bits appear twice in the 8260's
- * address:
- *
- * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
- * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
- *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
- *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
- *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_MRS_OFFS	0x00000110
-
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_32                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV4                  |\
-			 ORxG_SCY_8_CLK                 |\
-			 ORxG_TRLX)
-
-/* SDRAM on TQM8272 can have either 8 or 9 columns.
- * The number affects configuration values.
- */
-
-/* Bank 1 - 60x bus SDRAM
- */
-#define CONFIG_SYS_PSRT        0x20	/* Low Value */
-/* #define CONFIG_SYS_PSRT        0x10	 Fast Value */
-#define CONFIG_SYS_LSRT        0x20	/* Local Bus */
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_SDRAM_P                 |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1_8COL
-
-/* SDRAM initialization values for 8-column chips
- */
-#define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A7             |\
-			 ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A15_IS_A5           |\
-			 PSDMR_BSMA_A12_A14             |\
-			 PSDMR_SDA10_PBI1_A8            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_EAMUX                    |\
-			 PSDMR_BUFCMD			|\
-			 PSDMR_CL_2)
-
-
-/* SDRAM initialization values for 9-column chips
- */
-#define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A5             |\
-			 ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A16_IS_A5           |\
-			 PSDMR_BSMA_A12_A14             |\
-			 PSDMR_SDA10_PBI1_A7            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_EAMUX                    |\
-			 PSDMR_BUFCMD			|\
-			 PSDMR_CL_2)
-
-#define CONFIG_SYS_OR1_10COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A4             |\
-			 ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_10COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A17_IS_A5           |\
-			 PSDMR_BSMA_A12_A14             |\
-			 PSDMR_SDA10_PBI1_A4            |\
-			 PSDMR_RFRC_6_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_EAMUX                    |\
-			 PSDMR_BUFCMD			|\
-			 PSDMR_CL_2)
-
-#define PSDMR_RFRC_66MHZ_SINGLE         0x00028000  /* PSDMR[RFRC] at 66 MHz single mode */
-#define PSDMR_RFRC_100MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 100 MHz single mode */
-#define PSDMR_RFRC_133MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 133 MHz single mode */
-#define PSDMR_RFRC_66MHZ_60X            0x00030000  /* PSDMR[RFRC] at 66 MHz 60x mode */
-#define PSDMR_RFRC_100MHZ_60X           0x00028000  /* PSDMR[RFRC] at 100 MHz 60x mode */
-#define PSDMR_RFRC_DEFAULT              PSDMR_RFRC_133MHZ_SINGLE  /* PSDMR[RFRC] default value */
-
-#define PSDMR_PRETOACT_66MHZ_SINGLE     0x00002000  /* PSDMR[PRETOACT] at 66 MHz single mode */
-#define PSDMR_PRETOACT_100MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 100 MHz single mode */
-#define PSDMR_PRETOACT_133MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 133 MHz single mode */
-#define PSDMR_PRETOACT_66MHZ_60X        0x00001000  /* PSDMR[PRETOACT] at 66 MHz 60x mode */
-#define PSDMR_PRETOACT_100MHZ_60X       0x00001000  /* PSDMR[PRETOACT] at 100 MHz 60x mode */
-#define PSDMR_PRETOACT_DEFAULT          PSDMR_PRETOACT_133MHZ_SINGLE  /* PSDMR[PRETOACT] default value */
-
-#define PSDMR_WRC_66MHZ_SINGLE          0x00000020  /* PSDMR[WRC] at 66 MHz single mode */
-#define PSDMR_WRC_100MHZ_SINGLE         0x00000020  /* PSDMR[WRC] at 100 MHz single mode */
-#define PSDMR_WRC_133MHZ_SINGLE         0x00000010  /* PSDMR[WRC] at 133 MHz single mode */
-#define PSDMR_WRC_66MHZ_60X             0x00000010  /* PSDMR[WRC] at 66 MHz 60x mode */
-#define PSDMR_WRC_100MHZ_60X            0x00000010  /* PSDMR[WRC] at 100 MHz 60x mode */
-#define PSDMR_WRC_DEFAULT               PSDMR_WRC_133MHZ_SINGLE  /* PSDMR[WRC] default value */
-
-#define PSDMR_BUFCMD_66MHZ_SINGLE       0x00000000  /* PSDMR[BUFCMD] at 66 MHz single mode */
-#define PSDMR_BUFCMD_100MHZ_SINGLE      0x00000000  /* PSDMR[BUFCMD] at 100 MHz single mode */
-#define PSDMR_BUFCMD_133MHZ_SINGLE      0x00000004  /* PSDMR[BUFCMD] at 133 MHz single mode */
-#define PSDMR_BUFCMD_66MHZ_60X          0x00000000  /* PSDMR[BUFCMD] at 66 MHz 60x mode */
-#define PSDMR_BUFCMD_100MHZ_60X         0x00000000  /* PSDMR[BUFCMD] at 100 MHz 60x mode */
-#define PSDMR_BUFCMD_DEFAULT            PSDMR_BUFCMD_133MHZ_SINGLE  /* PSDMR[BUFCMD] default value */
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index ca3750d4075..bbdc3f81fc4 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -19,6 +19,8 @@
 
 #define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
 #define CONFIG_TQM850L		1	/* ...on a TQM8xxL module	*/
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
 
 #define	CONFIG_SYS_TEXT_BASE	0x40000000
 
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index 659c9ad1c37..5fc87f2138d 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -19,6 +19,8 @@
 
 #define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
 #define CONFIG_TQM850M		1	/* ...on a TQM8xxM module	*/
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
 
 #define	CONFIG_SYS_TEXT_BASE	0x40000000
 
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index 906d79b0c87..589d168eba0 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -19,6 +19,8 @@
 
 #define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
 #define CONFIG_TQM855L		1	/* ...on a TQM8xxL module	*/
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
 
 #define	CONFIG_SYS_TEXT_BASE	0x40000000
 
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index 44d456e165a..60acb564e87 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -19,6 +19,8 @@
 
 #define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
 #define CONFIG_TQM855M		1	/* ...on a TQM8xxM module	*/
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
 
 #define	CONFIG_SYS_TEXT_BASE	0x40000000
 
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index 855b0cddc4b..ebc55716322 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -19,6 +19,8 @@
 
 #define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
 #define CONFIG_TQM860L		1	/* ...on a TQM8xxL module	*/
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
 
 #define	CONFIG_SYS_TEXT_BASE	0x40000000
 
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 8109379ae9b..f4ce07f20e3 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -19,6 +19,8 @@
 
 #define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
 #define CONFIG_TQM860M		1	/* ...on a TQM8xxM module	*/
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
 
 #define	CONFIG_SYS_TEXT_BASE	0x40000000
 
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index da4af93d251..97db519d530 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -20,6 +20,8 @@
 #define CONFIG_MPC860		1
 #define CONFIG_MPC860T		1
 #define CONFIG_MPC862		1
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_TQM862L		1	/* ...on a TQM8xxL module	*/
 
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index ec3a57b9618..25d60a74ef4 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -20,6 +20,8 @@
 #define CONFIG_MPC860		1
 #define CONFIG_MPC860T		1
 #define CONFIG_MPC862		1
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_TQM862M		1	/* ...on a TQM8xxM module	*/
 
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index cb8b84d3a17..928b8796091 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -19,6 +19,8 @@
 
 #define CONFIG_MPC866		1	/* This is a MPC866 CPU		*/
 #define CONFIG_TQM866M		1	/* ...on a TQM8xxM module	*/
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
 
 #define	CONFIG_SYS_TEXT_BASE	0x40000000
 
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index d1e6c5b2bb2..598020c8676 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2014
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * (C) Copyright 2006
@@ -22,6 +22,8 @@
 
 #define CONFIG_MPC885		1	/* This is a MPC885 CPU		*/
 #define CONFIG_TQM885D		1	/* ...on a TQM88D module	*/
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
 
 #define	CONFIG_SYS_TEXT_BASE	0x40000000
 
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
index f57820d8f59..54b7028c560 100644
--- a/include/configs/ac14xx.h
+++ b/include/configs/ac14xx.h
@@ -13,6 +13,9 @@
 #define __CONFIG_H
 
 #define CONFIG_AC14XX 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
+
 /*
  * Memory map for the ifm AC14xx board:
  *
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 476430ddd08..1ec783daf4f 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -352,10 +352,10 @@
 	"boot part 0 1;" \
 	"rootfs part 0 2;" \
 	"MLO fat 0 1;" \
-	"MLO.raw mmc 0x100 0x100;" \
-	"u-boot.img.raw mmc 0x300 0x400;" \
-	"spl-os-args.raw mmc 0x80 0x80;" \
-	"spl-os-image.raw mmc 0x900 0x2000;" \
+	"MLO.raw raw 0x100 0x100;" \
+	"u-boot.img.raw raw 0x300 0x400;" \
+	"spl-os-args.raw raw 0x80 0x80;" \
+	"spl-os-image.raw raw 0x900 0x2000;" \
 	"spl-os-args fat 0 1;" \
 	"spl-os-image fat 0 1;" \
 	"u-boot.img fat 0 1;" \
@@ -382,7 +382,7 @@
 	"fdt ram 0x80F80000 0x80000;" \
 	"ramdisk ram 0x81000000 0x4000000\0"
 #define DFUARGS \
-	"dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \
+	"dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
 	DFU_ALT_INFO_MMC \
 	DFU_ALT_INFO_RAM \
 	DFU_ALT_INFO_NAND
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index fcb4033c01f..0fbfa3fb4c4 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -304,8 +304,8 @@
 
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index c5d64ca59ed..8719f763dd4 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -313,8 +313,8 @@
 
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 070782774d9..4472c3e5558 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -11,6 +11,9 @@
 
 #define CONFIG_AM43XX
 
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_SAVEENV
+
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_SYS_CACHELINE_SIZE       32
@@ -82,7 +85,11 @@
 /* NS16550 Configuration */
 #define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
 
-#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE		"mmc"
+#define FAT_ENV_DEVICE_AND_PART		"0:1"
+#define FAT_ENV_FILE			"uboot.env"
+#define CONFIG_FAT_WRITE
 
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
 
@@ -103,7 +110,7 @@
 
 #ifdef CONFIG_QSPI_BOOT
 #define CONFIG_SYS_TEXT_BASE           0x30000000
-#undef CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_ENV_IS_IN_FAT
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 #define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
new file mode 100644
index 00000000000..3cde923b5f9
--- /dev/null
+++ b/include/configs/apalis_t30.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2014 Marcel Ziswiler
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra30-common.h"
+
+/* High-level configuration options */
+#define V_PROMPT			"Apalis T30 # "
+#define CONFIG_TEGRA_BOARD_STRING	"Toradex Apalis T30"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_APALIS_T30
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* PCI host support */
+#undef CONFIG_PCI	/* just define once Tegra PCIe support got merged */
+#define CONFIG_PCI_TEGRA
+#define CONFIG_PCI_PNP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+
+/* PCI networking support */
+#define CONFIG_E1000
+#undef CONFIG_E1000_NO_NVM	/* just define once E1000 driver got fixed */
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/aria.h b/include/configs/aria.h
index c36cf33f070..2f9677c3328 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -13,6 +13,9 @@
 #define __CONFIG_H
 
 #define CONFIG_ARIA 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
+
 /*
  * Memory map for the ARIA board:
  *
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index 1bf83907221..6e8c56c1dde 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -83,12 +83,15 @@
 /*
  * I2C configuration
  */
-#define CONFIG_HARD_I2C
-#define CONFIG_DW_I2C
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DW
 #define CONFIG_I2C_ENV_EEPROM_BUS	2
 #define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SPEED1		100000
+#define CONFIG_SYS_I2C_SPEED2		100000
 #define CONFIG_SYS_I2C_SLAVE		0
+#define CONFIG_SYS_I2C_SLAVE1		0
+#define CONFIG_SYS_I2C_SLAVE2		0
 #define CONFIG_SYS_I2C_BASE		0xE001D000
 #define CONFIG_SYS_I2C_BASE1		0xE001E000
 #define CONFIG_SYS_I2C_BASE2		0xE001F000
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 7cf241e31d7..f7277eb1d17 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -19,7 +19,17 @@
 #define CONFIG_MX6
 #define CONFIG_SYS_LITTLE_ENDIAN
 #define CONFIG_MACH_TYPE		4273
-#define CONFIG_SYS_HZ			1000
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+
+#define CONFIG_DM_GPIO
+#define CONFIG_CMD_GPIO
+
+#define CONFIG_DM_SERIAL
+#define CONFIG_SYS_MALLOC_F_LEN		(1 << 10)
+#endif
 
 /* Display information on boot */
 #define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 6f4d97f2fd0..1919cde79fc 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -321,8 +321,8 @@
 
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
 
 #define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index 782b9d16b7a..a582e255169 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -11,7 +11,6 @@
 
 #include "tegra30-common.h"
 
-
 #define V_PROMPT			"Colibri T30 # "
 #define CONFIG_TEGRA_BOARD_STRING	"Toradex Colibri T30"
 
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 936be145119..fef267f70b2 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -25,6 +25,13 @@
 #define CONFIG_ZBOOT_32
 #define CONFIG_PHYSMEM
 #define CONFIG_SYS_EARLY_PCI_INIT
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+#define CONFIG_DM_GPIO
+#define CONFIG_DM_SERIAL
 
 #define CONFIG_LMB
 #define CONFIG_OF_LIBFDT
@@ -39,8 +46,10 @@
 #define CONFIG_BOOTSTAGE_USER_COUNT	60
 
 #define CONFIG_LZO
+#define CONFIG_FIT
 #undef CONFIG_ZLIB
 #undef CONFIG_GZIP
+#define CONFIG_SYS_BOOTM_LEN		(16 << 20)
 
 /*-----------------------------------------------------------------------
  * Watchdog Configuration
@@ -86,21 +95,16 @@
 /*-----------------------------------------------------------------------
  * Serial Configuration
  */
-#define CONFIG_CONS_INDEX		1
+#define CONFIG_COREBOOT_SERIAL
 #define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		1843200
-#define CONFIG_BAUDRATE			9600
+#define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{300, 600, 1200, 2400, 4800, \
 					 9600, 19200, 38400, 115200}
-#define CONFIG_SYS_NS16550_COM1	UART0_BASE
-#define CONFIG_SYS_NS16550_COM2	UART1_BASE
 #define CONFIG_SYS_NS16550_PORT_MAPPED
 
-#define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,eserial0\0" \
-					"stdout=vga,eserial0,cbmem\0" \
-					"stderr=vga,eserial0,cbmem\0"
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \
+					"stdout=vga,serial,cbmem\0" \
+					"stderr=vga,serial,cbmem\0"
 
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
@@ -109,7 +113,8 @@
 
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_COMMAND_HISTORY
-#define CONFIG_AUTOCOMPLETE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
 
 #define CONFIG_SUPPORT_VFAT
 /************************************************************
@@ -192,6 +197,7 @@
 #define CONFIG_CMD_EXT2
 
 #define CONFIG_CMD_ZBOOT
+#define CONFIG_CMD_ELF
 
 #define CONFIG_BOOTDELAY	2
 #define CONFIG_BOOTARGS		\
@@ -208,8 +214,7 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT			"boot > "
-#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_CBSIZE			512
 #define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + \
 						 sizeof(CONFIG_SYS_PROMPT) + \
 						 16)
@@ -218,7 +223,7 @@
 
 #define CONFIG_SYS_MEMTEST_START		0x00100000
 #define CONFIG_SYS_MEMTEST_END			0x01000000
-#define CONFIG_SYS_LOAD_ADDR			0x100000
+#define CONFIG_SYS_LOAD_ADDR			0x20000000
 
 /*-----------------------------------------------------------------------
  * SDRAM Configuration
@@ -253,7 +258,7 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MONITOR_LEN			(256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN			(0x20000 + 128 * 1024)
-
+#define CONFIG_SYS_MALLOC_F_LEN			(1 << 10)
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -283,6 +288,11 @@
  */
 #define CONFIG_PCI
 
+#define CONFIG_CROS_EC
+#define CONFIG_CROS_EC_LPC
+#define CONFIG_CMD_CROS_EC
+#define CONFIG_ARCH_EARLY_INIT_R
+
 /*-----------------------------------------------------------------------
  * USB configuration
  */
@@ -297,6 +307,12 @@
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 #define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_TFTP_TSIZE
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
 
 #define CONFIG_CMD_USB
 
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 12b32967b43..72b7efa5092 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -57,6 +57,7 @@
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
 #define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
 #define CONFIG_PCIE1			/* PCIE controler 1 */
 #define CONFIG_PCIE2			/* PCIE controler 2 */
@@ -648,6 +649,12 @@
 #define CONFIG_DOS_PARTITION
 #endif
 
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 /*
  * Miscellaneous configurable options
  */
@@ -745,4 +752,8 @@
 
 #include <asm/fsl_secure_boot.h>
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
new file mode 100644
index 00000000000..cb03e33b6e1
--- /dev/null
+++ b/include/configs/db-mv784mp-gp.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_DB_MV7846MP_GP_H
+#define _CONFIG_DB_MV7846MP_GP_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_ARMADA_XP		/* SOC Family Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define	CONFIG_SYS_TEXT_BASE	0x04000000
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TFTPPUT
+#define CONFIG_CMD_TIME
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE		MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED		1000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+#define CONFIG_SPI_FLASH_STMICRO
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
+
+#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
+#define CONFIG_PHY_BASE_ADDR	0x10
+#define CONFIG_SYS_NETA_INTERFACE_TYPE	PHY_INTERFACE_MODE_QSGMII
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+#define CONFIG_RESET_PHY_R
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
+#define CONFIG_SYS_ALT_MEMTEST
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#endif /* _CONFIG_DB_MV7846MP_GP_H */
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 7ab6d51642d..ca624619a0c 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -298,8 +298,8 @@
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION    1
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 
 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
@@ -341,8 +341,8 @@
 					0x400000)
 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
 
-#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME		"uImage"
-#define CONFIG_SPL_FAT_LOAD_ARGS_NAME		"args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME		"args"
 
 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x500 /* address 0xa0000 */
 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x8   /* address 0x1000 */
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index 2a8cb3940b6..76ec168c202 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -22,6 +22,8 @@
 
 #define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
 #define CONFIG_DIGSY_MTC	1	/* ... on InterControl digsyMTC board */
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
 
 /*
  * Valid values for CONFIG_SYS_TEXT_BASE are:
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
index 37bdcc0f332..47a8420f42d 100644
--- a/include/configs/edb93xx.h
+++ b/include/configs/edb93xx.h
@@ -89,7 +89,6 @@
 #define CONFIG_EP93XX		1		/* in a Cirrus Logic 93xx SoC */
 
 #define CONFIG_SYS_CLK_FREQ	14745600	/* EP93xx has a 14.7456 clock */
-#define CONFIG_SYS_HZ		1000		/* decr freq: 1 ms ticks */
 #undef CONFIG_USE_IRQ				/* Don't need IRQ/FIQ */
 
 /* Monitor configuration */
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index 371f32d8409..b258cb93c45 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -17,6 +17,13 @@
 #include <linux/sizes.h>
 
 #define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+#define CONFIG_DM_GPIO
+#define CONFIG_DM_SERIAL
+#define CONFIG_DM_SPI
+#define CONFIG_DM_SPI_FLASH
+
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
@@ -68,6 +75,7 @@
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
 #define CONFIG_FAT_WRITE
+#define CONFIG_CMD_FS_GENERIC
 
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
diff --git a/include/configs/hymod.h b/include/configs/hymod.h
deleted file mode 100644
index c973365e12c..00000000000
--- a/include/configs/hymod.h
+++ /dev/null
@@ -1,728 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Config header file for Hymod board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_HYMOD		1	/* ...on a Hymod board		*/
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define	CONFIG_SYS_TEXT_BASE	0x40000000
-
-#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
-
-#define CONFIG_BOARD_POSTCLK_INIT	/* have board_postclk_init() function */
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#define	CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef	CONFIG_CONS_NONE		/* define if console on something else*/
-#define	CONFIG_CONS_INDEX	1	/* which serial channel for console */
-#define	CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define	CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
-#define	CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define CONFIG_ETHER_INDEX	1	/* which channel for ether	*/
-#define CONFIG_ETHER_LOOPBACK_TEST	/* add ether external loopback test */
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-#if (CONFIG_ETHER_INDEX == 1)
-
-/*
- * - Rx-CLK is CLK10
- * - Tx-CLK is CLK11
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-# define MDIO_PORT		0		/* Port A */
-# define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
-					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-# define MDC_DECLARE		MDIO_DECLARE
-
-# define MDIO_DATA_PINMASK	0x00040000	/* Pin 13 */
-# define MDIO_CLCK_PINMASK	0x00080000	/* Pin 12 */
-
-#elif (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-# define MDIO_PORT		0		/* Port A */
-# define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
-					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-# define MDC_DECLARE		MDIO_DECLARE
-
-# define MDIO_DATA_PINMASK	0x00000040	/* Pin 25 */
-# define MDIO_CLCK_PINMASK	0x00000080	/* Pin 24 */
-
-#elif (CONFIG_ETHER_INDEX == 3)
-
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK16
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-# define MDIO_PORT		0		/* Port A */
-# define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
-					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-# define MDC_DECLARE		MDIO_DECLARE
-
-# define MDIO_DATA_PINMASK	0x00000100	/* Pin 23 */
-# define MDIO_CLCK_PINMASK	0x00000200	/* Pin 22 */
-
-#endif	/* CONFIG_ETHER_INDEX */
-
-#define CONFIG_MII			/* MII PHY management	*/
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
-
-#define MDIO_ACTIVE	(iop->pdir |=  MDIO_DATA_PINMASK)
-#define MDIO_TRISTATE	(iop->pdir &= ~MDIO_DATA_PINMASK)
-#define MDIO_READ	((iop->pdat &  MDIO_DATA_PINMASK) != 0)
-
-#define MDIO(bit)	if(bit) iop->pdat |=  MDIO_DATA_PINMASK; \
-			else	iop->pdat &= ~MDIO_DATA_PINMASK
-
-#define MDC(bit)	if(bit) iop->pdat |=  MDIO_CLCK_PINMASK; \
-			else	iop->pdat &= ~MDIO_CLCK_PINMASK
-
-#define MIIDELAY	udelay(1)
-
-#endif	/* CONFIG_ETHER_ON_FCC */
-
-
-/* other options */
-#define CONFIG_HARD_I2C		1	/* To enable I2C hardware support	*/
-#define CONFIG_DTT_ADM1021	1	/* ADM1021 temp sensor support */
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#ifdef DEBUG
-#define CONFIG_8260_CLKIN	33333333	/* in Hz */
-#else
-#define CONFIG_8260_CLKIN	66666666	/* in Hz */
-#endif
-
-#if defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		115200
-#else
-#define CONFIG_BAUDRATE		9600
-#endif
-
-/* default ip addresses - these will be overridden */
-#define CONFIG_IPADDR		192.168.1.1	/* hymod "boot" address */
-#define CONFIG_SERVERIP		192.168.1.254	/* hymod "server" address */
-
-#define CONFIG_LAST_STAGE_INIT
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_CDP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_KGDB
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PORTIO
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_XIMG
-
-#ifdef DEBUG
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#define CONFIG_BOOT_RETRY_TIME 30	/* retry autoboot after 30 secs	*/
-#define CONFIG_BOOT_RETRY_MIN	1	/* can go down to 1 second timeout */
-/* Be selective on what keys can delay or stop the autoboot process
- *	To stop use: " "
- */
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT		"Autobooting in %d seconds, " \
-					"press <SPACE> to stop\n", bootdelay
-#define CONFIG_AUTOBOOT_STOP_STR	" "
-#undef CONFIG_AUTOBOOT_DELAY_STR
-#define DEBUG_BOOTKEYS		0
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
-#define	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
-#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
-#define	CONFIG_KGDB_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define	CONFIG_KGDB_EXTC_RATE	3686400	/* serial ext clk rate in Hz */
-#define	CONFIG_KGDB_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
-# if defined(CONFIG_KGDB_USE_EXTC)
-#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
-# else
-#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
-# endif
-#endif
-
-#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
-
-#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
-
-/*
- * Hymod specific configurable options
- */
-#undef	CONFIG_SYS_HYMOD_DBLEDS			/* walk mezz board LEDs */
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x03c00000	/* 4 ... 60 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define	CONFIG_SYS_I2C_SPEED		50000
-#define	CONFIG_SYS_I2C_SLAVE		0x7e
-
-/* these are for the ST M24C02 2kbit serial i2c eeprom */
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4	/* 16 byte write page size */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CONFIG_SYS_I2C_MULTI_EEPROMS	1		/* hymod has two eeproms */
-
-#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* philips PCF8563 RTC address */
-
-/*
- * standard dtt sensor configuration - bottom bit will determine local or
- * remote sensor of the ADM1021, the rest determines index into
- * CONFIG_SYS_DTT_ADM1021 array below.
- *
- * On HYMOD board, the remote sensor should be connected to the MPC8260
- * temperature diode thingy, but an errata said this didn't work and
- * should be disabled - so it isn't connected.
- */
-#if 0
-#define CONFIG_DTT_SENSORS		{ 0, 1 }
-#else
-#define CONFIG_DTT_SENSORS		{ 0 }
-#endif
-
-/*
- * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
- * there will be one entry in this array for each two (dummy) sensors in
- * CONFIG_DTT_SENSORS.
- *
- * For HYMOD board:
- * - only one ADM1021
- * - i2c addr 0x2a (both ADD0 and ADD1 are N/C)
- * - conversion rate 0x02 = 0.25 conversions/second
- * - ALERT ouput disabled
- * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
- * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above)
- */
-#define CONFIG_SYS_DTT_ADM1021		{ { 0x2a, 0x02, 0, 1, 0, 85, 0, } }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#ifdef DEBUG
-#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
-			 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
-			 HRCW_MODCK_H0010)
-#else
-#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
-			 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
-			 HRCW_MODCK_H0101)
-#endif
-/* no slaves so just duplicate the master hrcw */
-#define CONFIG_SYS_HRCW_SLAVE1	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE2	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE3	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE4	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE5	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE6	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE7	CONFIG_SYS_HRCW_MASTER
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define	CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
-#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FPGA_BASE		0x80000000
-/*
- * unfortunately, CONFIG_SYS_MONITOR_LEN must include the
- * (very large i.e. 256kB) environment flash sector
- */
-#define	CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor*/
-#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max num of sects on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-#define	CONFIG_ENV_SIZE		0x40000	/* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE	0x40000	/* see README - env sect real size */
-#define	CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers			 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-				HID0_IFEM|HID0_ABE)
-#ifdef DEBUG
-#define CONFIG_SYS_HID0_FINAL	0
-#else
-#define CONFIG_SYS_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
-#endif
-#define CONFIG_SYS_HID2	0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register					 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#ifdef DEBUG
-#define CONFIG_SYS_RMR		0
-#else
-#define CONFIG_SYS_RMR		RMR_CSRE
-#endif
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration					 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR		(BCR_ETM)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC10|SIUMCR_L2CPC01|\
-			 SIUMCR_APPC10|SIUMCR_MMR11)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control			 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control					 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR	(SCCR_DFBRG01)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration				13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR	0
-
-/*
- * Init Memory Controller:
- *
- * Bank	Bus	Machine	PortSz	Device
- * ----	---	-------	------	------
- *  0	60x	GPCM	32 bit	FLASH
- *  1	60x	GPCM	32 bit	FLASH (same as 0 - unused for now)
- *  2	60x	SDRAM	64 bit	SDRAM
- *  3	Local	UPMC	 8 bit	Main Xilinx configuration
- *  4	Local	GPCM	32 bit	Main Xilinx register mode
- *  5	Local	UPMB	32 bit	Main Xilinx port mode
- *  6	Local	UPMC	 8 bit	Mezz Xilinx configuration
- */
-
-/*
- * Bank 0 - FLASH
- *
- * Quotes from the HYMOD IO Board Reference manual:
- *
- * "The flash memory is two Intel StrataFlash chips, each configured for
- *  16 bit operation and connected to give a 32 bit wide port."
- *
- * "The chip select logic is configured to respond to both *CS0 and *CS1.
- *  Therefore the FLASH memory will be mapped to both bank 0 and bank 1.
- *  It is suggested that bank 0 be read-only and bank 1 be read/write. The
- *  FLASH will then appear as ROM during boot."
- *
- * Initially, we are only going to use bank 0 in read/write mode.
- */
-
-/* 32 bit, read-write, GPCM on 60x bus */
-#define	CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE&BRx_BA_MSK)|\
-				BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
-/* up to 32 Mb */
-#define	CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
-
-/*
- * Bank 2 - SDRAM
- *
- * Quotes from the HYMOD IO Board Reference manual:
- *
- * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a
- *  fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous
- *  dynamic random access memory organised as 4 banks by 4096 rows by 512
- *  columns by 16 bits. Four chips provide a 64-bit port on the 60x bus."
- *
- * "The locations in SDRAM are accessed using multiplexed address pins to
- *  specify row and column. The pins also act to specify commands. The state
- *  of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP
- *  pin may function as a row address or as the AUTO PRECHARGE control line,
- *  depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260
- *  address lines to be configured to the required multiplexing scheme."
- */
-
-#define CONFIG_SYS_SDRAM_SIZE	64
-
-/* 64 bit, read-write, SDRAM on 60x bus */
-#define	CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM_BASE&BRx_BA_MSK)|\
-				BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
-/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
-#define	CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)|\
-				ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
-
-/*
- * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows:
- *
- * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5
- * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16
- * as bank select, A7 is output on SDA10 during an ACTIVATE command,
- * earliest timing for ACTIVATE command after REFRESH command is 6 clocks,
- * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE
- * command is 2 clocks, earliest timing for PRECHARGE after last data
- * was read is 1 clock, earliest timing for PRECHARGE after last data
- * was written is 1 clock, CAS Latency is 2.
- */
-
-#define CONFIG_SYS_PSDMR	(PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
-				PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
-				PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
-				PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
-				PSDMR_WRC_1C|PSDMR_CL_2)
-
-/*
- * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh
- * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register
- * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer
- * Prescaler, hence the P instead of the R). The refresh timer period is given
- * by (note that there was a change in the 8260 UM Errata):
- *
- *	TimerPeriod = (PSRT + 1) / Fmptc
- *
- * where Fmptc is the BusClock divided by PTP. i.e.
- *
- *	TimerPeriod = (PSRT + 1) / (BusClock / PTP)
- *
- * or
- *
- *	TImerPeriod = (PTP * (PSRT + 1)) / BusClock
- *
- * The requirement for the Toshiba TC59SM716FTL-10 is that there must be
- * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096
- * = 15.625 usecs.
- *
- * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32
- * appear to be reasonable.
- */
-
-#ifdef DEBUG
-#define CONFIG_SYS_PSRT	39
-#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV8
-#else
-#define CONFIG_SYS_PSRT	31
-#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV32
-#endif
-
-/*
- * Banks 3,4,5 and 6 - FPGA access
- *
- * Quotes from the HYMOD IO Board Reference manual:
- *
- * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made
- *  for configuring an optional FPGA on the mezzanine interface.
- *
- *  Access to the FPGAs may be divided into several catagories:
- *
- *  1. Configuration
- *  2. Register mode access
- *  3. Port mode access
- *
- *  The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be
- *  configured only (mode 1). Consequently there are four access types.
- *
- *  To improve interface performance and simplify software design, the four
- *  possible access types are separately mapped to different memory banks.
- *
- *  All are accessed using the local bus."
- *
- *	 Device		    Mode      Memory Bank Machine Port Size    Access
- *
- *	  Main		Configuration	   3	   UPMC	     8bit	R/W
- *	  Main		  Register	   4	   GPCM	    32bit	R/W
- *	  Main		    Port	   5	   UPMB	    32bit	R/W
- *	Mezzanine	Configuration	   6	   UPMC	     8bit	W/O
- *
- * "Note that mezzanine mode 1 access is write-only."
- */
-
-/* all the bank sizes must be a power of two, greater or equal to 32768 */
-#define FPGA_MAIN_CFG_BASE	(CONFIG_SYS_FPGA_BASE)
-#define FPGA_MAIN_CFG_SIZE	32768
-#define FPGA_MAIN_REG_BASE	(FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
-#define FPGA_MAIN_REG_SIZE	32768
-#define FPGA_MAIN_PORT_BASE	(FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE)
-#define FPGA_MAIN_PORT_SIZE	32768
-#define FPGA_MEZZ_CFG_BASE	(FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE)
-#define FPGA_MEZZ_CFG_SIZE	32768
-
-/* 8 bit, read-write, UPMC */
-#define	CONFIG_SYS_BR3_PRELIM	(FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
-/* up to 32Kbyte, burst inhibit */
-#define	CONFIG_SYS_OR3_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
-
-/* 32 bit, read-write, GPCM */
-#define	CONFIG_SYS_BR4_PRELIM	(FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
-/* up to 32Kbyte */
-#define	CONFIG_SYS_OR4_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
-
-/* 32 bit, read-write, UPMB */
-#define	CONFIG_SYS_BR5_PRELIM	(FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
-/* up to 32Kbyte */
-#define	CONFIG_SYS_OR5_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
-
-/* 8 bit, write-only, UPMC */
-#define	CONFIG_SYS_BR6_PRELIM	(FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
-/* up to 32Kbyte, burst inhibit */
-#define	CONFIG_SYS_OR6_PRELIM	(P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
-
-/*-----------------------------------------------------------------------
- * MBMR - Machine B Mode					10-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_MBMR	(MxMR_BSEL|MxMR_OP_NORM)	/* XXX - needs more */
-
-/*-----------------------------------------------------------------------
- * MCMR - Machine C Mode					10-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_MCMR	(MxMR_BSEL|MxMR_DSx_2_CYCL)	/* XXX - needs more */
-
-/*
- * FPGA I/O Port/Bit information
- */
-
-#define FPGA_MAIN_PROG_PORT	IOPIN_PORTA
-#define FPGA_MAIN_PROG_PIN	4	/* PA4 */
-#define FPGA_MAIN_INIT_PORT	IOPIN_PORTA
-#define FPGA_MAIN_INIT_PIN	5	/* PA5 */
-#define FPGA_MAIN_DONE_PORT	IOPIN_PORTA
-#define FPGA_MAIN_DONE_PIN	6	/* PA6 */
-
-#define FPGA_MEZZ_PROG_PORT	IOPIN_PORTA
-#define FPGA_MEZZ_PROG_PIN	0	/* PA0 */
-#define FPGA_MEZZ_INIT_PORT	IOPIN_PORTA
-#define FPGA_MEZZ_INIT_PIN	1	/* PA1 */
-#define FPGA_MEZZ_DONE_PORT	IOPIN_PORTA
-#define FPGA_MEZZ_DONE_PIN	2	/* PA2 */
-#define FPGA_MEZZ_ENABLE_PORT	IOPIN_PORTA
-#define FPGA_MEZZ_ENABLE_PIN	3	/* PA3 */
-
-/*
- * FPGA Interrupt configuration
- */
-#define FPGA_MAIN_IRQ		SIU_INT_IRQ2
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		""
-#define MTDPARTS_DEFAULT	""
-*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 52fe9cf4374..5a5f9400c3d 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -46,7 +46,7 @@
 #if defined(CONFIG_SPL_MMC_SUPPORT)
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	138 /* offset 69KB */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	800 /* 400 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION	1
 #define CONFIG_SYS_MONITOR_LEN  (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024)
 #endif
 
@@ -58,7 +58,7 @@
 
 /* Define the payload for FAT/EXT support */
 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME  "u-boot.img"
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME  "u-boot.img"
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #endif
 
diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index 3502d104720..7c8065ad187 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -34,4 +34,15 @@
 /* NAND Configuration */
 #define CONFIG_SYS_NAND_PAGE_2K
 
+/* Network */
+#define CONFIG_DRIVER_TI_KEYSTONE_NET
+#define CONFIG_TI_KSNAV
+#define CONFIG_KSNAV_PKTDMA_NETCP
+#define CONFIG_KSNET_NETCP_V1_5
+#define CONFIG_KSNET_CPSW_NUM_PORTS	9
+#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
+
+/* SerDes */
+#define CONFIG_TI_KEYSTONE_SERDES
+
 #endif /* __CONFIG_K2E_EVM_H */
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index 8aa616da0e0..034cbfd4d78 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -36,5 +36,12 @@
 
 /* Network */
 #define CONFIG_DRIVER_TI_KEYSTONE_NET
+#define CONFIG_TI_KSNAV
+#define CONFIG_KSNAV_PKTDMA_NETCP
+#define CONFIG_KSNET_NETCP_V1_0
+#define CONFIG_KSNET_CPSW_NUM_PORTS	5
+
+/* SerDes */
+#define CONFIG_TI_KEYSTONE_SERDES
 
 #endif /* __CONFIG_K2HK_EVM_H */
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
new file mode 100644
index 00000000000..0e1f7251b3a
--- /dev/null
+++ b/include/configs/k2l_evm.h
@@ -0,0 +1,37 @@
+/*
+ * Configuration header file for TI's k2l-evm
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_K2L_EVM_H
+#define __CONFIG_K2L_EVM_H
+
+/* Platform type */
+#define CONFIG_SOC_K2L
+#define CONFIG_K2L_EVM
+
+/* U-Boot general configuration */
+#define CONFIG_SYS_PROMPT		"K2L EVM # "
+
+#define KS2_ARGS_UBI   "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
+		       "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0"
+
+#define KS2_FDT_NAME	"name_fdt=k2l-evm.dtb\0"
+#define KS2_ADDR_MON	"addr_mon=0x0c140000\0"
+#define KS2_NAME_MON	"name_mon=skern-k2l-evm.bin\0"
+#define NAME_UBOOT	"name_uboot=u-boot-spi-k2l-evm.gph\0"
+#define NAME_UBI	"name_ubi=k2l-evm-ubifs.ubi\0"
+
+#include <configs/ks2_evm.h>
+
+/* SPL SPI Loader Configuration */
+#define CONFIG_SPL_TEXT_BASE		0x0c100000
+
+/* NAND Configuration */
+#define CONFIG_SYS_NAND_PAGE_4K
+
+#endif /* __CONFIG_K2L_EVM_H */
diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
index 51926f721f1..b0c91d8dcb5 100644
--- a/include/configs/ks2_evm.h
+++ b/include/configs/ks2_evm.h
@@ -23,7 +23,6 @@
 #define CONFIG_ARMV7
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_SYS_ARCH_TIMER
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_TEXT_BASE		0x0c001000
 #define CONFIG_SPL_TARGET		"u-boot-spi.gph"
 #define CONFIG_SYS_DCACHE_OFF
@@ -92,6 +91,8 @@
 #define CONFIG_SYS_SPI2_NUM_CS		4
 
 /* Network Configuration */
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MARVELL
 #define CONFIG_MII
 #define CONFIG_BOOTP_DEFAULT
 #define CONFIG_BOOTP_DNS
@@ -99,11 +100,46 @@
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_NET_RETRY_COUNT		32
 #define CONFIG_NET_MULTI
-#define CONFIG_GET_LINK_STATUS_ATTEMPTS	5
 #define CONFIG_SYS_SGMII_REFCLK_MHZ	312
 #define CONFIG_SYS_SGMII_LINERATE_MHZ	1250
 #define CONFIG_SYS_SGMII_RATESCALE	2
 
+/* Keyston Navigator Configuration */
+#define CONFIG_KSNAV_QM_BASE_ADDRESS		KS2_QM_BASE_ADDRESS
+#define CONFIG_KSNAV_QM_CONF_BASE		KS2_QM_CONF_BASE
+#define CONFIG_KSNAV_QM_DESC_SETUP_BASE		KS2_QM_DESC_SETUP_BASE
+#define CONFIG_KSNAV_QM_STATUS_RAM_BASE		KS2_QM_STATUS_RAM_BASE
+#define CONFIG_KSNAV_QM_INTD_CONF_BASE		KS2_QM_INTD_CONF_BASE
+#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE		KS2_QM_PDSP1_CMD_BASE
+#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE		KS2_QM_PDSP1_CTRL_BASE
+#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE		KS2_QM_PDSP1_IRAM_BASE
+#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE	KS2_QM_MANAGER_QUEUES_BASE
+#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE	KS2_QM_MANAGER_Q_PROXY_BASE
+#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE	KS2_QM_QUEUE_STATUS_BASE
+#define CONFIG_KSNAV_QM_LINK_RAM_BASE		KS2_QM_LINK_RAM_BASE
+#define CONFIG_KSNAV_QM_REGION_NUM		KS2_QM_REGION_NUM
+#define CONFIG_KSNAV_QM_QPOOL_NUM		KS2_QM_QPOOL_NUM
+
+/* NETCP pktdma */
+#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE	KS2_NETCP_PDMA_CTRL_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE		KS2_NETCP_PDMA_TX_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM	KS2_NETCP_PDMA_TX_CH_NUM
+#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE		KS2_NETCP_PDMA_RX_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM	KS2_NETCP_PDMA_RX_CH_NUM
+#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE	KS2_NETCP_PDMA_SCHED_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE	KS2_NETCP_PDMA_RX_FLOW_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM	KS2_NETCP_PDMA_RX_FLOW_NUM
+#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE	KS2_NETCP_PDMA_RX_FREE_QUEUE
+#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE	KS2_NETCP_PDMA_RX_RCV_QUEUE
+#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE	KS2_NETCP_PDMA_TX_SND_QUEUE
+
+/* Keystone net */
+#define CONFIG_KSNET_MAC_ID_BASE		KS2_MAC_ID_BASE_ADDR
+#define CONFIG_KSNET_NETCP_BASE			KS2_NETCP_BASE
+#define CONFIG_KSNET_SERDES_SGMII_BASE		KS2_SGMII_SERDES_BASE
+#define CONFIG_KSNET_SERDES_SGMII2_BASE		KS2_SGMII_SERDES2_BASE
+#define CONFIG_KSNET_SERDES_LANES_PER_SGMII	KS2_LANES_PER_SGMII_SERDES
+
 /* AEMIF */
 #define CONFIG_TI_AEMIF
 #define CONFIG_AEMIF_CNTRL_BASE		KS2_AEMIF_CNTRL_BASE
@@ -154,6 +190,20 @@
 					"1024k(bootloader)ro,512k(params)ro," \
 					"-(ubifs)"
 
+/* USB Configuration */
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_KEYSTONE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_FS_FAT
+#define CONFIG_SYS_CACHELINE_SIZE		64
+#define CONFIG_USB_SS_BASE			KS2_USB_SS_BASE
+#define CONFIG_USB_HOST_XHCI_BASE		KS2_USB_HOST_XHCI_BASE
+#define CONFIG_DEV_USB_PHY_BASE			KS2_DEV_USB_PHY_BASE
+#define CONFIG_USB_PHY_CFG_BASE			KS2_USB_PHY_CFG_BASE
+
 /* U-Boot command configuration */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_ASKENV
@@ -167,9 +217,11 @@
 #define CONFIG_CMD_UBIFS
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_USB
 
 /* U-Boot general configuration */
 #define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_MISC_INIT_R
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SYS_PBSIZE		2048
 #define CONFIG_SYS_MAXARGS		16
@@ -266,8 +318,4 @@
 #include <asm/arch/clock.h>
 #define CONFIG_SYS_HZ_CLOCK		clk_get_rate(KS2_CLK1_6)
 
-/* Maximum memory size for relocated U-boot at the end of the DDR3 memory
-   which is NOT applicable for DDR ECC test */
-#define CONFIG_MAX_UBOOT_MEM_SIZE	(4 << 20)	/* 4 MiB */
-
 #endif /* __CONFIG_KS2_EVM_H */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index bb478133453..d1f6ea7e7b0 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -69,6 +69,7 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_SYS_HAS_SERDES
 
+#define CONFIG_FSL_CAAM			/* Enable CAAM */
 /*
  * IFC Definitions
  */
@@ -359,7 +360,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_MEMTEST_END		0x9fffffff
 
 #define CONFIG_SYS_LOAD_ADDR		0x82000000
-#define CONFIG_SYS_HZ			1000
 
 /*
  * Stack sizes
@@ -388,4 +388,14 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_OF_BOARD_SETUP
 #define CONFIG_CMD_BOOTZ
 
+#define CONFIG_MISC_INIT_R
+
+/* Hash command with SHA acceleration supported in hardware */
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 45b2272ff5b..3c73af8ac39 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -48,6 +48,8 @@
 
 #define CONFIG_SYS_HAS_SERDES
 
+#define CONFIG_FSL_CAAM			/* Enable CAAM */
+
 /*
  * IFC Definitions
  */
@@ -259,7 +261,6 @@
 #define CONFIG_SYS_MEMTEST_END		0x9fffffff
 
 #define CONFIG_SYS_LOAD_ADDR		0x82000000
-#define CONFIG_SYS_HZ			1000
 
 /*
  * Stack sizes
@@ -288,4 +289,14 @@
 #define CONFIG_OF_BOARD_SETUP
 #define CONFIG_CMD_BOOTZ
 
+#define CONFIG_MISC_INIT_R
+
+/* Hash command with SHA acceleration supported in hardware */
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index a72e1f3567d..6fe032c9ff6 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -253,8 +253,6 @@
 
 #define CONFIG_NR_DRAM_BANKS		3
 
-#define CONFIG_SYS_HZ			1000
-
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		128
 
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
new file mode 100644
index 00000000000..72217bdb574
--- /dev/null
+++ b/include/configs/maxbcm.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_DB_MV7846MP_GP_H
+#define _CONFIG_DB_MV7846MP_GP_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_ARMADA_XP		/* SOC Family Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define	CONFIG_SYS_TEXT_BASE	0x04000000
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TFTPPUT
+#define CONFIG_CMD_TIME
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE		MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED		1000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+#define CONFIG_SPI_FLASH_STMICRO
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
+
+#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
+#define CONFIG_PHY_BASE_ADDR	0x0
+#define CONFIG_SYS_NETA_INTERFACE_TYPE	PHY_INTERFACE_MODE_SGMII
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+#define CONFIG_RESET_PHY_R
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
+#define CONFIG_SYS_ALT_MEMTEST
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#endif /* _CONFIG_DB_MV7846MP_GP_H */
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index cd85a6c9e89..b775ebd0ede 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -172,9 +172,6 @@
 
 #define CONFIG_BOOTFILE		"uImage"
 
-#define xstr(s)	str(s)
-#define str(s)	#s
-
 /* Setup MTD for NAND on the SOM */
 #define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
 #define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO),"	\
@@ -201,13 +198,13 @@
 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
 	"baudrate=115200\0"						\
 	"consoledev=ttyO2\0"						\
-	"hostname=" xstr(CONFIG_HOSTNAME) "\0"				\
+	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
 	"loadaddr=0x82000000\0"						\
 	"load=tftp ${loadaddr} ${u-boot}\0"				\
 	"load_k=tftp ${loadaddr} ${bootfile}\0"				\
 	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0"			\
 	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
-	"mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0"				\
+	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
 	"mmcargs=root=/dev/mmcblk0p2 rw "				\
 		"rootfstype=ext3 rootwait\0"				\
 	"mmcboot=echo Booting from mmc ...; "				\
@@ -221,7 +218,7 @@
 		"bootm ${loadaddr}\0"					\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
-	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0"			\
+	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
 	"uboot_addr=0x80000\0"						\
 	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
 		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
@@ -372,8 +369,8 @@
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
 
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
 
 /* NAND boot config */
 #define CONFIG_SYS_NAND_PAGE_COUNT	64
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index 6c19817f86a..0b9cbae5bad 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -15,6 +15,9 @@
 #define __CONFIG_H
 
 #define CONFIG_MECP5123 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
+
 /*
  * Memory map for the MECP5123 board:
  *
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index 7de245b33cb..41ae0a53f89 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -12,6 +12,9 @@
 #define __CONFIG_H
 
 #define CONFIG_MPC5121ADS 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
+
 /*
  * Memory map for the MPC5121ADS board:
  *
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index eb96fc17f3e..dea8227aeb7 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -148,7 +148,8 @@
 
 /* I2C */
 #ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MXS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXS
 #define CONFIG_HARD_I2C
 #ifndef CONFIG_SYS_I2C_SPEED
 #define CONFIG_SYS_I2C_SPEED		400000
diff --git a/include/configs/o2d.h b/include/configs/o2d.h
index eff1bcef3b5..b2905b2697f 100644
--- a/include/configs/o2d.h
+++ b/include/configs/o2d.h
@@ -43,8 +43,8 @@
 
 #define CONFIG_BOARD_NAME		"o2d"
 #define CONFIG_BOARD_BOOTCMD		"run dhcp_boot"
-#define CONFIG_BOARD_MEM_LIMIT		xstr(126)
-#define BOARD_POST_CRC32_END		xstr(0x01000000)
+#define CONFIG_BOARD_MEM_LIMIT		__stringify(126)
+#define BOARD_POST_CRC32_END		__stringify(0x01000000)
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
@@ -56,7 +56,7 @@
 	"ramtop=fc55ffff\0"						\
 	"jffbot=fc560000\0"						\
 	"jfftop=fcffffff\0"						\
-	"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0"			\
+	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
 	"ubotop=fc03ffff\0"						\
 	"kernel_addr=0xfc060000\0"					\
 	"ramdisk_addr=0xfc160000\0"					\
diff --git a/include/configs/o2d300.h b/include/configs/o2d300.h
index 1af53834f75..a8222d9f97e 100644
--- a/include/configs/o2d300.h
+++ b/include/configs/o2d300.h
@@ -44,8 +44,8 @@
 
 #define CONFIG_BOARD_NAME		"o2d300"
 #define CONFIG_BOARD_BOOTCMD		"run dhcp_boot"
-#define CONFIG_BOARD_MEM_LIMIT		xstr(126)
-#define BOARD_POST_CRC32_END		xstr(0x02000000)
+#define CONFIG_BOARD_MEM_LIMIT		__stringify(126)
+#define BOARD_POST_CRC32_END		__stringify(0x02000000)
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
@@ -63,7 +63,7 @@
 	"ramtop=fc57ffff\0"						\
 	"jffbot=fc580000\0"						\
 	"jfftop=fd39ffff\0"						\
-	"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0"			\
+	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
 	"ubotop=fc03ffff\0"						\
 	"halname="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME"_halcon\0"	\
 	"halbot=fd3a0000\0"						\
diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h
index 133dc6f8cd1..183c4492848 100644
--- a/include/configs/o2dnt-common.h
+++ b/include/configs/o2dnt-common.h
@@ -114,9 +114,6 @@
 
 #undef	CONFIG_BOOTARGS
 
-#define xstr(s) str(s)
-#define str(s)  #s
-
 #if !defined(CONFIG_CONSOLE_DEV)
 #define CONFIG_CONSOLE_DEV	"ttyPSC1"
 #endif
@@ -158,7 +155,7 @@
 	"kernel_addr_r=600000\0"					\
 	"initrd_high=0x03e00000\0"					\
 	"memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0"			\
-	"memtest=mtest 0x00100000 "xstr(CONFIG_SYS_MEMTEST_END)" 0 1\0"	\
+	"memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \
 	"netdev=eth0\0"							\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
@@ -182,7 +179,7 @@
 	"unlock=yes\0"							\
 	"post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;"	\
 		"setenv bootdelay 1;"					\
-		"crc32 "xstr(CONFIG_SYS_TEXT_BASE)" "			\
+		"crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" "		\
 			BOARD_POST_CRC32_END";"				\
 		"setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0"
 
diff --git a/include/configs/o2dnt2.h b/include/configs/o2dnt2.h
index 3636c0e1d41..1b765a7e4e4 100644
--- a/include/configs/o2dnt2.h
+++ b/include/configs/o2dnt2.h
@@ -43,8 +43,8 @@
 
 #define CONFIG_BOARD_NAME		"o2dnt2"
 #define CONFIG_BOARD_BOOTCMD		"run flash_self"
-#define CONFIG_BOARD_MEM_LIMIT		xstr(126)
-#define BOARD_POST_CRC32_END		xstr(0x01000000)
+#define CONFIG_BOARD_MEM_LIMIT		__stringify(126)
+#define BOARD_POST_CRC32_END		__stringify(0x01000000)
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
@@ -56,7 +56,7 @@
 	"ramtop=fc55ffff\0"						\
 	"jffbot=fc560000\0"						\
 	"jfftop=fce5ffff\0"						\
-	"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0"			\
+	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
 	"ubotop=fc03ffff\0"						\
 	"calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0"	\
 	"calbot=fce60000\0"						\
diff --git a/include/configs/o2i.h b/include/configs/o2i.h
index 8fe1da58bb2..c0fcedaf10c 100644
--- a/include/configs/o2i.h
+++ b/include/configs/o2i.h
@@ -37,8 +37,8 @@
 
 #define CONFIG_BOARD_NAME		"o2i"
 #define CONFIG_BOARD_BOOTCMD		"run dhcp_boot"
-#define CONFIG_BOARD_MEM_LIMIT		xstr(62)
-#define BOARD_POST_CRC32_END		xstr(0x01000000)
+#define CONFIG_BOARD_MEM_LIMIT		__stringify(62)
+#define BOARD_POST_CRC32_END		__stringify(0x01000000)
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
@@ -52,7 +52,7 @@
 	"jfftop=ffebffff\0"						\
 	"kernel_addr=0xff060000\0"					\
 	"ramdisk_addr=0xff160000\0"					\
-	"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0"			\
+	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
 	"ubotop=ff03ffff\0"						\
 	"autoload=no\0"							\
 	"dhcp_boot=run dhcpcmd; run flash_mtd\0"			\
diff --git a/include/configs/o2mnt.h b/include/configs/o2mnt.h
index c2164b5efb4..eb63cb0c852 100644
--- a/include/configs/o2mnt.h
+++ b/include/configs/o2mnt.h
@@ -39,8 +39,8 @@
 
 #define CONFIG_BOARD_NAME		"o2mnt"
 #define CONFIG_BOARD_BOOTCMD		"${newcmd}"
-#define CONFIG_BOARD_MEM_LIMIT		xstr(62)
-#define BOARD_POST_CRC32_END		xstr(0x01000000)
+#define CONFIG_BOARD_MEM_LIMIT		__stringify(62)
+#define BOARD_POST_CRC32_END		__stringify(0x01000000)
 
 #ifndef CONFIG_IFM_SENSOR_TYPE
 #define CONFIG_IFM_SENSOR_TYPE		"O2M110"
@@ -56,7 +56,7 @@
 	"ramtop=ffc5ffff\0"						\
 	"jffbot=ffc60000\0"						\
 	"jfftop=ffffffff\0"						\
-	"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0"			\
+	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
 	"ubotop=ff03ffff\0"						\
 	"kernel_addr=0xff060000\0"					\
 	"ramdisk_addr=0xff260000\0"					\
diff --git a/include/configs/o3dnt.h b/include/configs/o3dnt.h
index 05cd3608159..77907507b30 100644
--- a/include/configs/o3dnt.h
+++ b/include/configs/o3dnt.h
@@ -44,8 +44,8 @@
 
 #define CONFIG_BOARD_NAME		"o3dnt"
 #define CONFIG_BOARD_BOOTCMD		"run flash_self"
-#define CONFIG_BOARD_MEM_LIMIT		xstr(62)
-#define BOARD_POST_CRC32_END		xstr(0x01000000)
+#define CONFIG_BOARD_MEM_LIMIT		__stringify(62)
+#define BOARD_POST_CRC32_END		__stringify(0x01000000)
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
@@ -57,7 +57,7 @@
 	"ramtop=fc55ffff\0"						\
 	"jffbot=fc560000\0"						\
 	"jfftop=fce5ffff\0"						\
-	"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0"			\
+	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
 	"ubotop=fc03ffff\0"						\
 	"calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0"	\
 	"calbot=fce60000\0"						\
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index b7638fb8a68..27bf89c114c 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -75,8 +75,8 @@
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
 
 /* Partition tables */
 #define CONFIG_EFI_PARTITION
diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h
index 50929aaea2c..2daf13c6422 100644
--- a/include/configs/omap3_evm_quick_mmc.h
+++ b/include/configs/omap3_evm_quick_mmc.h
@@ -87,7 +87,7 @@
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
 
 #endif /* __OMAP3_EVM_QUICK_MMC_H */
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index b17e495f5f7..c58636a5417 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -35,6 +35,13 @@
 /* TWL4030 LED */
 #define CONFIG_TWL4030_LED
 
+/* USB EHCI */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	183
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
+
 /* Initialize GPIOs by default */
 #define CONFIG_OMAP3_GPIO_2	/* GPIO32..63 is in GPIO Bank 2 */
 #define CONFIG_OMAP3_GPIO_3	/* GPIO64..95 is in GPIO Bank 3 */
@@ -44,6 +51,7 @@
 
 /* commands to include */
 #define CONFIG_CMD_CACHE
+#define CONFIG_CMD_USB
 #undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
 #undef CONFIG_CMD_IMI		/* iminfo			*/
 #undef CONFIG_CMD_NFS		/* NFS support			*/
@@ -131,8 +139,9 @@
 		"bootz ${loadaddr} - ${fdtaddr}\0" \
 	"nandboot=echo Booting from nand ...; " \
 		"run nandargs; " \
-		"nand read ${loadaddr} linux; " \
-		"bootm ${loadaddr}\0" \
+		"if nand read ${loadaddr} linux; then " \
+			"bootm ${loadaddr};" \
+		"fi;\0" \
 
 #define CONFIG_BOOTCOMMAND \
 	"mmc dev ${mmcdev}; if mmc rescan; then " \
diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h
deleted file mode 100644
index a210e293a9b..00000000000
--- a/include/configs/p3mx.h
+++ /dev/null
@@ -1,434 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Based on original work by
- *      Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards
- *
- * The defines:
- * CONFIG_P3M750 or
- * CONFIG_P3M7448
- * are written into include/config.h by the "make xxx_config" command
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_P3Mx			/* used for both board versions	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-#if defined (CONFIG_P3M750)
-#define CONFIG_750FX			/* 750GL/GX/FX			*/
-#define CONFIG_HIGH_BATS		/* High BATs supported		*/
-#define CONFIG_SYS_BOARD_NAME		"P3M750"
-#define CONFIG_SYS_BUS_CLK		100000000
-#define CONFIG_SYS_TCLK		100000000
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_74xx
-#define CONFIG_SYS_BOARD_NAME		"P3M7448"
-#define CONFIG_SYS_BUS_CLK		133333333
-#define CONFIG_SYS_TCLK		133333333
-#endif
-#define CONFIG_SYS_GT_DUAL_CPU			/* also for JTAG even with one cpu */
-
-/* which initialization functions to call for this board */
-#define CONFIG_SYS_BOARD_ASM_INIT	1
-#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
-#define CONFIG_MISC_INIT_R      1	/* Call misc_init_r()		*/
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#ifdef CONFIG_P3M750
-#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte	*/
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#if defined (CONFIG_P3M750)
-#define CONFIG_SYS_FLASH_BASE		0xff800000	/* start of flash banks	*/
-#define CONFIG_SYS_BOOT_SIZE		_8M		/* boot flash		*/
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of flash banks	*/
-#define CONFIG_SYS_BOOT_SIZE		_16M		/* boot flash		*/
-#endif
-#define CONFIG_SYS_BOOT_SPACE		CONFIG_SYS_FLASH_BASE	/* BOOT_CS0 flash 0    */
-#define CONFIG_SYS_MONITOR_BASE	0xfff00000
-#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
-#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
-
-#define CONFIG_SYS_DFL_GT_REGS		0xf1000000	/* boot time GT_REGS */
-#define CONFIG_SYS_GT_REGS		0xf1000000	/* GT Registers are mapped here */
-#define CONFIG_SYS_INT_SRAM_BASE	0x42000000	/* GT offers 256k internal SRAM */
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
- /*
- * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
- * To an unused memory region. The stack will remain in cache until RAM
- * is initialized
-*/
-#undef	CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0x42000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_MPSC			/* MV64460 Serial		*/
-#define CONFIG_MPSC_PORT	0
-#define CONFIG_BAUDRATE		115200	/* console baudrate		*/
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-/*-----------------------------------------------------------------------
- * Ethernet
- *----------------------------------------------------------------------*/
-/* Change the default ethernet port, use this define (options: 0, 1, 2) */
-#define CONFIG_SYS_ETH_PORT		ETH_0
-#define MV_ETH_DEVS		2
-#define CONFIG_PHY_RESET        1	/* reset phy upon startup         */
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible		*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver		*/
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection	*/
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-#if defined (CONFIG_P3M750)
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* one sector (1 device)		*/
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_ENV_SECT_SIZE	0x40000	/* two sectors (2 devices parallel	*/
-#endif
-#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_MV64460_ECC
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED		100000		/* I2C speed default	*/
-
-/* I2C RTC */
-#define CONFIG_RTC_M41T11	1
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR	1900	/* play along with linux	*/
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *----------------------------------------------------------------------*/
-#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#undef CONFIG_PCI			/* include pci support		*/
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-#define CONFIG_PCI_SCAN_SHOW		/* show devices on bus		*/
-#endif /* CONFIG_PCI */
-
-/* PCI MEMORY MAP section */
-#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
-#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
-#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
-
-#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
-#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
-
-/* PCI I/O MAP section */
-#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
-#define CONFIG_SYS_PCI0_IO_SIZE	_16M
-#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
-#define CONFIG_SYS_PCI1_IO_SIZE	_16M
-
-#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
-#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
-#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
-
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI_IDSEL 0x30
-
-#undef	CONFIG_BOOTARGS
-#define	CONFIG_EXTRA_ENV_SETTINGS_COMMON				\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-		"bootm\0"						\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"u-boot=p3mx/u-boot/u-boot.bin\0"				\
-	"load=tftp 100000 ${u-boot}\0"					\
-	"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;"	\
-		"cp.b 100000 fff00000 40000;"			        \
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
-	"serverip=11.0.0.152\0"
-
-#if defined (CONFIG_P3M750)
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_EXTRA_ENV_SETTINGS_COMMON				\
-	"hostname=p3m750\0"						\
-	"bootfile=/tftpboot/p3mx/vxWorks.st\0"				\
-	"kernel_addr=fc000000\0"					\
-	"ramdisk_addr=fc180000\0"					\
-	"vxfile=p3m750/vxWorks\0"					\
-	"vxuser=ddg\0"							\
-	"vxpass=ddg\0"							\
-	"vxtarget=target\0"						\
-	"vxflags=0x8\0"							\
-	"vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} "	\
-		"e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} "	\
-		"f=${vxflags}\0"
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_EXTRA_ENV_SETTINGS_COMMON				\
-	"hostname=p3m7448\0"
-#endif
-
-#if defined (CONFIG_P3M750)
-#define CONFIG_BOOTCOMMAND	"tftp;run vxargs;bootvx"
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_BOOTCOMMAND	" "
-#endif
-
-#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_SDRAM
-
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_HUSH_PARSER
-
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on	        */
-#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x08000000	/* default load address */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-/*-----------------------------------------------------------------------
- * Marvell MV64460 config settings
- *----------------------------------------------------------------------*/
-/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */
-#if defined (CONFIG_P3M750)
-#define CONFIG_SYS_BOOT_PAR		0x8FDFF87F	/* 16 bit flash, disable burst*/
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_SYS_BOOT_PAR		0x8FEFFFFF	/* 32 bit flash, burst enabled */
-#endif
-
-/*
- * MPP[0]	Serial Port 0 TxD	TxD	OUT	Connected to P14 (buffered)
- * MPP[1]	Serial Port 0 RxD	RxD	IN	Connected to P14 (buffered)
- * MPP[2]	NC
- * MPP[3]	Serial Port 1 TxD	TxD	OUT	Connected to P14 (buffered)
- * MPP[4]	PCI Monarch#		GPIO	IN	Connected to P12
- * MPP[5]	Serial Port 1 RxD	RxD	IN	Connected to P14 (buffered)
- * MPP[6]	PMC Carrier Interrupt 0	Int	IN	Connected to P14
- * MPP[7]	PMC Carrier Interrupt 1	Int	IN	Connected to P14
- * MPP[8]	Reserved				Do not use
- * MPP[9]	Reserved				Do not use
- * MPP[10]	Reserved				Do not use
- * MPP[11]	Reserved				Do not use
- * MPP[12]	Phy 0 Interrupt		Int	IN
- * MPP[13]	Phy 1 Interrupt		Int	IN
- * MPP[14]	NC
- * MPP[15]	NC
- * MPP[16]	PCI Interrupt C		Int	IN	Connected to P11
- * MPP[17]	PCI Interrupt D		Int	IN	Connected to P11
- * MPP[18]	Watchdog NMI#		GPIO	IN	Connected to MPP[24]
- * MPP[19]	Watchdog Expired#	WDE	OUT	Connected to rst logic
- * MPP[20]	Watchdog Status		WD_STS	IN	Read back of rst by watchdog
- * MPP[21]	NC
- * MPP[22]	GP LED Green		GPIO	OUT
- * MPP[23]	GP LED Red		GPIO	OUT
- * MPP[24]	Watchdog NMI#		Int	OUT
- * MPP[25]	NC
- * MPP[26]	NC
- * MPP[27]	PCI Interrupt A		Int	IN	Connected to P11
- * MPP[28]	NC
- * MPP[29]	PCI Interrupt B		Int	IN	Connected to P11
- * MPP[30]	Module reset		GPIO	OUT	Board reset
- * MPP[31]	PCI EReady		GPIO	IN	Connected to P12
- */
-#define CONFIG_SYS_MPP_CONTROL_0	0x00303022
-#define CONFIG_SYS_MPP_CONTROL_1	0x00000000
-#define CONFIG_SYS_MPP_CONTROL_2	0x00004000
-#define CONFIG_SYS_MPP_CONTROL_3	0x00000004
-#define CONFIG_SYS_GPP_LEVEL_CONTROL	0x280730D0
-
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* init ram */
-#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-
-/* PCI0, PCI1 in one BAT */
-#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* set rest out of range for Linux !!!!!!!!!!! */
-
-/* IBAT5 and DBAT5 */
-#define CONFIG_SYS_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-/* IBAT6 and DBAT6 */
-#define CONFIG_SYS_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-/* IBAT7 and DBAT7 */
-#define CONFIG_SYS_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_VXWORKS_MAC_PTR	0x42010000 /* use some memory in SRAM that's not used!!! */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
- */
-#define CONFIG_SYS_L2
-
-#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
-#define L2_INIT 0
-#else
-#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-#endif
-
-#define L2_ENABLE	(L2_INIT | L2CR_L2E)
-
-#ifndef __ASSEMBLY__
-#include <../board/Marvell/include/core.h>
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index f92496571ba..1c04a58e9fe 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -29,8 +29,6 @@
 #endif
 #endif
 
-#define CONFIG_SYS_LITTLE_ENDIAN
-
 #define CONFIG_ETHADDR		DE:AD:BE:EF:01:01    /* Ethernet address */
 
 #define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h
index 553eb8f9672..17d7bcab008 100644
--- a/include/configs/pdm360ng.h
+++ b/include/configs/pdm360ng.h
@@ -13,6 +13,8 @@
 #define __CONFIG_H
 
 #define CONFIG_PDM360NG 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
 
 /*
  * Memory map for the PDM360NG board:
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index ab8ac60df23..91bd37d6bca 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h
@@ -38,6 +38,7 @@
 
 #define CONFIG_POWER_TPS65090_EC
 #define CONFIG_CROS_EC_SPI		/* Support CROS_EC over SPI */
+#define CONFIG_DM_CROS_EC
 
 #define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_EXYNOS
diff --git a/include/configs/ph1_ld4.h b/include/configs/ph1_ld4.h
index a28d7b579a6..005a853f568 100644
--- a/include/configs/ph1_ld4.h
+++ b/include/configs/ph1_ld4.h
@@ -28,14 +28,10 @@
  *   SoC UART     : enable CONFIG_UNIPHIER_SERIAL
  *   On-board UART: enable CONFIG_SYS_NS16550_SERIAL
  */
-#if 1
-#define CONFIG_UNIPHIER_SERIAL
-#else
+#if 0
 #define CONFIG_SYS_NS16550_SERIAL
 #endif
 
-#define CONFIG_SYS_UNIPHIER_UART_CLK    36864000
-
 #define CONFIG_SMC911X
 
 #define CONFIG_DDR_NUM_CH0 1
diff --git a/include/configs/ph1_pro4.h b/include/configs/ph1_pro4.h
index b79967f7da4..7dd6fd2a929 100644
--- a/include/configs/ph1_pro4.h
+++ b/include/configs/ph1_pro4.h
@@ -28,14 +28,10 @@
  *   SoC UART     : enable CONFIG_UNIPHIER_SERIAL
  *   On-board UART: enable CONFIG_SYS_NS16550_SERIAL
  */
-#if 1
-#define CONFIG_UNIPHIER_SERIAL
-#else
+#if 0
 #define CONFIG_SYS_NS16550_SERIAL
 #endif
 
-#define CONFIG_SYS_UNIPHIER_UART_CLK    73728000
-
 #define CONFIG_SMC911X
 
 #define CONFIG_DDR_NUM_CH0 2
diff --git a/include/configs/ph1_sld8.h b/include/configs/ph1_sld8.h
index 9d391f1d74a..1062aace38a 100644
--- a/include/configs/ph1_sld8.h
+++ b/include/configs/ph1_sld8.h
@@ -28,14 +28,10 @@
  *   SoC UART     : enable CONFIG_UNIPHIER_SERIAL
  *   On-board UART: enable CONFIG_SYS_NS16550_SERIAL
  */
-#if 1
-#define CONFIG_UNIPHIER_SERIAL
-#else
+#if 0
 #define CONFIG_SYS_NS16550_SERIAL
 #endif
 
-#define CONFIG_SYS_UNIPHIER_UART_CLK    80000000
-
 #define CONFIG_SMC911X
 
 #define CONFIG_DDR_NUM_CH0 1
diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h
index 2d698094800..ca27f9ad787 100644
--- a/include/configs/rpi_b.h
+++ b/include/configs/rpi_b.h
@@ -31,6 +31,11 @@
  */
 #define CONFIG_MACH_TYPE		MACH_TYPE_BCM2708
 
+/* Enable driver model */
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+#define CONFIG_DM_GPIO
+
 /* Memory layout */
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
@@ -77,6 +82,16 @@
 #define CONFIG_MMC_SDHCI_IO_ACCESSORS
 #define CONFIG_BCM2835_SDHCI
 
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#define CONFIG_USB_DWC2_REG_ADDR 0x20980000
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MISC_INIT_R
+#endif
+
 /* Console UART */
 #define CONFIG_PL011_SERIAL
 #define CONFIG_PL011_CLOCK		3000000
@@ -124,13 +139,7 @@
 
 /* Some things don't make sense on this HW or yet */
 #undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
 #undef CONFIG_CMD_SAVEENV
-#undef CONFIG_CMD_DHCP
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_PING
 
 /* Environment */
 #define ENV_DEVICE_SETTINGS \
@@ -171,7 +180,10 @@
 	"ramdisk_addr_r=0x02100000\0" \
 
 #define BOOT_TARGET_DEVICES(func) \
-	func(MMC, mmc, 0)
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
 #include <config_distro_bootcmd.h>
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 0c6e9c78784..3633a355bd7 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -276,6 +276,8 @@
 #define CONFIG_SYS_I2C_SOFT_SPEED	50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
 #define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_INIT_BOARD
+
 #define CONFIG_SYS_MAX_I2C_BUS	7
 #define CONFIG_USB_GADGET
 #define CONFIG_USB_GADGET_S3C_UDC_OTG
@@ -286,4 +288,10 @@
 
 #define CONFIG_OF_LIBFDT
 
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+#define CONFIG_DM_GPIO
+#define CONFIG_DM_SERIAL
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 27f3d0af471..4b30d148c31 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -187,17 +187,7 @@
  * SPI Settings
  */
 #define CONFIG_SOFT_SPI
-#define CONFIG_SOFT_SPI_MODE SPI_MODE_3
-#define CONFIG_SOFT_SPI_GPIO_SCLK EXYNOS4_GPIO_Y31
-#define CONFIG_SOFT_SPI_GPIO_MOSI EXYNOS4_GPIO_Y33
-#define CONFIG_SOFT_SPI_GPIO_MISO EXYNOS4_GPIO_Y30
-#define CONFIG_SOFT_SPI_GPIO_CS EXYNOS4_GPIO_Y43
-
-#define SPI_DELAY udelay(1)
-#undef SPI_INIT
-#define SPI_SCL(bit) universal_spi_scl(bit)
-#define SPI_SDA(bit) universal_spi_sda(bit)
-#define SPI_READ universal_spi_read()
+
 #ifndef	__ASSEMBLY__
 void universal_spi_scl(int bit);
 void universal_spi_sda(int bit);
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index b5064ab37c0..2dee315f91e 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -259,7 +259,6 @@
 #define I2C_MOSI	0x00004000      /* PD 17: Master Out, Slave In */
 #define I2C_MISO	0x00008000      /* PD 16: Master In, Slave Out */
 
-#undef  SPI_INIT			/* no port initialization needed */
 #define SPI_READ        ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
 #define SPI_SDA(bit)    do {						\
 			if(bit) immr->im_ioport.iop_pdatd |=  I2C_MOSI; \
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
index 0dfb7e7918d..5b77db26985 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -230,8 +230,8 @@
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x400
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
 
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index c46baf254f1..dfbf3cb7861 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -276,8 +276,8 @@
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x400
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
 
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 69726432a3c..ee4b24473cd 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -32,6 +32,7 @@
 #define CONFIG_DM_GPIO
 #define CONFIG_DM_TEST
 #define CONFIG_DM_SERIAL
+#define CONFIG_DM_CROS_EC
 
 #define CONFIG_SYS_STDIO_DEREGISTER
 
@@ -97,8 +98,8 @@
 #define CONFIG_CMD_SF_TEST
 #define CONFIG_CMD_SPI
 #define CONFIG_SPI_FLASH
-#define CONFIG_OF_SPI
-#define CONFIG_OF_SPI_FLASH
+#define CONFIG_DM_SPI
+#define CONFIG_DM_SPI_FLASH
 #define CONFIG_SPI_FLASH_ATMEL
 #define CONFIG_SPI_FLASH_EON
 #define CONFIG_SPI_FLASH_GIGADEVICE
@@ -172,6 +173,7 @@
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define LCD_BPP			LCD_COLOR16
+#define CONFIG_LCD_BMP_RLE8
 
 #define CONFIG_CROS_EC_KEYB
 #define CONFIG_KEYBOARD
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 1ce0965912b..0d5dba18b1f 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -148,8 +148,8 @@
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
 
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_FS_FAT
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index 22835ffd640..982d0dcea39 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -223,4 +223,10 @@
 
 #define CONFIG_OF_LIBFDT
 
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+#define CONFIG_DM_GPIO
+#define CONFIG_DM_SERIAL
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 49504dcafbc..83a1bcdfbe3 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -22,7 +22,7 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_MISC_INIT_R
+#define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_CLOCKS
 
@@ -157,6 +157,21 @@
 #define CONFIG_BAUDRATE			115200
 
 /*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#define CONFIG_USB_STORAGE
+/*
+ * NOTE: User must define either of the following to select which
+ *       of the two USB controllers available on SoCFPGA to use.
+ *       The DWC2 driver doesn't support multiple USB controllers.
+ * #define CONFIG_USB_DWC2_REG_ADDR	SOCFPGA_USB0_ADDRESS
+ * #define CONFIG_USB_DWC2_REG_ADDR	SOCFPGA_USB1_ADDRESS
+ */
+#endif
+
+/*
  * U-Boot environment
  */
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
@@ -167,16 +182,21 @@
 
 /*
  * SPL
+ *
+ * SRAM Memory layout:
+ *
+ * 0xFFFF_0000 ...... Start of SRAM
+ * 0xFFFF_xxxx ...... Top of stack (grows down)
+ * 0xFFFF_yyyy ...... Malloc area
+ * 0xFFFF_zzzz ...... Global Data
+ * 0xFFFF_FF00 ...... End of SRAM
  */
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_RAM_DEVICE
-#define CONFIG_SPL_TEXT_BASE		0xFFFF0000
-#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SPL_STACK_SIZE		(4 * 1024)
-#define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)	/* FIXME */
-#define CONFIG_SYS_SPL_MALLOC_START	((unsigned long) (&__malloc_start))
-#define CONFIG_SYS_SPL_MALLOC_SIZE	(&__malloc_end - &__malloc_start)
+#define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_SPL_MALLOC_START	CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(5 * 1024)
 
 #define CHUNKSZ_CRC32			(1 * 1024)	/* FIXME: ewww */
 #define CONFIG_CRC32_VERIFY
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 60d7e20e83b..942738c138b 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -55,10 +55,8 @@
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_EMAC_BASE		SOCFPGA_EMAC1_ADDRESS
 #define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
-#define CONFIG_EPHY0_PHY_ADDR		0
 
 /* PHY */
-#define CONFIG_EPHY1_PHY_ADDR		4
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9021
 #define CONFIG_KSZ9021_CLK_SKEW_ENV	"micrel-ksz9021-clk-skew"
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index c0eba3721d7..a11f4ed2e18 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -37,8 +37,8 @@
 #define CONFIG_EXTRA_ENV_USBTTY			"usbtty=cdc_acm\0"
 
 /* I2C driver configuration */
-#define CONFIG_HARD_I2C
-#define CONFIG_DW_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DW
 #if defined(CONFIG_SPEAR600)
 #define CONFIG_SYS_I2C_BASE			0xD0200000
 #elif defined(CONFIG_SPEAR300)
diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h
index 5611ecc85f2..e0ec52dcde7 100644
--- a/include/configs/sun4i.h
+++ b/include/configs/sun4i.h
@@ -11,10 +11,10 @@
 /*
  * A10 specific configuration
  */
-#define CONFIG_SUN4I		/* sun4i SoC generation */
 #define CONFIG_CLK_FULL_SPEED		1008000000
 
 #define CONFIG_SYS_PROMPT		"sun4i# "
+#define CONFIG_MACH_TYPE		4104
 
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h
index 6066371a17d..09f7533575c 100644
--- a/include/configs/sun5i.h
+++ b/include/configs/sun5i.h
@@ -11,10 +11,10 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_SUN5I		/* sun5i SoC generation */
 #define CONFIG_CLK_FULL_SPEED		1008000000
 
 #define CONFIG_SYS_PROMPT		"sun5i# "
+#define CONFIG_MACH_TYPE		4138
 
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h
new file mode 100644
index 00000000000..b7144745c92
--- /dev/null
+++ b/include/configs/sun6i.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ * (C) Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * Configuration settings for the Allwinner A31 (sun6i) CPU
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A31 specific configuration
+ */
+
+#define CONFIG_SYS_PROMPT		"sun6i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index a902b845744..0193826a9dd 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -12,10 +12,10 @@
 /*
  * A20 specific configuration
  */
-#define CONFIG_SUN7I		/* sun7i SoC generation */
 #define CONFIG_CLK_FULL_SPEED		912000000
 
 #define CONFIG_SYS_PROMPT		"sun7i# "
+#define CONFIG_MACH_TYPE		4283
 
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
new file mode 100644
index 00000000000..6f1fc48cf02
--- /dev/null
+++ b/include/configs/sun8i.h
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2014 Chen-Yu Tsai <wens@csie.org>
+ *
+ * Configuration settings for the Allwinner A23 (sun8i) CPU
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A23 specific configuration
+ */
+#define CONFIG_SYS_PROMPT	"sun8i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 1d947d7d9ea..ce038eddf04 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -27,6 +27,14 @@
 
 #define CONFIG_SYS_TEXT_BASE		0x4a000000
 
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
+# define CONFIG_CMD_DM
+# define CONFIG_DM_GPIO
+# define CONFIG_DM_SERIAL
+# define CONFIG_DW_SERIAL
+# define CONFIG_SYS_MALLOC_F_LEN	(1 << 10)
+#endif
+
 /*
  * Display CPU information
  */
@@ -36,12 +44,15 @@
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 /* ns16550 reg in the low bits of cpu reg */
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
 #define CONFIG_SYS_NS16550_CLK		24000000
-#define CONFIG_SYS_NS16550_COM1		SUNXI_UART0_BASE
-#define CONFIG_SYS_NS16550_COM2		SUNXI_UART1_BASE
-#define CONFIG_SYS_NS16550_COM3		SUNXI_UART2_BASE
-#define CONFIG_SYS_NS16550_COM4		SUNXI_UART3_BASE
+#ifndef CONFIG_DM_SERIAL
+# define CONFIG_SYS_NS16550_REG_SIZE	-4
+# define CONFIG_SYS_NS16550_COM1		SUNXI_UART0_BASE
+# define CONFIG_SYS_NS16550_COM2		SUNXI_UART1_BASE
+# define CONFIG_SYS_NS16550_COM3		SUNXI_UART2_BASE
+# define CONFIG_SYS_NS16550_COM4		SUNXI_UART3_BASE
+# define CONFIG_SYS_NS16550_COM5		SUNXI_R_UART_BASE
+#endif
 
 /* DRAM Base */
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
@@ -77,6 +88,7 @@
 #define CONFIG_INITRD_TAG
 
 /* mmc config */
+#if !defined(CONFIG_UART0_PORT_F)
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_MMC
@@ -84,6 +96,7 @@
 #define CONFIG_MMC_SUNXI_SLOT		0
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0	/* first detected MMC controller */
+#endif
 
 /* 4MB of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))
@@ -92,8 +105,8 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_CMD_ECHO
-#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE	384	/* Print Buffer Size */
+#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE	1024	/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 #define CONFIG_SYS_GENERIC_BOARD
 
@@ -105,8 +118,6 @@
 /* standalone support */
 #define CONFIG_STANDALONE_LOAD_ADDR	0x42000000
 
-#define CONFIG_SYS_HZ			1000
-
 /* baudrate */
 #define CONFIG_BAUDRATE			115200
 
@@ -183,6 +194,7 @@
 
 /* GPIO */
 #define CONFIG_SUNXI_GPIO
+#define CONFIG_SPL_GPIO_SUPPORT
 #define CONFIG_CMD_GPIO
 
 /* Ethernet support */
@@ -227,16 +239,28 @@
 	"pxefile_addr_r=0x43200000\0" \
 	"ramdisk_addr_r=0x43300000\0"
 
+#ifdef CONFIG_MMC
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
 #ifdef CONFIG_AHCI
 #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
 #else
 #define BOOT_TARGET_DEVICES_SCSI(func)
 #endif
 
+#ifdef CONFIG_USB_EHCI
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
 #define BOOT_TARGET_DEVICES(func) \
-	func(MMC, mmc, 0) \
+	BOOT_TARGET_DEVICES_MMC(func) \
 	BOOT_TARGET_DEVICES_SCSI(func) \
-	func(USB, usb, 0) \
+	BOOT_TARGET_DEVICES_USB(func) \
 	func(PXE, pxe, na) \
 	func(DHCP, dhcp, na)
 
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index 8d2db27ecb9..d687717dfb8 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -305,8 +305,8 @@
 
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
 
 #define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index 23e3c8af31a..c3ad8beb903 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -59,7 +59,7 @@
 	BOARD_EXTRA_ENV_SETTINGS
 
 #if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI)
-#define CONFIG_FDT_SPI
+#define CONFIG_TEGRA_SPI
 #endif
 
 /* overrides for SPL build here */
@@ -67,10 +67,6 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-/* remove devicetree support */
-#ifdef CONFIG_OF_CONTROL
-#endif
-
 /* remove I2C support */
 #ifdef CONFIG_SYS_I2C_TEGRA
 #undef CONFIG_SYS_I2C_TEGRA
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 834b3d5686c..5d2b12a11d1 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -24,6 +24,8 @@
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_DM_SERIAL
 #endif
+#define CONFIG_DM_SPI
+#define CONFIG_DM_SPI_FLASH
 
 #define CONFIG_SYS_TIMER_RATE		1000000
 #define CONFIG_SYS_TIMER_COUNTER	NV_PA_TMRUS_BASE
@@ -116,6 +118,8 @@
 #define CONFIG_SYS_MEMTEST_START	(NV_PA_SDRC_CS0 + 0x600000)
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)
 
+#define CONFIG_USE_ARCH_MEMCPY
+
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
@@ -152,10 +156,6 @@
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_GPIO_SUPPORT
 
-#ifdef CONFIG_SPL_BUILD
-# define CONFIG_USE_PRIVATE_LIBGCC
-#endif
-
 #define CONFIG_SYS_GENERIC_BOARD
 
 /* Misc utility code */
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index a55bde23683..2fddef3cab7 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -178,8 +178,8 @@
 
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION    1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
 
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index e86c36443ba..aeabb1b7d5f 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -144,8 +144,8 @@
 
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION    1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
 
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 80976e7e3b8..5ed86d9365c 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -19,12 +19,23 @@
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
 
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_DM
+# define CONFIG_CMD_DM
+# define CONFIG_DM_GPIO
+# define CONFIG_DM_SERIAL
+# define CONFIG_OMAP_SERIAL
+# define CONFIG_SYS_MALLOC_F_LEN	(1 << 10)
+#endif
+
 #include <asm/arch/omap.h>
 
 /* NS16550 Configuration */
 #define CONFIG_SYS_NS16550
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#endif
 #define CONFIG_SYS_NS16550_CLK		48000000
 
 /* Network defines. */
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 85171dbb4c4..4b9b6296924 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -232,13 +232,13 @@
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
 
 /* FAT sd card locations. */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
 
 #ifdef CONFIG_SPL_OS_BOOT
 /* FAT */
-#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME		"uImage"
-#define CONFIG_SPL_FAT_LOAD_ARGS_NAME		"args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME		"args"
 
 /* RAW SD card / eMMC */
 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index 3b19d3d6baf..3c634ee680d 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -18,6 +18,15 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/omap3.h>
 
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_DM
+# define CONFIG_CMD_DM
+# define CONFIG_DM_GPIO
+# define CONFIG_DM_SERIAL
+# define CONFIG_OMAP_SERIAL
+# define CONFIG_SYS_MALLOC_F_LEN	(1 << 10)
+#endif
+
 /* The chip has SDRC controller */
 #define CONFIG_SDRC
 
@@ -28,16 +37,20 @@
 /* NS16550 Configuration */
 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
 #define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+#ifdef CONFIG_SPL_BUILD
+# define CONFIG_SYS_NS16550_SERIAL
+# define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+# define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+#endif
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
 					115200}
 
 /* Select serial console configuration */
 #define CONFIG_CONS_INDEX		3
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
 #define CONFIG_SERIAL3			3
+#endif
 
 /* Physical Memory Map */
 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index b0f199e3f4a..1c93aab1a7d 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -167,6 +167,9 @@
 #define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
 					 (128 << 20))
 
+/* SPL: Allow to use an EXT partition */
+#define CONFIG_SPL_EXT_SUPPORT
+
 #ifdef CONFIG_NAND
 #define CONFIG_SPL_NAND_AM33XX_BCH	/* ELM support */
 #endif
diff --git a/include/configs/top9000.h b/include/configs/top9000.h
deleted file mode 100644
index a96a9cb4167..00000000000
--- a/include/configs/top9000.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * Configuation settings for the TOP9000 CPU module with AT91SAM9XE.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/*
- * top9000 with at91sam9xe256 or at91sam9xe512
- *
- * Initial Bootloader is in embedded flash.
- * Vital Product Data, U-Boot Environment are in I2C-EEPROM.
- * U-Boot is in embedded flash, a backup U-Boot can be in NAND flash.
- * kernel and file system are either in NAND flash or on a micro SD card.
- * NAND flash is optional.
- * I2C EEPROM is never optional.
- * SPI FRAM is optional.
- * SPI ENC28J60 is optional.
- * 16 or 32 bit wide SDRAM.
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* SoC must be defined first, before hardware.h is included */
-#define CONFIG_AT91SAM9XE
-#include <asm/hardware.h>
-
-/*
- * Warning: changing CONFIG_SYS_TEXT_BASE requires
- * adapting the initial boot program.
- */
-#define CONFIG_SYS_TEXT_BASE		0x20000000	/* start of SDRAM */
-
-/* Command line configuration */
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_XIMG
-#define CONFIG_CMD_ASKENV
-#define CONFIG_SYS_CBSIZE		256
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_PBSIZE \
-	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_PROMPT		"TOP9000> "
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_CACHE
-
-/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
-
-/* Misc CPU related */
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_AT91RESET_EXTRST		/* assert external reset */
-
-/* general purpose I/O */
-#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
-#define CONFIG_AT91_GPIO
-#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
-
-/* serial console */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
-#define	CONFIG_USART_ID			ATMEL_ID_SYS
-#define CONFIG_BAUDRATE			115200
-
-/* SD/MMC card */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_SYS_MMC_CD_PIN		AT91_PIN_PC9
-#define CONFIG_CMD_MMC
-
-/* Ethernet */
-#define CONFIG_MACB
-#define CONFIG_SYS_PHY_ID	1
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT	20
-
-/* real time clock */
-#define CONFIG_RTC_AT91SAM9_RTT
-#define CONFIG_CMD_DATE
-
-#if defined(CONFIG_AT91SAM9XE)
-/*
- * NOR flash - use embedded flash of SAM9XE256/512
- * U-Boot will not fit into 128K !
- * 2010.09 will not fit into 256K with all options enabled !
- *
- * Layout:
- * 16kB	1st Bootloader
- * Rest U-Boot
- * the first sector (16kB) of EFLASH cannot be unprotected
- * with u-boot commands
- */
-# define CONFIG_AT91_EFLASH
-# define CONFIG_SYS_FLASH_BASE		ATMEL_BASE_FLASH
-# define CONFIG_SYS_MAX_FLASH_SECT	32
-# define CONFIG_SYS_MAX_FLASH_BANKS	1
-# define CONFIG_SYS_FLASH_PROTECTION
-# define CONFIG_EFLASH_PROTSECTORS	1	/* protect first sector */
-#endif
-
-/* SPI */
-#define CONFIG_ATMEL_SPI
-#define CONFIG_CMD_SPI
-
-/* RAMTRON FRAM */
-#define CONFIG_CMD_SF
-#define CONFIG_ATMEL_SPI0		/* SPI used for FRAM is SPI0 */
-#define FRAM_SPI_BUS		0
-#define FRAM_CS_NUM		0
-#define CONFIG_SPI_FRAM_RAMTRON
-#define CONFIG_SF_DEFAULT_SPEED	1000000	/* be conservative here... */
-#define CONFIG_SF_DEFAULT_MODE	SPI_MODE_0
-#define CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC	"FM25H20"
-
-/* Microchip ENC28J60 (second LAN) */
-#if defined(CONFIG_EVAL9000)
-# define CONFIG_ENC28J60
-# define CONFIG_ATMEL_SPI1		/* SPI used for ENC28J60 is SPI1 */
-# define ENC_SPI_BUS		1
-# define ENC_CS_NUM		0
-# define ENC_SPI_CLOCK	1000000
-#endif /* CONFIG_EVAL9000 */
-
-/*
- * SDRAM: 1 bank, min 32, max 128 MB
- * Initialized before u-boot gets started.
- */
-#define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE		0x08000000
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01e00000)
-#define CONFIG_SYS_LOAD_ADDR \
-	(CONFIG_SYS_SDRAM_BASE + 0x01000000)
-/*
- * Initial stack pointer: 16k - GENERATED_GBL_DATA_SIZE in internal SRAM,
- * leaving the correct space for initial global data structure above
- * that address while providing maximum stack area below.
- */
-#define CONFIG_SYS_INIT_SP_ADDR \
-	(ATMEL_BASE_SRAM + 0x4000 - GENERATED_GBL_DATA_SIZE)
-
-/*
- * NAND flash: 256 MB (optional)
- *
- * Layout:
- * 640kB: u-boot (includes space for spare sectors, handled by
- * initial loader)
- * 2MB: kernel
- * rest: file system
- */
-#define CONFIG_NAND_ATMEL
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
-#define CONFIG_CMD_NAND
-
-/* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	ATMEL_UHP_BASE
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"top9000"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
-#define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
-
-/* I2C support must always be enabled */
-#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
-
-#define I2C0_PORT			AT91_PIO_PORTA
-#define SDA0_PIN			23
-#define SCL0_PIN			24
-#define I2C1_PORT			AT91_PIO_PORTB
-#define SDA1_PIN			12
-#define SCL1_PIN			13
-#define I2C_SOFT_DECLARATIONS		void iic_init(void);\
-					int iic_read(void);\
-					void iic_sda(int);\
-					void iic_scl(int);
-#define I2C_ACTIVE
-#define I2C_TRISTATE
-#define I2C_INIT			iic_init()
-#define I2C_READ			iic_read()
-#define I2C_SDA(bit)			iic_sda(bit)
-#define I2C_SCL(bit)			iic_scl(bit)
-#define I2C_DELAY			udelay(3)
-/* EEPROM configuration */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
-#define CONFIG_SYS_EEPROM_SIZE		0x2000
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
-/* later: #define CONFIG_I2C_ENV_EEPROM_BUS	0 */
-/* ENV is always in I2C-EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_OFFSET		0x1000
-#define CONFIG_ENV_SIZE			0x0f00
-/* VPD settings */
-#define CONFIG_SYS_I2C_FACT_ADDR	0x57
-#define CONFIG_SYS_FACT_OFFSET		0x1F00
-#define CONFIG_SYS_FACT_SIZE		0x0100
-/* later: #define CONFIG_MISC_INIT_R */
-/* define the next only if you want to allow users to enter VPD data */
-#define CONFIG_SYS_FACT_ENTRY
-#ifndef __ASSEMBLY__
-extern void read_factory_r(void);
-#endif
-
-/*
- * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
- * data on the serial line may interrupt the boot sequence.
- */
-#define CONFIG_BOOTDELAY		1
-#define CONFIG_AUTOBOOT
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT \
-	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR	"d"
-#define CONFIG_AUTOBOOT_STOP_STR	" "
-
-/*
- * add filesystem commands if we have at least 1 storage
- * media with filesystem
- */
-#if defined(CONFIG_NAND_ATMEL) \
-	|| defined(CONFIG_USB_ATMEL) \
-	|| defined(CONFIG_MMC)
-# define CONFIG_DOS_PARTITION
-# define CONFIG_CMD_FAT
-# define CONFIG_CMD_EXT2
-/* later: #define CONFIG_CMD_JFFS2 */
-#endif
-
-/* add NET commands if we have at least 1 LAN */
-#if defined(CONFIG_MACB) || defined(CONFIG_ENC28J60)
-# define CONFIG_CMD_PING
-# define CONFIG_CMD_DHCP
-# define CONFIG_CMD_MII
-/* is this really needed ? */
-# define CONFIG_RESET_PHY_R
-/* BOOTP options */
-# define CONFIG_BOOTP_BOOTFILESIZE
-# define CONFIG_BOOTP_BOOTPATH
-# define CONFIG_BOOTP_GATEWAY
-# define CONFIG_BOOTP_HOSTNAME
-#endif
-
-/* linux in NAND flash */
-#define CONFIG_BOOTCOUNT_LIMIT	1
-#define CONFIG_BOOTCOMMAND \
-	"nand read 0x21000000 0xA0000 0x200000; bootm"
-#define CONFIG_BOOTARGS \
-	"console=ttyS0,115200 " \
-	"root=/dev/mtdblock2 " \
-	"mtdparts=atmel_nand:" \
-		"640k(uboot)ro," \
-		"2M(linux)," \
-		"16M(root)," \
-		"-(rest) " \
-	"rw "\
-	"rootfstype=jffs2"
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN \
-	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-
-#endif
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index 9ba015560b7..c94eee19a27 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -463,7 +463,6 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
-#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_STACKSIZE		(128u * SZ_1K)
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 6ddf3d5d5e4..6e7a7fbf28f 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -348,8 +348,8 @@
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION    1
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 
 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
diff --git a/include/configs/uniphier-common.h b/include/configs/uniphier-common.h
index 18fe277cada..b18ae6dfaeb 100644
--- a/include/configs/uniphier-common.h
+++ b/include/configs/uniphier-common.h
@@ -33,18 +33,17 @@ are defined. Select only one of them."
 # define CONFIG_SUPPORT_CARD_UART_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00200000)
 #endif
 
+#ifdef CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_COM1		CONFIG_SUPPORT_CARD_UART_BASE
 #define CONFIG_SYS_NS16550_CLK		12288000
 #define CONFIG_SYS_NS16550_REG_SIZE	-2
+#endif
 
 #define CONFIG_SMC911X_BASE		CONFIG_SUPPORT_CARD_ETHER_BASE
 #define CONFIG_SMC911X_32_BIT
 
-#define CONFIG_SYS_UNIPHIER_SERIAL_BASE0 0x54006800
-#define CONFIG_SYS_UNIPHIER_SERIAL_BASE1 0x54006900
-#define CONFIG_SYS_UNIPHIER_SERIAL_BASE2 0x54006a00
-#define CONFIG_SYS_UNIPHIER_SERIAL_BASE3 0x54006b00
+#define CONFIG_SYS_MALLOC_F_LEN  0x7000
 
 /*-----------------------------------------------------------------------
  * MMU and Cache Setting
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index 259205e8817..d3d3e694cda 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -242,8 +242,6 @@
  * Default environment and default scripts
  * to update uboot and load kernel
  */
-#define xstr(s)	str(s)
-#define str(s)	#s
 
 #define CONFIG_HOSTNAME woodburn
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
@@ -263,9 +261,9 @@
 	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
 	"loadaddr=80800000\0"						\
 	"kernel_addr_r=80800000\0"					\
-	"hostname=" xstr(CONFIG_HOSTNAME) "\0"				\
-	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0"			\
-	"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0"		\
+	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
+	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
+	"ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0"	\
 	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
@@ -279,9 +277,9 @@
 		"run ramargs addip addtty addmtd addmisc;"		\
 		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
 		"else echo Images not loades;fi\0"			\
-	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0"			\
+	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
 	"load=tftp ${loadaddr} ${u-boot}\0"				\
-	"uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0"		\
+	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0"		\
 	"update=protect off ${uboot_addr} +80000;"			\
 		"erase ${uboot_addr} +80000;"				\
 		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 71373e98f95..04187c0a312 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -83,8 +83,8 @@
 #define CONFIG_SPEAR_GPIO
 
 /* I2C config options */
-#define CONFIG_HARD_I2C
-#define CONFIG_DW_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DW
 #define CONFIG_SYS_I2C_BASE			0xD0200000
 #define CONFIG_SYS_I2C_SPEED			400000
 #define CONFIG_SYS_I2C_SLAVE			0x02
@@ -181,26 +181,24 @@
 #define CONFIG_UBI_PART				ubi0
 #define CONFIG_UBIFS_VOLUME			rootfs
 
-#define xstr(s)	str(s)
-#define str(s)	#s
-
 #define MTDIDS_DEFAULT		"nand0=nand"
 #define MTDPARTS_DEFAULT	"mtdparts=nand:64M(ubi0),64M(ubi1)"
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"u-boot_addr=1000000\0"						\
-	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.spr\0"			\
+	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0"		\
 	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
-	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"\
-		"erase " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"	\
-		"cp.b ${u-boot_addr} " xstr(CONFIG_SYS_MONITOR_BASE)	\
+	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};"					\
+		"erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
+		"cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
 		" ${filesize};"						\
-		"protect on " xstr(CONFIG_SYS_MONITOR_BASE)		\
+		"protect on " __stringify(CONFIG_SYS_MONITOR_BASE)	\
 		" +${filesize}\0"					\
 	"upd=run load update\0"						\
-	"ubifs=" xstr(CONFIG_HOSTNAME) "/ubifs.img\0"			\
-	"part=" xstr(CONFIG_UBI_PART) "\0"				\
-	"vol=" xstr(CONFIG_UBIFS_VOLUME) "\0"				\
+	"ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0"		\
+	"part=" __stringify(CONFIG_UBI_PART) "\0"			\
+	"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0"			\
 	"load_ubifs=tftp ${kernel_addr} ${ubifs}\0"			\
 	"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}"	\
 		" ${filesize}\0"					\
@@ -223,11 +221,12 @@
 		"saveenv;boot\0"					\
 	"ubifsargs=set bootargs ubi.mtd=ubi${boot_part} "		\
 		"root=ubi0:rootfs rootfstype=ubifs\0"			\
-	"kernel=" xstr(CONFIG_HOSTNAME) "/uImage\0"			\
+	"kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
 	"kernel_fs=/boot/uImage \0"					\
 	"kernel_addr=1000000\0"						\
-	"dtb=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0"	\
-	"dtb_fs=/boot/" xstr(CONFIG_HOSTNAME) ".dtb\0"			\
+	"dtb=" __stringify(CONFIG_HOSTNAME) "/"				\
+		__stringify(CONFIG_HOSTNAME) ".dtb\0"			\
+	"dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0"		\
 	"dtb_addr=1800000\0"						\
 	"load_kernel=tftp ${kernel_addr} ${kernel}\0"			\
 	"load_dtb=tftp ${dtb_addr} ${dtb}\0"				\
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index 41a7c99edcf..fe331bc0825 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -99,7 +99,6 @@
 #define	CONFIG_VIDEO_BMP_GZIP
 #define	CONFIG_VIDEO_BMP_RLE8
 #define	CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)
-#undef	SPI_INIT
 
 #define	SPI_DELAY	udelay(10)
 #define	SPI_SDA(val)	zipitz2_spi_sda(val)
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 0b4dd665b8c..2bc1562cecd 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -268,10 +268,10 @@
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION    1
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME     "u-boot-dtb.img"
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME     "u-boot-dtb.img"
 #endif
 
 /* Disable dcache for SPL just for sure */
@@ -283,8 +283,8 @@
 /* Address in RAM where the parameters must be copied by SPL. */
 #define CONFIG_SYS_SPL_ARGS_ADDR	0x10000000
 
-#define CONFIG_SPL_FAT_LOAD_ARGS_NAME		"system.dtb"
-#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME		"uImage"
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME		"system.dtb"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
 
 /* Not using MMC raw mode - just for compilation purpose */
 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0
diff --git a/include/cros_ec.h b/include/cros_ec.h
index 1e4d8db96b7..9e13146ecbb 100644
--- a/include/cros_ec.h
+++ b/include/cros_ec.h
@@ -14,6 +14,7 @@
 #include <fdtdec.h>
 #include <cros_ec_message.h>
 
+#ifndef CONFIG_DM_CROS_EC
 /* Which interface is the device on? */
 enum cros_ec_interface_t {
 	CROS_EC_IF_NONE,
@@ -22,9 +23,13 @@ enum cros_ec_interface_t {
 	CROS_EC_IF_LPC,	/* Intel Low Pin Count interface */
 	CROS_EC_IF_SANDBOX,
 };
+#endif
 
 /* Our configuration information */
 struct cros_ec_dev {
+#ifdef CONFIG_DM_CROS_EC
+	struct udevice *dev;		/* Transport device */
+#else
 	enum cros_ec_interface_t interface;
 	struct spi_slave *spi;		/* Our SPI slave, if using SPI */
 	int node;                       /* Our node */
@@ -33,6 +38,7 @@ struct cros_ec_dev {
 	unsigned int addr;		/* Device address (for I2C) */
 	unsigned int bus_num;		/* Bus number (for I2C) */
 	unsigned int max_frequency;	/* Maximum interface frequency */
+#endif
 	struct fdt_gpio_state ec_int;	/* GPIO used as EC interrupt line */
 	int protocol_version;           /* Protocol version to use */
 	int optimise_flash_write;	/* Don't write erased flash blocks */
@@ -233,6 +239,22 @@ int cros_ec_flash_update_rw(struct cros_ec_dev *dev,
  */
 struct cros_ec_dev *board_get_cros_ec_dev(void);
 
+#ifdef CONFIG_DM_CROS_EC
+
+struct dm_cros_ec_ops {
+	int (*check_version)(struct udevice *dev);
+	int (*command)(struct udevice *dev, uint8_t cmd, int cmd_version,
+		       const uint8_t *dout, int dout_len,
+		       uint8_t **dinp, int din_len);
+	int (*packet)(struct udevice *dev, int out_bytes, int in_bytes);
+};
+
+#define dm_cros_ec_get_ops(dev) \
+		((struct dm_cros_ec_ops *)(dev)->driver->ops)
+
+int cros_ec_register(struct udevice *dev);
+
+#else /* !CONFIG_DM_CROS_EC */
 
 /* Internal interfaces */
 int cros_ec_i2c_init(struct cros_ec_dev *dev, const void *blob);
@@ -336,6 +358,7 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes);
 int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes,
 			   int in_bytes);
+#endif
 
 /**
  * Dump a block of data for a command.
@@ -489,9 +512,11 @@ int cros_ec_get_error(void);
  * Returns information from the FDT about the Chrome EC flash
  *
  * @param blob		FDT blob to use
+ * @param node		Node offset to read from
  * @param config	Structure to use to return information
  */
-int cros_ec_decode_ec_flash(const void *blob, struct fdt_cros_ec *config);
+int cros_ec_decode_ec_flash(const void *blob, int node,
+			    struct fdt_cros_ec *config);
 
 /**
  * Check the current keyboard state, in case recovery mode is requested.
diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h
index 7005d03d08f..44cb7ef93bf 100644
--- a/include/dm/device-internal.h
+++ b/include/dm/device-internal.h
@@ -66,6 +66,19 @@ int device_bind_by_name(struct udevice *parent, bool pre_reloc_only,
 int device_probe(struct udevice *dev);
 
 /**
+ * device_probe() - Probe a child device, activating it
+ *
+ * Activate a device so that it is ready for use. All its parents are probed
+ * first. The child is provided with parent data if parent_priv is not NULL.
+ *
+ * @dev: Pointer to device to probe
+ * @parent_priv: Pointer to parent data. If non-NULL then this is provided to
+ * the child.
+ * @return 0 if OK, -ve on error
+ */
+int device_probe_child(struct udevice *dev, void *parent_priv);
+
+/**
  * device_remove() - Remove a device, de-activating it
  *
  * De-activate a device so that it is no longer ready for use. All its
diff --git a/include/dm/device.h b/include/dm/device.h
index c8a4072bcf7..9ce95a834e7 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -57,7 +57,8 @@ struct driver_info;
  * @sibling_node: Next device in list of all devices
  * @flags: Flags for this device DM_FLAG_...
  * @req_seq: Requested sequence number for this device (-1 = any)
- * @seq: Allocated sequence number for this device (-1 = none)
+ * @seq: Allocated sequence number for this device (-1 = none). This is set up
+ * when the device is probed and will be unique within the device's uclass.
  */
 struct udevice {
 	struct driver *driver;
@@ -96,6 +97,12 @@ struct udevice_id {
 	ulong data;
 };
 
+#ifdef CONFIG_OF_CONTROL
+#define of_match_ptr(_ptr)	(_ptr)
+#else
+#define of_match_ptr(_ptr)	NULL
+#endif /* CONFIG_OF_CONTROL */
+
 /**
  * struct driver - A driver for a feature or peripheral
  *
@@ -133,6 +140,10 @@ struct udevice_id {
  * @per_child_auto_alloc_size: Each device can hold private data owned by
  * its parent. If required this will be automatically allocated if this
  * value is non-zero.
+ * TODO(sjg@chromium.org): I'm considering dropping this, and just having
+ * device_probe_child() pass it in. So far the use case for allocating it
+ * is SPI, but I found that unsatisfactory. Since it is here I will leave it
+ * until things are clearer.
  * @ops: Driver-specific operations. This is typically a list of function
  * pointers defined by the driver, to implement driver functions required by
  * the uclass.
@@ -274,4 +285,22 @@ int device_find_child_by_of_offset(struct udevice *parent, int of_offset,
 int device_get_child_by_of_offset(struct udevice *parent, int seq,
 				  struct udevice **devp);
 
+/**
+ * device_find_first_child() - Find the first child of a device
+ *
+ * @parent: Parent device to search
+ * @devp: Returns first child device, or NULL if none
+ * @return 0
+ */
+int device_find_first_child(struct udevice *parent, struct udevice **devp);
+
+/**
+ * device_find_first_child() - Find the first child of a device
+ *
+ * @devp: Pointer to previous child device on entry. Returns pointer to next
+ *		child device, or NULL if none
+ * @return 0
+ */
+int device_find_next_child(struct udevice **devp);
+
 #endif
diff --git a/include/dm/lists.h b/include/dm/lists.h
index 23568952467..704e33e37fb 100644
--- a/include/dm/lists.h
+++ b/include/dm/lists.h
@@ -38,7 +38,7 @@ struct uclass_driver *lists_uclass_lookup(enum uclass_id id);
  * This searches the U_BOOT_DEVICE() structures and creates new devices for
  * each one. The devices will have @parent as their parent.
  *
- * @parent: parent driver (root)
+ * @parent: parent device (root)
  * @early_only: If true, bind only drivers with the DM_INIT_F flag. If false
  * bind all drivers.
  */
@@ -50,7 +50,7 @@ int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only);
  * This creates a new device bound to the given device tree node, with
  * @parent as its parent.
  *
- * @parent: parent driver (root)
+ * @parent: parent device (root)
  * @blob: device tree blob
  * @offset: offset of this device tree node
  * @devp: if non-NULL, returns a pointer to the bound device
diff --git a/include/dm/platdata.h b/include/dm/platdata.h
index 2bc8b147edf..fbc8a6b3add 100644
--- a/include/dm/platdata.h
+++ b/include/dm/platdata.h
@@ -11,10 +11,12 @@
 #ifndef _DM_PLATDATA_H
 #define _DM_PLATDATA_H
 
+#include <linker_lists.h>
+
 /**
  * struct driver_info - Information required to instantiate a device
  *
- * @name:	Device name
+ * @name:	Driver name
  * @platdata:	Driver-specific platform data
  */
 struct driver_info {
@@ -25,4 +27,8 @@ struct driver_info {
 #define U_BOOT_DEVICE(__name)						\
 	ll_entry_declare(struct driver_info, __name, driver_info)
 
+/* Declare a list of devices. The argument is a driver_info[] array */
+#define U_BOOT_DEVICES(__name)						\
+	ll_entry_declare_list(struct driver_info, __name, driver_info)
+
 #endif
diff --git a/include/dm/platform_data/serial-uniphier.h b/include/dm/platform_data/serial-uniphier.h
new file mode 100644
index 00000000000..52343e34ee7
--- /dev/null
+++ b/include/dm/platform_data/serial-uniphier.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PLAT_UNIPHIER_SERIAL_H
+#define __PLAT_UNIPHIER_SERIAL_H
+
+#define DRIVER_NAME	"uniphier-uart"
+
+struct uniphier_serial_platform_data {
+	unsigned long base;
+	unsigned int uartclk;
+};
+
+#endif /* __PLAT_UNIPHIER_SERIAL_H */
diff --git a/include/dm/platform_data/serial_mxc.h b/include/dm/platform_data/serial_mxc.h
new file mode 100644
index 00000000000..7d3ace2f9e4
--- /dev/null
+++ b/include/dm/platform_data/serial_mxc.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __serial_mxc_h
+#define __serial_mxc_h
+
+/* Information about a serial port */
+struct mxc_serial_platdata {
+	struct mxc_uart *reg;  /* address of registers in physical memory */
+};
+
+#endif
diff --git a/include/dm/platform_data/serial_pl01x.h b/include/dm/platform_data/serial_pl01x.h
new file mode 100644
index 00000000000..5e068f390bd
--- /dev/null
+++ b/include/dm/platform_data/serial_pl01x.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __serial_pl01x_h
+#define __serial_pl01x_h
+
+enum pl01x_type {
+	TYPE_PL010,
+	TYPE_PL011,
+};
+
+/*
+ *Information about a serial port
+ *
+ * @base: Register base address
+ * @type: Port type
+ * @clock: Input clock rate, used for calculating the baud rate divisor
+ */
+struct pl01x_serial_platdata {
+	unsigned long base;
+	enum pl01x_type type;
+	unsigned int clock;
+};
+
+#endif
diff --git a/include/dm/test.h b/include/dm/test.h
index 235d728bfbe..f08c05da814 100644
--- a/include/dm/test.h
+++ b/include/dm/test.h
@@ -8,6 +8,7 @@
 #define __DM_TEST_H
 
 #include <dm.h>
+#include <malloc.h>
 
 /**
  * struct dm_test_cdata - configuration data for test instance
@@ -120,6 +121,7 @@ struct dm_test_state {
 	int force_fail_alloc;
 	int skip_post_probe;
 	struct udevice *removed;
+	struct mallinfo start;
 };
 
 /* Test flags for each test */
@@ -178,6 +180,27 @@ int dm_check_operations(struct dm_test_state *dms, struct udevice *dev,
 int dm_check_devices(struct dm_test_state *dms, int num_devices);
 
 /**
+ * dm_leak_check_start() - Prepare to check for a memory leak
+ *
+ * Call this before allocating memory to record the amount of memory being
+ * used.
+ *
+ * @dms: Overall test state
+ */
+void dm_leak_check_start(struct dm_test_state *dms);
+
+/**
+ * dm_leak_check_end() - Check that no memory has leaked
+ *
+ * Call this after dm_leak_check_start() and after you have hopefuilly freed
+ * all the memory that was allocated. This function will print an error if
+ * it sees a different amount of total memory allocated than before.
+ *
+ * @dms: Overall test state
+ */int dm_leak_check_end(struct dm_test_state *dms);
+
+
+/**
  * dm_test_main() - Run all the tests
  *
  * This runs all available driver model tests
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 7f0e37b7b78..a8944c97d03 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -18,10 +18,16 @@ enum uclass_id {
 	UCLASS_TEST,
 	UCLASS_TEST_FDT,
 	UCLASS_TEST_BUS,
+	UCLASS_SPI_EMUL,	/* sandbox SPI device emulator */
+	UCLASS_SIMPLE_BUS,
 
 	/* U-Boot uclasses start here */
 	UCLASS_GPIO,		/* Bank of general-purpose I/O pins */
 	UCLASS_SERIAL,		/* Serial UART */
+	UCLASS_SPI,		/* SPI bus */
+	UCLASS_SPI_GENERIC,	/* Generic SPI flash target */
+	UCLASS_SPI_FLASH,	/* SPI flash */
+	UCLASS_CROS_EC,	/* Chrome OS EC */
 
 	UCLASS_COUNT,
 	UCLASS_INVALID = -1,
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index 8d09ecff7b4..f6ec6d7e9f6 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -11,6 +11,7 @@
 #define _DM_UCLASS_H
 
 #include <dm/uclass-id.h>
+#include <linker_lists.h>
 #include <linux/list.h>
 
 /**
diff --git a/include/dm/util.h b/include/dm/util.h
index 8be64a921dd..6ac3a38ef00 100644
--- a/include/dm/util.h
+++ b/include/dm/util.h
@@ -5,6 +5,7 @@
  */
 
 #ifndef __DM_UTIL_H
+#define __DM_UTIL_H
 
 void dm_warn(const char *fmt, ...);
 
diff --git a/include/dt-bindings/input/input.h b/include/dt-bindings/input/input.h
new file mode 100644
index 00000000000..042e7b3b629
--- /dev/null
+++ b/include/dt-bindings/input/input.h
@@ -0,0 +1,525 @@
+/*
+ * This header provides constants for most input bindings.
+ *
+ * Most input bindings include key code, matrix key code format.
+ * In most cases, key code and matrix key code format uses
+ * the standard values/macro defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_INPUT_INPUT_H
+#define _DT_BINDINGS_INPUT_INPUT_H
+
+#define KEY_RESERVED		0
+#define KEY_ESC			1
+#define KEY_1			2
+#define KEY_2			3
+#define KEY_3			4
+#define KEY_4			5
+#define KEY_5			6
+#define KEY_6			7
+#define KEY_7			8
+#define KEY_8			9
+#define KEY_9			10
+#define KEY_0			11
+#define KEY_MINUS		12
+#define KEY_EQUAL		13
+#define KEY_BACKSPACE		14
+#define KEY_TAB			15
+#define KEY_Q			16
+#define KEY_W			17
+#define KEY_E			18
+#define KEY_R			19
+#define KEY_T			20
+#define KEY_Y			21
+#define KEY_U			22
+#define KEY_I			23
+#define KEY_O			24
+#define KEY_P			25
+#define KEY_LEFTBRACE		26
+#define KEY_RIGHTBRACE		27
+#define KEY_ENTER		28
+#define KEY_LEFTCTRL		29
+#define KEY_A			30
+#define KEY_S			31
+#define KEY_D			32
+#define KEY_F			33
+#define KEY_G			34
+#define KEY_H			35
+#define KEY_J			36
+#define KEY_K			37
+#define KEY_L			38
+#define KEY_SEMICOLON		39
+#define KEY_APOSTROPHE		40
+#define KEY_GRAVE		41
+#define KEY_LEFTSHIFT		42
+#define KEY_BACKSLASH		43
+#define KEY_Z			44
+#define KEY_X			45
+#define KEY_C			46
+#define KEY_V			47
+#define KEY_B			48
+#define KEY_N			49
+#define KEY_M			50
+#define KEY_COMMA		51
+#define KEY_DOT			52
+#define KEY_SLASH		53
+#define KEY_RIGHTSHIFT		54
+#define KEY_KPASTERISK		55
+#define KEY_LEFTALT		56
+#define KEY_SPACE		57
+#define KEY_CAPSLOCK		58
+#define KEY_F1			59
+#define KEY_F2			60
+#define KEY_F3			61
+#define KEY_F4			62
+#define KEY_F5			63
+#define KEY_F6			64
+#define KEY_F7			65
+#define KEY_F8			66
+#define KEY_F9			67
+#define KEY_F10			68
+#define KEY_NUMLOCK		69
+#define KEY_SCROLLLOCK		70
+#define KEY_KP7			71
+#define KEY_KP8			72
+#define KEY_KP9			73
+#define KEY_KPMINUS		74
+#define KEY_KP4			75
+#define KEY_KP5			76
+#define KEY_KP6			77
+#define KEY_KPPLUS		78
+#define KEY_KP1			79
+#define KEY_KP2			80
+#define KEY_KP3			81
+#define KEY_KP0			82
+#define KEY_KPDOT		83
+
+#define KEY_ZENKAKUHANKAKU	85
+#define KEY_102ND		86
+#define KEY_F11			87
+#define KEY_F12			88
+#define KEY_RO			89
+#define KEY_KATAKANA		90
+#define KEY_HIRAGANA		91
+#define KEY_HENKAN		92
+#define KEY_KATAKANAHIRAGANA	93
+#define KEY_MUHENKAN		94
+#define KEY_KPJPCOMMA		95
+#define KEY_KPENTER		96
+#define KEY_RIGHTCTRL		97
+#define KEY_KPSLASH		98
+#define KEY_SYSRQ		99
+#define KEY_RIGHTALT		100
+#define KEY_LINEFEED		101
+#define KEY_HOME		102
+#define KEY_UP			103
+#define KEY_PAGEUP		104
+#define KEY_LEFT		105
+#define KEY_RIGHT		106
+#define KEY_END			107
+#define KEY_DOWN		108
+#define KEY_PAGEDOWN		109
+#define KEY_INSERT		110
+#define KEY_DELETE		111
+#define KEY_MACRO		112
+#define KEY_MUTE		113
+#define KEY_VOLUMEDOWN		114
+#define KEY_VOLUMEUP		115
+#define KEY_POWER		116	/* SC System Power Down */
+#define KEY_KPEQUAL		117
+#define KEY_KPPLUSMINUS		118
+#define KEY_PAUSE		119
+#define KEY_SCALE		120	/* AL Compiz Scale (Expose) */
+
+#define KEY_KPCOMMA		121
+#define KEY_HANGEUL		122
+#define KEY_HANGUEL		KEY_HANGEUL
+#define KEY_HANJA		123
+#define KEY_YEN			124
+#define KEY_LEFTMETA		125
+#define KEY_RIGHTMETA		126
+#define KEY_COMPOSE		127
+
+#define KEY_STOP		128	/* AC Stop */
+#define KEY_AGAIN		129
+#define KEY_PROPS		130	/* AC Properties */
+#define KEY_UNDO		131	/* AC Undo */
+#define KEY_FRONT		132
+#define KEY_COPY		133	/* AC Copy */
+#define KEY_OPEN		134	/* AC Open */
+#define KEY_PASTE		135	/* AC Paste */
+#define KEY_FIND		136	/* AC Search */
+#define KEY_CUT			137	/* AC Cut */
+#define KEY_HELP		138	/* AL Integrated Help Center */
+#define KEY_MENU		139	/* Menu (show menu) */
+#define KEY_CALC		140	/* AL Calculator */
+#define KEY_SETUP		141
+#define KEY_SLEEP		142	/* SC System Sleep */
+#define KEY_WAKEUP		143	/* System Wake Up */
+#define KEY_FILE		144	/* AL Local Machine Browser */
+#define KEY_SENDFILE		145
+#define KEY_DELETEFILE		146
+#define KEY_XFER		147
+#define KEY_PROG1		148
+#define KEY_PROG2		149
+#define KEY_WWW			150	/* AL Internet Browser */
+#define KEY_MSDOS		151
+#define KEY_COFFEE		152	/* AL Terminal Lock/Screensaver */
+#define KEY_SCREENLOCK		KEY_COFFEE
+#define KEY_DIRECTION		153
+#define KEY_CYCLEWINDOWS	154
+#define KEY_MAIL		155
+#define KEY_BOOKMARKS		156	/* AC Bookmarks */
+#define KEY_COMPUTER		157
+#define KEY_BACK		158	/* AC Back */
+#define KEY_FORWARD		159	/* AC Forward */
+#define KEY_CLOSECD		160
+#define KEY_EJECTCD		161
+#define KEY_EJECTCLOSECD	162
+#define KEY_NEXTSONG		163
+#define KEY_PLAYPAUSE		164
+#define KEY_PREVIOUSSONG	165
+#define KEY_STOPCD		166
+#define KEY_RECORD		167
+#define KEY_REWIND		168
+#define KEY_PHONE		169	/* Media Select Telephone */
+#define KEY_ISO			170
+#define KEY_CONFIG		171	/* AL Consumer Control Configuration */
+#define KEY_HOMEPAGE		172	/* AC Home */
+#define KEY_REFRESH		173	/* AC Refresh */
+#define KEY_EXIT		174	/* AC Exit */
+#define KEY_MOVE		175
+#define KEY_EDIT		176
+#define KEY_SCROLLUP		177
+#define KEY_SCROLLDOWN		178
+#define KEY_KPLEFTPAREN		179
+#define KEY_KPRIGHTPAREN	180
+#define KEY_NEW			181	/* AC New */
+#define KEY_REDO		182	/* AC Redo/Repeat */
+
+#define KEY_F13			183
+#define KEY_F14			184
+#define KEY_F15			185
+#define KEY_F16			186
+#define KEY_F17			187
+#define KEY_F18			188
+#define KEY_F19			189
+#define KEY_F20			190
+#define KEY_F21			191
+#define KEY_F22			192
+#define KEY_F23			193
+#define KEY_F24			194
+
+#define KEY_PLAYCD		200
+#define KEY_PAUSECD		201
+#define KEY_PROG3		202
+#define KEY_PROG4		203
+#define KEY_DASHBOARD		204	/* AL Dashboard */
+#define KEY_SUSPEND		205
+#define KEY_CLOSE		206	/* AC Close */
+#define KEY_PLAY		207
+#define KEY_FASTFORWARD		208
+#define KEY_BASSBOOST		209
+#define KEY_PRINT		210	/* AC Print */
+#define KEY_HP			211
+#define KEY_CAMERA		212
+#define KEY_SOUND		213
+#define KEY_QUESTION		214
+#define KEY_EMAIL		215
+#define KEY_CHAT		216
+#define KEY_SEARCH		217
+#define KEY_CONNECT		218
+#define KEY_FINANCE		219	/* AL Checkbook/Finance */
+#define KEY_SPORT		220
+#define KEY_SHOP		221
+#define KEY_ALTERASE		222
+#define KEY_CANCEL		223	/* AC Cancel */
+#define KEY_BRIGHTNESSDOWN	224
+#define KEY_BRIGHTNESSUP	225
+#define KEY_MEDIA		226
+
+#define KEY_SWITCHVIDEOMODE	227	/* Cycle between available video
+					   outputs (Monitor/LCD/TV-out/etc) */
+#define KEY_KBDILLUMTOGGLE	228
+#define KEY_KBDILLUMDOWN	229
+#define KEY_KBDILLUMUP		230
+
+#define KEY_SEND		231	/* AC Send */
+#define KEY_REPLY		232	/* AC Reply */
+#define KEY_FORWARDMAIL		233	/* AC Forward Msg */
+#define KEY_SAVE		234	/* AC Save */
+#define KEY_DOCUMENTS		235
+
+#define KEY_BATTERY		236
+
+#define KEY_BLUETOOTH		237
+#define KEY_WLAN		238
+#define KEY_UWB			239
+
+#define KEY_UNKNOWN		240
+
+#define KEY_VIDEO_NEXT		241	/* drive next video source */
+#define KEY_VIDEO_PREV		242	/* drive previous video source */
+#define KEY_BRIGHTNESS_CYCLE	243	/* brightness up, after max is min */
+#define KEY_BRIGHTNESS_ZERO	244	/* brightness off, use ambient */
+#define KEY_DISPLAY_OFF		245	/* display device to off state */
+
+#define KEY_WIMAX		246
+#define KEY_RFKILL		247	/* Key that controls all radios */
+
+#define KEY_MICMUTE		248	/* Mute / unmute the microphone */
+
+/* Code 255 is reserved for special needs of AT keyboard driver */
+
+#define BTN_MISC		0x100
+#define BTN_0			0x100
+#define BTN_1			0x101
+#define BTN_2			0x102
+#define BTN_3			0x103
+#define BTN_4			0x104
+#define BTN_5			0x105
+#define BTN_6			0x106
+#define BTN_7			0x107
+#define BTN_8			0x108
+#define BTN_9			0x109
+
+#define BTN_MOUSE		0x110
+#define BTN_LEFT		0x110
+#define BTN_RIGHT		0x111
+#define BTN_MIDDLE		0x112
+#define BTN_SIDE		0x113
+#define BTN_EXTRA		0x114
+#define BTN_FORWARD		0x115
+#define BTN_BACK		0x116
+#define BTN_TASK		0x117
+
+#define BTN_JOYSTICK		0x120
+#define BTN_TRIGGER		0x120
+#define BTN_THUMB		0x121
+#define BTN_THUMB2		0x122
+#define BTN_TOP			0x123
+#define BTN_TOP2		0x124
+#define BTN_PINKIE		0x125
+#define BTN_BASE		0x126
+#define BTN_BASE2		0x127
+#define BTN_BASE3		0x128
+#define BTN_BASE4		0x129
+#define BTN_BASE5		0x12a
+#define BTN_BASE6		0x12b
+#define BTN_DEAD		0x12f
+
+#define BTN_GAMEPAD		0x130
+#define BTN_SOUTH		0x130
+#define BTN_A			BTN_SOUTH
+#define BTN_EAST		0x131
+#define BTN_B			BTN_EAST
+#define BTN_C			0x132
+#define BTN_NORTH		0x133
+#define BTN_X			BTN_NORTH
+#define BTN_WEST		0x134
+#define BTN_Y			BTN_WEST
+#define BTN_Z			0x135
+#define BTN_TL			0x136
+#define BTN_TR			0x137
+#define BTN_TL2			0x138
+#define BTN_TR2			0x139
+#define BTN_SELECT		0x13a
+#define BTN_START		0x13b
+#define BTN_MODE		0x13c
+#define BTN_THUMBL		0x13d
+#define BTN_THUMBR		0x13e
+
+#define BTN_DIGI		0x140
+#define BTN_TOOL_PEN		0x140
+#define BTN_TOOL_RUBBER		0x141
+#define BTN_TOOL_BRUSH		0x142
+#define BTN_TOOL_PENCIL		0x143
+#define BTN_TOOL_AIRBRUSH	0x144
+#define BTN_TOOL_FINGER		0x145
+#define BTN_TOOL_MOUSE		0x146
+#define BTN_TOOL_LENS		0x147
+#define BTN_TOOL_QUINTTAP	0x148	/* Five fingers on trackpad */
+#define BTN_TOUCH		0x14a
+#define BTN_STYLUS		0x14b
+#define BTN_STYLUS2		0x14c
+#define BTN_TOOL_DOUBLETAP	0x14d
+#define BTN_TOOL_TRIPLETAP	0x14e
+#define BTN_TOOL_QUADTAP	0x14f	/* Four fingers on trackpad */
+
+#define BTN_WHEEL		0x150
+#define BTN_GEAR_DOWN		0x150
+#define BTN_GEAR_UP		0x151
+
+#define KEY_OK			0x160
+#define KEY_SELECT		0x161
+#define KEY_GOTO		0x162
+#define KEY_CLEAR		0x163
+#define KEY_POWER2		0x164
+#define KEY_OPTION		0x165
+#define KEY_INFO		0x166	/* AL OEM Features/Tips/Tutorial */
+#define KEY_TIME		0x167
+#define KEY_VENDOR		0x168
+#define KEY_ARCHIVE		0x169
+#define KEY_PROGRAM		0x16a	/* Media Select Program Guide */
+#define KEY_CHANNEL		0x16b
+#define KEY_FAVORITES		0x16c
+#define KEY_EPG			0x16d
+#define KEY_PVR			0x16e	/* Media Select Home */
+#define KEY_MHP			0x16f
+#define KEY_LANGUAGE		0x170
+#define KEY_TITLE		0x171
+#define KEY_SUBTITLE		0x172
+#define KEY_ANGLE		0x173
+#define KEY_ZOOM		0x174
+#define KEY_MODE		0x175
+#define KEY_KEYBOARD		0x176
+#define KEY_SCREEN		0x177
+#define KEY_PC			0x178	/* Media Select Computer */
+#define KEY_TV			0x179	/* Media Select TV */
+#define KEY_TV2			0x17a	/* Media Select Cable */
+#define KEY_VCR			0x17b	/* Media Select VCR */
+#define KEY_VCR2		0x17c	/* VCR Plus */
+#define KEY_SAT			0x17d	/* Media Select Satellite */
+#define KEY_SAT2		0x17e
+#define KEY_CD			0x17f	/* Media Select CD */
+#define KEY_TAPE		0x180	/* Media Select Tape */
+#define KEY_RADIO		0x181
+#define KEY_TUNER		0x182	/* Media Select Tuner */
+#define KEY_PLAYER		0x183
+#define KEY_TEXT		0x184
+#define KEY_DVD			0x185	/* Media Select DVD */
+#define KEY_AUX			0x186
+#define KEY_MP3			0x187
+#define KEY_AUDIO		0x188	/* AL Audio Browser */
+#define KEY_VIDEO		0x189	/* AL Movie Browser */
+#define KEY_DIRECTORY		0x18a
+#define KEY_LIST		0x18b
+#define KEY_MEMO		0x18c	/* Media Select Messages */
+#define KEY_CALENDAR		0x18d
+#define KEY_RED			0x18e
+#define KEY_GREEN		0x18f
+#define KEY_YELLOW		0x190
+#define KEY_BLUE		0x191
+#define KEY_CHANNELUP		0x192	/* Channel Increment */
+#define KEY_CHANNELDOWN		0x193	/* Channel Decrement */
+#define KEY_FIRST		0x194
+#define KEY_LAST		0x195	/* Recall Last */
+#define KEY_AB			0x196
+#define KEY_NEXT		0x197
+#define KEY_RESTART		0x198
+#define KEY_SLOW		0x199
+#define KEY_SHUFFLE		0x19a
+#define KEY_BREAK		0x19b
+#define KEY_PREVIOUS		0x19c
+#define KEY_DIGITS		0x19d
+#define KEY_TEEN		0x19e
+#define KEY_TWEN		0x19f
+#define KEY_VIDEOPHONE		0x1a0	/* Media Select Video Phone */
+#define KEY_GAMES		0x1a1	/* Media Select Games */
+#define KEY_ZOOMIN		0x1a2	/* AC Zoom In */
+#define KEY_ZOOMOUT		0x1a3	/* AC Zoom Out */
+#define KEY_ZOOMRESET		0x1a4	/* AC Zoom */
+#define KEY_WORDPROCESSOR	0x1a5	/* AL Word Processor */
+#define KEY_EDITOR		0x1a6	/* AL Text Editor */
+#define KEY_SPREADSHEET		0x1a7	/* AL Spreadsheet */
+#define KEY_GRAPHICSEDITOR	0x1a8	/* AL Graphics Editor */
+#define KEY_PRESENTATION	0x1a9	/* AL Presentation App */
+#define KEY_DATABASE		0x1aa	/* AL Database App */
+#define KEY_NEWS		0x1ab	/* AL Newsreader */
+#define KEY_VOICEMAIL		0x1ac	/* AL Voicemail */
+#define KEY_ADDRESSBOOK		0x1ad	/* AL Contacts/Address Book */
+#define KEY_MESSENGER		0x1ae	/* AL Instant Messaging */
+#define KEY_DISPLAYTOGGLE	0x1af	/* Turn display (LCD) on and off */
+#define KEY_SPELLCHECK		0x1b0   /* AL Spell Check */
+#define KEY_LOGOFF		0x1b1   /* AL Logoff */
+
+#define KEY_DOLLAR		0x1b2
+#define KEY_EURO		0x1b3
+
+#define KEY_FRAMEBACK		0x1b4	/* Consumer - transport controls */
+#define KEY_FRAMEFORWARD	0x1b5
+#define KEY_CONTEXT_MENU	0x1b6	/* GenDesc - system context menu */
+#define KEY_MEDIA_REPEAT	0x1b7	/* Consumer - transport control */
+#define KEY_10CHANNELSUP	0x1b8	/* 10 channels up (10+) */
+#define KEY_10CHANNELSDOWN	0x1b9	/* 10 channels down (10-) */
+#define KEY_IMAGES		0x1ba	/* AL Image Browser */
+
+#define KEY_DEL_EOL		0x1c0
+#define KEY_DEL_EOS		0x1c1
+#define KEY_INS_LINE		0x1c2
+#define KEY_DEL_LINE		0x1c3
+
+#define KEY_FN			0x1d0
+#define KEY_FN_ESC		0x1d1
+#define KEY_FN_F1		0x1d2
+#define KEY_FN_F2		0x1d3
+#define KEY_FN_F3		0x1d4
+#define KEY_FN_F4		0x1d5
+#define KEY_FN_F5		0x1d6
+#define KEY_FN_F6		0x1d7
+#define KEY_FN_F7		0x1d8
+#define KEY_FN_F8		0x1d9
+#define KEY_FN_F9		0x1da
+#define KEY_FN_F10		0x1db
+#define KEY_FN_F11		0x1dc
+#define KEY_FN_F12		0x1dd
+#define KEY_FN_1		0x1de
+#define KEY_FN_2		0x1df
+#define KEY_FN_D		0x1e0
+#define KEY_FN_E		0x1e1
+#define KEY_FN_F		0x1e2
+#define KEY_FN_S		0x1e3
+#define KEY_FN_B		0x1e4
+
+#define KEY_BRL_DOT1		0x1f1
+#define KEY_BRL_DOT2		0x1f2
+#define KEY_BRL_DOT3		0x1f3
+#define KEY_BRL_DOT4		0x1f4
+#define KEY_BRL_DOT5		0x1f5
+#define KEY_BRL_DOT6		0x1f6
+#define KEY_BRL_DOT7		0x1f7
+#define KEY_BRL_DOT8		0x1f8
+#define KEY_BRL_DOT9		0x1f9
+#define KEY_BRL_DOT10		0x1fa
+
+#define KEY_NUMERIC_0		0x200	/* used by phones, remote controls, */
+#define KEY_NUMERIC_1		0x201	/* and other keypads */
+#define KEY_NUMERIC_2		0x202
+#define KEY_NUMERIC_3		0x203
+#define KEY_NUMERIC_4		0x204
+#define KEY_NUMERIC_5		0x205
+#define KEY_NUMERIC_6		0x206
+#define KEY_NUMERIC_7		0x207
+#define KEY_NUMERIC_8		0x208
+#define KEY_NUMERIC_9		0x209
+#define KEY_NUMERIC_STAR	0x20a
+#define KEY_NUMERIC_POUND	0x20b
+
+#define KEY_CAMERA_FOCUS	0x210
+#define KEY_WPS_BUTTON		0x211	/* WiFi Protected Setup key */
+
+#define KEY_TOUCHPAD_TOGGLE	0x212	/* Request switch touchpad on or off */
+#define KEY_TOUCHPAD_ON		0x213
+#define KEY_TOUCHPAD_OFF	0x214
+
+#define KEY_CAMERA_ZOOMIN	0x215
+#define KEY_CAMERA_ZOOMOUT	0x216
+#define KEY_CAMERA_UP		0x217
+#define KEY_CAMERA_DOWN		0x218
+#define KEY_CAMERA_LEFT		0x219
+#define KEY_CAMERA_RIGHT	0x21a
+
+#define KEY_ATTENDANT_ON	0x21b
+#define KEY_ATTENDANT_OFF	0x21c
+#define KEY_ATTENDANT_TOGGLE	0x21d	/* Attendant call on or off */
+#define KEY_LIGHTS_TOGGLE	0x21e	/* Reading light on or off */
+
+#define BTN_DPAD_UP		0x220
+#define BTN_DPAD_DOWN		0x221
+#define BTN_DPAD_LEFT		0x222
+#define BTN_DPAD_RIGHT		0x223
+
+#define MATRIX_KEY(row, col, code)	\
+	((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))
+
+#endif /* _DT_BINDINGS_INPUT_INPUT_H */
diff --git a/arch/arm/dts/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h
index 2fbc804e1a4..2fbc804e1a4 100644
--- a/arch/arm/dts/dt-bindings/pinctrl/am33xx.h
+++ b/include/dt-bindings/pinctrl/am33xx.h
diff --git a/arch/arm/dts/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h
index edbd250809c..edbd250809c 100644
--- a/arch/arm/dts/dt-bindings/pinctrl/omap.h
+++ b/include/dt-bindings/pinctrl/omap.h
diff --git a/include/elf.h b/include/elf.h
index b8ecc41063b..63d93416a3e 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -570,4 +570,6 @@ unsigned long elf_hash(const unsigned char *name);
    that may still be in object files.  */
 #define R_PPC_TOC16             255
 
+int valid_elf_image(unsigned long addr);
+
 #endif /* _ELF_H */
diff --git a/include/fdt_support.h b/include/fdt_support.h
index c3d1fbcf356..55cef94358b 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -144,6 +144,8 @@ static inline u64 of_read_number(const fdt32_t *cell, int size)
 
 void of_bus_default_count_cells(void *blob, int parentoffset,
 					int *addrc, int *sizec);
+int ft_verify_fdt(void *fdt);
+int arch_fixup_memory_node(void *blob);
 
 #endif /* ifdef CONFIG_OF_LIBFDT */
 
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 2590d3071fd..4ae77be9ba7 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -40,6 +40,27 @@ struct fdt_memory {
 	fdt_addr_t end;
 };
 
+/*
+ * Information about a resource. start is the first address of the resource
+ * and end is the last address (inclusive). The length of the resource will
+ * be equal to: end - start + 1.
+ */
+struct fdt_resource {
+	fdt_addr_t start;
+	fdt_addr_t end;
+};
+
+/**
+ * Compute the size of a resource.
+ *
+ * @param res	the resource to operate on
+ * @return the size of the resource
+ */
+static inline fdt_size_t fdt_resource_size(const struct fdt_resource *res)
+{
+	return res->end - res->start + 1;
+}
+
 /**
  * Compat types that we know about and for which we might have drivers.
  * Each is named COMPAT_<dir>_<filename> where <dir> is the directory
@@ -96,6 +117,7 @@ enum fdt_compat_id {
 	COMPAT_NXP_PTN3460,		/* NXP PTN3460 DP/LVDS bridge */
 	COMPAT_SAMSUNG_EXYNOS_SYSMMU,	/* Exynos sysmmu */
 	COMPAT_PARADE_PS8625,		/* Parade PS8622 EDP->LVDS bridge */
+	COMPAT_INTEL_LPC,		/* Intel Low Pin Count I/F */
 
 	COMPAT_COUNT,
 };
@@ -597,4 +619,46 @@ struct fmap_entry {
  */
 int fdtdec_read_fmap_entry(const void *blob, int node, const char *name,
 			   struct fmap_entry *entry);
+
+/**
+ * Obtain an indexed resource from a device property.
+ *
+ * @param fdt		FDT blob
+ * @param node		node to examine
+ * @param property	name of the property to parse
+ * @param index		index of the resource to retrieve
+ * @param res		returns the resource
+ * @return 0 if ok, negative on error
+ */
+int fdt_get_resource(const void *fdt, int node, const char *property,
+		     unsigned int index, struct fdt_resource *res);
+
+/**
+ * Obtain a named resource from a device property.
+ *
+ * Look up the index of the name in a list of strings and return the resource
+ * at that index.
+ *
+ * @param fdt		FDT blob
+ * @param node		node to examine
+ * @param property	name of the property to parse
+ * @param prop_names	name of the property containing the list of names
+ * @param name		the name of the entry to look up
+ * @param res		returns the resource
+ */
+int fdt_get_named_resource(const void *fdt, int node, const char *property,
+			   const char *prop_names, const char *name,
+			   struct fdt_resource *res);
+
+/**
+ * Look at the reg property of a device node that represents a PCI device
+ * and parse the bus, device and function number from it.
+ *
+ * @param fdt		FDT blob
+ * @param node		node to examine
+ * @param bdf		returns bus, device, function triplet
+ * @return 0 if ok, negative on error
+ */
+int fdtdec_pci_get_bdf(const void *fdt, int node, int *bdf);
+
 #endif
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
new file mode 100644
index 00000000000..aa850a3bf13
--- /dev/null
+++ b/include/fsl_sec.h
@@ -0,0 +1,181 @@
+/*
+ * Common internal memory map for some Freescale SoCs
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ */
+
+#ifndef __FSL_SEC_H
+#define __FSL_SEC_H
+
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_SYS_FSL_SEC_LE
+#define sec_in32(a)       in_le32(a)
+#define sec_out32(a, v)   out_le32(a, v)
+#define sec_in16(a)       in_le16(a)
+#define sec_clrbits32     clrbits_le32
+#define sec_setbits32     setbits_le32
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+#define sec_in32(a)       in_be32(a)
+#define sec_out32(a, v)   out_be32(a, v)
+#define sec_in16(a)       in_be16(a)
+#define sec_clrbits32     clrbits_be32
+#define sec_setbits32     setbits_be32
+#else
+#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
+#endif
+
+/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+/* RNG4 TRNG test registers */
+struct rng4tst {
+#define RTMCTL_PRGM 0x00010000	/* 1 -> program mode, 0 -> run mode */
+	u32 rtmctl;		/* misc. control register */
+	u32 rtscmisc;		/* statistical check misc. register */
+	u32 rtpkrrng;		/* poker range register */
+#define RTSDCTL_ENT_DLY_MIN	1200
+#define RTSDCTL_ENT_DLY_MAX	12800
+	union {
+		u32 rtpkrmax;	/* PRGM=1: poker max. limit register */
+		u32 rtpkrsq;	/* PRGM=0: poker square calc. result register */
+	};
+#define RTSDCTL_ENT_DLY_SHIFT 16
+#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
+	u32 rtsdctl;		/* seed control register */
+	union {
+		u32 rtsblim;	/* PRGM=1: sparse bit limit register */
+		u32 rttotsam;	/* PRGM=0: total samples register */
+	};
+	u32 rtfreqmin;		/* frequency count min. limit register */
+	union {
+		u32 rtfreqmax;	/* PRGM=1: freq. count max. limit register */
+		u32 rtfreqcnt;	/* PRGM=0: freq. count register */
+	};
+	u32 rsvd1[40];
+#define RNG_STATE0_HANDLE_INSTANTIATED	0x00000001
+	u32 rdsta;		/*RNG DRNG Status Register*/
+	u32 rsvd2[15];
+};
+
+typedef struct ccsr_sec {
+	u32	res0;
+	u32	mcfgr;		/* Master CFG Register */
+	u8	res1[0x4];
+	u32	scfgr;
+	struct {
+		u32	ms;	/* Job Ring LIODN Register, MS */
+		u32	ls;	/* Job Ring LIODN Register, LS */
+	} jrliodnr[4];
+	u8	res2[0x2c];
+	u32	jrstartr;	/* Job Ring Start Register */
+	struct {
+		u32	ms;	/* RTIC LIODN Register, MS */
+		u32	ls;	/* RTIC LIODN Register, LS */
+	} rticliodnr[4];
+	u8	res3[0x1c];
+	u32	decorr;		/* DECO Request Register */
+	struct {
+		u32	ms;	/* DECO LIODN Register, MS */
+		u32	ls;	/* DECO LIODN Register, LS */
+	} decoliodnr[8];
+	u8	res4[0x40];
+	u32	dar;		/* DECO Avail Register */
+	u32	drr;		/* DECO Reset Register */
+	u8	res5[0x4d8];
+	struct rng4tst rng;	/* RNG Registers */
+	u8	res11[0x8a0];
+	u32	crnr_ms;	/* CHA Revision Number Register, MS */
+	u32	crnr_ls;	/* CHA Revision Number Register, LS */
+	u32	ctpr_ms;	/* Compile Time Parameters Register, MS */
+	u32	ctpr_ls;	/* Compile Time Parameters Register, LS */
+	u8	res6[0x10];
+	u32	far_ms;		/* Fault Address Register, MS */
+	u32	far_ls;		/* Fault Address Register, LS */
+	u32	falr;		/* Fault Address LIODN Register */
+	u32	fadr;		/* Fault Address Detail Register */
+	u8	res7[0x4];
+	u32	csta;		/* CAAM Status Register */
+	u8	res8[0x8];
+	u32	rvid;		/* Run Time Integrity Checking Version ID Reg.*/
+	u32	ccbvid;		/* CHA Cluster Block Version ID Register */
+	u32	chavid_ms;	/* CHA Version ID Register, MS */
+	u32	chavid_ls;	/* CHA Version ID Register, LS */
+	u32	chanum_ms;	/* CHA Number Register, MS */
+	u32	chanum_ls;	/* CHA Number Register, LS */
+	u32	secvid_ms;	/* SEC Version ID Register, MS */
+	u32	secvid_ls;	/* SEC Version ID Register, LS */
+	u8	res9[0x6020];
+	u32	qilcr_ms;	/* Queue Interface LIODN CFG Register, MS */
+	u32	qilcr_ls;	/* Queue Interface LIODN CFG Register, LS */
+	u8	res10[0x8fd8];
+} ccsr_sec_t;
+
+#define SEC_CTPR_MS_AXI_LIODN		0x08000000
+#define SEC_CTPR_MS_QI			0x02000000
+#define SEC_CTPR_MS_VIRT_EN_INCL	0x00000001
+#define SEC_CTPR_MS_VIRT_EN_POR		0x00000002
+#define SEC_RVID_MA			0x0f000000
+#define SEC_CHANUM_MS_JRNUM_MASK	0xf0000000
+#define SEC_CHANUM_MS_JRNUM_SHIFT	28
+#define SEC_CHANUM_MS_DECONUM_MASK	0x0f000000
+#define SEC_CHANUM_MS_DECONUM_SHIFT	24
+#define SEC_SECVID_MS_IPID_MASK	0xffff0000
+#define SEC_SECVID_MS_IPID_SHIFT	16
+#define SEC_SECVID_MS_MAJ_REV_MASK	0x0000ff00
+#define SEC_SECVID_MS_MAJ_REV_SHIFT	8
+#define SEC_CCBVID_ERA_MASK		0xff000000
+#define SEC_CCBVID_ERA_SHIFT		24
+#define SEC_SCFGR_RDBENABLE		0x00000400
+#define SEC_SCFGR_VIRT_EN		0x00008000
+#define SEC_CHAVID_LS_RNG_SHIFT		16
+#define SEC_CHAVID_RNG_LS_MASK		0x000f0000
+
+#define CONFIG_JRSTARTR_JR0		0x00000001
+
+struct jr_regs {
+#ifdef CONFIG_SYS_FSL_SEC_LE
+	u32 irba_l;
+	u32 irba_h;
+#else
+	u32 irba_h;
+	u32 irba_l;
+#endif
+	u32 rsvd1;
+	u32 irs;
+	u32 rsvd2;
+	u32 irsa;
+	u32 rsvd3;
+	u32 irja;
+#ifdef CONFIG_SYS_FSL_SEC_LE
+	u32 orba_l;
+	u32 orba_h;
+#else
+	u32 orba_h;
+	u32 orba_l;
+#endif
+	u32 rsvd4;
+	u32 ors;
+	u32 rsvd5;
+	u32 orjr;
+	u32 rsvd6;
+	u32 orsf;
+	u32 rsvd7;
+	u32 jrsta;
+	u32 rsvd8;
+	u32 jrint;
+	u32 jrcfg0;
+	u32 jrcfg1;
+	u32 rsvd9;
+	u32 irri;
+	u32 rsvd10;
+	u32 orwi;
+	u32 rsvd11;
+	u32 jrcr;
+};
+
+int sec_init(void);
+#endif
+
+#endif /* __FSL_SEC_H */
diff --git a/include/ide.h b/include/ide.h
index c2a48e0b378..d5e05e97cb2 100644
--- a/include/ide.h
+++ b/include/ide.h
@@ -23,6 +23,7 @@ extern ulong ide_bus_offset[];
 #define LED_IDE2	0x02
 #define	DEVICE_LED(d)	((d & 2) | ((d & 2) == 0)) /* depends on bit positions! */
 
+void ide_led(uchar led, uchar status);
 #endif /* CONFIG_IDE_LED */
 
 #ifdef CONFIG_SYS_64BIT_LBA
diff --git a/include/image.h b/include/image.h
index 4347532520b..07e9aed16d9 100644
--- a/include/image.h
+++ b/include/image.h
@@ -173,6 +173,7 @@ struct lmb;
 #define IH_ARCH_OPENRISC        21	/* OpenRISC 1000  */
 #define IH_ARCH_ARM64		22	/* ARM64	*/
 #define IH_ARCH_ARC		23	/* Synopsys DesignWare ARC */
+#define IH_ARCH_X86_64		24	/* AMD x86_64, Intel and Via */
 
 /*
  * Image Types
@@ -233,6 +234,7 @@ struct lmb;
 #define IH_TYPE_GPIMAGE		17	/* TI Keystone GPHeader Image	*/
 #define IH_TYPE_ATMELIMAGE	18	/* ATMEL ROM bootable Image	*/
 #define IH_TYPE_SOCFPGAIMAGE	19	/* Altera SOCFPGA Preloader	*/
+#define IH_TYPE_X86_SETUP	20	/* x86 setup.bin Image		*/
 
 /*
  * Compression Types
@@ -273,6 +275,7 @@ typedef struct image_info {
 	ulong		image_start, image_len; /* start of image within blob, len of image */
 	ulong		load;			/* load addr for the image */
 	uint8_t		comp, type, os;		/* compression, type of image, os type */
+	uint8_t		arch;			/* CPU architecture */
 } image_info_t;
 
 /*
@@ -303,6 +306,10 @@ typedef struct bootm_headers {
 	void		*fit_hdr_fdt;	/* FDT blob FIT image header */
 	const char	*fit_uname_fdt;	/* FDT blob subimage node unit name */
 	int		fit_noffset_fdt;/* FDT blob subimage node offset */
+
+	void		*fit_hdr_setup;	/* x86 setup FIT image header */
+	const char	*fit_uname_setup; /* x86 setup subimage node name */
+	int		fit_noffset_setup;/* x86 setup subimage node offset */
 #endif
 
 #ifndef USE_HOSTCC
@@ -417,6 +424,9 @@ enum fit_load_op {
 	FIT_LOAD_REQUIRED,	/* Must be provided */
 };
 
+int boot_get_setup(bootm_headers_t *images, uint8_t arch, ulong *setup_start,
+		   ulong *setup_len);
+
 #ifndef USE_HOSTCC
 /* Image format types, returned by _get_format() routine */
 #define IMAGE_FORMAT_INVALID	0x00
@@ -438,6 +448,9 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
 		uint8_t arch, ulong *rd_start, ulong *rd_end);
 #endif
 
+int boot_get_setup_fit(bootm_headers_t *images, uint8_t arch,
+		       ulong *setup_start, ulong *setup_len);
+
 /**
  * fit_image_load() - load an image from a FIT
  *
@@ -721,6 +734,7 @@ int bootz_setup(ulong image, ulong *start, ulong *end);
 #define FIT_RAMDISK_PROP	"ramdisk"
 #define FIT_FDT_PROP		"fdt"
 #define FIT_DEFAULT_PROP	"default"
+#define FIT_SETUP_PROP		"setup"
 
 #define FIT_MAX_HASH_LEN	HASH_MAX_DIGEST_SIZE
 
diff --git a/include/inttypes.h b/include/inttypes.h
new file mode 100644
index 00000000000..e2e569d0acf
--- /dev/null
+++ b/include/inttypes.h
@@ -0,0 +1,287 @@
+/*
+ * Copyright (C) 1997-2001, 2004, 2007 Free Software Foundation, Inc.
+ *
+ * This file is taken from the GNU C Library v2.15, with the unimplemented
+ * functions removed and a few style fixes.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ *	ISO C99: 7.8 Format conversion of integer types	<inttypes.h>
+ */
+
+#ifndef _INTTYPES_H
+#define _INTTYPES_H	1
+
+#include <linux/compiler.h>
+
+/* Get a definition for wchar_t.  But we must not define wchar_t itself.  */
+#ifndef ____gwchar_t_defined
+# ifdef __cplusplus
+#  define __gwchar_t wchar_t
+# elif defined __WCHAR_TYPE__
+typedef __WCHAR_TYPE__ __gwchar_t;
+# else
+#  define __need_wchar_t
+#  include <stddef.h>
+typedef wchar_t __gwchar_t;
+# endif
+# define ____gwchar_t_defined	1
+#endif
+
+
+/* The ISO C99 standard specifies that these macros must only be
+   defined if explicitly requested.  */
+#if !defined __cplusplus || defined __STDC_FORMAT_MACROS
+
+#ifdef CONFIG_USE_STDINT
+# if __WORDSIZE == 64
+#  define __PRI64_PREFIX	"l"
+#  define __PRIPTR_PREFIX	"l"
+# else
+#  define __PRI64_PREFIX	"ll"
+#  define __PRIPTR_PREFIX
+# endif
+#else
+/* linux/types.h always uses long long for 64-bit and long for uintptr_t */
+# define __PRI64_PREFIX	"ll"
+# define __PRIPTR_PREFIX	"l"
+#endif
+
+/* Macros for printing format specifiers.  */
+
+/* Decimal notation.  */
+# define PRId8		"d"
+# define PRId16		"d"
+# define PRId32		"d"
+# define PRId64		__PRI64_PREFIX "d"
+
+# define PRIdLEAST8	"d"
+# define PRIdLEAST16	"d"
+# define PRIdLEAST32	"d"
+# define PRIdLEAST64	__PRI64_PREFIX "d"
+
+# define PRIdFAST8	"d"
+# define PRIdFAST16	__PRIPTR_PREFIX "d"
+# define PRIdFAST32	__PRIPTR_PREFIX "d"
+# define PRIdFAST64	__PRI64_PREFIX "d"
+
+
+# define PRIi8		"i"
+# define PRIi16		"i"
+# define PRIi32		"i"
+# define PRIi64		__PRI64_PREFIX "i"
+
+# define PRIiLEAST8	"i"
+# define PRIiLEAST16	"i"
+# define PRIiLEAST32	"i"
+# define PRIiLEAST64	__PRI64_PREFIX "i"
+
+# define PRIiFAST8	"i"
+# define PRIiFAST16	__PRIPTR_PREFIX "i"
+# define PRIiFAST32	__PRIPTR_PREFIX "i"
+# define PRIiFAST64	__PRI64_PREFIX "i"
+
+/* Octal notation.  */
+# define PRIo8		"o"
+# define PRIo16		"o"
+# define PRIo32		"o"
+# define PRIo64		__PRI64_PREFIX "o"
+
+# define PRIoLEAST8	"o"
+# define PRIoLEAST16	"o"
+# define PRIoLEAST32	"o"
+# define PRIoLEAST64	__PRI64_PREFIX "o"
+
+# define PRIoFAST8	"o"
+# define PRIoFAST16	__PRIPTR_PREFIX "o"
+# define PRIoFAST32	__PRIPTR_PREFIX "o"
+# define PRIoFAST64	__PRI64_PREFIX "o"
+
+/* Unsigned integers.  */
+# define PRIu8		"u"
+# define PRIu16		"u"
+# define PRIu32		"u"
+# define PRIu64		__PRI64_PREFIX "u"
+
+# define PRIuLEAST8	"u"
+# define PRIuLEAST16	"u"
+# define PRIuLEAST32	"u"
+# define PRIuLEAST64	__PRI64_PREFIX "u"
+
+# define PRIuFAST8	"u"
+# define PRIuFAST16	__PRIPTR_PREFIX "u"
+# define PRIuFAST32	__PRIPTR_PREFIX "u"
+# define PRIuFAST64	__PRI64_PREFIX "u"
+
+/* lowercase hexadecimal notation.  */
+# define PRIx8		"x"
+# define PRIx16		"x"
+# define PRIx32		"x"
+# define PRIx64		__PRI64_PREFIX "x"
+
+# define PRIxLEAST8	"x"
+# define PRIxLEAST16	"x"
+# define PRIxLEAST32	"x"
+# define PRIxLEAST64	__PRI64_PREFIX "x"
+
+# define PRIxFAST8	"x"
+# define PRIxFAST16	__PRIPTR_PREFIX "x"
+# define PRIxFAST32	__PRIPTR_PREFIX "x"
+# define PRIxFAST64	__PRI64_PREFIX "x"
+
+/* UPPERCASE hexadecimal notation.  */
+# define PRIX8		"X"
+# define PRIX16		"X"
+# define PRIX32		"X"
+# define PRIX64		__PRI64_PREFIX "X"
+
+# define PRIXLEAST8	"X"
+# define PRIXLEAST16	"X"
+# define PRIXLEAST32	"X"
+# define PRIXLEAST64	__PRI64_PREFIX "X"
+
+# define PRIXFAST8	"X"
+# define PRIXFAST16	__PRIPTR_PREFIX "X"
+# define PRIXFAST32	__PRIPTR_PREFIX "X"
+# define PRIXFAST64	__PRI64_PREFIX "X"
+
+
+/* Macros for printing `intmax_t' and `uintmax_t'.  */
+# define PRIdMAX	__PRI64_PREFIX "d"
+# define PRIiMAX	__PRI64_PREFIX "i"
+# define PRIoMAX	__PRI64_PREFIX "o"
+# define PRIuMAX	__PRI64_PREFIX "u"
+# define PRIxMAX	__PRI64_PREFIX "x"
+# define PRIXMAX	__PRI64_PREFIX "X"
+
+
+/* Macros for printing `intptr_t' and `uintptr_t'.  */
+# define PRIdPTR	__PRIPTR_PREFIX "d"
+# define PRIiPTR	__PRIPTR_PREFIX "i"
+# define PRIoPTR	__PRIPTR_PREFIX "o"
+# define PRIuPTR	__PRIPTR_PREFIX "u"
+# define PRIxPTR	__PRIPTR_PREFIX "x"
+# define PRIXPTR	__PRIPTR_PREFIX "X"
+
+
+/* Macros for scanning format specifiers.  */
+
+/* Signed decimal notation.  */
+# define SCNd8		"hhd"
+# define SCNd16		"hd"
+# define SCNd32		"d"
+# define SCNd64		__PRI64_PREFIX "d"
+
+# define SCNdLEAST8	"hhd"
+# define SCNdLEAST16	"hd"
+# define SCNdLEAST32	"d"
+# define SCNdLEAST64	__PRI64_PREFIX "d"
+
+# define SCNdFAST8	"hhd"
+# define SCNdFAST16	__PRIPTR_PREFIX "d"
+# define SCNdFAST32	__PRIPTR_PREFIX "d"
+# define SCNdFAST64	__PRI64_PREFIX "d"
+
+/* Signed decimal notation.  */
+# define SCNi8		"hhi"
+# define SCNi16		"hi"
+# define SCNi32		"i"
+# define SCNi64		__PRI64_PREFIX "i"
+
+# define SCNiLEAST8	"hhi"
+# define SCNiLEAST16	"hi"
+# define SCNiLEAST32	"i"
+# define SCNiLEAST64	__PRI64_PREFIX "i"
+
+# define SCNiFAST8	"hhi"
+# define SCNiFAST16	__PRIPTR_PREFIX "i"
+# define SCNiFAST32	__PRIPTR_PREFIX "i"
+# define SCNiFAST64	__PRI64_PREFIX "i"
+
+/* Unsigned decimal notation.  */
+# define SCNu8		"hhu"
+# define SCNu16		"hu"
+# define SCNu32		"u"
+# define SCNu64		__PRI64_PREFIX "u"
+
+# define SCNuLEAST8	"hhu"
+# define SCNuLEAST16	"hu"
+# define SCNuLEAST32	"u"
+# define SCNuLEAST64	__PRI64_PREFIX "u"
+
+# define SCNuFAST8	"hhu"
+# define SCNuFAST16	__PRIPTR_PREFIX "u"
+# define SCNuFAST32	__PRIPTR_PREFIX "u"
+# define SCNuFAST64	__PRI64_PREFIX "u"
+
+/* Octal notation.  */
+# define SCNo8		"hho"
+# define SCNo16		"ho"
+# define SCNo32		"o"
+# define SCNo64		__PRI64_PREFIX "o"
+
+# define SCNoLEAST8	"hho"
+# define SCNoLEAST16	"ho"
+# define SCNoLEAST32	"o"
+# define SCNoLEAST64	__PRI64_PREFIX "o"
+
+# define SCNoFAST8	"hho"
+# define SCNoFAST16	__PRIPTR_PREFIX "o"
+# define SCNoFAST32	__PRIPTR_PREFIX "o"
+# define SCNoFAST64	__PRI64_PREFIX "o"
+
+/* Hexadecimal notation.  */
+# define SCNx8		"hhx"
+# define SCNx16		"hx"
+# define SCNx32		"x"
+# define SCNx64		__PRI64_PREFIX "x"
+
+# define SCNxLEAST8	"hhx"
+# define SCNxLEAST16	"hx"
+# define SCNxLEAST32	"x"
+# define SCNxLEAST64	__PRI64_PREFIX "x"
+
+# define SCNxFAST8	"hhx"
+# define SCNxFAST16	__PRIPTR_PREFIX "x"
+# define SCNxFAST32	__PRIPTR_PREFIX "x"
+# define SCNxFAST64	__PRI64_PREFIX "x"
+
+
+/* Macros for scanning `intmax_t' and `uintmax_t'.  */
+# define SCNdMAX	__PRI64_PREFIX "d"
+# define SCNiMAX	__PRI64_PREFIX "i"
+# define SCNoMAX	__PRI64_PREFIX "o"
+# define SCNuMAX	__PRI64_PREFIX "u"
+# define SCNxMAX	__PRI64_PREFIX "x"
+
+/* Macros for scaning `intptr_t' and `uintptr_t'.  */
+# define SCNdPTR	__PRIPTR_PREFIX "d"
+# define SCNiPTR	__PRIPTR_PREFIX "i"
+# define SCNoPTR	__PRIPTR_PREFIX "o"
+# define SCNuPTR	__PRIPTR_PREFIX "u"
+# define SCNxPTR	__PRIPTR_PREFIX "x"
+
+#endif	/* C++ && format macros */
+
+
+#if __WORDSIZE == 64
+
+/* We have to define the `uintmax_t' type using `ldiv_t'.  */
+typedef struct {
+	long int quot;		/* Quotient.  */
+	long int rem;		/* Remainder.  */
+} imaxdiv_t;
+
+#else
+
+/* We have to define the `uintmax_t' type using `lldiv_t'.  */
+typedef struct {
+	long long int quot;		/* Quotient.  */
+	long long int rem;		/* Remainder.  */
+} imaxdiv_t;
+
+#endif
+
+#endif /* inttypes.h */
diff --git a/include/libfdt.h b/include/libfdt.h
index a1ef1e15df3..f3cbb637be4 100644
--- a/include/libfdt.h
+++ b/include/libfdt.h
@@ -163,6 +163,31 @@ int fdt_first_subnode(const void *fdt, int offset);
  */
 int fdt_next_subnode(const void *fdt, int offset);
 
+/**
+ * fdt_for_each_subnode - iterate over all subnodes of a parent
+ *
+ * This is actually a wrapper around a for loop and would be used like so:
+ *
+ *	fdt_for_each_subnode(fdt, node, parent) {
+ *		...
+ *		use node
+ *		...
+ *	}
+ *
+ * Note that this is implemented as a macro and node is used as iterator in
+ * the loop. It should therefore be a locally allocated variable. The parent
+ * variable on the other hand is never modified, so it can be constant or
+ * even a literal.
+ *
+ * @fdt:	FDT blob (const void *)
+ * @node:	child node (int)
+ * @parent:	parent node (int)
+ */
+#define fdt_for_each_subnode(fdt, node, parent)		\
+	for (node = fdt_first_subnode(fdt, parent);	\
+	     node >= 0;					\
+	     node = fdt_next_subnode(fdt, node))
+
 /**********************************************************************/
 /* General functions                                                  */
 /**********************************************************************/
@@ -857,6 +882,53 @@ int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
  */
 int fdt_stringlist_contains(const char *strlist, int listlen, const char *str);
 
+/**
+ * fdt_count_strings - count the number of strings in a string list
+ * @fdt: pointer to the device tree blob
+ * @node: offset of the node
+ * @property: name of the property containing the string list
+ * @return: the number of strings in the given property
+ */
+int fdt_count_strings(const void *fdt, int node, const char *property);
+
+/**
+ * fdt_find_string - find a string in a string list and return its index
+ * @fdt: pointer to the device tree blob
+ * @node: offset of the node
+ * @property: name of the property containing the string list
+ * @string: string to look up in the string list
+ * @return: the index of the string or negative on error
+ */
+int fdt_find_string(const void *fdt, int node, const char *property,
+		    const char *string);
+
+/**
+ * fdt_get_string_index() - obtain the string at a given index in a string list
+ * @fdt: pointer to the device tree blob
+ * @node: offset of the node
+ * @property: name of the property containing the string list
+ * @index: index of the string to return
+ * @output: return location for the string
+ * @return: 0 if the string was found or a negative error code otherwise
+ */
+int fdt_get_string_index(const void *fdt, int node, const char *property,
+			 int index, const char **output);
+
+/**
+ * fdt_get_string() - obtain the string at a given index in a string list
+ * @fdt: pointer to the device tree blob
+ * @node: offset of the node
+ * @property: name of the property containing the string list
+ * @output: return location for the string
+ * @return: 0 if the string was found or a negative error code otherwise
+ *
+ * This is a shortcut for:
+ *
+ *	fdt_get_string_index(fdt, node, property, 0, output).
+ */
+int fdt_get_string(const void *fdt, int node, const char *property,
+		   const char **output);
+
 /**********************************************************************/
 /* Read-only functions (addressing related)                           */
 /**********************************************************************/
diff --git a/include/linker_lists.h b/include/linker_lists.h
index 507d61ba9a5..d37fba44dca 100644
--- a/include/linker_lists.h
+++ b/include/linker_lists.h
@@ -11,6 +11,8 @@
 #ifndef __LINKER_LISTS_H__
 #define __LINKER_LISTS_H__
 
+#include <linux/compiler.h>
+
 /*
  * There is no use in including this from ASM files, but that happens
  * anyway, e.g. PPC kgdb.S includes command.h which incluse us.
@@ -141,6 +143,27 @@
 			section(".u_boot_list_2_"#_list"_2_"#_name)))
 
 /**
+ * ll_entry_declare_list() - Declare a list of link-generated array entries
+ * @_type:	Data type of each entry
+ * @_name:	Name of the entry
+ * @_list:	name of the list. Should contain only characters allowed
+ *		in a C variable name!
+ *
+ * This is like ll_entry_declare() but creates multiple entries. It should
+ * be assigned to an array.
+ *
+ * ll_entry_declare_list(struct my_sub_cmd, my_sub_cmd, cmd_sub, cmd.sub) = {
+ *	{ .x = 3, .y = 4 },
+ *	{ .x = 8, .y = 2 },
+ *	{ .x = 1, .y = 7 }
+ * };
+ */
+#define ll_entry_declare_list(_type, _name, _list)			\
+	_type _u_boot_list_2_##_list##_2_##_name[] __aligned(4)		\
+			__attribute__((unused,				\
+			section(".u_boot_list_2_"#_list"_2_"#_name)))
+
+/**
  * We need a 0-byte-size type for iterator symbols, and the compiler
  * does not allow defining objects of C type 'void'. Using an empty
  * struct is allowed by the compiler, but causes gcc versions 4.4 and
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
new file mode 100644
index 00000000000..717cbeab37f
--- /dev/null
+++ b/include/linux/mbus.h
@@ -0,0 +1,73 @@
+/*
+ * Marvell MBUS common definitions.
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __LINUX_MBUS_H
+#define __LINUX_MBUS_H
+
+struct resource;
+
+struct mbus_dram_target_info {
+	/*
+	 * The 4-bit MBUS target ID of the DRAM controller.
+	 */
+	u8		mbus_dram_target_id;
+
+	/*
+	 * The base address, size, and MBUS attribute ID for each
+	 * of the possible DRAM chip selects.  Peripherals are
+	 * required to support at least 4 decode windows.
+	 */
+	int		num_cs;
+	struct mbus_dram_window {
+		u8	cs_index;
+		u8	mbus_attr;
+		u32	base;
+		u32	size;
+	} cs[4];
+};
+
+struct mvebu_mbus_state {
+	void __iomem *mbuswins_base;
+	void __iomem *sdramwins_base;
+	struct dentry *debugfs_root;
+	struct dentry *debugfs_sdram;
+	struct dentry *debugfs_devs;
+	const struct mvebu_mbus_soc_data *soc;
+	int hw_io_coherency;
+};
+
+/* Flags for PCI/PCIe address decoding regions */
+#define MVEBU_MBUS_PCI_IO  0x1
+#define MVEBU_MBUS_PCI_MEM 0x2
+#define MVEBU_MBUS_PCI_WA  0x3
+
+/*
+ * Magic value that explicits that we don't need a remapping-capable
+ * address decoding window.
+ */
+#define MVEBU_MBUS_NO_REMAP (0xffffffff)
+
+/* Maximum size of a mbus window name */
+#define MVEBU_MBUS_MAX_WINNAME_SZ 32
+
+const struct mbus_dram_target_info *mvebu_mbus_dram_info(void);
+void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
+void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
+int mvebu_mbus_add_window_remap_by_id(unsigned int target,
+				      unsigned int attribute,
+				      phys_addr_t base, size_t size,
+				      phys_addr_t remap);
+int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
+				phys_addr_t base, size_t size);
+int mvebu_mbus_del_window(phys_addr_t base, size_t size);
+int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
+		      u32 base, u32 size, u8 target, u8 attr);
+
+#endif /* __LINUX_MBUS_H */
diff --git a/include/linux/string.h b/include/linux/string.h
index 8e44855712c..96348d617fc 100644
--- a/include/linux/string.h
+++ b/include/linux/string.h
@@ -20,6 +20,10 @@ extern __kernel_size_t strspn(const char *,const char *);
  */
 #include <asm/string.h>
 
+#ifndef __HAVE_ARCH_BCOPY
+char *bcopy(const char *src, char *dest, int count);
+#endif
+
 #ifndef __HAVE_ARCH_STRCPY
 extern char * strcpy(char *,const char *);
 #endif
@@ -89,6 +93,9 @@ extern void * memchr(const void *,int,__kernel_size_t);
 void *memchr_inv(const void *, int, size_t);
 #endif
 
+unsigned long ustrtoul(const char *cp, char **endp, unsigned int base);
+unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/linux/types.h b/include/linux/types.h
index 9aebc4e8cf0..c9a8d9a8c2c 100644
--- a/include/linux/types.h
+++ b/include/linux/types.h
@@ -104,7 +104,8 @@ typedef		__u8		uint8_t;
 typedef		__u16		uint16_t;
 typedef		__u32		uint32_t;
 
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__) && \
+	(!defined(CONFIG_USE_STDINT) || !defined(__INT64_TYPE__))
 typedef		__u64		uint64_t;
 typedef		__u64		u_int64_t;
 typedef		__s64		int64_t;
@@ -112,6 +113,12 @@ typedef		__s64		int64_t;
 
 #endif /* __KERNEL_STRICT_NAMES */
 
+#if defined(CONFIG_USE_STDINT) && defined(__INT64_TYPE__)
+typedef		__UINT64_TYPE__	uint64_t;
+typedef		__UINT64_TYPE__	u_int64_t;
+typedef		__INT64_TYPE__		int64_t;
+#endif
+
 /*
  * Below are truly Linux-specific types that should never collide with
  * any application/library that wants linux/types.h.
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index 97d179a6e9e..7edc760c7b2 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -41,7 +41,8 @@
 #define DWC3_REG_OFFSET				0xC100
 
 struct g_event_buffer {
-	u64 g_evntadr;
+	u32 g_evntadrlo;
+	u32 g_evntadrhi;
 	u32 g_evntsiz;
 	u32 g_evntcount;
 };
@@ -185,4 +186,9 @@ struct dwc3 {					/* offset: 0xC100 */
 #define DWC3_GTXFIFOSIZ_TXFDEF(n)		((n) & 0xffff)
 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n)		((n) & 0xffff0000)
 
+/* Device Control Register */
+#define DWC3_DCTL_RUN_STOP			(1 << 31)
+#define DWC3_DCTL_CSFTRST			(1 << 30)
+#define DWC3_DCTL_LSFTRST			(1 << 29)
+
 #endif /* __DWC3_H_ */
diff --git a/include/linux/usb/musb.h b/include/linux/usb/musb.h
index 9f65ef96ac1..075d222195f 100644
--- a/include/linux/usb/musb.h
+++ b/include/linux/usb/musb.h
@@ -14,6 +14,8 @@
 #define __deprecated
 #endif
 
+#include <linux/compat.h>
+
 /* The USB role is defined by the connector used on the board, so long as
  * standards are being followed.  (Developer boards sometimes won't.)
  */
diff --git a/include/mmc.h b/include/mmc.h
index 7f5f9bc8ca8..d74a190eea0 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -387,6 +387,7 @@ int mmc_legacy_init(int verbose);
 
 int board_mmc_init(bd_t *bis);
 int cpu_mmc_init(bd_t *bis);
+int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
 
 /* Set block count limit because of 16 bit register limit on some hardware*/
 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
diff --git a/include/netdev.h b/include/netdev.h
index a887bfb5f7a..34651ab3779 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -65,6 +65,7 @@ int mpc512x_fec_initialize(bd_t *bis);
 int mpc5xxx_fec_initialize(bd_t *bis);
 int mpc82xx_scc_enet_initialize(bd_t *bis);
 int mvgbe_initialize(bd_t *bis);
+int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr);
 int natsemi_initialize(bd_t *bis);
 int ne2k_register(void);
 int npe_initialize(bd_t *bis);
diff --git a/include/ns16550.h b/include/ns16550.h
index 5784cfd97b8..0607379537d 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -53,7 +53,7 @@
  * @clock:		UART base clock speed in Hz
  */
 struct ns16550_platdata {
-	unsigned char *base;
+	unsigned long base;
 	int reg_shift;
 	int clock;
 };
diff --git a/include/pci_ids.h b/include/pci_ids.h
index f220c3aa5cb..f84c13ac642 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -2547,10 +2547,12 @@
 #define PCI_DEVICE_ID_INTEL_82380FB	0x124b
 #define PCI_DEVICE_ID_INTEL_82439	0x1250
 #define PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED		0x1531
+#define PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED		0x1532
 #define PCI_DEVICE_ID_INTEL_I210_COPPER			0x1533
 #define PCI_DEVICE_ID_INTEL_I210_SERDES			0x1536
 #define PCI_DEVICE_ID_INTEL_I210_1000BASEKX		0x1537
 #define PCI_DEVICE_ID_INTEL_I210_EXTPHY			0x1538
+#define PCI_DEVICE_ID_INTEL_I211_COPPER			0x1539
 #define PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS	0x157b
 #define PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS	0x157c
 #define PCI_DEVICE_ID_INTEL_80960_RP	0x1960
diff --git a/include/pcmcia.h b/include/pcmcia.h
index 4b667f49ce9..00065b2fdde 100644
--- a/include/pcmcia.h
+++ b/include/pcmcia.h
@@ -29,8 +29,6 @@
 # define CONFIG_PCMCIA_SLOT_A
 #elif defined(CONFIG_LWMON)		/* The LWMON  use SLOT_B	*/
 # define CONFIG_PCMCIA_SLOT_B
-#elif defined(CONFIG_ICU862)		/* The ICU862 use SLOT_B	*/
-# define CONFIG_PCMCIA_SLOT_B
 #elif defined(CONFIG_R360MPI)		/* The R360MPI use SLOT_B	*/
 # define CONFIG_PCMCIA_SLOT_B
 #elif defined(CONFIG_ATC)		/* The ATC use SLOT_A	*/
diff --git a/include/phy.h b/include/phy.h
index 2fcc328d5bc..b4950776977 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -32,7 +32,9 @@
 #define PHY_10G_FEATURES	(PHY_GBIT_FEATURES | \
 				SUPPORTED_10000baseT_Full)
 
+#ifndef PHY_ANEG_TIMEOUT
 #define PHY_ANEG_TIMEOUT	4000
+#endif
 
 
 typedef enum {
diff --git a/include/serial.h b/include/serial.h
index 8f574e4ef89..66ed12c9c21 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -164,4 +164,53 @@ struct serial_dev_priv {
 /* Access the serial operations for a device */
 #define serial_get_ops(dev)	((struct dm_serial_ops *)(dev)->driver->ops)
 
+void altera_jtag_serial_initialize(void);
+void altera_serial_initialize(void);
+void amirix_serial_initialize(void);
+void arc_serial_initialize(void);
+void arm_dcc_initialize(void);
+void asc_serial_initialize(void);
+void atmel_serial_initialize(void);
+void au1x00_serial_initialize(void);
+void bfin_jtag_initialize(void);
+void bfin_serial_initialize(void);
+void bmw_serial_initialize(void);
+void clps7111_serial_initialize(void);
+void cogent_serial_initialize(void);
+void cpci750_serial_initialize(void);
+void evb64260_serial_initialize(void);
+void imx_serial_initialize(void);
+void iop480_serial_initialize(void);
+void jz_serial_initialize(void);
+void ks8695_serial_initialize(void);
+void leon2_serial_initialize(void);
+void leon3_serial_initialize(void);
+void lh7a40x_serial_initialize(void);
+void lpc32xx_serial_initialize(void);
+void marvell_serial_initialize(void);
+void max3100_serial_initialize(void);
+void mcf_serial_initialize(void);
+void ml2_serial_initialize(void);
+void mpc512x_serial_initialize(void);
+void mpc5xx_serial_initialize(void);
+void mpc8260_scc_serial_initialize(void);
+void mpc8260_smc_serial_initialize(void);
+void mpc85xx_serial_initialize(void);
+void mpc8xx_serial_initialize(void);
+void mxc_serial_initialize(void);
+void mxs_auart_initialize(void);
+void ns16550_serial_initialize(void);
+void oc_serial_initialize(void);
+void p3mx_serial_initialize(void);
+void pl01x_serial_initialize(void);
+void pxa_serial_initialize(void);
+void s3c24xx_serial_initialize(void);
+void s5p_serial_initialize(void);
+void sa1100_serial_initialize(void);
+void sandbox_serial_initialize(void);
+void sconsole_serial_initialize(void);
+void sh_serial_initialize(void);
+void uartlite_serial_initialize(void);
+void zynq_serial_initialize(void);
+
 #endif
diff --git a/include/spi.h b/include/spi.h
index b673be270c8..aa0a48ea627 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -54,12 +54,31 @@
 
 #define SPI_DEFAULT_WORDLEN 8
 
+#ifdef CONFIG_DM_SPI
+struct dm_spi_bus {
+	uint max_hz;
+};
+
+#endif /* CONFIG_DM_SPI */
+
 /**
  * struct spi_slave - Representation of a SPI slave
  *
- * Drivers are expected to extend this with controller-specific data.
+ * For driver model this is the per-child data used by the SPI bus. It can
+ * be accessed using dev_get_parentdata() on the slave device. Each SPI
+ * driver should define this child data in its U_BOOT_DRIVER() definition:
+ *
+ *	.per_child_auto_alloc_size	= sizeof(struct spi_slave),
  *
- * @bus:		ID of the bus that the slave is attached to.
+ * If not using driver model, drivers are expected to extend this with
+ * controller-specific data.
+ *
+ * @dev:		SPI slave device
+ * @max_hz:		Maximum speed for this slave
+ * @mode:		SPI mode to use for this slave (see SPI mode flags)
+ * @bus:		ID of the bus that the slave is attached to. For
+ *			driver model this is the sequence number of the SPI
+ *			bus (bus->seq) so does not need to be stored
  * @cs:			ID of the chip select connected to the slave.
  * @op_mode_rx:		SPI RX operation mode.
  * @op_mode_tx:		SPI TX operation mode.
@@ -71,7 +90,13 @@
  * @flags:		Indication of SPI flags.
  */
 struct spi_slave {
+#ifdef CONFIG_DM_SPI
+	struct udevice *dev;	/* struct spi_slave is dev->parentdata */
+	uint max_hz;
+	uint mode;
+#else
 	unsigned int bus;
+#endif
 	unsigned int cs;
 	u8 op_mode_rx;
 	u8 op_mode_tx;
@@ -228,8 +253,9 @@ int  spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
  * Returns: 1 if bus:cs identifies a valid chip on this board, 0
  * otherwise.
  */
-int  spi_cs_is_valid(unsigned int bus, unsigned int cs);
+int spi_cs_is_valid(unsigned int bus, unsigned int cs);
 
+#ifndef CONFIG_DM_SPI
 /**
  * Activate a SPI chipselect.
  * This function is provided by the board code when using a driver
@@ -255,6 +281,7 @@ void spi_cs_deactivate(struct spi_slave *slave);
  * @hz:		The transfer speed
  */
 void spi_set_speed(struct spi_slave *slave, uint hz);
+#endif
 
 /**
  * Write 8 bits, then read 8 bits.
@@ -305,4 +332,270 @@ struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
 struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum,
 					   int node);
 
+#ifdef CONFIG_DM_SPI
+
+/**
+ * struct spi_cs_info - Information about a bus chip select
+ *
+ * @dev:	Connected device, or NULL if none
+ */
+struct spi_cs_info {
+	struct udevice *dev;
+};
+
+/**
+ * struct struct dm_spi_ops - Driver model SPI operations
+ *
+ * The uclass interface is implemented by all SPI devices which use
+ * driver model.
+ */
+struct dm_spi_ops {
+	/**
+	 * Claim the bus and prepare it for communication.
+	 *
+	 * The device provided is the slave device. It's parent controller
+	 * will be used to provide the communication.
+	 *
+	 * This must be called before doing any transfers with a SPI slave. It
+	 * will enable and initialize any SPI hardware as necessary, and make
+	 * sure that the SCK line is in the correct idle state. It is not
+	 * allowed to claim the same bus for several slaves without releasing
+	 * the bus in between.
+	 *
+	 * @bus:	The SPI slave
+	 *
+	 * Returns: 0 if the bus was claimed successfully, or a negative value
+	 * if it wasn't.
+	 */
+	int (*claim_bus)(struct udevice *bus);
+
+	/**
+	 * Release the SPI bus
+	 *
+	 * This must be called once for every call to spi_claim_bus() after
+	 * all transfers have finished. It may disable any SPI hardware as
+	 * appropriate.
+	 *
+	 * @bus:	The SPI slave
+	 */
+	int (*release_bus)(struct udevice *bus);
+
+	/**
+	 * Set the word length for SPI transactions
+	 *
+	 * Set the word length (number of bits per word) for SPI transactions.
+	 *
+	 * @bus:	The SPI slave
+	 * @wordlen:	The number of bits in a word
+	 *
+	 * Returns: 0 on success, -ve on failure.
+	 */
+	int (*set_wordlen)(struct udevice *bus, unsigned int wordlen);
+
+	/**
+	 * SPI transfer
+	 *
+	 * This writes "bitlen" bits out the SPI MOSI port and simultaneously
+	 * clocks "bitlen" bits in the SPI MISO port.  That's just the way SPI
+	 * works.
+	 *
+	 * The source of the outgoing bits is the "dout" parameter and the
+	 * destination of the input bits is the "din" parameter.  Note that
+	 * "dout" and "din" can point to the same memory location, in which
+	 * case the input data overwrites the output data (since both are
+	 * buffered by temporary variables, this is OK).
+	 *
+	 * spi_xfer() interface:
+	 * @dev:	The slave device to communicate with
+	 * @bitlen:	How many bits to write and read.
+	 * @dout:	Pointer to a string of bits to send out.  The bits are
+	 *		held in a byte array and are sent MSB first.
+	 * @din:	Pointer to a string of bits that will be filled in.
+	 * @flags:	A bitwise combination of SPI_XFER_* flags.
+	 *
+	 * Returns: 0 on success, not -1 on failure
+	 */
+	int (*xfer)(struct udevice *dev, unsigned int bitlen, const void *dout,
+		    void *din, unsigned long flags);
+
+	/**
+	 * Set transfer speed.
+	 * This sets a new speed to be applied for next spi_xfer().
+	 * @bus:	The SPI bus
+	 * @hz:		The transfer speed
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_speed)(struct udevice *bus, uint hz);
+
+	/**
+	 * Set the SPI mode/flags
+	 *
+	 * It is unclear if we want to set speed and mode together instead
+	 * of separately.
+	 *
+	 * @bus:	The SPI bus
+	 * @mode:	Requested SPI mode (SPI_... flags)
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_mode)(struct udevice *bus, uint mode);
+
+	/**
+	 * Get information on a chip select
+	 *
+	 * This is only called when the SPI uclass does not know about a
+	 * chip select, i.e. it has no attached device. It gives the driver
+	 * a chance to allow activity on that chip select even so.
+	 *
+	 * @bus:	The SPI bus
+	 * @cs:		The chip select (0..n-1)
+	 * @info:	Returns information about the chip select, if valid.
+	 *		On entry info->dev is NULL
+	 * @return 0 if OK (and @info is set up), -ENODEV if the chip select
+	 *	   is invalid, other -ve value on error
+	 */
+	int (*cs_info)(struct udevice *bus, uint cs, struct spi_cs_info *info);
+};
+
+struct dm_spi_emul_ops {
+	/**
+	 * SPI transfer
+	 *
+	 * This writes "bitlen" bits out the SPI MOSI port and simultaneously
+	 * clocks "bitlen" bits in the SPI MISO port.  That's just the way SPI
+	 * works. Here the device is a slave.
+	 *
+	 * The source of the outgoing bits is the "dout" parameter and the
+	 * destination of the input bits is the "din" parameter.  Note that
+	 * "dout" and "din" can point to the same memory location, in which
+	 * case the input data overwrites the output data (since both are
+	 * buffered by temporary variables, this is OK).
+	 *
+	 * spi_xfer() interface:
+	 * @slave:	The SPI slave which will be sending/receiving the data.
+	 * @bitlen:	How many bits to write and read.
+	 * @dout:	Pointer to a string of bits sent to the device. The
+	 *		bits are held in a byte array and are sent MSB first.
+	 * @din:	Pointer to a string of bits that will be sent back to
+	 *		the master.
+	 * @flags:	A bitwise combination of SPI_XFER_* flags.
+	 *
+	 * Returns: 0 on success, not -1 on failure
+	 */
+	int (*xfer)(struct udevice *slave, unsigned int bitlen,
+		    const void *dout, void *din, unsigned long flags);
+};
+
+/**
+ * spi_find_bus_and_cs() - Find bus and slave devices by number
+ *
+ * Given a bus number and chip select, this finds the corresponding bus
+ * device and slave device. Neither device is activated by this function,
+ * although they may have been activated previously.
+ *
+ * @busnum:	SPI bus number
+ * @cs:		Chip select to look for
+ * @busp:	Returns bus device
+ * @devp:	Return slave device
+ * @return 0 if found, -ENODEV on error
+ */
+int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp,
+			struct udevice **devp);
+
+/**
+ * spi_get_bus_and_cs() - Find and activate bus and slave devices by number
+ *
+ * Given a bus number and chip select, this finds the corresponding bus
+ * device and slave device.
+ *
+ * If no such slave exists, and drv_name is not NULL, then a new slave device
+ * is automatically bound on this chip select.
+ *
+ * Ths new slave device is probed ready for use with the given speed and mode.
+ *
+ * @busnum:	SPI bus number
+ * @cs:		Chip select to look for
+ * @speed:	SPI speed to use for this slave
+ * @mode:	SPI mode to use for this slave
+ * @drv_name:	Name of driver to attach to this chip select
+ * @dev_name:	Name of the new device thus created
+ * @busp:	Returns bus device
+ * @devp:	Return slave device
+ * @return 0 if found, -ve on error
+ */
+int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
+			const char *drv_name, const char *dev_name,
+			struct udevice **busp, struct spi_slave **devp);
+
+/**
+ * spi_chip_select() - Get the chip select for a slave
+ *
+ * @return the chip select this slave is attached to
+ */
+int spi_chip_select(struct udevice *slave);
+
+/**
+ * spi_bind_device() - bind a device to a bus's chip select
+ *
+ * This binds a new device to an given chip select (which must be unused).
+ *
+ * @bus:	SPI bus to search
+ * @cs:		Chip select to attach to
+ * @drv_name:	Name of driver to attach to this chip select
+ * @dev_name:	Name of the new device thus created
+ * @devp:	Returns the newly bound device
+ */
+int spi_bind_device(struct udevice *bus, int cs, const char *drv_name,
+		    const char *dev_name, struct udevice **devp);
+
+/**
+ * spi_ofdata_to_platdata() - decode standard SPI platform data
+ *
+ * This decodes the speed and mode from a device tree node and puts it into
+ * the spi_slave structure.
+ *
+ * @blob:	Device tree blob
+ * @node:	Node offset to read from
+ * @spi:	Place to put the decoded information
+ */
+int spi_ofdata_to_platdata(const void *blob, int node, struct spi_slave *spi);
+
+/**
+ * spi_cs_info() - Check information on a chip select
+ *
+ * This checks a particular chip select on a bus to see if it has a device
+ * attached, or is even valid.
+ *
+ * @bus:	The SPI bus
+ * @cs:		The chip select (0..n-1)
+ * @info:	Returns information about the chip select, if valid
+ * @return 0 if OK (and @info is set up), -ENODEV if the chip select
+ *	   is invalid, other -ve value on error
+ */
+int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info);
+
+struct sandbox_state;
+
+/**
+ * sandbox_spi_get_emul() - get an emulator for a SPI slave
+ *
+ * This provides a way to attach an emulated SPI device to a particular SPI
+ * slave, so that xfer() operations on the slave will be handled by the
+ * emulator. If a emulator already exists on that chip select it is returned.
+ * Otherwise one is created.
+ *
+ * @state:	Sandbox state
+ * @bus:	SPI bus requesting the emulator
+ * @slave:	SPI slave device requesting the emulator
+ * @emuip:	Returns pointer to emulator
+ * @return 0 if OK, -ve on error
+ */
+int sandbox_spi_get_emul(struct sandbox_state *state,
+			 struct udevice *bus, struct udevice *slave,
+			 struct udevice **emulp);
+
+/* Access the serial operations for a device */
+#define spi_get_ops(dev)	((struct dm_spi_ops *)(dev)->driver->ops)
+#define spi_emul_get_ops(dev)	((struct dm_spi_emul_ops *)(dev)->driver->ops)
+#endif /* CONFIG_DM_SPI */
+
 #endif	/* _SPI_H_ */
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 408a5b401cd..5913b39e268 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -15,9 +15,8 @@
 #ifndef _SPI_FLASH_H_
 #define _SPI_FLASH_H_
 
-#include <spi.h>
+#include <dm.h>	/* Because we dereference struct udevice here */
 #include <linux/types.h>
-#include <linux/compiler.h>
 
 #ifndef CONFIG_SF_DEFAULT_SPEED
 # define CONFIG_SF_DEFAULT_SPEED	1000000
@@ -32,64 +31,19 @@
 # define CONFIG_SF_DEFAULT_BUS		0
 #endif
 
-/* sf param flags */
-#define SECT_4K		1 << 1
-#define SECT_32K	1 << 2
-#define E_FSR		1 << 3
-#define WR_QPP		1 << 4
-
-/* Enum list - Full read commands */
-enum spi_read_cmds {
-	ARRAY_SLOW = 1 << 0,
-	DUAL_OUTPUT_FAST = 1 << 1,
-	DUAL_IO_FAST = 1 << 2,
-	QUAD_OUTPUT_FAST = 1 << 3,
-	QUAD_IO_FAST = 1 << 4,
-};
-#define RD_EXTN		ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST
-#define RD_FULL		RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST
-
-/* Dual SPI flash memories */
-enum spi_dual_flash {
-	SF_SINGLE_FLASH = 0,
-	SF_DUAL_STACKED_FLASH = 1 << 0,
-	SF_DUAL_PARALLEL_FLASH = 1 << 1,
-};
-
-/**
- * struct spi_flash_params - SPI/QSPI flash device params structure
- *
- * @name:		Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
- * @jedec:		Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
- * @ext_jedec:		Device ext_jedec ID
- * @sector_size:	Sector size of this device
- * @nr_sectors:		No.of sectors on this device
- * @e_rd_cmd:		Enum list for read commands
- * @flags:		Important param, for flash specific behaviour
- */
-struct spi_flash_params {
-	const char *name;
-	u32 jedec;
-	u16 ext_jedec;
-	u32 sector_size;
-	u32 nr_sectors;
-	u8 e_rd_cmd;
-	u16 flags;
-};
-
-extern const struct spi_flash_params spi_flash_params_table[];
+struct spi_slave;
 
 /**
  * struct spi_flash - SPI flash structure
  *
  * @spi:		SPI slave
  * @name:		Name of SPI flash
- * @dual_flash:		Indicates dual flash memories - dual stacked, parallel
+ * @dual_flash:	Indicates dual flash memories - dual stacked, parallel
  * @shift:		Flash shift useful in dual parallel
  * @size:		Total flash size
  * @page_size:		Write (page) size
  * @sector_size:	Sector size
- * @erase_size:		Erase size
+ * @erase_size:	Erase size
  * @bank_read_cmd:	Bank read cmd
  * @bank_write_cmd:	Bank write cmd
  * @bank_curr:		Current flash bank
@@ -97,8 +51,8 @@ extern const struct spi_flash_params spi_flash_params_table[];
  * @erase_cmd:		Erase cmd 4K, 32K, 64K
  * @read_cmd:		Read cmd - Array Fast, Extn read and quad read.
  * @write_cmd:		Write cmd - page and quad program.
- * @dummy_byte:		Dummy cycles for read operation.
- * @memory_map:		Address of read-only SPI flash access
+ * @dummy_byte:	Dummy cycles for read operation.
+ * @memory_map:	Address of read-only SPI flash access
  * @read:		Flash read ops: Read len bytes at offset into buf
  *			Supported cmds: Fast Array Read
  * @write:		Flash write ops: Write len bytes from buf into offset
@@ -108,7 +62,12 @@ extern const struct spi_flash_params spi_flash_params_table[];
  * return 0 - Success, 1 - Failure
  */
 struct spi_flash {
+#ifdef CONFIG_DM_SPI_FLASH
+	struct spi_slave *spi;
+	struct udevice *dev;
+#else
 	struct spi_slave *spi;
+#endif
 	const char *name;
 	u8 dual_flash;
 	u8 shift;
@@ -129,12 +88,75 @@ struct spi_flash {
 	u8 dummy_byte;
 
 	void *memory_map;
+#ifndef CONFIG_DM_SPI_FLASH
+	/*
+	 * These are not strictly needed for driver model, but keep them here
+	 * whilt the transition is in progress.
+	 *
+	 * Normally each driver would provide its own operations, but for
+	 * SPI flash most chips use the same algorithms. One approach is
+	 * to create a 'common' SPI flash device which knows how to talk
+	 * to most devices, and then allow other drivers to be used instead
+	 * if requird, perhaps with a way of scanning through the list to
+	 * find the driver that matches the device.
+	 */
 	int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);
 	int (*write)(struct spi_flash *flash, u32 offset, size_t len,
 			const void *buf);
 	int (*erase)(struct spi_flash *flash, u32 offset, size_t len);
+#endif
 };
 
+struct dm_spi_flash_ops {
+	int (*read)(struct udevice *dev, u32 offset, size_t len, void *buf);
+	int (*write)(struct udevice *dev, u32 offset, size_t len,
+		     const void *buf);
+	int (*erase)(struct udevice *dev, u32 offset, size_t len);
+};
+
+/* Access the serial operations for a device */
+#define sf_get_ops(dev) ((struct dm_spi_flash_ops *)(dev)->driver->ops)
+
+#ifdef CONFIG_DM_SPI_FLASH
+int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
+			   unsigned int max_hz, unsigned int spi_mode,
+			   struct udevice **devp);
+
+/* Compatibility function - this is the old U-Boot API */
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int spi_mode);
+
+/* Compatibility function - this is the old U-Boot API */
+void spi_flash_free(struct spi_flash *flash);
+
+int spi_flash_remove(struct udevice *flash);
+
+static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
+		size_t len, void *buf)
+{
+	return sf_get_ops(flash->dev)->read(flash->dev, offset, len, buf);
+}
+
+static inline int spi_flash_write(struct spi_flash *flash, u32 offset,
+		size_t len, const void *buf)
+{
+	return sf_get_ops(flash->dev)->write(flash->dev, offset, len, buf);
+}
+
+static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
+		size_t len)
+{
+	return sf_get_ops(flash->dev)->erase(flash->dev, offset, len);
+}
+
+struct sandbox_state;
+
+int sandbox_sf_bind_emul(struct sandbox_state *state, int busnum, int cs,
+			 struct udevice *bus, int of_offset, const char *spec);
+
+void sandbox_sf_unbind_emul(struct sandbox_state *state, int busnum, int cs);
+
+#else
 struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
 		unsigned int max_hz, unsigned int spi_mode);
 
@@ -169,6 +191,7 @@ static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
 {
 	return flash->erase(flash, offset, len);
 }
+#endif
 
 void spi_boot(void) __noreturn;
 void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
diff --git a/include/spl.h b/include/spl.h
index a7e41da7fd4..16b3566a947 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -15,7 +15,7 @@
 /* Boot type */
 #define MMCSD_MODE_UNDEFINED	0
 #define MMCSD_MODE_RAW		1
-#define MMCSD_MODE_FAT		2
+#define MMCSD_MODE_FS		2
 #define MMCSD_MODE_EMMCBOOT	3
 
 struct spl_image_info {
@@ -72,6 +72,12 @@ void spl_sata_load_image(void);
 int spl_load_image_fat(block_dev_desc_t *block_dev, int partition, const char *filename);
 int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition);
 
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image);
+
+/* SPL EXT image functions */
+int spl_load_image_ext(block_dev_desc_t *block_dev, int partition, const char *filename);
+int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition);
+
 #ifdef CONFIG_SPL_BOARD_INIT
 void spl_board_init(void);
 #endif
diff --git a/include/status_led.h b/include/status_led.h
index c1d2242b9db..c5de8943324 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -114,25 +114,6 @@ void status_led_set  (int led, int state);
 # define STATUS_LED_GREEN	1
 # define STATUS_LED_BOOT	2		/* IDE LED used for boot status */
 
-/*****  ICU862   ********************************************************/
-#elif defined(CONFIG_ICU862)
-
-# define STATUS_LED_PAR		im_ioport.iop_papar
-# define STATUS_LED_DIR		im_ioport.iop_padir
-# define STATUS_LED_ODR		im_ioport.iop_paodr
-# define STATUS_LED_DAT		im_ioport.iop_padat
-
-# define STATUS_LED_BIT		0x4000		/* LED 0 is on PA.1 */
-# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
-# define STATUS_LED_STATE	STATUS_LED_BLINKING
-# define STATUS_LED_BIT1	0x1000		/* LED 1 is on PA.3 */
-# define STATUS_LED_PERIOD1	(CONFIG_SYS_HZ)
-# define STATUS_LED_STATE1	STATUS_LED_OFF
-
-# define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
-
-# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
-
 /*****  Someone else defines these  *************************************/
 #elif defined(STATUS_LED_PAR)
 
diff --git a/include/stdlib.h b/include/stdlib.h
new file mode 100644
index 00000000000..6bc7fbb3c4c
--- /dev/null
+++ b/include/stdlib.h
@@ -0,0 +1,12 @@
+/*
+ *  Copyright (C) 2013 Google Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __STDLIB_H_
+#define __STDLIB_H_
+
+#include <malloc.h>
+
+#endif /* __STDLIB_H_ */
diff --git a/include/twl4030.h b/include/twl4030.h
index 093c61d6db0..18795a601b5 100644
--- a/include/twl4030.h
+++ b/include/twl4030.h
@@ -395,6 +395,8 @@
 #define TWL4030_PM_RECEIVER_VDAC_VSEL_18		0x03
 #define TWL4030_PM_RECEIVER_VMMC1_VSEL_30		0x02
 #define TWL4030_PM_RECEIVER_VMMC1_VSEL_32		0x03
+#define TWL4030_PM_RECEIVER_VMMC2_VSEL_30		0x0B
+#define TWL4030_PM_RECEIVER_VMMC2_VSEL_32		0x0C
 #define TWL4030_PM_RECEIVER_VSIM_VSEL_18		0x03
 
 /* Device Selection in PM Receiver Module */
diff --git a/include/usb.h b/include/usb.h
index c355fbe4819..9d0d04dd8e1 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -129,6 +129,8 @@ struct usb_device {
 	unsigned int slot_id;
 };
 
+struct int_queue;
+
 /*
  * You can initialize platform's USB host or device
  * ports by passing this enum as an argument to
@@ -150,7 +152,8 @@ enum usb_init_type {
 	defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \
 	defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X) || \
 	defined(CONFIG_USB_MUSB_DSPS) || defined(CONFIG_USB_MUSB_AM35X) || \
-	defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_XHCI)
+	defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_XHCI) || \
+	defined(CONFIG_USB_DWC2)
 
 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller);
 int usb_lowlevel_stop(int index);
@@ -162,6 +165,13 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 			int transfer_len, int interval);
 
+#ifdef CONFIG_USB_EHCI /* Only the ehci code has pollable int support */
+struct int_queue *create_int_queue(struct usb_device *dev, unsigned long pipe,
+	int queuesize, int elementsize, void *buffer);
+int destroy_int_queue(struct usb_device *dev, struct int_queue *queue);
+void *poll_int_queue(struct usb_device *dev, struct int_queue *queue);
+#endif
+
 /* Defines */
 #define USB_UHCI_VEND_ID	0x8086
 #define USB_UHCI_DEV_ID		0x7112
diff --git a/include/usb/omap1510_udc.h b/include/usb/omap1510_udc.h
deleted file mode 100644
index adfbf549965..00000000000
--- a/include/usb/omap1510_udc.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * (C) Copyright 2003
- * Gerry Hamel, geh@ti.com, Texas Instruments
- *
- * Based on
- * linux/drivers/usb/device/bi/omap.h
- * Register definitions for TI OMAP1510 USB bus interface driver
- *
- * Author: MontaVista Software, Inc.
- *	   source@mvista.com
- *
- * 2003 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __USBDCORE_OMAP1510_H__
-#define __USBDCORE_OMAP1510_H__
-
-
-/*
- * 13.2 MPU Register Map
- */
-
-/* Table 13-1. USB Function Module Registers (endpoint) */
-#define UDC_BASE		     0xFFFB4000
-#define UDC_OFFSET(offset)	     (UDC_BASE + (offset))
-#define UDC_REV			     UDC_OFFSET(0x0)	/* Revision */
-#define UDC_EP_NUM		     UDC_OFFSET(0x4)	/* Endpoint selection */
-#define UDC_DATA		     UDC_OFFSET(0x08)	/* Data */
-#define UDC_CTRL		     UDC_OFFSET(0x0C)	/* Control */
-#define UDC_STAT_FLG		     UDC_OFFSET(0x10)	/* Status flag */
-#define UDC_RXFSTAT		     UDC_OFFSET(0x14)	/* Receive FIFO status */
-#define UDC_SYSCON1		     UDC_OFFSET(0x18)	/* System configuration 1 */
-#define UDC_SYSCON2		     UDC_OFFSET(0x1C)	/* System configuration 2 */
-#define UDC_DEVSTAT		     UDC_OFFSET(0x20)	/* Device status */
-#define UDC_SOF			     UDC_OFFSET(0x24)	/* Start of frame */
-#define UDC_IRQ_EN		     UDC_OFFSET(0x28)	/* Interrupt enable */
-#define UDC_DMA_IRQ_EN		     UDC_OFFSET(0x2C)	/* DMA interrupt enable */
-#define UDC_IRQ_SRC		     UDC_OFFSET(0x30)	/* Interrupt source */
-#define UDC_EPN_STAT		     UDC_OFFSET(0x34)	/* Endpoint interrupt status */
-#define UDC_DMAN_STAT		     UDC_OFFSET(0x3C)	/* DMA endpoint interrupt status */
-
-/* IRQ_EN register fields */
-#define UDC_Sof_IE		     (1 << 7)	/* Start-of-frame interrupt enabled */
-#define UDC_EPn_RX_IE		     (1 << 5)	/* Receive endpoint interrupt enabled */
-#define UDC_EPn_TX_IE		     (1 << 4)	/* Transmit endpoint interrupt enabled */
-#define UDC_DS_Chg_IE		     (1 << 3)	/* Device state changed interrupt enabled */
-#define UDC_EP0_IE		     (1 << 0)	/* EP0 transaction interrupt enabled */
-
-/* IRQ_SRC register fields */
-#define UDC_TXn_Done		     (1 << 10)	/* Transmit DMA channel n done */
-#define UDC_RXn_Cnt		     (1 << 9)	/* Receive DMA channel n transactions count */
-#define UDC_RXn_EOT		     (1 << 8)	/* Receive DMA channel n end of transfer */
-#define UDC_SOF_Flg		     (1 << 7)	/* Start-of-frame interrupt flag */
-#define UDC_EPn_RX		     (1 << 5)	/* Endpoint n OUT transaction */
-#define UDC_EPn_TX		     (1 << 4)	/* Endpoint n IN transaction */
-#define UDC_DS_Chg		     (1 << 3)	/* Device state changed */
-#define UDC_Setup		     (1 << 2)	/* Setup transaction */
-#define UDC_EP0_RX		     (1 << 1)	/* EP0 OUT transaction */
-#define UDC_EP0_TX		     (1 << 0)	/* EP0 IN transaction */
-
-/* DEVSTAT register fields, 14.2.9 */
-#define UDC_R_WK_OK		     (1 << 6)	/* Remote wakeup granted */
-#define UDC_USB_Reset		     (1 << 5)	/* USB reset signalling is active */
-#define UDC_SUS			     (1 << 4)	/* Suspended state */
-#define UDC_CFG			     (1 << 3)	/* Configured state */
-#define UDC_ADD			     (1 << 2)	/* Addressed state */
-#define UDC_DEF			     (1 << 1)	/* Default state */
-#define UDC_ATT			     (1 << 0)	/* Attached state */
-
-/* SYSCON1 register fields */
-#define UDC_Cfg_Lock		     (1 << 8)	/* Device configuration locked */
-#define UDC_Nak_En		     (1 << 4)	/* NAK enable */
-#define UDC_Self_Pwr		     (1 << 2)	/* Device is self-powered */
-#define UDC_Soff_Dis		     (1 << 1)	/* Shutoff disabled */
-#define UDC_Pullup_En		     (1 << 0)	/* External pullup enabled */
-
-/* SYSCON2 register fields */
-#define UDC_Rmt_Wkp		     (1 << 6)	/* Remote wakeup */
-#define UDC_Stall_Cmd		     (1 << 5)	/* Stall endpoint */
-#define UDC_Dev_Cfg		     (1 << 3)	/* Device configured */
-#define UDC_Clr_Cfg		     (1 << 2)	/* Clear configured */
-
-/*
- * Select and enable endpoints
- */
-
-/* Table 13-1. USB Function Module Registers (endpoint configuration) */
-#define UDC_EPBASE		     UDC_OFFSET(0x80)	/* Endpoints base address */
-#define UDC_EP0			     UDC_EPBASE /* Control endpoint configuration */
-#define UDC_EP_RX_BASE		     UDC_OFFSET(0x84)	/* Receive endpoints base address */
-#define UDC_EP_RX(endpoint)	     (UDC_EP_RX_BASE + ((endpoint) - 1) * 4)
-#define UDC_EP_TX_BASE		     UDC_OFFSET(0xC4)	/* Transmit endpoints base address */
-#define UDC_EP_TX(endpoint)	     (UDC_EP_TX_BASE + ((endpoint) - 1) * 4)
-
-/* EP_NUM register fields */
-#define UDC_Setup_Sel		     (1 << 6)	/* Setup FIFO select */
-#define UDC_EP_Sel		     (1 << 5)	/* TX/RX FIFO select */
-#define UDC_EP_Dir		     (1 << 4)	/* Endpoint direction */
-
-/* CTRL register fields */
-#define UDC_Clr_Halt		     (1 << 7)	/* Clear halt endpoint */
-#define UDC_Set_Halt		     (1 << 6)	/* Set halt endpoint */
-#define UDC_Set_FIFO_En		     (1 << 2)	/* Set FIFO enable */
-#define UDC_Clr_EP		     (1 << 1)	/* Clear endpoint */
-#define UDC_Reset_EP		     (1 << 0)	/* Reset endpoint */
-
-/* STAT_FLG register fields */
-#define UDC_Miss_In		     (1 << 14)
-#define UDC_Data_Flush		     (1 << 13)
-#define UDC_ISO_Err		     (1 << 12)
-#define UDC_ISO_FIFO_Empty	     (1 << 9)
-#define UDC_ISO_FIFO_Full	     (1 << 8)
-#define UDC_EP_Halted		     (1 << 6)
-#define UDC_STALL		     (1 << 5)
-#define UDC_NAK			     (1 << 4)
-#define UDC_ACK			     (1 << 3)
-#define UDC_FIFO_En		     (1 << 2)
-#define UDC_Non_ISO_FIFO_Empty	     (1 << 1)
-#define UDC_Non_ISO_FIFO_Full	     (1 << 0)
-
-/* EPn_RX register fields */
-#define UDC_EPn_RX_Valid	     (1 << 15)	/* valid */
-#define UDC_EPn_RX_Db		     (1 << 14)	/* double-buffer */
-#define UDC_EPn_RX_Iso		     (1 << 11)	/* isochronous */
-
-/* EPn_TX register fields */
-#define UDC_EPn_TX_Valid	     (1 << 15)	/* valid */
-#define UDC_EPn_TX_Db		     (1 << 14)	/* double-buffer */
-#define UDC_EPn_TX_Iso		     (1 << 11)	/* isochronous */
-
-#define EP0_PACKETSIZE		     0x40
-
-/* physical to logical endpoint mapping
- * Physical endpoints are an index into device->bus->endpoint_array.
- * Logical endpoints are endpoints 0 to 15 IN and OUT as defined in
- * the USB specification.
- *
- *	physical ep	logical ep	direction	endpoint_address
- *	0		0		IN and OUT	0x00
- *	1 to 15		1 to 15		OUT		0x01 to 0x0f
- *	16 to 30	1 to 15		IN		0x81 to 0x8f
- */
-#define PHYS_EP_TO_EP_ADDR(ep) (((ep) < 16) ? (ep) : (((ep) - 15) | 0x80))
-#define EP_ADDR_TO_PHYS_EP(a) (((a) & 0x80) ? (((a) & ~0x80) + 15) : (a))
-
-/* MOD_CONF_CTRL_0 bits (FIXME: move to board hardware.h ?) */
-#define CONF_MOD_USB_W2FC_VBUS_MODE_R (1 << 17)
-
-/* Other registers (may be) related to USB */
-
-#define CLOCK_CTRL	    (0xFFFE0830)
-#define APLL_CTRL	    (0xFFFE084C)
-#define DPLL_CTRL	    (0xFFFE083C)
-#define SOFT_REQ	    (0xFFFE0834)
-#define STATUS_REQ	    (0xFFFE0840)
-
-/* FUNC_MUX_CTRL_0 bits related to USB */
-#define UDC_VBUS_CTRL	    (1 << 19)
-#define UDC_VBUS_MODE	    (1 << 18)
-
-/* OMAP Endpoint parameters */
-#define UDC_OUT_PACKET_SIZE	64
-#define UDC_IN_PACKET_SIZE	64
-#define UDC_INT_PACKET_SIZE	16
-#define UDC_BULK_PACKET_SIZE	16
-
-#define UDC_INT_ENDPOINT 5
-#define UDC_OUT_ENDPOINT 2
-#define UDC_IN_ENDPOINT	1
-
-#endif
diff --git a/lib/Kconfig b/lib/Kconfig
index 88e5da72ecc..8460439d8e7 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -8,4 +8,23 @@ config CC_OPTIMIZE_LIBS_FOR_SPEED
 
 	  If unsure, say N.
 
+config HAVE_PRIVATE_LIBGCC
+	bool
+
+config USE_PRIVATE_LIBGCC
+	bool "Use private libgcc"
+	depends on HAVE_PRIVATE_LIBGCC
+	help
+	  This option allows you to use the built-in libgcc implementation
+	  of U-boot instead of the one privided by the compiler.
+	  If unsure, say N.
+
+config SYS_HZ
+	int
+	default 1000
+	help
+	  The frequency of the timer returned by get_timer().
+	  get_timer() must operate in milliseconds and this option must be
+	  set to 1000.
+
 endmenu
diff --git a/lib/display_options.c b/lib/display_options.c
index 4c0c886d615..d5d17b2818e 100644
--- a/lib/display_options.c
+++ b/lib/display_options.c
@@ -7,6 +7,7 @@
 
 #include <config.h>
 #include <common.h>
+#include <inttypes.h>
 #include <version.h>
 #include <linux/ctype.h>
 #include <asm/io.h>
@@ -21,15 +22,10 @@ int display_options (void)
 	return 0;
 }
 
-/*
- * print sizes as "xxx KiB", "xxx.y KiB", "xxx MiB", "xxx.y MiB",
- * xxx GiB, xxx.y GiB, etc as needed; allow for optional trailing string
- * (like "\n")
- */
-void print_size(unsigned long long size, const char *s)
+void print_size(uint64_t size, const char *s)
 {
 	unsigned long m = 0, n;
-	unsigned long long f;
+	uint64_t f;
 	static const char names[] = {'E', 'P', 'T', 'G', 'M', 'K'};
 	unsigned long d = 10 * ARRAY_SIZE(names);
 	char c = 0;
@@ -43,7 +39,7 @@ void print_size(unsigned long long size, const char *s)
 	}
 
 	if (!c) {
-		printf("%llu Bytes%s", size, s);
+		printf("%" PRIu64 " Bytes%s", size, s);
 		return;
 	}
 
@@ -127,7 +123,7 @@ int print_buffer(ulong addr, const void *data, uint width, uint count,
 			else
 				x = lb.uc[i] = *(volatile uint8_t *)data;
 #ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
-			printf(" %0*llx", width * 2, x);
+			printf(" %0*" PRIx64, width * 2, x);
 #else
 			printf(" %0*x", width * 2, x);
 #endif
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 06d45420296..9714620ab3e 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -72,6 +72,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"),
 	COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
 	COMPAT(PARADE_PS8625, "parade,ps8625"),
+	COMPAT(COMPAT_INTEL_LPC, "intel,lpc"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
@@ -708,4 +709,75 @@ int fdtdec_read_fmap_entry(const void *blob, int node, const char *name,
 
 	return 0;
 }
+
+static u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells)
+{
+	u64 number = 0;
+
+	while (cells--)
+		number = (number << 32) | fdt32_to_cpu(*ptr++);
+
+	return number;
+}
+
+int fdt_get_resource(const void *fdt, int node, const char *property,
+		     unsigned int index, struct fdt_resource *res)
+{
+	const fdt32_t *ptr, *end;
+	int na, ns, len, parent;
+	unsigned int i = 0;
+
+	parent = fdt_parent_offset(fdt, node);
+	if (parent < 0)
+		return parent;
+
+	na = fdt_address_cells(fdt, parent);
+	ns = fdt_size_cells(fdt, parent);
+
+	ptr = fdt_getprop(fdt, node, property, &len);
+	if (!ptr)
+		return len;
+
+	end = ptr + len / sizeof(*ptr);
+
+	while (ptr + na + ns <= end) {
+		if (i == index) {
+			res->start = res->end = fdtdec_get_number(ptr, na);
+			res->end += fdtdec_get_number(&ptr[na], ns) - 1;
+			return 0;
+		}
+
+		ptr += na + ns;
+		i++;
+	}
+
+	return -FDT_ERR_NOTFOUND;
+}
+
+int fdt_get_named_resource(const void *fdt, int node, const char *property,
+			   const char *prop_names, const char *name,
+			   struct fdt_resource *res)
+{
+	int index;
+
+	index = fdt_find_string(fdt, node, prop_names, name);
+	if (index < 0)
+		return index;
+
+	return fdt_get_resource(fdt, node, property, index, res);
+}
+
+int fdtdec_pci_get_bdf(const void *fdt, int node, int *bdf)
+{
+	const fdt32_t *prop;
+	int len;
+
+	prop = fdt_getprop(fdt, node, "reg", &len);
+	if (!prop)
+		return len;
+
+	*bdf = fdt32_to_cpu(*prop) & 0xffffff;
+
+	return 0;
+}
 #endif
diff --git a/lib/initcall.c b/lib/initcall.c
index 7597bad5554..39f4b3f8ad5 100644
--- a/lib/initcall.c
+++ b/lib/initcall.c
@@ -15,14 +15,16 @@ int initcall_run_list(const init_fnc_t init_sequence[])
 
 	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
 		unsigned long reloc_ofs = 0;
+		int ret;
 
 		if (gd->flags & GD_FLG_RELOC)
 			reloc_ofs = gd->reloc_off;
 		debug("initcall: %p\n", (char *)*init_fnc_ptr - reloc_ofs);
-		if ((*init_fnc_ptr)()) {
-			printf("initcall sequence %p failed at call %p\n",
+		ret = (*init_fnc_ptr)();
+		if (ret) {
+			printf("initcall sequence %p failed at call %p (err=%d)\n",
 			       init_sequence,
-			       (char *)*init_fnc_ptr - reloc_ofs);
+			       (char *)*init_fnc_ptr - reloc_ofs, ret);
 			return -1;
 		}
 	}
diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c
index 36af0435254..03733e574f7 100644
--- a/lib/libfdt/fdt_ro.c
+++ b/lib/libfdt/fdt_ro.c
@@ -491,6 +491,82 @@ int fdt_stringlist_contains(const char *strlist, int listlen, const char *str)
 	return 0;
 }
 
+int fdt_count_strings(const void *fdt, int node, const char *property)
+{
+	int length, i, count = 0;
+	const char *list;
+
+	list = fdt_getprop(fdt, node, property, &length);
+	if (!list)
+		return -length;
+
+	for (i = 0; i < length; i++) {
+		int len = strlen(list);
+
+		list += len + 1;
+		i += len;
+		count++;
+	}
+
+	return count;
+}
+
+int fdt_find_string(const void *fdt, int node, const char *property,
+		    const char *string)
+{
+	const char *list, *end;
+	int len, index = 0;
+
+	list = fdt_getprop(fdt, node, property, &len);
+	if (!list)
+		return len;
+
+	end = list + len;
+	len = strlen(string);
+
+	while (list < end) {
+		int l = strlen(list);
+
+		if (l == len && memcmp(list, string, len) == 0)
+			return index;
+
+		list += l + 1;
+		index++;
+	}
+
+	return -FDT_ERR_NOTFOUND;
+}
+
+int fdt_get_string_index(const void *fdt, int node, const char *property,
+			 int index, const char **output)
+{
+	const char *list;
+	int length, i;
+
+	list = fdt_getprop(fdt, node, property, &length);
+
+	for (i = 0; i < length; i++) {
+		int len = strlen(list);
+
+		if (index == 0) {
+			*output = list;
+			return 0;
+		}
+
+		list += len + 1;
+		i += len;
+		index--;
+	}
+
+	return FDT_ERR_NOTFOUND;
+}
+
+int fdt_get_string(const void *fdt, int node, const char *property,
+		   const char **output)
+{
+	return fdt_get_string_index(fdt, node, property, 0, output);
+}
+
 int fdt_node_check_compatible(const void *fdt, int nodeoffset,
 			      const char *compatible)
 {
diff --git a/lib/lmb.c b/lib/lmb.c
index 41a2be46356..031f0e1ac89 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -236,7 +236,7 @@ long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size)
 	return lmb_add_region(_rgn, base, size);
 }
 
-long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base,
+static long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base,
 				phys_size_t size)
 {
 	unsigned long i;
diff --git a/lib/time.c b/lib/time.c
index c7b026498be..477440de16f 100644
--- a/lib/time.c
+++ b/lib/time.c
@@ -10,10 +10,6 @@
 #include <div64.h>
 #include <asm/io.h>
 
-#if CONFIG_SYS_HZ != 1000
-#warning "CONFIG_SYS_HZ must be 1000 and should not be defined by platforms"
-#endif
-
 #ifndef CONFIG_WD_PERIOD
 # define CONFIG_WD_PERIOD	(10 * 1000 * 1000)	/* 10 seconds default */
 #endif
@@ -41,7 +37,7 @@ unsigned long notrace timer_read_counter(void)
 extern unsigned long __weak timer_read_counter(void);
 #endif
 
-unsigned long long __weak notrace get_ticks(void)
+uint64_t __weak notrace get_ticks(void)
 {
 	unsigned long now = timer_read_counter();
 
@@ -49,11 +45,11 @@ unsigned long long __weak notrace get_ticks(void)
 	if (now < gd->timebase_l)
 		gd->timebase_h++;
 	gd->timebase_l = now;
-	return ((unsigned long long)gd->timebase_h << 32) | gd->timebase_l;
+	return ((uint64_t)gd->timebase_h << 32) | gd->timebase_l;
 }
 
 /* Returns time in milliseconds */
-static unsigned long long notrace tick_to_time(unsigned long long tick)
+static uint64_t notrace tick_to_time(uint64_t tick)
 {
 	ulong div = get_tbclk();
 
@@ -78,9 +74,9 @@ unsigned long __weak notrace timer_get_us(void)
 	return tick_to_time(get_ticks() * 1000);
 }
 
-static unsigned long long usec_to_tick(unsigned long usec)
+static uint64_t usec_to_tick(unsigned long usec)
 {
-	unsigned long long tick = usec;
+	uint64_t tick = usec;
 	tick *= get_tbclk();
 	do_div(tick, 1000000);
 	return tick;
@@ -88,7 +84,7 @@ static unsigned long long usec_to_tick(unsigned long usec)
 
 void __weak __udelay(unsigned long usec)
 {
-	unsigned long long tmp;
+	uint64_t tmp;
 
 	tmp = get_ticks() + usec_to_tick(usec);	/* get current timestamp */
 
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index 7ec758e40fc..b585713b7c5 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -270,7 +270,7 @@ static char *put_dec_full(char *buf, unsigned q)
 	return buf;
 }
 /* No inlining helps gcc to use registers better */
-static noinline char *put_dec(char *buf, u64 num)
+static noinline char *put_dec(char *buf, uint64_t num)
 {
 	while (1) {
 		unsigned rem;
diff --git a/net/eth.c b/net/eth.c
index 76ffa05608a..eac4f7b3d0e 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -153,7 +153,7 @@ static void eth_current_changed(void)
 		setenv("ethact", NULL);
 }
 
-int eth_address_set(unsigned char *addr)
+static int eth_address_set(unsigned char *addr)
 {
 	return memcmp(addr, "\0\0\0\0\0\0", 6);
 }
diff --git a/net/tftp.c b/net/tftp.c
index 966d1cfba36..0a2c53302ca 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -299,6 +299,8 @@ static void tftp_complete(void)
 		putc('#');
 		TftpNumchars++;
 	}
+	puts("  ");
+	print_size(TftpTsize, "");
 #endif
 	time_start = get_timer(time_start);
 	if (time_start > 0) {
diff --git a/post/post.c b/post/post.c
index 4af5355fa5a..4194edb89e8 100644
--- a/post/post.c
+++ b/post/post.c
@@ -52,7 +52,7 @@ int post_init_f(void)
  * Boards with hotkey support can override this weak default function
  * by defining one in their board specific code.
  */
-int __post_hotkeys_pressed(void)
+__weak int post_hotkeys_pressed(void)
 {
 #ifdef CONFIG_SYS_POST_HOTKEYS_GPIO
 	int ret;
@@ -73,9 +73,6 @@ int __post_hotkeys_pressed(void)
 
 	return 0;	/* No hotkeys supported */
 }
-int post_hotkeys_pressed(void)
-	__attribute__((weak, alias("__post_hotkeys_pressed")));
-
 
 void post_bootmode_init(void)
 {
@@ -236,11 +233,9 @@ static void post_get_flags(int *test_flags)
 			test_flags[j] |= POST_SLOWTEST;
 }
 
-void __show_post_progress(unsigned int test_num, int before, int result)
+__weak void show_post_progress(unsigned int test_num, int before, int result)
 {
 }
-void show_post_progress(unsigned int, int, int)
-			__attribute__((weak, alias("__show_post_progress")));
 
 static int post_run_single(struct post_test *test,
 				int test_flags, int flags, unsigned int i)
diff --git a/scripts/Makefile.extrawarn b/scripts/Makefile.extrawarn
index 65643506c71..0ec0d24b1c7 100644
--- a/scripts/Makefile.extrawarn
+++ b/scripts/Makefile.extrawarn
@@ -26,16 +26,6 @@ warning-1 += $(call cc-option, -Wmissing-include-dirs)
 warning-1 += $(call cc-option, -Wunused-but-set-variable)
 warning-1 += $(call cc-disable-warning, missing-field-initializers)
 
-# Clang
-warning-1 += $(call cc-disable-warning, initializer-overrides)
-warning-1 += $(call cc-disable-warning, unused-value)
-warning-1 += $(call cc-disable-warning, format)
-warning-1 += $(call cc-disable-warning, unknown-warning-option)
-warning-1 += $(call cc-disable-warning, sign-compare)
-warning-1 += $(call cc-disable-warning, format-zero-length)
-warning-1 += $(call cc-disable-warning, uninitialized)
-warning-1 += $(call cc-option, -fcatch-undefined-behavior)
-
 warning-2 := -Waggregate-return
 warning-2 += -Wcast-align
 warning-2 += -Wdisabled-optimization
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 88c01d18ecf..7afe437e62e 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -216,13 +216,13 @@ $(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin
 endif
 
 quiet_cmd_u-boot-spl = LD      $@
-      cmd_u-boot-spl = cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
+      cmd_u-boot-spl = (cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
 		       $(patsubst $(obj)/%,%,$(u-boot-spl-init)) --start-group \
 		       $(patsubst $(obj)/%,%,$(u-boot-spl-main)) --end-group \
-		       $(PLATFORM_LIBS) -Map $(SPL_BIN).map -o $(SPL_BIN)
+		       $(PLATFORM_LIBS) -Map $(SPL_BIN).map -o $(SPL_BIN))
 
-$(obj)/$(SPL_BIN): $(u-boot-spl-init) $(u-boot-spl-main) $(obj)/u-boot-spl.lds
-	$(call cmd,u-boot-spl)
+$(obj)/$(SPL_BIN): $(u-boot-spl-init) $(u-boot-spl-main) $(obj)/u-boot-spl.lds FORCE
+	$(call if_changed,u-boot-spl)
 
 $(sort $(u-boot-spl-init) $(u-boot-spl-main)): $(u-boot-spl-dirs) ;
 
diff --git a/scripts/kconfig/merge_config.sh b/scripts/kconfig/merge_config.sh
index 81b0c61bb9e..efa47334619 100755
--- a/scripts/kconfig/merge_config.sh
+++ b/scripts/kconfig/merge_config.sh
@@ -87,7 +87,7 @@ TMP_FILE=$(mktemp ./.tmp.config.XXXXXXXXXX)
 echo "Using $INITFILE as base"
 cat $INITFILE > $TMP_FILE
 
-# Merge files, printing warnings on overrided values
+# Merge files, printing warnings on overridden values
 for MERGE_FILE in $MERGE_LIST ; do
 	echo "Merging $MERGE_FILE"
 	CFG_LIST=$(sed -n "$SED_CONFIG_EXP" $MERGE_FILE)
diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh
index 3a963c7973d..70f3a5df6f7 100644
--- a/scripts/multiconfig.sh
+++ b/scripts/multiconfig.sh
@@ -162,6 +162,16 @@ do_defconfig () {
 	fi
 }
 
+do_board_felconfig () {
+    do_board_defconfig ${1%%_felconfig}_defconfig
+    if ! grep -q CONFIG_ARCH_SUNXI=y .config || ! grep -q CONFIG_SPL=y .config ; then
+	echo "$progname: Cannot felconfig a non-sunxi or non-SPL platform" >&2
+	exit 1
+    fi
+    sed -i -e 's/\# CONFIG_SPL_FEL is not set/CONFIG_SPL_FEL=y/g' \
+	.config spl/.config
+}
+
 do_savedefconfig () {
 	if [ -r "$KCONFIG_CONFIG" ]; then
 		subimages=$(get_enabled_subimages)
@@ -297,9 +307,24 @@ do_others () {
 	else
 		objdir=${1%/*}
 		check_enabled_subimage $1 $objdir
+
+		if [ -f "$objdir/$KCONFIG_CONFIG" ]; then
+			timestamp_before=$(stat --printf="%Y" \
+						$objdir/$KCONFIG_CONFIG)
+		fi
 	fi
 
 	run_make_config $target $objdir
+
+	if [ "$timestamp_before" -a -f "$objdir/$KCONFIG_CONFIG" ]; then
+		timestamp_after=$(stat --printf="%Y" $objdir/$KCONFIG_CONFIG)
+
+		if [ "$timestamp_after" -gt "$timestamp_before" ]; then
+			# $objdir/.config has been updated.
+			# touch .config to invoke "make silentoldconfig"
+			touch $KCONFIG_CONFIG
+		fi
+	fi
 }
 
 progname=$(basename $0)
@@ -308,6 +333,8 @@ target=$1
 case $target in
 *_defconfig)
 	do_board_defconfig $target;;
+*_felconfig)
+	do_board_felconfig $target;;
 *_config)
 	# backward compatibility
 	do_board_defconfig ${target%_config}_defconfig;;
diff --git a/test/command_ut.c b/test/command_ut.c
index ae6466d0ed8..e136075541b 100644
--- a/test/command_ut.c
+++ b/test/command_ut.c
@@ -66,7 +66,21 @@ static int do_ut_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	assert(run_command_list("false", -1, 0) == 1);
 	assert(run_command_list("echo", -1, 0) == 0);
 
+	run_command("setenv foo 'setenv monty 1; setenv python 2'", 0);
+	run_command("run foo", 0);
+	assert(getenv("monty") != NULL);
+	assert(!strcmp("1", getenv("monty")));
+	assert(getenv("python") != NULL);
+	assert(!strcmp("2", getenv("python")));
+
 #ifdef CONFIG_SYS_HUSH_PARSER
+	run_command("setenv foo 'setenv black 1\nsetenv adder 2'", 0);
+	run_command("run foo", 0);
+	assert(getenv("black") != NULL);
+	assert(!strcmp("1", getenv("black")));
+	assert(getenv("adder") != NULL);
+	assert(!strcmp("2", getenv("adder")));
+
 	/* Test the 'test' command */
 
 #define HUSH_TEST(name, expr, expected_result) \
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 5c2415e3d2a..75d3d41536b 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -18,4 +18,6 @@ obj-$(CONFIG_DM_TEST) += core.o
 obj-$(CONFIG_DM_TEST) += ut.o
 ifneq ($(CONFIG_SANDBOX),)
 obj-$(CONFIG_DM_GPIO) += gpio.o
+obj-$(CONFIG_DM_SPI) += spi.o
+obj-$(CONFIG_DM_SPI_FLASH) += sf.o
 endif
diff --git a/test/dm/bus.c b/test/dm/bus.c
index 873d64e42a4..abbaccff509 100644
--- a/test/dm/bus.c
+++ b/test/dm/bus.c
@@ -140,6 +140,37 @@ static int dm_test_bus_children_funcs(struct dm_test_state *dms)
 }
 DM_TEST(dm_test_bus_children_funcs, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
 
+/* Test that we can iterate through children */
+static int dm_test_bus_children_iterators(struct dm_test_state *dms)
+{
+	struct udevice *bus, *dev, *child;
+
+	/* Walk through the children one by one */
+	ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus));
+	ut_assertok(device_find_first_child(bus, &dev));
+	ut_asserteq_str("c-test@5", dev->name);
+	ut_assertok(device_find_next_child(&dev));
+	ut_asserteq_str("c-test@0", dev->name);
+	ut_assertok(device_find_next_child(&dev));
+	ut_asserteq_str("c-test@1", dev->name);
+	ut_assertok(device_find_next_child(&dev));
+	ut_asserteq_ptr(dev, NULL);
+
+	/* Move to the next child without using device_find_first_child() */
+	ut_assertok(device_find_child_by_seq(bus, 5, true, &dev));
+	ut_asserteq_str("c-test@5", dev->name);
+	ut_assertok(device_find_next_child(&dev));
+	ut_asserteq_str("c-test@0", dev->name);
+
+	/* Try a device with no children */
+	ut_assertok(device_find_first_child(dev, &child));
+	ut_asserteq_ptr(child, NULL);
+
+	return 0;
+}
+DM_TEST(dm_test_bus_children_iterators,
+	DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
 /* Test that the bus can store data about each child */
 static int dm_test_bus_parent_data(struct dm_test_state *dms)
 {
diff --git a/test/dm/core.c b/test/dm/core.c
index b0cfb42c85f..ff5c2a749c5 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -67,6 +67,34 @@ static struct driver_info driver_info_pre_reloc = {
 	.platdata = &test_pdata_manual,
 };
 
+void dm_leak_check_start(struct dm_test_state *dms)
+{
+	dms->start = mallinfo();
+	if (!dms->start.uordblks)
+		puts("Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c\n");
+}
+
+int dm_leak_check_end(struct dm_test_state *dms)
+{
+	struct mallinfo end;
+	int id;
+
+	/* Don't delete the root class, since we started with that */
+	for (id = UCLASS_ROOT + 1; id < UCLASS_COUNT; id++) {
+		struct uclass *uc;
+
+		uc = uclass_find(id);
+		if (!uc)
+			continue;
+		ut_assertok(uclass_destroy(uc));
+	}
+
+	end = mallinfo();
+	ut_asserteq(dms->start.uordblks, end.uordblks);
+
+	return 0;
+}
+
 /* Test that binding with platdata occurs correctly */
 static int dm_test_autobind(struct dm_test_state *dms)
 {
@@ -377,14 +405,11 @@ static int dm_test_leak(struct dm_test_state *dms)
 	int i;
 
 	for (i = 0; i < 2; i++) {
-		struct mallinfo start, end;
 		struct udevice *dev;
 		int ret;
 		int id;
 
-		start = mallinfo();
-		if (!start.uordblks)
-			puts("Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c\n");
+		dm_leak_check_start(dms);
 
 		ut_assertok(dm_scan_platdata(false));
 		ut_assertok(dm_scan_fdt(gd->fdt_blob, false));
@@ -398,18 +423,7 @@ static int dm_test_leak(struct dm_test_state *dms)
 			ut_assertok(ret);
 		}
 
-		/* Don't delete the root class, since we started with that */
-		for (id = UCLASS_ROOT + 1; id < UCLASS_COUNT; id++) {
-			struct uclass *uc;
-
-			uc = uclass_find(id);
-			if (!uc)
-				continue;
-			ut_assertok(uclass_destroy(uc));
-		}
-
-		end = mallinfo();
-		ut_asserteq(start.uordblks, end.uordblks);
+		ut_assertok(dm_leak_check_end(dms));
 	}
 
 	return 0;
diff --git a/test/dm/gpio.c b/test/dm/gpio.c
index 2b2b0b51fa7..94bd0d99dc0 100644
--- a/test/dm/gpio.c
+++ b/test/dm/gpio.c
@@ -7,11 +7,14 @@
 #include <common.h>
 #include <fdtdec.h>
 #include <dm.h>
+#include <dm/root.h>
 #include <dm/ut.h>
 #include <dm/test.h>
 #include <dm/util.h>
 #include <asm/gpio.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Test that sandbox GPIOs work correctly */
 static int dm_test_gpio(struct dm_test_state *dms)
 {
@@ -39,52 +42,51 @@ static int dm_test_gpio(struct dm_test_state *dms)
 
 	/* Get the operations for this device */
 	ops = gpio_get_ops(dev);
-	ut_assert(ops->get_state);
+	ut_assert(ops->get_function);
 
 	/* Cannot get a value until it is reserved */
-	ut_asserteq(-1, ops->get_value(dev, offset));
-
+	ut_asserteq(-EBUSY, gpio_get_value(gpio + 1));
 	/*
 	 * Now some tests that use the 'sandbox' back door. All GPIOs
 	 * should default to input, include b4 that we are using here.
 	 */
-	ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
-	ut_asserteq_str("b4:  in: 0 [ ]", buf);
+	ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b4: input: 0 [ ]", buf);
 
 	/* Change it to an output */
 	sandbox_gpio_set_direction(dev, offset, 1);
-	ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
-	ut_asserteq_str("b4: out: 0 [ ]", buf);
+	ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b4: output: 0 [ ]", buf);
 
 	sandbox_gpio_set_value(dev, offset, 1);
-	ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
-	ut_asserteq_str("b4: out: 1 [ ]", buf);
+	ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b4: output: 1 [ ]", buf);
 
-	ut_assertok(ops->request(dev, offset, "testing"));
-	ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
-	ut_asserteq_str("b4: out: 1 [x] testing", buf);
+	ut_assertok(gpio_request(gpio, "testing"));
+	ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b4: output: 1 [x] testing", buf);
 
 	/* Change the value a bit */
 	ut_asserteq(1, ops->get_value(dev, offset));
 	ut_assertok(ops->set_value(dev, offset, 0));
 	ut_asserteq(0, ops->get_value(dev, offset));
-	ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
-	ut_asserteq_str("b4: out: 0 [x] testing", buf);
+	ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b4: output: 0 [x] testing", buf);
 	ut_assertok(ops->set_value(dev, offset, 1));
 	ut_asserteq(1, ops->get_value(dev, offset));
 
 	/* Make it an input */
 	ut_assertok(ops->direction_input(dev, offset));
-	ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
-	ut_asserteq_str("b4:  in: 1 [x] testing", buf);
+	ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b4: input: 1 [x] testing", buf);
 	sandbox_gpio_set_value(dev, offset, 0);
 	ut_asserteq(0, sandbox_gpio_get_value(dev, offset));
-	ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
-	ut_asserteq_str("b4:  in: 0 [x] testing", buf);
+	ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b4: input: 0 [x] testing", buf);
 
-	ut_assertok(ops->free(dev, offset));
-	ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
-	ut_asserteq_str("b4:  in: 0 [ ]", buf);
+	ut_assertok(gpio_free(gpio));
+	ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b4: input: 0 [ ]", buf);
 
 	/* Check the 'a' bank also */
 	ut_assertok(gpio_lookup_name("a15", &dev, &offset, &gpio));
@@ -96,6 +98,18 @@ static int dm_test_gpio(struct dm_test_state *dms)
 	ut_asserteq_str("a", name);
 	ut_asserteq(20, offset_count);
 
+	return 0;
+}
+DM_TEST(dm_test_gpio, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that sandbox anonymous GPIOs work correctly */
+static int dm_test_gpio_anon(struct dm_test_state *dms)
+{
+	unsigned int offset, gpio;
+	struct udevice *dev;
+	const char *name;
+	int offset_count;
+
 	/* And the anonymous bank */
 	ut_assertok(gpio_lookup_name("14", &dev, &offset, &gpio));
 	ut_asserteq_str(dev->name, "gpio_sandbox");
@@ -108,4 +122,57 @@ static int dm_test_gpio(struct dm_test_state *dms)
 
 	return 0;
 }
-DM_TEST(dm_test_gpio, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_anon, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that gpio_requestf() works as expected */
+static int dm_test_gpio_requestf(struct dm_test_state *dms)
+{
+	unsigned int offset, gpio;
+	struct udevice *dev;
+	char buf[80];
+
+	ut_assertok(gpio_lookup_name("b5", &dev, &offset, &gpio));
+	ut_assertok(gpio_requestf(gpio, "testing %d %s", 1, "hi"));
+	sandbox_gpio_set_direction(dev, offset, 1);
+	sandbox_gpio_set_value(dev, offset, 1);
+	ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b5: output: 1 [x] testing 1 hi", buf);
+
+	return 0;
+}
+DM_TEST(dm_test_gpio_requestf, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that gpio_request() copies its string */
+static int dm_test_gpio_copy(struct dm_test_state *dms)
+{
+	unsigned int offset, gpio;
+	struct udevice *dev;
+	char buf[80], name[10];
+
+	ut_assertok(gpio_lookup_name("b6", &dev, &offset, &gpio));
+	strcpy(name, "odd_name");
+	ut_assertok(gpio_request(gpio, name));
+	sandbox_gpio_set_direction(dev, offset, 1);
+	sandbox_gpio_set_value(dev, offset, 1);
+	ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b6: output: 1 [x] odd_name", buf);
+	strcpy(name, "nothing");
+	ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b6: output: 1 [x] odd_name", buf);
+
+	return 0;
+}
+DM_TEST(dm_test_gpio_copy, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that we don't leak memory with GPIOs */
+static int dm_test_gpio_leak(struct dm_test_state *dms)
+{
+	ut_assertok(dm_test_gpio(dms));
+	ut_assertok(dm_test_gpio_anon(dms));
+	ut_assertok(dm_test_gpio_requestf(dms));
+	ut_assertok(dm_leak_check_end(dms));
+
+	return 0;
+}
+
+DM_TEST(dm_test_gpio_leak, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/sf.c b/test/dm/sf.c
new file mode 100644
index 00000000000..57dd1345c43
--- /dev/null
+++ b/test/dm/sf.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <asm/state.h>
+#include <dm/ut.h>
+#include <dm/test.h>
+#include <dm/util.h>
+
+/* Test that sandbox SPI flash works correctly */
+static int dm_test_spi_flash(struct dm_test_state *dms)
+{
+	/*
+	 * Create an empty test file and run the SPI flash tests. This is a
+	 * long way from being a unit test, but it does test SPI device and
+	 * emulator binding, probing, the SPI flash emulator including
+	 * device tree decoding, plus the file-based backing store of SPI.
+	 *
+	 * More targeted tests could be created to perform the above steps
+	 * one at a time. This might not increase test coverage much, but
+	 * it would make bugs easier to find. It's not clear whether the
+	 * benefit is worth the extra complexity.
+	 */
+	ut_asserteq(0, run_command_list(
+		"sb save hostfs - spi.bin 0 200000;"
+		"sf probe;"
+		"sf test 0 10000", -1,  0));
+	/*
+	 * Since we are about to destroy all devices, we must tell sandbox
+	 * to forget the emulation device
+	 */
+	sandbox_sf_unbind_emul(state_get_current(), 0, 0);
+
+	return 0;
+}
+DM_TEST(dm_test_spi_flash, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/spi.c b/test/dm/spi.c
new file mode 100644
index 00000000000..61b5b2548c4
--- /dev/null
+++ b/test/dm/spi.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <dm/device-internal.h>
+#include <dm/test.h>
+#include <dm/uclass-internal.h>
+#include <dm/ut.h>
+#include <dm/util.h>
+#include <asm/state.h>
+
+/* Test that we can find buses and chip-selects */
+static int dm_test_spi_find(struct dm_test_state *dms)
+{
+	struct sandbox_state *state = state_get_current();
+	struct spi_slave *slave;
+	struct udevice *bus, *dev;
+	const int busnum = 0, cs = 0, mode = 0, speed = 1000000, cs_b = 1;
+	struct spi_cs_info info;
+	int of_offset;
+
+	ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_SPI, busnum,
+						       false, &bus));
+
+	/*
+	 * spi_post_bind() will bind devices to chip selects. Check this then
+	 * remove the emulation and the slave device.
+	 */
+	ut_asserteq(0, uclass_get_device_by_seq(UCLASS_SPI, busnum, &bus));
+	ut_assertok(spi_cs_info(bus, cs, &info));
+	of_offset = info.dev->of_offset;
+	sandbox_sf_unbind_emul(state_get_current(), busnum, cs);
+	device_remove(info.dev);
+	device_unbind(info.dev);
+
+	/*
+	 * Even though the device is gone, the sandbox SPI drivers always
+	 * reports that CS 0 is present
+	 */
+	ut_assertok(spi_cs_info(bus, cs, &info));
+	ut_asserteq_ptr(info.dev, NULL);
+
+	/* This finds nothing because we removed the device */
+	ut_asserteq(-ENODEV, spi_find_bus_and_cs(busnum, cs, &bus, &dev));
+	ut_asserteq(-ENODEV, spi_get_bus_and_cs(busnum, cs, speed, mode,
+						NULL, 0, &bus, &slave));
+
+	/*
+	 * This forces the device to be re-added, but there is no emulation
+	 * connected so the probe will fail. We require that bus is left
+	 * alone on failure, and that the spi_get_bus_and_cs() does not add
+	 * a 'partially-inited' device.
+	 */
+	ut_asserteq(-ENODEV, spi_find_bus_and_cs(busnum, cs, &bus, &dev));
+	ut_asserteq(-ENOENT, spi_get_bus_and_cs(busnum, cs, speed, mode,
+						"spi_flash_std", "name", &bus,
+						&slave));
+	ut_assertok(spi_cs_info(bus, cs, &info));
+	ut_asserteq_ptr(info.dev, NULL);
+
+	/* Add the emulation and try again */
+	ut_assertok(sandbox_sf_bind_emul(state, busnum, cs, bus, of_offset,
+					 "name"));
+	ut_assertok(spi_find_bus_and_cs(busnum, cs, &bus, &dev));
+	ut_assertok(spi_get_bus_and_cs(busnum, cs, speed, mode,
+				       "spi_flash_std", "name", &bus, &slave));
+
+	ut_assertok(spi_cs_info(bus, cs, &info));
+	ut_asserteq_ptr(info.dev, slave->dev);
+
+	/* We should be able to add something to another chip select */
+	ut_assertok(sandbox_sf_bind_emul(state, busnum, cs_b, bus, of_offset,
+					 "name"));
+	ut_assertok(spi_get_bus_and_cs(busnum, cs_b, speed, mode,
+				       "spi_flash_std", "name", &bus, &slave));
+	ut_assertok(spi_cs_info(bus, cs_b, &info));
+	ut_asserteq_ptr(info.dev, slave->dev);
+
+	/*
+	 * Since we are about to destroy all devices, we must tell sandbox
+	 * to forget the emulation device
+	 */
+	sandbox_sf_unbind_emul(state_get_current(), busnum, cs);
+	sandbox_sf_unbind_emul(state_get_current(), busnum, cs_b);
+
+	return 0;
+}
+DM_TEST(dm_test_spi_find, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that sandbox SPI works correctly */
+static int dm_test_spi_xfer(struct dm_test_state *dms)
+{
+	struct spi_slave *slave;
+	struct udevice *bus;
+	const int busnum = 0, cs = 0, mode = 0;
+	const char dout[5] = {0x9f};
+	unsigned char din[5];
+
+	ut_assertok(spi_get_bus_and_cs(busnum, cs, 1000000, mode, NULL, 0,
+				       &bus, &slave));
+	ut_assertok(spi_claim_bus(slave));
+	ut_assertok(spi_xfer(slave, 40, dout, din,
+			     SPI_XFER_BEGIN | SPI_XFER_END));
+	ut_asserteq(0xff, din[0]);
+	ut_asserteq(0x20, din[1]);
+	ut_asserteq(0x20, din[2]);
+	ut_asserteq(0x15, din[3]);
+	spi_release_bus(slave);
+
+	/*
+	 * Since we are about to destroy all devices, we must tell sandbox
+	 * to forget the emulation device
+	 */
+#ifdef CONFIG_DM_SPI_FLASH
+	sandbox_sf_unbind_emul(state_get_current(), busnum, cs);
+#endif
+
+	return 0;
+}
+DM_TEST(dm_test_spi_xfer, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/test-dm.sh b/test/dm/test-dm.sh
index ef5aca5ac3c..bb99677ece9 100755
--- a/test/dm/test-dm.sh
+++ b/test/dm/test-dm.sh
@@ -4,4 +4,6 @@ NUM_CPUS=$(cat /proc/cpuinfo |grep -c processor)
 dtc -I dts -O dtb test/dm/test.dts -o test/dm/test.dtb
 make O=sandbox sandbox_config
 make O=sandbox -s -j${NUM_CPUS}
+dd if=/dev/zero of=spi.bin bs=1M count=2
 ./sandbox/u-boot -d test/dm/test.dtb -c "dm test"
+rm spi.bin
diff --git a/test/dm/test-main.c b/test/dm/test-main.c
index 94ce72abfd5..90ca81092f7 100644
--- a/test/dm/test-main.c
+++ b/test/dm/test-main.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
+#include <malloc.h>
 #include <dm/test.h>
 #include <dm/root.h>
 #include <dm/uclass-internal.h>
@@ -88,6 +89,7 @@ int dm_test_main(void)
 		printf("Test: %s\n", test->name);
 		ut_assertok(dm_test_init(dms));
 
+		dms->start = mallinfo();
 		if (test->flags & DM_TESTF_SCAN_PDATA)
 			ut_assertok(dm_scan_platdata(false));
 		if (test->flags & DM_TESTF_PROBE_TEST)
diff --git a/test/dm/test.dts b/test/dm/test.dts
index 84895951550..1fba7925642 100644
--- a/test/dm/test.dts
+++ b/test/dm/test.dts
@@ -81,7 +81,7 @@
 		compatible = "google,another-fdt-test";
 	};
 
-	base-gpios {
+	gpio_a: base-gpios {
 		compatible = "sandbox,gpio";
 		gpio-bank-name = "a";
 		num-gpios = <20>;
@@ -92,4 +92,19 @@
 		gpio-bank-name = "b";
 		num-gpios = <10>;
 	};
+
+	spi@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+		compatible = "sandbox,spi";
+		cs-gpios = <0>, <&gpio_a 0>;
+		spi.bin@0 {
+			reg = <0>;
+			compatible = "spansion,m25p16", "spi-flash";
+			spi-max-frequency = <40000000>;
+			sandbox,filename = "spi.bin";
+		};
+	};
+
 };
diff --git a/test/stdint/int-types.c b/test/stdint/int-types.c
new file mode 100644
index 00000000000..2660084d946
--- /dev/null
+++ b/test/stdint/int-types.c
@@ -0,0 +1,13 @@
+#include <common.h>
+#include <inttypes.h>
+
+int test_types(void)
+{
+	uintptr_t uintptr = 0;
+	uint64_t uint64 = 0;
+	u64 u64_val = 0;
+
+	printf("uintptr = %" PRIuPTR "\n", uintptr);
+	printf("uint64 = %" PRIu64 "\n", uint64);
+	printf("u64 = %" PRIu64 "\n", u64_val);
+}
diff --git a/test/stdint/test-includes.sh b/test/stdint/test-includes.sh
new file mode 100755
index 00000000000..077bdc73a13
--- /dev/null
+++ b/test/stdint/test-includes.sh
@@ -0,0 +1,58 @@
+#!/bin/bash
+
+# Test script to check uintptr_t and 64-bit types for warnings
+#
+# It builds a few boards with different toolchains. If there are no warnings
+# then all is well.
+#
+# Usage:
+#
+# Make sure that your toolchains are correct at the bottom of this file
+#
+# Then:
+#	./test/stdint/test-includes.sh
+
+out=/tmp/test-includes.tmp
+
+try_test() {
+	local board=$1
+	local arch=$2
+	local soc=$3
+	local gcc=$4
+	local flags="$5"
+
+	echo $@
+	if ! which ${gcc} >/dev/null 2>&1; then
+		echo "Not found: ${gcc}"
+		return
+	fi
+
+	rm -rf ${out}
+	mkdir -p ${out}
+	touch ${out}/config.h
+	mkdir -p ${out}/generated
+	touch ${out}/generated/generic-asm-offsets.h
+	mkdir -p ${out}/include/asm
+	ln -s $(pwd)/arch/${arch}/include/asm/arch-${soc} \
+			${out}/include/asm/arch
+
+	cmd="${gcc} -c -D__KERNEL__ ${flags} \
+		-fno-builtin -ffreestanding \
+		-Iarch/${arch}/include \
+		-Iinclude \
+		-I${out} -I${out}/include \
+		-include configs/${board}.h test/stdint/int-types.c \
+		-o /dev/null"
+	$cmd
+}
+
+# Run a test with and without CONFIG_USE_STDINT
+try_both() {
+	try_test $@
+	try_test $@ -DCONFIG_USE_STDINT
+}
+
+# board arch soc path-to-gcc
+try_both sandbox sandbox - gcc
+try_both coreboot x86 - x86_64-linux-gnu-gcc
+try_both seaboard arm tegra20 /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.08_linux/bin/arm-linux-gnueabihf-gcc
diff --git a/tools/.gitignore b/tools/.gitignore
index cefe9235e2f..e7f0f8ff728 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -1,3 +1,4 @@
+/atmel_pmecc_params
 /bmp_logo
 /envcrc
 /fit_check_sign
diff --git a/tools/Makefile b/tools/Makefile
index 2b05b202a07..3b95964fd15 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -140,6 +140,7 @@ ubsha1-objs := os_support.o ubsha1.o lib/sha1.o
 HOSTCFLAGS_ubsha1.o := -pedantic
 
 hostprogs-$(CONFIG_KIRKWOOD) += kwboot
+hostprogs-$(CONFIG_ARMADA_XP) += kwboot
 hostprogs-y += proftool
 hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela
 
diff --git a/tools/bddb/README b/tools/bddb/README
deleted file mode 100644
index 9bee59a0fe7..00000000000
--- a/tools/bddb/README
+++ /dev/null
@@ -1,116 +0,0 @@
-Hymod Board Database
-
-(C) Copyright 2001
-Murray Jensen <Murray.Jensen@csiro.au>
-CSIRO Manufacturing Science and Technology, Preston Lab
-
-25-Jun-01
-
-This stuff is a set of PHP/MySQL scripts to implement a custom board
-database. It will need *extensive* hacking to modify it to keep the
-information about your custom boards that you want, however it is a good
-starting point.
-
-How it is used:
-
-	1. a board has gone through all the hardware testing etc and is
-	   ready to have the flash programmed for the first time - first you
-	   go to a web page and fill in information about the board in a form
-	   to register it in a database
-
-	2. the web stuff allocates a (unique) serial number and (optionally)
-	   a (locally administered) ethernet address and stores the information
-	   in a database using the serial number as the key (can do whole
-	   batches of boards in one go and/or use a previously registered board
-	   as defaults for the new board(s))
-
-	3. it then creates a file in the tftp area of a server somewhere
-	   containing the board information in a simple text format (one
-	   per serial number)
-
-	4. all hymod boards have an i2c eeprom, and when U-Boot sees that
-	   the eeprom is unitialised, it prompts for a serial number and
-	   ethernet address (if not set), then transfers the file created
-	   in step 3 from the server and initialises the eeprom from its
-	   contents
-
-What this means is you can't boot the board until you have allocated a serial
-number, but you don't have to type it all twice - you do it once on the web
-and the board then finds the info it needs to initialise its eeprom. The
-other side of the coin is the reading of the eeprom and how it gets passed
-to Linux (or another O/S).
-
-To see how this is all done for the hymod boards look at the code in the
-"board/hymod" directory and in the file "include/asm/hymod.h". Hymod boards
-can have a mezzanine card which also have an eeprom that needs allocating,
-the same process is used for these as well - just a different i2c address.
-
-Other forms provide the following functions:
-
-	- browsing the board database
-	- editing board information (one at a time)
-	- maintaining/browsing a (simple) per board event log
-
-You will need: MySQL (I use version 3.23.7-alpha), PHP4 (with MySQL
-support enabled) and a web server (I use Apache 1.3.x).
-
-I originally started by using phpMyBuilder (http://kyber.dk/phpMyBuilder)
-but it soon got far more complicated than that could handle (but I left
-the copyright messages in there anyway). Most of the code resides in the
-common defs.php file, which shouldn't need much alteration - all the work
-will be in shaping the front-end php files to your liking.
-
-Here's a quick summary of what needs doing to use it for your boards:
-
-1. get phpMyAdmin (http://phpwizard.net/projects/phpMyAdmin/) - it's an
-   invaluable tool for this sort of stuff (this step is optional of course)
-
-2. edit "bddb.css" to your taste, if you could be bothered - I have no
-   idea what is in there or what it does - I copied it from somewhere else
-   ("user.css" from the phpMyEdit (http://phpmyedit.sourcerforge.net) package,
-   I think) - I figure one day I'll see what sort of things I can change
-   in there.
-
-3. create a mysql database - call it whatever you like
-
-4. edit "create_tables.sql" and modify the "boards" table schema to
-   reflect the information you want to keep about your boards. It may or
-   may not be easier to do this and the next step in phpMyAdmin. Check out
-   the MySQL documentation at http://www.mysql.com/doc/ in particular the
-   column types at http://www.mysql.com/doc/C/o/Column_types.html - Note
-   there is only support for a few data types:
-
-	int		- presented as an html text input
-	char/text	- presented as an html text input
-	date		- presented as an html text input
-	enum		- presented as an html radio input
-
-   I also have what I call "enum_multi" which is a set of enums with the
-   same name, but suffixed with a number e.g. fred0, fred1, fred2. These
-   are presented as a number of html select's with a single label "fred"
-   this is useful for board characteristics that have multiple items of
-   the same type e.g. multiple banks of sdram.
-
-5. use the "create_tables.sql" file to create the "boards" table in the
-   database e.g. mysql dbname < create_tables.sql
-
-6. create a user and password for the web server to log into the MySQL
-   database with; give this user select, insert and update privileges
-   to the database created in 3 (and delete, if you want the "delete"
-   functions in the edit forms to work- I have this turned off). phpMyAdmin
-   helps in this step.
-
-7. edit "config.php" and set the variables: $mysql_user, $mysql_pw, $mysql_db,
-   $bddb_cfgdir and $bddb_label - keep the contents of this file secret - it
-   contains the web servers username and password (the three $mysql_* vars
-   are set from the previous step)
-
-8. edit "defs.php" and a. adjust the various enum value arrays and b. edit
-   the function "pg_foot()" to remove my email address :-)
-
-9. do major hacking on the following files: browse.php, doedit.php, donew.php,
-   edit.php and new.php to reflect your database schema - fortunately the
-   hacking is fairly straight-forward, but it is boring and time-consuming.
-
-These notes were written rather hastily - if you find any obvious problems
-please let me know.
diff --git a/tools/bddb/badsubmit.php b/tools/bddb/badsubmit.php
deleted file mode 100644
index 5092a31969c..00000000000
--- a/tools/bddb/badsubmit.php
+++ /dev/null
@@ -1,23 +0,0 @@
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	require("defs.php");
-	pg_head("$bddb_label - Unknown Submit Type");
-?>
-<center>
-  <font size="+4">
-    <b>
-      The <?php echo "$bddb_label"; ?> form was submitted with an
-      unknown SUBMIT type <?php echo "(value was '$submit')" ?>.
-      <br></br>
-      Perhaps you typed the URL in directly? Click here to go to the
-      home page of the <a href="index.php"><?php echo "$bddb_label"; ?></a>.
-    </b>
-  </font>
-</center>
-<?php
-	pg_foot();
-?>
diff --git a/tools/bddb/bddb.css b/tools/bddb/bddb.css
deleted file mode 100644
index dee2b2ee492..00000000000
--- a/tools/bddb/bddb.css
+++ /dev/null
@@ -1,207 +0,0 @@
-BODY {
-	background:	#e0ffff;
-	color:		#000000;
-	font-family:	Arial, Verdana,	Helvetica;
-}
-H1 {
-	font-family:	"Copperplate Gothic Bold";
-	background:	transparent;
-	color:		#993300;
-	text-align:	center;
-}
-H2, H3, H4, H5 {
-	background:	transparent;
-	color:		#993300;
-	margin-top:	4%;
-	text-align:	center;
-}
-Body.Plain Div.Abstract, Body.Plain P.Abstract {
-	background:	#cccc99;
-	color:		#333300;
-	border:		white;
-	padding:	3%;
-	font-family:	Times, Verdana;
-}
-TH.Nav {
-	background:	#0000cc;
-	color:		#ff9900;
-}
-TH.Menu	{
-	background:	#3366cc;
-	color:		#ff9900;
-}
-A:hover	{
-	color:		#ff6600;
-}
-A.Menu:hover {
-	color:		#ff6600;
-}
-A.HoMe:hover {
-	color:		#ff6600;
-}
-A.Menu {
-	background:	transparent;
-	color:		#ffcc33;
-	font-family:	Verdana, Helvetica, Arial;
-	font-size:	smaller;
-	text-decoration:	none;
-}
-A.Menu:visited {
-	background:	transparent;
-	color:		#ffcc99;
-}
-A.HoMe {
-	background:	transparent;
-	color:		#ffcc33;
-	font-family:	Verdana, Helvetica, Arial;
-	text-decoration:none;
-}
-A.HoMe:visited {
-	background:	transparent;
-	color:		#ffcc99;
-}
-TH.Xmp {
-	background:	#eeeeee;
-	color:		#330066;
-	font-family:	courier;
-	font-weight:	normal;
-}
-TH.LuT {
-	background:	#cccccc;
-	color:	#000000;
-}
-TD.LuT {
-	background:	#ffffcc;
-	color:		#000000;
-	font-size:	85%;
-}
-TH.Info, TD.Info {
-	background:	#ffffcc;
-	color:		#660000;
-	font-family:	"Comic Sans MS", Cursive, Verdana;
-	font-size:	smaller;
-}
-Div.Info, P.Info {
-	background:	#ffff99;
-	color:		#990033;
-	text-align:	left;
-	padding:	2%;
-	font-family:	"Comic Sans MS", Cursive, Verdana;
-	font-size:	85%;
-	}
-Div.Info A {
-	background:	transparent;
-	color:		#ff6600;
-}
-.HL {
-	background:	#ffff99;
-	color:		#000000;
-}
-TD.HL {
-	background:	#ccffff;
-	color:		#000000;
-}
-Div.Margins {
-	width:		512px;
-	text-align:	center;
-}
-TD.Plain {
-	background:	#ffffcc;
-	color:		#000033;
-}
-.Type {
-	background:	#cccccc;
-	color:		#660000;
-}
-.Name {
-	background:	#eeeeee;
-	color:		#660000;
-	vertical-align:	top;
-	text-align:	right;
-}
-.Value {
-	background:	#ffffee;
-	color:		#000066;
-}
-.Drop {
-	background:	#333366;
-	color:		#ffcc33;
-	font-family:	"Copperplate Gothic Light", Helvetica, Verdana, Arial;
-}
-A.Button:hover {
-	color:		#ff6600;
-}
-A.Button {
-	text-decoration:none;
-	color:		#003366;
-	background:	#ffcc66;
-}
-.Button {
-	font-size:	9pt;
-	text-align:	center;
-	text-decoration:none;
-	color:		#003366;
-	background:	#ffcc66;
-	margin-bottom:	2pt;
-	border-top:	2px solid #ffff99;
-	border-left:	2px solid #ffff99;
-	border-right:	2px solid #cc9933;
-	border-bottom:	2px solid #cc9933;
-	font-family:	Verdana, Arial, "Comic Sans MS";
-}
-.Banner	{
-	width:		468;
-	font-size:	12pt;
-	text-align:	center;
-	text-decoration:none;
-	color:		#003366;
-	background:	#ffcc66;
-	border-top:	4px solid #ffff99;
-	border-left:	4px solid #ffff99;
-	border-right:	4px solid #cc9933;
-	border-bottom:	4px solid #cc9933;
-	font-family:	Verdana, Arial, "Comic Sans MS";
-}
-TD.Nova, Body.Nova {
-	background:	#000000;
-	font-family:	"Times New Roman";
-	font-weight:	light;
-	color:		#ffcc00;
-}
-Body.Nova A.Button {
-	background:	gold;
-	color:		#003366;
-}
-Body.Nova A.Banner {
-	background:	transparent;
-	color:		#003366;
-}
-Body.Nova A {
-	background:	transparent;
-	text-decoration:none;
-	color:		#ffd766;
-}
-Body.Nova H1, Body.Nova H2, Body.Nova H3, Body.Nova H4 {
-	background:	transparent;
-	color:		white;
-	margin-top:	4%;
-	text-align:	center;
-	filter:		Blur(Add=1, Direction=0, Strength=8);
-}
-Body.Nova Div.Abstract {
-	background:	#000000;
-	color:		#ffffff;
-	font-family:	Times, Verdana;
-}
-Body.Nova A.Abstract {
-	background:	transparent;
-	color:		#ffeedd;
-}
-Body.Nova TH.LuT {
-	background:	black;
-	color:		#ffff99;
-}
-Body.Nova TD.LuT {
-	background:	navy;
-	color:		#ffff99;
-}
diff --git a/tools/bddb/brlog.php b/tools/bddb/brlog.php
deleted file mode 100644
index fccfbd011c2..00000000000
--- a/tools/bddb/brlog.php
+++ /dev/null
@@ -1,109 +0,0 @@
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	// list page (hymod_bddb / boards)
-
-	require("defs.php");
-
-	pg_head("$bddb_label - Browse Board Log");
-
-	$serno=intval($serno);
-	if ($serno == 0)
-		die("serial number not specified or invalid!");
-
-	function print_cell($str) {
-		if ($str == '')
-			$str = '&nbsp;';
-		echo "\t<td>$str</td>\n";
-	}
-?>
-<table align=center border=1 cellpadding=10>
-<tr>
-<th>serno / edit</th>
-<th>ethaddr</th>
-<th>date</th>
-<th>batch</th>
-<th>type</th>
-<th>rev</th>
-<th>location</th>
-</tr>
-<?php
-	$r=mysql_query("select * from boards where serno=$serno");
-
-	while($row=mysql_fetch_array($r)){
-		foreach ($columns as $key) {
-			if (!key_in_array($key, $row))
-				$row[$key] = '';
-		}
-
-		echo "<tr>\n";
-		print_cell("<a href=\"edit.php?serno=$row[serno]\">$row[serno]</a>");
-		print_cell($row['ethaddr']);
-		print_cell($row['date']);
-		print_cell($row['batch']);
-		print_cell($row['type']);
-		print_cell($row['rev']);
-		print_cell($row['location']);
-		echo "</tr>\n";
-	}
-
-	mysql_free_result($r);
-?>
-</table>
-<hr></hr>
-<p></p>
-<?php
-	$limit=abs(isset($_REQUEST['limit'])?$_REQUEST['limit']:20);
-	$offset=abs(isset($_REQUEST['offset'])?$_REQUEST['offset']:0);
-	$lr=mysql_query("select count(*) as n from log where serno=$serno");
-	$lrow=mysql_fetch_array($lr);
-	if($lrow['n']>$limit){
-		$preoffset=max(0,$offset-$limit);
-		$postoffset=$offset+$limit;
-		echo "<table width=\"100%\">\n<tr align=center>\n";
-		printf("<td><%sa href=\"%s?submit=Log&serno=$serno&offset=%d\"><img border=0 alt=\"&lt;\" src=\"/icons/left.gif\"></a></td>\n", $offset>0?"":"no", $PHP_SELF, $preoffset);
-		printf("<td><%sa href=\"%s?submit=Log&serno=$serno&offset=%d\"><img border=0 alt=\"&gt;\" src=\"/icons/right.gif\"></a></td>\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset);
-		echo "</tr>\n</table>\n";
-	}
-	mysql_free_result($lr);
-?>
-<table width="100%" border=1 cellpadding=10>
-<tr valign=top>
-<th>logno / edit</th>
-<th>date</th>
-<th>who</th>
-<th width="70%">details</th>
-</tr>
-<?php
-	$r=mysql_query("select * from log where serno=$serno order by logno limit $offset,$limit");
-
-	while($row=mysql_fetch_array($r)){
-		echo "<tr>\n";
-		print_cell("<a href=\"edlog.php?serno=$row[serno]&logno=$row[logno]\">$row[logno]</a>");
-		print_cell($row['date']);
-		print_cell($row['who']);
-		print_cell("<pre>" . urldecode($row['details']) . "</pre>");
-		echo "</tr>\n";
-	}
-
-	mysql_free_result($r);
-?>
-</table>
-<hr></hr>
-<p></p>
-<table width="100%">
-<tr>
-  <td align=center>
-    <a href="newlog.php?serno=<?php echo "$serno"; ?>">Add to Log</a>
-  </td>
-  <td align=center>
-    <a href="index.php">Back to Start</a>
-  </td>
-</tr>
-</table>
-<?php
-	pg_foot();
-?>
diff --git a/tools/bddb/browse.php b/tools/bddb/browse.php
deleted file mode 100644
index 675dfab749d..00000000000
--- a/tools/bddb/browse.php
+++ /dev/null
@@ -1,147 +0,0 @@
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	// list page (hymod_bddb / boards)
-
-	require("defs.php");
-
-	$serno=isset($_REQUEST['serno'])?$_REQUEST['serno']:'';
-
-	$verbose=isset($_REQUEST['verbose'])?intval($_REQUEST['verbose']):0;
-
-	pg_head("$bddb_label - Browse database" . ($verbose?" (verbose)":""));
-?>
-<p></p>
-<?php
-	$limit=isset($_REQUEST['limit'])?abs(intval($_REQUEST['limit'])):20;
-	$offset=isset($_REQUEST['offset'])?abs(intval($_REQUEST['offset'])):0;
-
-	if ($serno == '') {
-
-		$lr=mysql_query("select count(*) as n from boards");
-		$lrow=mysql_fetch_array($lr);
-
-		if($lrow['n']>$limit){
-			$preoffset=max(0,$offset-$limit);
-			$postoffset=$offset+$limit;
-			echo "<table width=\"100%\">\n<tr>\n";
-			printf("<td align=left><%sa href=\"%s?submit=Browse&offset=%d&verbose=%d\"><img border=0 alt=\"&lt;\" src=\"/icons/left.gif\"></a></td>\n", $offset>0?"":"no", $PHP_SELF, $preoffset, $verbose);
-			printf("<td align=right><%sa href=\"%s?submit=Browse&offset=%d&verbose=%d\"><img border=0 alt=\"&gt;\" src=\"/icons/right.gif\"></a></td>\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset, $offset);
-			echo "</tr>\n</table>\n";
-		}
-
-		mysql_free_result($lr);
-	}
-?>
-<table align=center border=1 cellpadding=10>
-<tr>
-<th></th>
-<th>serno / edit</th>
-<th>ethaddr</th>
-<th>date</th>
-<th>batch</th>
-<th>type</th>
-<th>rev</th>
-<th>location</th>
-<?php
-	if ($verbose) {
-		echo "<th>comments</th>\n";
-		echo "<th>sdram</th>\n";
-		echo "<th>flash</th>\n";
-		echo "<th>zbt</th>\n";
-		echo "<th>xlxtyp</th>\n";
-		echo "<th>xlxspd</th>\n";
-		echo "<th>xlxtmp</th>\n";
-		echo "<th>xlxgrd</th>\n";
-		echo "<th>cputyp</th>\n";
-		echo "<th>cpuspd</th>\n";
-		echo "<th>cpmspd</th>\n";
-		echo "<th>busspd</th>\n";
-		echo "<th>hstype</th>\n";
-		echo "<th>hschin</th>\n";
-		echo "<th>hschout</th>\n";
-	}
-?>
-</tr>
-<?php
-	$query = "select * from boards";
-	if ($serno != '') {
-		$pre = " where ";
-		foreach (preg_split("/[\s,]+/", $serno) as $s) {
-			if (preg_match('/^[0-9]+$/',$s))
-				$query .= $pre . "serno=" . $s;
-			else if (preg_match('/^([0-9]+)-([0-9]+)$/',$s,$m)) {
-				$m1 = intval($m[1]); $m2 = intval($m[2]);
-				if ($m2 <= $m1)
-					die("bad serial number range ($s)");
-				$query .= $pre . "(serno>=$m[1] and serno<=$m[2])";
-			}
-			else
-				die("illegal serial number ($s)");
-			$pre = " or ";
-		}
-	}
-	$query .= " order by serno";
-	if ($serno == '')
-		$query .= " limit $offset,$limit";
-
-	$r = mysql_query($query);
-
-	function print_cell($str) {
-		if ($str == '')
-			$str = '&nbsp;';
-		echo "\t<td>$str</td>\n";
-	}
-
-	while($row=mysql_fetch_array($r)){
-		foreach ($columns as $key) {
-			if (!key_in_array($key, $row))
-				$row[$key] = '';
-		}
-
-		echo "<tr>\n";
-		print_cell("<a href=\"brlog.php?serno=$row[serno]\">Log</a>");
-		print_cell("<a href=\"edit.php?serno=$row[serno]\">$row[serno]</a>");
-		print_cell($row['ethaddr']);
-		print_cell($row['date']);
-		print_cell($row['batch']);
-		print_cell($row['type']);
-		print_cell($row['rev']);
-		print_cell($row['location']);
-		if ($verbose) {
-			print_cell("<pre>\n" . urldecode($row['comments']) .
-				"\n\t</pre>");
-			print_cell(gather_enum_multi_print("sdram", 4, $row));
-			print_cell(gather_enum_multi_print("flash", 4, $row));
-			print_cell(gather_enum_multi_print("zbt", 16, $row));
-			print_cell(gather_enum_multi_print("xlxtyp", 4, $row));
-			print_cell(gather_enum_multi_print("xlxspd", 4, $row));
-			print_cell(gather_enum_multi_print("xlxtmp", 4, $row));
-			print_cell(gather_enum_multi_print("xlxgrd", 4, $row));
-			print_cell($row['cputyp']);
-			print_cell($row['cpuspd']);
-			print_cell($row['cpmspd']);
-			print_cell($row['busspd']);
-			print_cell($row['hstype']);
-			print_cell($row['hschin']);
-			print_cell($row['hschout']);
-		}
-		echo "</tr>\n";
-	}
-?>
-</table>
-<p></p>
-<table width="100%">
-<tr>
-  <td align=center><?php
-	printf("<a href=\"%s?submit=Browse&offset=%d&verbose=%d%s\">%s Listing</a>\n", $PHP_SELF, $offset, $verbose?0:1, $serno!=''?"&serno=$serno":'', $verbose?"Terse":"Verbose");
-  ?></td>
-  <td align=center><a href="index.php">Back to Start</a></td>
-</tr>
-</table>
-<?php
-	pg_foot();
-?>
diff --git a/tools/bddb/config.php b/tools/bddb/config.php
deleted file mode 100644
index 67257578f0e..00000000000
--- a/tools/bddb/config.php
+++ /dev/null
@@ -1,16 +0,0 @@
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	// mysql database access info
-	$mysql_user="fred";
-	$mysql_pw="apassword";
-	$mysql_db="mydbname";
-
-	// where to put the eeprom config files
-	$bddb_cfgdir = '/tftpboot/bddb';
-
-	// what this database is called
-	$bddb_label = 'Hymod Board Database';
-?>
diff --git a/tools/bddb/create_tables.sql b/tools/bddb/create_tables.sql
deleted file mode 100644
index a2a578867fd..00000000000
--- a/tools/bddb/create_tables.sql
+++ /dev/null
@@ -1,90 +0,0 @@
-# phpMyAdmin MySQL-Dump
-# http://phpwizard.net/phpMyAdmin/
-#
-# Host: localhost Database : hymod_bddb
-
-# (C) Copyright 2001
-# Murray Jensen <Murray.Jensen@csiro.au>
-# CSIRO Manufacturing and Infrastructure Technology, Preston Lab
-
-# --------------------------------------------------------
-#
-# Table structure for table 'boards'
-#
-
-DROP TABLE IF EXISTS boards;
-CREATE TABLE boards (
-   serno int(10) unsigned zerofill NOT NULL auto_increment,
-   ethaddr char(17),
-   date date NOT NULL,
-   batch char(32),
-   type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY') NOT NULL,
-   rev tinyint(3) unsigned zerofill NOT NULL,
-   location char(64),
-   comments text,
-   sdram0 enum('32M','64M','128M','256M','512M','1G','2G','4G'),
-   sdram1 enum('32M','64M','128M','256M','512M','1G','2G','4G'),
-   sdram2 enum('32M','64M','128M','256M','512M','1G','2G','4G'),
-   sdram3 enum('32M','64M','128M','256M','512M','1G','2G','4G'),
-   flash0 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'),
-   flash1 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'),
-   flash2 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'),
-   flash3 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'),
-   zbt0 enum('512K','1M','2M','4M','8M','16M'),
-   zbt1 enum('512K','1M','2M','4M','8M','16M'),
-   zbt2 enum('512K','1M','2M','4M','8M','16M'),
-   zbt3 enum('512K','1M','2M','4M','8M','16M'),
-   zbt4 enum('512K','1M','2M','4M','8M','16M'),
-   zbt5 enum('512K','1M','2M','4M','8M','16M'),
-   zbt6 enum('512K','1M','2M','4M','8M','16M'),
-   zbt7 enum('512K','1M','2M','4M','8M','16M'),
-   zbt8 enum('512K','1M','2M','4M','8M','16M'),
-   zbt9 enum('512K','1M','2M','4M','8M','16M'),
-   zbta enum('512K','1M','2M','4M','8M','16M'),
-   zbtb enum('512K','1M','2M','4M','8M','16M'),
-   zbtc enum('512K','1M','2M','4M','8M','16M'),
-   zbtd enum('512K','1M','2M','4M','8M','16M'),
-   zbte enum('512K','1M','2M','4M','8M','16M'),
-   zbtf enum('512K','1M','2M','4M','8M','16M'),
-   xlxtyp0 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'),
-   xlxtyp1 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'),
-   xlxtyp2 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'),
-   xlxtyp3 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'),
-   xlxspd0 enum('6','7','8','4','5','9','10','11','12'),
-   xlxspd1 enum('6','7','8','4','5','9','10','11','12'),
-   xlxspd2 enum('6','7','8','4','5','9','10','11','12'),
-   xlxspd3 enum('6','7','8','4','5','9','10','11','12'),
-   xlxtmp0 enum('COM','IND'),
-   xlxtmp1 enum('COM','IND'),
-   xlxtmp2 enum('COM','IND'),
-   xlxtmp3 enum('COM','IND'),
-   xlxgrd0 enum('NORMAL','ENGSAMP'),
-   xlxgrd1 enum('NORMAL','ENGSAMP'),
-   xlxgrd2 enum('NORMAL','ENGSAMP'),
-   xlxgrd3 enum('NORMAL','ENGSAMP'),
-   cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)','MPC8560'),
-   cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'),
-   cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'),
-   busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'),
-   hstype enum('AMCC-S2064A','Xilinx-Rockets'),
-   hschin enum('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'),
-   hschout enum('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'),
-   PRIMARY KEY (serno),
-   KEY serno (serno),
-   UNIQUE serno_2 (serno)
-);
-
-#
-# Table structure for table 'log'
-#
-
-DROP TABLE IF EXISTS log;
-CREATE TABLE log (
-   logno int(10) unsigned zerofill NOT NULL auto_increment,
-   serno int(10) unsigned zerofill NOT NULL,
-   date date NOT NULL,
-   details text NOT NULL,
-   PRIMARY KEY (logno),
-   KEY logno (logno, serno, date),
-   UNIQUE logno_2 (logno)
-);
diff --git a/tools/bddb/defs.php b/tools/bddb/defs.php
deleted file mode 100644
index 0b50602823d..00000000000
--- a/tools/bddb/defs.php
+++ /dev/null
@@ -1,710 +0,0 @@
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	// contains mysql user id and password - keep secret
-	require("config.php");
-
-	if (isset($_REQUEST['logout'])) {
-		Header("status: 401 Unauthorized");
-		Header("HTTP/1.0 401 Unauthorized");
-		Header("WWW-authenticate: basic realm=\"$bddb_label\"");
-
-		echo "<html><head><title>" .
-			"Access to '$bddb_label' Denied" .
-			"</title></head>\n";
-		echo "<body bgcolor=#ffffff><br></br><br></br><center><h1>" .
-			"You must be an Authorised User " .
-			"to access the '$bddb_label'" .
-			"</h1>\n</center></body></html>\n";
-		exit;
-	}
-
-	// contents of the various enumerated types - if first item is
-	// empty ('') then the enum is allowed to be null (ie "not null"
-	// is not set on the column)
-
-	// all column names in the database table
-	$columns = array(
-		'serno','ethaddr','date','batch',
-		'type','rev','location','comments',
-		'sdram0','sdram1','sdram2','sdram3',
-		'flash0','flash1','flash2','flash3',
-		'zbt0','zbt1','zbt2','zbt3','zbt4','zbt5','zbt6','zbt7',
-		'zbt8','zbt9','zbta','zbtb','zbtc','zbtd','zbte','zbtf',
-		'xlxtyp0','xlxtyp1','xlxtyp2','xlxtyp3',
-		'xlxspd0','xlxspd1','xlxspd2','xlxspd3',
-		'xlxtmp0','xlxtmp1','xlxtmp2','xlxtmp3',
-		'xlxgrd0','xlxgrd1','xlxgrd2','xlxgrd3',
-		'cputyp','cpuspd','cpmspd','busspd',
-		'hstype','hschin','hschout'
-	);
-
-	// board type
-	$type_vals = array('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY');
-
-	// Xilinx fpga types
-	$xlxtyp_vals = array('','XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140');
-
-	// Xilinx fpga speeds
-	$xlxspd_vals = array('','6','7','8','4','5','9','10','11','12');
-
-	// Xilinx fpga temperatures (commercial or industrial)
-	$xlxtmp_vals = array('','COM','IND');
-
-	// Xilinx fpga grades (normal or engineering sample)
-	$xlxgrd_vals = array('','NORMAL','ENGSAMP');
-
-	// CPU types
-	$cputyp_vals = array('','MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)','MPC8560');
-
-	// CPU/BUS/CPM clock speeds 
-	$clk_vals = array('','33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ');
-
-	// sdram sizes (nbits array is for eeprom config file)
-	$sdram_vals = array('','32M','64M','128M','256M','512M','1G','2G','4G');
-	$sdram_nbits = array(0,25,26,27,28,29,30,31,32);
-
-	// flash sizes (nbits array is for eeprom config file)
-	$flash_vals = array('','4M','8M','16M','32M','64M','128M','256M','512M','1G');
-	$flash_nbits = array(0,22,23,24,25,26,27,28,29,30);
-
-	// zbt ram sizes (nbits array is for write into eeprom config file)
-	$zbt_vals = array('','512K','1M','2M','4M','8M','16M');
-	$zbt_nbits = array(0,19,20,21,22,23,24);
-
-	// high-speed serial attributes
-	$hstype_vals = array('','AMCC-S2064A','Xilinx-Rockets');
-	$hschin_vals = array('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16');
-	$hschout_vals = array('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16');
-
-	// value filters - used when outputting html
-	function rev_filter($num) {
-		if ($num == 0)
-			return "001";
-		else
-			return sprintf("%03d", $num);
-	}
-
-	function text_filter($str) {
-		return urldecode($str);
-	}
-
-	mt_srand(time() | getmypid());
-
-	// set up MySQL connection
-	mysql_connect("", $mysql_user, $mysql_pw) || die("cannot connect");
-	mysql_select_db($mysql_db) || die("cannot select db");
-
-	// page header
-	function pg_head($title)
-	{
-		echo "<html>\n<head>\n";
-		echo "<link rel=stylesheet href=\"bddb.css\" type=\"text/css\" title=\"style sheet\"></link>\n";
-		echo "<title>$title</title>\n";
-		echo "</head>\n";
-		echo "<body>\n";
-		echo "<center><h1>$title</h1></center>\n";
-		echo "<hr></hr>\n";
-	}
-
-	// page footer
-	function pg_foot()
-	{
-		echo "<hr></hr>\n";
-		echo "<table width=\"100%\"><tr><td align=left>\n<address>" .
-			"If you have any problems, email " .
-			"<a href=\"mailto:Murray.Jensen@csiro.au\">" .
-			"Murray Jensen" .
-			"</a></address>\n" .
-			"</td><td align=right>\n" .
-			"<a href=\"index.php?logout=true\">logout</a>\n" .
-			"</td></tr></table>\n";
-		echo "<p><small><i>Made with " .
-		    "<a href=\"http://kyber.dk/phpMyBuilder/\">" .
-		    "Kyber phpMyBuilder</a></i></small></p>\n";
-		echo "</body>\n";
-		echo "</html>\n";
-	}
-
-	// some support functions
-
-	if (!function_exists('array_search')) {
-
-		function array_search($needle, $haystack, $strict = false) {
-
-			if (is_array($haystack) && count($haystack)) {
-
-				$ntype = gettype($needle);
-
-				foreach ($haystack as $key => $value) {
-
-					if ($value == $needle && (!$strict ||
-					    gettype($value) == $ntype))
-						return $key;
-				}
-			}
-
-			return false;
-		}
-	}
-
-	if (!function_exists('in_array')) {
-
-		function in_array($needle, $haystack, $strict = false) {
-
-			if (is_array($haystack) && count($haystack)) {
-
-				$ntype = gettype($needle);
-
-				foreach ($haystack as $key => $value) {
-
-					if ($value == $needle && (!$strict ||
-					    gettype($value) == $ntype))
-						return true;
-				}
-			}
-
-			return false;
-		}
-	}
-
-	function key_in_array($key, $array) {
-		return in_array($key, array_keys($array), true);
-	}
-
-	function enum_to_index($name, $vals) {
-		$index = array_search($GLOBALS[$name], $vals);
-		if ($vals[0] != '')
-			$index++;
-		return $index;
-	}
-
-	// fetch a value from an array - return empty string is not present
-	function get_key_value($key, $array) {
-		if (key_in_array($key, $array))
-			return $array[$key];
-		else
-			return '';
-	}
-
-	function fprintf() {
-		$n = func_num_args();
-		if ($n < 2)
-			return FALSE;
-		$a = func_get_args();
-		$fp = array_shift($a);
-		$x = "\$s = sprintf";
-		$sep = '(';
-		foreach ($a as $z) {
-			$x .= "$sep'$z'";
-			$sep = ',';
-		}
-		$x .= ');';
-		eval($x);
-		$l = strlen($s);
-		$r = fwrite($fp, $s, $l);
-		if ($r != $l)
-			return FALSE;
-		else
-			return TRUE;
-	}
-
-	// functions to display (print) a database table and its columns
-
-	function begin_table($ncols) {
-		global $table_ncols;
-		$table_ncols = $ncols;
-		echo "<table align=center width=\"100%\""
-			. " border=1 cellpadding=4 cols=$table_ncols>\n";
-	}
-
-	function begin_field($name, $span = 0) {
-		global $table_ncols;
-		echo "<tr valign=top>\n";
-		echo "\t<th align=center>$name</th>\n";
-		if ($span <= 0)
-			$span = $table_ncols - 1;
-		if ($span > 1)
-			echo "\t<td colspan=$span>\n";
-		else
-			echo "\t<td>\n";
-	}
-
-	function cont_field($span = 1) {
-		echo "\t</td>\n";
-		if ($span > 1)
-			echo "\t<td colspan=$span>\n";
-		else
-			echo "\t<td>\n";
-	}
-
-	function end_field() {
-		echo "\t</td>\n";
-		echo "</tr>\n";
-	}
-
-	function end_table() {
-		echo "</table>\n";
-	}
-
-	function print_field($name, $array, $size = 0, $filt='') {
-
-		begin_field($name);
-
-		if (key_in_array($name, $array))
-			$value = $array[$name];
-		else
-			$value = '';
-
-		if ($filt != '')
-			$value = $filt($value);
-
-		echo "\t\t<input name=$name value=\"$value\"";
-		if ($size > 0)
-			echo " size=$size maxlength=$size";
-		echo "></input>\n";
-
-		end_field();
-	}
-
-	function print_field_multiline($name, $array, $cols, $rows, $filt='') {
-
-		begin_field($name);
-
-		if (key_in_array($name, $array))
-			$value = $array[$name];
-		else
-			$value = '';
-
-		if ($filt != '')
-			$value = $filt($value);
-
-		echo "\t\t<textarea name=$name " .
-			"cols=$cols rows=$rows wrap=off>\n";
-		echo "$value";
-		echo "</textarea>\n";
-
-		end_field();
-	}
-
-	// print a mysql ENUM as an html RADIO INPUT
-	function print_enum($name, $array, $vals, $def = -1) {
-
-		begin_field($name);
-
-		if (key_in_array($name, $array))
-			$chk = array_search($array[$name], $vals, FALSE);
-		else
-			$chk = $def;
-
-		$nval = count($vals);
-
-		for ($i = 0; $i < $nval; $i++) {
-
-			$val = $vals[$i];
-			if ($val == '')
-				$pval = "none";
-			else
-				$pval = "$val";
-
-			printf("\t\t<input type=radio name=$name"
-				. " value=\"$val\"%s>$pval</input>\n",
-				$i == $chk ? " checked" : "");
-		}
-
-		end_field();
-	}
-
-	// print a mysql ENUM as an html SELECT INPUT
-	function print_enum_select($name, $array, $vals, $def = -1) {
-
-		begin_field($name);
-
-		echo "\t\t<select name=$name>\n";
-
-		if (key_in_array($name, $array))
-			$chk = array_search($array[$name], $vals, FALSE);
-		else
-			$chk = $def;
-
-		$nval = count($vals);
-
-		for ($i = 0; $i < $nval; $i++) {
-
-			$val = $vals[$i];
-			if ($val == '')
-				$pval = "none";
-			else
-				$pval = "$val";
-
-			printf("\t\t\t<option " .
-				"value=\"%s\"%s>%s</option>\n",
-				$val, $i == $chk ? " selected" : "", $pval);
-		}
-
-		echo "\t\t</select>\n";
-
-		end_field();
-	}
-
-	// print a group of mysql ENUMs (e.g. name0,name1,...) as an html SELECT
-	function print_enum_multi($base, $array, $vals, $cnt, $defs, $grp = 0) {
-
-		global $table_ncols;
-
-		if ($grp <= 0)
-			$grp = $cnt;
-		$ncell = $cnt / $grp;
-		$span = ($table_ncols - 1) / $ncell;
-
-		begin_field($base, $span);
-
-		$nval = count($vals);
-
-		for ($i = 0; $i < $cnt; $i++) {
-
-			if ($i > 0 && ($i % $grp) == 0)
-				cont_field($span);
-
-			$name = sprintf("%s%x", $base, $i);
-
-			echo "\t\t<select name=$name>\n";
-
-			if (key_in_array($name, $array))
-				$ai = array_search($array[$name], $vals, FALSE);
-			else {
-				if (key_in_array($i, $defs))
-					$ai = $defs[$i];
-				else
-					$ai = 0;
-			}
-
-			for ($j = 0; $j < $nval; $j++) {
-
-				$val = $vals[$j];
-				if ($val == '')
-					$pval = "&nbsp;";
-				else
-					$pval = "$val";
-
-				printf("\t\t\t<option " .
-					"value=\"%s\"%s>%s</option>\n",
-					$val,
-					$j == $ai ? " selected" : "",
-					$pval);
-			}
-
-			echo "\t\t</select>\n";
-		}
-
-		end_field();
-	}
-
-	// functions to handle the form input
-
-	// fetch all the parts of an "enum_multi" into a string suitable
-	// for a MySQL query
-	function gather_enum_multi_query($base, $cnt) {
-
-		$retval = '';
-
-		for ($i = 0; $i < $cnt; $i++) {
-
-			$name = sprintf("%s%x", $base, $i);
-
-			if (isset($_REQUEST[$name])) {
-				$retval .= sprintf(", %s='%s'",
-					$name, $_REQUEST[$name]);
-			}
-		}
-
-		return $retval;
-	}
-
-	// fetch all the parts of an "enum_multi" into a string suitable
-	// for a display e.g. in an html table cell
-	function gather_enum_multi_print($base, $cnt, $array) {
-
-		$retval = '';
-
-		for ($i = 0; $i < $cnt; $i++) {
-
-			$name = sprintf("%s%x", $base, $i);
-
-			if ($array[$name] != '') {
-				if ($retval != '')
-					$retval .= ',';
-				$retval .= $array[$name];
-			}
-		}
-
-		return $retval;
-	}
-
-	// fetch all the parts of an "enum_multi" into a string suitable
-	// for writing to the eeprom data file
-	function gather_enum_multi_write($base, $cnt, $vals, $xfrm = array()) {
-
-		$retval = '';
-
-		for ($i = 0; $i < $cnt; $i++) {
-
-			$name = sprintf("%s%x", $base, $i);
-
-			if ($GLOBALS[$name] != '') {
-				if ($retval != '')
-					$retval .= ',';
-				$index = enum_to_index($name, $vals);
-				if ($xfrm != array())
-					$retval .= $xfrm[$index];
-				else
-					$retval .= $index;
-			}
-		}
-
-		return $retval;
-	}
-
-	// count how many parts of an "enum_multi" are actually set
-	function count_enum_multi($base, $cnt) {
-
-		$retval = 0;
-
-		for ($i = 0; $i < $cnt; $i++) {
-
-			$name = sprintf("%s%x", $base, $i);
-
-			if (isset($_REQUEST[$name]))
-				$retval++;
-		}
-
-		return $retval;
-	}
-
-	// ethernet address functions
-
-	// generate a (possibly not unique) random vendor ethernet address
-	// (setting bit 6 in the ethernet address - motorola wise i.e. bit 0
-	// is the most significant bit - means it is not an assigned ethernet
-	// address - it is a "locally administered" address). Also, make sure
-	// it is NOT a multicast ethernet address (by setting bit 7 to 0).
-	// e.g. the first byte of all ethernet addresses generated here will
-	// have 2 in the bottom two bits (incidentally, these are the first
-	// two bits transmitted on the wire, since the octets in ethernet
-	// addresses are transmitted LSB first).
-
-	function gen_eth_addr($serno) {
-
-		$ethaddr_hgh = (mt_rand(0, 65535) & 0xfeff) | 0x0200;
-		$ethaddr_mid = mt_rand(0, 65535);
-		$ethaddr_low = mt_rand(0, 65535);
-
-		return sprintf("%02lx:%02lx:%02lx:%02lx:%02lx:%02lx",
-			$ethaddr_hgh >> 8, $ethaddr_hgh & 0xff,
-			$ethaddr_mid >> 8, $ethaddr_mid & 0xff,
-			$ethaddr_low >> 8, $ethaddr_low & 0xff);
-	}
-
-	// check that an ethernet address is valid
-	function eth_addr_is_valid($ethaddr) {
-
-		$ethbytes = split(':', $ethaddr);
-
-		if (count($ethbytes) != 6)
-			return FALSE;
-
-		for ($i = 0; $i < 6; $i++) {
-			$ethbyte = $ethbytes[$i];
-			if (!ereg('^[0-9a-f][0-9a-f]$', $ethbyte))
-				return FALSE;
-		}
-
-		return TRUE;
-	}
-
-	// write a simple eeprom configuration file
-	function write_eeprom_cfg_file() {
-
-		global $sernos, $nsernos, $bddb_cfgdir, $numerrs, $cfgerrs;
-		global $date, $batch, $type_vals, $rev;
-		global $sdram_vals, $sdram_nbits;
-		global $flash_vals, $flash_nbits;
-		global $zbt_vals, $zbt_nbits;
-		global $xlxtyp_vals, $xlxspd_vals, $xlxtmp_vals, $xlxgrd_vals;
-		global $cputyp, $cputyp_vals, $clk_vals;
-		global $hstype, $hstype_vals, $hschin, $hschout;
-
-		$numerrs = 0;
-		$cfgerrs = array();
-
-		for ($i = 0; $i < $nsernos; $i++) {
-
-			$serno = sprintf("%010d", $sernos[$i]);
-
-			$wfp = @fopen($bddb_cfgdir . "/$serno.cfg", "w");
-			if (!$wfp) {
-				$cfgerrs[$i] = 'file create fail';
-				$numerrs++;
-				continue;
-			}
-			set_file_buffer($wfp, 0);
-
-			if (!fprintf($wfp, "serno=%d\n", $sernos[$i])) {
-				$cfgerrs[$i] = 'cfg wr fail (serno)';
-				fclose($wfp);
-				$numerrs++;
-				continue;
-			}
-
-			if (!fprintf($wfp, "date=%s\n", $date)) {
-				$cfgerrs[$i] = 'cfg wr fail (date)';
-				fclose($wfp);
-				$numerrs++;
-				continue;
-			}
-
-			if ($batch != '') {
-				if (!fprintf($wfp, "batch=%s\n", $batch)) {
-					$cfgerrs[$i] = 'cfg wr fail (batch)';
-					fclose($wfp);
-					$numerrs++;
-					continue;
-				}
-			}
-
-			$typei = enum_to_index("type", $type_vals);
-			if (!fprintf($wfp, "type=%d\n", $typei)) {
-				$cfgerrs[$i] = 'cfg wr fail (type)';
-				fclose($wfp);
-				$numerrs++;
-				continue;
-			}
-
-			if (!fprintf($wfp, "rev=%d\n", $rev)) {
-				$cfgerrs[$i] = 'cfg wr fail (rev)';
-				fclose($wfp);
-				$numerrs++;
-				continue;
-			}
-
-			$s = gather_enum_multi_write("sdram", 4,
-				$sdram_vals, $sdram_nbits);
-			if ($s != '') {
-				$b = fprintf($wfp, "sdram=%s\n", $s);
-				if (!$b) {
-					$cfgerrs[$i] = 'cfg wr fail (sdram)';
-					fclose($wfp);
-					$numerrs++;
-					continue;
-				}
-			}
-
-			$s = gather_enum_multi_write("flash", 4,
-				$flash_vals, $flash_nbits);
-			if ($s != '') {
-				$b = fprintf($wfp, "flash=%s\n", $s);
-				if (!$b) {
-					$cfgerrs[$i] = 'cfg wr fail (flash)';
-					fclose($wfp);
-					$numerrs++;
-					continue;
-				}
-			}
-
-			$s = gather_enum_multi_write("zbt", 16,
-				$zbt_vals, $zbt_nbits);
-			if ($s != '') {
-				$b = fprintf($wfp, "zbt=%s\n", $s);
-				if (!$b) {
-					$cfgerrs[$i] = 'cfg wr fail (zbt)';
-					fclose($wfp);
-					$numerrs++;
-					continue;
-				}
-			}
-
-			$s = gather_enum_multi_write("xlxtyp", 4, $xlxtyp_vals);
-			if ($s != '') {
-				$b = fprintf($wfp, "xlxtyp=%s\n", $s);
-				if (!$b) {
-					$cfgerrs[$i] = 'cfg wr fail (xlxtyp)';
-					fclose($wfp);
-					$numerrs++;
-					continue;
-				}
-			}
-
-			$s = gather_enum_multi_write("xlxspd", 4, $xlxspd_vals);
-			if ($s != '') {
-				$b = fprintf($wfp, "xlxspd=%s\n", $s);
-				if (!$b) {
-					$cfgerrs[$i] = 'cfg wr fail (xlxspd)';
-					fclose($wfp);
-					$numerrs++;
-					continue;
-				}
-			}
-
-			$s = gather_enum_multi_write("xlxtmp", 4, $xlxtmp_vals);
-			if ($s != '') {
-				$b = fprintf($wfp, "xlxtmp=%s\n", $s);
-				if (!$b) {
-					$cfgerrs[$i] = 'cfg wr fail (xlxtmp)';
-					fclose($wfp);
-					$numerrs++;
-					continue;
-				}
-			}
-
-			$s = gather_enum_multi_write("xlxgrd", 4, $xlxgrd_vals);
-			if ($s != '') {
-				$b = fprintf($wfp, "xlxgrd=%s\n", $s);
-				if (!$b) {
-					$cfgerrs[$i] = 'cfg wr fail (xlxgrd)';
-					fclose($wfp);
-					$numerrs++;
-					continue;
-				}
-			}
-
-			if ($cputyp != '') {
-				$cputypi = enum_to_index("cputyp",$cputyp_vals);
-				$cpuspdi = enum_to_index("cpuspd", $clk_vals);
-				$busspdi = enum_to_index("busspd", $clk_vals);
-				$cpmspdi = enum_to_index("cpmspd", $clk_vals);
-				$b = fprintf($wfp, "cputyp=%d\ncpuspd=%d\n" .
-					"busspd=%d\ncpmspd=%d\n",
-					$cputypi, $cpuspdi, $busspdi, $cpmspdi);
-				if (!$b) {
-					$cfgerrs[$i] = 'cfg wr fail (cputyp)';
-					fclose($wfp);
-					$numerrs++;
-					continue;
-				}
-			}
-
-			if ($hstype != '') {
-				$hstypei = enum_to_index("hstype",$hstype_vals);
-				$b = fprintf($wfp, "hstype=%d\n" .
-					"hschin=%s\nhschout=%s\n",
-					$hstypei, $hschin, $hschout);
-				if (!$b) {
-					$cfgerrs[$i] = 'cfg wr fail (hstype)';
-					fclose($wfp);
-					$numerrs++;
-					continue;
-				}
-			}
-
-			if (!fclose($wfp)) {
-				$cfgerrs[$i] = 'file cls fail';
-				$numerrs++;
-			}
-		}
-
-		return $numerrs;
-	}
-?>
diff --git a/tools/bddb/dodelete.php b/tools/bddb/dodelete.php
deleted file mode 100644
index 4839e36e60e..00000000000
--- a/tools/bddb/dodelete.php
+++ /dev/null
@@ -1,65 +0,0 @@
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	// dodelete page (hymod_bddb / boards)
-
-	require("defs.php");
-
-	pg_head("$bddb_label - Delete Board Results");
-
-	if (!isset($_REQUEST['serno']))
-		die("the board serial number was not specified");
-	$serno=intval($_REQUEST['serno']);
-
-	mysql_query("delete from boards where serno=$serno");
-
-	if(mysql_errno()) {
-		$errstr = mysql_error();
-		echo "\t<font size=+4>\n";
-		echo "\t\t<p>\n";
-		echo "\t\t\tThe following error was encountered:\n";
-		echo "\t\t</p>\n";
-		echo "\t\t<center>\n";
-		printf("\t\t\t<b>%s</b>\n", $errstr);
-		echo "\t\t</center>\n";
-		echo "\t</font>\n";
-	}
-	else {
-		echo "\t<font size=+2>\n";
-		echo "\t\t<p>\n";
-		echo "\t\t\tThe board with serial number <b>$serno</b> was"
-			. " successfully deleted\n";
-		mysql_query("delete from log where serno=$serno");
-		if (mysql_errno()) {
-			$errstr = mysql_error();
-			echo "\t\t\t<font size=+4>\n";
-			echo "\t\t\t\t<p>\n";
-			echo "\t\t\t\t\tBut the following error occurred " .
-				"when deleting the log entries:\n";
-			echo "\t\t\t\t</p>\n";
-			echo "\t\t\t\t<center>\n";
-			printf("\t\t\t\t\t<b>%s</b>\n", $errstr);
-			echo "\t\t\t\t</center>\n";
-			echo "\t\t\t</font>\n";
-		}
-		echo "\t\t</p>\n";
-		echo "\t</font>\n";
-	}
-?>
-<p>
-<table width="100%">
-<tr>
-  <td align=center>
-    <a href="browse.php">Back to Browse</a>
-  </td>
-  <td align=center>
-    <a href="index.php">Back to Start</a>
-  </td>
-</tr>
-</table>
-<?php
-	pg_foot();
-?>
diff --git a/tools/bddb/dodellog.php b/tools/bddb/dodellog.php
deleted file mode 100644
index 9dd78c11b6d..00000000000
--- a/tools/bddb/dodellog.php
+++ /dev/null
@@ -1,57 +0,0 @@
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	// dodelete page (hymod_bddb / boards)
-
-	require("defs.php");
-
-	pg_head("$bddb_label - Delete Log Entry Results");
-
-	if (!isset($_REQUEST['serno']))
-		die("the board serial number was not specified");
-	$serno=intval($_REQUEST['serno']);
-
-	if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == 0)
-		die("the log entry number not specified!");
-	$logno=$_REQUEST['logno'];
-
-	mysql_query("delete from log where serno=$serno and logno=$logno");
-
-	if(mysql_errno()) {
-		$errstr = mysql_error();
-		echo "\t<font size=+4>\n";
-		echo "\t\t<p>\n";
-		echo "\t\t\tThe following error was encountered:\n";
-		echo "\t\t</p>\n";
-		echo "\t\t<center>\n";
-		printf("\t\t\t<b>%s</b>\n", $errstr);
-		echo "\t\t</center>\n";
-		echo "\t</font>\n";
-	}
-	else {
-		echo "\t<font size=+2>\n";
-		echo "\t\t<p>\n";
-		echo "\t\t\tThe log entry with log number <b>$logno</b>\n";
-		echo "\t\t\tand serial number <b>$serno</b> ";
-		echo "was successfully deleted\n";
-		echo "\t\t</p>\n";
-		echo "\t</font>\n";
-	}
-?>
-<p>
-<table width="100%">
-<tr>
-  <td align=center>
-    <a href="brlog.php?serno=<?php echo "$serno"; ?>">Back to Log</a>
-  </td>
-  <td align=center>
-    <a href="index.php">Back to Start</a>
-  </td>
-</tr>
-</table>
-<?php
-	pg_foot();
-?>
diff --git a/tools/bddb/doedit.php b/tools/bddb/doedit.php
deleted file mode 100644
index 13fbb694790..00000000000
--- a/tools/bddb/doedit.php
+++ /dev/null
@@ -1,186 +0,0 @@
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	// doedit page (hymod_bddb / boards)
-
-	require("defs.php");
-
-	pg_head("$bddb_label - Edit Board Results");
-
-	if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
-		die("the board serial number was not specified");
-	$serno=intval($_REQUEST['serno']);
-
-	$query="update boards set";
-
-	if (isset($_REQUEST['ethaddr'])) {
-		$ethaddr=$_REQUEST['ethaddr'];
-		if (!eth_addr_is_valid($ethaddr))
-			die("ethaddr is invalid ('$ethaddr')");
-		$query.=" ethaddr='$ethaddr',";
-	}
-
-	if (isset($_REQUEST['date'])) {
-		$date=$_REQUEST['date'];
-		list($y, $m, $d) = split("-", $date);
-		if (!checkdate($m, $d, $y) || $y < 1999)
-			die("date is invalid (input '$date', " .
-				"yyyy-mm-dd '$y-$m-$d')");
-		$query.=" date='$date'";
-	}
-
-	if (isset($_REQUEST['batch'])) {
-		$batch=$_REQUEST['batch'];
-		if (strlen($batch) > 32)
-			die("batch field too long (>32)");
-		$query.=", batch='$batch'";
-	}
-
-	if (isset($_REQUEST['type'])) {
-		$type=$_REQUEST['type'];
-		if (!in_array($type, $type_vals))
-			die("Invalid type ($type) specified");
-		$query.=", type='$type'";
-	}
-
-	if (isset($_REQUEST['rev'])) {
-		$rev=$_REQUEST['rev'];
-		if (($rev = intval($rev)) <= 0 || $rev > 255)
-			die("Revision number is invalid ($rev)");
-		$query.=sprintf(", rev=%d", $rev);
-	}
-
-	if (isset($_REQUEST['location'])) {
-		$location=$_REQUEST['location'];
-		if (strlen($location) > 64)
-			die("location field too long (>64)");
-		$query.=", location='$location'";
-	}
-
-	if (isset($_REQUEST['comments']))
-		$comments=$_REQUEST['comments'];
-		$query.=", comments='" . rawurlencode($comments) . "'";
-
-	$query.=gather_enum_multi_query("sdram", 4);
-
-	$query.=gather_enum_multi_query("flash", 4);
-
-	$query.=gather_enum_multi_query("zbt", 16);
-
-	$query.=gather_enum_multi_query("xlxtyp", 4);
-	$nxlx = count_enum_multi("xlxtyp", 4);
-
-	$query.=gather_enum_multi_query("xlxspd", 4);
-	if (count_enum_multi("xlxspd", 4) != $nxlx)
-		die("number of xilinx speeds not same as number of types");
-
-	$query.=gather_enum_multi_query("xlxtmp", 4);
-	if (count_enum_multi("xlxtmp", 4) != $nxlx)
-		die("number of xilinx temps. not same as number of types");
-
-	$query.=gather_enum_multi_query("xlxgrd", 4);
-	if (count_enum_multi("xlxgrd", 4) != $nxlx)
-		die("number of xilinx grades not same as number of types");
-
-	if (isset($_REQUEST['cputyp'])) {
-		$cputyp=$_REQUEST['cputyp'];
-		$query.=", cputyp='$cputyp'";
-		if (!isset($_REQUEST['cpuspd']) || $_REQUEST['cpuspd'] == '')
-			die("must specify cpu speed if cpu type is defined");
-		$cpuspd=$_REQUEST['cpuspd'];
-		$query.=", cpuspd='$cpuspd'";
-		if (!isset($_REQUEST['cpmspd']) || $_REQUEST['cpmspd'] == '')
-			die("must specify cpm speed if cpu type is defined");
-		$cpmspd=$_REQUEST['cpmspd'];
-		$query.=", cpmspd='$cpmspd'";
-		if (!isset($_REQUEST['busspd']) || $_REQUEST['busspd'] == '')
-			die("must specify bus speed if cpu type is defined");
-		$busspd=$_REQUEST['busspd'];
-		$query.=", busspd='$busspd'";
-	}
-	else {
-		if (isset($_REQUEST['cpuspd']))
-			die("can't specify cpu speed if there is no cpu");
-		if (isset($_REQUEST['cpmspd']))
-			die("can't specify cpm speed if there is no cpu");
-		if (isset($_REQUEST['busspd']))
-			die("can't specify bus speed if there is no cpu");
-	}
-
-	if (isset($_REQUEST['hschin'])) {
-		$hschin=$_REQUEST['hschin'];
-		if (($hschin = intval($hschin)) < 0 || $hschin > 4)
-			die("Invalid number of hs input chans ($hschin)");
-	}
-	else
-		$hschin = 0;
-	if (isset($_REQUEST['hschout'])) {
-		$hschout=$_REQUEST['hschout'];
-		if (($hschout = intval($hschout)) < 0 || $hschout > 4)
-			die("Invalid number of hs output chans ($hschout)");
-	}
-	else
-		$hschout = 0;
-	if (isset($_REQUEST['hstype'])) {
-		$hstype=$_REQUEST['hstype'];
-		$query.=", hstype='$hstype'";
-	}
-	else {
-		if ($_REQUEST['hschin'] != 0)
-			die("number of high-speed input channels must be zero"
-				. " if high-speed chip is not present");
-		if ($_REQUEST['hschout'] != 0)
-			die("number of high-speed output channels must be zero"
-				. " if high-speed chip is not present");
-	}
-	$query.=", hschin='$hschin'";
-	$query.=", hschout='$hschout'";
-
-	$query.=" where serno=$serno";
-
-	mysql_query($query);
-	if(mysql_errno()) {
-		$errstr = mysql_error();
-		echo "\t<font size=+4>\n";
-		echo "\t\t<p>\n";
-		echo "\t\t\tThe following error was encountered:\n";
-		echo "\t\t</p>\n";
-		echo "\t\t<center>\n";
-		printf("\t\t\t<b>%s</b>\n", $errstr);
-		echo "\t\t</center>\n";
-		echo "\t</font>\n";
-	}
-	else {
-		$sernos = array($serno);
-		$nsernos = 1;
-
-		write_eeprom_cfg_file();
-
-		echo "\t<font size=+2>\n";
-		echo "\t\t<p>\n";
-		echo "\t\t\tThe board with serial number <b>$serno</b> was"
-			. " successfully updated";
-		if ($numerrs > 0) {
-			$errstr = $cfgerrs[0];
-			echo "<br>\n\t\t\t";
-			echo "(but the cfg file update failed: $errstr)";
-		}
-		echo "\n";
-		echo "\t\t</p>\n";
-		echo "\t</font>\n";
-	}
-
-?>
-<p>
-<table align=center width="100%">
-<tr>
-  <td align=center><a href="browse.php">Back to Browse</a></td>
-  <td align=center><a href="index.php">Back to Start</a></td>
-</tr>
-</table>
-<?php
-	pg_foot();
-?>
diff --git a/tools/bddb/doedlog.php b/tools/bddb/doedlog.php
deleted file mode 100644
index 7009aa7dad1..00000000000
--- a/tools/bddb/doedlog.php
+++ /dev/null
@@ -1,76 +0,0 @@
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	// doedit page (hymod_bddb / boards)
-
-	require("defs.php");
-
-	pg_head("$bddb_label - Edit Log Entry Results");
-
-	if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
-		die("the board serial number was not specified");
-	$serno=intval($_REQUEST['serno']);
-
-	if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == '')
-		die("log number not specified!");
-	$logno=intval($_REQUEST['logno']);
-
-	$query="update log set";
-
-	if (isset($_REQUEST['date'])) {
-		$date=$_REQUEST['date'];
-		list($y, $m, $d) = split("-", $date);
-		if (!checkdate($m, $d, $y) || $y < 1999)
-			die("date is invalid (input '$date', " .
-				"yyyy-mm-dd '$y-$m-$d')");
-		$query.=" date='$date'";
-	}
-
-	if (isset($_REQUEST['who'])) {
-		$who=$_REQUEST['who'];
-		$query.=", who='" . $who . "'";
-	}
-
-	if (isset($_REQUEST['details'])) {
-		$details=$_REQUEST['details'];
-		$query.=", details='" . rawurlencode($details) . "'";
-	}
-
-	$query.=" where serno=$serno and logno=$logno";
-
-	mysql_query($query);
-	if(mysql_errno()) {
-		$errstr = mysql_error();
-		echo "\t<font size=+4>\n";
-		echo "\t\t<p>\n";
-		echo "\t\t\tThe following error was encountered:\n";
-		echo "\t\t</p>\n";
-		echo "\t\t<center>\n";
-		printf("\t\t\t<b>%s</b>\n", $errstr);
-		echo "\t\t</center>\n";
-		echo "\t</font>\n";
-	}
-	else {
-		echo "\t<font size=+2>\n";
-		echo "\t\t<p>\n";
-		echo "\t\t\tThe log entry with log number <b>$logno</b> and\n";
-		echo "\t\t\tserial number <b>$serno</b> ";
-		echo "was successfully updated\n";
-		echo "\t\t</p>\n";
-		echo "\t</font>\n";
-	}
-
-?>
-<p>
-<table align=center width="100%">
-<tr>
-  <td align=center><a href="brlog.php?serno=<?php echo "$serno"; ?>">Back to Log</a></td>
-  <td align=center><a href="index.php">Back to Start</a></td>
-</tr>
-</table>
-<?php
-	pg_foot();
-?>
diff --git a/tools/bddb/donew.php b/tools/bddb/donew.php
deleted file mode 100644
index 39b2c78fcae..00000000000
--- a/tools/bddb/donew.php
+++ /dev/null
@@ -1,230 +0,0 @@
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	// doedit page (hymod_bddb / boards)
-
-	require("defs.php");
-
-	pg_head("$bddb_label - Board Registration Results");
-
-	if (isset($_REQUEST['serno'])) {
-		$serno=$_REQUEST['serno'];
-		die("serial number must not be set ($serno) when Creating!");
-	}
-
-	$query="update boards set";
-
-	list($y, $m, $d) = split("-", $date);
-	if (!checkdate($m, $d, $y) || $y < 1999)
-		die("date is invalid (input '$date', yyyy-mm-dd '$y-$m-$d')");
-	$query.=" date='$date'";
-
-	if ($batch != '') {
-		if (strlen($batch) > 32)
-			die("batch field too long (>32)");
-		$query.=", batch='$batch'";
-	}
-
-	if (!in_array($type, $type_vals))
-		die("Invalid type ($type) specified");
-	$query.=", type='$type'";
-
-	if (($rev = intval($rev)) <= 0 || $rev > 255)
-		die("Revision number is invalid ($rev)");
-	$query.=sprintf(", rev=%d", $rev);
-
-	$query.=gather_enum_multi_query("sdram", 4);
-
-	$query.=gather_enum_multi_query("flash", 4);
-
-	$query.=gather_enum_multi_query("zbt", 16);
-
-	$query.=gather_enum_multi_query("xlxtyp", 4);
-	$nxlx = count_enum_multi("xlxtyp", 4);
-
-	$query.=gather_enum_multi_query("xlxspd", 4);
-	if (count_enum_multi("xlxspd", 4) != $nxlx)
-		die("number of xilinx speeds not same as number of types");
-
-	$query.=gather_enum_multi_query("xlxtmp", 4);
-	if (count_enum_multi("xlxtmp", 4) != $nxlx)
-		die("number of xilinx temps. not same as number of types");
-
-	$query.=gather_enum_multi_query("xlxgrd", 4);
-	if (count_enum_multi("xlxgrd", 4) != $nxlx)
-		die("number of xilinx grades not same as number of types");
-
-	if ($cputyp == '') {
-		if ($cpuspd != '')
-			die("can't specify cpu speed if there is no cpu");
-		if ($cpmspd != '')
-			die("can't specify cpm speed if there is no cpu");
-		if ($busspd != '')
-			die("can't specify bus speed if there is no cpu");
-	}
-	else {
-		$query.=", cputyp='$cputyp'";
-		if ($cpuspd == '')
-			die("must specify cpu speed if cpu type is defined");
-		$query.=", cpuspd='$cpuspd'";
-		if ($cpmspd == '')
-			die("must specify cpm speed if cpu type is defined");
-		$query.=", cpmspd='$cpmspd'";
-		if ($busspd == '')
-			die("must specify bus speed if cpu type is defined");
-		$query.=", busspd='$busspd'";
-	}
-
-	if (($hschin = intval($hschin)) < 0 || $hschin > 4)
-		die("Invalid number of hs input chans ($hschin)");
-	if (($hschout = intval($hschout)) < 0 || $hschout > 4)
-		die("Invalid number of hs output chans ($hschout)");
-	if ($hstype == '') {
-		if ($hschin != 0)
-			die("number of high-speed input channels must be zero"
-				. " if high-speed chip is not present");
-		if ($hschout != 0)
-			die("number of high-speed output channels must be zero"
-				. " if high-speed chip is not present");
-	}
-	else
-		$query.=", hstype='$hstype'";
-	$query.=", hschin='$hschin'";
-	$query.=", hschout='$hschout'";
-
-	// echo "final query = '$query'<br>\n";
-
-	$quant = intval($quant);
-	if ($quant <= 0) $quant = 1;
-
-	$sernos = array();
-	if ($geneths)
-		$ethaddrs = array();
-
-	$sqlerr = '';
-
-	while ($quant-- > 0) {
-
-		mysql_query("insert into boards (serno) values (null)");
-		if (mysql_errno()) {
-			$sqlerr = mysql_error();
-			break;
-		}
-
-		$serno = mysql_insert_id();
-		if (!$serno) {
-			$sqlerr = "couldn't allocate new serial number";
-			break;
-		}
-
-		mysql_query($query . " where serno=$serno");
-		if (mysql_errno()) {
-			$sqlerr = mysql_error();
-			break;
-		}
-
-		array_push($sernos, $serno);
-
-		if ($geneths) {
-
-			$ethaddr = gen_eth_addr($serno);
-
-			mysql_query("update boards set ethaddr='$ethaddr'" .
-			    " where serno=$serno");
-			if (mysql_errno()) {
-				$sqlerr = mysql_error();
-
-				array_push($ethaddrs,
-					"<font color=#ff0000><b>" .
-					"db save fail" .
-					"</b></font>");
-				break;
-			}
-
-			array_push($ethaddrs, $ethaddr);
-		}
-	}
-
-	$nsernos = count($sernos);
-
-	if ($nsernos > 0) {
-
-		write_eeprom_cfg_file();
-
-		echo "<font size=+2>\n";
-		echo "\t<p>\n";
-		echo "\t\tThe following board serial numbers were"
-			. " successfully allocated";
-		if ($numerrs > 0)
-			echo " (but with $numerrs cfg file error" .
-				($numerrs > 1 ? "s" : "") . ")";
-		echo ":\n";
-		echo "\t</p>\n";
-
-		echo "</font>\n";
-
-		echo "<table align=center width=\"100%\">\n";
-		echo "<tr>\n";
-		echo "\t<th>Serial Number</th>\n";
-		if ($numerrs > 0)
-			echo "\t<th>Cfg File Errs</th>\n";
-		if ($geneths)
-			echo "\t<th>Ethernet Address</th>\n";
-		echo "</tr>\n";
-
-		for ($i = 0; $i < $nsernos; $i++) {
-
-			$serno = sprintf("%010d", $sernos[$i]);
-
-			echo "<tr>\n";
-
-			echo "\t<td align=center><font size=+2>" .
-				"<b>$serno</b></font></td>\n";
-
-			if ($numerrs > 0) {
-				if (($errstr = $cfgerrs[$i]) == '')
-					$errstr = '&nbsp;';
-				echo "\t<td align=center>" .
-					"<font size=+2 color=#ff0000><b>" .
-					$errstr .
-					"</b></font></td>\n";
-			}
-
-			if ($geneths) {
-				echo "\t<td align=center>" .
-					"<font size=+2 color=#00ff00><b>" .
-					$ethaddrs[$i] .
-					"</b></font></td>\n";
-			}
-
-			echo "</tr>\n";
-		}
-
-		echo "</table>\n";
-	}
-
-	if ($sqlerr != '') {
-		echo "\t<font size=+4>\n";
-		echo "\t\t<p>\n";
-		echo "\t\t\tThe following SQL error was encountered:\n";
-		echo "\t\t</p>\n";
-		echo "\t\t<center>\n";
-		printf("\t\t\t<b>%s</b>\n", $sqlerr);
-		echo "\t\t</center>\n";
-		echo "\t</font>\n";
-	}
-
-?>
-<p>
-<table align=center width="100%">
-<tr>
-  <td align=center><a href="browse.php">Go to Browse</a></td>
-  <td align=center><a href="index.php">Back to Start</a></td>
-</tr>
-</table>
-<?php
-	pg_foot();
-?>
diff --git a/tools/bddb/donewlog.php b/tools/bddb/donewlog.php
deleted file mode 100644
index 7635d2992d9..00000000000
--- a/tools/bddb/donewlog.php
+++ /dev/null
@@ -1,86 +0,0 @@
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	// doedit page (hymod_bddb / boards)
-
-	require("defs.php");
-
-	pg_head("$bddb_label - Add Log Entry Results");
-
-	if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
-		die("serial number not specified!");
-	$serno=intval($_REQUEST['serno']);
-
-	if (isset($_REQUEST['logno'])) {
-		$logno=$_REQUEST['logno'];
-		die("log number must not be set ($logno) when Creating!");
-	}
-
-	$query="update log set serno=$serno";
-
-	list($y, $m, $d) = split("-", $date);
-	if (!checkdate($m, $d, $y) || $y < 1999)
-		die("date is invalid (input '$date', yyyy-mm-dd '$y-$m-$d')");
-	$query.=", date='$date'";
-
-	if (isset($_REQUEST['who'])) {
-		$who=$_REQUEST['who'];
-		$query.=", who='" . $who . "'";
-	}
-
-	if (isset($_REQUEST['details'])) {
-		$details=$_REQUEST['details'];
-		$query.=", details='" . rawurlencode($details) . "'";
-	}
-
-	// echo "final query = '$query'<br>\n";
-
-	$sqlerr = '';
-
-	mysql_query("insert into log (logno) values (null)");
-	if (mysql_errno())
-		$sqlerr = mysql_error();
-	else {
-		$logno = mysql_insert_id();
-		if (!$logno)
-			$sqlerr = "couldn't allocate new serial number";
-		else {
-			mysql_query($query . " where logno=$logno");
-			if (mysql_errno())
-				$sqlerr = mysql_error();
-		}
-	}
-
-	if ($sqlerr == '') {
-		echo "<font size=+2>\n";
-		echo "\t<p>\n";
-		echo "\t\tA log entry with log number '$logno' was " .
-			"added to the board with serial number '$serno'\n";
-		echo "\t</p>\n";
-		echo "</font>\n";
-	}
-	else {
-		echo "\t<font size=+4>\n";
-		echo "\t\t<p>\n";
-		echo "\t\t\tThe following SQL error was encountered:\n";
-		echo "\t\t</p>\n";
-		echo "\t\t<center>\n";
-		printf("\t\t\t<b>%s</b>\n", $sqlerr);
-		echo "\t\t</center>\n";
-		echo "\t</font>\n";
-	}
-
-?>
-<p></p>
-<table width="100%">
-<tr>
-  <td align=center><a href="brlog.php?serno=<?php echo "$serno"; ?>">Go to Browse</a></td>
-  <td align=center><a href="index.php">Back to Start</a></td>
-</tr>
-</table>
-<?php
-	pg_foot();
-?>
diff --git a/tools/bddb/edit.php b/tools/bddb/edit.php
deleted file mode 100644
index dd8c26c5cd3..00000000000
--- a/tools/bddb/edit.php
+++ /dev/null
@@ -1,131 +0,0 @@
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	// edit page (hymod_bddb / boards)
-
-	require("defs.php");
-
-	pg_head("$bddb_label - Edit Board Registration");
-
-	if ($serno == 0)
-		die("serial number not specified or invalid!");
-
-	$pserno = sprintf("%010d", $serno);
-
-	echo "<center><b><font size=+2>";
-	echo "Board Serial Number: $pserno";
-	echo "</font></b></center>\n";
-
-?>
-<p>
-<form action=doedit.php method=POST>
-<?php
-	echo "<input type=hidden name=serno value=$serno>\n";
-
-	$r=mysql_query("select * from boards where serno=$serno");
-	$row=mysql_fetch_array($r);
-	if(!$row) die("no record of serial number '$serno' in database");
-
-	begin_table(5);
-
-	// ethaddr char(17)
-	print_field("ethaddr", $row, 17);
-
-	// date date
-	print_field("date", $row);
-
-	// batch char(32)
-	print_field("batch", $row, 32);
-
-	// type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY')
-	print_enum("type", $row, $type_vals);
-
-	// rev tinyint(3) unsigned zerofill
-	print_field("rev", $row, 3, 'rev_filter');
-
-	// location char(64)
-	print_field("location", $row, 64);
-
-	// comments text
-	print_field_multiline("comments", $row, 60, 10, 'text_filter');
-
-	// sdram[0-3] enum('32M','64M','128M','256M')
-	print_enum_multi("sdram", $row, $sdram_vals, 4, array());
-
-	// flash[0-3] enum('4M','8M','16M','32M','64M')
-	print_enum_multi("flash", $row, $flash_vals, 4, array());
-
-	// zbt[0-f] enum('512K','1M','2M','4M')
-	print_enum_multi("zbt", $row, $zbt_vals, 16, array());
-
-	// xlxtyp[0-3] enum('XCV300E','XCV400E','XCV600E')
-	print_enum_multi("xlxtyp", $row, $xlxtyp_vals, 4, array(), 1);
-
-	// xlxspd[0-3] enum('6','7','8')
-	print_enum_multi("xlxspd", $row, $xlxspd_vals, 4, array(), 1);
-
-	// xlxtmp[0-3] enum('COM','IND')
-	print_enum_multi("xlxtmp", $row, $xlxtmp_vals, 4, array(), 1);
-
-	// xlxgrd[0-3] enum('NORMAL','ENGSAMP')
-	print_enum_multi("xlxgrd", $row, $xlxgrd_vals, 4, array(), 1);
-
-	// cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)')
-	print_enum("cputyp", $row, $cputyp_vals);
-
-	// cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
-	print_enum_select("cpuspd", $row, $clk_vals);
-
-	// cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
-	print_enum_select("cpmspd", $row, $clk_vals);
-
-	// busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
-	print_enum_select("busspd", $row, $clk_vals);
-
-	// hstype enum('AMCC-S2064A')
-	print_enum("hstype", $row, $hstype_vals);
-
-	// hschin enum('0','1','2','3','4')
-	print_enum("hschin", $row, $hschin_vals);
-
-	// hschout enum('0','1','2','3','4')
-	print_enum("hschout", $row, $hschout_vals);
-
-	end_table();
-
-	echo "<p>\n";
-	echo "<center><b>";
-	echo "<font color=#ff0000>WARNING: NO UNDO ON DELETE!</font>";
-	echo "<br></br>\n";
-	echo "<tt>[ <a href=\"dodelete.php?serno=$serno\">delete</a> ]</tt>";
-	echo "</b></center>\n";
-	echo "</p>\n";
-?>
-<p>
-<table align=center width="100%">
-<tr>
-  <td align=center>
-    <input type=submit value=Edit>
-  </td>
-  <td>
-    &nbsp;
-  </td>
-  <td align=center>
-    <input type=reset value=Reset>
-  </td>
-  <td>
-    &nbsp;
-  </td>
-  <td align=center>
-    <a href="index.php">Back to Start</a>
-  </td>
-</tr>
-</table>
-</p>
-</form>
-<?php
-	pg_foot();
-?>
diff --git a/tools/bddb/edlog.php b/tools/bddb/edlog.php
deleted file mode 100644
index 8befd35b924..00000000000
--- a/tools/bddb/edlog.php
+++ /dev/null
@@ -1,86 +0,0 @@
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	// edit page (hymod_bddb / boards)
-
-	require("defs.php");
-
-	pg_head("$bddb_label - Edit Board Log Entry");
-
-	if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
-		die("serial number not specified!");
-	$serno=intval($_REQUEST['serno']);
-
-	if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == '')
-		die("log number not specified!");
-	$logno=intval($_REQUEST['logno']);
-
-	$pserno = sprintf("%010d", $serno);
-	$plogno = sprintf("%010d", $logno);
-
-	echo "<center><b><font size=+2>";
-	echo "Board Serial Number: $pserno, Log Number: $plogno";
-	echo "</font></b></center>\n";
-
-?>
-<p>
-<form action=doedlog.php method=POST>
-<?php
-	echo "<input type=hidden name=serno value=$serno>\n";
-	echo "<input type=hidden name=logno value=$logno>\n";
-
-	$r=mysql_query("select * from log where serno=$serno and logno=$logno");
-	$row=mysql_fetch_array($r);
-	if(!$row)
-		die("no record of log entry with serial number '$serno' " .
-			"and log number '$logno' in database");
-
-	begin_table(3);
-
-	// date date
-	print_field("date", $row);
-
-	// who char(20)
-	print_field("who", $row);
-
-	// details text
-	print_field_multiline("details", $row, 60, 10, 'text_filter');
-
-	end_table();
-
-	echo "<p>\n";
-	echo "<center><b>";
-	echo "<font color=#ff0000>WARNING: NO UNDO ON DELETE!</font>";
-	echo "<br></br>\n";
-	echo "<tt>[ <a href=\"dodellog.php?serno=$serno&logno=$logno\">delete</a> ]</tt>";
-	echo "</b></center>\n";
-	echo "</p>\n";
-?>
-<p>
-<table align=center width="100%">
-<tr>
-  <td align=center>
-    <input type=submit value=Edit>
-  </td>
-  <td>
-    &nbsp;
-  </td>
-  <td align=center>
-    <input type=reset value=Reset>
-  </td>
-  <td>
-    &nbsp;
-  </td>
-  <td align=center>
-    <a href="index.php">Back to Start</a>
-  </td>
-</tr>
-</table>
-</p>
-</form>
-<?php
-	pg_foot();
-?>
diff --git a/tools/bddb/execute.php b/tools/bddb/execute.php
deleted file mode 100644
index 0b62882d751..00000000000
--- a/tools/bddb/execute.php
+++ /dev/null
@@ -1,33 +0,0 @@
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	$serno=isset($_REQUEST['serno'])?$_REQUEST['serno']:'';
-
-	$submit=isset($_REQUEST['submit'])?$_REQUEST['submit']:"[NOT SET]";
-
-	switch ($submit) {
-
-	case "New":
-		require("new.php");
-		break;
-
-	case "Edit":
-		require("edit.php");
-		break;
-
-	case "Browse":
-		require("browse.php");
-		break;
-
-	case "Log":
-		require("brlog.php");
-		break;
-
-	default:
-		require("badsubmit.php");
-		break;
-	}
-?>
diff --git a/tools/bddb/index.php b/tools/bddb/index.php
deleted file mode 100644
index 842aed55fb0..00000000000
--- a/tools/bddb/index.php
+++ /dev/null
@@ -1,38 +0,0 @@
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	require("defs.php");
-	pg_head("$bddb_label");
-?>
-<font size="+4">
-  <form action=execute.php method=POST>
-    <table width="100%" cellspacing=10 cellpadding=10>
-      <tr>
-	<td align=center>
-	  <input type=submit name=submit value="New"></input>
-	</td>
-	<td align=center>
-	  <input type=submit name=submit value="Edit"></input>
-	</td>
-	<td align=center>
-	  <input type=submit name=submit value="Browse"></input>
-	</td>
-	<td align=center>
-	  <input type=submit name=submit value="Log"></input>
-	</td>
-      </tr>
-      <tr>
-	<td align=center colspan=4>
-	  <b>Serial Number:</b>
-	  <input type=text name=serno size=10 maxsize=10 value=""></input>
-	</td>
-      </tr>
-    </table>
-  </form>
-</font>
-<?php
-	pg_foot();
-?>
diff --git a/tools/bddb/new.php b/tools/bddb/new.php
deleted file mode 100644
index 30323ff8192..00000000000
--- a/tools/bddb/new.php
+++ /dev/null
@@ -1,120 +0,0 @@
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	// edit page (hymod_bddb / boards)
-
-	require("defs.php");
-
-	pg_head("$bddb_label - New Board Registration");
-?>
-<form action=donew.php method=POST>
-<p></p>
-<?php
-	$serno=intval($serno);
-	// if a serial number was supplied, fetch the record
-	// and use its contents as defaults
-	if ($serno != 0) {
-		$r=mysql_query("select * from boards where serno=$serno");
-		$row=mysql_fetch_array($r);
-		if(!$row)die("no record of serial number '$serno' in database");
-	}
-	else
-		$row = array();
-
-	begin_table(5);
-
-	// date date
-	print_field("date", array('date' => date("Y-m-d")));
-
-	// batch char(32)
-	print_field("batch", $row, 32);
-
-	// type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY')
-	print_enum("type", $row, $type_vals, 0);
-
-	// rev tinyint(3) unsigned zerofill
-	print_field("rev", $row, 3, 'rev_filter');
-
-	// sdram[0-3] enum('32M','64M','128M','256M')
-	print_enum_multi("sdram", $row, $sdram_vals, 4, array(2));
-
-	// flash[0-3] enum('4M','8M','16M','32M','64M')
-	print_enum_multi("flash", $row, $flash_vals, 4, array(2));
-
-	// zbt[0-f] enum('512K','1M','2M','4M')
-	print_enum_multi("zbt", $row, $zbt_vals, 16, array(2, 2));
-
-	// xlxtyp[0-3] enum('XCV300E','XCV400E','XCV600E')
-	print_enum_multi("xlxtyp", $row, $xlxtyp_vals, 4, array(1), 1);
-
-	// xlxspd[0-3] enum('6','7','8')
-	print_enum_multi("xlxspd", $row, $xlxspd_vals, 4, array(1), 1);
-
-	// xlxtmp[0-3] enum('COM','IND')
-	print_enum_multi("xlxtmp", $row, $xlxtmp_vals, 4, array(1), 1);
-
-	// xlxgrd[0-3] enum('NORMAL','ENGSAMP')
-	print_enum_multi("xlxgrd", $row, $xlxgrd_vals, 4, array(1), 1);
-
-	// cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)')
-	print_enum("cputyp", $row, $cputyp_vals, 1);
-
-	// cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
-	print_enum_select("cpuspd", $row, $clk_vals, 4);
-
-	// cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
-	print_enum_select("cpmspd", $row, $clk_vals, 4);
-
-	// busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
-	print_enum_select("busspd", $row, $clk_vals, 2);
-
-	// hstype enum('AMCC-S2064A')
-	print_enum("hstype", $row, $hstype_vals, 1);
-
-	// hschin enum('0','1','2','3','4')
-	print_enum("hschin", $row, $hschin_vals, 4);
-
-	// hschout enum('0','1','2','3','4')
-	print_enum("hschout", $row, $hschout_vals, 4);
-
-	end_table();
-?>
-<p></p>
-<table width="100%">
-<tr>
-  <td align=center colspan=3>
-    Allocate
-    <input type=text name=quant size=2 maxlength=2 value=" 1">
-    board serial number(s)
-  </td>
-</tr>
-<tr>
-  <td align=center colspan=3>
-    <input type=checkbox name=geneths checked>
-    Generate Ethernet Address(es)
-  </td>
-</tr>
-<tr>
-  <td colspan=3>
-    &nbsp;
-  </td>
-</tr>
-<tr>
-  <td align=center>
-    <input type=submit value="Register Board">
-  </td>
-  <td>
-    &nbsp;
-  </td>
-  <td align=center>
-    <input type=reset value="Reset Form Contents">
-  </td>
-</tr>
-</table>
-</form>
-<?php
-	pg_foot();
-?>
diff --git a/tools/bddb/newlog.php b/tools/bddb/newlog.php
deleted file mode 100644
index 609bb855c5a..00000000000
--- a/tools/bddb/newlog.php
+++ /dev/null
@@ -1,54 +0,0 @@
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
-	// (C) Copyright 2001
-	// Murray Jensen <Murray.Jensen@csiro.au>
-	// CSIRO Manufacturing Science and Technology, Preston Lab
-
-	// edit page (hymod_bddb / boards)
-
-	require("defs.php");
-
-	pg_head("$bddb_label - New Log Entry");
-
-	if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
-		die("serial number not specified or invalid!");
-	$serno=intval($_REQUEST['serno']);
-
-	if (isset($_REQUEST['logno'])) {
-		$logno=$_REQUEST['logno'];
-		die("log number must not be specified when adding! ($logno)");
-	}
-?>
-<form action=donewlog.php method=POST>
-<p></p>
-<?php
-	echo "<input type=hidden name=serno value=$serno>\n";
-
-	begin_table(3);
-
-	// date date
-	print_field("date", array('date' => date("Y-m-d")));
-
-	// who char(20)
-	print_field("who", array());
-
-	// details text
-	print_field_multiline("details", array(), 60, 10, 'text_filter');
-
-	end_table();
-?>
-<p></p>
-<table width="100%">
-<tr>
-  <td align=center>
-    <input type=submit value="Add Log Entry">
-  </td>
-  <td align=center>
-    <input type=reset value="Reset Form Contents">
-  </td>
-</tr>
-</table>
-</form>
-<?php
-	pg_foot();
-?>
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 109d61686ec..c50f2e2b249 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -1,364 +1,824 @@
 /*
- * (C) Copyright 2008
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Image manipulator for Marvell SoCs
+ *  supports Kirkwood, Dove, Armada 370, and Armada XP
+ *
+ * (C) Copyright 2013 Thomas Petazzoni
+ * <thomas.petazzoni@free-electrons.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Not implemented: support for the register headers and secure
+ * headers in v1 images
  */
 
 #include "imagetool.h"
+#include <limits.h>
 #include <image.h>
+#include <stdint.h>
 #include "kwbimage.h"
 
-/*
- * Supported commands for configuration file
- */
-static table_entry_t kwbimage_cmds[] = {
-	{CMD_BOOT_FROM,		"BOOT_FROM",		"boot command",	},
-	{CMD_NAND_ECC_MODE,	"NAND_ECC_MODE",	"NAND mode",	},
-	{CMD_NAND_PAGE_SIZE,	"NAND_PAGE_SIZE",	"NAND size",	},
-	{CMD_SATA_PIO_MODE,	"SATA_PIO_MODE",	"SATA mode",	},
-	{CMD_DDR_INIT_DELAY,	"DDR_INIT_DELAY",	"DDR init dly",	},
-	{CMD_DATA,		"DATA",			"Reg Write Data", },
-	{CMD_INVALID,		"",			"",	},
+#define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1))
+
+/* Structure of the main header, version 0 (Kirkwood, Dove) */
+struct main_hdr_v0 {
+	uint8_t  blockid;		/*0     */
+	uint8_t  nandeccmode;		/*1     */
+	uint16_t nandpagesize;		/*2-3   */
+	uint32_t blocksize;		/*4-7   */
+	uint32_t rsvd1;			/*8-11  */
+	uint32_t srcaddr;		/*12-15 */
+	uint32_t destaddr;		/*16-19 */
+	uint32_t execaddr;		/*20-23 */
+	uint8_t  satapiomode;		/*24    */
+	uint8_t  rsvd3;			/*25    */
+	uint16_t ddrinitdelay;		/*26-27 */
+	uint16_t rsvd2;			/*28-29 */
+	uint8_t  ext;			/*30    */
+	uint8_t  checksum;		/*31    */
+};
+
+struct ext_hdr_v0_reg {
+	uint32_t raddr;
+	uint32_t rdata;
+};
+
+#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
+
+struct ext_hdr_v0 {
+	uint32_t              offset;
+	uint8_t               reserved[0x20 - sizeof(uint32_t)];
+	struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
+	uint8_t               reserved2[7];
+	uint8_t               checksum;
+};
+
+/* Structure of the main header, version 1 (Armada 370, Armada XP) */
+struct main_hdr_v1 {
+	uint8_t  blockid;               /* 0 */
+	uint8_t  reserved1;             /* 1 */
+	uint16_t reserved2;             /* 2-3 */
+	uint32_t blocksize;             /* 4-7 */
+	uint8_t  version;               /* 8 */
+	uint8_t  headersz_msb;          /* 9 */
+	uint16_t headersz_lsb;          /* A-B */
+	uint32_t srcaddr;               /* C-F */
+	uint32_t destaddr;              /* 10-13 */
+	uint32_t execaddr;              /* 14-17 */
+	uint8_t  reserved3;             /* 18 */
+	uint8_t  nandblocksize;         /* 19 */
+	uint8_t  nandbadblklocation;    /* 1A */
+	uint8_t  reserved4;             /* 1B */
+	uint16_t reserved5;             /* 1C-1D */
+	uint8_t  ext;                   /* 1E */
+	uint8_t  checksum;              /* 1F */
 };
 
 /*
- * Supported Boot options for configuration file
+ * Header for the optional headers, version 1 (Armada 370, Armada XP)
  */
-static table_entry_t kwbimage_bootops[] = {
-	{IBR_HDR_SPI_ID,	"spi",		"SPI Flash",	},
-	{IBR_HDR_NAND_ID,	"nand",		"NAND Flash",	},
-	{IBR_HDR_SATA_ID,	"sata",		"Sata port",	},
-	{IBR_HDR_PEX_ID,	"pex",		"PCIe port",	},
-	{IBR_HDR_UART_ID,	"uart",		"Serial port",	},
-	{-1,			"",		"Invalid",	},
+struct opt_hdr_v1 {
+	uint8_t  headertype;
+	uint8_t  headersz_msb;
+	uint16_t headersz_lsb;
+	char     data[0];
 };
 
 /*
- * Supported NAND ecc options configuration file
+ * Various values for the opt_hdr_v1->headertype field, describing the
+ * different types of optional headers. The "secure" header contains
+ * informations related to secure boot (encryption keys, etc.). The
+ * "binary" header contains ARM binary code to be executed prior to
+ * executing the main payload (usually the bootloader). This is
+ * typically used to execute DDR3 training code. The "register" header
+ * allows to describe a set of (address, value) tuples that are
+ * generally used to configure the DRAM controller.
  */
-static table_entry_t kwbimage_eccmodes[] = {
-	{IBR_HDR_ECC_DEFAULT,		"default",	"Default mode",	},
-	{IBR_HDR_ECC_FORCED_HAMMING,	"hamming",	"Hamming mode",	},
-	{IBR_HDR_ECC_FORCED_RS,		"rs",		"RS mode",	},
-	{IBR_HDR_ECC_DISABLED,		"disabled",	"ECC Disabled",	},
-	{-1,				"",		"",	},
+#define OPT_HDR_V1_SECURE_TYPE   0x1
+#define OPT_HDR_V1_BINARY_TYPE   0x2
+#define OPT_HDR_V1_REGISTER_TYPE 0x3
+
+#define KWBHEADER_V1_SIZE(hdr) \
+	(((hdr)->headersz_msb << 16) | (hdr)->headersz_lsb)
+
+static struct image_cfg_element *image_cfg;
+static int cfgn;
+
+struct boot_mode {
+	unsigned int id;
+	const char *name;
+};
+
+struct boot_mode boot_modes[] = {
+	{ 0x4D, "i2c"  },
+	{ 0x5A, "spi"  },
+	{ 0x8B, "nand" },
+	{ 0x78, "sata" },
+	{ 0x9C, "pex"  },
+	{ 0x69, "uart" },
+	{},
+};
+
+struct nand_ecc_mode {
+	unsigned int id;
+	const char *name;
+};
+
+struct nand_ecc_mode nand_ecc_modes[] = {
+	{ 0x00, "default" },
+	{ 0x01, "hamming" },
+	{ 0x02, "rs" },
+	{ 0x03, "disabled" },
+	{},
+};
+
+/* Used to identify an undefined execution or destination address */
+#define ADDR_INVALID ((uint32_t)-1)
+
+#define BINARY_MAX_ARGS 8
+
+/* In-memory representation of a line of the configuration file */
+struct image_cfg_element {
+	enum {
+		IMAGE_CFG_VERSION = 0x1,
+		IMAGE_CFG_BOOT_FROM,
+		IMAGE_CFG_DEST_ADDR,
+		IMAGE_CFG_EXEC_ADDR,
+		IMAGE_CFG_NAND_BLKSZ,
+		IMAGE_CFG_NAND_BADBLK_LOCATION,
+		IMAGE_CFG_NAND_ECC_MODE,
+		IMAGE_CFG_NAND_PAGESZ,
+		IMAGE_CFG_BINARY,
+		IMAGE_CFG_PAYLOAD,
+		IMAGE_CFG_DATA,
+	} type;
+	union {
+		unsigned int version;
+		unsigned int bootfrom;
+		struct {
+			const char *file;
+			unsigned int args[BINARY_MAX_ARGS];
+			unsigned int nargs;
+		} binary;
+		const char *payload;
+		unsigned int dstaddr;
+		unsigned int execaddr;
+		unsigned int nandblksz;
+		unsigned int nandbadblklocation;
+		unsigned int nandeccmode;
+		unsigned int nandpagesz;
+		struct ext_hdr_v0_reg regdata;
+	};
 };
 
-static struct kwb_header kwbimage_header;
-static int datacmd_cnt = 0;
-static char * fname = "Unknown";
-static int lineno = -1;
+#define IMAGE_CFG_ELEMENT_MAX 256
 
 /*
- * Report Error if xflag is set in addition to default
+ * Byte 8 of the image header contains the version number. In the v0
+ * header, byte 8 was reserved, and always set to 0. In the v1 header,
+ * byte 8 has been changed to a proper field, set to 1.
  */
-static int kwbimage_check_params(struct image_tool_params *params)
+static unsigned int image_version(void *header)
 {
-	if (!strlen (params->imagename)) {
-		printf ("Error:%s - Configuration file not specified, "
-			"it is needed for kwbimage generation\n",
-			params->cmdname);
-		return CFG_INVALID;
-	}
-	return	((params->dflag && (params->fflag || params->lflag)) ||
-		(params->fflag && (params->dflag || params->lflag)) ||
-		(params->lflag && (params->dflag || params->fflag)) ||
-		(params->xflag) || !(strlen (params->imagename)));
+	unsigned char *ptr = header;
+	return ptr[8];
+}
+
+/*
+ * Utility functions to manipulate boot mode and ecc modes (convert
+ * them back and forth between description strings and the
+ * corresponding numerical identifiers).
+ */
+
+static const char *image_boot_mode_name(unsigned int id)
+{
+	int i;
+	for (i = 0; boot_modes[i].name; i++)
+		if (boot_modes[i].id == id)
+			return boot_modes[i].name;
+	return NULL;
 }
 
-static uint32_t check_get_hexval (char *token)
+int image_boot_mode_id(const char *boot_mode_name)
 {
-	uint32_t hexval;
+	int i;
+	for (i = 0; boot_modes[i].name; i++)
+		if (!strcmp(boot_modes[i].name, boot_mode_name))
+			return boot_modes[i].id;
+
+	return -1;
+}
+
+int image_nand_ecc_mode_id(const char *nand_ecc_mode_name)
+{
+	int i;
+	for (i = 0; nand_ecc_modes[i].name; i++)
+		if (!strcmp(nand_ecc_modes[i].name, nand_ecc_mode_name))
+			return nand_ecc_modes[i].id;
+	return -1;
+}
+
+static struct image_cfg_element *
+image_find_option(unsigned int optiontype)
+{
+	int i;
 
-	if (!sscanf (token, "%x", &hexval)) {
-		printf ("Error:%s[%d] - Invalid hex data(%s)\n", fname,
-			lineno, token);
-		exit (EXIT_FAILURE);
+	for (i = 0; i < cfgn; i++) {
+		if (image_cfg[i].type == optiontype)
+			return &image_cfg[i];
 	}
-	return hexval;
+
+	return NULL;
+}
+
+static unsigned int
+image_count_options(unsigned int optiontype)
+{
+	int i;
+	unsigned int count = 0;
+
+	for (i = 0; i < cfgn; i++)
+		if (image_cfg[i].type == optiontype)
+			count++;
+
+	return count;
 }
 
 /*
- * Generates 8 bit checksum
+ * Compute a 8-bit checksum of a memory area. This algorithm follows
+ * the requirements of the Marvell SoC BootROM specifications.
  */
-static uint8_t kwbimage_checksum8 (void *start, uint32_t len, uint8_t csum)
+static uint8_t image_checksum8(void *start, uint32_t len)
 {
-	register uint8_t sum = csum;
-	volatile uint8_t *p = (volatile uint8_t *)start;
+	uint8_t csum = 0;
+	uint8_t *p = start;
 
 	/* check len and return zero checksum if invalid */
 	if (!len)
 		return 0;
 
 	do {
-		sum += *p;
+		csum += *p;
 		p++;
 	} while (--len);
-	return (sum);
+
+	return csum;
 }
 
-/*
- * Generates 32 bit checksum
- */
-static uint32_t kwbimage_checksum32 (uint32_t *start, uint32_t len, uint32_t csum)
+static uint32_t image_checksum32(void *start, uint32_t len)
 {
-	register uint32_t sum = csum;
-	volatile uint32_t *p = start;
+	uint32_t csum = 0;
+	uint32_t *p = start;
 
 	/* check len and return zero checksum if invalid */
 	if (!len)
 		return 0;
 
 	if (len % sizeof(uint32_t)) {
-		printf ("Error:%s[%d] - length is not in multiple of %zu\n",
-			__FUNCTION__, len, sizeof(uint32_t));
+		fprintf(stderr, "Length %d is not in multiple of %zu\n",
+			len, sizeof(uint32_t));
 		return 0;
 	}
 
 	do {
-		sum += *p;
+		csum += *p;
 		p++;
 		len -= sizeof(uint32_t);
 	} while (len > 0);
-	return (sum);
+
+	return csum;
 }
 
-static void kwbimage_check_cfgdata (char *token, enum kwbimage_cmd cmdsw,
-					struct kwb_header *kwbhdr)
+static void *image_create_v0(size_t *imagesz, struct image_tool_params *params,
+			     int payloadsz)
 {
-	bhr_t *mhdr = &kwbhdr->kwb_hdr;
-	extbhr_t *exthdr = &kwbhdr->kwb_exthdr;
-	int i;
+	struct image_cfg_element *e;
+	size_t headersz;
+	struct main_hdr_v0 *main_hdr;
+	struct ext_hdr_v0 *ext_hdr;
+	void *image;
+	int has_ext = 0;
+
+	/*
+	 * Calculate the size of the header and the size of the
+	 * payload
+	 */
+	headersz  = sizeof(struct main_hdr_v0);
+
+	if (image_count_options(IMAGE_CFG_DATA) > 0) {
+		has_ext = 1;
+		headersz += sizeof(struct ext_hdr_v0);
+	}
 
-	switch (cmdsw) {
-	case CMD_BOOT_FROM:
-		i = get_table_entry_id (kwbimage_bootops,
-				"Kwbimage boot option", token);
+	if (image_count_options(IMAGE_CFG_PAYLOAD) > 1) {
+		fprintf(stderr, "More than one payload, not possible\n");
+		return NULL;
+	}
 
-		if (i < 0)
-			goto INVL_DATA;
+	image = malloc(headersz);
+	if (!image) {
+		fprintf(stderr, "Cannot allocate memory for image\n");
+		return NULL;
+	}
 
-		mhdr->blockid = i;
-		printf ("Preparing kirkwood boot image to boot "
-			"from %s\n", token);
-		break;
-	case CMD_NAND_ECC_MODE:
-		i = get_table_entry_id (kwbimage_eccmodes,
-			"NAND ecc mode", token);
+	memset(image, 0, headersz);
+
+	main_hdr = image;
+
+	/* Fill in the main header */
+	main_hdr->blocksize = payloadsz + sizeof(uint32_t) - headersz;
+	main_hdr->srcaddr   = headersz;
+	main_hdr->ext       = has_ext;
+	main_hdr->destaddr  = params->addr;
+	main_hdr->execaddr  = params->ep;
+
+	e = image_find_option(IMAGE_CFG_BOOT_FROM);
+	if (e)
+		main_hdr->blockid = e->bootfrom;
+	e = image_find_option(IMAGE_CFG_NAND_ECC_MODE);
+	if (e)
+		main_hdr->nandeccmode = e->nandeccmode;
+	e = image_find_option(IMAGE_CFG_NAND_PAGESZ);
+	if (e)
+		main_hdr->nandpagesize = e->nandpagesz;
+	main_hdr->checksum = image_checksum8(image,
+					     sizeof(struct main_hdr_v0));
+
+	/* Generate the ext header */
+	if (has_ext) {
+		int cfgi, datai;
+
+		ext_hdr = image + sizeof(struct main_hdr_v0);
+		ext_hdr->offset = 0x40;
+
+		for (cfgi = 0, datai = 0; cfgi < cfgn; cfgi++) {
+			e = &image_cfg[cfgi];
+			if (e->type != IMAGE_CFG_DATA)
+				continue;
+
+			ext_hdr->rcfg[datai].raddr = e->regdata.raddr;
+			ext_hdr->rcfg[datai].rdata = e->regdata.rdata;
+			datai++;
+		}
 
-		if (i < 0)
-			goto INVL_DATA;
+		ext_hdr->checksum = image_checksum8(ext_hdr,
+						    sizeof(struct ext_hdr_v0));
+	}
 
-		mhdr->nandeccmode = i;
-		printf ("Nand ECC mode = %s\n", token);
-		break;
-	case CMD_NAND_PAGE_SIZE:
-		mhdr->nandpagesize =
-			(uint16_t) check_get_hexval (token);
-		printf ("Nand page size = 0x%x\n", mhdr->nandpagesize);
-		break;
-	case CMD_SATA_PIO_MODE:
-		mhdr->satapiomode =
-			(uint8_t) check_get_hexval (token);
-		printf ("Sata PIO mode = 0x%x\n",
-				mhdr->satapiomode);
-		break;
-	case CMD_DDR_INIT_DELAY:
-		mhdr->ddrinitdelay =
-			(uint16_t) check_get_hexval (token);
-		printf ("DDR init delay = %d msec\n", mhdr->ddrinitdelay);
-		break;
-	case CMD_DATA:
-		exthdr->rcfg[datacmd_cnt].raddr =
-			check_get_hexval (token);
+	*imagesz = headersz;
+	return image;
+}
 
-		break;
-	case CMD_INVALID:
-		goto INVL_DATA;
-	default:
-		goto INVL_DATA;
+static size_t image_headersz_v1(struct image_tool_params *params,
+				int *hasext)
+{
+	struct image_cfg_element *binarye;
+	size_t headersz;
+	int ret;
+
+	/*
+	 * Calculate the size of the header and the size of the
+	 * payload
+	 */
+	headersz = sizeof(struct main_hdr_v1);
+
+	if (image_count_options(IMAGE_CFG_BINARY) > 1) {
+		fprintf(stderr, "More than one binary blob, not supported\n");
+		return 0;
 	}
-	return;
 
-INVL_DATA:
-	printf ("Error:%s[%d] - Invalid data\n", fname, lineno);
-	exit (EXIT_FAILURE);
+	if (image_count_options(IMAGE_CFG_PAYLOAD) > 1) {
+		fprintf(stderr, "More than one payload, not possible\n");
+		return 0;
+	}
+
+	binarye = image_find_option(IMAGE_CFG_BINARY);
+	if (binarye) {
+		struct stat s;
+
+		ret = stat(binarye->binary.file, &s);
+		if (ret < 0) {
+			char cwd[PATH_MAX];
+			char *dir = cwd;
+
+			memset(cwd, 0, sizeof(cwd));
+			if (!getcwd(cwd, sizeof(cwd))) {
+				dir = "current working directory";
+				perror("getcwd() failed");
+			}
+
+			fprintf(stderr,
+				"Didn't find the file '%s' in '%s' which is mandatory to generate the image\n"
+				"This file generally contains the DDR3 training code, and should be extracted from an existing bootable\n"
+				"image for your board. See 'kwbimage -x' to extract it from an existing image.\n",
+				binarye->binary.file, dir);
+			return 0;
+		}
+
+		headersz += s.st_size +
+			binarye->binary.nargs * sizeof(unsigned int);
+		if (hasext)
+			*hasext = 1;
+	}
+
+	/*
+	 * The payload should be aligned on some reasonable
+	 * boundary
+	 */
+	return ALIGN_SUP(headersz, 4096);
 }
 
-/*
- * this function sets the kwbimage header by-
- * 	1. Abstracting input command line arguments data
- *	2. parses the kwbimage configuration file and update extebded header data
- *	3. calculates header, extended header and image checksums
- */
-static void kwdimage_set_ext_header (struct kwb_header *kwbhdr, char* name) {
-	bhr_t *mhdr = &kwbhdr->kwb_hdr;
-	extbhr_t *exthdr = &kwbhdr->kwb_exthdr;
-	FILE *fd = NULL;
-	int j;
-	char *line = NULL;
-	char * token, *saveptr1, *saveptr2;
-	size_t len = 0;
-	enum kwbimage_cmd cmd;
-
-	fname = name;
-	/* set dram register offset */
-	exthdr->dramregsoffs = (intptr_t)&exthdr->rcfg - (intptr_t)mhdr;
-
-	if ((fd = fopen (name, "r")) == 0) {
-		printf ("Error:%s - Can't open\n", fname);
-		exit (EXIT_FAILURE);
+static void *image_create_v1(size_t *imagesz, struct image_tool_params *params,
+			     int payloadsz)
+{
+	struct image_cfg_element *e, *binarye;
+	struct main_hdr_v1 *main_hdr;
+	size_t headersz;
+	void *image, *cur;
+	int hasext = 0;
+	int ret;
+
+	/*
+	 * Calculate the size of the header and the size of the
+	 * payload
+	 */
+	headersz = image_headersz_v1(params, &hasext);
+	if (headersz == 0)
+		return NULL;
+
+	image = malloc(headersz);
+	if (!image) {
+		fprintf(stderr, "Cannot allocate memory for image\n");
+		return NULL;
 	}
 
-	/* Simple kwimage.cfg file parser */
-	lineno=0;
-	while ((getline (&line, &len, fd)) > 0) {
-		lineno++;
-		token = strtok_r (line, "\r\n", &saveptr1);
-		/* drop all lines with zero tokens (= empty lines) */
-		if (token == NULL)
-			continue;
+	memset(image, 0, headersz);
+
+	cur = main_hdr = image;
+	cur += sizeof(struct main_hdr_v1);
+
+	/* Fill the main header */
+	main_hdr->blocksize    = payloadsz - headersz + sizeof(uint32_t);
+	main_hdr->headersz_lsb = headersz & 0xFFFF;
+	main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
+	main_hdr->destaddr     = params->addr;
+	main_hdr->execaddr     = params->ep;
+	main_hdr->srcaddr      = headersz;
+	main_hdr->ext          = hasext;
+	main_hdr->version      = 1;
+	e = image_find_option(IMAGE_CFG_BOOT_FROM);
+	if (e)
+		main_hdr->blockid = e->bootfrom;
+	e = image_find_option(IMAGE_CFG_NAND_BLKSZ);
+	if (e)
+		main_hdr->nandblocksize = e->nandblksz / (64 * 1024);
+	e = image_find_option(IMAGE_CFG_NAND_BADBLK_LOCATION);
+	if (e)
+		main_hdr->nandbadblklocation = e->nandbadblklocation;
+
+	binarye = image_find_option(IMAGE_CFG_BINARY);
+	if (binarye) {
+		struct opt_hdr_v1 *hdr = cur;
+		unsigned int *args;
+		size_t binhdrsz;
+		struct stat s;
+		int argi;
+		FILE *bin;
+
+		hdr->headertype = OPT_HDR_V1_BINARY_TYPE;
+
+		bin = fopen(binarye->binary.file, "r");
+		if (!bin) {
+			fprintf(stderr, "Cannot open binary file %s\n",
+				binarye->binary.file);
+			return NULL;
+		}
 
-		for (j = 0, cmd = CMD_INVALID, line = token; ; line = NULL) {
-			token = strtok_r (line, " \t", &saveptr2);
-			if (token == NULL)
-			break;
-			/* Drop all text starting with '#' as comments */
-			if (token[0] == '#')
-				break;
+		fstat(fileno(bin), &s);
 
-			/* Process rest as valid config command line */
-			switch (j) {
-			case CFG_COMMAND:
-				cmd = get_table_entry_id (kwbimage_cmds,
-						"Kwbimage command", token);
+		binhdrsz = sizeof(struct opt_hdr_v1) +
+			(binarye->binary.nargs + 1) * sizeof(unsigned int) +
+			s.st_size;
+		hdr->headersz_lsb = binhdrsz & 0xFFFF;
+		hdr->headersz_msb = (binhdrsz & 0xFFFF0000) >> 16;
 
-				if (cmd == CMD_INVALID)
-					goto INVL_CMD;
-				break;
+		cur += sizeof(struct opt_hdr_v1);
 
-			case CFG_DATA0:
-				kwbimage_check_cfgdata (token, cmd, kwbhdr);
-				break;
+		args = cur;
+		*args = binarye->binary.nargs;
+		args++;
+		for (argi = 0; argi < binarye->binary.nargs; argi++)
+			args[argi] = binarye->binary.args[argi];
 
-			case CFG_DATA1:
-				if (cmd != CMD_DATA)
-					goto INVL_CMD;
-
-				exthdr->rcfg[datacmd_cnt].rdata =
-						check_get_hexval (token);
-
-				if (datacmd_cnt > KWBIMAGE_MAX_CONFIG ) {
-					printf ("Error:%s[%d] - Found more "
-						"than max(%zd) allowed "
-						"data configurations\n",
-						fname, lineno,
-						KWBIMAGE_MAX_CONFIG);
-				exit (EXIT_FAILURE);
-				} else
-					datacmd_cnt++;
-				break;
+		cur += (binarye->binary.nargs + 1) * sizeof(unsigned int);
+
+		ret = fread(cur, s.st_size, 1, bin);
+		if (ret != 1) {
+			fprintf(stderr,
+				"Could not read binary image %s\n",
+				binarye->binary.file);
+			return NULL;
+		}
+
+		fclose(bin);
 
-			default:
-				goto INVL_CMD;
+		cur += s.st_size;
+
+		/*
+		 * For now, we don't support more than one binary
+		 * header, and no other header types are
+		 * supported. So, the binary header is necessarily the
+		 * last one
+		 */
+		*((unsigned char *)cur) = 0;
+
+		cur += sizeof(uint32_t);
+	}
+
+	/* Calculate and set the header checksum */
+	main_hdr->checksum = image_checksum8(main_hdr, headersz);
+
+	*imagesz = headersz;
+	return image;
+}
+
+static int image_create_config_parse_oneline(char *line,
+					     struct image_cfg_element *el)
+{
+	char *keyword, *saveptr;
+	char deliminiters[] = " \t";
+
+	keyword = strtok_r(line, deliminiters, &saveptr);
+	if (!strcmp(keyword, "VERSION")) {
+		char *value = strtok_r(NULL, deliminiters, &saveptr);
+		el->type = IMAGE_CFG_VERSION;
+		el->version = atoi(value);
+	} else if (!strcmp(keyword, "BOOT_FROM")) {
+		char *value = strtok_r(NULL, deliminiters, &saveptr);
+		el->type = IMAGE_CFG_BOOT_FROM;
+		el->bootfrom = image_boot_mode_id(value);
+		if (el->bootfrom < 0) {
+			fprintf(stderr,
+				"Invalid boot media '%s'\n", value);
+			return -1;
+		}
+	} else if (!strcmp(keyword, "NAND_BLKSZ")) {
+		char *value = strtok_r(NULL, deliminiters, &saveptr);
+		el->type = IMAGE_CFG_NAND_BLKSZ;
+		el->nandblksz = strtoul(value, NULL, 16);
+	} else if (!strcmp(keyword, "NAND_BADBLK_LOCATION")) {
+		char *value = strtok_r(NULL, deliminiters, &saveptr);
+		el->type = IMAGE_CFG_NAND_BADBLK_LOCATION;
+		el->nandbadblklocation =
+			strtoul(value, NULL, 16);
+	} else if (!strcmp(keyword, "NAND_ECC_MODE")) {
+		char *value = strtok_r(NULL, deliminiters, &saveptr);
+		el->type = IMAGE_CFG_NAND_ECC_MODE;
+		el->nandeccmode = image_nand_ecc_mode_id(value);
+		if (el->nandeccmode < 0) {
+			fprintf(stderr,
+				"Invalid NAND ECC mode '%s'\n", value);
+			return -1;
+		}
+	} else if (!strcmp(keyword, "NAND_PAGE_SIZE")) {
+		char *value = strtok_r(NULL, deliminiters, &saveptr);
+		el->type = IMAGE_CFG_NAND_PAGESZ;
+		el->nandpagesz = strtoul(value, NULL, 16);
+	} else if (!strcmp(keyword, "BINARY")) {
+		char *value = strtok_r(NULL, deliminiters, &saveptr);
+		int argi = 0;
+
+		el->type = IMAGE_CFG_BINARY;
+		el->binary.file = strdup(value);
+		while (1) {
+			value = strtok_r(NULL, deliminiters, &saveptr);
+			if (!value)
+				break;
+			el->binary.args[argi] = strtoul(value, NULL, 16);
+			argi++;
+			if (argi >= BINARY_MAX_ARGS) {
+				fprintf(stderr,
+					"Too many argument for binary\n");
+				return -1;
 			}
-			j++;
 		}
+		el->binary.nargs = argi;
+	} else if (!strcmp(keyword, "DATA")) {
+		char *value1 = strtok_r(NULL, deliminiters, &saveptr);
+		char *value2 = strtok_r(NULL, deliminiters, &saveptr);
+
+		if (!value1 || !value2) {
+			fprintf(stderr,
+				"Invalid number of arguments for DATA\n");
+			return -1;
+		}
+
+		el->type = IMAGE_CFG_DATA;
+		el->regdata.raddr = strtoul(value1, NULL, 16);
+		el->regdata.rdata = strtoul(value2, NULL, 16);
+	} else {
+		fprintf(stderr, "Ignoring unknown line '%s'\n", line);
 	}
-	if (line)
-		free (line);
 
-	fclose (fd);
-	return;
+	return 0;
+}
 
 /*
- * Invalid Command error reporring
- *
- * command CMD_DATA needs three strings on a line
- * whereas other commands need only two.
- *
- * if more than two/three (as per command type) are observed,
- * then error will be reported
+ * Parse the configuration file 'fcfg' into the array of configuration
+ * elements 'image_cfg', and return the number of configuration
+ * elements in 'cfgn'.
  */
-INVL_CMD:
-	printf ("Error:%s[%d] - Invalid command\n", fname, lineno);
-	exit (EXIT_FAILURE);
+static int image_create_config_parse(FILE *fcfg)
+{
+	int ret;
+	int cfgi = 0;
+
+	/* Parse the configuration file */
+	while (!feof(fcfg)) {
+		char *line;
+		char buf[256];
+
+		/* Read the current line */
+		memset(buf, 0, sizeof(buf));
+		line = fgets(buf, sizeof(buf), fcfg);
+		if (!line)
+			break;
+
+		/* Ignore useless lines */
+		if (line[0] == '\n' || line[0] == '#')
+			continue;
+
+		/* Strip final newline */
+		if (line[strlen(line) - 1] == '\n')
+			line[strlen(line) - 1] = 0;
+
+		/* Parse the current line */
+		ret = image_create_config_parse_oneline(line,
+							&image_cfg[cfgi]);
+		if (ret)
+			return ret;
+
+		cfgi++;
+
+		if (cfgi >= IMAGE_CFG_ELEMENT_MAX) {
+			fprintf(stderr,
+				"Too many configuration elements in .cfg file\n");
+			return -1;
+		}
+	}
+
+	cfgn = cfgi;
+	return 0;
+}
+
+static int image_get_version(void)
+{
+	struct image_cfg_element *e;
+
+	e = image_find_option(IMAGE_CFG_VERSION);
+	if (!e)
+		return -1;
+
+	return e->version;
+}
+
+static int image_version_file(const char *input)
+{
+	FILE *fcfg;
+	int version;
+	int ret;
+
+	fcfg = fopen(input, "r");
+	if (!fcfg) {
+		fprintf(stderr, "Could not open input file %s\n", input);
+		return -1;
+	}
+
+	image_cfg = malloc(IMAGE_CFG_ELEMENT_MAX *
+			   sizeof(struct image_cfg_element));
+	if (!image_cfg) {
+		fprintf(stderr, "Cannot allocate memory\n");
+		fclose(fcfg);
+		return -1;
+	}
+
+	memset(image_cfg, 0,
+	       IMAGE_CFG_ELEMENT_MAX * sizeof(struct image_cfg_element));
+	rewind(fcfg);
+
+	ret = image_create_config_parse(fcfg);
+	fclose(fcfg);
+	if (ret) {
+		free(image_cfg);
+		return -1;
+	}
+
+	version = image_get_version();
+	/* Fallback to version 0 is no version is provided in the cfg file */
+	if (version == -1)
+		version = 0;
+
+	free(image_cfg);
+
+	return version;
 }
 
-static void kwbimage_set_header (void *ptr, struct stat *sbuf, int ifd,
+static void kwbimage_set_header(void *ptr, struct stat *sbuf, int ifd,
 				struct image_tool_params *params)
 {
-	struct kwb_header *hdr = (struct kwb_header *)ptr;
-	bhr_t *mhdr = &hdr->kwb_hdr;
-	extbhr_t *exthdr = &hdr->kwb_exthdr;
+	FILE *fcfg;
+	void *image = NULL;
+	int version;
+	size_t headersz;
 	uint32_t checksum;
+	int ret;
 	int size;
 
-	/* Build and add image checksum header */
-	checksum = kwbimage_checksum32 ((uint32_t *)ptr, sbuf->st_size, 0);
+	fcfg = fopen(params->imagename, "r");
+	if (!fcfg) {
+		fprintf(stderr, "Could not open input file %s\n",
+			params->imagename);
+		exit(EXIT_FAILURE);
+	}
 
-	size = write (ifd, &checksum, sizeof(uint32_t));
+	image_cfg = malloc(IMAGE_CFG_ELEMENT_MAX *
+			   sizeof(struct image_cfg_element));
+	if (!image_cfg) {
+		fprintf(stderr, "Cannot allocate memory\n");
+		fclose(fcfg);
+		exit(EXIT_FAILURE);
+	}
+
+	memset(image_cfg, 0,
+	       IMAGE_CFG_ELEMENT_MAX * sizeof(struct image_cfg_element));
+	rewind(fcfg);
+
+	ret = image_create_config_parse(fcfg);
+	fclose(fcfg);
+	if (ret) {
+		free(image_cfg);
+		exit(EXIT_FAILURE);
+	}
+
+	version = image_get_version();
+	switch (version) {
+		/*
+		 * Fallback to version 0 if no version is provided in the
+		 * cfg file
+		 */
+	case -1:
+	case 0:
+		image = image_create_v0(&headersz, params, sbuf->st_size);
+		break;
+
+	case 1:
+		image = image_create_v1(&headersz, params, sbuf->st_size);
+		break;
+
+	default:
+		fprintf(stderr, "Unsupported version %d\n", version);
+		free(image_cfg);
+		exit(EXIT_FAILURE);
+	}
+
+	if (!image) {
+		fprintf(stderr, "Could not create image\n");
+		free(image_cfg);
+		exit(EXIT_FAILURE);
+	}
+
+	free(image_cfg);
+
+	/* Build and add image checksum header */
+	checksum = image_checksum32((uint32_t *)ptr, sbuf->st_size);
+	size = write(ifd, &checksum, sizeof(uint32_t));
 	if (size != sizeof(uint32_t)) {
-		printf ("Error:%s - Checksum write %d bytes %s\n",
+		fprintf(stderr, "Error:%s - Checksum write %d bytes %s\n",
 			params->cmdname, size, params->imagefile);
-		exit (EXIT_FAILURE);
+		exit(EXIT_FAILURE);
 	}
 
 	sbuf->st_size += sizeof(uint32_t);
 
-	mhdr->blocksize = sbuf->st_size - sizeof(struct kwb_header);
-	mhdr->srcaddr = sizeof(struct kwb_header);
-	mhdr->destaddr= params->addr;
-	mhdr->execaddr =params->ep;
-	mhdr->ext = 0x1; /* header extension appended */
-
-	kwdimage_set_ext_header (hdr, params->imagename);
-	/* calculate checksums */
-	mhdr->checkSum = kwbimage_checksum8 ((void *)mhdr, sizeof(bhr_t), 0);
-	exthdr->checkSum = kwbimage_checksum8 ((void *)exthdr,
-						sizeof(extbhr_t), 0);
-}
-
-static int kwbimage_verify_header (unsigned char *ptr, int image_size,
-			struct image_tool_params *params)
-{
-	struct kwb_header *hdr = (struct kwb_header *)ptr;
-	bhr_t *mhdr = &hdr->kwb_hdr;
-	extbhr_t *exthdr = &hdr->kwb_exthdr;
-	uint8_t calc_hdrcsum;
-	uint8_t calc_exthdrcsum;
-
-	calc_hdrcsum = kwbimage_checksum8 ((void *)mhdr,
-			sizeof(bhr_t) - sizeof(uint8_t), 0);
-	if (calc_hdrcsum != mhdr->checkSum)
-		return -FDT_ERR_BADSTRUCTURE;	/* mhdr csum not matched */
-
-	calc_exthdrcsum = kwbimage_checksum8 ((void *)exthdr,
-			sizeof(extbhr_t) - sizeof(uint8_t), 0);
-	if (calc_exthdrcsum != exthdr->checkSum)
-		return -FDT_ERR_BADSTRUCTURE; /* exthdr csum not matched */
+	/* Finally copy the header into the image area */
+	memcpy(ptr, image, headersz);
 
-	return 0;
+	free(image);
 }
 
-static void kwbimage_print_header (const void *ptr)
+static void kwbimage_print_header(const void *ptr)
 {
-	struct kwb_header *hdr = (struct kwb_header *) ptr;
-	bhr_t *mhdr = &hdr->kwb_hdr;
-	char *name = get_table_entry_name (kwbimage_bootops,
-				"Kwbimage boot option",
-				(int) mhdr->blockid);
-
-	printf ("Image Type:   Kirkwood Boot from %s Image\n", name);
-	printf ("Data Size:    ");
-	genimg_print_size (mhdr->blocksize - sizeof(uint32_t));
-	printf ("Load Address: %08x\n", mhdr->destaddr);
-	printf ("Entry Point:  %08x\n", mhdr->execaddr);
+	struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr;
+
+	printf("Image Type:   MVEBU Boot from %s Image\n",
+	       image_boot_mode_name(mhdr->blockid));
+	printf("Image version:%d\n", image_version((void *)ptr));
+	printf("Data Size:    ");
+	genimg_print_size(mhdr->blocksize - sizeof(uint32_t));
+	printf("Load Address: %08x\n", mhdr->destaddr);
+	printf("Entry Point:  %08x\n", mhdr->execaddr);
 }
 
-static int kwbimage_check_image_types (uint8_t type)
+static int kwbimage_check_image_types(uint8_t type)
 {
 	if (type == IH_TYPE_KWBIMAGE)
 		return EXIT_SUCCESS;
@@ -366,18 +826,93 @@ static int kwbimage_check_image_types (uint8_t type)
 		return EXIT_FAILURE;
 }
 
+static int kwbimage_verify_header(unsigned char *ptr, int image_size,
+				  struct image_tool_params *params)
+{
+	struct main_hdr_v0 *main_hdr;
+	struct ext_hdr_v0 *ext_hdr;
+	uint8_t checksum;
+
+	main_hdr = (void *)ptr;
+	checksum = image_checksum8(ptr,
+				   sizeof(struct main_hdr_v0)
+				   - sizeof(uint8_t));
+	if (checksum != main_hdr->checksum)
+		return -FDT_ERR_BADSTRUCTURE;
+
+	/* Only version 0 extended header has checksum */
+	if (image_version((void *)ptr) == 0) {
+		ext_hdr = (void *)ptr + sizeof(struct main_hdr_v0);
+		checksum = image_checksum8(ext_hdr,
+					   sizeof(struct ext_hdr_v0)
+					   - sizeof(uint8_t));
+		if (checksum != ext_hdr->checksum)
+			return -FDT_ERR_BADSTRUCTURE;
+	}
+
+	return 0;
+}
+
+static int kwbimage_generate(struct image_tool_params *params,
+			     struct image_type_params *tparams)
+{
+	int alloc_len;
+	void *hdr;
+	int version = 0;
+
+	version = image_version_file(params->imagename);
+	if (version == 0) {
+		alloc_len = sizeof(struct main_hdr_v0) +
+			sizeof(struct ext_hdr_v0);
+	} else {
+		alloc_len = image_headersz_v1(params, NULL);
+	}
+
+	hdr = malloc(alloc_len);
+	if (!hdr) {
+		fprintf(stderr, "%s: malloc return failure: %s\n",
+			params->cmdname, strerror(errno));
+		exit(EXIT_FAILURE);
+	}
+
+	memset(hdr, 0, alloc_len);
+	tparams->header_size = alloc_len;
+	tparams->hdr = hdr;
+
+	return 0;
+}
+
+/*
+ * Report Error if xflag is set in addition to default
+ */
+static int kwbimage_check_params(struct image_tool_params *params)
+{
+	if (!strlen(params->imagename)) {
+		fprintf(stderr, "Error:%s - Configuration file not specified, "
+			"it is needed for kwbimage generation\n",
+			params->cmdname);
+		return CFG_INVALID;
+	}
+
+	return (params->dflag && (params->fflag || params->lflag)) ||
+		(params->fflag && (params->dflag || params->lflag)) ||
+		(params->lflag && (params->dflag || params->fflag)) ||
+		(params->xflag) || !(strlen(params->imagename));
+}
+
 /*
  * kwbimage type parameters definition
  */
 static struct image_type_params kwbimage_params = {
-	.name = "Kirkwood Boot Image support",
-	.header_size = sizeof(struct kwb_header),
-	.hdr = (void*)&kwbimage_header,
+	.name		= "Marvell MVEBU Boot Image support",
+	.header_size	= 0,		/* no fixed header size */
+	.hdr		= NULL,
+	.vrec_header	= kwbimage_generate,
 	.check_image_type = kwbimage_check_image_types,
-	.verify_header = kwbimage_verify_header,
-	.print_header = kwbimage_print_header,
-	.set_header = kwbimage_set_header,
-	.check_params = kwbimage_check_params,
+	.verify_header	= kwbimage_verify_header,
+	.print_header	= kwbimage_print_header,
+	.set_header	= kwbimage_set_header,
+	.check_params	= kwbimage_check_params,
 };
 
 void init_kwb_image_type (void)
diff --git a/tools/kwboot.c b/tools/kwboot.c
index e773f01df3f..1368b4c948a 100644
--- a/tools/kwboot.c
+++ b/tools/kwboot.c
@@ -1,5 +1,6 @@
 /*
- * Boot a Marvell Kirkwood SoC, with Xmodem over UART0.
+ * Boot a Marvell SoC, with Xmodem over UART0.
+ *  supports Kirkwood, Dove, Armada 370, Armada XP
  *
  * (c) 2012 Daniel Stodden <daniel.stodden@gmail.com>
  *
@@ -37,9 +38,18 @@ static unsigned char kwboot_msg_boot[] = {
 	0xBB, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
 };
 
+static unsigned char kwboot_msg_debug[] = {
+	0xDD, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
+};
+
+/* Defines known to work on Kirkwood */
 #define KWBOOT_MSG_REQ_DELAY	10 /* ms */
 #define KWBOOT_MSG_RSP_TIMEO	50 /* ms */
 
+/* Defines known to work on Armada XP */
+#define KWBOOT_MSG_REQ_DELAY_AXP	1000 /* ms */
+#define KWBOOT_MSG_RSP_TIMEO_AXP	1000 /* ms */
+
 /*
  * Xmodem Transfers
  */
@@ -62,6 +72,9 @@ struct kwboot_block {
 
 static int kwboot_verbose;
 
+static int msg_req_delay = KWBOOT_MSG_REQ_DELAY;
+static int msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO;
+
 static void
 kwboot_printv(const char *fmt, ...)
 {
@@ -184,6 +197,9 @@ kwboot_tty_send(int fd, const void *buf, size_t len)
 	int rc;
 	ssize_t n;
 
+	if (!buf)
+		return 0;
+
 	rc = -1;
 
 	do {
@@ -268,7 +284,10 @@ kwboot_bootmsg(int tty, void *msg)
 	int rc;
 	char c;
 
-	kwboot_printv("Sending boot message. Please reboot the target...");
+	if (msg == NULL)
+		kwboot_printv("Please reboot the target into UART boot mode...");
+	else
+		kwboot_printv("Sending boot message. Please reboot the target...");
 
 	do {
 		rc = tcflush(tty, TCIOFLUSH);
@@ -277,11 +296,11 @@ kwboot_bootmsg(int tty, void *msg)
 
 		rc = kwboot_tty_send(tty, msg, 8);
 		if (rc) {
-			usleep(KWBOOT_MSG_REQ_DELAY * 1000);
+			usleep(msg_req_delay * 1000);
 			continue;
 		}
 
-		rc = kwboot_tty_recv(tty, &c, 1, KWBOOT_MSG_RSP_TIMEO);
+		rc = kwboot_tty_recv(tty, &c, 1, msg_rsp_timeo);
 
 		kwboot_spinner();
 
@@ -293,6 +312,37 @@ kwboot_bootmsg(int tty, void *msg)
 }
 
 static int
+kwboot_debugmsg(int tty, void *msg)
+{
+	int rc;
+
+	kwboot_printv("Sending debug message. Please reboot the target...");
+
+	do {
+		char buf[16];
+
+		rc = tcflush(tty, TCIOFLUSH);
+		if (rc)
+			break;
+
+		rc = kwboot_tty_send(tty, msg, 8);
+		if (rc) {
+			usleep(msg_req_delay * 1000);
+			continue;
+		}
+
+		rc = kwboot_tty_recv(tty, buf, 16, msg_rsp_timeo);
+
+		kwboot_spinner();
+
+	} while (rc);
+
+	kwboot_printv("\n");
+
+	return rc;
+}
+
+static int
 kwboot_xm_makeblock(struct kwboot_block *block, const void *data,
 		    size_t size, int pnum)
 {
@@ -300,6 +350,7 @@ kwboot_xm_makeblock(struct kwboot_block *block, const void *data,
 	size_t n;
 	int i;
 
+	block->soh = SOH;
 	block->pnum = pnum;
 	block->_pnum = ~block->pnum;
 
@@ -326,9 +377,15 @@ kwboot_xm_sendblock(int fd, struct kwboot_block *block)
 		if (rc)
 			break;
 
-		rc = kwboot_tty_recv(fd, &c, 1, KWBOOT_BLK_RSP_TIMEO);
-		if (rc)
-			break;
+		do {
+			rc = kwboot_tty_recv(fd, &c, 1, KWBOOT_BLK_RSP_TIMEO);
+			if (rc)
+				break;
+
+			if (c != ACK && c != NAK && c != CAN)
+				printf("%c", c);
+
+		} while (c != ACK && c != NAK && c != CAN);
 
 		if (c != ACK)
 			kwboot_progress(-1, '+');
@@ -511,7 +568,6 @@ kwboot_mmap_image(const char *path, size_t *size, int prot)
 	void *img;
 
 	rc = -1;
-	fd = -1;
 	img = NULL;
 
 	fd = open(path, O_RDONLY);
@@ -601,11 +657,16 @@ static void
 kwboot_usage(FILE *stream, char *progname)
 {
 	fprintf(stream,
-		"Usage: %s -b <image> [ -p ] [ -t ] "
-		"[-B <baud> ] <TTY>\n", progname);
+		"Usage: %s [-d | -a | -b <image> | -D <image> ] [ -t ] [-B <baud> ] <TTY>\n",
+		progname);
 	fprintf(stream, "\n");
-	fprintf(stream, "  -b <image>: boot <image>\n");
+	fprintf(stream,
+		"  -b <image>: boot <image> with preamble (Kirkwood, Armada 370/XP)\n");
 	fprintf(stream, "  -p: patch <image> to type 0x69 (uart boot)\n");
+	fprintf(stream,
+		"  -D <image>: boot <image> without preamble (Dove)\n");
+	fprintf(stream, "  -d: enter debug mode\n");
+	fprintf(stream, "  -a: use timings for Armada XP\n");
 	fprintf(stream, "\n");
 	fprintf(stream, "  -t: mini terminal\n");
 	fprintf(stream, "\n");
@@ -619,6 +680,7 @@ main(int argc, char **argv)
 	const char *ttypath, *imgpath;
 	int rv, rc, tty, term, prot, patch;
 	void *bootmsg;
+	void *debugmsg;
 	void *img;
 	size_t size;
 	speed_t speed;
@@ -626,6 +688,7 @@ main(int argc, char **argv)
 	rv = 1;
 	tty = -1;
 	bootmsg = NULL;
+	debugmsg = NULL;
 	imgpath = NULL;
 	img = NULL;
 	term = 0;
@@ -636,7 +699,7 @@ main(int argc, char **argv)
 	kwboot_verbose = isatty(STDOUT_FILENO);
 
 	do {
-		int c = getopt(argc, argv, "hb:ptB:");
+		int c = getopt(argc, argv, "hb:ptaB:dD:");
 		if (c < 0)
 			break;
 
@@ -646,6 +709,15 @@ main(int argc, char **argv)
 			imgpath = optarg;
 			break;
 
+		case 'D':
+			bootmsg = NULL;
+			imgpath = optarg;
+			break;
+
+		case 'd':
+			debugmsg = kwboot_msg_debug;
+			break;
+
 		case 'p':
 			patch = 1;
 			break;
@@ -654,6 +726,11 @@ main(int argc, char **argv)
 			term = 1;
 			break;
 
+		case 'a':
+			msg_req_delay = KWBOOT_MSG_REQ_DELAY_AXP;
+			msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO_AXP;
+			break;
+
 		case 'B':
 			speed = kwboot_tty_speed(atoi(optarg));
 			if (speed == -1)
@@ -667,7 +744,7 @@ main(int argc, char **argv)
 		}
 	} while (1);
 
-	if (!bootmsg && !term)
+	if (!bootmsg && !term && !debugmsg)
 		goto usage;
 
 	if (patch && !imgpath)
@@ -702,7 +779,13 @@ main(int argc, char **argv)
 		}
 	}
 
-	if (bootmsg) {
+	if (debugmsg) {
+		rc = kwboot_debugmsg(tty, debugmsg);
+		if (rc) {
+			perror("debugmsg");
+			goto out;
+		}
+	} else {
 		rc = kwboot_bootmsg(tty, bootmsg);
 		if (rc) {
 			perror("bootmsg");
diff --git a/tools/socfpgaimage.c b/tools/socfpgaimage.c
index 396d8a5472f..917873e7b3c 100644
--- a/tools/socfpgaimage.c
+++ b/tools/socfpgaimage.c
@@ -74,12 +74,12 @@ static uint16_t hdr_checksum(struct socfpga_header *header)
 static void build_header(uint8_t *buf, uint8_t version, uint8_t flags,
 			 uint16_t length_bytes)
 {
-	header.validation = htole32(VALIDATION_WORD);
+	header.validation = cpu_to_le32(VALIDATION_WORD);
 	header.version = version;
 	header.flags = flags;
-	header.length_u32 = htole16(length_bytes/4);
+	header.length_u32 = cpu_to_le16(length_bytes/4);
 	header.zero = 0;
-	header.checksum = htole16(hdr_checksum(&header));
+	header.checksum = cpu_to_le16(hdr_checksum(&header));
 
 	memcpy(buf, &header, sizeof(header));
 }
@@ -92,12 +92,12 @@ static int verify_header(const uint8_t *buf)
 {
 	memcpy(&header, buf, sizeof(header));
 
-	if (le32toh(header.validation) != VALIDATION_WORD)
+	if (le32_to_cpu(header.validation) != VALIDATION_WORD)
 		return -1;
-	if (le16toh(header.checksum) != hdr_checksum(&header))
+	if (le16_to_cpu(header.checksum) != hdr_checksum(&header))
 		return -1;
 
-	return le16toh(header.length_u32) * 4;
+	return le16_to_cpu(header.length_u32) * 4;
 }
 
 /* Sign the buffer and return the signed buffer size */
@@ -116,7 +116,7 @@ static int sign_buffer(uint8_t *buf,
 	/* Calculate and apply the CRC */
 	calc_crc = ~pbl_crc32(0, (char *)buf, len);
 
-	*((uint32_t *)(buf + len)) = htole32(calc_crc);
+	*((uint32_t *)(buf + len)) = cpu_to_le32(calc_crc);
 
 	if (!pad_64k)
 		return len + 4;
@@ -150,7 +150,7 @@ static int verify_buffer(const uint8_t *buf)
 
 	calc_crc = ~pbl_crc32(0, (const char *)buf, len);
 
-	buf_crc = le32toh(*((uint32_t *)(buf + len)));
+	buf_crc = le32_to_cpu(*((uint32_t *)(buf + len)));
 
 	if (buf_crc != calc_crc) {
 		fprintf(stderr, "CRC32 does not match (%08x != %08x)\n",