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-rw-r--r--arch/arm/mach-imx/cpu.c4
-rw-r--r--arch/arm/mach-imx/mx6/clock.c30
2 files changed, 18 insertions, 16 deletions
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 1017eb84f95..18205dc9849 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -25,7 +25,7 @@
#include <fsl_esdhc.h>
#endif
-#if defined(CONFIG_DISPLAY_CPUINFO)
+#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
static u32 reset_cause = -1;
static char *get_reset_cause(void)
@@ -132,7 +132,7 @@ unsigned imx_ddr_size(void)
}
#endif
-#if defined(CONFIG_DISPLAY_CPUINFO)
+#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
const char *get_imx_type(u32 imxtype)
{
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index 0e019c42622..71a9e6bca0f 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -1220,6 +1220,20 @@ void enable_thermal_clk(void)
enable_pll3();
}
+#ifdef CONFIG_MTD_NOR_FLASH
+void enable_eim_clk(unsigned char enable)
+{
+ u32 reg;
+
+ reg = __raw_readl(&imx_ccm->CCGR6);
+ if (enable)
+ reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ else
+ reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ __raw_writel(reg, &imx_ccm->CCGR6);
+}
+#endif
+
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
@@ -1262,6 +1276,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return 0;
}
+#ifndef CONFIG_SPL_BUILD
/*
* Dump some core clockes.
*/
@@ -1463,20 +1478,6 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk)
}
#endif
-#ifdef CONFIG_MTD_NOR_FLASH
-void enable_eim_clk(unsigned char enable)
-{
- u32 reg;
-
- reg = __raw_readl(&imx_ccm->CCGR6);
- if (enable)
- reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
- else
- reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
- __raw_writel(reg, &imx_ccm->CCGR6);
-}
-#endif
-
/***************************************************/
U_BOOT_CMD(
@@ -1484,3 +1485,4 @@ U_BOOT_CMD(
"display clocks",
""
);
+#endif