diff options
112 files changed, 2169 insertions, 401 deletions
@@ -227,7 +227,7 @@ config BUILD_ROM config BUILD_TARGET string "Build target special images" default "u-boot-with-spl.sfp" if ARCH_SOCFPGA - default "u-boot-spl.kwb" if ARCH_MVEBU && SPL_BUILD + default "u-boot-spl.kwb" if ARCH_MVEBU && SPL default "u-boot-elf.srec" if RCAR_GEN3 default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI default "u-boot.kwb" if KIRKWOOD diff --git a/MAINTAINERS b/MAINTAINERS index 69131e4ffa..29449ffed6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -720,7 +720,9 @@ F: configs/am335x_hs_evm_defconfig F: configs/am335x_hs_evm_uart_defconfig F: configs/am43xx_hs_evm_defconfig F: configs/am57xx_hs_evm_defconfig +F: configs/am57xx_hs_evm_usb_defconfig F: configs/dra7xx_hs_evm_defconfig +F: configs/dra7xx_hs_evm_usb_defconfig F: configs/k2hk_hs_evm_defconfig F: configs/k2e_hs_evm_defconfig F: configs/k2g_hs_evm_defconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f0edb10003..455f06cfee 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -528,6 +528,12 @@ config ARCH_BCM283X imply CMD_DM imply FAT_WRITE +config ARCH_BCM63158 + bool "Broadcom BCM63158 family" + select DM + select OF_CONTROL + imply CMD_DM + config ARCH_BCM6858 bool "Broadcom BCM6858 family" select DM @@ -1526,6 +1532,7 @@ source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" source "board/broadcom/bcm23550_w1d/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" +source "board/broadcom/bcm963158/Kconfig" source "board/broadcom/bcm968580xref/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts index 498105f25f..cdff44aca5 100644 --- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts @@ -99,6 +99,11 @@ 0 0 0 0 0 0 0xe 0xe 0xe 0xe 0xe 0xe 0 >; + cpm_pcie_reset_pins: cpm-pcie-reset-pins { + marvell,pins = < 32 >; + marvell,function = <0>; + }; + cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { marvell,pins = < 47 >; marvell,function = <0>; @@ -120,6 +125,9 @@ &cpm_pcie0 { num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&cpm_pcie_reset_pins>; + marvell,reset-gpio = <&cpm_gpio1 0 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index 7e8e2f707c..5a046d9de4 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -132,7 +132,7 @@ num-lanes = <4>; pinctrl-names = "default"; pinctrl-0 = <&cpm_pcie_reset_pins>; - marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */ + marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */ status = "okay"; }; diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi new file mode 100644 index 0000000000..6a3fbc9093 --- /dev/null +++ b/arch/arm/dts/bcm63158.dtsi @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com> + */ + +#include "skeleton64.dtsi" + +/ { + compatible = "brcm,bcm63158"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + l2: l2-cache0 { + compatible = "cache"; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0xbebc200>; + u-boot,dm-pre-reloc; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + + uart0: serial@ff812000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xff812000 0x0 0x1000>; + clock = <50000000>; + + status = "disabled"; + }; + + wdt1: watchdog@ff800480 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x0 0xff800480 0x0 0x14>; + clocks = <&periph_osc>; + }; + + wdt2: watchdog@ff8004c0 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x0 0xff8004c0 0x0 0x14>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt1>; + }; + }; +}; diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi index d78d34d213..23b80c67a6 100644 --- a/arch/arm/dts/bcm6858.dtsi +++ b/arch/arm/dts/bcm6858.dtsi @@ -81,5 +81,22 @@ status = "disabled"; }; + + wdt1: watchdog@ff802780 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x0 0xff802780 0x0 0x14>; + clocks = <&periph_osc>; + }; + + wdt2: watchdog@ff8027c0 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x0 0xff8027c0 0x0 0x14>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt1>; + }; }; }; diff --git a/arch/arm/dts/bcm963158.dts b/arch/arm/dts/bcm963158.dts new file mode 100644 index 0000000000..dc5afb5a24 --- /dev/null +++ b/arch/arm/dts/bcm963158.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com> + */ + +/dts-v1/; + +#include "bcm63158.dtsi" + +/ { + model = "Broadcom bcm963158"; + compatible = "broadcom,bcm963158", "brcm,bcm63158"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/arm/dts/exynos5250-spring.dts b/arch/arm/dts/exynos5250-spring.dts index 191e12af6a..c7553208ad 100644 --- a/arch/arm/dts/exynos5250-spring.dts +++ b/arch/arm/dts/exynos5250-spring.dts @@ -40,9 +40,46 @@ reg = <0x40000000 0x80000000>; }; + iram { + reg = <0x02020000 0x60000>; + }; + + config { + samsung,bl1-offset = <0x1400>; + samsung,bl2-offset = <0x3400>; + u-boot-memory = "/memory"; + u-boot-offset = <0x3e00000 0x100000>; + }; + flash@0 { - spl { /* spl size override */ - size = <0x8000>; + reg = <0 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + pre-boot { + label = "bl1 pre-boot"; + reg = <0 0x2000>; + read-only; + filename = "e5250.nbl1.bin"; + type = "blob exynos-bl1"; + required; + }; + + spl { + label = "bl2 spl"; + reg = <0x2000 0x8000>; + read-only; + filename = "bl2.bin"; + type = "blob exynos-bl2 boot,dtb"; + payload = "/flash/ro-boot"; + required; + }; + + ro-boot { + label = "u-boot"; + reg = <0xa000 0xb0000>; + read-only; + type = "blob boot,dtb"; + required; }; }; @@ -93,6 +130,22 @@ samsung,vbus-gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>; }; + sound { + compatible = "google,spring-audio-max98088"; + + samsung,model = "Spring-I2S-MAX98088"; + samsung,audio-codec = <&max98088>; + codec-enable-gpio = <&gpx1 7 0>; + + cpu { + sound-dai = <&i2s1 0>; + }; + + codec { + sound-dai = <&max98088 0>; + }; + }; + spi@12d30000 { spi-max-frequency = <50000000>; firmware_storage_spi: flash@0 { @@ -638,27 +691,11 @@ }; }; - max98095: soundcodec@10 { + max98088: soundcodec@10 { reg = <0x10>; - compatible = "maxim,max98095"; + compatible = "maxim,max98088"; #sound-dai-cells = <1>; }; - - sound { - compatible = "google,spring-audio-max98095"; - - samsung,model = "Spring-I2S-MAX98095"; - samsung,audio-codec = <&max98095>; - - cpu { - sound-dai = <&i2s0 0>; - }; - - codec { - sound-dai = <&max98095 0>; - }; - }; - }; #include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index 4898483e1d..70bbf66704 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -39,6 +39,10 @@ }; }; +&clk_hse { + st,digbypass; +}; + &uart4_pins_a { u-boot,dm-pre-reloc; pins1 { @@ -68,7 +72,6 @@ u-boot,dm-pre-reloc; }; -/* CLOCK init */ &rcc { st,clksrc = < CLK_MPU_PLL1P @@ -101,7 +104,7 @@ CLK_FMC_ACLK CLK_QSPI_ACLK CLK_ETH_DISABLED - CLK_SDMMC12_PLL3R + CLK_SDMMC12_PLL4P CLK_DSI_DSIPLL CLK_STGEN_HSE CLK_USBPHY_HSE @@ -110,7 +113,7 @@ CLK_SPI45_HSI CLK_SPI6_HSI CLK_I2C46_HSI - CLK_SDMMC3_PLL3R + CLK_SDMMC3_PLL4P CLK_USBO_USBPHY CLK_ADC_CKPER CLK_CEC_LSE @@ -121,17 +124,17 @@ CLK_UART35_HSI CLK_UART6_HSI CLK_UART78_HSI - CLK_SPDIF_PLL3Q + CLK_SPDIF_PLL4P CLK_FDCAN_PLL4Q CLK_SAI1_PLL3Q CLK_SAI2_PLL3Q CLK_SAI3_PLL3Q CLK_SAI4_PLL3Q - CLK_RNG1_CSI - CLK_RNG2_CSI + CLK_RNG1_LSI + CLK_RNG2_LSI CLK_LPTIM1_PCLK1 CLK_LPTIM23_PCLK3 - CLK_LPTIM45_PCLK3 + CLK_LPTIM45_LSE >; /* VCO = 1300.0 MHz => P = 650 (CPU) */ @@ -148,16 +151,16 @@ u-boot,dm-pre-reloc; }; - /* VCO = 786.4 MHz => P = 197, Q = 49, R = 98 */ + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ pll3: st,pll@2 { - cfg = < 2 97 3 15 7 PQR(1,1,1) >; - frac = < 0x9ba >; + cfg = < 1 33 1 16 36 PQR(1,1,1) >; + frac = < 0x1a04 >; u-boot,dm-pre-reloc; }; - /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */ + /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ pll4: st,pll@3 { - cfg = < 5 126 8 8 8 PQR(1,1,1) >; + cfg = < 3 98 5 7 7 PQR(1,1,1) >; u-boot,dm-pre-reloc; }; }; diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index ed04369cfa..3807770362 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -8,6 +8,8 @@ config ARCH_EXYNOS4 bool "Exynos4 SoC family" select BOARD_EARLY_INIT_F select CPU_V7A + select BLK + select DM_MMC help Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There are multiple SoCs in this family including Exynos4210, Exynos4412, @@ -24,6 +26,9 @@ config ARCH_EXYNOS5 imply USB_ETHER_ASIX imply USB_ETHER_RTL8152 imply USB_ETHER_SMSC95XX + select BLK + select DM_MMC + help Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs @@ -33,6 +38,8 @@ config ARCH_EXYNOS7 bool "Exynos7 SoC family" select ARM64 select BOARD_EARLY_INIT_F + select BLK + select DM_MMC help Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or Cortex-A53 CPU (and some in a big.LITTLE configuration). There are diff --git a/arch/arm/mach-exynos/include/mach/mmc.h b/arch/arm/mach-exynos/include/mach/mmc.h index ca4e7eda34..eece44ea1a 100644 --- a/arch/arm/mach-exynos/include/mach/mmc.h +++ b/arch/arm/mach-exynos/include/mach/mmc.h @@ -64,6 +64,4 @@ static inline int s5p_mmc_init(int index, int bus_width) return s5p_sdhci_init(base, index, bus_width); } -int exynos_mmc_init(const void *blob); - #endif diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index cc89d4a296..5909bbfa8f 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -19,33 +19,25 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) /* * It is assumed that remoteproc device 1 is the corresponding - * cortex A core which runs ATF. Make sure DT reflects the same. + * Cortex-A core which runs ATF. Make sure DT reflects the same. */ ret = rproc_dev_init(1); - if (ret) { - printf("%s: ATF failed to Initialize on rproc: ret= %d\n", - __func__, ret); - hang(); - } + if (ret) + panic("%s: ATF failed to initialize on rproc (%d)\n", __func__, + ret); ret = rproc_load(1, spl_image->entry_point, 0x200); - if (ret) { - printf("%s: ATF failed to load on rproc: ret= %d\n", - __func__, ret); - hang(); - } + if (ret) + panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret); - /* Add an extra newline to differentiate the ATF logs from SPL*/ + /* Add an extra newline to differentiate the ATF logs from SPL */ printf("Starting ATF on ARM64 core...\n\n"); ret = rproc_start(1); - if (ret) { - printf("%s: ATF failed to start on rproc: ret= %d\n", - __func__, ret); - hang(); - } + if (ret) + panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret); - debug("ATF started. Wait indefiniely\n"); + debug("ATF started. Waiting indefinitely...\n"); while (1) asm volatile("wfe"); } diff --git a/arch/arm/mach-s5pc1xx/Kconfig b/arch/arm/mach-s5pc1xx/Kconfig index 04acdaad79..8cffced551 100644 --- a/arch/arm/mach-s5pc1xx/Kconfig +++ b/arch/arm/mach-s5pc1xx/Kconfig @@ -7,6 +7,8 @@ choice config TARGET_S5P_GONI bool "S5P Goni board" select OF_CONTROL + select BLK + select DM_MMC config TARGET_SMDKC100 bool "Support smdkc100 board" diff --git a/arch/arm/mach-s5pc1xx/Makefile b/arch/arm/mach-s5pc1xx/Makefile index a4be3fcbda..ab804604d5 100644 --- a/arch/arm/mach-s5pc1xx/Makefile +++ b/arch/arm/mach-s5pc1xx/Makefile @@ -10,3 +10,4 @@ obj-y = cache.o obj-y += reset.o obj-y += clock.o +obj-y += pinmux.o diff --git a/arch/arm/mach-s5pc1xx/pinmux.c b/arch/arm/mach-s5pc1xx/pinmux.c new file mode 100644 index 0000000000..818d75164d --- /dev/null +++ b/arch/arm/mach-s5pc1xx/pinmux.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Dummy functions to keep s5p_goni building (although it won't work) + * + * Copyright 2018 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <common.h> +#include <asm/arch/pinmux.h> + +int exynos_pinmux_config(int peripheral, int flags) +{ + return 0; +} + +int pinmux_decode_periph_id(const void *blob, int node) +{ + return 0; +} diff --git a/arch/mips/dts/brcm,bcm6838.dtsi b/arch/mips/dts/brcm,bcm6838.dtsi index 77d6a8e214..b6f9559147 100644 --- a/arch/mips/dts/brcm,bcm6838.dtsi +++ b/arch/mips/dts/brcm,bcm6838.dtsi @@ -73,6 +73,23 @@ status = "disabled"; }; + wdt0: watchdog@14e002d0 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x14e002d0 0xc>; + clocks = <&periph_osc>; + }; + + wdt1: watchdog@14e002dc { + compatible = "brcm,bcm6345-wdt"; + reg = <0x14e002dc 0xc>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt0>; + }; + leds: led-controller@14e00f00 { compatible = "brcm,bcm6328-leds"; reg = <0x14e00f00 0x28>; diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c index d2e7c72242..b8ab19c0e7 100644 --- a/board/BuR/brppt1/board.c +++ b/board/BuR/brppt1/board.c @@ -106,9 +106,8 @@ void am33xx_spl_board_init(void) /* setup I2C */ enable_i2c_pin_mux(); - i2c_set_bus_num(0); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - pmicsetup(0); + + pmicsetup(0, 0); /* peripheral reset */ rc = gpio_request(64 + 29, "GPMC_WAIT1"); diff --git a/board/BuR/brxre1/board.c b/board/BuR/brxre1/board.c index 41ed28b4bc..82c53d5bc2 100644 --- a/board/BuR/brxre1/board.c +++ b/board/BuR/brxre1/board.c @@ -132,7 +132,7 @@ void am33xx_spl_board_init(void) puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n"); } - pmicsetup(0); + pmicsetup(0, 0); } const struct dpll_params *get_dpll_ddr_params(void) diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h index 5f2d0d055f..f743194c34 100644 --- a/board/BuR/common/bur_common.h +++ b/board/BuR/common/bur_common.h @@ -15,7 +15,7 @@ int load_lcdtiming(struct am335x_lcdpanel *panel); void br_summaryscreen(void); -void pmicsetup(u32 mpupll); +void pmicsetup(u32 mpupll, unsigned int bus); void enable_uart0_pin_mux(void); void enable_i2c_pin_mux(void); void enable_board_pin_mux(void); diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index f3eae5cbc1..a1f7c44abf 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -269,13 +269,14 @@ int ft_board_setup(void *blob, bd_t *bd) static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; -void pmicsetup(u32 mpupll) +void pmicsetup(u32 mpupll, unsigned int bus) { int mpu_vdd; int usb_cur_lim; - if (i2c_probe(TPS65217_CHIP_PM)) { - puts("PMIC (0x24) not found! skip further initalization.\n"); + if (power_tps65217_init(bus)) { + printf("WARN: cannot setup PMIC 0x24 @ bus #%d, not found!.\n", + bus); return; } diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c index b34ae51345..d7d1942fe6 100644 --- a/board/alliedtelesis/x530/x530.c +++ b/board/alliedtelesis/x530/x530.c @@ -57,7 +57,7 @@ static struct mv_ddr_topology_map board_topology_map = { SPEED_BIN_DDR_1866M, /* speed_bin */ MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */ MV_DDR_DIE_CAP_4GBIT, /* die capacity */ - MV_DDR_FREQ_933, /* frequency */ + MV_DDR_FREQ_SAR, /* frequency */ 0, 0, /* cas_l cas_wl */ MV_DDR_TEMP_LOW, /* temperature */ MV_DDR_TIM_2T} }, /* timing */ diff --git a/board/broadcom/bcm963158/Kconfig b/board/broadcom/bcm963158/Kconfig new file mode 100644 index 0000000000..41b6adbb80 --- /dev/null +++ b/board/broadcom/bcm963158/Kconfig @@ -0,0 +1,17 @@ +if ARCH_BCM63158 + +config SYS_VENDOR + default "broadcom" + +config SYS_BOARD + default "bcm963158" + +config SYS_CONFIG_NAME + default "broadcom_bcm963158" + +endif + +config TARGET_BCM963158 + bool "Support Broadcom bcm963158" + depends on ARCH_BCM63158 + select ARM64 diff --git a/board/broadcom/bcm963158/MAINTAINERS b/board/broadcom/bcm963158/MAINTAINERS new file mode 100644 index 0000000000..d28d971f9d --- /dev/null +++ b/board/broadcom/bcm963158/MAINTAINERS @@ -0,0 +1,6 @@ +BROADCOM BCM963158 +M: Philippe Reynes <philippe.reynes@softathome.com> +S: Maintained +F: board/broadcom/bcm963158/ +F: include/configs/broadcom_bcm963158.h +F: configs/bcm963158_ram_defconfig diff --git a/board/broadcom/bcm963158/Makefile b/board/broadcom/bcm963158/Makefile new file mode 100644 index 0000000000..0a902c9cf6 --- /dev/null +++ b/board/broadcom/bcm963158/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += bcm963158.o diff --git a/board/broadcom/bcm963158/bcm963158.c b/board/broadcom/bcm963158/bcm963158.c new file mode 100644 index 0000000000..db82cd570d --- /dev/null +++ b/board/broadcom/bcm963158/bcm963158.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com> + */ + +#include <common.h> +#include <fdtdec.h> +#include <linux/io.h> + +#ifdef CONFIG_ARM64 +#include <asm/armv8/mmu.h> + +static struct mm_region broadcom_bcm963158_mem_map[] = { + { + /* RAM */ + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 8UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* SoC */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0xff80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = broadcom_bcm963158_mem_map; +#endif + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + printf("fdtdec_setup_mem_size_base() has failed\n"); + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +int print_cpuinfo(void) +{ + return 0; +} diff --git a/board/broadcom/bcm968580xref/MAINTAINERS b/board/broadcom/bcm968580xref/MAINTAINERS index 1ecdfbc0bb..5ee0c4dd4e 100644 --- a/board/broadcom/bcm968580xref/MAINTAINERS +++ b/board/broadcom/bcm968580xref/MAINTAINERS @@ -1,6 +1,6 @@ -BROADCOM BCM968580XREF +BCM968580XREF BOARD M: Philippe Reynes <philippe.reynes@softathome.com> S: Maintained F: board/broadcom/bcm968580xref/ F: include/configs/broadcom_bcm968580xref.h -F: configs/bcm968580_ram_defconfig +F: configs/bcm968580xref_ram_defconfig diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 6fd26a3a91..96228a86a1 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -249,56 +249,16 @@ int board_eth_init(bd_t *bis) return 0; } -#ifdef CONFIG_MMC -static int init_mmc(void) -{ -#ifdef CONFIG_MMC_SDHCI - return exynos_mmc_init(gd->fdt_blob); -#else - return 0; -#endif -} - -static int init_dwmmc(void) -{ -#ifdef CONFIG_MMC_DW - return exynos_dwmmc_init(gd->fdt_blob); -#else - return 0; -#endif -} - -int board_mmc_init(bd_t *bis) -{ - int ret; - - if (get_boot_mode() == BOOT_MODE_SD) { - ret = init_mmc(); - ret |= init_dwmmc(); - } else { - ret = init_dwmmc(); - ret |= init_mmc(); - } - - if (ret) - debug("mmc init failed\n"); - - return ret; -} -#endif - #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard(void) { - const char *board_info; + if (IS_ENABLED(CONFIG_BOARD_TYPES)) { + const char *board_info = get_board_type(); + + if (board_info) + printf("Type: %s\n", board_info); + } - board_info = fdt_getprop(gd->fdt_blob, 0, "model", NULL); - printf("Board: %s\n", board_info ? board_info : "unknown"); -#ifdef CONFIG_BOARD_TYPES - board_info = get_board_type(); - if (board_info) - printf("Type: %s\n", board_info); -#endif return 0; } #endif diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index c183965b92..87eb381345 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -34,37 +34,8 @@ DECLARE_GLOBAL_DATA_PTR; -static void board_enable_audio_codec(void) -{ - int node, ret; - struct gpio_desc en_gpio; - - node = fdtdec_next_compatible(gd->fdt_blob, 0, - COMPAT_SAMSUNG_EXYNOS5_SOUND); - if (node <= 0) - return; - - ret = gpio_request_by_name_nodev(offset_to_ofnode(node), - "codec-enable-gpio", 0, &en_gpio, - GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); - if (ret == -FDT_ERR_NOTFOUND) - return; - - /* Turn on the GPIO which connects to the codec's "enable" line. */ - gpio_set_pull(gpio_get_number(&en_gpio), S5P_GPIO_PULL_NONE); - -#ifdef CONFIG_SOUND_MAX98095 - /* Enable MAX98095 Codec */ - gpio_request(EXYNOS5_GPIO_X17, "max98095_enable"); - gpio_direction_output(EXYNOS5_GPIO_X17, 1); - gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE); -#endif -} - int exynos_init(void) { - board_enable_audio_codec(); - return 0; } diff --git a/cmd/sata.c b/cmd/sata.c index 6d62ba8f74..a73cc54bd3 100644 --- a/cmd/sata.c +++ b/cmd/sata.c @@ -60,6 +60,10 @@ int sata_probe(int devnum) printf("Cannot probe SATA device %d (err=%d)\n", devnum, rc); return CMD_RET_FAILURE; } + if (!dev) { + printf("No SATA device found!\n"); + return CMD_RET_FAILURE; + } rc = sata_scan(dev); if (rc) { printf("Cannot scan SATA device %d (err=%d)\n", devnum, rc); diff --git a/common/Kconfig b/common/Kconfig index 8f9d2959ba..0a14bdedaa 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -656,6 +656,14 @@ config BOUNCE_BUFFER A second possible use of bounce buffers is their ability to provide aligned buffers for DMA operations. +config BOARD_TYPES + bool "Call get_board_type() to get and display the board type" + help + If this option is enabled, checkboard() will call get_board_type() + to get a string containing the board type and this will be + displayed immediately after the model is shown on the console + early in boot. + menu "Start-up hooks" config ARCH_EARLY_INIT_R diff --git a/common/board_r.c b/common/board_r.c index 5f3d27aa9f..472987d5d5 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -633,10 +633,7 @@ static int run_main_loop(void) } /* - * Over time we hope to remove these functions with code fragments and - * stub functions, and instead call the relevant function directly. - * - * We also hope to remove most of the driver-related init and do it if/when + * We hope to remove most of the driver-related init and do it if/when * the driver is later used. * * TODO: perhaps reset the watchdog in the initcall function after each call? diff --git a/common/image-fdt.c b/common/image-fdt.c index 5988808f18..94089b2215 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -268,6 +268,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, ulong load, load_end; ulong image_start, image_data, image_end; #endif + ulong img_addr; ulong fdt_addr; char *fdt_blob = NULL; void *buf; @@ -283,6 +284,9 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, *of_flat_tree = NULL; *of_size = 0; + img_addr = simple_strtoul(argv[0], NULL, 16); + buf = map_sysmem(img_addr, 0); + if (argc > 2) select = argv[2]; if (select || genimg_has_config(images)) { @@ -453,6 +457,23 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, debug("## No Flattened Device Tree\n"); goto no_fdt; } +#ifdef CONFIG_ANDROID_BOOT_IMAGE + } else if (genimg_get_format(buf) == IMAGE_FORMAT_ANDROID) { + struct andr_img_hdr *hdr = buf; + ulong fdt_data, fdt_len; + + if (android_image_get_second(hdr, &fdt_data, &fdt_len) != 0) + goto no_fdt; + + fdt_blob = (char *)fdt_data; + if (fdt_check_header(fdt_blob) != 0) + goto no_fdt; + + if (fdt_totalsize(fdt_blob) != fdt_len) + goto error; + + debug("## Using FDT found in Android image second area\n"); +#endif } else { debug("## No Flattened Device Tree\n"); goto no_fdt; diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index f9805d24f3..7a0fd927b8 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_SPI_LOAD=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_PMIC is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15" diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig new file mode 100644 index 0000000000..6e4580ae39 --- /dev/null +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_TI_COMMON_CMD_OPTIONS=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_OMAP54XX=y +CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000 +CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000 +CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 +CONFIG_ISW_ENTRY_ADDR=0x40306d50 +CONFIG_TARGET_AM57XX_EVM=y +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ARMV7_LPAE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=beagle_x15board" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_MISC_INIT_R is not set +CONFIG_VERSION_VARIABLE=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_DMA_SUPPORT=y +# CONFIG_SPL_NAND_SUPPORT is not set +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +CONFIG_SPL_YMODEM_SUPPORT=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_PMIC is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15" +CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +# CONFIG_BLK is not set +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 +CONFIG_FASTBOOT_USB_DEV=1 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_OMAP_HS=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y +CONFIG_PHY=y +CONFIG_PIPE3_PHY=y +CONFIG_OMAP_USB2_PHY=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_PALMAS=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PALMAS=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_TI_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index d2ec2dd7fe..49498b13b6 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -33,6 +33,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index b77ecc1781..6ef6616554 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -8,6 +8,7 @@ CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS3,115200n8" +CONFIG_BOARD_TYPES=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AXS# " diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index f42b694ca7..2208bdb9be 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -8,6 +8,7 @@ CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS3,115200n8" +CONFIG_BOARD_TYPES=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AXS# " diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig new file mode 100644 index 0000000000..9083f1dc9f --- /dev/null +++ b/configs/bcm963158_ram_defconfig @@ -0,0 +1,42 @@ +CONFIG_ARM=y +# CONFIG_ARM64_SUPPORT_AARCH32 is not set +CONFIG_ARCH_BCM63158=y +CONFIG_SYS_TEXT_BASE=0x10000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 +CONFIG_TARGET_BCM963158=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y +CONFIG_FIT_VERBOSE=y +CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTEFI_SELFTEST=y +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_CACHE=y +CONFIG_DOS_PARTITION=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_DEFAULT_DEVICE_TREE="bcm963158" +# CONFIG_NET is not set +CONFIG_BLK=y +CONFIG_CLK=y +# CONFIG_MMC is not set +CONFIG_SPECIFY_CONSOLE_INDEX=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_CONS_INDEX=0 +CONFIG_DM_SERIAL=y +CONFIG_SERIAL_SEARCH_ALL=y +CONFIG_PL01X_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_WDT_BCM6345=y +CONFIG_REGEX=y +# CONFIG_GENERATE_SMBIOS_TABLE is not set diff --git a/configs/bcm968380gerg_ram_defconfig b/configs/bcm968380gerg_ram_defconfig index 848d898ddf..61661bd756 100644 --- a/configs/bcm968380gerg_ram_defconfig +++ b/configs/bcm968380gerg_ram_defconfig @@ -44,4 +44,6 @@ CONFIG_RESET_BCM6345=y # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_DM_SERIAL=y CONFIG_BCM6345_SERIAL=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_WDT_BCM6345=y CONFIG_LZO=y diff --git a/configs/bcm968580_ram_defconfig b/configs/bcm968580xref_ram_defconfig index 56e0a56028..1f433a3d39 100644 --- a/configs/bcm968580_ram_defconfig +++ b/configs/bcm968580xref_ram_defconfig @@ -18,7 +18,6 @@ CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_DOS_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="bcm968580xref" # CONFIG_NET is not set CONFIG_BLK=y @@ -31,5 +30,7 @@ CONFIG_DM_SERIAL=y CONFIG_SERIAL_SEARCH_ALL=y CONFIG_BCM6345_SERIAL=y CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_WDT_BCM6345=y CONFIG_REGEX=y # CONFIG_GENERATE_SMBIOS_TABLE is not set diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 083b5f7e5f..f2d8220126 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -71,7 +71,6 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_MISC=y CONFIG_DM_MMC=y diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig index 1cfd5fc709..275727d11f 100644 --- a/configs/brppt1_nand_defconfig +++ b/configs/brppt1_nand_defconfig @@ -73,7 +73,6 @@ CONFIG_BLK=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_MISC=y # CONFIG_MMC is not set diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index 37373967df..668c4c22c2 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -76,7 +76,6 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_MISC=y CONFIG_DM_MMC=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index f98ee470a9..3cf7659496 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_SECURE_DEVICE=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 CONFIG_OMAP54XX=y CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000 @@ -37,13 +37,18 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm" +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000 +CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y CONFIG_DWC_AHCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y @@ -62,6 +67,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig new file mode 100644 index 0000000000..378b3d791c --- /dev/null +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -0,0 +1,113 @@ +CONFIG_ARM=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_TI_COMMON_CMD_OPTIONS=y +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_OMAP54XX=y +CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000 +CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000 +CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 +CONFIG_ISW_ENTRY_ADDR=0x40306d50 +CONFIG_TARGET_DRA7XX_EVM=y +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ARMV7_LPAE=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_MISC_INIT_R is not set +CONFIG_VERSION_VARIABLE=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_DMA_SUPPORT=y +# CONFIG_SPL_NAND_SUPPORT is not set +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +CONFIG_SPL_YMODEM_SUPPORT=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" +CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm" +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000 +CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_DWC_AHCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_DM_GPIO=y +CONFIG_PCF8575_GPIO=y +CONFIG_DM_I2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_OMAP_HS=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y +CONFIG_SPL_PHY=y +CONFIG_PIPE3_PHY=y +CONFIG_OMAP_USB2_PHY=y +CONFIG_PMIC_PALMAS=y +CONFIG_PMIC_LP873X=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_REGULATOR_PALMAS=y +CONFIG_DM_REGULATOR_LP873X=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_TI_QSPI=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index 11796e5bdf..f6f05b2948 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x43E00000 CONFIG_ARCH_EXYNOS5=y +CONFIG_BOARD_TYPES=y CONFIG_IDENT_STRING=" for ODROID-XU3/XU4/HC1/HC2" CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=8 diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index cdb033ba78..184bb62c1c 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x43e00000 CONFIG_ARCH_EXYNOS4=y CONFIG_TARGET_ODROID=y +CONFIG_BOARD_TYPES=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=8 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/spring_defconfig b/configs/spring_defconfig index 5c5569acd2..c0084289d9 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -62,6 +62,7 @@ CONFIG_DEBUG_UART_S5P=y CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y +CONFIG_SOUND_MAX98088=y CONFIG_SOUND_MAX98095=y CONFIG_SOUND_WM8994=y CONFIG_EXYNOS_SPI=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 304688e56f..d20b2ab350 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_PROMPT="STM32MP> " # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_MEMINFO=y CONFIG_CMD_ADC=y +CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/doc/README.ti-secure b/doc/README.ti-secure index 4b5380c0f3..76950253ac 100644 --- a/doc/README.ti-secure +++ b/doc/README.ti-secure @@ -108,7 +108,8 @@ Booting of U-Boot SPL Invoking the script for DRA7xx/AM57xx Secure Devices ==================================================== - create-boot-image.sh <IMAGE_TYPE> <INPUT_FILE> <OUTPUT_FILE> + create-boot-image.sh \ + <IMAGE_TYPE> <INPUT_FILE> <OUTPUT_FILE> <SPL_LOAD_ADDR> <IMAGE_TYPE> is a value that specifies the type of the image to generate OR the action the image generation tool will take. Valid @@ -116,7 +117,6 @@ Booting of U-Boot SPL X-LOADER - Generates an image for NOR or QSPI boot modes MLO - Generates an image for SD/MMC/eMMC boot modes ULO - Generates an image for USB/UART peripheral boot modes - Note: ULO is not yet used by the u-boot build process <INPUT_FILE> is the full path and filename of the public world boot loader binary file (for this platform, this is always u-boot-spl.bin). @@ -130,9 +130,13 @@ Booting of U-Boot SPL the device ROM bootloader requires for loading from the FAT partition of an SD card (same as on non-secure devices) + u-boot-spl_HS_ULO - boot image for USB/UART peripheral boot modes u-boot-spl_HS_X-LOADER - boot image for all other flash memories including QSPI and NOR flash + <SPL_LOAD_ADDR> is the address at which SOC ROM should load the + <INPUT_FILE> + Invoking the script for Keystone2 Secure Devices ============================================= diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt index 6a9397e105..ffcf8cd31d 100644 --- a/doc/device-tree-bindings/clock/st,stm32mp1.txt +++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt @@ -132,15 +132,15 @@ Optional Properties: frac = < 0x810 >; }; st,pll@1 { - cfg = < 1 43 1 0 0 PQR(0,1,1)>; - csg = <10 20 1>; + cfg = < 1 43 1 0 0 PQR(0,1,1) >; + csg = < 10 20 1 >; }; st,pll@2 { - cfg = < 2 85 3 13 3 0>; - csg = <10 20 SSCG_MODE_CENTER_SPREAD>; + cfg = < 2 85 3 13 3 0 >; + csg = < 10 20 SSCG_MODE_CENTER_SPREAD >; }; st,pll@3 { - cfg = < 2 78 4 7 9 3>; + cfg = < 2 78 4 7 9 3 >; }; st,pkcs = < CLK_STGEN_HSE diff --git a/doc/driver-model/of-plat.txt b/doc/driver-model/of-plat.txt index 732bc34f06..0109ec56c3 100644 --- a/doc/driver-model/of-plat.txt +++ b/doc/driver-model/of-plat.txt @@ -64,17 +64,24 @@ strictly necessary. Notable problems include: normally also supports device tree it must use #ifdef to separate out this code, since the structures are only available in SPL. + - Correct relations between nodes are not implemented. This means that + parent/child relations (like bus device iteration) do not work yet. + Some phandles (those that are recognised as such) are converted into + a pointer to platform data. This pointer can potentially be used to + access the referenced device (by searching for the pointer value). + This feature is not yet implemented, however. + How it works ------------ -The feature is enabled by CONFIG SPL_OF_PLATDATA. This is only available -in SPL and should be tested with: +The feature is enabled by CONFIG OF_PLATDATA. This is only available in +SPL/TPL and should be tested with: - #if CONFIG_IS_ENABLED(SPL_OF_PLATDATA) + #if CONFIG_IS_ENABLED(OF_PLATDATA) A new tool called 'dtoc' converts a device tree file either into a set of -struct declarations, one for each compatible node, or a set of +struct declarations, one for each compatible node, and a set of U_BOOT_DEVICE() declarations along with the actual platform data for each device. As an example, consider this MMC node: @@ -156,6 +163,13 @@ This avoids the code overhead of converting the device tree data to platform data in the driver. The ofdata_to_platdata() method should therefore do nothing in such a driver. +Note that for the platform data to be matched with a driver, the 'name' +property of the U_BOOT_DEVICE() declaration has to match a driver declared +via U_BOOT_DRIVER(). This effectively means that a U_BOOT_DRIVER() with a +'name' corresponding to the devicetree 'compatible' string (after converting +it to a valid name for C) is needed, so a dedicated driver is required for +each 'compatible' string. + Where a node has multiple compatible strings, a #define is used to make them equivalent, e.g.: @@ -165,8 +179,8 @@ equivalent, e.g.: Converting of-platdata to a useful form --------------------------------------- -Of course it would be possible use the of-platdata directly in your driver -whenever configuration information is required. However this meands that the +Of course it would be possible to use the of-platdata directly in your driver +whenever configuration information is required. However this means that the driver will not be able to support device tree, since the of-platdata structure is not available when device tree is used. It would make no sense to use this structure if device tree were available, since the structure has @@ -282,11 +296,6 @@ prevents them being used inadvertently. All usage must be bracketed with The dt-platdata.c file contains the device declarations and is is built in spl/dt-platdata.c. -Some phandles (thsoe that are recognised as such) are converted into -points to platform data. This pointer can potentially be used to access the -referenced device (by searching for the pointer value). This feature is not -yet implemented, however. - The beginnings of a libfdt Python module are provided. So far this only implements a subset of the features. diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index b7c5d34fe0..aebc6f0a34 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -165,6 +165,7 @@ /* used for ALL PLLNCR registers */ #define RCC_PLLNCR_PLLON BIT(0) #define RCC_PLLNCR_PLLRDY BIT(1) +#define RCC_PLLNCR_SSCG_CTRL BIT(2) #define RCC_PLLNCR_DIVPEN BIT(4) #define RCC_PLLNCR_DIVQEN BIT(5) #define RCC_PLLNCR_DIVREN BIT(6) @@ -241,7 +242,6 @@ enum stm32mp1_parent_id { _LSI, _LSE, _I2S_CKIN, - _USB_PHY_48, NB_OSC, /* other parent source */ @@ -273,6 +273,7 @@ enum stm32mp1_parent_id { _CK_MPU, _CK_MCU, _DSI_PHY, + _USB_PHY_48, _PARENT_NB, _UNKNOWN_ID = 0xff, }; @@ -536,6 +537,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), @@ -665,8 +667,8 @@ static const u8 stm32mp1_axi_div[8] = { 1, 2, 3, 4, 4, 4, 4, 4 }; -#ifdef DEBUG -static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = { +static const __maybe_unused +char * const stm32mp1_clk_parent_name[_PARENT_NB] = { [_HSI] = "HSI", [_HSE] = "HSE", [_CSI] = "CSI", @@ -704,7 +706,8 @@ static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = { [_DSI_PHY] = "DSI_PHY_PLL", }; -static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { +static const __maybe_unused +char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { [_I2C12_SEL] = "I2C12", [_I2C35_SEL] = "I2C35", [_I2C46_SEL] = "I2C46", @@ -723,7 +726,6 @@ static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { [_DSI_SEL] = "DSI", [_ADC12_SEL] = "ADC12", }; -#endif static const struct stm32mp1_clk_data stm32mp1_data = { .gate = stm32mp1_clk_gate, @@ -1079,7 +1081,7 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) break; /* other */ case _USB_PHY_48: - clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48); + clock = 48000000; break; case _DSI_PHY: { @@ -1179,10 +1181,7 @@ static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset, static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on) { - if (enable) - setbits_le32(rcc + RCC_OCENSETR, mask_on); - else - setbits_le32(rcc + RCC_OCENCLRR, mask_on); + writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); } static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset, @@ -1253,20 +1252,20 @@ static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable) static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css) { if (digbyp) - setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_DIGBYP); + writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR); if (bypass || digbyp) - setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP); + writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR); stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON); stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY); if (css) - setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON); + writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR); } static void stm32mp1_csi_set(fdt_addr_t rcc, int enable) { - stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION); + stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION); stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY); } @@ -1321,7 +1320,10 @@ static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id) { const struct stm32mp1_clk_pll *pll = priv->data->pll; - writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr); + clrsetbits_le32(priv->base + pll[pll_id].pllxcr, + RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | + RCC_PLLNCR_DIVREN, + RCC_PLLNCR_PLLON); } static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output) @@ -1440,6 +1442,8 @@ static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg) RCC_PLLNCSGR_SSCG_MODE_MASK); writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr); + + setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL); } static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc) @@ -1471,10 +1475,15 @@ static void stgen_config(struct stm32mp1_clk_priv *priv) rate = stm32mp1_clk_get(priv, p); if (cntfid0 != rate) { + u64 counter; + pr_debug("System Generic Counter (STGEN) update\n"); clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); - writel(0x0, stgenc + STGENC_CNTCVL); - writel(0x0, stgenc + STGENC_CNTCVU); + counter = (u64)readl(stgenc + STGENC_CNTCVL); + counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32; + counter = lldiv(counter * (u64)rate, cntfid0); + writel((u32)counter, stgenc + STGENC_CNTCVL); + writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU); writel(rate, stgenc + STGENC_CNTFID0); setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); @@ -1859,7 +1868,7 @@ static void stm32mp1_osc_init(struct udevice *dev) [_HSE] = "clk-hse", [_CSI] = "clk-csi", [_I2S_CKIN] = "i2s_ckin", - [_USB_PHY_48] = "ck_usbo_48m"}; + }; for (i = 0; i < NB_OSC; i++) { stm32mp1_osc_clk_init(name[i], priv, i); @@ -1867,6 +1876,54 @@ static void stm32mp1_osc_init(struct udevice *dev) } } +static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv) +{ + char buf[32]; + int i, s, p; + + printf("Clocks:\n"); + for (i = 0; i < _PARENT_NB; i++) { + printf("- %s : %s MHz\n", + stm32mp1_clk_parent_name[i], + strmhz(buf, stm32mp1_clk_get(priv, i))); + } + printf("Source Clocks:\n"); + for (i = 0; i < _PARENT_SEL_NB; i++) { + p = (readl(priv->base + priv->data->sel[i].offset) >> + priv->data->sel[i].src) & priv->data->sel[i].msk; + if (p < priv->data->sel[i].nb_parent) { + s = priv->data->sel[i].parent[p]; + printf("- %s(%d) => parent %s(%d)\n", + stm32mp1_clk_parent_sel_name[i], i, + stm32mp1_clk_parent_name[s], s); + } else { + printf("- %s(%d) => parent index %d is invalid\n", + stm32mp1_clk_parent_sel_name[i], i, p); + } + } +} + +#ifdef CONFIG_CMD_CLK +int soc_clk_dump(void) +{ + struct udevice *dev; + struct stm32mp1_clk_priv *priv; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(stm32mp1_clock), + &dev); + if (ret) + return ret; + + priv = dev_get_priv(dev); + + stm32mp1_clk_dump(priv); + + return 0; +} +#endif + static int stm32mp1_clk_probe(struct udevice *dev) { int result = 0; @@ -1890,6 +1947,33 @@ static int stm32mp1_clk_probe(struct udevice *dev) result = stm32mp1_clktree(dev); #endif +#ifndef CONFIG_SPL_BUILD +#if defined(DEBUG) + /* display debug information for probe after relocation */ + if (gd->flags & GD_FLG_RELOC) + stm32mp1_clk_dump(priv); +#endif + +#if defined(CONFIG_DISPLAY_CPUINFO) + if (gd->flags & GD_FLG_RELOC) { + char buf[32]; + + printf("Clocks:\n"); + printf("- MPU : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _CK_MPU))); + printf("- MCU : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU))); + printf("- AXI : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _ACLK))); + printf("- PER : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _CK_PER))); + /* DDRPHYC father */ + printf("- DDR : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _PLL2_R))); + } +#endif /* CONFIG_DISPLAY_CPUINFO */ +#endif + return result; } diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index a622f07941..fc3157de39 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -225,7 +225,7 @@ int uclass_find_first_device(enum uclass_id id, struct udevice **devp) if (ret) return ret; if (list_empty(&uc->dev_head)) - return 0; + return -ENODEV; *devp = list_first_entry(&uc->dev_head, struct udevice, uclass_node); diff --git a/drivers/misc/misc-uclass.c b/drivers/misc/misc-uclass.c index f240cda5c0..55381edc98 100644 --- a/drivers/misc/misc-uclass.c +++ b/drivers/misc/misc-uclass.c @@ -68,4 +68,7 @@ int misc_set_enabled(struct udevice *dev, bool val) UCLASS_DRIVER(misc) = { .id = UCLASS_MISC, .name = "misc", +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .post_bind = dm_scan_fdt_dev, +#endif }; diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 84d157ff40..b04345a1e1 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -724,7 +724,8 @@ static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) return err; } -int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) +static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value, + bool send_status) { struct mmc_cmd cmd; int timeout = 1000; @@ -740,19 +741,29 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) while (retries > 0) { ret = mmc_send_cmd(mmc, &cmd, NULL); - /* Waiting for the ready status */ - if (!ret) { - ret = mmc_send_status(mmc, timeout); - return ret; + if (ret) { + retries--; + continue; + } + + if (!send_status) { + mdelay(50); + return 0; } - retries--; + /* Waiting for the ready status */ + return mmc_send_status(mmc, timeout); } return ret; } +int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) +{ + return __mmc_switch(mmc, set, index, value, true); +} + #if !CONFIG_IS_ENABLED(MMC_TINY) static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode, bool hsdowngrade) @@ -784,8 +795,9 @@ static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode, default: return -EINVAL; } - err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, - speed_bits); + + err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, + speed_bits, !hsdowngrade); if (err) return err; diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 5cb97eb02a..826a39fad7 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -47,6 +47,7 @@ #endif #include <dm.h> #include <power/regulator.h> +#include <thermal.h> DECLARE_GLOBAL_DATA_PTR; @@ -470,21 +471,21 @@ static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV) return 0; /* Disable PBIAS */ - ret = regulator_set_enable(priv->pbias_supply, false); - if (ret && ret != -ENOSYS) + ret = regulator_set_enable_if_allowed(priv->pbias_supply, false); + if (ret) return ret; /* Turn off IO voltage */ - ret = regulator_set_enable(mmc->vqmmc_supply, false); - if (ret && ret != -ENOSYS) + ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false); + if (ret) return ret; /* Program a new IO voltage value */ ret = regulator_set_value(mmc->vqmmc_supply, uV); if (ret) return ret; /* Turn on IO voltage */ - ret = regulator_set_enable(mmc->vqmmc_supply, true); - if (ret && ret != -ENOSYS) + ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true); + if (ret) return ret; /* Program PBIAS voltage*/ @@ -492,8 +493,8 @@ static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV) if (ret && ret != -ENOSYS) return ret; /* Enable PBIAS */ - ret = regulator_set_enable(priv->pbias_supply, true); - if (ret && ret != -ENOSYS) + ret = regulator_set_enable_if_allowed(priv->pbias_supply, true); + if (ret) return ret; return 0; @@ -622,6 +623,10 @@ static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) u32 phase_delay = 0; u32 start_window = 0, max_window = 0; u32 length = 0, max_len = 0; + bool single_point_failure = false; + struct udevice *thermal_dev; + int temperature; + int i; mmc_base = priv->base_addr; val = readl(&mmc_base->capa2); @@ -632,9 +637,25 @@ static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50)))) return 0; + ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev); + if (ret) { + printf("Couldn't get thermal device for tuning\n"); + return ret; + } + ret = thermal_get_temp(thermal_dev, &temperature); + if (ret) { + printf("Couldn't get temperature for tuning\n"); + return ret; + } val = readl(&mmc_base->dll); val |= DLL_SWT; writel(val, &mmc_base->dll); + + /* + * Stage 1: Search for a maximum pass window ignoring any + * any single point failures. If the tuning value ends up + * near it, move away from it in stage 2 below + */ while (phase_delay <= MAX_PHASE_DELAY) { omap_hsmmc_set_dll(mmc, phase_delay); @@ -643,10 +664,16 @@ static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) if (cur_match) { if (prev_match) { length++; + } else if (single_point_failure) { + /* ignore single point failure */ + length++; + single_point_failure = false; } else { start_window = phase_delay; length = 1; } + } else { + single_point_failure = prev_match; } if (length > max_len) { @@ -668,8 +695,71 @@ static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) ret = -EIO; goto tuning_error; } + /* + * Assign tuning value as a ratio of maximum pass window based + * on temperature + */ + if (temperature < -20000) + phase_delay = min(max_window + 4 * max_len - 24, + max_window + + DIV_ROUND_UP(13 * max_len, 16) * 4); + else if (temperature < 20000) + phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4; + else if (temperature < 40000) + phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4; + else if (temperature < 70000) + phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4; + else if (temperature < 90000) + phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4; + else if (temperature < 120000) + phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4; + else + phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4; + + /* + * Stage 2: Search for a single point failure near the chosen tuning + * value in two steps. First in the +3 to +10 range and then in the + * +2 to -10 range. If found, move away from it in the appropriate + * direction by the appropriate amount depending on the temperature. + */ + for (i = 3; i <= 10; i++) { + omap_hsmmc_set_dll(mmc, phase_delay + i); + if (mmc_send_tuning(mmc, opcode, NULL)) { + if (temperature < 10000) + phase_delay += i + 6; + else if (temperature < 20000) + phase_delay += i - 12; + else if (temperature < 70000) + phase_delay += i - 8; + else if (temperature < 90000) + phase_delay += i - 6; + else + phase_delay += i - 6; + + goto single_failure_found; + } + } + + for (i = 2; i >= -10; i--) { + omap_hsmmc_set_dll(mmc, phase_delay + i); + if (mmc_send_tuning(mmc, opcode, NULL)) { + if (temperature < 10000) + phase_delay += i + 12; + else if (temperature < 20000) + phase_delay += i + 8; + else if (temperature < 70000) + phase_delay += i + 8; + else if (temperature < 90000) + phase_delay += i + 10; + else + phase_delay += i + 12; + + goto single_failure_found; + } + } + +single_failure_found: - phase_delay = max_window + 4 * ((3 * max_len) >> 2); omap_hsmmc_set_dll(mmc, phase_delay); mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 733b6d62f5..a556acd5cb 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -462,6 +462,16 @@ static void renesas_sdhi_filter_caps(struct udevice *dev) priv->nrtaps = 4; else priv->nrtaps = 8; + + /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */ + if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && + (rmobile_get_cpu_rev_integer() <= 1)) || + ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && + (rmobile_get_cpu_rev_integer() == 1) && + (rmobile_get_cpu_rev_fraction() == 0))) + priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD; + else + priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2; } static int renesas_sdhi_probe(struct udevice *dev) diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 591a3bce08..9dd0b865eb 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -118,9 +118,6 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width) return s5p_sdhci_core_init(host); } -#if CONFIG_IS_ENABLED(OF_CONTROL) -struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS]; - static int do_sdhci_init(struct sdhci_host *host) { int dev_id, flag, ret; @@ -191,53 +188,6 @@ static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) return 0; } -static int process_nodes(const void *blob, int node_list[], int count) -{ - struct sdhci_host *host; - int i, node, ret; - int failed = 0; - - debug("%s: count = %d\n", __func__, count); - - /* build sdhci_host[] for each controller */ - for (i = 0; i < count; i++) { - node = node_list[i]; - if (node <= 0) - continue; - - host = &sdhci_host[i]; - - ret = sdhci_get_config(blob, node, host); - if (ret) { - printf("%s: failed to decode dev %d (%d)\n", __func__, i, ret); - failed++; - continue; - } - - ret = do_sdhci_init(host); - if (ret && ret != -ENODEV) { - printf("%s: failed to initialize dev %d (%d)\n", __func__, i, ret); - failed++; - } - } - - /* we only consider it an error when all nodes fail */ - return (failed == count ? -1 : 0); -} - -int exynos_mmc_init(const void *blob) -{ - int count; - int node_list[SDHCI_MAX_HOSTS]; - - count = fdtdec_find_aliases_for_id(blob, "mmc", - COMPAT_SAMSUNG_EXYNOS_MMC, node_list, - SDHCI_MAX_HOSTS); - - return process_nodes(blob, node_list, count); -} -#endif - #ifdef CONFIG_DM_MMC static int s5p_sdhci_probe(struct udevice *dev) { diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 201492001f..2421915a07 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -347,12 +347,10 @@ static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) /* * The DMA READ completion flag position differs on Socionext * and Renesas SoCs. It is bit 20 on Socionext SoCs and using - * bit 17 is a hardware bug and forbidden. It is bit 17 on - * Renesas SoCs and bit 20 does not work on them. + * bit 17 is a hardware bug and forbidden. It is either bit 17 + * or bit 20 on Renesas SoCs, depending on SoC. */ - poll_flag = (priv->caps & TMIO_SD_CAP_RCAR) ? - TMIO_SD_DMA_INFO1_END_RD : - TMIO_SD_DMA_INFO1_END_RD2; + poll_flag = priv->read_poll_flag; tmp |= TMIO_SD_DMA_MODE_DIR_RD; } else { buf = (void *)data->src; @@ -369,6 +367,9 @@ static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks); + if (poll_flag == TMIO_SD_DMA_INFO1_END_RD) + udelay(1); + __dma_unmap_single(dma_addr, len, dir); return ret; diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h index 192026ce3e..58ce3d65b0 100644 --- a/drivers/mmc/tmio-common.h +++ b/drivers/mmc/tmio-common.h @@ -119,6 +119,7 @@ struct tmio_sd_priv { void __iomem *regbase; unsigned int version; u32 caps; + u32 read_poll_flag; #define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */ #define TMIO_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */ #define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index 6539880ab5..8f89bda233 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -47,6 +47,7 @@ static int uniphier_sd_probe(struct udevice *dev) struct tmio_sd_priv *priv = dev_get_priv(dev); priv->clk_get_rate = uniphier_sd_clk_get_rate; + priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2; #ifndef CONFIG_SPL_BUILD int ret; diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 8081005c27..95fb41966f 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -489,7 +489,9 @@ static int pcie_dw_mvebu_probe(struct udevice *dev) * using this GPIO. */ if (dm_gpio_is_valid(&reset_gpio)) { - dm_gpio_set_value(&reset_gpio, 1); + dm_gpio_set_value(&reset_gpio, 1); /* assert */ + mdelay(200); + dm_gpio_set_value(&reset_gpio, 0); /* de-assert */ mdelay(200); } #else diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 39e46279d5..6f355b969a 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -113,11 +113,22 @@ int regulator_set_enable(struct udevice *dev, bool enable) uc_pdata = dev_get_uclass_platdata(dev); if (!enable && uc_pdata->always_on) - return 0; + return -EACCES; return ops->set_enable(dev, enable); } +int regulator_set_enable_if_allowed(struct udevice *dev, bool enable) +{ + int ret; + + ret = regulator_set_enable(dev, enable); + if (ret == -ENOSYS || ret == -EACCES) + return 0; + + return ret; +} + int regulator_get_mode(struct udevice *dev) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 12512f6578..2a5f256184 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -363,9 +363,7 @@ U_BOOT_DRIVER(serial_pl01x) = { .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata), .probe = pl01x_serial_probe, .ops = &pl01x_serial_ops, -#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, -#endif .priv_auto_alloc_size = sizeof(struct pl01x_priv), }; diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig index 22e379681d..40f4f7598a 100644 --- a/drivers/sound/Kconfig +++ b/drivers/sound/Kconfig @@ -32,7 +32,7 @@ config I2S_ROCKCHIP config I2S_SAMSUNG bool "Enable I2C support for Samsung SoCs" - depends on SOUND + depends on I2S help Samsung Exynos SoCs support an I2S interface for sending audio data to an audio codec. This option enables support for this, @@ -40,9 +40,17 @@ config I2S_SAMSUNG option provides an implementation for sound_init() and sound_play(). +config SOUND_MAX98088 + bool "Support Maxim max98088 audio codec" + depends on I2S + help + Enable the max98088 audio codec. This is connected via I2S for + audio data and I2C for codec control. At present it only works + with the Samsung I2S driver. + config SOUND_MAX98090 bool "Support Maxim max98090 audio codec" - depends on I2S_SAMSUNG + depends on I2S help Enable the max98090 audio codec. This is connected via I2S for audio data and I2C for codec control. At present it only works @@ -50,7 +58,7 @@ config SOUND_MAX98090 config SOUND_MAX98095 bool "Support Maxim max98095 audio codec" - depends on I2S_SAMSUNG + depends on I2S help Enable the max98095 audio codec. This is connected via I2S for audio data and I2C for codec control. At present it only works diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile index d0bf51bab6..170e06ad53 100644 --- a/drivers/sound/Makefile +++ b/drivers/sound/Makefile @@ -12,5 +12,6 @@ obj-$(CONFIG_SOUND_SANDBOX) += sandbox.o obj-$(CONFIG_I2S_ROCKCHIP) += rockchip_i2s.o rockchip_sound.o obj-$(CONFIG_I2S_SAMSUNG) += samsung_sound.o obj-$(CONFIG_SOUND_WM8994) += wm8994.o +obj-$(CONFIG_SOUND_MAX98088) += max98088.o maxim_codec.o obj-$(CONFIG_SOUND_MAX98090) += max98090.o maxim_codec.o obj-$(CONFIG_SOUND_MAX98095) += max98095.o maxim_codec.o diff --git a/drivers/sound/max98088.c b/drivers/sound/max98088.c new file mode 100644 index 0000000000..332254d5aa --- /dev/null +++ b/drivers/sound/max98088.c @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * max98088.c -- MAX98088 ALSA SoC Audio driver + * + * Copyright 2010 Maxim Integrated Products + * + * Modified for U-Boot by Chih-Chung Chang (chihchung@chromium.org), + * following the changes made in max98095.c + */ + +#include <common.h> +#include <audio_codec.h> +#include <div64.h> +#include <dm.h> +#include <i2c.h> +#include <i2s.h> +#include <sound.h> +#include <asm/gpio.h> +#include "maxim_codec.h" +#include "max98088.h" + +/* codec mclk clock divider coefficients. Index 0 is reserved. */ +static const int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, + 44100, 48000, 88200, 96000}; + +/* + * codec mclk clock divider coefficients based on sampling rate + * + * @param rate sampling rate + * @param value address of indexvalue to be stored + * + * @return 0 for success or negative error code. + */ +static int rate_value(int rate, u8 *value) +{ + int i; + + for (i = 1; i < ARRAY_SIZE(rate_table); i++) { + if (rate_table[i] >= rate) { + *value = i; + return 0; + } + } + *value = 1; + + return -EINVAL; +} + +/* + * Sets hw params for max98088 + * + * @priv: max98088 information pointer + * @rate: Sampling rate + * @bits_per_sample: Bits per sample + * + * @return -EIO for error, 0 for success. + */ +int max98088_hw_params(struct maxim_priv *priv, unsigned int rate, + unsigned int bits_per_sample) +{ + int error; + u8 regval; + + switch (bits_per_sample) { + case 16: + error = maxim_bic_or(priv, M98088_REG_DAI1_FORMAT, + M98088_DAI_WS, 0); + break; + case 24: + error = maxim_bic_or(priv, M98088_REG_DAI1_FORMAT, + M98088_DAI_WS, M98088_DAI_WS); + break; + default: + debug("%s: Illegal bits per sample %d.\n", + __func__, bits_per_sample); + return -EINVAL; + } + + error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, M98088_SHDNRUN, 0); + + if (rate_value(rate, ®val)) { + debug("%s: Failed to set sample rate to %d.\n", + __func__, rate); + return -EIO; + } + + error |= maxim_bic_or(priv, M98088_REG_DAI1_CLKMODE, + M98088_CLKMODE_MASK, regval << 4); + priv->rate = rate; + + /* Update sample rate mode */ + if (rate < 50000) + error |= maxim_bic_or(priv, M98088_REG_DAI1_FILTERS, + M98088_DAI_DHF, 0); + else + error |= maxim_bic_or(priv, M98088_REG_DAI1_FILTERS, + M98088_DAI_DHF, M98088_DAI_DHF); + + error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, M98088_SHDNRUN, + M98088_SHDNRUN); + + if (error < 0) { + debug("%s: Error setting hardware params.\n", __func__); + return -EIO; + } + priv->rate = rate; + + return 0; +} + +/* + * Configures Audio interface system clock for the given frequency + * + * @priv: max98088 information + * @freq: Sampling frequency in Hz + * + * @return -EIO for error, 0 for success. + */ +int max98088_set_sysclk(struct maxim_priv *priv, unsigned int freq) +{ + int error = 0; + u8 pwr; + + /* Requested clock frequency is already setup */ + if (freq == priv->sysclk) + return 0; + + /* + * Setup clocks for slave mode, and using the PLL + * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) + * 0x02 (when master clk is 20MHz to 30MHz).. + */ + if (freq >= 10000000 && freq < 20000000) { + error = maxim_i2c_write(priv, M98088_REG_SYS_CLK, 0x10); + } else if ((freq >= 20000000) && (freq < 30000000)) { + error = maxim_i2c_write(priv, M98088_REG_SYS_CLK, 0x20); + } else { + debug("%s: Invalid master clock frequency\n", __func__); + return -EIO; + } + + error |= maxim_i2c_read(priv, M98088_REG_PWR_SYS, &pwr); + if (pwr & M98088_SHDNRUN) { + error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, + M98088_SHDNRUN, 0); + error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, + M98088_SHDNRUN, M98088_SHDNRUN); + } + + debug("%s: Clock at %uHz\n", __func__, freq); + if (error < 0) + return -EIO; + + priv->sysclk = freq; + + return 0; +} + +/* + * Sets Max98090 I2S format + * + * @priv: max98088 information + * @fmt: i2S format - supports a subset of the options defined in i2s.h. + * + * @return -EIO for error, 0 for success. + */ +int max98088_set_fmt(struct maxim_priv *priv, int fmt) +{ + u8 reg15val; + u8 reg14val = 0; + int error = 0; + + if (fmt == priv->fmt) + return 0; + + priv->fmt = fmt; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + /* Slave mode PLL */ + error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLKCFG_HI, + 0x80); + error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLKCFG_LO, + 0x00); + break; + case SND_SOC_DAIFMT_CBM_CFM: + /* Set to master mode */ + reg14val |= M98088_DAI_MAS; + break; + case SND_SOC_DAIFMT_CBS_CFM: + case SND_SOC_DAIFMT_CBM_CFS: + default: + debug("%s: Clock mode unsupported\n", __func__); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + reg14val |= M98088_DAI_DLY; + break; + case SND_SOC_DAIFMT_LEFT_J: + break; + default: + debug("%s: Unrecognized format.\n", __func__); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_NB_IF: + reg14val |= M98088_DAI_WCI; + break; + case SND_SOC_DAIFMT_IB_NF: + reg14val |= M98088_DAI_BCI; + break; + case SND_SOC_DAIFMT_IB_IF: + reg14val |= M98088_DAI_BCI | M98088_DAI_WCI; + break; + default: + debug("%s: Unrecognized inversion settings.\n", __func__); + return -EINVAL; + } + + error |= maxim_bic_or(priv, M98088_REG_DAI1_FORMAT, + M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI | + M98088_DAI_WCI, reg14val); + reg15val = M98088_DAI_BSEL64; + error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLOCK, reg15val); + + if (error < 0) { + debug("%s: Error setting i2s format.\n", __func__); + return -EIO; + } + + return 0; +} + +/* + * max98088_reset() - reset the audio codec + * + * @priv: max98088 information + * @return -EIO for error, 0 for success. + */ +static int max98088_reset(struct maxim_priv *priv) +{ + int ret, i; + u8 val; + + /* + * Reset to hardware default for registers, as there is not a soft + * reset hardware control register. + */ + for (i = M98088_REG_IRQ_ENABLE; i <= M98088_REG_PWR_SYS; i++) { + switch (i) { + case M98088_REG_BIAS_CNTL: + val = 0xf0; + break; + case M98088_REG_DAC_BIAS2: + val = 0x0f; + break; + default: + val = 0; + } + ret = maxim_i2c_write(priv, i, val); + if (ret < 0) { + debug("%s: Failed to reset: %d\n", __func__, ret); + return ret; + } + } + + return 0; +} + +/** + * max98088_device_init() - Initialise max98088 codec device + * + * @priv: max98088 information + * + * @return -EIO for error, 0 for success. + */ +static int max98088_device_init(struct maxim_priv *priv) +{ + unsigned char id; + int error = 0; + + /* reset the codec, the DSP core, and disable all interrupts */ + error = max98088_reset(priv); + if (error != 0) { + debug("Reset\n"); + return error; + } + + /* initialize private data */ + priv->sysclk = -1U; + priv->rate = -1U; + priv->fmt = -1U; + + error = maxim_i2c_read(priv, M98088_REG_REV_ID, &id); + if (error < 0) { + debug("%s: Failure reading hardware revision: %d\n", + __func__, id); + return -EIO; + } + debug("%s: Hardware revision: %d\n", __func__, id); + + return 0; +} + +static int max98088_setup_interface(struct maxim_priv *priv) +{ + int error; + + /* Reading interrupt status to clear them */ + error = maxim_i2c_write(priv, M98088_REG_PWR_SYS, M98088_PWRSV); + error |= maxim_i2c_write(priv, M98088_REG_IRQ_ENABLE, 0x00); + + /* + * initialize registers to hardware default configuring audio + * interface2 to DAI1 + */ + error |= maxim_i2c_write(priv, M98088_REG_MIX_DAC, + M98088_DAI1L_TO_DACL | M98088_DAI1R_TO_DACR); + error |= maxim_i2c_write(priv, M98088_REG_BIAS_CNTL, 0xF0); + error |= maxim_i2c_write(priv, M98088_REG_DAC_BIAS2, 0x0F); + error |= maxim_i2c_write(priv, M98088_REG_DAI1_IOCFG, + M98088_S2NORMAL | M98088_SDATA); + + /* + * route DACL and DACR output to headphone and speakers + * Ordering: DACL, DACR, DACL, DACR + */ + error |= maxim_i2c_write(priv, M98088_REG_MIX_SPK_LEFT, 1); + error |= maxim_i2c_write(priv, M98088_REG_MIX_SPK_RIGHT, 1); + error |= maxim_i2c_write(priv, M98088_REG_MIX_HP_LEFT, 1); + error |= maxim_i2c_write(priv, M98088_REG_MIX_HP_RIGHT, 1); + + /* set volume: -12db */ + error |= maxim_i2c_write(priv, M98088_REG_LVL_SPK_L, 0x0f); + error |= maxim_i2c_write(priv, M98088_REG_LVL_SPK_R, 0x0f); + + /* set volume: -22db */ + error |= maxim_i2c_write(priv, M98088_REG_LVL_HP_L, 0x0d); + error |= maxim_i2c_write(priv, M98088_REG_LVL_HP_R, 0x0d); + + /* power enable */ + error |= maxim_i2c_write(priv, M98088_REG_PWR_EN_OUT, + M98088_HPLEN | M98088_HPREN | M98088_SPLEN | + M98088_SPREN | M98088_DALEN | M98088_DAREN); + if (error < 0) + return -EIO; + + return 0; +} + +static int max98088_do_init(struct maxim_priv *priv, int sampling_rate, + int mclk_freq, int bits_per_sample) +{ + int ret = 0; + + ret = max98088_setup_interface(priv); + if (ret < 0) { + debug("%s: max98088 setup interface failed\n", __func__); + return ret; + } + + ret = max98088_set_sysclk(priv, mclk_freq); + if (ret < 0) { + debug("%s: max98088 codec set sys clock failed\n", __func__); + return ret; + } + + ret = max98088_hw_params(priv, sampling_rate, bits_per_sample); + + if (ret == 0) { + ret = max98088_set_fmt(priv, SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS); + } + + return ret; +} + +static int max98088_set_params(struct udevice *dev, int interface, int rate, + int mclk_freq, int bits_per_sample, + uint channels) +{ + struct maxim_priv *priv = dev_get_priv(dev); + + return max98088_do_init(priv, rate, mclk_freq, bits_per_sample); +} + +static int max98088_probe(struct udevice *dev) +{ + struct maxim_priv *priv = dev_get_priv(dev); + int ret; + + priv->dev = dev; + ret = max98088_device_init(priv); + if (ret < 0) { + debug("%s: max98088 codec chip init failed\n", __func__); + return ret; + } + + return 0; +} + +static const struct audio_codec_ops max98088_ops = { + .set_params = max98088_set_params, +}; + +static const struct udevice_id max98088_ids[] = { + { .compatible = "maxim,max98088" }, + { } +}; + +U_BOOT_DRIVER(max98088) = { + .name = "max98088", + .id = UCLASS_AUDIO_CODEC, + .of_match = max98088_ids, + .probe = max98088_probe, + .ops = &max98088_ops, + .priv_auto_alloc_size = sizeof(struct maxim_priv), +}; diff --git a/drivers/sound/max98088.h b/drivers/sound/max98088.h new file mode 100644 index 0000000000..127d2bda30 --- /dev/null +++ b/drivers/sound/max98088.h @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * max98088.h -- MAX98088 ALSA SoC Audio driver + * + * Copyright 2010 Maxim Integrated Products + */ + +#ifndef _MAX98088_H +#define _MAX98088_H + +/* MAX98088 Registers Definition */ +#define M98088_REG_IRQ_STATUS 0x00 +#define M98088_REG_MIC_STATUS 0x01 +#define M98088_REG_JACK_STAUS 0x02 +#define M98088_REG_BATTERY_VOLTAGE 0x03 +#define M98088_REG_IRQ_ENABLE 0x0f +#define M98088_REG_SYS_CLK 0X10 +#define M98088_REG_DAI1_CLKMODE 0x11 +#define M98088_REG_DAI1_CLKCFG_HI 0x12 +#define M98088_REG_DAI1_CLKCFG_LO 0x13 +#define M98088_REG_DAI1_FORMAT 0x14 +#define M98088_REG_DAI1_CLOCK 0x15 +#define M98088_REG_DAI1_IOCFG 0x16 +#define M98088_REG_DAI1_TDM 0X17 +#define M98088_REG_DAI1_FILTERS 0x18 +#define M98088_REG_DAI2_CLKMODE 0x19 +#define M98088_REG_DAI2_CLKCFG_HI 0x1a +#define M98088_REG_DAI2_CLKCFG_LO 0x1b +#define M98088_REG_DAI2_FORMAT 0x1c +#define M98088_REG_DAI2_CLOCK 0x1d +#define M98088_REG_DAI2_IOCFG 0x1e +#define M98088_REG_DAI2_TDM 0X1f +#define M98088_REG_DAI2_FILTERS 0x20 +#define M98088_REG_SRC 0X21 +#define M98088_REG_MIX_DAC 0X22 +#define M98088_REG_MIX_ADC_LEFT 0x23 +#define M98088_REG_MIX_ADC_RIGHT 0x24 +#define M98088_REG_MIX_HP_LEFT 0x25 +#define M98088_REG_MIX_HP_RIGHT 0x26 +#define M98088_REG_MIX_HP_CNTL 0x27 +#define M98088_REG_MIX_REC_LEFT 0x28 +#define M98088_REG_MIX_REC_RIGHT 0x29 +#define M98088_REG_MIC_REC_CNTL 0x2a +#define M98088_REG_MIX_SPK_LEFT 0x2b +#define M98088_REG_MIX_SPK_RIGHT 0x2c +#define M98088_REG_MIX_SPK_CNTL 0x2d +#define M98088_REG_LVL_SIDETONE 0x2e +#define M98088_REG_LVL_DAI1_PLAY 0x2f +#define M98088_REG_LVL_DAI1_PLAY_EQ 0x30 +#define M98088_REG_LVL_DAI2_PLAY 0x31 +#define M98088_REG_LVL_DAI2_PLAY_EQ 0x32 +#define M98088_REG_LVL_ADC_L 0X33 +#define M98088_REG_LVL_ADC_R 0X34 +#define M98088_REG_LVL_MIC1 0X35 +#define M98088_REG_LVL_MIC2 0X36 +#define M98088_REG_LVL_INA 0X37 +#define M98088_REG_LVL_INB 0X38 +#define M98088_REG_LVL_HP_L 0X39 +#define M98088_REG_LVL_HP_R 0X3a +#define M98088_REG_LVL_REC_L 0X3b +#define M98088_REG_LVL_REC_R 0X3c +#define M98088_REG_LVL_SPK_L 0X3d +#define M98088_REG_LVL_SPK_R 0X3e +#define M98088_REG_MICAGC_CFG 0x3f +#define M98088_REG_MICAGC_THRESH 0x40 +#define M98088_REG_SPKDHP 0X41 +#define M98088_REG_SPKDHP_THRESH 0x42 +#define M98088_REG_SPKALC_COMP 0x43 +#define M98088_REG_PWRLMT_CFG 0x44 +#define M98088_REG_PWRLMT_TIME 0x45 +#define M98088_REG_THDLMT_CFG 0x46 +#define M98088_REG_CFG_AUDIO_IN 0x47 +#define M98088_REG_CFG_MIC 0X48 +#define M98088_REG_CFG_LEVEL 0X49 +#define M98088_REG_CFG_BYPASS 0x4a +#define M98088_REG_CFG_JACKDET 0x4b +#define M98088_REG_PWR_EN_IN 0X4c +#define M98088_REG_PWR_EN_OUT 0x4d +#define M98088_REG_BIAS_CNTL 0X4e +#define M98088_REG_DAC_BIAS1 0X4f +#define M98088_REG_DAC_BIAS2 0X50 +#define M98088_REG_PWR_SYS 0X51 +#define M98088_REG_DAI1_EQ_BASE 0x52 +#define M98088_REG_DAI2_EQ_BASE 0x84 +#define M98088_REG_DAI1_BIQUAD_BASE 0xb6 +#define M98088_REG_DAI2_BIQUAD_BASE 0xc0 +#define M98088_REG_REV_ID 0xff + +#define M98088_REG_CNT (0xff + 1) + +/* MAX98088 Registers Bit Fields */ + +/* M98088_REG_11_DAI1_CLKMODE, M98088_REG_19_DAI2_CLKMODE */ +#define M98088_CLKMODE_MASK 0xFF + +/* M98088_REG_14_DAI1_FORMAT, M98088_REG_1C_DAI2_FORMAT */ +#define M98088_DAI_MAS BIT(7) +#define M98088_DAI_WCI BIT(6) +#define M98088_DAI_BCI BIT(5) +#define M98088_DAI_DLY BIT(4) +#define M98088_DAI_TDM BIT(2) +#define M98088_DAI_FSW BIT(1) +#define M98088_DAI_WS BIT(0) + +/* M98088_REG_15_DAI1_CLOCK, M98088_REG_1D_DAI2_CLOCK */ +#define M98088_DAI_BSEL64 BIT(0) +#define M98088_DAI_OSR64 BIT(6) + +/* M98088_REG_16_DAI1_IOCFG, M98088_REG_1E_DAI2_IOCFG */ +#define M98088_S1NORMAL BIT(6) +#define M98088_S2NORMAL (2 << 6) +#define M98088_SDATA (3 << 0) + +/* M98088_REG_18_DAI1_FILTERS, M98088_REG_20_DAI2_FILTERS */ +#define M98088_DAI_DHF BIT(3) + +/* M98088_REG_22_MIX_DAC */ +#define M98088_DAI1L_TO_DACL BIT(7) +#define M98088_DAI1R_TO_DACL BIT(6) +#define M98088_DAI2L_TO_DACL BIT(5) +#define M98088_DAI2R_TO_DACL BIT(4) +#define M98088_DAI1L_TO_DACR BIT(3) +#define M98088_DAI1R_TO_DACR BIT(2) +#define M98088_DAI2L_TO_DACR BIT(1) +#define M98088_DAI2R_TO_DACR BIT(0) + +/* M98088_REG_2A_MIC_REC_CNTL */ +#define M98088_REC_LINEMODE BIT(7) +#define M98088_REC_LINEMODE_MASK BIT(7) + +/* M98088_REG_2D_MIX_SPK_CNTL */ +#define M98088_MIX_SPKR_GAIN_MASK (3 << 2) +#define M98088_MIX_SPKR_GAIN_SHIFT 2 +#define M98088_MIX_SPKL_GAIN_MASK (3 << 0) +#define M98088_MIX_SPKL_GAIN_SHIFT 0 + +/* M98088_REG_2F_LVL_DAI1_PLAY, M98088_REG_31_LVL_DAI2_PLAY */ +#define M98088_DAI_MUTE BIT(7) +#define M98088_DAI_MUTE_MASK BIT(7) +#define M98088_DAI_VOICE_GAIN_MASK (3 << 4) +#define M98088_DAI_ATTENUATION_MASK (0xf << 0) +#define M98088_DAI_ATTENUATION_SHIFT 0 + +/* M98088_REG_35_LVL_MIC1, M98088_REG_36_LVL_MIC2 */ +#define M98088_MICPRE_MASK (3 << 5) +#define M98088_MICPRE_SHIFT 5 + +/* M98088_REG_3A_LVL_HP_R */ +#define M98088_HP_MUTE BIT(7) + +/* M98088_REG_3C_LVL_REC_R */ +#define M98088_REC_MUTE BIT(7) + +/* M98088_REG_3E_LVL_SPK_R */ +#define M98088_SP_MUTE BIT(7) + +/* M98088_REG_48_CFG_MIC */ +#define M98088_EXTMIC_MASK (3 << 0) +#define M98088_DIGMIC_L BIT(5) +#define M98088_DIGMIC_R BIT(4) + +/* M98088_REG_49_CFG_LEVEL */ +#define M98088_VSEN BIT(6) +#define M98088_ZDEN BIT(5) +#define M98088_EQ2EN BIT(1) +#define M98088_EQ1EN BIT(0) + +/* M98088_REG_4C_PWR_EN_IN */ +#define M98088_INAEN BIT(7) +#define M98088_INBEN BIT(6) +#define M98088_MBEN BIT(3) +#define M98088_ADLEN BIT(1) +#define M98088_ADREN BIT(0) + +/* M98088_REG_4D_PWR_EN_OUT */ +#define M98088_HPLEN BIT(7) +#define M98088_HPREN BIT(6) +#define M98088_HPEN (BIT(7) | BIT(6)) +#define M98088_SPLEN BIT(5) +#define M98088_SPREN BIT(4) +#define M98088_RECEN BIT(3) +#define M98088_DALEN BIT(1) +#define M98088_DAREN BIT(0) + +/* M98088_REG_51_PWR_SYS */ +#define M98088_SHDNRUN BIT(7) +#define M98088_PERFMODE BIT(3) +#define M98088_HPPLYBACK BIT(2) +#define M98088_PWRSV8K BIT(1) +#define M98088_PWRSV BIT(0) + +#endif diff --git a/drivers/sound/max98090.c b/drivers/sound/max98090.c index 346ff5ffbe..5505c35166 100644 --- a/drivers/sound/max98090.c +++ b/drivers/sound/max98090.c @@ -13,10 +13,6 @@ #include <i2s.h> #include <sound.h> #include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/clk.h> -#include <asm/arch/cpu.h> -#include <asm/arch/power.h> #include "maxim_codec.h" #include "max98090.h" @@ -240,9 +236,6 @@ int max98090_device_init(struct maxim_priv *priv) unsigned char id; int error = 0; - /* Enable codec clock */ - set_xclkout(); - /* reset the codec, the DSP core, and disable all interrupts */ error = max98090_reset(priv); if (error != 0) { diff --git a/drivers/sound/max98095.c b/drivers/sound/max98095.c index 99c0e996b4..9e08e96670 100644 --- a/drivers/sound/max98095.c +++ b/drivers/sound/max98095.c @@ -15,10 +15,6 @@ #include <i2c.h> #include <sound.h> #include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/clk.h> -#include <asm/arch/cpu.h> -#include <asm/arch/power.h> #include "i2s.h" #include "max98095.h" @@ -306,9 +302,6 @@ static int max98095_device_init(struct maxim_priv *priv) unsigned char id; int ret; - /* Enable codec clock */ - set_xclkout(); - /* reset the codec, the DSP core, and disable all interrupts */ ret = max98095_reset(priv); if (ret != 0) { diff --git a/drivers/sound/maxim_codec.c b/drivers/sound/maxim_codec.c index dcaf081988..5480dce108 100644 --- a/drivers/sound/maxim_codec.c +++ b/drivers/sound/maxim_codec.c @@ -12,9 +12,6 @@ #include <sound.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clk.h> -#include <asm/arch/cpu.h> -#include <asm/arch/power.h> #include "maxim_codec.h" /* diff --git a/drivers/sound/samsung-i2s.c b/drivers/sound/samsung-i2s.c index c19e08e7e3..104584073a 100644 --- a/drivers/sound/samsung-i2s.c +++ b/drivers/sound/samsung-i2s.c @@ -24,7 +24,7 @@ /* * Sets the frame size for I2S LR clock * - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * @param rfs Frame Size */ static void i2s_set_lr_framesize(struct i2s_reg *i2s_reg, unsigned int rfs) @@ -54,7 +54,7 @@ static void i2s_set_lr_framesize(struct i2s_reg *i2s_reg, unsigned int rfs) /* * Sets the i2s transfer control * - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * @param on 1 enable tx , 0 disable tx transfer */ static void i2s_txctrl(struct i2s_reg *i2s_reg, int on) @@ -77,7 +77,7 @@ static void i2s_txctrl(struct i2s_reg *i2s_reg, int on) /* * set the bit clock frame size (in multiples of LRCLK) * - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * @param bfs bit Frame Size */ static void i2s_set_bitclk_framesize(struct i2s_reg *i2s_reg, unsigned bfs) @@ -108,7 +108,7 @@ static void i2s_set_bitclk_framesize(struct i2s_reg *i2s_reg, unsigned bfs) /* * flushes the i2stx fifo * - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * @param flush Tx fifo flush command (0x00 - do not flush * 0x80 - flush tx fifo) */ @@ -122,7 +122,7 @@ static void i2s_fifo(struct i2s_reg *i2s_reg, unsigned int flush) /* * Set System Clock direction * - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * @param dir Clock direction * * @return int value 0 for success, -1 in case of error @@ -145,7 +145,7 @@ static int i2s_set_sysclk_dir(struct i2s_reg *i2s_reg, int dir) * Sets I2S Clcok format * * @param fmt i2s clock properties - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * * @return int value 0 for success, -1 in case of error */ @@ -222,7 +222,7 @@ static int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt) * Sets the sample width in bits * * @param blc samplewidth (size of sample in bits) - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * * @return int value 0 for success, -1 in case of error */ @@ -294,7 +294,7 @@ int i2s_transfer_tx_data(struct i2s_uc_priv *pi2s_tx, void *data, return 0; } -int i2s_tx_init(struct i2s_uc_priv *pi2s_tx) +static int i2s_tx_init(struct i2s_uc_priv *pi2s_tx) { int ret; struct i2s_reg *i2s_reg = (struct i2s_reg *)pi2s_tx->base_address; diff --git a/drivers/sound/samsung_sound.c b/drivers/sound/samsung_sound.c index 1d711c8732..b6952675bd 100644 --- a/drivers/sound/samsung_sound.c +++ b/drivers/sound/samsung_sound.c @@ -10,6 +10,7 @@ #include <i2s.h> #include <sound.h> #include <asm/gpio.h> +#include <asm/arch/power.h> static int samsung_sound_setup(struct udevice *dev) { @@ -79,6 +80,9 @@ static int samsung_sound_probe(struct udevice *dev) debug("Probed sound '%s' with codec '%s' and i2s '%s'\n", dev->name, uc_priv->codec->name, uc_priv->i2s->name); + /* Enable codec clock */ + set_xclkout(); + return 0; } @@ -89,7 +93,7 @@ static const struct sound_ops samsung_sound_ops = { static const struct udevice_id samsung_sound_ids[] = { { .compatible = "google,snow-audio-max98095" }, - { .compatible = "google,spring-audio-max98095" }, + { .compatible = "google,spring-audio-max98088" }, { .compatible = "samsung,smdk5420-audio-wm8994" }, { .compatible = "google,peach-audio-max98090" }, { } diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 10fd3039aa..115fc4551f 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -88,7 +88,7 @@ config WDT_ASPEED config WDT_BCM6345 bool "BCM6345 watchdog timer support" - depends on WDT && ARCH_BMIPS + depends on WDT && (ARCH_BMIPS || ARCH_BCM6858 || ARCH_BCM63158) help Select this to enable watchdog timer for BCM6345 SoCs. The watchdog timer is stopped when initialized. diff --git a/drivers/watchdog/bcm6345_wdt.c b/drivers/watchdog/bcm6345_wdt.c index e1bd73dfd4..44f5662038 100644 --- a/drivers/watchdog/bcm6345_wdt.c +++ b/drivers/watchdog/bcm6345_wdt.c @@ -32,8 +32,8 @@ static int bcm6345_wdt_reset(struct udevice *dev) { struct bcm6345_wdt_priv *priv = dev_get_priv(dev); - writel_be(WDT_CTL_START1_MASK, priv->regs + WDT_CTL_REG); - writel_be(WDT_CTL_START2_MASK, priv->regs + WDT_CTL_REG); + writel(WDT_CTL_START1_MASK, priv->regs + WDT_CTL_REG); + writel(WDT_CTL_START2_MASK, priv->regs + WDT_CTL_REG); return 0; } @@ -50,7 +50,7 @@ static int bcm6345_wdt_start(struct udevice *dev, u64 timeout, ulong flags) timeout = WDT_VAL_MAX; } - writel_be(timeout, priv->regs + WDT_VAL_REG); + writel(timeout, priv->regs + WDT_VAL_REG); return bcm6345_wdt_reset(dev); } @@ -64,8 +64,8 @@ static int bcm6345_wdt_stop(struct udevice *dev) { struct bcm6345_wdt_priv *priv = dev_get_priv(dev); - writel_be(WDT_CTL_STOP1_MASK, priv->regs + WDT_CTL_REG); - writel_be(WDT_CTL_STOP2_MASK, priv->regs + WDT_CTL_REG); + writel(WDT_CTL_STOP1_MASK, priv->regs + WDT_CTL_REG); + writel(WDT_CTL_STOP2_MASK, priv->regs + WDT_CTL_REG); return 0; } diff --git a/dts/Kconfig b/dts/Kconfig index 8917f42444..3e85914d11 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -265,8 +265,7 @@ config SPL_OF_PLATDATA This option works by generating C structure declarations for each compatible string, then adding platform data and U_BOOT_DEVICE - declarations for each node. See README.platdata for more - information. + declarations for each node. See of-plat.txt for more information. config TPL_OF_PLATDATA bool "Generate platform data for use in TPL" @@ -287,8 +286,7 @@ config TPL_OF_PLATDATA This option works by generating C structure declarations for each compatible string, then adding platform data and U_BOOT_DEVICE - declarations for each node. See README.platdata for more - information. + declarations for each node. See of-plat.txt for more information. endmenu @@ -801,6 +801,8 @@ int do_fs_type(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) else printf("%s\n", info->name); + fs_close(); + return CMD_RET_SUCCESS; } diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 31749c6d06..9ce5b6e824 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -37,6 +37,8 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE - 4) +#define CONFIG_SYS_BOOTM_LEN SZ_64M + /* U-Boot general configuration */ #define EXTRA_ENV_AM65X_BOARD_SETTINGS \ "findfdt=" \ diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index e128d1c08b..0f4d78a594 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -32,11 +32,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x82000000 /* - * This board might be of different versions so handle it - */ -#define CONFIG_BOARD_TYPES - -/* * NAND Flash configuration */ #define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000) diff --git a/include/configs/broadcom_bcm963158.h b/include/configs/broadcom_bcm963158.h new file mode 100644 index 0000000000..5834e1e2a2 --- /dev/null +++ b/include/configs/broadcom_bcm963158.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com> + */ + +#include <linux/sizes.h> + +/* + * common + */ + +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 500000, 1500000 } +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 24 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_BOOTM_LEN (16 * 1024 * 1024) + +/* + * 63158 + */ + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +/* U-Boot */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* + * bcm963158 + */ + +#define CONFIG_ENV_SIZE (8 * 1024) diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 9af1d12701..7735cc1720 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -33,11 +33,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x82000000 /* - * This board might be of different versions so handle it - */ -#define CONFIG_BOARD_TYPES - -/* * UART configuration */ #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/odroid.h b/include/configs/odroid.h index c3520bb15f..b8809c8dcc 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -186,7 +186,6 @@ * TODO: Add Odroid X support */ #define CONFIG_MISC_COMMON -#define CONFIG_BOARD_TYPES #undef CONFIG_REVISION_TAG diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 0337c26475..f178549a72 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -87,7 +87,6 @@ /* Set soc_rev, soc_id, board_rev, boardname, fdtfile */ #define CONFIG_ODROID_REV_AIN 9 #define CONFIG_REVISION_TAG -#define CONFIG_BOARD_TYPES #undef CONFIG_SYS_BOARD #define CONFIG_SYS_BOARD "odroid" diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h index 04bce2f8b4..ef69b24dd0 100644 --- a/include/configs/omap3_cairo.h +++ b/include/configs/omap3_cairo.h @@ -190,16 +190,6 @@ /* env defaults */ #define CONFIG_BOOTFILE "uImage" -/* Override OMAP3 common serial console configuration from UART3 - * to UART2. - * - * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3) - * are needed and peripheral clocks for UART2 must be enabled in - * function per_clocks_enable(). - */ -#ifdef CONFIG_SPL_BUILD -#endif - /* Provide the MACH_TYPE value the vendor kernel requires */ #define CONFIG_MACH_TYPE 3063 diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index 90ec780bfc..4cdaf13582 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -248,7 +248,4 @@ #define STM32MP1_LAST_CLK 232 -#define LTDC_K LTDC_PX -#define ETHMAC_K ETHCK_K - #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ diff --git a/include/fdtdec.h b/include/fdtdec.h index c2dd87ede2..b7e35cd87c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -133,21 +133,14 @@ enum fdt_compat_id { /* Tegra210 XUSB pad controller */ COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */ COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */ - COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */ - COMPAT_SAMSUNG_EXYNOS5_SOUND, /* Exynos Sound */ - COMPAT_WOLFSON_WM8994_CODEC, /* Wolfson WM8994 Sound Codec */ COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */ COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */ COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */ COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */ COMPAT_SAMSUNG_EXYNOS_DWMMC, /* Exynos DWMMC controller */ - COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */ COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */ - COMPAT_MAXIM_98095_CODEC, /* MAX98095 Codec */ - COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ COMPAT_INTEL_MICROCODE, /* Intel microcode update */ - COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */ COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ diff --git a/include/i2s.h b/include/i2s.h index 28f6184811..7760aab7c4 100644 --- a/include/i2s.h +++ b/include/i2s.h @@ -78,7 +78,7 @@ struct i2s_reg { /* This structure stores the i2s related information */ struct i2s_uc_priv { unsigned int rfs; /* LR clock frame size */ - unsigned int bfs; /* Bit slock frame size */ + unsigned int bfs; /* Bit clock frame size */ unsigned int audio_pll_clk; /* Audio pll frequency in Hz */ unsigned int samplingrate; /* sampling rate */ unsigned int bitspersample; /* bits per sample */ @@ -123,13 +123,4 @@ int i2s_tx_data(struct udevice *dev, void *data, uint data_size); int i2s_transfer_tx_data(struct i2s_uc_priv *pi2s_tx, void *data, uint data_size); -/* - * Initialise i2s transmiter - * - * @param pi2s_tx pointer of i2s transmitter parameter structure. - * - * @return int value 0 for success, -1 in case of error - */ -int i2s_tx_init(struct i2s_uc_priv *pi2s_tx); - #endif /* __I2S_H__ */ diff --git a/include/initcall.h b/include/initcall.h index 01f3f2833f..3ac01aa2cd 100644 --- a/include/initcall.h +++ b/include/initcall.h @@ -8,6 +8,39 @@ typedef int (*init_fnc_t)(void); -int initcall_run_list(const init_fnc_t init_sequence[]); +#include <common.h> +#include <initcall.h> +#include <efi.h> + +DECLARE_GLOBAL_DATA_PTR; + +static inline int initcall_run_list(const init_fnc_t init_sequence[]) +{ + const init_fnc_t *init_fnc_ptr; + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + unsigned long reloc_ofs = 0; + int ret; + + if (gd->flags & GD_FLG_RELOC) + reloc_ofs = gd->reloc_off; +#ifdef CONFIG_EFI_APP + reloc_ofs = (unsigned long)image_base; +#endif + debug("initcall: %p", (char *)*init_fnc_ptr - reloc_ofs); + if (gd->flags & GD_FLG_RELOC) + debug(" (relocated to %p)\n", (char *)*init_fnc_ptr); + else + debug("\n"); + ret = (*init_fnc_ptr)(); + if (ret) { + printf("initcall sequence %p failed at call %p (err=%d)\n", + init_sequence, + (char *)*init_fnc_ptr - reloc_ofs, ret); + return -1; + } + } + return 0; +} #endif diff --git a/include/power/regulator.h b/include/power/regulator.h index 5318ab3ace..314160a894 100644 --- a/include/power/regulator.h +++ b/include/power/regulator.h @@ -304,6 +304,17 @@ int regulator_get_enable(struct udevice *dev); int regulator_set_enable(struct udevice *dev, bool enable); /** + * regulator_set_enable_if_allowed: set regulator enable state if allowed by + * regulator + * + * @dev - pointer to the regulator device + * @enable - set true or false + * @return - 0 on success or if enabling is not supported + * -errno val if fails. + */ +int regulator_set_enable_if_allowed(struct udevice *dev, bool enable); + +/** * regulator_get_mode: get active operation mode id of a given regulator * * @dev - pointer to the regulator device diff --git a/include/samsung/misc.h b/include/samsung/misc.h index 0f957dc367..017560c256 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -32,9 +32,7 @@ void draw_logo(void); char *get_dfu_alt_system(char *interface, char *devstr); char *get_dfu_alt_boot(char *interface, char *devstr); #endif -#ifdef CONFIG_BOARD_TYPES void set_board_type(void); const char *get_board_type(void); -#endif #endif /* __SAMSUNG_MISC_COMMON_H__ */ diff --git a/include/test/lib.h b/include/test/lib.h new file mode 100644 index 0000000000..04b6241e54 --- /dev/null +++ b/include/test/lib.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 Heinrich Schuchardt <xypron.glpk@gmx.de> + */ + +#ifndef __TEST_LIB_H__ +#define __TEST_LIB_H__ + +#include <test/test.h> + +/* Declare a new library function test */ +#define LIB_TEST(_name, _flags) UNIT_TEST(_name, _flags, lib_test) + +#endif /* __TEST_LIB_H__ */ diff --git a/include/test/suites.h b/include/test/suites.h index 77d863b4a6..01bee09346 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -27,6 +27,7 @@ int do_ut_bloblist(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); int do_ut_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_env(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +int do_ut_lib(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_unicode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); diff --git a/lib/Makefile b/lib/Makefile index 61d7ff0678..47829bfed5 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -35,7 +35,6 @@ obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o obj-$(CONFIG_GZIP_COMPRESSED) += gzip.o obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o obj-$(CONFIG_IMAGE_SPARSE) += image-sparse.o -obj-y += initcall.o obj-y += ldiv.o obj-$(CONFIG_MD5) += md5.o obj-y += net_utils.o diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 55811975ef..09a7e133a5 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -40,21 +40,14 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"), COMPAT(SMSC_LAN9215, "smsc,lan9215"), COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"), - COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"), - COMPAT(SAMSUNG_EXYNOS5_SOUND, "samsung,exynos-sound"), - COMPAT(WOLFSON_WM8994_CODEC, "wolfson,wm8994-codec"), COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"), COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"), COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"), COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"), COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"), - COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"), COMPAT(GENERIC_SPI_FLASH, "spi-flash"), - COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"), - COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"), COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"), COMPAT(INTEL_MICROCODE, "intel,microcode"), - COMPAT(AMS_AS3722, "ams,as3722"), COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"), COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"), COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"), diff --git a/lib/hashtable.c b/lib/hashtable.c index 50ff40a397..0d288d12d9 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -40,6 +40,9 @@ #define CONFIG_ENV_MAX_ENTRIES 512 #endif +#define USED_FREE 0 +#define USED_DELETED -1 + #include <env_callback.h> #include <env_flags.h> #include <search.h> @@ -303,7 +306,7 @@ int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval, */ unsigned hval2; - if (htab->table[idx].used == -1 + if (htab->table[idx].used == USED_DELETED && !first_deleted) first_deleted = idx; @@ -335,13 +338,17 @@ int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval, if (idx == hval) break; + if (htab->table[idx].used == USED_DELETED + && !first_deleted) + first_deleted = idx; + /* If entry is found use it. */ ret = _compare_and_overwrite_entry(item, action, retval, htab, flag, hval, idx); if (ret != -1) return ret; } - while (htab->table[idx].used); + while (htab->table[idx].used != USED_FREE); } /* An empty bucket has been found. */ @@ -433,7 +440,7 @@ static void _hdelete(const char *key, struct hsearch_data *htab, ENTRY *ep, free(ep->data); ep->callback = NULL; ep->flags = 0; - htab->table[idx].used = -1; + htab->table[idx].used = USED_DELETED; --htab->filled; } diff --git a/lib/initcall.c b/lib/initcall.c deleted file mode 100644 index 8f1dac68e4..0000000000 --- a/lib/initcall.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2013 The Chromium OS Authors. - */ - -#include <common.h> -#include <initcall.h> -#include <efi.h> - -DECLARE_GLOBAL_DATA_PTR; - -int initcall_run_list(const init_fnc_t init_sequence[]) -{ - const init_fnc_t *init_fnc_ptr; - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - unsigned long reloc_ofs = 0; - int ret; - - if (gd->flags & GD_FLG_RELOC) - reloc_ofs = gd->reloc_off; -#ifdef CONFIG_EFI_APP - reloc_ofs = (unsigned long)image_base; -#endif - debug("initcall: %p", (char *)*init_fnc_ptr - reloc_ofs); - if (gd->flags & GD_FLG_RELOC) - debug(" (relocated to %p)\n", (char *)*init_fnc_ptr); - else - debug("\n"); - ret = (*init_fnc_ptr)(); - if (ret) { - printf("initcall sequence %p failed at call %p (err=%d)\n", - init_sequence, - (char *)*init_fnc_ptr - reloc_ofs, ret); - return -1; - } - } - return 0; -} diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 38c7f01fad..2b3572568b 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -129,7 +129,6 @@ CONFIG_BOARD_POSTCLK_INIT CONFIG_BOARD_REVISION_TAG CONFIG_BOARD_SIZE_LIMIT CONFIG_BOARD_TAURUS -CONFIG_BOARD_TYPES CONFIG_BOOGER CONFIG_BOOTBLOCK CONFIG_BOOTFILE diff --git a/test/Kconfig b/test/Kconfig index de16d179d0..48a0e501f8 100644 --- a/test/Kconfig +++ b/test/Kconfig @@ -6,6 +6,14 @@ menuconfig UNIT_TEST This does not require sandbox to be included, but it is most often used there. +config UT_LIB + bool "Unit tests for library functions" + depends on UNIT_TEST + default y + help + Enables the 'ut lib' command which tests library functions like + memcat(), memcyp(), memmove(). + config UT_TIME bool "Unit tests for time functions" depends on UNIT_TEST diff --git a/test/cmd_ut.c b/test/cmd_ut.c index 56924a5272..e3b89504e7 100644 --- a/test/cmd_ut.c +++ b/test/cmd_ut.c @@ -46,6 +46,9 @@ static cmd_tbl_t cmd_ut_sub[] = { #ifdef CONFIG_UT_OVERLAY U_BOOT_CMD_MKENT(overlay, CONFIG_SYS_MAXARGS, 1, do_ut_overlay, "", ""), #endif +#ifdef CONFIG_UT_LIB + U_BOOT_CMD_MKENT(lib, CONFIG_SYS_MAXARGS, 1, do_ut_lib, "", ""), +#endif #ifdef CONFIG_UT_TIME U_BOOT_CMD_MKENT(time, CONFIG_SYS_MAXARGS, 1, do_ut_time, "", ""), #endif @@ -108,6 +111,9 @@ static char ut_help_text[] = #ifdef CONFIG_UT_ENV "ut env [test-name]\n" #endif +#ifdef CONFIG_UT_LIB + "ut lib [test-name] - test library functions\n" +#endif #ifdef CONFIG_UT_OVERLAY "ut overlay [test-name]\n" #endif diff --git a/test/dm/core.c b/test/dm/core.c index 260f6494a2..edd55b05d6 100644 --- a/test/dm/core.c +++ b/test/dm/core.c @@ -749,6 +749,10 @@ static int dm_test_uclass_devices_find(struct unit_test_state *uts) ut_assert(dev); } + ret = uclass_find_first_device(UCLASS_TEST_DUMMY, &dev); + ut_assert(ret == -ENODEV); + ut_assert(!dev); + return 0; } DM_TEST(dm_test_uclass_devices_find, DM_TESTF_SCAN_PDATA); diff --git a/test/dm/regulator.c b/test/dm/regulator.c index 5d11e946b2..e510539542 100644 --- a/test/dm/regulator.c +++ b/test/dm/regulator.c @@ -175,6 +175,27 @@ static int dm_test_power_regulator_set_get_enable(struct unit_test_state *uts) } DM_TEST(dm_test_power_regulator_set_get_enable, DM_TESTF_SCAN_FDT); +/* Test regulator set and get enable if allowed method */ +static +int dm_test_power_regulator_set_enable_if_allowed(struct unit_test_state *uts) +{ + const char *platname; + struct udevice *dev, *dev_autoset; + bool val_set = false; + + /* Get BUCK1 - always on regulator */ + platname = regulator_names[BUCK1][PLATNAME]; + ut_assertok(regulator_autoset_by_name(platname, &dev_autoset)); + ut_assertok(regulator_get_by_platname(platname, &dev)); + + /* Try disabling always-on regulator */ + ut_assertok(regulator_set_enable_if_allowed(dev, val_set)); + ut_asserteq(regulator_get_enable(dev), !val_set); + + return 0; +} +DM_TEST(dm_test_power_regulator_set_enable_if_allowed, DM_TESTF_SCAN_FDT); + /* Test regulator set and get mode method */ static int dm_test_power_regulator_set_get_mode(struct unit_test_state *uts) { diff --git a/test/env/Makefile b/test/env/Makefile index d71a11b6e2..5c8eae31b0 100644 --- a/test/env/Makefile +++ b/test/env/Makefile @@ -4,3 +4,4 @@ obj-y += cmd_ut_env.o obj-y += attr.o +obj-y += hashtable.o diff --git a/test/env/hashtable.c b/test/env/hashtable.c new file mode 100644 index 0000000000..8c87e65457 --- /dev/null +++ b/test/env/hashtable.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2019 + * Roman Kapl, SYSGO, rka@sysgo.com + */ + +#include <common.h> +#include <command.h> +#include <search.h> +#include <stdio.h> +#include <test/env.h> +#include <test/ut.h> + +#define SIZE 32 +#define ITERATIONS 10000 + +static int htab_fill(struct unit_test_state *uts, + struct hsearch_data *htab, size_t size) +{ + size_t i; + ENTRY item; + ENTRY *ritem; + char key[20]; + + for (i = 0; i < size; i++) { + sprintf(key, "%d", (int)i); + item.callback = NULL; + item.data = key; + item.flags = 0; + item.key = key; + ut_asserteq(1, hsearch_r(item, ENTER, &ritem, htab, 0)); + } + + return 0; +} + +static int htab_check_fill(struct unit_test_state *uts, + struct hsearch_data *htab, size_t size) +{ + size_t i; + ENTRY item; + ENTRY *ritem; + char key[20]; + + for (i = 0; i < size; i++) { + sprintf(key, "%d", (int)i); + item.callback = NULL; + item.flags = 0; + item.data = key; + item.key = key; + hsearch_r(item, FIND, &ritem, htab, 0); + ut_assert(ritem); + ut_asserteq_str(key, ritem->key); + ut_asserteq_str(key, ritem->data); + } + + return 0; +} + +static int htab_create_delete(struct unit_test_state *uts, + struct hsearch_data *htab, size_t iterations) +{ + size_t i; + ENTRY item; + ENTRY *ritem; + char key[20]; + + for (i = 0; i < iterations; i++) { + sprintf(key, "cd-%d", (int)i); + item.callback = NULL; + item.flags = 0; + item.data = key; + item.key = key; + hsearch_r(item, ENTER, &ritem, htab, 0); + ritem = NULL; + + hsearch_r(item, FIND, &ritem, htab, 0); + ut_assert(ritem); + ut_asserteq_str(key, ritem->key); + ut_asserteq_str(key, ritem->data); + + ut_asserteq(1, hdelete_r(key, htab, 0)); + } + + return 0; +} + +/* Completely fill up the hash table */ +static int env_test_htab_fill(struct unit_test_state *uts) +{ + struct hsearch_data htab; + + memset(&htab, 0, sizeof(htab)); + ut_asserteq(1, hcreate_r(SIZE, &htab)); + + ut_assertok(htab_fill(uts, &htab, SIZE)); + ut_assertok(htab_check_fill(uts, &htab, SIZE)); + ut_asserteq(SIZE, htab.filled); + + hdestroy_r(&htab); + return 0; +} + +ENV_TEST(env_test_htab_fill, 0); + +/* Fill the hashtable up halfway an repeateadly delete/create elements + * and check for corruption + */ +static int env_test_htab_deletes(struct unit_test_state *uts) +{ + struct hsearch_data htab; + + memset(&htab, 0, sizeof(htab)); + ut_asserteq(1, hcreate_r(SIZE, &htab)); + + ut_assertok(htab_fill(uts, &htab, SIZE / 2)); + ut_assertok(htab_create_delete(uts, &htab, ITERATIONS)); + ut_assertok(htab_check_fill(uts, &htab, SIZE / 2)); + ut_asserteq(SIZE / 2, htab.filled); + + hdestroy_r(&htab); + return 0; +} + +ENV_TEST(env_test_htab_deletes, 0); diff --git a/test/lib/Makefile b/test/lib/Makefile index 5a636aac74..308c61708e 100644 --- a/test/lib/Makefile +++ b/test/lib/Makefile @@ -2,5 +2,7 @@ # # (C) Copyright 2018 # Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc +obj-y += cmd_ut_lib.o obj-y += hexdump.o obj-y += lmb.o +obj-y += string.o diff --git a/test/lib/cmd_ut_lib.c b/test/lib/cmd_ut_lib.c new file mode 100644 index 0000000000..eb90e53914 --- /dev/null +++ b/test/lib/cmd_ut_lib.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Heinrich Schuchardt <xypron.glpk@gmx.de> + * + * Unit tests for library functions + */ + +#include <common.h> +#include <command.h> +#include <test/lib.h> +#include <test/suites.h> +#include <test/ut.h> + +int do_ut_lib(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct unit_test *tests = ll_entry_start(struct unit_test, lib_test); + const int n_ents = ll_entry_count(struct unit_test, lib_test); + + return cmd_ut_category("lib", tests, n_ents, argc, argv); +} diff --git a/test/lib/string.c b/test/lib/string.c new file mode 100644 index 0000000000..8e246ab4ed --- /dev/null +++ b/test/lib/string.c @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 Heinrich Schuchardt <xypron.glpk@gmx.de> + * + * Unit tests for memory functions + * + * The architecture dependent implementations run through different lines of + * code depending on the alignment and length of memory regions copied or set. + * This has to be considered in testing. + */ + +#include <common.h> +#include <command.h> +#include <test/lib.h> +#include <test/test.h> +#include <test/ut.h> + +/* Xor mask used for marking memory regions */ +#define MASK 0xA5 +/* Number of different alignment values */ +#define SWEEP 16 +/* Allow for copying up to 32 bytes */ +#define BUFLEN (SWEEP + 33) + +/** + * init_buffer() - initialize buffer + * + * The buffer is filled with incrementing values xor'ed with the mask. + * + * @buf: buffer + * @mask: xor mask + */ +static void init_buffer(u8 buf[], u8 mask) +{ + int i; + + for (i = 0; i < BUFLEN; ++i) + buf[i] = i ^ mask; +} + +/** + * test_memset() - test result of memset() + * + * @uts: unit test state + * @buf: buffer + * @mask: value set by memset() + * @offset: relative start of region changed by memset() in buffer + * @len: length of region changed by memset() + * Return: 0 = success, 1 = failure + */ +static int test_memset(struct unit_test_state *uts, u8 buf[], u8 mask, + int offset, int len) +{ + int i; + + for (i = 0; i < BUFLEN; ++i) { + if (i < offset || i >= offset + len) { + ut_asserteq(i, buf[i]); + } else { + ut_asserteq(mask, buf[i]); + } + } + return 0; +} + +/** + * lib_memset() - unit test for memset() + * + * Test memset() with varied alignment and length of the changed buffer. + * + * @uts: unit test state + * Return: 0 = success, 1 = failure + */ +static int lib_memset(struct unit_test_state *uts) +{ + u8 buf[BUFLEN]; + int offset, len; + void *ptr; + + for (offset = 0; offset <= SWEEP; ++offset) { + for (len = 1; len < BUFLEN - SWEEP; ++len) { + init_buffer(buf, 0); + ptr = memset(buf + offset, MASK, len); + ut_asserteq_ptr(buf + offset, (u8 *)ptr); + if (test_memset(uts, buf, MASK, offset, len)) { + debug("%s: failure %d, %d\n", + __func__, offset, len); + return CMD_RET_FAILURE; + } + } + } + return 0; +} + +LIB_TEST(lib_memset, 0); + +/** + * test_memmove() - test result of memcpy() or memmove() + * + * @uts: unit test state + * @buf: buffer + * @mask: xor mask used to initialize source buffer + * @offset1: relative start of copied region in source buffer + * @offset2: relative start of copied region in destination buffer + * @len: length of region changed by memset() + * Return: 0 = success, 1 = failure + */ +static int test_memmove(struct unit_test_state *uts, u8 buf[], u8 mask, + int offset1, int offset2, int len) +{ + int i; + + for (i = 0; i < BUFLEN; ++i) { + if (i < offset2 || i >= offset2 + len) { + ut_asserteq(i, buf[i]); + } else { + ut_asserteq((i + offset1 - offset2) ^ mask, buf[i]); + } + } + return 0; +} + +/** + * lib_memcpy() - unit test for memcpy() + * + * Test memcpy() with varied alignment and length of the copied buffer. + * + * @uts: unit test state + * Return: 0 = success, 1 = failure + */ +static int lib_memcpy(struct unit_test_state *uts) +{ + u8 buf1[BUFLEN]; + u8 buf2[BUFLEN]; + int offset1, offset2, len; + void *ptr; + + init_buffer(buf1, MASK); + + for (offset1 = 0; offset1 <= SWEEP; ++offset1) { + for (offset2 = 0; offset2 <= SWEEP; ++offset2) { + for (len = 1; len < BUFLEN - SWEEP; ++len) { + init_buffer(buf2, 0); + ptr = memcpy(buf2 + offset2, buf1 + offset1, + len); + ut_asserteq_ptr(buf2 + offset2, (u8 *)ptr); + if (test_memmove(uts, buf2, MASK, offset1, + offset2, len)) { + debug("%s: failure %d, %d, %d\n", + __func__, offset1, offset2, len); + return CMD_RET_FAILURE; + } + } + } + } + return 0; +} + +LIB_TEST(lib_memcpy, 0); + +/** + * lib_memmove() - unit test for memmove() + * + * Test memmove() with varied alignment and length of the copied buffer. + * + * @uts: unit test state + * Return: 0 = success, 1 = failure + */ +static int lib_memmove(struct unit_test_state *uts) +{ + u8 buf[BUFLEN]; + int offset1, offset2, len; + void *ptr; + + for (offset1 = 0; offset1 <= SWEEP; ++offset1) { + for (offset2 = 0; offset2 <= SWEEP; ++offset2) { + for (len = 1; len < BUFLEN - SWEEP; ++len) { + init_buffer(buf, 0); + ptr = memmove(buf + offset2, buf + offset1, + len); + ut_asserteq_ptr(buf + offset2, (u8 *)ptr); + if (test_memmove(uts, buf, 0, offset1, offset2, + len)) { + debug("%s: failure %d, %d, %d\n", + __func__, offset1, offset2, len); + return CMD_RET_FAILURE; + } + } + } + } + return 0; +} + +LIB_TEST(lib_memmove, 0); diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py index 6b156f152d..8a9d47cd5e 100644 --- a/tools/buildman/builderthread.py +++ b/tools/buildman/builderthread.py @@ -322,6 +322,9 @@ class BuilderThread(threading.Thread): # Write out the image and function size information and an objdump env = result.toolchain.MakeEnvironment(self.builder.full_path) + with open(os.path.join(build_dir, 'env'), 'w') as fd: + for var in sorted(env.keys()): + print >>fd, '%s="%s"' % (var, env[var]) lines = [] for fname in ['u-boot', 'spl/u-boot-spl']: cmd = ['%snm' % self.toolchain.cross, '--size-sort', fname] diff --git a/tools/buildman/control.py b/tools/buildman/control.py index 27916d3c35..fcf531c5f1 100644 --- a/tools/buildman/control.py +++ b/tools/buildman/control.py @@ -99,7 +99,7 @@ def CheckOutputDir(output_dir): cwd_path = os.path.realpath('.') while True: if os.path.realpath(path) == cwd_path: - Print("Cannot use output directory '%s' since it is within the current directtory '%s'" % + Print("Cannot use output directory '%s' since it is within the current directory '%s'" % (path, cwd_path)) sys.exit(1) parent = os.path.dirname(path) diff --git a/tools/k3_x509template.txt b/tools/k3_x509template.txt index bd3a9ab056..f176ff3ad2 100644 --- a/tools/k3_x509template.txt +++ b/tools/k3_x509template.txt @@ -42,7 +42,7 @@ # salt = FORMAT:HEX,OCT:TEST_IMAGE_KEY_DERIVE_SALT [ debug ] + debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000 debugType = INTEGER:4 coreDbgEn = INTEGER:0 coreDbgSecEn = INTEGER:0 - debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000 diff --git a/tools/moveconfig.py b/tools/moveconfig.py index caa81ac2ed..1a214c5605 100755 --- a/tools/moveconfig.py +++ b/tools/moveconfig.py @@ -545,6 +545,28 @@ def confirm(options, prompt): return True +def cleanup_empty_blocks(header_path, options): + """Clean up empty conditional blocks + + Arguments: + header_path: path to the cleaned file. + options: option flags. + """ + pattern = re.compile(r'^\s*#\s*if.*$\n^\s*#\s*endif.*$\n*', flags=re.M) + with open(header_path) as f: + data = f.read() + + new_data = pattern.sub('\n', data) + + show_diff(data.splitlines(True), new_data.splitlines(True), header_path, + options.color) + + if options.dry_run: + return + + with open(header_path, 'w') as f: + f.write(new_data) + def cleanup_one_header(header_path, patterns, options): """Clean regex-matched lines away from a file. @@ -626,8 +648,9 @@ def cleanup_headers(configs, options): continue for filename in filenames: if not fnmatch.fnmatch(filename, '*~'): - cleanup_one_header(os.path.join(dirpath, filename), - patterns, options) + header_path = os.path.join(dirpath, filename) + cleanup_one_header(header_path, patterns, options) + cleanup_empty_blocks(header_path, options) def cleanup_one_extra_option(defconfig_path, configs, options): """Delete config defines in CONFIG_SYS_EXTRA_OPTIONS in one defconfig file. |