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-rw-r--r--arch/x86/dts/Makefile1
-rw-r--r--arch/x86/dts/chromebook_samus.dts628
-rw-r--r--board/google/Kconfig13
-rw-r--r--board/google/chromebook_samus/Kconfig40
-rw-r--r--board/google/chromebook_samus/MAINTAINERS6
-rw-r--r--board/google/chromebook_samus/Makefile7
-rw-r--r--board/google/chromebook_samus/samus.c18
-rw-r--r--configs/chromebook_samus_defconfig51
-rw-r--r--doc/README.x8681
-rw-r--r--include/configs/chromebook_samus.h29
-rw-r--r--include/configs/x86-chromebook.h3
11 files changed, 876 insertions, 1 deletions
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 84feb193d7..fcfce9537d 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -5,6 +5,7 @@
dtb-y += bayleybay.dtb \
chromebook_link.dtb \
chromebox_panther.dtb \
+ chromebook_samus.dtb \
cougarcanyon2.dtb \
crownbay.dtb \
efi.dtb \
diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
new file mode 100644
index 0000000000..5dd3e57cb9
--- /dev/null
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -0,0 +1,628 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/x86-gpio.h>
+
+/include/ "skeleton.dtsi"
+/include/ "keyboard.dtsi"
+/include/ "serial.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+ model = "Google Samus";
+ compatible = "google,samus", "intel,broadwell";
+
+ aliases {
+ spi0 = &spi;
+ usb0 = &usb_0;
+ usb1 = &usb_1;
+ };
+
+ config {
+ silent_console = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "intel,core-i3-gen5";
+ reg = <0>;
+ intel,apic-id = <0>;
+ intel,slow-ramp = <3>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "intel,core-i3-gen5";
+ reg = <1>;
+ intel,apic-id = <1>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "intel,core-i3-gen5";
+ reg = <2>;
+ intel,apic-id = <2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "intel,core-i3-gen5";
+ reg = <3>;
+ intel,apic-id = <3>;
+ };
+
+ };
+
+ chosen {
+ stdout-path = "/serial";
+ };
+
+ keyboard {
+ intel,duplicate-por;
+ };
+
+ pch_pinctrl {
+ compatible = "intel,x86-broadwell-pinctrl";
+ u-boot,dm-pre-reloc;
+ reg = <0 0>;
+
+ /* Put this first: it is the default */
+ gpio_unused: gpio-unused {
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ owner = <OWNER_GPIO>;
+ sense-disable;
+ };
+
+ gpio_acpi_sci: acpi-sci {
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ invert;
+ route = <ROUTE_SCI>;
+ };
+
+ gpio_acpi_smi: acpi-smi {
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ invert;
+ route = <ROUTE_SMI>;
+ };
+
+ gpio_input: gpio-input {
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ owner = <OWNER_GPIO>;
+ };
+
+ gpio_input_invert: gpio-input-invert {
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ owner = <OWNER_GPIO>;
+ invert;
+ };
+
+ gpio_native: gpio-native {
+ };
+
+ gpio_out_high: gpio-out-high {
+ mode-gpio;
+ direction = <PIN_OUTPUT>;
+ output-value = <1>;
+ owner = <OWNER_GPIO>;
+ sense-disable;
+ };
+
+ gpio_out_low: gpio-out-low {
+ mode-gpio;
+ direction = <PIN_OUTPUT>;
+ output-value = <0>;
+ owner = <OWNER_GPIO>;
+ sense-disable;
+ };
+
+ gpio_pirq: gpio-pirq {
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ owner = <OWNER_GPIO>;
+ pirq-apic = <PIRQ_APIC_ROUTE>;
+ };
+
+ soc_gpio@0 {
+ config =
+ <0 &gpio_unused 0>, /* unused */
+ <1 &gpio_unused 0>, /* unused */
+ <2 &gpio_unused 0>, /* unused */
+ <3 &gpio_unused 0>, /* unused */
+ <4 &gpio_native 0>, /* native: i2c0_sda_gpio4 */
+ <5 &gpio_native 0>, /* native: i2c0_scl_gpio5 */
+ <6 &gpio_native 0>, /* native: i2c1_sda_gpio6 */
+ <7 &gpio_native 0>, /* native: i2c1_scl_gpio7 */
+ <8 &gpio_acpi_sci 0>, /* pch_lte_wake_l */
+ <9 &gpio_input_invert 0>, /* trackpad_int_l (wake) */
+ <10 &gpio_acpi_sci 0>, /* pch_wlan_wake_l */
+ <11 &gpio_unused 0>, /* unused */
+ <12 &gpio_unused 0>, /* unused */
+ <13 &gpio_pirq 3>, /* trackpad_int_l (pirql) */
+ <14 &gpio_pirq 4>, /* touch_int_l (pirqm) */
+ <15 &gpio_unused 0>, /* unused (strap) */
+ <16 &gpio_input 0>, /* pch_wp */
+ <17 &gpio_unused 0>, /* unused */
+ <18 &gpio_unused 0>, /* unused */
+ <19 &gpio_unused 0>, /* unused */
+ <20 &gpio_native 0>, /* pcie_wlan_clkreq_l */
+ <21 &gpio_out_high 0>, /* pp3300_ssd_en */
+ <22 &gpio_unused 0>, /* unused */
+ <23 &gpio_out_low 0>, /* pp3300_autobahn_en */
+ <24 &gpio_unused 0>, /* unused */
+ <25 &gpio_input 0>, /* ec_in_rw */
+ <26 &gpio_unused 0>, /* unused */
+ <27 &gpio_acpi_sci 0>, /* pch_wake_l */
+ <28 &gpio_unused 0>, /* unused */
+ <29 &gpio_unused 0>, /* unused */
+ <30 &gpio_native 0>, /* native: pch_suswarn_l */
+ <31 &gpio_native 0>, /* native: acok_buf */
+ <32 &gpio_native 0>, /* native: lpc_clkrun_l */
+ <33 &gpio_native 0>, /* native: ssd_devslp */
+ <34 &gpio_acpi_smi 0>, /* ec_smi_l */
+ <35 &gpio_acpi_smi 0>, /* pch_nmi_dbg_l (route in nmi_en) */
+ <36 &gpio_acpi_sci 0>, /* ec_sci_l */
+ <37 &gpio_unused 0>, /* unused */
+ <38 &gpio_unused 0>, /* unused */
+ <39 &gpio_unused 0>, /* unused */
+ <40 &gpio_native 0>, /* native: pch_usb1_oc_l */
+ <41 &gpio_native 0>, /* native: pch_usb2_oc_l */
+ <42 &gpio_unused 0>, /* wlan_disable_l */
+ <43 &gpio_out_high 0>, /* pp1800_codec_en */
+ <44 &gpio_unused 0>, /* unused */
+ <45 &gpio_acpi_sci 0>, /* dsp_int - codec wake */
+ <46 &gpio_pirq 6>, /* hotword_det_l_3v3 (pirqo) - codec irq */
+ <47 &gpio_out_low 0>, /* ssd_reset_l */
+ <48 &gpio_unused 0>, /* unused */
+ <49 &gpio_unused 0>, /* unused */
+ <50 &gpio_unused 0>, /* unused */
+ <51 &gpio_unused 0>, /* unused */
+ <52 &gpio_input 0>, /* sim_det */
+ <53 &gpio_unused 0>, /* unused */
+ <54 &gpio_unused 0>, /* unused */
+ <55 &gpio_unused 0>, /* unused */
+ <56 &gpio_unused 0>, /* unused */
+ <57 &gpio_out_high 0>, /* codec_reset_l */
+ <58 &gpio_unused 0>, /* unused */
+ <59 &gpio_out_high 0>, /* lte_disable_l */
+ <60 &gpio_unused 0>, /* unused */
+ <61 &gpio_native 0>, /* native: pch_sus_stat */
+ <62 &gpio_native 0>, /* native: pch_susclk */
+ <63 &gpio_native 0>, /* native: pch_slp_s5_l */
+ <64 &gpio_unused 0>, /* unused */
+ <65 &gpio_input 0>, /* ram_id3 */
+ <66 &gpio_input 0>, /* ram_id3_old (strap) */
+ <67 &gpio_input 0>, /* ram_id0 */
+ <68 &gpio_input 0>, /* ram_id1 */
+ <69 &gpio_input 0>, /* ram_id2 */
+ <70 &gpio_unused 0>, /* unused */
+ <71 &gpio_native 0>, /* native: modphy_en */
+ <72 &gpio_unused 0>, /* unused */
+ <73 &gpio_unused 0>, /* unused */
+ <74 &gpio_unused 0>, /* unused */
+ <75 &gpio_unused 0>, /* unused */
+ <76 &gpio_unused 0>, /* unused */
+ <77 &gpio_unused 0>, /* unused */
+ <78 &gpio_unused 0>, /* unused */
+ <79 &gpio_unused 0>, /* unused */
+ <80 &gpio_unused 0>, /* unused */
+ <81 &gpio_unused 0>, /* unused */
+ <82 &gpio_native 0>, /* native: ec_rcin_l */
+ <83 &gpio_native 0>, /* gspi0_cs */
+ <84 &gpio_native 0>, /* gspi0_clk */
+ <85 &gpio_native 0>, /* gspi0_miso */
+ <86 &gpio_native 0>, /* gspi0_mosi (strap) */
+ <87 &gpio_unused 0>, /* unused */
+ <88 &gpio_unused 0>, /* unused */
+ <89 &gpio_out_high 0>, /* pp3300_sd_en */
+ <90 &gpio_unused 0>, /* unused */
+ <91 &gpio_unused 0>, /* unused */
+ <92 &gpio_unused 0>, /* unused */
+ <93 &gpio_unused 0>, /* unused */
+ <94 &gpio_unused 0>; /* unused */
+ };
+ };
+
+ pci {
+ compatible = "pci-x86";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
+ 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
+ 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
+
+ northbridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ compatible = "intel,broadwell-northbridge";
+ board-id-gpios = <&gpio_c 5 0>, <&gpio_c 4 0>,
+ <&gpio_c 3 0>, <&gpio_c 1 0>;
+ u-boot,dm-pre-reloc;
+ spd {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ samsung_4 {
+ reg = <6>;
+ data = [91 20 f1 03 04 11 05 0b
+ 03 11 01 08 0a 00 50 01
+ 78 78 90 50 90 11 50 e0
+ 10 04 3c 3c 01 90 00 00
+ 00 80 00 00 00 00 00 a8
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 11 02 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 80 ce 01
+ 00 00 55 00 00 00 00 00
+ 4b 34 45 38 45 33 30 34
+ 45 44 2d 45 47 43 45 20
+ 20 20 00 00 80 ce 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00];
+ };
+ hynix-h9ccnnnbltmlar-ntm-lpddr3-32 {
+ /*
+ * banks 8, ranks 2, rows 14,
+ * columns 10, density 4096 mb, x32
+ */
+ reg = <8>;
+ data = [91 20 f1 03 04 11 05 0b
+ 03 11 01 08 0a 00 50 01
+ 78 78 90 50 90 11 50 e0
+ 10 04 3c 3c 01 90 00 00
+ 00 80 00 00 00 00 00 a8
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 01 02 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 80 ad 00
+ 00 00 55 00 00 00 00 00
+ 48 39 43 43 4e 4e 4e 42
+ 4c 54 4d 4c 41 52 2d 4e
+ 54 4d 00 00 80 ad 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00];
+ };
+ samsung_8 {
+ reg = <10>;
+ data = [91 20 f1 03 04 12 05 0a
+ 03 11 01 08 0a 00 50 01
+ 78 78 90 50 90 11 50 e0
+ 10 04 3c 3c 01 90 00 00
+ 00 80 00 00 00 00 00 a8
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 11 02 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 80 ce 01
+ 00 00 55 00 00 00 00 00
+ 4b 34 45 36 45 33 30 34
+ 45 44 2d 45 47 43 45 20
+ 20 20 00 00 80 ce 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00];
+ };
+ hynix-h9ccnnnbltmlar-ntm-lpddr3-16 {
+ /*
+ * banks 8, ranks 2, rows 14,
+ * columns 11, density 4096 mb, x16
+ */
+ reg = <12>;
+ data = [91 20 f1 03 04 12 05 0a
+ 03 11 01 08 0a 00 50 01
+ 78 78 90 50 90 11 50 e0
+ 10 04 3c 3c 01 90 00 00
+ 00 80 00 00 00 00 00 a8
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 01 02 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 80 ad 00
+ 00 00 55 00 00 00 00 00
+ 48 39 43 43 4e 4e 4e 42
+ 4c 54 4d 4c 41 52 2d 4e
+ 54 4d 00 00 80 ad 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00];
+ };
+ hynix-h9ccnnncltmlar-lpddr3 {
+ /*
+ * banks 8, ranks 2, rows 15,
+ * columns 11, density 8192 mb, x16
+ */
+ reg = <13>;
+ data = [91 20 f1 03 05 1a 05 0a
+ 03 11 01 08 0a 00 50 01
+ 78 78 90 50 90 11 50 e0
+ 90 06 3c 3c 01 90 00 00
+ 00 80 00 00 00 00 00 a8
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 01 02 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 80 ad 00
+ 00 00 55 00 00 00 00 00
+ 48 39 43 43 4e 4e 4e 43
+ 4c 54 4d 4c 41 52 00 00
+ 00 00 00 00 80 ad 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00];
+ };
+ elpida-edfb232a1ma {
+ /*
+ * banks 8, ranks 2, rows 15,
+ * columns 11, density 8192 mb, x16
+ */
+ reg = <15>;
+ data = [91 20 f1 03 05 1a 05 0a
+ 03 11 01 08 0a 00 50 01
+ 78 78 90 50 90 11 50 e0
+ 90 06 3c 3c 01 90 00 00
+ 00 80 00 00 00 00 00 a8
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 01 02 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 02 fe 00
+ 00 00 00 00 00 00 00 00
+ 45 44 46 42 32 33 32 41
+ 31 4d 41 2d 47 44 2d 46
+ 00 00 00 00 02 fe 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00];
+ };
+ };
+ };
+
+ gma@2,0 {
+ reg = <0x00001000 0 0 0 0>;
+ compatible = "intel,broadwell-igd";
+ intel,dp-hotplug = <6 6 6>;
+ intel,port-select = <1>; /* eDP */
+ intel,power-cycle-delay = <6>;
+ intel,power-up-delay = <2000>;
+ intel,power-down-delay = <500>;
+ intel,power-backlight-on-delay = <2000>;
+ intel,power-backlight-off-delay = <2000>;
+ intel,cpu-backlight = <0x00000200>;
+ intel,pch-backlight = <0x04000200>;
+ intel,pre-graphics-delay = <200>;
+ };
+
+ me@16,0 {
+ reg = <0x0000b000 0 0 0 0>;
+ compatible = "intel,me";
+ u-boot,dm-pre-reloc;
+ };
+
+ usb_1: usb@14,0 {
+ reg = <0x0000a000 0 0 0 0>;
+ compatible = "xhci-pci";
+ };
+
+ usb_0: usb@1d,0 {
+ status = "disabled";
+ reg = <0x0000e800 0 0 0 0>;
+ compatible = "ehci-pci";
+ };
+
+ pch@1f,0 {
+ reg = <0x0000f800 0 0 0 0>;
+ compatible = "intel,broadwell-pch";
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
+ 0x80 0x80 0x80 0x80>;
+ intel,gpi-routing = <0 0 0 0 0 0 0 2
+ 1 0 0 0 0 0 0 0>;
+ /* Enable EC SMI source */
+ intel,alt-gp-smi-enable = <0x0040>;
+
+ /* EC-SCI is GPIO36 */
+ intel,gpe0-en = <0 0x10 0 0>;
+
+ power-enable-gpio = <&gpio_a 23 0>;
+
+ spi: spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich9-spi";
+ spi-flash@0 {
+ #size-cells = <1>;
+ #address-cells = <1>;
+ reg = <0>;
+ compatible = "winbond,w25q64",
+ "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ reg = <0x003e0000 0x00010000>;
+ };
+ };
+ };
+
+ gpio_a: gpioa {
+ compatible = "intel,broadwell-gpio";
+ u-boot,dm-pre-reloc;
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0 0>;
+ bank-name = "A";
+ };
+
+ gpio_b: gpiob {
+ compatible = "intel,broadwell-gpio";
+ u-boot,dm-pre-reloc;
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <1 0>;
+ bank-name = "B";
+ };
+
+ gpio_c: gpioc {
+ compatible = "intel,broadwell-gpio";
+ u-boot,dm-pre-reloc;
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <2 0>;
+ bank-name = "C";
+ };
+
+ lpc {
+ compatible = "intel,broadwell-lpc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+ intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
+ cros-ec@200 {
+ compatible = "google,cros-ec-lpc";
+ reg = <0x204 1 0x200 1 0x880 0x80>;
+
+ /*
+ * Describes the flash memory within
+ * the EC
+ */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ flash@8000000 {
+ reg = <0x08000000 0x20000>;
+ erase-value = <0xff>;
+ };
+ };
+ };
+ };
+
+ sata@1f,2 {
+ compatible = "intel,wildcatpoint-ahci";
+ reg = <0x0000fa00 0 0 0 0>;
+ u-boot,dm-pre-reloc;
+ intel,sata-mode = "ahci";
+ intel,sata-port-map = <1>;
+ intel,sata-port0-gen3-tx = <0x72>;
+ reset-gpio = <&gpio_b 15 GPIO_ACTIVE_LOW>;
+ };
+
+ smbus: smbus@1f,3 {
+ compatible = "intel,ich-i2c";
+ reg = <0x0000fb00 0 0 0 0>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ tpm {
+ reg = <0xfed40000 0x5000>;
+ compatible = "infineon,slb9635lpc";
+ };
+
+ microcode {
+ update@0 {
+#include "microcode/mc0306d4_00000018.dtsi"
+ };
+ };
+
+};
diff --git a/board/google/Kconfig b/board/google/Kconfig
index e9559c9080..7ba73a2461 100644
--- a/board/google/Kconfig
+++ b/board/google/Kconfig
@@ -36,9 +36,22 @@ config TARGET_CHROMEBOX_PANTHER
video output and a 16GB SATA solid state drive. There is no Chrome
OS EC on this model.
+config TARGET_CHROMEBOOK_SAMUS
+ bool "Chromebook samus"
+ help
+ This is the Chromebook Pixel released in 2015. It uses an Intel
+ Broadwell U Core i5 or Core i7 CPU with either 8GB or 16GB of
+ LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a
+ 720p webcam, USB SD reader, microphone and speakers, 2 USB 3 Type
+ C ports which can support charging and up to a 4K external display.
+ There is a solid state drive, either 32GB or 64GB. There is a
+ Chrome OS EC connected on LPC, and it provides a 2560x1700 high
+ resolution touch-enabled LCD display.
+
endchoice
source "board/google/chromebook_link/Kconfig"
source "board/google/chromebox_panther/Kconfig"
+source "board/google/chromebook_samus/Kconfig"
endif
diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig
new file mode 100644
index 0000000000..f2b9481563
--- /dev/null
+++ b/board/google/chromebook_samus/Kconfig
@@ -0,0 +1,40 @@
+if TARGET_CHROMEBOOK_SAMUS
+
+config SYS_BOARD
+ default "chromebook_samus"
+
+config SYS_VENDOR
+ default "google"
+
+config SYS_SOC
+ default "broadwell"
+
+config SYS_CONFIG_NAME
+ default "chromebook_samus"
+
+config SYS_TEXT_BASE
+ default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select X86_RESET_VECTOR
+ select INTEL_BROADWELL
+ select HAVE_INTEL_ME
+ select BOARD_ROMSIZE_KB_8192
+
+config PCIE_ECAM_BASE
+ default 0xf0000000
+
+config EARLY_POST_CROS_EC
+ bool "Enable early post to Chrome OS EC"
+ default y
+
+config SYS_CAR_ADDR
+ hex
+ default 0xff7c0000
+
+config SYS_CAR_SIZE
+ hex
+ default 0x40000
+
+endif
diff --git a/board/google/chromebook_samus/MAINTAINERS b/board/google/chromebook_samus/MAINTAINERS
new file mode 100644
index 0000000000..5500e46b40
--- /dev/null
+++ b/board/google/chromebook_samus/MAINTAINERS
@@ -0,0 +1,6 @@
+CHROMEBOOK SAMUS BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/google/chromebook_samus/
+F: include/configs/chromebook_samus.h
+F: configs/chromebook_samus_defconfig
diff --git a/board/google/chromebook_samus/Makefile b/board/google/chromebook_samus/Makefile
new file mode 100644
index 0000000000..152228678b
--- /dev/null
+++ b/board/google/chromebook_samus/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += samus.o
diff --git a/board/google/chromebook_samus/samus.c b/board/google/chromebook_samus/samus.c
new file mode 100644
index 0000000000..3c3f5d4833
--- /dev/null
+++ b/board/google/chromebook_samus/samus.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/cpu.h>
+
+int arch_early_init_r(void)
+{
+ return cpu_run_reference_code();
+}
+
+int board_early_init_f(void)
+{
+ return 0;
+}
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
new file mode 100644
index 0000000000..448446d5cf
--- /dev/null
+++ b/configs/chromebook_samus_defconfig
@@ -0,0 +1,51 @@
+CONFIG_X86=y
+CONFIG_SYS_MALLOC_F_LEN=0x1800
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
+CONFIG_TARGET_CHROMEBOOK_SAMUS=y
+CONFIG_ENABLE_MRC_CACHE=y
+CONFIG_HAVE_MRC=y
+CONFIG_HAVE_REFCODE=y
+CONFIG_SMP=y
+CONFIG_HAVE_VGA_BIOS=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_TPM_TEST=y
+CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_INTEL_BROADWELL_GPIO=y
+CONFIG_CMD_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_LPC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
+CONFIG_TPM_TIS_LPC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_VIDEO=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_VIDEO_BROADWELL_IGD=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_TPM=y
diff --git a/doc/README.x86 b/doc/README.x86
index 5b51559f41..c5c3010ee2 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -105,6 +105,87 @@ $ make all
---
+Chromebook Samus (2015 Pixel) instructions for bare mode:
+
+First, you need the following binary blobs:
+
+* descriptor.bin - Intel flash descriptor
+* me.bin - Intel Management Engine
+* mrc.bin - Memory Reference Code, which sets up SDRAM
+* refcode.elf - Additional Reference code
+* vga.bin - video ROM, which sets up the display
+
+If you have a samus you can obtain them from your flash, for example, in
+developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and
+log in as 'root'):
+
+ cd /tmp
+ flashrom -w samus.bin
+ scp samus.bin username@ip_address:/path/to/somewhere
+
+If not see the coreboot tree [4] where you can use:
+
+ bash crosfirmware.sh samus
+
+to get the image. There is also an 'extract_blobs.sh' scripts that you can use
+on the 'coreboot-Google_Samus.*' file to short-circuit some of the below.
+
+Then 'ifdtool -x samus.bin' on your development machine will produce:
+
+ flashregion_0_flashdescriptor.bin
+ flashregion_1_bios.bin
+ flashregion_2_intel_me.bin
+
+Rename flashregion_0_flashdescriptor.bin to descriptor.bin
+Rename flashregion_2_intel_me.bin to me.bin
+You can ignore flashregion_1_bios.bin - it is not used.
+
+To get the rest, use 'cbfstool samus.bin print':
+
+samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000
+alignment: 64 bytes, architecture: x86
+
+Name Offset Type Size
+cmos_layout.bin 0x700000 cmos_layout 1164
+pci8086,0406.rom 0x7004c0 optionrom 65536
+spd.bin 0x710500 (unknown) 4096
+cpu_microcode_blob.bin 0x711540 microcode 70720
+fallback/romstage 0x722a00 stage 54210
+fallback/ramstage 0x72fe00 stage 96382
+config 0x7476c0 raw 6075
+fallback/vboot 0x748ec0 stage 15980
+fallback/refcode 0x74cd80 stage 75578
+fallback/payload 0x75f500 payload 62878
+u-boot.dtb 0x76eb00 (unknown) 5318
+(empty) 0x770000 null 196504
+mrc.bin 0x79ffc0 (unknown) 222876
+(empty) 0x7d66c0 null 167320
+
+You can extract what you need:
+
+ cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
+ cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod
+ cbfstool samus.bin extract -n mrc.bin -f mrc.bin
+ cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U
+
+Note that the -U flag is only supported by the latest cbfstool. It unpacks
+and decompresses the stage to produce a coreboot rmodule. This is a simple
+representation of an ELF file. You need the patch "Support decoding a stage
+with compression".
+
+Put all 5 files into board/google/chromebook_samus.
+
+Now you can build U-Boot and obtain u-boot.rom:
+
+$ make chromebook_link_defconfig
+$ make all
+
+If you are using em100, then this command will flash write -Boot:
+
+ em100 -s -d filename.rom -c W25Q64CV -r
+
+---
+
Intel Crown Bay specific instructions for bare mode:
U-Boot support of Intel Crown Bay board [4] relies on a binary blob called
diff --git a/include/configs/chromebook_samus.h b/include/configs/chromebook_samus.h
new file mode 100644
index 0000000000..b89ba4154a
--- /dev/null
+++ b/include/configs/chromebook_samus.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+#include <configs/x86-chromebook.h>
+
+#undef CONFIG_CFB_CONSOLE
+
+#undef CONFIG_STD_DEVICES_SETTINGS
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
+ "stdout=vidconsole,serial\0" \
+ "stderr=vidconsole,serial\0"
+
+#define CONFIG_ENV_SECT_SIZE 0x1000
+#define CONFIG_ENV_OFFSET 0x003f8000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index c94096a349..312987edc8 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -21,7 +21,8 @@
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}, \
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI}
#define CONFIG_PCI_MEM_BUS 0xe0000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-30 01:33:48 +0000