diff options
| -rw-r--r-- | board/chromebook-x86/coreboot/chromeos.dtsi | 5 | ||||
| -rw-r--r-- | board/nvidia/seaboard/chromeos.dtsi | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/board/chromebook-x86/coreboot/chromeos.dtsi b/board/chromebook-x86/coreboot/chromeos.dtsi index 0e0147b068..c808354fee 100644 --- a/board/chromebook-x86/coreboot/chromeos.dtsi +++ b/board/chromebook-x86/coreboot/chromeos.dtsi @@ -12,6 +12,11 @@ chromeos-config { twostop; /* Two-stop boot */ twostop-optional; /* One-stop optimization enabled */ + + /* Memory addresses for kernel, cros-system and gbb */ + kernel = <0x00100000 0x00800000>; + cros-system-data = <0x00900000 0x8000>; + google-binary-block = <0x00908000 0x80000>; }; config { diff --git a/board/nvidia/seaboard/chromeos.dtsi b/board/nvidia/seaboard/chromeos.dtsi index c04ef8257b..0088121556 100644 --- a/board/nvidia/seaboard/chromeos.dtsi +++ b/board/nvidia/seaboard/chromeos.dtsi @@ -18,6 +18,11 @@ * Device and offset for second-stage firmware, in SPI for now * second-stage = <&emmc 0x00000080 0>; */ + + /* Memory addresses for kernel, cros-system and gbb */ + kernel = <0x00100000 0x00800000>; + cros-system-data = <0x00900000 0x8000>; + google-binary-block = <0x00908000 0x80000>; }; config { |