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-rw-r--r--arch/arm/mach-socfpga/include/mach/misc.h4
-rw-r--r--arch/arm/mach-socfpga/misc.c26
-rw-r--r--arch/arm/mach-socfpga/misc_arria10.c23
-rw-r--r--arch/arm/mach-socfpga/misc_gen5.c22
-rw-r--r--arch/arm/mach-socfpga/misc_s10.c22
-rw-r--r--drivers/fpga/altera.c6
-rw-r--r--include/altera.h4
7 files changed, 79 insertions, 28 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 26609927c8..86d5d2b62b 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -18,9 +18,9 @@ struct bsel {
extern struct bsel bsel_str[];
#ifdef CONFIG_FPGA
-void socfpga_fpga_add(void);
+void socfpga_fpga_add(void *fpga_desc);
#else
-static inline void socfpga_fpga_add(void) {}
+inline void socfpga_fpga_add(void *fpga_desc) {}
#endif
#ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index a4f6d5c1ac..78fbe28724 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -88,33 +88,11 @@ int overwrite_console(void)
#endif
#ifdef CONFIG_FPGA
-/*
- * FPGA programming support for SoC FPGA Cyclone V
- */
-static Altera_desc altera_fpga[] = {
- {
- /* Family */
- Altera_SoCFPGA,
- /* Interface type */
- fast_passive_parallel,
- /* No limitation as additional data will be ignored */
- -1,
- /* No device function table */
- NULL,
- /* Base interface address specified in driver */
- NULL,
- /* No cookie implementation */
- 0
- },
-};
-
/* add device descriptor to FPGA device table */
-void socfpga_fpga_add(void)
+void socfpga_fpga_add(void *fpga_desc)
{
- int i;
fpga_init();
- for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
- fpga_add(fpga_altera, &altera_fpga[i]);
+ fpga_add(fpga_altera, fpga_desc);
}
#endif
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index f347ae857e..63b8c75d31 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -30,6 +30,27 @@
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * FPGA programming support for SoC FPGA Arria 10
+ */
+static Altera_desc altera_fpga[] = {
+ {
+ /* Family */
+ Altera_SoCFPGA,
+ /* Interface type */
+ fast_passive_parallel,
+ /* No limitation as additional data will be ignored */
+ -1,
+ /* No device function table */
+ NULL,
+ /* Base interface address specified in driver */
+ NULL,
+ /* No cookie implementation */
+ 0
+ },
+};
+
#if defined(CONFIG_SPL_BUILD)
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -73,7 +94,7 @@ void socfpga_sdram_remap_zero(void)
int arch_early_init_r(void)
{
/* Add device descriptor to FPGA device table */
- socfpga_fpga_add();
+ socfpga_fpga_add(&altera_fpga[0]);
return 0;
}
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 5fa40937c4..04f237d100 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -35,6 +35,26 @@ static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
/*
+ * FPGA programming support for SoC FPGA Cyclone V
+ */
+static Altera_desc altera_fpga[] = {
+ {
+ /* Family */
+ Altera_SoCFPGA,
+ /* Interface type */
+ fast_passive_parallel,
+ /* No limitation as additional data will be ignored */
+ -1,
+ /* No device function table */
+ NULL,
+ /* Base interface address specified in driver */
+ NULL,
+ /* No cookie implementation */
+ 0
+ },
+};
+
+/*
* DesignWare Ethernet initialization
*/
#ifdef CONFIG_ETH_DESIGNWARE
@@ -221,7 +241,7 @@ int arch_early_init_r(void)
socfpga_sdram_remap_zero();
/* Add device descriptor to FPGA device table */
- socfpga_fpga_add();
+ socfpga_fpga_add(&altera_fpga[0]);
#ifdef CONFIG_DESIGNWARE_SPI
/* Get Designware SPI controller out of reset */
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index e599362f14..113eace650 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -25,6 +25,26 @@ static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
/*
+ * FPGA programming support for SoC FPGA Stratix 10
+ */
+static Altera_desc altera_fpga[] = {
+ {
+ /* Family */
+ Intel_FPGA_Stratix10,
+ /* Interface type */
+ secure_device_manager_mailbox,
+ /* No limitation as additional data will be ignored */
+ -1,
+ /* No device function table */
+ NULL,
+ /* Base interface address specified in driver */
+ NULL,
+ /* No cookie implementation */
+ 0
+ },
+};
+
+/*
* DesignWare Ethernet initialization
*/
#ifdef CONFIG_ETH_DESIGNWARE
@@ -125,6 +145,8 @@ int arch_misc_init(void)
int arch_early_init_r(void)
{
+ socfpga_fpga_add(&altera_fpga[0]);
+
return 0;
}
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index 9605554c6a..7c8f518509 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -39,6 +39,9 @@ static const struct altera_fpga {
#if defined(CONFIG_FPGA_STRATIX_V)
{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
#endif
+#if defined(CONFIG_FPGA_STRATIX10)
+ { Intel_FPGA_Stratix10, "Stratix10", stratix10_load, NULL, NULL },
+#endif
#if defined(CONFIG_FPGA_SOCFPGA)
{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
#endif
@@ -154,6 +157,9 @@ int altera_info(Altera_desc *desc)
case fast_passive_parallel_security:
printf("Fast Passive Parallel with Security (FPPS)\n");
break;
+ case secure_device_manager_mailbox:
+ puts("Secure Device Manager (SDM) Mailbox\n");
+ break;
/* Add new interface types here */
default:
printf("Unsupported interface type, %d\n", desc->iface);
diff --git a/include/altera.h b/include/altera.h
index 233b467dba..22d55cfd73 100644
--- a/include/altera.h
+++ b/include/altera.h
@@ -39,6 +39,8 @@ enum altera_iface {
fast_passive_parallel,
/* fast passive parallel with security (FPPS) */
fast_passive_parallel_security,
+ /* secure device manager (SDM) mailbox */
+ secure_device_manager_mailbox,
/* insert all new types before this */
max_altera_iface_type,
};
@@ -54,6 +56,8 @@ enum altera_family {
Altera_StratixII,
/* StratixV Family */
Altera_StratixV,
+ /* Stratix10 Family */
+ Intel_FPGA_Stratix10,
/* SoCFPGA Family */
Altera_SoCFPGA,
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-07 10:45:12 +0000