diff options
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/scg.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-imx/mx7ulp/clock.c | 15 | ||||
| -rw-r--r-- | arch/arm/mach-imx/mx7ulp/scg.c | 55 | ||||
| -rw-r--r-- | arch/arm/mach-imx/mx7ulp/soc.c | 8 |
4 files changed, 72 insertions, 7 deletions
diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h index b79bde338f4..72b4dc7d8ec 100644 --- a/arch/arm/include/asm/arch-mx7ulp/scg.h +++ b/arch/arm/include/asm/arch-mx7ulp/scg.h @@ -325,6 +325,7 @@ typedef struct scg_regs { u32 scg_clk_get_rate(enum scg_clk clk); int scg_enable_pll_pfd(enum scg_clk clk, u32 frac); +int scg_disable_pll_pfd(enum scg_clk clk); int scg_enable_usb_pll(bool usb_control); u32 decode_pll(enum pll_clocks pll); diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index 3c0bcccd0dc..6830b896083 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP */ #include <common.h> @@ -149,8 +150,8 @@ void init_clk_usdhc(u32 index) /*Disable the clock before configure it */ pcc_clock_enable(PER_CLK_USDHC0, false); - /* 158MHz / 1 = 158MHz */ - pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK); + /* 352.8MHz / 1 = 352.8MHz */ + pcc_clock_sel(PER_CLK_USDHC0, SCG_APLL_PFD1_CLK); pcc_clock_div_config(PER_CLK_USDHC0, false, 1); pcc_clock_enable(PER_CLK_USDHC0, true); break; @@ -158,9 +159,9 @@ void init_clk_usdhc(u32 index) /*Disable the clock before configure it */ pcc_clock_enable(PER_CLK_USDHC1, false); - /* 158MHz / 1 = 158MHz */ - pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK); - pcc_clock_div_config(PER_CLK_USDHC1, false, 1); + /* 352.8MHz / 2 = 176.4MHz */ + pcc_clock_sel(PER_CLK_USDHC1, SCG_APLL_PFD1_CLK); + pcc_clock_div_config(PER_CLK_USDHC1, false, 2); pcc_clock_enable(PER_CLK_USDHC1, true); break; default: @@ -303,8 +304,8 @@ void clock_init(void) scg_a7_init_core_clk(); - /* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */ - scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35); + /* APLL PFD1 = 352.8Mhz, PFD2=340.2Mhz, PFD3=793.8Mhz */ + scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 27); scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28); scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12); diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index c7bb7a1c667..b74e54ee88b 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -713,6 +713,61 @@ int scg_enable_pll_pfd(enum scg_clk clk, u32 frac) return 0; } +int scg_disable_pll_pfd(enum scg_clk clk) +{ + u32 reg; + u32 gate; + u32 addr; + + switch (clk) { + case SCG_SPLL_PFD0_CLK: + case SCG_APLL_PFD0_CLK: + gate = SCG_PLL_PFD0_GATE_MASK; + + if (clk == SCG_SPLL_PFD0_CLK) + addr = (u32)(&scg1_regs->spllpfd); + else + addr = (u32)(&scg1_regs->apllpfd); + break; + case SCG_SPLL_PFD1_CLK: + case SCG_APLL_PFD1_CLK: + gate = SCG_PLL_PFD1_GATE_MASK; + + if (clk == SCG_SPLL_PFD1_CLK) + addr = (u32)(&scg1_regs->spllpfd); + else + addr = (u32)(&scg1_regs->apllpfd); + break; + case SCG_SPLL_PFD2_CLK: + case SCG_APLL_PFD2_CLK: + gate = SCG_PLL_PFD2_GATE_MASK; + + if (clk == SCG_SPLL_PFD2_CLK) + addr = (u32)(&scg1_regs->spllpfd); + else + addr = (u32)(&scg1_regs->apllpfd); + break; + case SCG_SPLL_PFD3_CLK: + case SCG_APLL_PFD3_CLK: + gate = SCG_PLL_PFD3_GATE_MASK; + + if (clk == SCG_SPLL_PFD3_CLK) + addr = (u32)(&scg1_regs->spllpfd); + else + addr = (u32)(&scg1_regs->apllpfd); + break; + default: + return -EINVAL; + } + + /* Gate the PFD */ + reg = readl(addr); + reg |= gate; + writel(reg, addr); + + return 0; +} + #define SIM_MISC_CTRL0_USB_PLL_EN_MASK (0x1 << 2) int scg_enable_usb_pll(bool usb_control) { diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index a44b6d4e972..b83930c3fed 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP */ #include <cpu_func.h> #include <init.h> @@ -364,6 +365,13 @@ static char *get_reset_cause(char *ret) return ret; } +void arch_preboot_os(void) +{ + scg_disable_pll_pfd(SCG_APLL_PFD1_CLK); + scg_disable_pll_pfd(SCG_APLL_PFD2_CLK); + scg_disable_pll_pfd(SCG_APLL_PFD3_CLK); +} + #ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) { |