diff options
97 files changed, 3724 insertions, 1443 deletions
@@ -5,7 +5,7 @@ VERSION = 2016 PATCHLEVEL = 03 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d8b63e9407..6e5544f9d7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -690,15 +690,16 @@ config TARGET_COLIBRI_PXA270 config ARCH_UNIPHIER bool "Socionext UniPhier SoCs" select CLK_UNIPHIER - select CPU_V7 select SUPPORT_SPL select SPL select OF_CONTROL select SPL_OF_CONTROL select DM select SPL_DM + select DM_GPIO select DM_SERIAL select DM_I2C + select DM_MMC help Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 1ec79a6f35..3ebdfddc80 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -78,7 +78,7 @@ cpu_init_crit: mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00000002 @ set bit 1 (A) Align orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 4c0ab4d0ee..a602d4e693 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -78,7 +78,7 @@ cpu_init_crit: mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00000002 @ set bit 1 (A) Align orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache /* Prepare to disable the MMU */ diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 07404502c8..69cabebed9 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -131,7 +131,7 @@ cpu_init_crit: mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00000002 @ set bit 1 (A) Align orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 82cc1c9477..f05113da9d 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -95,7 +95,7 @@ flush_dcache: #else bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ #endif - orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ + orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ #ifndef CONFIG_SYS_ICACHE_OFF orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ #endif diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index b55395aa53..214cd8cbd9 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -86,7 +86,7 @@ cpu_init_crit: mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ - orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ + orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ mcr p15, 0, r0, c1, c0, 0 diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 652d319a08..c6168e98d7 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -110,7 +110,7 @@ config TARGET_OMAP3_CAIRO select DM_GPIO config TARGET_SNIPER - bool "Sniper" + bool "LG Optimus Black" select SUPPORT_SPL select DM select DM_SERIAL diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 879390be2d..24b6ad187a 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -100,7 +100,7 @@ cpu_init_crit: mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS) bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00000002 @ set bit 1 (A) Align mcr p15, 0, r0, c1, c0, 0 mov pc, lr /* back to my caller */ diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index eebff661f8..408b70dbc1 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -112,7 +112,7 @@ cpu_init_crit: bic r0, r0, #0x00002000 @ clear bit 13 (X) bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) orr r0, r0, #0x00001000 @ set bit 12 (I) Icache - orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00000002 @ set bit 1 (A) Align mcr p15,0,r0,c1,c0 /* diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi index 59511bde94..7d59112ddd 100644 --- a/arch/arm/dts/uniphier-common32.dtsi +++ b/arch/arm/dts/uniphier-common32.dtsi @@ -23,12 +23,6 @@ ranges; interrupt-parent = <&intc>; - extbus: extbus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - }; - serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -69,9 +63,16 @@ clocks = <&uart_clk>; }; - system-bus-controller@58c00000 { - compatible = "socionext,uniphier-system-bus-controller"; - reg = <0x58c00000 0x400>, <0x59800000 0x2000>; + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; }; mio: mioctrl@59810000 { diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts index f62916da39..d7b000796e 100644 --- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts @@ -51,6 +51,10 @@ status = "okay"; }; +&sd { + status = "okay"; +}; + &usb0 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi index 7c8759f929..5ae029ea97 100644 --- a/arch/arm/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi @@ -56,6 +56,118 @@ cache-level = <2>; }; + port0x: gpio@55000008 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000008 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port1x: gpio@55000010 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000010 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port2x: gpio@55000018 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000018 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port3x: gpio@55000020 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000020 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port4: gpio@55000028 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000028 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port5x: gpio@55000030 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000030 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port6x: gpio@55000038 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000038 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port7x: gpio@55000040 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000040 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port8x: gpio@55000048 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000048 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port9x: gpio@55000050 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000050 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port10x: gpio@55000058 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000058 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port11x: gpio@55000060 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000060 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port12x: gpio@55000068 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000068 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port13x: gpio@55000070 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000070 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port14x: gpio@55000078 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000078 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port16x: gpio@55000088 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000088 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + i2c0: i2c@58400000 { compatible = "socionext,uniphier-i2c"; status = "disabled"; @@ -108,6 +220,31 @@ clock-frequency = <100000>; }; + sd: sdhc@5a400000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a400000 0x200>; + interrupts = <0 76 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_1v8>; + clocks = <&mio 0>; + bus-width = <4>; + }; + + emmc: sdhc@5a500000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a500000 0x200>; + interrupts = <0 78 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_emmc>; + pinctrl-1 = <&pinctrl_emmc_1v8>; + clocks = <&mio 1>; + bus-width = <8>; + non-removable; + }; + usb0: usb@5a800100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts index dca408bb70..13a29fdfaa 100644 --- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts @@ -53,6 +53,10 @@ status = "okay"; }; +&sd { + status = "okay"; +}; + &usb0 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-ph1-pro4-ace.dts b/arch/arm/dts/uniphier-ph1-pro4-ace.dts index 6e741ea45b..37e0853365 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-ace.dts +++ b/arch/arm/dts/uniphier-ph1-pro4-ace.dts @@ -69,6 +69,10 @@ status = "okay"; }; +&sd { + status = "okay"; +}; + &usb0 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts index 202a642a4d..07a9783357 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts @@ -54,6 +54,14 @@ status = "okay"; }; +&sd { + status = "okay"; +}; + +&sd1 { + status = "okay"; +}; + &usb0 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts index 91a71ef469..82e2bd02c7 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts +++ b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts @@ -64,6 +64,10 @@ status = "okay"; }; +&emmc { + status = "okay"; +}; + &usb0 { status = "okay"; }; @@ -91,6 +95,14 @@ u-boot,dm-pre-reloc; }; +&mio { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + &pinctrl { u-boot,dm-pre-reloc; }; @@ -98,3 +110,7 @@ &pinctrl_uart0 { u-boot,dm-pre-reloc; }; + +&pinctrl_emmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index cb5b8f1a86..d5767b6252 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -64,6 +64,209 @@ cache-level = <2>; }; + port0x: gpio@55000008 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000008 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port1x: gpio@55000010 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000010 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port2x: gpio@55000018 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000018 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port3x: gpio@55000020 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000020 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port4: gpio@55000028 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000028 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port5x: gpio@55000030 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000030 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port6x: gpio@55000038 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000038 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port7x: gpio@55000040 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000040 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port8x: gpio@55000048 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000048 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port9x: gpio@55000050 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000050 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port10x: gpio@55000058 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000058 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port11x: gpio@55000060 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000060 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port12x: gpio@55000068 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000068 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port13x: gpio@55000070 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000070 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port14x: gpio@55000078 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000078 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port17x: gpio@550000a0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000a0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port18x: gpio@550000a8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000a8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port19x: gpio@550000b0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000b0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port20x: gpio@550000b8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000b8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port21x: gpio@550000c0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000c0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port22x: gpio@550000c8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000c8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port23x: gpio@550000d0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000d0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port24x: gpio@550000d8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000d8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port25x: gpio@550000e0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000e0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port26x: gpio@550000e8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000e8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port27x: gpio@550000f0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000f0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port28x: gpio@550000f8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000f8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port29x: gpio@55000100 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000100 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port30x: gpio@55000108 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000108 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + i2c0: i2c@58780000 { compatible = "socionext,uniphier-fi2c"; status = "disabled"; @@ -140,6 +343,43 @@ clock-frequency = <400000>; }; + sd: sdhc@5a400000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a400000 0x200>; + interrupts = <0 76 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_1v8>; + clocks = <&mio 0>; + bus-width = <4>; + }; + + emmc: sdhc@5a500000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a500000 0x200>; + interrupts = <0 78 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_emmc>; + pinctrl-1 = <&pinctrl_emmc_1v8>; + clocks = <&mio 1>; + bus-width = <8>; + non-removable; + }; + + sd1: sdhc@5a600000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a600000 0x200>; + interrupts = <0 85 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_sd1>; + pinctrl-1 = <&pinctrl_sd1_1v8>; + clocks = <&mio 2>; + bus-width = <4>; + }; + usb2: usb@5a800100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts index 02a3362e74..cbdc3ebbff 100644 --- a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts +++ b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts @@ -47,6 +47,14 @@ status = "okay"; }; +&emmc { + status = "okay"; +}; + +&sd { + status = "okay"; +}; + /* for U-Boot only */ / { soc { diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi index 087b25a950..bd1b4b1b66 100644 --- a/arch/arm/dts/uniphier-ph1-pro5.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi @@ -76,6 +76,209 @@ cache-level = <3>; }; + port0x: gpio@55000008 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000008 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port1x: gpio@55000010 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000010 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port2x: gpio@55000018 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000018 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port3x: gpio@55000020 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000020 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port4: gpio@55000028 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000028 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port5x: gpio@55000030 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000030 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port6x: gpio@55000038 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000038 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port7x: gpio@55000040 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000040 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port8x: gpio@55000048 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000048 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port9x: gpio@55000050 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000050 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port10x: gpio@55000058 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000058 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port11x: gpio@55000060 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000060 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port12x: gpio@55000068 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000068 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port13x: gpio@55000070 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000070 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port14x: gpio@55000078 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000078 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port17x: gpio@550000a0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000a0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port18x: gpio@550000a8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000a8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port19x: gpio@550000b0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000b0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port20x: gpio@550000b8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000b8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port21x: gpio@550000c0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000c0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port22x: gpio@550000c8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000c8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port23x: gpio@550000d0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000d0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port24x: gpio@550000d8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000d8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port25x: gpio@550000e0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000e0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port26x: gpio@550000e8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000e8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port27x: gpio@550000f0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000f0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port28x: gpio@550000f8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000f8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port29x: gpio@55000100 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000100 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port30x: gpio@55000108 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000108 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + i2c0: i2c@58780000 { compatible = "socionext,uniphier-fi2c"; status = "disabled"; @@ -152,6 +355,30 @@ clock-frequency = <400000>; }; + emmc: sdhc@68400000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x68400000 0x800>; + interrupts = <0 78 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc>; + clocks = <&mio 1>; + bus-width = <8>; + non-removable; + }; + + sd: sdhc@68800000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x68800000 0x800>; + interrupts = <0 76 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_1v8>; + clocks = <&mio 0>; + bus-width = <4>; + }; + usb0: usb@65a00000 { compatible = "socionext,uniphier-xhci", "generic-xhci"; status = "disabled"; diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts index ff17945e90..c7213c9ff4 100644 --- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts @@ -52,6 +52,10 @@ status = "okay"; }; +&sd { + status = "okay"; +}; + &usb0 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi index 85dde66f07..789713db12 100644 --- a/arch/arm/dts/uniphier-ph1-sld3.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi @@ -62,12 +62,6 @@ ranges; interrupt-parent = <&intc>; - extbus: extbus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - }; - timer@20000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x20000200 0x20>; @@ -117,6 +111,118 @@ clock-frequency = <36864000>; }; + port0x: gpio@55000008 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000008 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port1x: gpio@55000010 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000010 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port2x: gpio@55000018 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000018 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port3x: gpio@55000020 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000020 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port4: gpio@55000028 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000028 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port5x: gpio@55000030 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000030 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port6x: gpio@55000038 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000038 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port7x: gpio@55000040 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000040 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port8x: gpio@55000048 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000048 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port9x: gpio@55000050 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000050 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port10x: gpio@55000058 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000058 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port11x: gpio@55000060 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000060 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port12x: gpio@55000068 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000068 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port13x: gpio@55000070 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000070 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port14x: gpio@55000078 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000078 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port16x: gpio@55000088 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000088 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + i2c0: i2c@58400000 { compatible = "socionext,uniphier-i2c"; status = "disabled"; @@ -172,10 +278,16 @@ clock-frequency = <400000>; }; - system-bus-controller-misc@59800000 { - compatible = "socionext,uniphier-system-bus-controller-misc", - "syscon"; - reg = <0x59800000 0x2000>; + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; }; mio: mioctrl@59810000 { @@ -186,6 +298,25 @@ clocks = <&sysctrl 10>, <&sysctrl 18>; }; + emmc: sdhc@5a400000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a400000 0x200>; + interrupts = <0 78 4>; + clocks = <&mio 1>; + bus-width = <8>; + non-removable; + }; + + sd: sdhc@5a500000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a500000 0x200>; + interrupts = <0 76 4>; + clocks = <&mio 0>; + bus-width = <4>; + }; + usb0: usb@5a800100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts index b5b6f65d36..ec5c5bdadc 100644 --- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts @@ -51,6 +51,10 @@ status = "okay"; }; +&sd { + status = "okay"; +}; + &usb0 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi index f93db83661..61e0b45781 100644 --- a/arch/arm/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi @@ -56,6 +56,118 @@ cache-level = <2>; }; + port0x: gpio@55000008 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000008 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port1x: gpio@55000010 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000010 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port2x: gpio@55000018 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000018 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port3x: gpio@55000020 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000020 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port4: gpio@55000028 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000028 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port5x: gpio@55000030 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000030 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port6x: gpio@55000038 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000038 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port7x: gpio@55000040 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000040 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port8x: gpio@55000048 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000048 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port9x: gpio@55000050 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000050 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port10x: gpio@55000058 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000058 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port11x: gpio@55000060 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000060 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port12x: gpio@55000068 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000068 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port13x: gpio@55000070 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000070 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port14x: gpio@55000078 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000078 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port16x: gpio@55000088 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000088 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + i2c0: i2c@58400000 { compatible = "socionext,uniphier-i2c"; status = "disabled"; @@ -108,6 +220,31 @@ clock-frequency = <100000>; }; + sd: sdhc@5a400000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a400000 0x200>; + interrupts = <0 76 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_1v8>; + clocks = <&mio 0>; + bus-width = <4>; + }; + + emmc: sdhc@5a500000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + interrupts = <0 78 4>; + reg = <0x5a500000 0x200>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_emmc>; + pinctrl-1 = <&pinctrl_emmc_1v8>; + clocks = <&mio 1>; + bus-width = <8>; + non-removable; + }; + usb0: usb@5a800100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi index b1691d0679..494139a05d 100644 --- a/arch/arm/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/dts/uniphier-pinctrl.dtsi @@ -12,6 +12,11 @@ function = "emmc"; }; + pinctrl_emmc_1v8: emmc_grp_1v8 { + groups = "emmc", "emmc_dat8"; + function = "emmc"; + }; + pinctrl_i2c0: i2c0_grp { groups = "i2c0"; function = "i2c0"; @@ -37,11 +42,21 @@ function = "sd"; }; + pinctrl_sd_1v8: sd_grp_1v8 { + groups = "sd"; + function = "sd"; + }; + pinctrl_sd1: sd1_grp { groups = "sd1"; function = "sd1"; }; + pinctrl_sd1_1v8: sd1_grp_1v8 { + groups = "sd1"; + function = "sd1"; + }; + pinctrl_uart0: uart0_grp { groups = "uart0"; function = "uart0"; diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts index dc0def30fd..eb1d2bcc63 100644 --- a/arch/arm/dts/uniphier-proxstream2-gentil.dts +++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts @@ -52,6 +52,10 @@ status = "okay"; }; +&emmc { + status = "okay"; +}; + &usb0 { status = "okay"; }; @@ -71,6 +75,14 @@ u-boot,dm-pre-reloc; }; +&mio { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + &pinctrl { u-boot,dm-pre-reloc; }; @@ -78,3 +90,7 @@ &pinctrl_uart2 { u-boot,dm-pre-reloc; }; + +&pinctrl_emmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts index 3703ad36a5..e7d5db8894 100644 --- a/arch/arm/dts/uniphier-proxstream2-vodka.dts +++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts @@ -41,6 +41,10 @@ status = "okay"; }; +&emmc { + status = "okay"; +}; + &usb0 { status = "okay"; }; @@ -56,6 +60,14 @@ u-boot,dm-pre-reloc; }; +&mio { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + &pinctrl { u-boot,dm-pre-reloc; }; @@ -63,3 +75,7 @@ &pinctrl_uart2 { u-boot,dm-pre-reloc; }; + +&pinctrl_emmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi index 2d324f95a4..12968bdd17 100644 --- a/arch/arm/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/dts/uniphier-proxstream2.dtsi @@ -78,6 +78,202 @@ cache-level = <2>; }; + port0x: gpio@55000008 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000008 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port1x: gpio@55000010 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000010 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port2x: gpio@55000018 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000018 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port3x: gpio@55000020 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000020 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port4: gpio@55000028 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000028 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port5x: gpio@55000030 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000030 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port6x: gpio@55000038 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000038 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port7x: gpio@55000040 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000040 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port8x: gpio@55000048 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000048 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port9x: gpio@55000050 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000050 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port10x: gpio@55000058 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000058 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port12x: gpio@55000068 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000068 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port13x: gpio@55000070 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000070 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port14x: gpio@55000078 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000078 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port15x: gpio@55000080 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000080 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port16x: gpio@55000088 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000088 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port17x: gpio@550000a0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000a0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port18x: gpio@550000a8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000a8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port19x: gpio@550000b0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000b0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port20x: gpio@550000b8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000b8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port21x: gpio@550000c0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000c0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port22x: gpio@550000c8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000c8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port23x: gpio@550000d0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000d0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port24x: gpio@550000d8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000d8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port25x: gpio@550000e0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000e0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port26x: gpio@550000e8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000e8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port27x: gpio@550000f0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000f0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port28x: gpio@550000f8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000f8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + i2c0: i2c@58780000 { compatible = "socionext,uniphier-fi2c"; status = "disabled"; @@ -163,6 +359,30 @@ clock-frequency = <400000>; }; + emmc: sdhc@5a000000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a000000 0x800>; + interrupts = <0 78 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc>; + clocks = <&mio 1>; + bus-width = <8>; + non-removable; + }; + + sd: sdhc@5a400000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a400000 0x800>; + interrupts = <0 76 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_1v8>; + clocks = <&mio 0>; + bus-width = <4>; + }; + usb0: usb@65a00000 { compatible = "socionext,uniphier-xhci", "generic-xhci"; status = "disabled"; diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 0e2bd5366c..a140be05f1 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -34,7 +34,7 @@ PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE) #define VF610_GPIO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_IBE_ENABLE) + PAD_CTL_IBE_ENABLE) #define VF610_DSPI_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_DSE_20ohm | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH) diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index d49ad080e2..fe4419cae4 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,2 +1,4 @@ +#ifndef CONFIG_ARCH_UNIPHIER #include <asm/arch/gpio.h> +#endif #include <asm-generic/gpio.h> diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 03256be403..660f83c855 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -3,54 +3,52 @@ if ARCH_UNIPHIER config SYS_CONFIG_NAME default "uniphier" +choice + prompt "UniPhier SoC select" + default ARCH_UNIPHIER_PH1_PRO4 + config ARCH_UNIPHIER_PH1_SLD3 bool "UniPhier PH1-sLD3 SoC" - help - This enables support for UniPhier PH1-sLD3 SoC. + select CPU_V7 -config ARCH_UNIPHIER_PH1_LD4 - bool "UniPhier PH1-LD4 SoC" - depends on !ARCH_UNIPHIER_PH1_SLD3 - help - This enables support for UniPhier PH1-LD4 SoC. +config ARCH_UNIPHIER_LD4_SLD8 + bool "UniPhier PH1-LD4/PH1-sLD8 SoC" + select CPU_V7 config ARCH_UNIPHIER_PH1_PRO4 bool "UniPhier PH1-Pro4 SoC" - depends on !ARCH_UNIPHIER_PH1_SLD3 && \ - !ARCH_UNIPHIER_PH1_LD4 && \ - !ARCH_UNIPHIER_PH1_SLD8 - help - This enables support for UniPhier PH1-Pro4 SoC. + select CPU_V7 + +config ARCH_UNIPHIER_PRO5_PXS2_LD6B + bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC" + select CPU_V7 + +endchoice + +config ARCH_UNIPHIER_PH1_LD4 + bool "Enable UniPhier PH1-LD4 SoC support" + depends on ARCH_UNIPHIER_LD4_SLD8 + default y config ARCH_UNIPHIER_PH1_SLD8 - bool "UniPhier PH1-sLD8 SoC" - depends on !ARCH_UNIPHIER_PH1_SLD3 - help - This enables support for UniPhier PH1-sLD8 SoC. + bool "Enable UniPhier PH1-sLD8 SoC support" + depends on ARCH_UNIPHIER_LD4_SLD8 + default y config ARCH_UNIPHIER_PH1_PRO5 - bool "UniPhier PH1-Pro5 SoC" - depends on !ARCH_UNIPHIER_PH1_SLD3 && \ - !ARCH_UNIPHIER_PH1_LD4 && \ - !ARCH_UNIPHIER_PH1_SLD8 - help - This enables support for UniPhier PH1-Pro5 SoC. + bool "Enable UniPhier PH1-Pro5 SoC support" + depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B + default y config ARCH_UNIPHIER_PROXSTREAM2 - bool "UniPhier ProXstream2 SoC" - depends on !ARCH_UNIPHIER_PH1_SLD3 && \ - !ARCH_UNIPHIER_PH1_LD4 && \ - !ARCH_UNIPHIER_PH1_SLD8 - help - This enables support for UniPhier ProXstream2 SoC. + bool "Enable UniPhier ProXstream2 SoC support" + depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B + default y config ARCH_UNIPHIER_PH1_LD6B - bool "UniPhier PH1-LD6b SoC" - depends on !ARCH_UNIPHIER_PH1_SLD3 && \ - !ARCH_UNIPHIER_PH1_LD4 && \ - !ARCH_UNIPHIER_PH1_SLD8 - help - This enables support for UniPhier PH1-LD6b SoC. + bool "Enable UniPhier PH1-LD6b SoC support" + depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B + default y config MICRO_SUPPORT_CARD bool "Use Micro Support Card" diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index e65d602350..1a8c649964 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -4,16 +4,11 @@ ifdef CONFIG_SPL_BUILD -obj-y += lowlevel_init.o - obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ -obj-$(CONFIG_DEBUG_LL) += debug_ll.o - else -obj-y += late_lowlevel_init.o obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o @@ -22,16 +17,16 @@ obj-y += board_common.o obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o obj-y += reset.o -obj-y += cache_uniphier.o obj-y += pinctrl/ clk/ endif -obj-y += timer.o obj-y += boards.o obj-y += soc_info.o obj-y += boot-mode/ obj-y += dram/ obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o + +obj-$(CONFIG_CPU_V7) += arm32/ diff --git a/arch/arm/mach-uniphier/arm32/Makefile b/arch/arm/mach-uniphier/arm32/Makefile new file mode 100644 index 0000000000..376c06b597 --- /dev/null +++ b/arch/arm/mach-uniphier/arm32/Makefile @@ -0,0 +1,13 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += lowlevel_init.o +obj-$(CONFIG_DEBUG_LL) += debug_ll.o +else +obj-y += late_lowlevel_init.o +obj-y += cache_uniphier.o +endif + +obj-y += timer.o diff --git a/arch/arm/mach-uniphier/arm-mpcore.h b/arch/arm/mach-uniphier/arm32/arm-mpcore.h index cf7cd46c10..cf7cd46c10 100644 --- a/arch/arm/mach-uniphier/arm-mpcore.h +++ b/arch/arm/mach-uniphier/arm32/arm-mpcore.h diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/arm32/cache_uniphier.c index 4398114658..4398114658 100644 --- a/arch/arm/mach-uniphier/cache_uniphier.c +++ b/arch/arm/mach-uniphier/arm32/cache_uniphier.c diff --git a/arch/arm/mach-uniphier/debug_ll.S b/arch/arm/mach-uniphier/arm32/debug_ll.S index 6aa5f897a1..a70954cbee 100644 --- a/arch/arm/mach-uniphier/debug_ll.S +++ b/arch/arm/mach-uniphier/arm32/debug_ll.S @@ -9,9 +9,9 @@ #include <linux/serial_reg.h> #include <linux/linkage.h> -#include "bcu/bcu-regs.h" -#include "sc-regs.h" -#include "sg-regs.h" +#include "../bcu/bcu-regs.h" +#include "../sc-regs.h" +#include "../sg-regs.h" #if !defined(CONFIG_DEBUG_SEMIHOSTING) #include CONFIG_DEBUG_LL_INCLUDE diff --git a/arch/arm/mach-uniphier/late_lowlevel_init.S b/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S index cce91dfac7..cce91dfac7 100644 --- a/arch/arm/mach-uniphier/late_lowlevel_init.S +++ b/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S index dd03ad8143..dd03ad8143 100644 --- a/arch/arm/mach-uniphier/lowlevel_init.S +++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S diff --git a/arch/arm/mach-uniphier/ssc-regs.h b/arch/arm/mach-uniphier/arm32/ssc-regs.h index 02fca3b6f6..02fca3b6f6 100644 --- a/arch/arm/mach-uniphier/ssc-regs.h +++ b/arch/arm/mach-uniphier/arm32/ssc-regs.h diff --git a/arch/arm/mach-uniphier/timer.c b/arch/arm/mach-uniphier/arm32/timer.c index a34e30b72b..a34e30b72b 100644 --- a/arch/arm/mach-uniphier/timer.c +++ b/arch/arm/mach-uniphier/arm32/timer.c diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c index f82c7d1f8e..bbe8a74ce3 100644 --- a/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c +++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c @@ -22,7 +22,7 @@ int ph1_ld4_bcu_init(const struct uniphier_board_data *bd) writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */ /* Specify DDR channel */ - shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4; + shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4; writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ shift -= 32; diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c index 75ccd155b0..b7497e9e57 100644 --- a/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c +++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c @@ -26,7 +26,7 @@ int ph1_sld3_bcu_init(const struct uniphier_board_data *bd) writel(0x24440000, BCSCR5); /* Specify DDR channel */ - shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4; + shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4; writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ shift -= 32; diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index d70c712206..408aff0cd0 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -14,106 +14,154 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) static const struct uniphier_board_data ph1_sld3_data = { - .dram_ch0_base = 0x80000000, - .dram_ch0_size = 0x20000000, - .dram_ch0_width = 32, - .dram_ch1_base = 0xc0000000, - .dram_ch1_size = 0x20000000, - .dram_ch1_width = 16, - .dram_ch2_base = 0xc0000000, - .dram_ch2_size = 0x10000000, - .dram_ch2_width = 16, - .dram_freq = 1600, + .dram_freq = 1600, + .dram_nr_ch = 3, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x20000000, + .width = 32, + }, + .dram_ch[1] = { + .base = 0xc0000000, + .size = 0x20000000, + .width = 16, + }, + .dram_ch[2] = { + .base = 0xc0000000, + .size = 0x10000000, + .width = 16, + }, }; #endif #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) static const struct uniphier_board_data ph1_ld4_data = { - .dram_ch0_base = 0x80000000, - .dram_ch0_size = 0x10000000, - .dram_ch0_width = 16, - .dram_ch1_base = 0x90000000, - .dram_ch1_size = 0x10000000, - .dram_ch1_width = 16, - .dram_freq = 1600, + .dram_freq = 1600, + .dram_nr_ch = 2, + .dram_ddr3plus = true, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x10000000, + .width = 16, + }, + .dram_ch[1] = { + .base = 0x90000000, + .size = 0x10000000, + .width = 16, + }, }; #endif #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) /* 1GB RAM board */ static const struct uniphier_board_data ph1_pro4_data = { - .dram_ch0_base = 0x80000000, - .dram_ch0_size = 0x20000000, - .dram_ch0_width = 32, - .dram_ch1_base = 0xa0000000, - .dram_ch1_size = 0x20000000, - .dram_ch1_width = 32, - .dram_freq = 1600, + .dram_freq = 1600, + .dram_nr_ch = 2, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x20000000, + .width = 32, + }, + .dram_ch[1] = { + .base = 0xa0000000, + .size = 0x20000000, + .width = 32, + }, }; /* 2GB RAM board */ static const struct uniphier_board_data ph1_pro4_2g_data = { - .dram_ch0_base = 0x80000000, - .dram_ch0_size = 0x40000000, - .dram_ch0_width = 32, - .dram_ch1_base = 0xc0000000, - .dram_ch1_size = 0x40000000, - .dram_ch1_width = 32, - .dram_freq = 1600, + .dram_freq = 1600, + .dram_nr_ch = 2, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x40000000, + .width = 32, + }, + .dram_ch[1] = { + .base = 0xc0000000, + .size = 0x40000000, + .width = 32, + }, }; #endif #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) static const struct uniphier_board_data ph1_sld8_data = { - .dram_ch0_base = 0x80000000, - .dram_ch0_size = 0x10000000, - .dram_ch0_width = 16, - .dram_ch1_base = 0x90000000, - .dram_ch1_size = 0x10000000, - .dram_ch1_width = 16, - .dram_freq = 1333, + .dram_freq = 1333, + .dram_nr_ch = 2, + .dram_ddr3plus = true, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x10000000, + .width = 16, + }, + .dram_ch[1] = { + .base = 0x90000000, + .size = 0x10000000, + .width = 16, + }, }; #endif #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5) static const struct uniphier_board_data ph1_pro5_data = { - .dram_ch0_base = 0x80000000, - .dram_ch0_size = 0x20000000, - .dram_ch0_width = 32, - .dram_ch1_base = 0xa0000000, - .dram_ch1_size = 0x20000000, - .dram_ch1_width = 32, - .dram_freq = 1866, + .dram_freq = 1866, + .dram_nr_ch = 2, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x20000000, + .width = 32, + }, + .dram_ch[1] = { + .base = 0xa0000000, + .size = 0x20000000, + .width = 32, + }, }; #endif #if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) static const struct uniphier_board_data proxstream2_data = { - .dram_ch0_base = 0x80000000, - .dram_ch0_size = 0x40000000, - .dram_ch0_width = 32, - .dram_ch1_base = 0xc0000000, - .dram_ch1_size = 0x20000000, - .dram_ch1_width = 32, - .dram_ch2_base = 0xe0000000, - .dram_ch2_size = 0x20000000, - .dram_ch2_width = 16, - .dram_freq = 2133, + .dram_freq = 2133, + .dram_nr_ch = 3, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x40000000, + .width = 32, + }, + .dram_ch[1] = { + .base = 0xc0000000, + .size = 0x20000000, + .width = 32, + }, + .dram_ch[2] = { + .base = 0xe0000000, + .size = 0x20000000, + .width = 16, + }, }; #endif #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) static const struct uniphier_board_data ph1_ld6b_data = { - .dram_ch0_base = 0x80000000, - .dram_ch0_size = 0x40000000, - .dram_ch0_width = 32, - .dram_ch1_base = 0xc0000000, - .dram_ch1_size = 0x20000000, - .dram_ch1_width = 32, - .dram_ch2_base = 0xe0000000, - .dram_ch2_size = 0x20000000, - .dram_ch2_width = 16, - .dram_freq = 1866, + .dram_freq = 1866, + .dram_nr_ch = 3, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x40000000, + .width = 32, + }, + .dram_ch[1] = { + .base = 0xc0000000, + .size = 0x20000000, + .width = 32, + }, + .dram_ch[2] = { + .base = 0xe0000000, + .size = 0x20000000, + .width = 16, + }, }; #endif diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c index 935e551472..cf39bf57e9 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c @@ -5,7 +5,9 @@ */ #include <common.h> +#include <mmc.h> #include <spl.h> +#include <linux/err.h> #include "../sbc/sbc-regs.h" #include "../soc-info.h" @@ -52,3 +54,65 @@ u32 spl_boot_device(void) return ret == BOOT_DEVICE_USB ? BOOT_DEVICE_NOR : ret; } + +u32 spl_boot_mode(void) +{ + struct mmc *mmc; + + /* + * work around a bug in the Boot ROM of PH1-sLD3, LD4, Pro4, and sLD8: + * + * The boot ROM in these SoCs breaks the PARTITION_CONFIG [179] of + * Extended CSD register; when switching to the Boot Partition 1, the + * Boot ROM should issue the SWITCH command (CMD6) with Set Bits for + * the Access Bits, but in fact it uses Write Byte for the Access Bits. + * As a result, the BOOT_PARTITION_ENABLE field of the PARTITION_CONFIG + * is lost. This bug was fixed for PH1-Pro5 and later SoCs. + * + * Fixup mmc->part_config here because it is used to determine the + * partition which the U-Boot image is read from. + */ + mmc = find_mmc_device(0); + mmc->part_config &= ~EXT_CSD_BOOT_PART_NUM(PART_ACCESS_MASK); + mmc->part_config |= EXT_CSD_BOOT_PARTITION_ENABLE; + + return MMCSD_MODE_EMMCBOOT; +} + +#if defined(CONFIG_DM_MMC) && !defined(CONFIG_SPL_BUILD) +static int find_first_mmc_device(void) +{ + struct mmc *mmc; + int i; + + for (i = 0; (mmc = find_mmc_device(i)); i++) { + if (!mmc_init(mmc) && IS_MMC(mmc)) + return i; + } + + return -ENODEV; +} + +int mmc_get_env_dev(void) +{ + return find_first_mmc_device(); +} + +static int do_mmcsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int dev; + + dev = find_first_mmc_device(); + if (dev < 0) + return CMD_RET_FAILURE; + + setenv_ulong("mmc_first_dev", dev); + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD( + mmcsetn, 1, 1, do_mmcsetn, + "Set the first MMC (not SD) dev number to \"mmc_first_dev\" enviroment", + "" +); +#endif diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c index 4e9d01bafd..aae8d1fabd 100644 --- a/arch/arm/mach-uniphier/cpu_info.c +++ b/arch/arm/mach-uniphier/cpu_info.c @@ -45,10 +45,10 @@ int print_cpuinfo(void) puts("PH1-LD6b (MN2WS0320)"); break; case 0x31: - puts("PH1-sLD11 ()"); + puts("PH1-LD11 ()"); break; case 0x32: - puts("PH1-LD10 ()"); + puts("PH1-LD20 ()"); break; default: printf("Unknown Processor ID (0x%x)\n", revision); diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile index a0a6003065..3d1553cbe1 100644 --- a/arch/arm/mach-uniphier/dram/Makefile +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -7,9 +7,9 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o \ ddrphy-training.o ddrphy-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o \ - ddrphy-training.o ddrphy-ph1-pro4.o + ddrphy-training.o ddrphy-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o \ - ddrphy-training.o ddrphy-ph1-sld8.o + ddrphy-training.o ddrphy-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += umc-proxstream2.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += umc-proxstream2.o diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c index d2bc5a15d4..eb9bf24da0 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c @@ -4,31 +4,52 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <common.h> +#include <linux/err.h> #include <linux/types.h> #include <linux/io.h> #include "ddrphy-regs.h" -int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +enum dram_freq { + DRAM_FREQ_1333M, + DRAM_FREQ_1600M, + DRAM_FREQ_NR, +}; + +static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0a806844, 0x0c807d04}; +static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x208e0124, 0x2710015E}; +static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x0f051616, 0x12061A80}; +static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x06ae08d6, 0x08027100}; +static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x85589955, 0x999cbb66}; +static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x1a8363c0, 0x1a878400}; +static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8}; +static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71}; +static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298}; + +int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus) { + enum dram_freq freq_e; u32 tmp; - writel(0x0300c473, &phy->pgcr[1]); - if (freq == 1333) { - writel(0x0a806844, &phy->ptr[0]); - writel(0x208e0124, &phy->ptr[1]); - } else { - writel(0x0c807d04, &phy->ptr[0]); - writel(0x2710015E, &phy->ptr[1]); + switch (freq) { + case 1333: + freq_e = DRAM_FREQ_1333M; + break; + case 1600: + freq_e = DRAM_FREQ_1600M; + break; + default: + printf("unsupported DRAM frequency %d MHz\n", freq); + return -EINVAL; } + + writel(0x0300c473, &phy->pgcr[1]); + writel(ddrphy_ptr0[freq_e], &phy->ptr[0]); + writel(ddrphy_ptr1[freq_e], &phy->ptr[1]); writel(0x00083DEF, &phy->ptr[2]); - if (freq == 1333) { - writel(0x0f051616, &phy->ptr[3]); - writel(0x06ae08d6, &phy->ptr[4]); - } else { - writel(0x12061A80, &phy->ptr[3]); - writel(0x08027100, &phy->ptr[4]); - } + writel(ddrphy_ptr3[freq_e], &phy->ptr[3]); + writel(ddrphy_ptr4[freq_e], &phy->ptr[4]); writel(0xF004001A, &phy->dsgcr); /* change the value of the on-die pull-up/pull-down registors */ @@ -38,30 +59,13 @@ int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) writel(tmp, &phy->dxccr); writel(0x0000040B, &phy->dcr); - if (freq == 1333) { - writel(0x85589955, &phy->dtpr[0]); - if (size == 1) - writel(0x1a8253c0, &phy->dtpr[1]); - else - writel(0x1a8363c0, &phy->dtpr[1]); - writel(0x5002c200, &phy->dtpr[2]); - writel(0x00000b51, &phy->mr0); - } else { - writel(0x999cbb66, &phy->dtpr[0]); - if (size == 1) - writel(0x1a82dbc0, &phy->dtpr[1]); - else - writel(0x1a878400, &phy->dtpr[1]); - writel(0xa00214f8, &phy->dtpr[2]); - writel(0x00000d71, &phy->mr0); - } + writel(ddrphy_dtpr0[freq_e], &phy->dtpr[0]); + writel(ddrphy_dtpr1[freq_e], &phy->dtpr[1]); + writel(ddrphy_dtpr2[freq_e], &phy->dtpr[2]); + writel(ddrphy_mr0[freq_e], &phy->mr0); writel(0x00000006, &phy->mr1); - if (freq == 1333) - writel(0x00000290, &phy->mr2); - else - writel(0x00000298, &phy->mr2); - - writel(0x00000800, &phy->mr3); + writel(ddrphy_mr2[freq_e], &phy->mr2); + writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3); while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) ; diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c deleted file mode 100644 index 9fb34f79a7..0000000000 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/types.h> -#include <linux/io.h> - -#include "ddrphy-regs.h" - -int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) -{ - u32 tmp; - - writel(0x0300c473, &phy->pgcr[1]); - if (freq == 1333) { - writel(0x0a806844, &phy->ptr[0]); - writel(0x208e0124, &phy->ptr[1]); - } else { - writel(0x0c807d04, &phy->ptr[0]); - writel(0x2710015E, &phy->ptr[1]); - } - writel(0x00083DEF, &phy->ptr[2]); - if (freq == 1333) { - writel(0x0f051616, &phy->ptr[3]); - writel(0x06ae08d6, &phy->ptr[4]); - } else { - writel(0x12061A80, &phy->ptr[3]); - writel(0x08027100, &phy->ptr[4]); - } - writel(0xF004001A, &phy->dsgcr); - - /* change the value of the on-die pull-up/pull-down registors */ - tmp = readl(&phy->dxccr); - tmp &= ~0x0ee0; - tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; - writel(tmp, &phy->dxccr); - - writel(0x0000040B, &phy->dcr); - if (freq == 1333) { - writel(0x85589955, &phy->dtpr[0]); - writel(0x1a8363c0, &phy->dtpr[1]); - writel(0x5002c200, &phy->dtpr[2]); - writel(0x00000b51, &phy->mr0); - } else { - writel(0x999cbb66, &phy->dtpr[0]); - writel(0x1a878400, &phy->dtpr[1]); - writel(0xa00214f8, &phy->dtpr[2]); - writel(0x00000d71, &phy->mr0); - } - writel(0x00000006, &phy->mr1); - if (freq == 1333) - writel(0x00000290, &phy->mr2); - else - writel(0x00000298, &phy->mr2); - - writel(0x00000000, &phy->mr3); - - while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) - ; - - writel(0x0300C473, &phy->pgcr[1]); - writel(0x0000005D, &phy->zq[0].cr[1]); - - return 0; -} diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c deleted file mode 100644 index 651069073c..0000000000 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <linux/types.h> -#include <linux/io.h> - -#include "ddrphy-regs.h" - -int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) -{ - u32 tmp; - - writel(0x0300c473, &phy->pgcr[1]); - if (freq == 1333) { - writel(0x0a806844, &phy->ptr[0]); - writel(0x208e0124, &phy->ptr[1]); - } else { - writel(0x0c807d04, &phy->ptr[0]); - writel(0x2710015E, &phy->ptr[1]); - } - writel(0x00083DEF, &phy->ptr[2]); - if (freq == 1333) { - writel(0x0f051616, &phy->ptr[3]); - writel(0x06ae08d6, &phy->ptr[4]); - } else { - writel(0x12061A80, &phy->ptr[3]); - writel(0x08027100, &phy->ptr[4]); - } - writel(0xF004001A, &phy->dsgcr); - - /* change the value of the on-die pull-up/pull-down registors */ - tmp = readl(&phy->dxccr); - tmp &= ~0x0ee0; - tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; - writel(tmp, &phy->dxccr); - - writel(0x0000040B, &phy->dcr); - if (freq == 1333) { - writel(0x85589955, &phy->dtpr[0]); - if (size == 1) - writel(0x1a8363c0, &phy->dtpr[1]); - else - writel(0x1a8363c0, &phy->dtpr[1]); - writel(0x5002c200, &phy->dtpr[2]); - writel(0x00000b51, &phy->mr0); - } else { - writel(0x999cbb66, &phy->dtpr[0]); - if (size == 1) - writel(0x1a878400, &phy->dtpr[1]); - else - writel(0x1a878400, &phy->dtpr[1]); - writel(0xa00214f8, &phy->dtpr[2]); - writel(0x00000d71, &phy->mr0); - } - writel(0x00000006, &phy->mr1); - if (freq == 1333) - writel(0x00000290, &phy->mr2); - else - writel(0x00000298, &phy->mr2); - -#ifdef CONFIG_DDR_STANDARD - writel(0x00000000, &phy->mr3); -#else - writel(0x00000800, &phy->mr3); -#endif - - while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) - ; - - writel(0x0300C473, &phy->pgcr[1]); - writel(0x0000005D, &phy->zq[0].cr[1]); - - return 0; -} diff --git a/arch/arm/mach-uniphier/dram/ddrphy-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-regs.h index 03aedc2e63..87f6d0d3a2 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/dram/ddrphy-regs.h @@ -11,6 +11,7 @@ #include <linux/bitops.h> #include <linux/compiler.h> +#include <linux/types.h> #ifndef __ASSEMBLY__ @@ -169,9 +170,7 @@ struct ddrphy { #define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy)) #ifndef __ASSEMBLY__ -int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); -int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); -int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); +int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus); void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank); int ddrphy_training(struct ddrphy __iomem *phy); #endif diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index ffd7aa97b2..72447cc776 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c @@ -8,11 +8,40 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> +#include <asm/processor.h> #include "../init.h" #include "ddrphy-regs.h" #include "umc-regs.h" +#define DRAM_CH_NR 2 + +enum dram_freq { + DRAM_FREQ_1333M, + DRAM_FREQ_1600M, + DRAM_FREQ_NR, +}; + +enum dram_size { + DRAM_SZ_128M, + DRAM_SZ_256M, + DRAM_SZ_NR, +}; + +static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x36bb0f17}; +static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6aa24}; +static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = { + {0x00240512, 0x00350512}, + {0x002b0617, 0x003f0617}, +}; +static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008}; +static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ae}; + +static int umc_get_rank(int ch) +{ + return ch; /* ch0: rank0, ch1: rank1 for this SoC */ +} + static void umc_start_ssif(void __iomem *ssif_base) { writel(0x00000000, ssif_base + 0x0000b004); @@ -47,130 +76,116 @@ static void umc_start_ssif(void __iomem *ssif_base) writel(0x00000001, ssif_base + UMC_DMDRST); } -static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq) +static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base, + int freq, unsigned long size, bool ddr3plus) { - if (freq == 1333) { - writel(0x45990b11, dramcont + UMC_CMDCTLA); - writel(0x16958924, dramcont + UMC_CMDCTLB); - writel(0x5101046A, dramcont + UMC_INITCTLA); - - if (size == 1) - writel(0x27028B0A, dramcont + UMC_INITCTLB); - else if (size == 2) - writel(0x38028B0A, dramcont + UMC_INITCTLB); - - writel(0x000FF0FF, dramcont + UMC_INITCTLC); - writel(0x00000b51, dramcont + UMC_DRMMR0); - } else if (freq == 1600) { - writel(0x36BB0F17, dramcont + UMC_CMDCTLA); - writel(0x18C6AA24, dramcont + UMC_CMDCTLB); - writel(0x5101387F, dramcont + UMC_INITCTLA); - - if (size == 1) - writel(0x2F030D3F, dramcont + UMC_INITCTLB); - else if (size == 2) - writel(0x43030D3F, dramcont + UMC_INITCTLB); - - writel(0x00FF00FF, dramcont + UMC_INITCTLC); - writel(0x00000d71, dramcont + UMC_DRMMR0); - } - - writel(0x00000006, dramcont + UMC_DRMMR1); - - if (freq == 1333) - writel(0x00000290, dramcont + UMC_DRMMR2); - else if (freq == 1600) - writel(0x00000298, dramcont + UMC_DRMMR2); - - writel(0x00000800, dramcont + UMC_DRMMR3); + enum dram_freq freq_e; + enum dram_size size_e; - if (freq == 1333) { - if (size == 1) - writel(0x00240512, dramcont + UMC_SPCCTLA); - else if (size == 2) - writel(0x00350512, dramcont + UMC_SPCCTLA); + if (!ddr3plus) { + pr_err("DDR3 standard is not supported\n"); + return -EINVAL; + } - writel(0x00ff0006, dramcont + UMC_SPCCTLB); - writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); - } else if (freq == 1600) { - if (size == 1) - writel(0x002B0617, dramcont + UMC_SPCCTLA); - else if (size == 2) - writel(0x003F0617, dramcont + UMC_SPCCTLA); + switch (freq) { + case 1333: + freq_e = DRAM_FREQ_1333M; + break; + case 1600: + freq_e = DRAM_FREQ_1600M; + break; + default: + pr_err("unsupported DRAM frequency %d MHz\n", freq); + return -EINVAL; + } - writel(0x00ff0008, dramcont + UMC_SPCCTLB); - writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); + switch (size) { + case 0: + return 0; + case SZ_128M: + size_e = DRAM_SZ_128M; + break; + case SZ_256M: + size_e = DRAM_SZ_256M; + break; + default: + pr_err("unsupported DRAM size 0x%08lx\n", size); + return -EINVAL; } - writel(0x04060806, dramcont + UMC_WDATACTL_D0); - writel(0x04a02000, dramcont + UMC_DATASET); + writel(umc_cmdctla_plus[freq_e], dc_base + UMC_CMDCTLA); + writel(umc_cmdctlb_plus[freq_e], dc_base + UMC_CMDCTLB); + writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA); + writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB); + writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0); + writel(0x04060806, dc_base + UMC_WDATACTL_D0); + writel(0x04a02000, dc_base + UMC_DATASET); writel(0x00000000, ca_base + 0x2300); - writel(0x00400020, dramcont + UMC_DCCGCTL); - writel(0x00000003, dramcont + 0x7000); - writel(0x0000000f, dramcont + 0x8000); - writel(0x000000c3, dramcont + 0x8004); - writel(0x00000071, dramcont + 0x8008); - writel(0x0000003b, dramcont + UMC_DICGCTLA); - writel(0x020a0808, dramcont + UMC_DICGCTLB); - writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x00400020, dc_base + UMC_DCCGCTL); + writel(0x00000003, dc_base + 0x7000); + writel(0x0000000f, dc_base + 0x8000); + writel(0x000000c3, dc_base + 0x8004); + writel(0x00000071, dc_base + 0x8008); + writel(0x0000003b, dc_base + UMC_DICGCTLA); + writel(0x020a0808, dc_base + UMC_DICGCTLB); + writel(0x00000004, dc_base + UMC_FLOWCTLG); writel(0x80000201, ca_base + 0xc20); - writel(0x0801e01e, dramcont + UMC_FLOWCTLA); - writel(0x00200000, dramcont + UMC_FLOWCTLB); - writel(0x00004444, dramcont + UMC_FLOWCTLC); - writel(0x200a0a00, dramcont + UMC_SPCSETB); - writel(0x00000000, dramcont + UMC_SPCSETD); - writel(0x00000520, dramcont + UMC_DFICUPDCTLA); + writel(0x0801e01e, dc_base + UMC_FLOWCTLA); + writel(0x00200000, dc_base + UMC_FLOWCTLB); + writel(0x00004444, dc_base + UMC_FLOWCTLC); + writel(0x200a0a00, dc_base + UMC_SPCSETB); + writel(0x00000000, dc_base + UMC_SPCSETD); + writel(0x00000520, dc_base + UMC_DFICUPDCTLA); + + return 0; } -static int umc_init_sub(int freq, int size_ch0, int size_ch1) +static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base, + int freq, unsigned long size, bool ddr3plus, int ch) { - void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; - void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); - void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); - void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); - void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); - void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); - void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); - - umc_dram_init_start(dramcont0); - umc_dram_init_start(dramcont1); - umc_dram_init_poll(dramcont0); - umc_dram_init_poll(dramcont1); - - writel(0x00000101, dramcont0 + UMC_DIOCTLA); - - ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0); + void __iomem *phy_base = dc_base + 0x00001000; + int ret; - ddrphy_prepare_training(phy0_0, 0); - ddrphy_training(phy0_0); + writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET); + while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST) + cpu_relax(); - writel(0x00000101, dramcont1 + UMC_DIOCTLA); + writel(0x00000101, dc_base + UMC_DIOCTLA); - ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1); + ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus); + if (ret) + return ret; - ddrphy_prepare_training(phy1_0, 1); - ddrphy_training(phy1_0); - - umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); - umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); - - umc_start_ssif(ssif_base); + ddrphy_prepare_training(phy_base, umc_get_rank(ch)); + ret = ddrphy_training(phy_base); + if (ret) + return ret; - return 0; + return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus); } int ph1_ld4_umc_init(const struct uniphier_board_data *bd) { - if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) && - (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) && - (bd->dram_freq == 1333 || bd->dram_freq == 1600) && - bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) { - return umc_init_sub(bd->dram_freq, - bd->dram_ch0_size / SZ_128M, - bd->dram_ch1_size / SZ_128M); - } else { - pr_err("Unsupported DDR configuration\n"); - return -EINVAL; + void __iomem *umc_base = (void __iomem *)0x5b800000; + void __iomem *ca_base = umc_base + 0x00001000; + void __iomem *dc_base = umc_base + 0x00400000; + void __iomem *ssif_base = umc_base; + int ch, ret; + + for (ch = 0; ch < DRAM_CH_NR; ch++) { + ret = umc_ch_init(dc_base, ca_base, bd->dram_freq, + bd->dram_ch[ch].size, + bd->dram_ddr3plus, ch); + if (ret) { + pr_err("failed to initialize UMC ch%d\n", ch); + return ret; + } + + ca_base += 0x00001000; + dc_base += 0x00200000; } + + umc_start_ssif(ssif_base); + + return 0; } diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 261f7cfce7..23fb7b9f53 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -8,11 +8,14 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> +#include <asm/processor.h> #include "../init.h" #include "ddrphy-regs.h" #include "umc-regs.h" +#define DRAM_CH_NR 2 + enum dram_size { DRAM_SZ_128M, DRAM_SZ_256M, @@ -20,14 +23,13 @@ enum dram_size { DRAM_SZ_NR, }; -static u32 umc_initctlb[DRAM_SZ_NR] = {0x43030d3f, 0x43030d3f, 0x7b030d3f}; static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617}; static void umc_start_ssif(void __iomem *ssif_base) { - writel(0x00000001, ssif_base + 0x0000b004); + writel(0x00000000, ssif_base + 0x0000b004); writel(0xffffffff, ssif_base + 0x0000c004); - writel(0x07ffffff, ssif_base + 0x0000c008); + writel(0x000fffcf, ssif_base + 0x0000c008); writel(0x00000001, ssif_base + 0x0000b000); writel(0x00000001, ssif_base + 0x0000c000); @@ -66,121 +68,117 @@ static void umc_start_ssif(void __iomem *ssif_base) writel(0x00000001, ssif_base + UMC_DMDRST); } -static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int width) +static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base, + int freq, unsigned long size, bool ddr3plus) { - enum dram_size dram_size; + enum dram_size size_e; + + if (freq != 1600) { + pr_err("Unsupported DDR frequency %d MHz\n", freq); + return -EINVAL; + } + + if (ddr3plus) { + pr_err("DDR3+ is not supported\n"); + return -EINVAL; + } - switch (size / (width / 16)) { + switch (size) { case SZ_128M: - dram_size = DRAM_SZ_128M; + size_e = DRAM_SZ_128M; break; case SZ_256M: - dram_size = DRAM_SZ_256M; + size_e = DRAM_SZ_256M; break; case SZ_512M: - dram_size = DRAM_SZ_512M; + size_e = DRAM_SZ_512M; break; default: - printf("unsupported DRAM size\n"); + pr_err("unsupported DRAM size 0x%08lx (per 16bit)\n", size); return -EINVAL; } - writel(0x66bb0f17, dramcont + UMC_CMDCTLA); - writel(0x18c6aa44, dramcont + UMC_CMDCTLB); - writel(0x5101387f, dramcont + UMC_INITCTLA); - writel(umc_initctlb[dram_size], dramcont + UMC_INITCTLB); - writel(0x00ff00ff, dramcont + UMC_INITCTLC); - writel(0x00000d71, dramcont + UMC_DRMMR0); - writel(0x00000006, dramcont + UMC_DRMMR1); - writel(0x00000298, dramcont + UMC_DRMMR2); - writel(0x00000000, dramcont + UMC_DRMMR3); - writel(umc_spcctla[dram_size], dramcont + UMC_SPCCTLA); - writel(0x00ff0008, dramcont + UMC_SPCCTLB); - writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); - writel(0x000c00ae, dramcont + UMC_RDATACTL_D1); - writel(0x04060802, dramcont + UMC_WDATACTL_D0); - writel(0x04060802, dramcont + UMC_WDATACTL_D1); - writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x66bb0f17, dc_base + UMC_CMDCTLA); + writel(0x18c6aa44, dc_base + UMC_CMDCTLB); + writel(umc_spcctla[size_e], dc_base + UMC_SPCCTLA); + writel(0x00ff0008, dc_base + UMC_SPCCTLB); + writel(0x000c00ae, dc_base + UMC_RDATACTL_D0); + writel(0x000c00ae, dc_base + UMC_RDATACTL_D1); + writel(0x04060802, dc_base + UMC_WDATACTL_D0); + writel(0x04060802, dc_base + UMC_WDATACTL_D1); + writel(0x04a02000, dc_base + UMC_DATASET); writel(0x00000000, ca_base + 0x2300); - writel(0x00400020, dramcont + UMC_DCCGCTL); - writel(0x0000000f, dramcont + 0x7000); - writel(0x0000000f, dramcont + 0x8000); - writel(0x000000c3, dramcont + 0x8004); - writel(0x00000071, dramcont + 0x8008); - writel(0x00000004, dramcont + UMC_FLOWCTLG); - writel(0x00000000, dramcont + 0x0060); + writel(0x00400020, dc_base + UMC_DCCGCTL); + writel(0x0000000f, dc_base + 0x7000); + writel(0x0000000f, dc_base + 0x8000); + writel(0x000000c3, dc_base + 0x8004); + writel(0x00000071, dc_base + 0x8008); + writel(0x00000004, dc_base + UMC_FLOWCTLG); + writel(0x00000000, dc_base + 0x0060); writel(0x80000201, ca_base + 0xc20); - writel(0x0801e01e, dramcont + UMC_FLOWCTLA); - writel(0x00200000, dramcont + UMC_FLOWCTLB); - writel(0x00004444, dramcont + UMC_FLOWCTLC); - writel(0x200a0a00, dramcont + UMC_SPCSETB); - writel(0x00010000, dramcont + UMC_SPCSETD); - writel(0x80000020, dramcont + UMC_DFICUPDCTLA); + writel(0x0801e01e, dc_base + UMC_FLOWCTLA); + writel(0x00200000, dc_base + UMC_FLOWCTLB); + writel(0x00004444, dc_base + UMC_FLOWCTLC); + writel(0x200a0a00, dc_base + UMC_SPCSETB); + writel(0x00010000, dc_base + UMC_SPCSETD); + writel(0x80000020, dc_base + UMC_DFICUPDCTLA); return 0; } -int ph1_pro4_umc_init(const struct uniphier_board_data *bd) +static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base, + int freq, unsigned long size, unsigned int width, + bool ddr3plus) { - void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; - void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); - void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); - void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); - void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); - void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); - void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1); - void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); - void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1); - int ret; - - if (bd->dram_freq != 1600) { - pr_err("Unsupported DDR configuration\n"); - return -EINVAL; - } - - umc_dram_init_start(dramcont0); - umc_dram_init_start(dramcont1); - umc_dram_init_poll(dramcont0); - umc_dram_init_poll(dramcont1); - - writel(0x00000101, dramcont0 + UMC_DIOCTLA); + void __iomem *phy_base = dc_base + 0x00001000; + int nr_phy = width / 16; + int phy, ret; - ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch0_size); + writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET); + while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST) + cpu_relax(); - ddrphy_prepare_training(phy0_0, 0); - ddrphy_training(phy0_0); + for (phy = 0; phy < nr_phy; phy++) { + writel(0x00000100 | ((1 << (phy + 1)) - 1), + dc_base + UMC_DIOCTLA); - writel(0x00000103, dramcont0 + UMC_DIOCTLA); + ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus); + if (ret) + return ret; - ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch0_size); + ddrphy_prepare_training(phy_base, phy); + ret = ddrphy_training(phy_base); + if (ret) + return ret; - ddrphy_prepare_training(phy0_1, 1); - ddrphy_training(phy0_1); - - writel(0x00000101, dramcont1 + UMC_DIOCTLA); - - ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch1_size); - - ddrphy_prepare_training(phy1_0, 0); - ddrphy_training(phy1_0); - - writel(0x00000103, dramcont1 + UMC_DIOCTLA); - - ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch1_size); - - ddrphy_prepare_training(phy1_1, 1); - ddrphy_training(phy1_1); + phy_base += 0x00001000; + } - ret = umc_dramcont_init(dramcont0, ca_base0, bd->dram_ch0_size, - bd->dram_ch0_width); - if (ret) - return ret; + return umc_dramcont_init(dc_base, ca_base, freq, size / (width / 16), + ddr3plus); +} - ret = umc_dramcont_init(dramcont1, ca_base1, bd->dram_ch1_size, - bd->dram_ch1_width); - if (ret) - return ret; +int ph1_pro4_umc_init(const struct uniphier_board_data *bd) +{ + void __iomem *umc_base = (void __iomem *)0x5b800000; + void __iomem *ca_base = umc_base + 0x00001000; + void __iomem *dc_base = umc_base + 0x00400000; + void __iomem *ssif_base = umc_base; + int ch, ret; + + for (ch = 0; ch < DRAM_CH_NR; ch++) { + ret = umc_ch_init(dc_base, ca_base, bd->dram_freq, + bd->dram_ch[ch].size, + bd->dram_ch[ch].width, + bd->dram_ddr3plus); + if (ret) { + pr_err("failed to initialize UMC ch%d\n", ch); + return ret; + } + + ca_base += 0x00001000; + dc_base += 0x00200000; + } umc_start_ssif(ssif_base); diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index 09f9ccfb43..6cacd25e7c 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -8,11 +8,43 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> +#include <asm/processor.h> #include "../init.h" #include "ddrphy-regs.h" #include "umc-regs.h" +#define DRAM_CH_NR 2 + +enum dram_freq { + DRAM_FREQ_1333M, + DRAM_FREQ_1600M, + DRAM_FREQ_NR, +}; + +enum dram_size { + DRAM_SZ_128M, + DRAM_SZ_256M, + DRAM_SZ_512M, + DRAM_SZ_NR, +}; + +static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x55990b11, 0x66bb0f17}; +static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x46bb0f17}; +static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x16958944, 0x18c6ab44}; +static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6ab24}; +static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = { + {0x00240512, 0x00350512, 0x00000000}, /* no data for 1333MHz,128MB */ + {0x002b0617, 0x003f0617, 0x00670617}, +}; +static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008}; +static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ac}; + +static int umc_get_rank(int ch) +{ + return ch; /* ch0: rank0, ch1: rank1 for this SoC */ +} + static void umc_start_ssif(void __iomem *ssif_base) { writel(0x00000000, ssif_base + 0x0000b004); @@ -47,110 +79,116 @@ static void umc_start_ssif(void __iomem *ssif_base) writel(0x00000001, ssif_base + UMC_DMDRST); } -static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq) +static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base, + int freq, unsigned long size, bool ddr3plus) { -#ifdef CONFIG_DDR_STANDARD - writel(0x55990b11, dramcont + UMC_CMDCTLA); - writel(0x16958944, dramcont + UMC_CMDCTLB); -#else - writel(0x45990b11, dramcont + UMC_CMDCTLA); - writel(0x16958924, dramcont + UMC_CMDCTLB); -#endif - - writel(0x5101046A, dramcont + UMC_INITCTLA); - - if (size == 1) - writel(0x27028B0A, dramcont + UMC_INITCTLB); - else if (size == 2) - writel(0x38028B0A, dramcont + UMC_INITCTLB); - - writel(0x00FF00FF, dramcont + UMC_INITCTLC); - writel(0x00000b51, dramcont + UMC_DRMMR0); - writel(0x00000006, dramcont + UMC_DRMMR1); - writel(0x00000290, dramcont + UMC_DRMMR2); - -#ifdef CONFIG_DDR_STANDARD - writel(0x00000000, dramcont + UMC_DRMMR3); -#else - writel(0x00000800, dramcont + UMC_DRMMR3); -#endif - - if (size == 1) - writel(0x00240512, dramcont + UMC_SPCCTLA); - else if (size == 2) - writel(0x00350512, dramcont + UMC_SPCCTLA); - - writel(0x00ff0006, dramcont + UMC_SPCCTLB); - writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); - writel(0x04060806, dramcont + UMC_WDATACTL_D0); - writel(0x04a02000, dramcont + UMC_DATASET); + enum dram_freq freq_e; + enum dram_size size_e; + + switch (freq) { + case 1333: + freq_e = DRAM_FREQ_1333M; + break; + case 1600: + freq_e = DRAM_FREQ_1600M; + break; + default: + pr_err("unsupported DRAM frequency %d MHz\n", freq); + return -EINVAL; + } + + switch (size) { + case 0: + return 0; + case SZ_128M: + size_e = DRAM_SZ_128M; + break; + case SZ_256M: + size_e = DRAM_SZ_256M; + break; + case SZ_512M: + size_e = DRAM_SZ_512M; + break; + default: + pr_err("unsupported DRAM size 0x%08lx\n", size); + return -EINVAL; + } + + writel((ddr3plus ? umc_cmdctla_plus : umc_cmdctla)[freq_e], + dc_base + UMC_CMDCTLA); + writel((ddr3plus ? umc_cmdctlb_plus : umc_cmdctlb)[freq_e], + dc_base + UMC_CMDCTLB); + writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA); + writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB); + writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0); + writel(0x04060806, dc_base + UMC_WDATACTL_D0); + writel(0x04a02000, dc_base + UMC_DATASET); writel(0x00000000, ca_base + 0x2300); - writel(0x00400020, dramcont + UMC_DCCGCTL); - writel(0x00000003, dramcont + 0x7000); - writel(0x0000004f, dramcont + 0x8000); - writel(0x000000c3, dramcont + 0x8004); - writel(0x00000077, dramcont + 0x8008); - writel(0x0000003b, dramcont + UMC_DICGCTLA); - writel(0x020a0808, dramcont + UMC_DICGCTLB); - writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x00400020, dc_base + UMC_DCCGCTL); + writel(0x00000003, dc_base + 0x7000); + writel(0x0000004f, dc_base + 0x8000); + writel(0x000000c3, dc_base + 0x8004); + writel(0x00000077, dc_base + 0x8008); + writel(0x0000003b, dc_base + UMC_DICGCTLA); + writel(0x020a0808, dc_base + UMC_DICGCTLB); + writel(0x00000004, dc_base + UMC_FLOWCTLG); writel(0x80000201, ca_base + 0xc20); - writel(0x0801e01e, dramcont + UMC_FLOWCTLA); - writel(0x00200000, dramcont + UMC_FLOWCTLB); - writel(0x00004444, dramcont + UMC_FLOWCTLC); - writel(0x200a0a00, dramcont + UMC_SPCSETB); - writel(0x00000000, dramcont + UMC_SPCSETD); - writel(0x00000520, dramcont + UMC_DFICUPDCTLA); + writel(0x0801e01e, dc_base + UMC_FLOWCTLA); + writel(0x00200000, dc_base + UMC_FLOWCTLB); + writel(0x00004444, dc_base + UMC_FLOWCTLC); + writel(0x200a0a00, dc_base + UMC_SPCSETB); + writel(0x00000000, dc_base + UMC_SPCSETD); + writel(0x00000520, dc_base + UMC_DFICUPDCTLA); + + return 0; } -static int umc_init_sub(int freq, int size_ch0, int size_ch1) +static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base, + int freq, unsigned long size, bool ddr3plus, int ch) { - void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; - void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); - void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); - void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); - void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); - void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); - void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); - - umc_dram_init_start(dramcont0); - umc_dram_init_start(dramcont1); - umc_dram_init_poll(dramcont0); - umc_dram_init_poll(dramcont1); + void __iomem *phy_base = dc_base + 0x00001000; + int ret; - writel(0x00000101, dramcont0 + UMC_DIOCTLA); + writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET); + while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST) + cpu_relax(); - ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0); + writel(0x00000101, dc_base + UMC_DIOCTLA); - ddrphy_prepare_training(phy0_0, 0); - ddrphy_training(phy0_0); + ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus); + if (ret) + return ret; - writel(0x00000101, dramcont1 + UMC_DIOCTLA); + ddrphy_prepare_training(phy_base, umc_get_rank(ch)); + ret = ddrphy_training(phy_base); + if (ret) + return ret; - ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1); - - ddrphy_prepare_training(phy1_0, 1); - ddrphy_training(phy1_0); - - umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); - umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); - - umc_start_ssif(ssif_base); - - return 0; + return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus); } int ph1_sld8_umc_init(const struct uniphier_board_data *bd) { - if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) && - (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) && - bd->dram_freq == 1333 && - bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) { - return umc_init_sub(bd->dram_freq, - bd->dram_ch0_size / SZ_128M, - bd->dram_ch1_size / SZ_128M); - } else { - pr_err("Unsupported DDR configuration\n"); - return -EINVAL; + void __iomem *umc_base = (void __iomem *)0x5b800000; + void __iomem *ca_base = umc_base + 0x00001000; + void __iomem *dc_base = umc_base + 0x00400000; + void __iomem *ssif_base = umc_base; + int ch, ret; + + for (ch = 0; ch < DRAM_CH_NR; ch++) { + ret = umc_ch_init(dc_base, ca_base, bd->dram_freq, + bd->dram_ch[ch].size, + bd->dram_ddr3plus, ch); + if (ret) { + pr_err("failed to initialize UMC ch%d\n", ch); + return ret; + } + + ca_base += 0x00001000; + dc_base += 0x00200000; } + + umc_start_ssif(ssif_base); + + return 0; } diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c index 6e7fa885c4..50c023825e 100644 --- a/arch/arm/mach-uniphier/dram/umc-proxstream2.c +++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c @@ -18,46 +18,45 @@ #include "ddrmphy-regs.h" #include "umc-regs.h" -#define CH_NR 3 +#define DRAM_CH_NR 3 enum dram_freq { - FREQ_1866M, - FREQ_2133M, - FREQ_NR, + DRAM_FREQ_1866M, + DRAM_FREQ_2133M, + DRAM_FREQ_NR, }; enum dram_size { - SIZE_0, - SIZE_512M, - SIZE_1G, - SIZE_NR, + DRAM_SZ_256M, + DRAM_SZ_512M, + DRAM_SZ_NR, }; -static u32 ddrphy_pgcr2[FREQ_NR] = {0x00FC7E5D, 0x00FC90AB}; -static u32 ddrphy_ptr0[FREQ_NR] = {0x0EA09205, 0x10C0A6C6}; -static u32 ddrphy_ptr1[FREQ_NR] = {0x0DAC041B, 0x0FA104B1}; -static u32 ddrphy_ptr3[FREQ_NR] = {0x15171e45, 0x18182357}; -static u32 ddrphy_ptr4[FREQ_NR] = {0x0e9ad8e9, 0x10b34157}; -static u32 ddrphy_dtpr0[FREQ_NR] = {0x35a00d88, 0x39e40e88}; -static u32 ddrphy_dtpr1[FREQ_NR] = {0x2288cc2c, 0x228a04d0}; -static u32 ddrphy_dtpr2[FREQ_NR] = {0x50005e00, 0x50006a00}; -static u32 ddrphy_dtpr3[FREQ_NR] = {0x0010cb49, 0x0010ec89}; -static u32 ddrphy_mr0[FREQ_NR] = {0x00000115, 0x00000125}; -static u32 ddrphy_mr2[FREQ_NR] = {0x000002a0, 0x000002a8}; +static u32 ddrphy_pgcr2[DRAM_FREQ_NR] = {0x00FC7E5D, 0x00FC90AB}; +static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0EA09205, 0x10C0A6C6}; +static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x0DAC041B, 0x0FA104B1}; +static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x15171e45, 0x18182357}; +static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x0e9ad8e9, 0x10b34157}; +static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x35a00d88, 0x39e40e88}; +static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x2288cc2c, 0x228a04d0}; +static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x50005e00, 0x50006a00}; +static u32 ddrphy_dtpr3[DRAM_FREQ_NR] = {0x0010cb49, 0x0010ec89}; +static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000115, 0x00000125}; +static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x000002a0, 0x000002a8}; /* dependent on package and board design */ -static u32 ddrphy_acbdlr0[CH_NR] = {0x0000000c, 0x0000000c, 0x00000009}; +static u32 ddrphy_acbdlr0[DRAM_CH_NR] = {0x0000000c, 0x0000000c, 0x00000009}; -static u32 umc_cmdctla[FREQ_NR] = {0x66DD131D, 0x77EE1722}; +static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x66DD131D, 0x77EE1722}; /* * The ch2 is a different generation UMC core. * The register spec is different, unfortunately. */ -static u32 umc_cmdctlb_ch01[FREQ_NR] = {0x13E87C44, 0x18F88C44}; -static u32 umc_cmdctlb_ch2[FREQ_NR] = {0x19E8DC44, 0x1EF8EC44}; -static u32 umc_spcctla[FREQ_NR][SIZE_NR] = { - {0x00000000, 0x004A071D, 0x0078071D}, - {0x00000000, 0x0055081E, 0x0089081E}, +static u32 umc_cmdctlb_ch01[DRAM_FREQ_NR] = {0x13E87C44, 0x18F88C44}; +static u32 umc_cmdctlb_ch2[DRAM_FREQ_NR] = {0x19E8DC44, 0x1EF8EC44}; +static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = { + {0x004A071D, 0x0078071D}, + {0x0055081E, 0x0089081E}, }; static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B}; @@ -344,7 +343,7 @@ static int __ddrphy_training(void __iomem *phy_base, do { if (--timeout < 0) { - printf("%s: error: timeout during DDR training\n", + pr_err("%s: error: timeout during DDR training\n", __func__); return -ETIMEDOUT; } @@ -354,7 +353,7 @@ static int __ddrphy_training(void __iomem *phy_base, for (s = seq; s->description; s++) { if (pgsr0 & s->err_flag) { - printf("%s: error: %s failed\n", __func__, + pr_err("%s: error: %s failed\n", __func__, s->description); return -EIO; } @@ -405,12 +404,12 @@ static int ddrphy_training(void __iomem *phy_base) } /* UMC */ -static void umc_set_system_latency(void __iomem *umc_dc_base, int phy_latency) +static void umc_set_system_latency(void __iomem *dc_base, int phy_latency) { u32 val; int latency; - val = readl(umc_dc_base + UMC_RDATACTL_D0); + val = readl(dc_base + UMC_RDATACTL_D0); latency = (val & UMC_RDATACTL_RADLTY_MASK) >> UMC_RDATACTL_RADLTY_SHIFT; latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >> UMC_RDATACTL_RAD2LTY_SHIFT; @@ -428,18 +427,18 @@ static void umc_set_system_latency(void __iomem *umc_dc_base, int phy_latency) val |= latency << UMC_RDATACTL_RADLTY_SHIFT; } - writel(val, umc_dc_base + UMC_RDATACTL_D0); - writel(val, umc_dc_base + UMC_RDATACTL_D1); + writel(val, dc_base + UMC_RDATACTL_D0); + writel(val, dc_base + UMC_RDATACTL_D1); - readl(umc_dc_base + UMC_RDATACTL_D1); /* relax */ + readl(dc_base + UMC_RDATACTL_D1); /* relax */ } /* enable/disable auto refresh */ -void umc_refresh_ctrl(void __iomem *umc_dc_base, int enable) +void umc_refresh_ctrl(void __iomem *dc_base, int enable) { u32 tmp; - tmp = readl(umc_dc_base + UMC_SPCSETB); + tmp = readl(dc_base + UMC_SPCSETB); tmp &= ~UMC_SPCSETB_AREFMD_MASK; if (enable) @@ -447,7 +446,7 @@ void umc_refresh_ctrl(void __iomem *umc_dc_base, int enable) else tmp |= UMC_SPCSETB_AREFMD_REG; - writel(tmp, umc_dc_base + UMC_SPCSETB); + writel(tmp, dc_base + UMC_SPCSETB); udelay(1); } @@ -459,20 +458,35 @@ static void umc_ud_init(void __iomem *umc_base, int ch) writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0); } -static void umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq, - enum dram_size size, int ch, int width) +static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, + unsigned long size, int width, int ch) { + enum dram_size size_e; int latency; u32 val; - writel(umc_cmdctla[freq], umc_dc_base + UMC_CMDCTLA); + switch (size) { + case 0: + return 0; + case SZ_256M: + size_e = DRAM_SZ_256M; + break; + case SZ_512M: + size_e = DRAM_SZ_512M; + break; + default: + pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n", + size, ch); + return -EINVAL; + } + + writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA); writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq], - umc_dc_base + UMC_CMDCTLB); + dc_base + UMC_CMDCTLB); - writel(umc_spcctla[freq][size / (width / 16)], - umc_dc_base + UMC_SPCCTLA); - writel(umc_spcctlb[freq], umc_dc_base + UMC_SPCCTLB); + writel(umc_spcctla[freq][size_e], dc_base + UMC_SPCCTLA); + writel(umc_spcctlb[freq], dc_base + UMC_SPCCTLB); val = 0x000e000e; latency = 12; @@ -487,54 +501,56 @@ static void umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq, val |= latency << UMC_RDATACTL_RADLTY_SHIFT; } - writel(val, umc_dc_base + UMC_RDATACTL_D0); + writel(val, dc_base + UMC_RDATACTL_D0); if (width >= 32) - writel(val, umc_dc_base + UMC_RDATACTL_D1); + writel(val, dc_base + UMC_RDATACTL_D1); - writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D0); + writel(0x04060A02, dc_base + UMC_WDATACTL_D0); if (width >= 32) - writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D1); - writel(0x04000000, umc_dc_base + UMC_DATASET); - writel(0x00400020, umc_dc_base + UMC_DCCGCTL); - writel(0x00000084, umc_dc_base + UMC_FLOWCTLG); - writel(0x00000000, umc_dc_base + UMC_ACSSETA); + writel(0x04060A02, dc_base + UMC_WDATACTL_D1); + writel(0x04000000, dc_base + UMC_DATASET); + writel(0x00400020, dc_base + UMC_DCCGCTL); + writel(0x00000084, dc_base + UMC_FLOWCTLG); + writel(0x00000000, dc_base + UMC_ACSSETA); writel(ch == 2 ? umc_flowctla_ch2[freq] : umc_flowctla_ch01[freq], - umc_dc_base + UMC_FLOWCTLA); + dc_base + UMC_FLOWCTLA); - writel(0x00004400, umc_dc_base + UMC_FLOWCTLC); - writel(0x200A0A00, umc_dc_base + UMC_SPCSETB); - writel(0x00000520, umc_dc_base + UMC_DFICUPDCTLA); - writel(0x0000000D, umc_dc_base + UMC_RESPCTL); + writel(0x00004400, dc_base + UMC_FLOWCTLC); + writel(0x200A0A00, dc_base + UMC_SPCSETB); + writel(0x00000520, dc_base + UMC_DFICUPDCTLA); + writel(0x0000000D, dc_base + UMC_RESPCTL); if (ch != 2) { - writel(0x00202000, umc_dc_base + UMC_FLOWCTLB); - writel(0xFDBFFFFF, umc_dc_base + UMC_FLOWCTLOB0); - writel(0xFFFFFFFF, umc_dc_base + UMC_FLOWCTLOB1); - writel(0x00080700, umc_dc_base + UMC_BSICMAPSET); + writel(0x00202000, dc_base + UMC_FLOWCTLB); + writel(0xFDBFFFFF, dc_base + UMC_FLOWCTLOB0); + writel(0xFFFFFFFF, dc_base + UMC_FLOWCTLOB1); + writel(0x00080700, dc_base + UMC_BSICMAPSET); } else { - writel(0x00200000, umc_dc_base + UMC_FLOWCTLB); - writel(0x00000000, umc_dc_base + UMC_BSICMAPSET); + writel(0x00200000, dc_base + UMC_FLOWCTLB); + writel(0x00000000, dc_base + UMC_BSICMAPSET); } - writel(0x00000000, umc_dc_base + UMC_ERRMASKA); - writel(0x00000000, umc_dc_base + UMC_ERRMASKB); + writel(0x00000000, dc_base + UMC_ERRMASKA); + writel(0x00000000, dc_base + UMC_ERRMASKB); + + return 0; } -static int umc_init(void __iomem *umc_base, enum dram_freq freq, int ch, - enum dram_size size, int width) +static int umc_ch_init(void __iomem *umc_ch_base, enum dram_freq freq, + unsigned long size, unsigned int width, int ch) { - void __iomem *umc_dc_base = umc_base + 0x00011000; - void __iomem *phy_base = umc_base + 0x00030000; + void __iomem *dc_base = umc_ch_base + 0x00011000; + void __iomem *phy_base = umc_ch_base + 0x00030000; int ret; - writel(0x00000002, umc_dc_base + UMC_INITSET); - while (readl(umc_dc_base + UMC_INITSTAT) & BIT(2)) + writel(0x00000002, dc_base + UMC_INITSET); + while (readl(dc_base + UMC_INITSTAT) & BIT(2)) cpu_relax(); /* deassert PHY reset signals */ writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST, - umc_dc_base + UMC_DIOCTLA); + dc_base + UMC_DIOCTLA); ddrphy_init(phy_base, freq, width, ch); @@ -546,28 +562,28 @@ static int umc_init(void __iomem *umc_base, enum dram_freq freq, int ch, if (ret) return ret; - umc_dc_init(umc_dc_base, freq, size, ch, width); + ret = umc_dc_init(dc_base, freq, size, width, ch); + if (ret) + return ret; - umc_ud_init(umc_base, ch); + umc_ud_init(umc_ch_base, ch); - if (size) { - ret = ddrphy_training(phy_base); - if (ret) - return ret; - } + ret = ddrphy_training(phy_base); + if (ret) + return ret; udelay(1); /* match the system latency between UMC and PHY */ - umc_set_system_latency(umc_dc_base, + umc_set_system_latency(dc_base, ddrphy_get_system_latency(phy_base, width)); udelay(1); /* stop auto refresh before clearing FIFO in PHY */ - umc_refresh_ctrl(umc_dc_base, 0); + umc_refresh_ctrl(dc_base, 0); ddrphy_fifo_reset(phy_base); - umc_refresh_ctrl(umc_dc_base, 1); + umc_refresh_ctrl(dc_base, 1); udelay(10); @@ -585,43 +601,34 @@ static void um_init(void __iomem *um_base) int proxstream2_umc_init(const struct uniphier_board_data *bd) { void __iomem *um_base = (void __iomem *)0x5b600000; - void __iomem *umc_ch0_base = (void __iomem *)0x5b800000; - void __iomem *umc_ch1_base = (void __iomem *)0x5ba00000; - void __iomem *umc_ch2_base = (void __iomem *)0x5bc00000; + void __iomem *umc_ch_base = (void __iomem *)0x5b800000; enum dram_freq freq; - int ret; + int ch, ret; switch (bd->dram_freq) { case 1866: - freq = FREQ_1866M; + freq = DRAM_FREQ_1866M; break; case 2133: - freq = FREQ_2133M; + freq = DRAM_FREQ_2133M; break; default: - printf("unsupported DRAM frequency %d MHz\n", bd->dram_freq); + pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq); return -EINVAL; } - ret = umc_init(umc_ch0_base, freq, 0, bd->dram_ch0_size / SZ_256M, - bd->dram_ch0_width); - if (ret) { - printf("failed to initialize UMC ch0\n"); - return ret; - } + for (ch = 0; ch < bd->dram_nr_ch; ch++) { + unsigned long size = bd->dram_ch[ch].size; + unsigned int width = bd->dram_ch[ch].width; - ret = umc_init(umc_ch1_base, freq, 1, bd->dram_ch1_size / SZ_256M, - bd->dram_ch1_width); - if (ret) { - printf("failed to initialize UMC ch1\n"); - return ret; - } + ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), + width, ch); + if (ret) { + pr_err("failed to initialize UMC ch%d\n", ch); + return ret; + } - ret = umc_init(umc_ch2_base, freq, 2, bd->dram_ch2_size / SZ_256M, - bd->dram_ch2_width); - if (ret) { - printf("failed to initialize UMC ch2\n"); - return ret; + umc_ch_base += 0x00200000; } um_init(um_base); diff --git a/arch/arm/mach-uniphier/dram/umc-regs.h b/arch/arm/mach-uniphier/dram/umc-regs.h index a6957a4a51..cc2dd27abf 100644 --- a/arch/arm/mach-uniphier/dram/umc-regs.h +++ b/arch/arm/mach-uniphier/dram/umc-regs.h @@ -9,10 +9,7 @@ #ifndef ARCH_UMC_REGS_H #define ARCH_UMC_REGS_H -#define UMC_BASE 0x5b800000 - -/* SSIF registers */ -#define UMC_SSIF_BASE UMC_BASE +#include <linux/bitops.h> #define UMC_CPURST 0x00000700 #define UMC_IDSRST 0x0000070C @@ -48,23 +45,14 @@ #define UMC_CLKEN_SSIF_RC 0x0000C080 #define UMC_CLKEN_SSIF_DST 0x0000C084 -/* CA registers */ -#define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch)) - -/* DRAM controller registers */ -#define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch)) - #define UMC_CMDCTLA 0x00000000 #define UMC_CMDCTLB 0x00000004 -#define UMC_INITCTLA 0x00000008 -#define UMC_INITCTLB 0x0000000C -#define UMC_INITCTLC 0x00000010 #define UMC_INITSET 0x00000014 +#define UMC_INITSET_INIT1EN BIT(1) /* init without power-on wait */ +#define UMC_INITSET_INIT0EN BIT(0) /* init with power-on wait */ #define UMC_INITSTAT 0x00000018 -#define UMC_DRMMR0 0x0000001C -#define UMC_DRMMR1 0x00000020 -#define UMC_DRMMR2 0x00000024 -#define UMC_DRMMR3 0x00000028 +#define UMC_INITSTAT_INIT1ST BIT(1) /* init without power-on wait */ +#define UMC_INITSTAT_INIT0ST BIT(0) /* init with power-on wait */ #define UMC_SPCCTLA 0x00000030 #define UMC_SPCCTLB 0x00000034 #define UMC_SPCSETA 0x00000038 @@ -116,30 +104,4 @@ #define UMC_BITPERPIXELMODE_D0 0x010 #define UMC_PAIR1DOFF_D0 0x054 -#ifndef __ASSEMBLY__ - -#include <linux/types.h> - -static inline void umc_polling(u32 address, u32 expval, u32 mask) -{ - u32 nmask = ~mask; - u32 data; - do { - data = readl(address) & nmask; - } while (data != expval); -} - -static inline void umc_dram_init_start(void __iomem *dramcont) -{ - writel(0x00000002, dramcont + UMC_INITSET); -} - -static inline void umc_dram_init_poll(void __iomem *dramcont) -{ - while ((readl(dramcont + UMC_INITSTAT) & 0x00000002)) - ; -} - -#endif - #endif diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 32cc448aeb..cffdfc9841 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -32,7 +32,7 @@ int dram_init(void) gd->ram_size = fdt32_to_cpu(*(val + 1)); - debug("DRAM size = %08lx\n", gd->ram_size); + debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size); return 0; } @@ -54,6 +54,7 @@ void dram_init_banksize(void) gd->bd->bi_dram[i].size = fdt32_to_cpu(*val++); debug("DRAM bank %d: start = %08lx, size = %08lx\n", - i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); + i, (unsigned long)gd->bd->bi_dram[i].start, + (unsigned long)gd->bd->bi_dram[i].size); } } diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index 0a47e70dcf..e969fd0c4e 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -7,17 +7,21 @@ #ifndef __MACH_INIT_H #define __MACH_INIT_H +#include <linux/types.h> + +#define UNIPHIER_MAX_NR_DRAM_CH 3 + +struct uniphier_dram_ch { + unsigned long base; + unsigned long size; + unsigned int width; +}; + struct uniphier_board_data { - unsigned long dram_ch0_base; - unsigned long dram_ch0_size; - unsigned long dram_ch0_width; - unsigned long dram_ch1_base; - unsigned long dram_ch1_size; - unsigned long dram_ch1_width; - unsigned long dram_ch2_base; - unsigned long dram_ch2_size; - unsigned long dram_ch2_width; - unsigned int dram_freq; + unsigned int dram_freq; + unsigned int dram_nr_ch; + bool dram_ddr3plus; + struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH]; }; const struct uniphier_board_data *uniphier_get_board_param(void); diff --git a/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c index 9718cc560f..6fdf910895 100644 --- a/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c +++ b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c @@ -21,14 +21,14 @@ int ph1_sld3_memconf_init(const struct uniphier_board_data *bd) tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK); - switch (bd->dram_ch2_width) { + switch (bd->dram_ch[2].width) { case 16: tmp |= SG_MEMCONF_CH2_NUM_1; - size_per_word = bd->dram_ch2_size; + size_per_word = bd->dram_ch[2].size; break; case 32: tmp |= SG_MEMCONF_CH2_NUM_2; - size_per_word = bd->dram_ch2_size >> 1; + size_per_word = bd->dram_ch[2].size >> 1; break; default: pr_err("error: unsupported DRAM Ch2 width\n"); diff --git a/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c b/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c index 9a91fb33ef..c47fe0ae53 100644 --- a/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c +++ b/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c @@ -21,14 +21,14 @@ int proxstream2_memconf_init(const struct uniphier_board_data *bd) tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK); - switch (bd->dram_ch2_width) { + switch (bd->dram_ch[2].width) { case 16: tmp |= SG_MEMCONF_CH2_NUM_1; - size_per_word = bd->dram_ch2_size; + size_per_word = bd->dram_ch[2].size; break; case 32: tmp |= SG_MEMCONF_CH2_NUM_2; - size_per_word = bd->dram_ch2_size >> 1; + size_per_word = bd->dram_ch[2].size >> 1; break; default: pr_err("error: unsupported DRAM Ch2 width\n"); diff --git a/arch/arm/mach-uniphier/memconf/memconf.c b/arch/arm/mach-uniphier/memconf/memconf.c index f2a0eaf3f5..3d4b50456b 100644 --- a/arch/arm/mach-uniphier/memconf/memconf.c +++ b/arch/arm/mach-uniphier/memconf/memconf.c @@ -21,14 +21,14 @@ int memconf_init(const struct uniphier_board_data *bd) tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK); - switch (bd->dram_ch0_width) { + switch (bd->dram_ch[0].width) { case 16: tmp |= SG_MEMCONF_CH0_NUM_1; - size_per_word = bd->dram_ch0_size; + size_per_word = bd->dram_ch[0].size; break; case 32: tmp |= SG_MEMCONF_CH0_NUM_2; - size_per_word = bd->dram_ch0_size >> 1; + size_per_word = bd->dram_ch[0].size >> 1; break; default: pr_err("error: unsupported DRAM Ch0 width\n"); @@ -59,14 +59,14 @@ int memconf_init(const struct uniphier_board_data *bd) tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK); - switch (bd->dram_ch1_width) { + switch (bd->dram_ch[1].width) { case 16: tmp |= SG_MEMCONF_CH1_NUM_1; - size_per_word = bd->dram_ch1_size; + size_per_word = bd->dram_ch[1].size; break; case 32: tmp |= SG_MEMCONF_CH1_NUM_2; - size_per_word = bd->dram_ch1_size >> 1; + size_per_word = bd->dram_ch[1].size >> 1; break; default: pr_err("error: unsupported DRAM Ch1 width\n"); @@ -94,7 +94,7 @@ int memconf_init(const struct uniphier_board_data *bd) return -EINVAL; } - if (bd->dram_ch0_base + bd->dram_ch0_size < bd->dram_ch1_base) + if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base) tmp |= SG_MEMCONF_SPARSEMEM; else tmp &= ~SG_MEMCONF_SPARSEMEM; diff --git a/arch/arm/mach-uniphier/micro-support-card.c b/arch/arm/mach-uniphier/micro-support-card.c index f777ac1ffe..f7a37e3e4c 100644 --- a/arch/arm/mach-uniphier/micro-support-card.c +++ b/arch/arm/mach-uniphier/micro-support-card.c @@ -142,7 +142,8 @@ static void detect_num_flash_banks(void) memory_bank; debug("flash bank found: base = 0x%lx, size = 0x%lx\n", - memory_bank->base, memory_bank->size); + (unsigned long)memory_bank->base, + (unsigned long)memory_bank->size); cfi_flash_num_flash_banks++; } } diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index 678d437fc9..3a535c70b2 100644 --- a/arch/arm/mach-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h @@ -105,7 +105,7 @@ static inline void sg_set_pinsel(unsigned pin, unsigned muxval, unsigned mux_bits, unsigned reg_stride) { unsigned shift = pin * mux_bits % 32; - unsigned reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride; + unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride; u32 mask = (1U << mux_bits) - 1; u32 tmp; diff --git a/arch/arm/mach-uniphier/soc-info.h b/arch/arm/mach-uniphier/soc-info.h index 3cfd1e9d6e..606094c80f 100644 --- a/arch/arm/mach-uniphier/soc-info.h +++ b/arch/arm/mach-uniphier/soc-info.h @@ -15,8 +15,8 @@ enum uniphier_soc_id { SOC_UNIPHIER_PH1_PRO5, SOC_UNIPHIER_PROXSTREAM2, SOC_UNIPHIER_PH1_LD6B, - SOC_UNIPHIER_PH1_SLD11, - SOC_UNIPHIER_PH1_LD10, + SOC_UNIPHIER_PH1_LD11, + SOC_UNIPHIER_PH1_LD20, SOC_UNIPHIER_UNKNOWN, }; @@ -28,8 +28,8 @@ enum uniphier_soc_id { IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + \ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + \ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B) + \ - IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD11) + \ - IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD10) + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD11) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD20) #define UNIPHIER_MULTI_SOC ((UNIPHIER_NR_ENABLED_SOCS) > 1) @@ -59,11 +59,11 @@ static inline enum uniphier_soc_id uniphier_get_soc_type(void) #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) return SOC_UNIPHIER_PH1_LD6B; #endif -#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD11) - return SOC_UNIPHIER_PH1_SLD11; +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD11) + return SOC_UNIPHIER_PH1_LD11; #endif -#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD10) - return SOC_UNIPHIER_PH1_LD10; +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD20) + return SOC_UNIPHIER_PH1_LD20; #endif return SOC_UNIPHIER_UNKNOWN; diff --git a/arch/arm/mach-uniphier/soc_info.c b/arch/arm/mach-uniphier/soc_info.c index fd799ca39a..3cfc183723 100644 --- a/arch/arm/mach-uniphier/soc_info.c +++ b/arch/arm/mach-uniphier/soc_info.c @@ -52,14 +52,14 @@ enum uniphier_soc_id uniphier_get_soc_type(void) ret = SOC_UNIPHIER_PH1_LD6B; break; #endif -#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD11 +#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD11 case 0x31: - ret = SOC_UNIPHIER_PH1_SLD11; + ret = SOC_UNIPHIER_PH1_LD11; break; #endif -#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD10 +#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD20 case 0x32: - ret = SOC_UNIPHIER_PH1_LD10; + ret = SOC_UNIPHIER_PH1_LD20; break; #endif default: diff --git a/board/freescale/mx6qarm2/MAINTAINERS b/board/freescale/mx6qarm2/MAINTAINERS index 52cf7f935a..fdbc7fa725 100644 --- a/board/freescale/mx6qarm2/MAINTAINERS +++ b/board/freescale/mx6qarm2/MAINTAINERS @@ -1,6 +1,6 @@ MX6QARM2 BOARD -M: Jason Liu <r64343@freescale.com> -M: Ye Li <b37916@freescale.com> +M: Jason Liu <jason.hui.liu@nxp.com> +M: Ye Li <ye.li@nxp.com> S: Maintained F: board/freescale/mx6qarm2/ F: include/configs/mx6qarm2.h diff --git a/board/freescale/mx6qsabreauto/MAINTAINERS b/board/freescale/mx6qsabreauto/MAINTAINERS index 687f68c2f9..f148dace13 100644 --- a/board/freescale/mx6qsabreauto/MAINTAINERS +++ b/board/freescale/mx6qsabreauto/MAINTAINERS @@ -1,6 +1,6 @@ MX6QSABREAUTO BOARD M: Fabio Estevam <fabio.estevam@nxp.com> -M: Peng Fan <Peng.Fan@freescale.com> +M: Peng Fan <peng.fan@nxp.com> S: Maintained F: board/freescale/mx6qsabreauto/ F: include/configs/mx6qsabreauto.h diff --git a/board/freescale/mx6slevk/MAINTAINERS b/board/freescale/mx6slevk/MAINTAINERS index 2e25433828..be2f3d5b37 100644 --- a/board/freescale/mx6slevk/MAINTAINERS +++ b/board/freescale/mx6slevk/MAINTAINERS @@ -1,6 +1,6 @@ MX6SLEVK BOARD M: Fabio Estevam <fabio.estevam@nxp.com> -M: Peng Fan <Peng.Fan@freescale.com> +M: Peng Fan <peng.fan@nxp.com> S: Maintained F: board/freescale/mx6slevk/ F: include/configs/mx6slevk.h diff --git a/board/freescale/mx6ul_14x14_evk/MAINTAINERS b/board/freescale/mx6ul_14x14_evk/MAINTAINERS index d5f74b7ff4..7c7a196d22 100644 --- a/board/freescale/mx6ul_14x14_evk/MAINTAINERS +++ b/board/freescale/mx6ul_14x14_evk/MAINTAINERS @@ -1,5 +1,5 @@ MX6ULEVK BOARD -M: Peng Fan <Peng.Fan@freescale.com> +M: Peng Fan <peng.fan@nxp.com> S: Maintained F: board/freescale/mx6ul_14x14_evk/ F: include/configs/mx6ul_14x14_evk.h diff --git a/board/lge/sniper/sniper.c b/board/lge/sniper/sniper.c index d0e7d66b49..f093f97e2b 100644 --- a/board/lge/sniper/sniper.c +++ b/board/lge/sniper/sniper.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; const omap3_sysinfo sysinfo = { .mtype = DDR_STACKED, - .board_string = "Sniper", + .board_string = "sniper", .nand_string = "MMC" }; @@ -58,6 +58,11 @@ static struct musb_hdrc_platform_data musb_platform_data = { .board_data = &musb_board_data, }; +void set_muxconf_regs(void) +{ + MUX_SNIPER(); +} + #ifdef CONFIG_SPL_BUILD void get_board_mem_timings(struct board_sdrc_timings *timings) { @@ -69,12 +74,6 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) } #endif -u32 get_board_rev(void) -{ - /* Sold devices are expected to be at least revision F. */ - return 6; -} - int board_init(void) { /* GPMC init */ @@ -147,6 +146,12 @@ int misc_init_r(void) return 0; } +u32 get_board_rev(void) +{ + /* Sold devices are expected to be at least revision F. */ + return 6; +} + void get_board_serial(struct tag_serialnr *serialnr) { omap_die_id_get_board_serial(serialnr); @@ -162,11 +167,6 @@ int fb_set_reboot_flag(void) return omap_reboot_mode_store('b'); } -void set_muxconf_regs(void) -{ - MUX_SNIPER(); -} - #ifndef CONFIG_SPL_BUILD int board_mmc_init(bd_t *bis) { diff --git a/board/lge/sniper/sniper.h b/board/lge/sniper/sniper.h index 01ab3015d2..0f81c437ac 100644 --- a/board/lge/sniper/sniper.h +++ b/board/lge/sniper/sniper.h @@ -13,353 +13,353 @@ #define MUX_SNIPER() \ /* SDRC */ \ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */ \ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* sdrc_d0 */\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* sdrc_d1 */\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* sdrc_d2 */\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* sdrc_d3 */\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* sdrc_d4 */\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* sdrc_d5 */\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* sdrc_d6 */\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* sdrc_d7 */\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* sdrc_d8 */\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* sdrc_d9 */\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* sdrc_d10 */\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* sdrc_d11 */\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* sdrc_d12 */\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* sdrc_d13 */\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* sdrc_d14 */\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* sdrc_d15 */\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* sdrc_d16 */\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* sdrc_d17 */\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* sdrc_d18 */\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* sdrc_d19 */\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* sdrc_d20 */\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* sdrc_d21 */\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* sdrc_d22 */\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* sdrc_d23 */\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* sdrc_d24 */\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* sdrc_d25 */\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* sdrc_d26 */\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* sdrc_d27 */\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* sdrc_d28 */\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* sdrc_d29 */\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* sdrc_d30 */\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* sdrc_d31 */\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* sdrc_clk */\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* sdrc_dqs0 */\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* sdrc_dqs1 */\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* sdrc_dqs2 */\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* sdrc_dqs3 */ \ /* GPMC */ \ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M4)) /* GPIO_34: LCD_RESET_N */ \ - MUX_VAL(CP(GPMC_A2), (IEN | PTD | DIS | M4)) /* GPIO_35: TOUCH_INT_N */ \ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M4)) /* GPIO_36: VT_CAM_PWDN */ \ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M4)) /* GPIO_37: CAM_SUBPM_EN */\ - MUX_VAL(CP(GPMC_A5), (IEN | PTD | DIS | M4)) /* GPIO_38: MODEM_PWR_CHK */\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* GPIO_39: MODEM_WAKE */\ - MUX_VAL(CP(GPMC_A7), (IEN | PTD | DIS | M4)) /* GPIO_40: MUIC_INT_N */\ - MUX_VAL(CP(GPMC_A8), (IEN | PTD | DIS | M4)) /* GPIO_41: GYRO_INT_N */\ - MUX_VAL(CP(GPMC_A9), (IEN | PTD | EN | M4)) /* GPIO_42: MOTION_INT_N */\ - MUX_VAL(CP(GPMC_A10), (IEN | PTD | DIS | M4)) /* GPIO_43: BT_HOST_WAKEUP */\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */ \ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */ \ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */ \ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */ \ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */ \ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */ \ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */ \ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */ \ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */ \ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */ \ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */ \ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */ \ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */ \ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */ \ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */ \ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M4)) /* gpio_34 */ \ + MUX_VAL(CP(GPMC_A2), (IEN | PTD | DIS | M4)) /* gpio_35 */ \ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M4)) /* gpio_36 */ \ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M4)) /* gpio_37 */\ + MUX_VAL(CP(GPMC_A5), (IEN | PTD | DIS | M4)) /* gpio_38 */\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* gpio_39 */\ + MUX_VAL(CP(GPMC_A7), (IEN | PTD | DIS | M4)) /* gpio_40 */\ + MUX_VAL(CP(GPMC_A8), (IEN | PTD | DIS | M4)) /* gpio_41 */\ + MUX_VAL(CP(GPMC_A9), (IEN | PTD | EN | M4)) /* gpio_42 */\ + MUX_VAL(CP(GPMC_A10), (IEN | PTD | DIS | M4)) /* gpio_43 */\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* gpmc_d0 */ \ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* gpmc_d1 */ \ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* gpmc_d2 */ \ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* gpmc_d3 */ \ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* gpmc_d4 */ \ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* gpmc_d5 */ \ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* gpmc_d6 */ \ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* gpmc_d7 */ \ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* gpmc_d8 */ \ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* gpmc_d9 */ \ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* gpmc_d10 */ \ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* gpmc_d11 */ \ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* gpmc_d12 */ \ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* gpmc_d13 */ \ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* gpmc_d14 */ \ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTD | DIS | M7)) \ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTD | DIS | M4)) /* GPIO_52: BT_WAKE_UP */ \ - MUX_VAL(CP(GPMC_NCS2), (IEN | PTD | DIS | M4)) /* GPIO_53: LCD_TE */ \ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54: LCD_CS */ \ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTD | DIS | M4)) /* GPIO_55: BT_MAKER_ID */ \ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M3)) /* GPIO_56: VIBE_PWM */ \ - MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M4)) /* GPIO_57: VIBE_EN */ \ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTD | DIS | M4)) /* GPIO_58: COM_INT */ \ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M7)) /* SAFE_MODE */ \ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTD | DIS | M4)) /* gpio_52 */ \ + MUX_VAL(CP(GPMC_NCS2), (IEN | PTD | DIS | M4)) /* gpio_53 */ \ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* gpio_54 */ \ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTD | DIS | M4)) /* gpio_55 */ \ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M3)) /* gpio_56 */ \ + MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M4)) /* gpio_57 */ \ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTD | DIS | M4)) /* gpio_58 */ \ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M7)) /* safe_mode */ \ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M7)) \ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M7)) \ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M7)) \ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M4)) /* GPIO_60: PROXI_LDO_EN */ \ - MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)) /* GPIO_61: VT_RESET_N */ \ - MUX_VAL(CP(GPMC_NWP), (IDIS | PTD | DIS | M4)) /* GPIO_62: LCD_CP_EN */ \ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M4)) /* gpio_60 */ \ + MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)) /* gpio_61 */ \ + MUX_VAL(CP(GPMC_NWP), (IDIS | PTD | DIS | M4)) /* gpio_62 */ \ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTD | DIS | M4)) /* GPIO_63: ONENAND_INT */ \ - MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTD | DIS | M2)) /* GPIO_64: UART4_TX_IPC */ \ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | DIS | M2)) /* GPIO_65: UART4_RX_IPC */ \ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTD | DIS | M4)) /* gpio_63 */ \ + MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTD | DIS | M2)) /* gpio_64 */ \ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | DIS | M2)) /* gpio_65 */ \ /* DSS */ \ - MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M1)) /* DSI_DX0 */ \ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M1)) /* DSI_DY0 */ \ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M1)) /* DSI_DX1 */ \ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M1)) /* DSI_DY1 */ \ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M1)) /* DSI_DX2 */ \ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M1)) /* DSI_DY2 */ \ - MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA7), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA10), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA11), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA12), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA13), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA14), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA15), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M4)) /* GPIO_87: MIC_SEL */ \ - MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA20), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA21), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA22), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA23), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ + MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M1)) /* dsi_dx0 */ \ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M1)) /* dsi_dy0 */ \ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M1)) /* dsi_dx1 */ \ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M1)) /* dsi_dy1 */ \ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M1)) /* dsi_dx2 */ \ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M1)) /* dsi_dy2 */ \ + MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA7), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA10), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA11), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA12), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA13), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA14), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA15), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M4)) /* gpio_87 */ \ + MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA20), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA21), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA22), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA23), (IEN | PTD | EN | M7)) /* safe_mode */ \ /* CAM */ \ - MUX_VAL(CP(CAM_HS), (IEN | PTD | EN | M0)) /* CAM_HS */ \ - MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M0)) /* CAM_VS */ \ - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /* CAM_XCLKA */ \ - MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M0)) /* CAM_PCLK */ \ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /* GPIO_98: 5M_RESET_N */ \ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M2)) /* CSI2_DX2 */ \ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M2)) /* CSI2_DY2 */ \ - MUX_VAL(CP(CAM_D2), (IDIS | PTD | EN | M4)) /* GPIO_101: IFX_USB_VBUS_EN */ \ - MUX_VAL(CP(CAM_D3), (IDIS | PTD | DIS | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /* CAM_D4 */ \ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /* CAM_D5 */ \ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /* CAM_D6 */ \ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /* CAM_D7 */ \ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /* CAM_D8 */ \ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /* CAM_D9 */ \ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /* CAM_D10 */ \ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /* CAM_D11 */ \ - MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M0)) /* CAM_XCLKB */ \ - MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)) /* GPIO_167: 5M_CAM_VCN_EN */ \ - MUX_VAL(CP(CAM_STROBE), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ + MUX_VAL(CP(CAM_HS), (IEN | PTD | EN | M0)) /* cam_hs */ \ + MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M0)) /* cam_vs */ \ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /* cam_xclka */ \ + MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M0)) /* cam_pclk */ \ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /* gpio_98 */ \ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M2)) /* csi2_dx2 */ \ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M2)) /* csi2_dy2 */ \ + MUX_VAL(CP(CAM_D2), (IDIS | PTD | EN | M4)) /* gpio_101 */ \ + MUX_VAL(CP(CAM_D3), (IDIS | PTD | DIS | M7)) /* safe_mode */ \ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /* cam_d4 */ \ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /* cam_d5 */ \ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /* cam_d6 */ \ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /* cam_d7 */ \ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /* cam_d8 */ \ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /* cam_d9 */ \ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /* cam_d10 */ \ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /* cam_d11 */ \ + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M0)) /* cam_xclkb */ \ + MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)) /* gpio_167 */ \ + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | DIS | M7)) /* safe_mode */ \ /* CSI2 */ \ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /* CSI2_DX0 */ \ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /* CSI2_DY0 */ \ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /* CSI2_DX1 */ \ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /* CSI2_DY1 */ \ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /* csi2_dx0 */ \ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /* csi2_dy0 */ \ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /* csi2_dx1 */ \ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /* csi2_dy1 */ \ /* MCBSP2 */ \ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /* MCBSP2_FSX */ \ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /* MCBSP2_CLKX */ \ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /* MCBSP2_DR */ \ - MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /* MCBSP2_DX */ \ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /* mcbsp2_fsx */ \ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /* mcbsp2_clkx */ \ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /* mcbsp2_dr */ \ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /* mcbsp2_dx */ \ /* MMC1 */ \ - MUX_VAL(CP(MMC1_CLK), (IEN | PTD | DIS | M0)) /* MMC1_CLK */ \ - MUX_VAL(CP(MMC1_CMD), (IEN | PTD | DIS | M0)) /* MMC1_CMD */ \ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTD | DIS | M0)) /* MMC1_DAT0 */ \ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTD | DIS | M0)) /* MMC1_DAT1 */ \ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTD | DIS | M0)) /* MMC1_DAT2 */ \ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTD | DIS | M0)) /* MMC1_DAT3 */ \ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ + MUX_VAL(CP(MMC1_CLK), (IEN | PTD | DIS | M0)) /* mmc1_clk */ \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTD | DIS | M0)) /* mmc1_cmd */ \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTD | DIS | M0)) /* mmc1_dat0 */ \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTD | DIS | M0)) /* mmc1_dat1 */ \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTD | DIS | M0)) /* mmc1_dat2 */ \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTD | DIS | M0)) /* mmc1_dat3 */ \ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M7)) /* safe_mode */ \ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M7)) /* safe_mode */ \ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | DIS | M7)) /* safe_mode */ \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | DIS | M7)) /* safe_mode */ \ /* MMC2 */ \ - MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) /* MMC2_CLK */ \ - MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) /* MMC2_CMD */ \ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) /* MMC2_DAT0 */ \ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) /* MMC2_DAT1 */ \ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) /* MMC2_DAT2 */ \ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) /* MMC2_DAT3 */ \ - MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0)) /* MMC2_DAT4 */ \ - MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0)) /* MMC2_DAT5 */ \ - MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0)) /* MMC2_DAT6 */ \ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0)) /* MMC2_DAT7 */ \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) /* mmc2_clk */ \ + MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) /* mmc2_cmd */ \ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) /* mmc2_dat0 */ \ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) /* mmc2_dat1 */ \ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) /* mmc2_dat2 */ \ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) /* mmc2_dat3 */ \ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0)) /* mmc2_dat4 */ \ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0)) /* mmc2_dat5 */ \ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0)) /* mmc2_dat6 */ \ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0)) /* mmc2_dat7 */ \ /* MCBSP3 */ \ - MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /* MCBSP3_DX */ \ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /* MCBSP3_DR */ \ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /* MCBSP3_CLKX */ \ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /* MCBSP3_FSX */ \ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /* mcbsp3_dx */ \ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /* mcbsp3_dr */ \ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /* mcbsp3_clkx */ \ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /* mcbsp3_fsx */ \ /* UART2 */ \ - MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M0)) /* UART2_CTS */ \ - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /* UART2_RTS */ \ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /* UART2_TX */ \ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /* UART2_RX */ \ + MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M0)) /* uart2_cts */ \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /* uart2_rts */ \ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /* uart2_tx */ \ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /* uart2_rx */ \ /* UART1 */ \ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */ \ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /* UART1_RTS */ \ - MUX_VAL(CP(UART1_CTS), (IEN | PTD | DIS | M0)) /* UART1_CTS */ \ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */ \ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* uart1_tx */ \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /* uart1_rts */ \ + MUX_VAL(CP(UART1_CTS), (IEN | PTD | DIS | M0)) /* uart1_cts */ \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* uart1_rx */ \ /* MCBSP4 */ \ - MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /* GPIO_152: GPS_PWR_ON */ \ - MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /* GPIO_153: GPS_RESET_N */ \ - MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /* GPIO_154: FLASH_LED_TORCH */ \ - MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /* GPIO_155: FLASH_LED_EN */ \ + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /* gpio_152 */ \ + MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /* gpio_153 */ \ + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /* gpio_154 */ \ + MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /* gpio_155 */ \ /* MCBSP1 */ \ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /* MCBSP1_CLKR */ \ - MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /* MCBSP1_FSR */ \ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) /* MCBSP1_DX */ \ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /* MCBSP1_DR */ \ - MUX_VAL(CP(MCBSP_CLKS), (IDIS | PTD | DIS | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /* GPIO_161: OMAP_UART_SW */ \ - MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /* GPIO_162: IFX_UART_SW */ \ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /* mcbsp1_clkr */ \ + MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /* mcbsp1_fsr */ \ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) /* mcbsp1_dx */ \ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /* mcbsp1_dr */ \ + MUX_VAL(CP(MCBSP_CLKS), (IDIS | PTD | DIS | M7)) /* safe_mode */ \ + MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /* gpio_161 */ \ + MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /* gpio_162 */ \ /* UART3 */ \ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M4)) /* GPIO_163: HOOK_DIG */ \ - MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX_IRRX */ \ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX_IRTX */ \ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M4)) /* gpio_163 */ \ + MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* uart3_rx_irrx */ \ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* uart3_tx_irtx */ \ /* HSUSB0 */ \ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | EN | M0)) /* HSUSB0_CLK */\ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTD | DIS | M0)) /* HSUSB0_STP */\ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | EN | M0)) /* HSUSB0_DIR */\ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | EN | M0)) /* HSUSB0_NXT */\ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | EN | M0)) /* HSUSB0_DATA0 */\ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | EN | M0)) /* HSUSB0_DATA1 */\ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | EN | M0)) /* HSUSB0_DATA2 */\ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | EN | M0)) /* HSUSB0_DATA3 */\ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | EN | M0)) /* HSUSB0_DATA4 */\ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | EN | M0)) /* HSUSB0_DATA5 */\ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | EN | M0)) /* HSUSB0_DATA6 */\ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | EN | M0)) /* HSUSB0_DATA7 */ \ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | EN | M0)) /* hsusb0_clk */\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTD | DIS | M0)) /* hsusb0_stp */\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | EN | M0)) /* hsusb0_dir */\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | EN | M0)) /* hsusb0_nxt */\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | EN | M0)) /* hsusb0_data0 */\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | EN | M0)) /* hsusb0_data1 */\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | EN | M0)) /* hsusb0_data2 */\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | EN | M0)) /* hsusb0_data3 */\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | EN | M0)) /* hsusb0_data4 */\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | EN | M0)) /* hsusb0_data5 */\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | EN | M0)) /* hsusb0_data6 */\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | EN | M0)) /* hsusb0_data7 */ \ /* I2C1 */ \ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */ \ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */ \ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* i2c1_scl */ \ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* i2c1_sda */ \ /* I2C2 */ \ - MUX_VAL(CP(I2C2_SCL), (IEN | PTD | DIS | M0)) /* I2C2_SCL */ \ - MUX_VAL(CP(I2C2_SDA), (IEN | PTD | DIS | M0)) /* I2C2_SDA */ \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTD | DIS | M0)) /* i2c2_scl */ \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTD | DIS | M0)) /* i2c2_sda */ \ /* I2C3 */ \ - MUX_VAL(CP(I2C3_SCL), (IEN | PTD | DIS | M0)) /* I2C3_SCL */ \ - MUX_VAL(CP(I2C3_SDA), (IEN | PTD | DIS | M0)) /* I2C3_SDA */ \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTD | DIS | M0)) /* i2c3_scl */ \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTD | DIS | M0)) /* i2c3_sda */ \ /* I2C4 */ \ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */ \ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */ \ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* i2c4_scl */ \ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* i2c4_sda */ \ /* HDQ */ \ - MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) /* GPIO_170: EAR_SENSE */ \ + MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) /* gpio_170 */ \ /* MCSPI1 */ \ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | DIS | M4)) /* GPIO_175: GAUGE_INT */ \ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /* GPIO_176: MODEM_SEND */ \ - MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTD | DIS | M4)) /* GPIO_177: MODEM_CHK */ \ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M0)) /* MCSPI2_CLK */ \ - MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | DIS | M0)) /* MCSPI2_SIMO */ \ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /* MCSPI2_SOMI */ \ - MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTD | DIS | M4)) /* GPIO_181: WLAN_WAKEUP */ \ - MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | DIS | M4)) /* GPIO_182: USIF1_SW */ \ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | DIS | M4)) /* gpio_175 */ \ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /* gpio_176 */ \ + MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTD | DIS | M4)) /* gpio_177 */ \ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M0)) /* mcspi2_clk */ \ + MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | DIS | M0)) /* mcspi2_simo */ \ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /* mcspi2_somi */ \ + MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTD | DIS | M4)) /* gpio_181 */ \ + MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | DIS | M4)) /* gpio_182 */ \ /* SYS */ \ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */ \ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /* SYS_CLKREQ */ \ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /* SYS_NIRQ */ \ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTU | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(SYS_OFF_MODE), (IDIS | PTD | DIS | M0)) /* SYS_OFF_MODE */ \ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4)) /* GPIO_10: MICROSD_DET_N */ \ - MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | EN | M7)) /* SAFE_MODE */ \ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* sys_32k */ \ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /* sys_clkreq */ \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /* sys_nirq */ \ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTU | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(SYS_OFF_MODE), (IDIS | PTD | DIS | M0)) /* sys_off_mode */ \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4)) /* gpio_10 */ \ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | EN | M7)) /* safe_mode */ \ /* JTAG */ \ - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /* JTAG_NTRST */ \ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /* JTAG_TCK */ \ - MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M0)) /* JTAG_TMS */ \ - MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M0)) /* JTAG_TDI */ \ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /* JTAG_EMU0 */ \ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /* JTAG_EMU1 */ \ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /* jtag_ntrst */ \ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /* jtag_tck */ \ + MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M0)) /* jtag_tms */ \ + MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M0)) /* jtag_tdi */ \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /* jtag_emu0 */ \ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /* jtag_emu1 */ \ /* ETK */ \ - MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_CLK */ \ - MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /* SDMMC3_CMD */ \ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M4)) /* GPIO_14: PROX_OUT */ \ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M4)) /* GPIO_15: CHG_STATUS_N_OMAP */ \ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | DIS | M4)) /* GPIO_16: BT_EN */ \ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT3 */ \ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT0 */ \ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT1 */ \ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT2 */ \ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M4)) /* GPIO_21: IPC_SRDY */ \ - MUX_VAL(CP(ETK_D8_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_22: IPC_MRDY */ \ - MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_23: WLAN_EN */ \ - MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | EN | M4)) /* GPIO_24: WLAN_HOST_WAKEUP */ \ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_25: CHG_EN_SET_N_OMAP */ \ - MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_26: IFX_RESET_1.8V */ \ - MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_27: IFX_PWRON_1.8V */ \ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28: CRADLE_DETECT_N */ \ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | EN | M4)) /* GPIO_29: CRADLE_DETECT_S */ \ + MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_clk */ \ + MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /* sdmmc3_cmd */ \ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M4)) /* gpio_14 */ \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M4)) /* gpio_15 */ \ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | DIS | M4)) /* gpio_16 */ \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat3 */ \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat0 */ \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat1 */ \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat2 */ \ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M4)) /* gpio_21 */ \ + MUX_VAL(CP(ETK_D8_ES2), (IDIS | PTD | DIS | M4)) /* gpio_22 */ \ + MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /* gpio_23 */ \ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | EN | M4)) /* gpio_24 */ \ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) /* gpio_25 */ \ + MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | DIS | M4)) /* gpio_26 */ \ + MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | DIS | M4)) /* gpio_27 */ \ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* gpio_28 */ \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | EN | M4)) /* gpio_29 */ \ /* D2D */ \ - MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0)) /* D2D_MCAD0 */ \ - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /* D2D_MCAD1 */ \ - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /* D2D_MCAD2 */ \ - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /* D2D_MCAD3 */ \ - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /* D2D_MCAD4 */ \ - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /* D2D_MCAD5 */ \ - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /* D2D_MCAD6 */ \ - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /* D2D_MCAD7 */ \ - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /* D2D_MCAD8 */ \ - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /* D2D_MCAD9 */ \ - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /* D2D_MCAD10 */ \ - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /* D2D_MCAD11 */ \ - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /* D2D_MCAD12 */ \ - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /* D2D_MCAD13 */ \ - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /* D2D_MCAD14 */ \ - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /* D2D_MCAD15 */ \ - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /* D2D_MCAD16 */ \ - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /* D2D_MCAD17 */ \ - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /* D2D_MCAD18 */ \ - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /* D2D_MCAD19 */ \ - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /* D2D_MCAD20 */ \ - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /* D2D_MCAD21 */ \ - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /* D2D_MCAD22 */ \ - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /* D2D_MCAD23 */ \ - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /* D2D_MCAD24 */ \ - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /* D2D_MCAD25 */ \ - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /* D2D_MCAD26 */ \ - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /* D2D_MCAD27 */ \ - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /* D2D_MCAD28 */ \ - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /* D2D_MCAD29 */ \ - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /* D2D_MCAD30 */ \ - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /* D2D_MCAD31 */ \ - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /* D2D_MCAD32 */ \ - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /* D2D_MCAD33 */ \ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /* D2D_MCAD34 */ \ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /* D2D_MCAD35 */ \ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /* D2D_MCAD36 */ \ - MUX_VAL(CP(D2D_CLK26MI), (IDIS | PTD | DIS | M0)) /* D2D_CLK26MI */ \ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTU | EN | M0)) /* D2D_NRESPWRON */ \ - MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTD | DIS | M0)) /* D2D_NRESWARM */ \ - MUX_VAL(CP(D2D_ARM9NIRQ), (IDIS | PTD | DIS | M0)) /* D2D_ARM9NIRQ */ \ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IDIS | PTD | DIS | M0)) /* D2D_UMA2P6FIQ */ \ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | DIS | M0)) /* D2D_SPINT */ \ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | DIS | M0)) /* D2D_FRINT */ \ - MUX_VAL(CP(D2D_DMAREQ0), (IDIS | PTD | DIS | M0)) /* D2D_DMAREQ0 */ \ - MUX_VAL(CP(D2D_DMAREQ1), (IDIS | PTD | DIS | M0)) /* D2D_DMAREQ1 */ \ - MUX_VAL(CP(D2D_DMAREQ2), (IDIS | PTD | DIS | M0)) /* D2D_DMAREQ2 */ \ - MUX_VAL(CP(D2D_DMAREQ3), (IDIS | PTD | DIS | M0)) /* D2D_DMAREQ3 */ \ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /* D2D_N3GTRST */ \ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTU | EN | M0)) /* D2D_N3GTDI */ \ - MUX_VAL(CP(D2D_N3GTDO), (IDIS | PTD | DIS | M0)) /* D2D_N3GTDO */ \ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTU | EN | M0)) /* D2D_N3GTMS */ \ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /* D2D_N3GTCK */ \ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /* D2D_N3GRTCK */ \ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /* D2D_MSTDBY */ \ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /* D2D_SWAKEUP */ \ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /* D2D_IDLEREQ */ \ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /* D2D_IDLEACK */ \ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /* D2D_MWRITE */ \ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /* D2D_SWRITE */ \ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /* D2D_MREAD */ \ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /* D2D_SREAD */ \ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /* D2D_MBUSFLAG */ \ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /* D2D_SBUSFLAG */ \ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTD | DIS | M0)) /* SDRC_CKE0 */ \ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M0)) /* SDRC_CKE1 */ \ - MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(GPIO126), (IDIS | PTD | DIS | M4)) /* GPIO_126: OMAP_SEND */ \ - MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /* GPIO_128: KEY_LED_RESET */ \ - MUX_VAL(CP(GPIO129), (IEN | PTD | DIS | M4)) /* GPIO_129: MODEM_AP_WAKE */ + MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0)) /* d2d_mcad0 */ \ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /* d2d_mcad1 */ \ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /* d2d_mcad2 */ \ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /* d2d_mcad3 */ \ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /* d2d_mcad4 */ \ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /* d2d_mcad5 */ \ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /* d2d_mcad6 */ \ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /* d2d_mcad7 */ \ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /* d2d_mcad8 */ \ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /* d2d_mcad9 */ \ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /* d2d_mcad10 */ \ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /* d2d_mcad11 */ \ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /* d2d_mcad12 */ \ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /* d2d_mcad13 */ \ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /* d2d_mcad14 */ \ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /* d2d_mcad15 */ \ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /* d2d_mcad16 */ \ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /* d2d_mcad17 */ \ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /* d2d_mcad18 */ \ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /* d2d_mcad19 */ \ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /* d2d_mcad20 */ \ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /* d2d_mcad21 */ \ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /* d2d_mcad22 */ \ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /* d2d_mcad23 */ \ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /* d2d_mcad24 */ \ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /* d2d_mcad25 */ \ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /* d2d_mcad26 */ \ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /* d2d_mcad27 */ \ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /* d2d_mcad28 */ \ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /* d2d_mcad29 */ \ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /* d2d_mcad30 */ \ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /* d2d_mcad31 */ \ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /* d2d_mcad32 */ \ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /* d2d_mcad33 */ \ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /* d2d_mcad34 */ \ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /* d2d_mcad35 */ \ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /* d2d_mcad36 */ \ + MUX_VAL(CP(D2D_CLK26MI), (IDIS | PTD | DIS | M0)) /* d2d_clk26mi */ \ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTU | EN | M0)) /* d2d_nrespwron */ \ + MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTD | DIS | M0)) /* d2d_nreswarm */ \ + MUX_VAL(CP(D2D_ARM9NIRQ), (IDIS | PTD | DIS | M0)) /* d2d_arm9nirq */ \ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IDIS | PTD | DIS | M0)) /* d2d_uma2p6fiq */ \ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | DIS | M0)) /* d2d_spint */ \ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | DIS | M0)) /* d2d_frint */ \ + MUX_VAL(CP(D2D_DMAREQ0), (IDIS | PTD | DIS | M0)) /* d2d_dmareq0 */ \ + MUX_VAL(CP(D2D_DMAREQ1), (IDIS | PTD | DIS | M0)) /* d2d_dmareq1 */ \ + MUX_VAL(CP(D2D_DMAREQ2), (IDIS | PTD | DIS | M0)) /* d2d_dmareq2 */ \ + MUX_VAL(CP(D2D_DMAREQ3), (IDIS | PTD | DIS | M0)) /* d2d_dmareq3 */ \ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /* d2d_n3gtrst */ \ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTU | EN | M0)) /* d2d_n3gtdi */ \ + MUX_VAL(CP(D2D_N3GTDO), (IDIS | PTD | DIS | M0)) /* d2d_n3gtdo */ \ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTU | EN | M0)) /* d2d_n3gtms */ \ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /* d2d_n3gtck */ \ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /* d2d_n3grtck */ \ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /* d2d_mstdby */ \ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /* d2d_swakeup */ \ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /* d2d_idlereq */ \ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /* d2d_idleack */ \ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /* d2d_mwrite */ \ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /* d2d_swrite */ \ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /* d2d_mread */ \ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /* d2d_sread */ \ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /* d2d_mbusflag */ \ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /* d2d_sbusflag */ \ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTD | DIS | M0)) /* sdrc_cke0 */ \ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M0)) /* sdrc_cke1 */ \ + MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M7)) /* safe_mode */ \ + MUX_VAL(CP(GPIO126), (IDIS | PTD | DIS | M4)) /* gpio_126 */ \ + MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /* gpio_128 */ \ + MUX_VAL(CP(GPIO129), (IEN | PTD | DIS | M4)) /* gpio_129 */ #endif diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c index f159af9fbe..f784459d8e 100644 --- a/board/tbs/tbs2910/tbs2910.c +++ b/board/tbs/tbs2910/tbs2910.c @@ -378,7 +378,7 @@ static const struct boot_mode board_boot_modes[] = { {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, /* 8 bit bus width */ - {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, {NULL, 0}, }; #endif diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig index 0474deb474..0335795c84 100644 --- a/configs/sniper_defconfig +++ b/configs/sniper_defconfig @@ -2,10 +2,13 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_SNIPER=y CONFIG_SPL=y -CONFIG_SYS_PROMPT="Sniper # " +CONFIG_SYS_PROMPT="sniper # " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_MUSB_GADGET=y diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index 535f96fb63..4d7afb82c7 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -1,8 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_ARCH_UNIPHIER_PH1_LD4=y -CONFIG_ARCH_UNIPHIER_PH1_SLD8=y +CONFIG_ARCH_UNIPHIER_LD4_SLD8=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref" @@ -13,12 +12,15 @@ CONFIG_CMD_NAND=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y # CONFIG_CMD_MISC is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_SIMPLE_BUS=y +CONFIG_GPIO_UNIPHIER=y +CONFIG_MMC_UNIPHIER=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig index 2361db6ab5..45ef8837e2 100644 --- a/configs/uniphier_pro4_defconfig +++ b/configs/uniphier_pro4_defconfig @@ -12,12 +12,15 @@ CONFIG_CMD_NAND=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y # CONFIG_CMD_MISC is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_SIMPLE_BUS=y +CONFIG_GPIO_UNIPHIER=y +CONFIG_MMC_UNIPHIER=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 diff --git a/configs/uniphier_pro5_defconfig b/configs/uniphier_pro5_defconfig deleted file mode 100644 index be0d7b5390..0000000000 --- a/configs/uniphier_pro5_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_UNIPHIER=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_ARCH_UNIPHIER_PH1_PRO5=y -CONFIG_MICRO_SUPPORT_CARD=y -CONFIG_SYS_TEXT_BASE=0x84000000 -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro5-4kbox" -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_ENV_EXISTS is not set -CONFIG_CMD_NAND=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -# CONFIG_CMD_FPGA is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_PING=y -CONFIG_CMD_TIME=y -# CONFIG_CMD_MISC is not set -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_SIMPLE_BUS=y -CONFIG_NAND_DENALI=y -CONFIG_SYS_NAND_DENALI_64BIT=y -CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 -CONFIG_SPL_NAND_DENALI=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_UNIPHIER_SERIAL=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig index f8cb794b8f..4a8d70b801 100644 --- a/configs/uniphier_pxs2_ld6b_defconfig +++ b/configs/uniphier_pxs2_ld6b_defconfig @@ -1,8 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_ARCH_UNIPHIER_PROXSTREAM2=y -CONFIG_ARCH_UNIPHIER_PH1_LD6B=y +CONFIG_ARCH_UNIPHIER_PRO5_PXS2_LD6B=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-proxstream2-vodka" @@ -13,12 +12,15 @@ CONFIG_CMD_NAND=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y # CONFIG_CMD_MISC is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_SIMPLE_BUS=y +CONFIG_GPIO_UNIPHIER=y +CONFIG_MMC_UNIPHIER=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig index e369c45e82..5f0d678c66 100644 --- a/configs/uniphier_sld3_defconfig +++ b/configs/uniphier_sld3_defconfig @@ -11,11 +11,14 @@ CONFIG_CMD_NAND=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y # CONFIG_CMD_MISC is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_GPIO_UNIPHIER=y +CONFIG_MMC_UNIPHIER=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 diff --git a/doc/README.uniphier b/doc/README.uniphier index bcf0ac3d4b..6c3b0924b2 100644 --- a/doc/README.uniphier +++ b/doc/README.uniphier @@ -45,8 +45,8 @@ PH1-Pro4 reference board: $ make CROSS_COMPILE=arm-linux-gnueabi- PH1-Pro5 4KBOX Board: - $ make uniphier_pro5_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- + $ make uniphier_pxs2_ld6b_defconfig + $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro5-4kbox ProXstream2 Gentil board: $ make uniphier_pxs2_ld6b_defconfig @@ -78,6 +78,20 @@ directory, and then run the following command at the U-Boot command line: => run nandupdate +Burn U-Boot images to eMMC +-------------------------- + +Write two files to the Boot partition 1 of the eMMC device as follows: + - spl/u-boot-spl.bin at the offset address 0x00000000 + - u-boot.img at the offset address 0x00010000 + +If a TFTP server is available, the images can be easily updated. +Just copy the u-boot-spl-dtb.bin and u-boot-dtb.img to the TFTP public +directory, and then run the following command at the U-Boot command line: + + => run emmcupdate + + UniPhier specific commands -------------------------- @@ -93,8 +107,10 @@ Supported devices - UART (on-chip) - NAND + - SD/eMMC - USB 2.0 (EHCI) - USB 3.0 (xHCI) + - GPIO - LAN (on-board SMSC9118) - I2C - EEPROM (connected to the on-board I2C bus) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 845dc725c5..94fabb9e18 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -76,6 +76,12 @@ config SANDBOX_GPIO_COUNT of 'anonymous' GPIOs that do not belong to any device or bank. Select a suitable value depending on your needs. +config GPIO_UNIPHIER + bool "UniPhier GPIO" + depends on ARCH_UNIPHIER + help + Say yes here to support UniPhier GPIOs. + config VYBRID_GPIO bool "Vybrid GPIO driver" depends on DM diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 845a6d4493..ca8c4879e4 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -43,6 +43,7 @@ oby-$(CONFIG_SX151X) += sx151x.o obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o +obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c new file mode 100644 index 0000000000..80bb16ec06 --- /dev/null +++ b/drivers/gpio/gpio-uniphier.c @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm/device.h> +#include <mapmem.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <asm/errno.h> +#include <asm/gpio.h> + +#define UNIPHIER_GPIO_PORTS_PER_BANK 8 + +#define UNIPHIER_GPIO_REG_DATA 0 /* data */ +#define UNIPHIER_GPIO_REG_DIR 4 /* direction (1:in, 0:out) */ + +struct uniphier_gpio_priv { + void __iomem *base; + char bank_name[16]; +}; + +static void uniphier_gpio_offset_write(struct udevice *dev, unsigned offset, + unsigned reg, int value) +{ + struct uniphier_gpio_priv *priv = dev_get_priv(dev); + u32 tmp; + + tmp = readl(priv->base + reg); + if (value) + tmp |= BIT(offset); + else + tmp &= ~BIT(offset); + writel(tmp, priv->base + reg); +} + +static int uniphier_gpio_offset_read(struct udevice *dev, unsigned offset, + unsigned reg) +{ + struct uniphier_gpio_priv *priv = dev_get_priv(dev); + + return !!(readl(priv->base + reg) & BIT(offset)); +} + +static int uniphier_gpio_direction_input(struct udevice *dev, unsigned offset) +{ + uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DIR, 1); + + return 0; +} + +static int uniphier_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) +{ + uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DATA, value); + uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DIR, 0); + + return 0; +} + +static int uniphier_gpio_get_value(struct udevice *dev, unsigned offset) +{ + return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_REG_DATA); +} + +static int uniphier_gpio_set_value(struct udevice *dev, unsigned offset, + int value) +{ + uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DATA, value); + + return 0; +} + +static int uniphier_gpio_get_function(struct udevice *dev, unsigned offset) +{ + return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_REG_DIR) ? + GPIOF_INPUT : GPIOF_OUTPUT; +} + +static const struct dm_gpio_ops uniphier_gpio_ops = { + .direction_input = uniphier_gpio_direction_input, + .direction_output = uniphier_gpio_direction_output, + .get_value = uniphier_gpio_get_value, + .set_value = uniphier_gpio_set_value, + .get_function = uniphier_gpio_get_function, +}; + +static int uniphier_gpio_probe(struct udevice *dev) +{ + struct uniphier_gpio_priv *priv = dev_get_priv(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + DECLARE_GLOBAL_DATA_PTR; + fdt_addr_t addr; + fdt_size_t size; + unsigned int tmp; + + addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", + &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = map_sysmem(addr, size); + if (!priv->base) + return -ENOMEM; + + uc_priv->gpio_count = UNIPHIER_GPIO_PORTS_PER_BANK; + + tmp = (addr & 0xfff); + + /* Unfortunately, there is a register hole at offset 0x90-0x9f. */ + if (tmp > 0x90) + tmp -= 0x10; + + snprintf(priv->bank_name, sizeof(priv->bank_name) - 1, + "port%d-", (tmp - 8) / 8); + + uc_priv->bank_name = priv->bank_name; + + return 0; +} + +static int uniphier_gpio_remove(struct udevice *dev) +{ + struct uniphier_gpio_priv *priv = dev_get_priv(dev); + + unmap_sysmem(priv->base); + + return 0; +} + +/* .data = the number of GPIO banks */ +static const struct udevice_id uniphier_gpio_match[] = { + { .compatible = "socionext,uniphier-gpio" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(uniphier_gpio) = { + .name = "uniphier_gpio", + .id = UCLASS_GPIO, + .of_match = uniphier_gpio_match, + .probe = uniphier_gpio_probe, + .remove = uniphier_gpio_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv), + .ops = &uniphier_gpio_ops, +}; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 9d3f7e908f..dc8532fe93 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -43,4 +43,10 @@ config ZYNQ_SDHCI help Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform +config MMC_UNIPHIER + bool "UniPhier SD/MMC Host Controller support" + depends on ARCH_UNIPHIER + help + This selects support for the SD/MMC Host Controller on UniPhier SoCs. + endmenu diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index c9c3e3e938..b85e4bfb77 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_SH_SDHI) += sh_sdhi.o obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o +obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o ifdef CONFIG_SPL_BUILD diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c new file mode 100644 index 0000000000..3bc4d942a0 --- /dev/null +++ b/drivers/mmc/uniphier-sd.c @@ -0,0 +1,751 @@ +/* + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <fdtdec.h> +#include <mapmem.h> +#include <mmc.h> +#include <dm/device.h> +#include <linux/compat.h> +#include <linux/io.h> +#include <asm/unaligned.h> +#include <asm/dma-mapping.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UNIPHIER_SD_CMD 0x000 /* command */ +#define UNIPHIER_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */ +#define UNIPHIER_SD_CMD_MULTI BIT(13) /* multiple block transfer */ +#define UNIPHIER_SD_CMD_RD BIT(12) /* 1: read, 0: write */ +#define UNIPHIER_SD_CMD_DATA BIT(11) /* data transfer */ +#define UNIPHIER_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */ +#define UNIPHIER_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */ +#define UNIPHIER_SD_CMD_RSP_NONE (3 << 8)/* response: none */ +#define UNIPHIER_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */ +#define UNIPHIER_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */ +#define UNIPHIER_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */ +#define UNIPHIER_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */ +#define UNIPHIER_SD_ARG 0x008 /* command argument */ +#define UNIPHIER_SD_STOP 0x010 /* stop action control */ +#define UNIPHIER_SD_STOP_SEC BIT(8) /* use sector count */ +#define UNIPHIER_SD_STOP_STP BIT(0) /* issue CMD12 */ +#define UNIPHIER_SD_SECCNT 0x014 /* sector counter */ +#define UNIPHIER_SD_RSP10 0x018 /* response[39:8] */ +#define UNIPHIER_SD_RSP32 0x020 /* response[71:40] */ +#define UNIPHIER_SD_RSP54 0x028 /* response[103:72] */ +#define UNIPHIER_SD_RSP76 0x030 /* response[127:104] */ +#define UNIPHIER_SD_INFO1 0x038 /* IRQ status 1 */ +#define UNIPHIER_SD_INFO1_CD BIT(5) /* state of card detect */ +#define UNIPHIER_SD_INFO1_INSERT BIT(4) /* card inserted */ +#define UNIPHIER_SD_INFO1_REMOVE BIT(3) /* card removed */ +#define UNIPHIER_SD_INFO1_CMP BIT(2) /* data complete */ +#define UNIPHIER_SD_INFO1_RSP BIT(0) /* response complete */ +#define UNIPHIER_SD_INFO2 0x03c /* IRQ status 2 */ +#define UNIPHIER_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */ +#define UNIPHIER_SD_INFO2_CBSY BIT(14) /* command busy */ +#define UNIPHIER_SD_INFO2_BWE BIT(9) /* write buffer ready */ +#define UNIPHIER_SD_INFO2_BRE BIT(8) /* read buffer ready */ +#define UNIPHIER_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */ +#define UNIPHIER_SD_INFO2_ERR_RTO BIT(6) /* response time out */ +#define UNIPHIER_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */ +#define UNIPHIER_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */ +#define UNIPHIER_SD_INFO2_ERR_TO BIT(3) /* time out error */ +#define UNIPHIER_SD_INFO2_ERR_END BIT(2) /* END bit error */ +#define UNIPHIER_SD_INFO2_ERR_CRC BIT(1) /* CRC error */ +#define UNIPHIER_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */ +#define UNIPHIER_SD_INFO1_MASK 0x040 +#define UNIPHIER_SD_INFO2_MASK 0x044 +#define UNIPHIER_SD_CLKCTL 0x048 /* clock divisor */ +#define UNIPHIER_SD_CLKCTL_DIV_MASK 0x104ff +#define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */ +#define UNIPHIER_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */ +#define UNIPHIER_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */ +#define UNIPHIER_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */ +#define UNIPHIER_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */ +#define UNIPHIER_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */ +#define UNIPHIER_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */ +#define UNIPHIER_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */ +#define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ +#define UNIPHIER_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */ +#define UNIPHIER_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */ +#define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */ +#define UNIPHIER_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */ +#define UNIPHIER_SD_SIZE 0x04c /* block size */ +#define UNIPHIER_SD_OPTION 0x050 +#define UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13) +#define UNIPHIER_SD_OPTION_WIDTH_1 (4 << 13) +#define UNIPHIER_SD_OPTION_WIDTH_4 (0 << 13) +#define UNIPHIER_SD_OPTION_WIDTH_8 (1 << 13) +#define UNIPHIER_SD_BUF 0x060 /* read/write buffer */ +#define UNIPHIER_SD_EXTMODE 0x1b0 +#define UNIPHIER_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */ +#define UNIPHIER_SD_SOFT_RST 0x1c0 +#define UNIPHIER_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */ +#define UNIPHIER_SD_VERSION 0x1c4 /* version register */ +#define UNIPHIER_SD_VERSION_IP 0xff /* IP version */ +#define UNIPHIER_SD_HOST_MODE 0x1c8 +#define UNIPHIER_SD_IF_MODE 0x1cc +#define UNIPHIER_SD_IF_MODE_DDR BIT(0) /* DDR mode */ +#define UNIPHIER_SD_VOLT 0x1e4 /* voltage switch */ +#define UNIPHIER_SD_VOLT_MASK (3 << 0) +#define UNIPHIER_SD_VOLT_OFF (0 << 0) +#define UNIPHIER_SD_VOLT_330 (1 << 0)/* 3.3V signal */ +#define UNIPHIER_SD_VOLT_180 (2 << 0)/* 1.8V signal */ +#define UNIPHIER_SD_DMA_MODE 0x410 +#define UNIPHIER_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */ +#define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */ +#define UNIPHIER_SD_DMA_CTL 0x414 +#define UNIPHIER_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */ +#define UNIPHIER_SD_DMA_RST 0x418 +#define UNIPHIER_SD_DMA_RST_RD BIT(9) +#define UNIPHIER_SD_DMA_RST_WR BIT(8) +#define UNIPHIER_SD_DMA_INFO1 0x420 +#define UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/ +#define UNIPHIER_SD_DMA_INFO1_END_RD BIT(17) /* Don't use! Hardware bug */ +#define UNIPHIER_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */ +#define UNIPHIER_SD_DMA_INFO1_MASK 0x424 +#define UNIPHIER_SD_DMA_INFO2 0x428 +#define UNIPHIER_SD_DMA_INFO2_ERR_RD BIT(17) +#define UNIPHIER_SD_DMA_INFO2_ERR_WR BIT(16) +#define UNIPHIER_SD_DMA_INFO2_MASK 0x42c +#define UNIPHIER_SD_DMA_ADDR_L 0x440 +#define UNIPHIER_SD_DMA_ADDR_H 0x444 + +/* alignment required by the DMA engine of this controller */ +#define UNIPHIER_SD_DMA_MINALIGN 0x10 + +struct uniphier_sd_priv { + struct mmc_config cfg; + struct mmc *mmc; + struct udevice *dev; + void __iomem *regbase; + unsigned long mclk; + unsigned int version; + u32 caps; +#define UNIPHIER_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */ +#define UNIPHIER_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */ +#define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ +}; + +static dma_addr_t __dma_map_single(void *ptr, size_t size, + enum dma_data_direction dir) +{ + unsigned long addr = (unsigned long)ptr; + + if (dir == DMA_FROM_DEVICE) + invalidate_dcache_range(addr, addr + size); + else + flush_dcache_range(addr, addr + size); + + return addr; +} + +static void __dma_unmap_single(dma_addr_t addr, size_t size, + enum dma_data_direction dir) +{ + if (dir != DMA_TO_DEVICE) + invalidate_dcache_range(addr, addr + size); +} + +static int uniphier_sd_check_error(struct uniphier_sd_priv *priv) +{ + u32 info2 = readl(priv->regbase + UNIPHIER_SD_INFO2); + + if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) { + /* + * TIMEOUT must be returned for unsupported command. Do not + * display error log since this might be a part of sequence to + * distinguish between SD and MMC. + */ + return TIMEOUT; + } + + if (info2 & UNIPHIER_SD_INFO2_ERR_TO) { + dev_err(priv->dev, "timeout error\n"); + return -ETIMEDOUT; + } + + if (info2 & (UNIPHIER_SD_INFO2_ERR_END | UNIPHIER_SD_INFO2_ERR_CRC | + UNIPHIER_SD_INFO2_ERR_IDX)) { + dev_err(priv->dev, "communication out of sync\n"); + return -EILSEQ; + } + + if (info2 & (UNIPHIER_SD_INFO2_ERR_ILA | UNIPHIER_SD_INFO2_ERR_ILR | + UNIPHIER_SD_INFO2_ERR_ILW)) { + dev_err(priv->dev, "illegal access\n"); + return -EIO; + } + + return 0; +} + +static int uniphier_sd_wait_for_irq(struct uniphier_sd_priv *priv, + unsigned int reg, u32 flag) +{ + long wait = 1000000; + int ret; + + while (!(readl(priv->regbase + reg) & flag)) { + if (wait-- < 0) { + dev_err(priv->dev, "timeout\n"); + return -ETIMEDOUT; + } + + ret = uniphier_sd_check_error(priv); + if (ret) + return ret; + + udelay(1); + } + + return 0; +} + +static int uniphier_sd_pio_read_one_block(struct mmc *mmc, u32 **pbuf, + uint blocksize) +{ + struct uniphier_sd_priv *priv = mmc->priv; + int i, ret; + + /* wait until the buffer is filled with data */ + ret = uniphier_sd_wait_for_irq(priv, UNIPHIER_SD_INFO2, + UNIPHIER_SD_INFO2_BRE); + if (ret) + return ret; + + /* + * Clear the status flag _before_ read the buffer out because + * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered. + */ + writel(0, priv->regbase + UNIPHIER_SD_INFO2); + + if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) { + for (i = 0; i < blocksize / 4; i++) + *(*pbuf)++ = readl(priv->regbase + UNIPHIER_SD_BUF); + } else { + for (i = 0; i < blocksize / 4; i++) + put_unaligned(readl(priv->regbase + UNIPHIER_SD_BUF), + (*pbuf)++); + } + + return 0; +} + +static int uniphier_sd_pio_write_one_block(struct mmc *mmc, const u32 **pbuf, + uint blocksize) +{ + struct uniphier_sd_priv *priv = mmc->priv; + int i, ret; + + /* wait until the buffer becomes empty */ + ret = uniphier_sd_wait_for_irq(priv, UNIPHIER_SD_INFO2, + UNIPHIER_SD_INFO2_BWE); + if (ret) + return ret; + + writel(0, priv->regbase + UNIPHIER_SD_INFO2); + + if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) { + for (i = 0; i < blocksize / 4; i++) + writel(*(*pbuf)++, priv->regbase + UNIPHIER_SD_BUF); + } else { + for (i = 0; i < blocksize / 4; i++) + writel(get_unaligned((*pbuf)++), + priv->regbase + UNIPHIER_SD_BUF); + } + + return 0; +} + +static int uniphier_sd_pio_xfer(struct mmc *mmc, struct mmc_data *data) +{ + u32 *dest = (u32 *)data->dest; + const u32 *src = (const u32 *)data->src; + int i, ret; + + for (i = 0; i < data->blocks; i++) { + if (data->flags & MMC_DATA_READ) + ret = uniphier_sd_pio_read_one_block(mmc, &dest, + data->blocksize); + else + ret = uniphier_sd_pio_write_one_block(mmc, &src, + data->blocksize); + if (ret) + return ret; + } + + return 0; +} + +static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv, + dma_addr_t dma_addr) +{ + u32 tmp; + + writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO1); + writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO2); + + /* enable DMA */ + tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE); + tmp |= UNIPHIER_SD_EXTMODE_DMA_EN; + writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE); + + writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_L); + + /* suppress the warning "right shift count >= width of type" */ + dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr)); + + writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_H); + + writel(UNIPHIER_SD_DMA_CTL_START, priv->regbase + UNIPHIER_SD_DMA_CTL); +} + +static int uniphier_sd_dma_wait_for_irq(struct uniphier_sd_priv *priv, u32 flag, + unsigned int blocks) +{ + long wait = 1000000 + 10 * blocks; + + while (!(readl(priv->regbase + UNIPHIER_SD_DMA_INFO1) & flag)) { + if (wait-- < 0) { + dev_err(priv->dev, "timeout during DMA\n"); + return -ETIMEDOUT; + } + + udelay(10); + } + + if (readl(priv->regbase + UNIPHIER_SD_DMA_INFO2)) { + dev_err(priv->dev, "error during DMA\n"); + return -EIO; + } + + return 0; +} + +static int uniphier_sd_dma_xfer(struct mmc *mmc, struct mmc_data *data) +{ + struct uniphier_sd_priv *priv = mmc->priv; + size_t len = data->blocks * data->blocksize; + void *buf; + enum dma_data_direction dir; + dma_addr_t dma_addr; + u32 poll_flag, tmp; + int ret; + + tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE); + + if (data->flags & MMC_DATA_READ) { + buf = data->dest; + dir = DMA_FROM_DEVICE; + poll_flag = UNIPHIER_SD_DMA_INFO1_END_RD2; + tmp |= UNIPHIER_SD_DMA_MODE_DIR_RD; + } else { + buf = (void *)data->src; + dir = DMA_TO_DEVICE; + poll_flag = UNIPHIER_SD_DMA_INFO1_END_WR; + tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD; + } + + writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE); + + dma_addr = __dma_map_single(buf, len, dir); + + uniphier_sd_dma_start(priv, dma_addr); + + ret = uniphier_sd_dma_wait_for_irq(priv, poll_flag, data->blocks); + + __dma_unmap_single(dma_addr, len, dir); + + return ret; +} + +/* check if the address is DMA'able */ +static bool uniphier_sd_addr_is_dmaable(unsigned long addr) +{ + if (!IS_ALIGNED(addr, UNIPHIER_SD_DMA_MINALIGN)) + return false; + +#if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \ + defined(CONFIG_SPL_BUILD) + /* + * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways + * of L2, which is unreachable from the DMA engine. + */ + if (addr < CONFIG_SPL_STACK) + return false; +#endif + + return true; +} + +static int uniphier_sd_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct uniphier_sd_priv *priv = mmc->priv; + int ret; + u32 tmp; + + if (readl(priv->regbase + UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) { + dev_err(priv->dev, "command busy\n"); + return -EBUSY; + } + + /* clear all status flags */ + writel(0, priv->regbase + UNIPHIER_SD_INFO1); + writel(0, priv->regbase + UNIPHIER_SD_INFO2); + + /* disable DMA once */ + tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE); + tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN; + writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE); + + writel(cmd->cmdarg, priv->regbase + UNIPHIER_SD_ARG); + + tmp = cmd->cmdidx; + + if (data) { + writel(data->blocksize, priv->regbase + UNIPHIER_SD_SIZE); + writel(data->blocks, priv->regbase + UNIPHIER_SD_SECCNT); + + /* Do not send CMD12 automatically */ + tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA; + + if (data->blocks > 1) + tmp |= UNIPHIER_SD_CMD_MULTI; + + if (data->flags & MMC_DATA_READ) + tmp |= UNIPHIER_SD_CMD_RD; + } + + /* + * Do not use the response type auto-detection on this hardware. + * CMD8, for example, has different response types on SD and eMMC, + * while this controller always assumes the response type for SD. + * Set the response type manually. + */ + switch (cmd->resp_type) { + case MMC_RSP_NONE: + tmp |= UNIPHIER_SD_CMD_RSP_NONE; + break; + case MMC_RSP_R1: + tmp |= UNIPHIER_SD_CMD_RSP_R1; + break; + case MMC_RSP_R1b: + tmp |= UNIPHIER_SD_CMD_RSP_R1B; + break; + case MMC_RSP_R2: + tmp |= UNIPHIER_SD_CMD_RSP_R2; + break; + case MMC_RSP_R3: + tmp |= UNIPHIER_SD_CMD_RSP_R3; + break; + default: + dev_err(priv->dev, "unknown response type\n"); + return -EINVAL; + } + + dev_dbg(priv->dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n", + cmd->cmdidx, tmp, cmd->cmdarg); + writel(tmp, priv->regbase + UNIPHIER_SD_CMD); + + ret = uniphier_sd_wait_for_irq(priv, UNIPHIER_SD_INFO1, + UNIPHIER_SD_INFO1_RSP); + if (ret) + return ret; + + if (cmd->resp_type & MMC_RSP_136) { + u32 rsp_127_104 = readl(priv->regbase + UNIPHIER_SD_RSP76); + u32 rsp_103_72 = readl(priv->regbase + UNIPHIER_SD_RSP54); + u32 rsp_71_40 = readl(priv->regbase + UNIPHIER_SD_RSP32); + u32 rsp_39_8 = readl(priv->regbase + UNIPHIER_SD_RSP10); + + cmd->response[0] = (rsp_127_104 & 0xffffff) << 8 | + (rsp_103_72 & 0xff); + cmd->response[1] = (rsp_103_72 & 0xffffff) << 8 | + (rsp_71_40 & 0xff); + cmd->response[2] = (rsp_71_40 & 0xffffff) << 8 | + (rsp_39_8 & 0xff); + cmd->response[3] = (rsp_39_8 & 0xffffff) << 8; + } else { + /* bit 39-8 */ + cmd->response[0] = readl(priv->regbase + UNIPHIER_SD_RSP10); + } + + if (data) { + /* use DMA if the HW supports it and the buffer is aligned */ + if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL && + uniphier_sd_addr_is_dmaable((long)data->src)) + ret = uniphier_sd_dma_xfer(mmc, data); + else + ret = uniphier_sd_pio_xfer(mmc, data); + + ret = uniphier_sd_wait_for_irq(priv, UNIPHIER_SD_INFO1, + UNIPHIER_SD_INFO1_CMP); + if (ret) + return ret; + } + + return ret; +} + +static void uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv, + struct mmc *mmc) +{ + u32 val, tmp; + + switch (mmc->bus_width) { + case 1: + val = UNIPHIER_SD_OPTION_WIDTH_1; + break; + case 4: + val = UNIPHIER_SD_OPTION_WIDTH_4; + break; + case 8: + val = UNIPHIER_SD_OPTION_WIDTH_8; + break; + default: + BUG(); + break; + } + + tmp = readl(priv->regbase + UNIPHIER_SD_OPTION); + tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK; + tmp |= val; + writel(tmp, priv->regbase + UNIPHIER_SD_OPTION); +} + +static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv, + struct mmc *mmc) +{ + u32 tmp; + + tmp = readl(priv->regbase + UNIPHIER_SD_IF_MODE); + if (mmc->ddr_mode) + tmp |= UNIPHIER_SD_IF_MODE_DDR; + else + tmp &= ~UNIPHIER_SD_IF_MODE_DDR; + writel(tmp, priv->regbase + UNIPHIER_SD_IF_MODE); +} + +static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv, + struct mmc *mmc) +{ + unsigned int divisor; + u32 val, tmp; + + if (!mmc->clock) + return; + + divisor = DIV_ROUND_UP(priv->mclk, mmc->clock); + + if (divisor <= 1) + val = UNIPHIER_SD_CLKCTL_DIV1; + else if (divisor <= 2) + val = UNIPHIER_SD_CLKCTL_DIV2; + else if (divisor <= 4) + val = UNIPHIER_SD_CLKCTL_DIV4; + else if (divisor <= 8) + val = UNIPHIER_SD_CLKCTL_DIV8; + else if (divisor <= 16) + val = UNIPHIER_SD_CLKCTL_DIV16; + else if (divisor <= 32) + val = UNIPHIER_SD_CLKCTL_DIV32; + else if (divisor <= 64) + val = UNIPHIER_SD_CLKCTL_DIV64; + else if (divisor <= 128) + val = UNIPHIER_SD_CLKCTL_DIV128; + else if (divisor <= 256) + val = UNIPHIER_SD_CLKCTL_DIV256; + else if (divisor <= 512 || !(priv->caps & UNIPHIER_SD_CAP_DIV1024)) + val = UNIPHIER_SD_CLKCTL_DIV512; + else + val = UNIPHIER_SD_CLKCTL_DIV1024; + + tmp = readl(priv->regbase + UNIPHIER_SD_CLKCTL); + + /* stop the clock before changing its rate to avoid a glitch signal */ + tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN; + writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL); + + tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK; + tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN; + writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL); + + tmp |= UNIPHIER_SD_CLKCTL_SCLKEN; + writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL); +} + +static void uniphier_sd_set_ios(struct mmc *mmc) +{ + struct uniphier_sd_priv *priv = mmc->priv; + + dev_dbg(priv->dev, "clock %uHz, DDRmode %d, width %u\n", + mmc->clock, mmc->ddr_mode, mmc->bus_width); + + uniphier_sd_set_bus_width(priv, mmc); + uniphier_sd_set_ddr_mode(priv, mmc); + uniphier_sd_set_clk_rate(priv, mmc); + + udelay(1000); +} + +static int uniphier_sd_init(struct mmc *mmc) +{ + struct uniphier_sd_priv *priv = mmc->priv; + u32 tmp; + + /* soft reset of the host */ + tmp = readl(priv->regbase + UNIPHIER_SD_SOFT_RST); + tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX; + writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST); + tmp |= UNIPHIER_SD_SOFT_RST_RSTX; + writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST); + + /* FIXME: implement eMMC hw_reset */ + + writel(UNIPHIER_SD_STOP_SEC, priv->regbase + UNIPHIER_SD_STOP); + + /* + * Connected to 32bit AXI. + * This register dropped backward compatibility at version 0x10. + * Write an appropriate value depending on the IP version. + */ + writel(priv->version >= 0x10 ? 0x00000101 : 0x00000000, + priv->regbase + UNIPHIER_SD_HOST_MODE); + + if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) { + tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE); + tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC; + writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE); + } + + return 0; +} + +static int uniphier_sd_getcd(struct mmc *mmc) +{ + struct uniphier_sd_priv *priv = mmc->priv; + + if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE) + return 1; + + return !!(readl(priv->regbase + UNIPHIER_SD_INFO1) & + UNIPHIER_SD_INFO1_CD); +} + +static const struct mmc_ops uniphier_sd_ops = { + .send_cmd = uniphier_sd_send_cmd, + .set_ios = uniphier_sd_set_ios, + .init = uniphier_sd_init, + .getcd = uniphier_sd_getcd, +}; + +int uniphier_sd_probe(struct udevice *dev) +{ + struct uniphier_sd_priv *priv = dev_get_priv(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + fdt_addr_t base; + fdt_size_t size; + struct udevice *clk_dev; + int clk_id; + int ret; + + priv->dev = dev; + + base = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size); + priv->regbase = map_sysmem(base, size); + if (!priv->regbase) + return -ENOMEM; + + clk_id = clk_get_by_index(dev, 0, &clk_dev); + if (clk_id < 0) { + dev_err(dev, "failed to get host clock\n"); + return clk_id; + } + + /* set to max rate */ + priv->mclk = clk_set_periph_rate(clk_dev, clk_id, ULONG_MAX); + if (IS_ERR_VALUE(priv->mclk)) { + dev_err(dev, "failed to set rate for host clock\n"); + return priv->mclk; + } + + ret = clk_enable(clk_dev, clk_id); + if (ret) { + dev_err(dev, "failed to enable host clock\n"); + return ret; + } + + priv->cfg.name = dev->name; + priv->cfg.ops = &uniphier_sd_ops; + priv->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; + + switch (fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width", 1)) { + case 8: + priv->cfg.host_caps |= MMC_MODE_8BIT; + break; + case 4: + priv->cfg.host_caps |= MMC_MODE_4BIT; + break; + case 1: + break; + default: + dev_err(dev, "Invalid \"bus-width\" value\n"); + return -EINVAL; + } + + if (fdt_get_property(gd->fdt_blob, dev->of_offset, "non-removable", + NULL)) + priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE; + + priv->version = readl(priv->regbase + UNIPHIER_SD_VERSION) & + UNIPHIER_SD_VERSION_IP; + dev_dbg(dev, "version %x\n", priv->version); + if (priv->version >= 0x10) { + priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL; + priv->caps |= UNIPHIER_SD_CAP_DIV1024; + } + + priv->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; + priv->cfg.f_min = priv->mclk / + (priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512); + priv->cfg.f_max = priv->mclk; + priv->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */ + + priv->mmc = mmc_create(&priv->cfg, priv); + if (!priv->mmc) + return -EIO; + + upriv->mmc = priv->mmc; + + return 0; +} + +int uniphier_sd_remove(struct udevice *dev) +{ + struct uniphier_sd_priv *priv = dev_get_priv(dev); + + unmap_sysmem(priv->regbase); + mmc_destroy(priv->mmc); + + return 0; +} + +static const struct udevice_id uniphier_sd_match[] = { + { .compatible = "socionext,uniphier-sdhc" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(uniphier_mmc) = { + .name = "uniphier-mmc", + .id = UCLASS_MMC, + .of_match = uniphier_sd_match, + .probe = uniphier_sd_probe, + .remove = uniphier_sd_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_sd_priv), +}; diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 28da9ddfd8..93dad338b3 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -105,7 +105,7 @@ static void ns16550_writeb(NS16550_t port, int offset, int value) * As far as we know it doesn't make sense to support selection of * these options at run-time, so use the existing CONFIG options. */ - serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); + serial_out_shift(addr, plat->reg_shift, value); } static int ns16550_readb(NS16550_t port, int offset) @@ -116,7 +116,7 @@ static int ns16550_readb(NS16550_t port, int offset) offset *= 1 << plat->reg_shift; addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset; - return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); + return serial_in_shift(addr, plat->reg_shift); } /* We can clean these up once everything is moved to driver model */ @@ -401,8 +401,6 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) return -EINVAL; plat->base = addr; - plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, - "reg-offset", 0); plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg-shift", 0); plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 78d8044e68..60d6be7a16 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -69,7 +69,6 @@ * Miscellaneous configurable options */ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 4658283014..0196280739 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -44,8 +44,25 @@ #ifndef CONFIG_SPL_BUILD /* Define the default GPT table for eMMC */ #define PARTS_DEFAULT \ + /* Linux partitions */ \ "uuid_disk=${uuid_gpt_disk};" \ - "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ + /* Android partitions */ \ + "partitions_android=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=xloader,start=128K,size=128K,uuid=${uuid_gpt_xloader};" \ + "name=bootloader,size=384K,uuid=${uuid_gpt_bootloader};" \ + "name=environment,size=128K,uuid=${uuid_gpt_environment};" \ + "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ + "name=efs,start=1280K,size=16M,uuid=${uuid_gpt_efs};" \ + "name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \ + "name=recovery,size=10M,uuid=${uuid_gpt_recovery};" \ + "name=boot,size=10M,uuid=${uuid_gpt_boot};" \ + "name=system,size=768M,uuid=${uuid_gpt_system};" \ + "name=cache,size=256M,uuid=${uuid_gpt_cache};" \ + "name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \ + "name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \ + "name=userdata,size=-,uuid=${uuid_gpt_userdata}" #define DFU_ALT_INFO_MMC \ "dfu_alt_info_mmc=" \ @@ -116,6 +133,7 @@ /* Enhance our eMMC support / experience. */ #define CONFIG_CMD_GPT #define CONFIG_EFI_PARTITION +#define CONFIG_RANDOM_UUID #define CONFIG_HSMMC2_8BIT /* CPSW Ethernet */ diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index fdb4134b13..25a4630e1e 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -31,6 +31,8 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MXC_GPIO +#define CONFIG_CMD_BOOTZ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI #define CONFIG_NAND_MXC @@ -93,12 +95,12 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "uimage=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr=0x71000000\0" \ + "fdt_addr=0x78000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ @@ -130,16 +132,16 @@ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -154,16 +156,16 @@ "${get_cmd} ${uimage}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 4152ecde26..171a8c4ced 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -61,11 +61,8 @@ */ #define CONFIG_SYS_TEXT_BASE 0x80100000 -#define CONFIG_SYS_SDRAM_BASE OMAP34XX_SDRC_CS0 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020F800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) @@ -103,8 +100,8 @@ * MMC */ -#define CONFIG_GENERIC_MMC #define CONFIG_MMC +#define CONFIG_GENERIC_MMC #define CONFIG_OMAP_HSMMC #define CONFIG_CMD_MMC @@ -183,7 +180,6 @@ * Serial */ - #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) @@ -192,7 +188,6 @@ #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 #define CONFIG_CONS_INDEX 3 -#define CONFIG_SERIAL3 3 #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index fcec0c0ae2..b1c8ccb7b9 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -99,16 +99,16 @@ #define CONFIG_CONS_INDEX 1 -/* - * For NAND booting the environment is embedded in the U-Boot image. Please take - * look at the file board/amcc/canyonlands/u-boot-nand.lds for details. - */ +/* #define CONFIG_ENV_IS_NOWHERE */ /* #define CONFIG_ENV_IS_IN_NAND */ -#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET 0x80000 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET 0x0 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 1 + /* Time clock 1MHz */ #define CONFIG_SYS_TIMER_RATE 1000000 @@ -146,6 +146,11 @@ #define CONFIG_FAT_WRITE #define CONFIG_DOS_PARTITION +/* SD/MMC */ +#define CONFIG_CMD_MMC +#define CONFIG_SUPPORT_EMMC_BOOT +#define CONFIG_GENERIC_MMC + /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) @@ -228,6 +233,13 @@ "netdev=eth0\0" \ "verify=n\0" \ "nor_base=0x42000000\0" \ + "emmcupdate=mmcsetn &&" \ + "mmc partconf $mmc_first_dev 0 1 1 &&" \ + "mmc erase 0 800 &&" \ + "tftpboot u-boot-spl.bin &&" \ + "mmc write $loadaddr 0 80 &&" \ + "tftpboot u-boot.img &&" \ + "mmc write $loadaddr 80 780\0" \ "nandupdate=nand erase 0 0x00100000 &&" \ "tftpboot u-boot-spl.bin &&" \ "nand write $loadaddr 0 0x00010000 &&" \ @@ -259,6 +271,7 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */ #define CONFIG_SPL_LIBGENERIC_SUPPORT @@ -266,6 +279,7 @@ #define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h index e057bd2a84..22ab246fee 100644 --- a/include/linux/compiler-gcc.h +++ b/include/linux/compiler-gcc.h @@ -5,14 +5,28 @@ /* * Common definitions for all gcc versions go here. */ -#define GCC_VERSION (__GNUC__ * 10000 \ - + __GNUC_MINOR__ * 100 \ - + __GNUC_PATCHLEVEL__) - +#define GCC_VERSION (__GNUC__ * 10000 \ + + __GNUC_MINOR__ * 100 \ + + __GNUC_PATCHLEVEL__) /* Optimization barrier */ + /* The "volatile" is due to gcc bugs */ #define barrier() __asm__ __volatile__("": : :"memory") +/* + * This version is i.e. to prevent dead stores elimination on @ptr + * where gcc and llvm may behave differently when otherwise using + * normal barrier(): while gcc behavior gets along with a normal + * barrier(), llvm needs an explicit input variable to be assumed + * clobbered. The issue is as follows: while the inline asm might + * access any memory it wants, the compiler could have fit all of + * @ptr into memory registers instead, and since @ptr never escaped + * from that, it proofed that the inline asm wasn't touching any of + * it. This version works well with both compilers, i.e. we're telling + * the compiler that the inline asm absolutely may see the contents + * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495 + */ +#define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory") /* * This macro obfuscates arithmetic on a variable address so that gcc @@ -32,58 +46,63 @@ * the inline assembly constraint from =g to =r, in this particular * case either is valid. */ -#define RELOC_HIDE(ptr, off) \ - ({ unsigned long __ptr; \ - __asm__ ("" : "=r"(__ptr) : "0"(ptr)); \ - (typeof(ptr)) (__ptr + (off)); }) +#define RELOC_HIDE(ptr, off) \ +({ \ + unsigned long __ptr; \ + __asm__ ("" : "=r"(__ptr) : "0"(ptr)); \ + (typeof(ptr)) (__ptr + (off)); \ +}) /* Make the optimizer believe the variable can be manipulated arbitrarily. */ -#define OPTIMIZER_HIDE_VAR(var) __asm__ ("" : "=r" (var) : "0" (var)) +#define OPTIMIZER_HIDE_VAR(var) \ + __asm__ ("" : "=r" (var) : "0" (var)) #ifdef __CHECKER__ -#define __must_be_array(arr) 0 +#define __must_be_array(a) 0 #else /* &a[0] degrades to a pointer: a different type from an array */ -#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0])) +#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0])) #endif /* * Force always-inline if the user requests it so via the .config, * or if gcc is too old: */ -#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \ +#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \ !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4) -# define inline inline __attribute__((always_inline)) notrace -# define __inline__ __inline__ __attribute__((always_inline)) notrace -# define __inline __inline __attribute__((always_inline)) notrace +#define inline inline __attribute__((always_inline)) notrace +#define __inline__ __inline__ __attribute__((always_inline)) notrace +#define __inline __inline __attribute__((always_inline)) notrace #else /* A lot of inline functions can cause havoc with function tracing */ -# define inline inline notrace -# define __inline__ __inline__ notrace -# define __inline __inline notrace +#define inline inline notrace +#define __inline__ __inline__ notrace +#define __inline __inline notrace #endif -#define __deprecated __attribute__((deprecated)) -#ifndef __packed -#define __packed __attribute__((packed)) -#endif -#ifndef __weak -#define __weak __attribute__((weak)) -#endif +#define __always_inline inline __attribute__((always_inline)) +#define noinline __attribute__((noinline)) + +#define __deprecated __attribute__((deprecated)) +#define __packed __attribute__((packed)) +#define __weak __attribute__((weak)) +#define __alias(symbol) __attribute__((alias(#symbol))) /* - * it doesn't make sense on ARM (currently the only user of __naked) to trace - * naked functions because then mcount is called without stack and frame pointer - * being set up and there is no chance to restore the lr register to the value - * before mcount was called. + * it doesn't make sense on ARM (currently the only user of __naked) + * to trace naked functions because then mcount is called without + * stack and frame pointer being set up and there is no chance to + * restore the lr register to the value before mcount was called. + * + * The asm() bodies of naked functions often depend on standard calling + * conventions, therefore they must be noinline and noclone. * - * The asm() bodies of naked functions often depend on standard calling conventions, - * therefore they must be noinline and noclone. GCC 4.[56] currently fail to enforce - * this, so we must do so ourselves. See GCC PR44290. + * GCC 4.[56] currently fail to enforce this, so we must do so ourselves. + * See GCC PR44290. */ -#define __naked __attribute__((naked)) noinline __noclone notrace +#define __naked __attribute__((naked)) noinline __noclone notrace -#define __noreturn __attribute__((noreturn)) +#define __noreturn __attribute__((noreturn)) /* * From the GCC manual: @@ -95,34 +114,170 @@ * would be. * [...] */ -#ifndef __pure -#define __pure __attribute__((pure)) +#define __pure __attribute__((pure)) +#define __aligned(x) __attribute__((aligned(x))) +#define __printf(a, b) __attribute__((format(printf, a, b))) +#define __scanf(a, b) __attribute__((format(scanf, a, b))) +#define __attribute_const__ __attribute__((__const__)) +#define __maybe_unused __attribute__((unused)) +#define __always_unused __attribute__((unused)) + +/* gcc version specific checks */ + +#if GCC_VERSION < 30200 +# error Sorry, your compiler is too old - please upgrade it. +#endif + +#if GCC_VERSION < 30300 +# define __used __attribute__((__unused__)) +#else +# define __used __attribute__((__used__)) +#endif + +#ifdef CONFIG_GCOV_KERNEL +# if GCC_VERSION < 30400 +# error "GCOV profiling support for gcc versions below 3.4 not included" +# endif /* __GNUC_MINOR__ */ +#endif /* CONFIG_GCOV_KERNEL */ + +#if GCC_VERSION >= 30400 +#define __must_check __attribute__((warn_unused_result)) +#endif + +#if GCC_VERSION >= 40000 + +/* GCC 4.1.[01] miscompiles __weak */ +#ifdef __KERNEL__ +# if GCC_VERSION >= 40100 && GCC_VERSION <= 40101 +# error Your version of gcc miscompiles the __weak directive +# endif +#endif + +#define __used __attribute__((__used__)) +#define __compiler_offsetof(a, b) \ + __builtin_offsetof(a, b) + +#if GCC_VERSION >= 40100 && GCC_VERSION < 40600 +# define __compiletime_object_size(obj) __builtin_object_size(obj, 0) +#endif + +#if GCC_VERSION >= 40300 +/* Mark functions as cold. gcc will assume any path leading to a call + * to them will be unlikely. This means a lot of manual unlikely()s + * are unnecessary now for any paths leading to the usual suspects + * like BUG(), printk(), panic() etc. [but let's keep them for now for + * older compilers] + * + * Early snapshots of gcc 4.3 don't support this and we can't detect this + * in the preprocessor, but we can live with this because they're unreleased. + * Maketime probing would be overkill here. + * + * gcc also has a __attribute__((__hot__)) to move hot functions into + * a special section, but I don't see any sense in this right now in + * the kernel context + */ +#define __cold __attribute__((__cold__)) + +#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) + +#ifndef __CHECKER__ +# define __compiletime_warning(message) __attribute__((warning(message))) +# define __compiletime_error(message) __attribute__((error(message))) +#endif /* __CHECKER__ */ +#endif /* GCC_VERSION >= 40300 */ + +#if GCC_VERSION >= 40500 +/* + * Mark a position in code as unreachable. This can be used to + * suppress control flow warnings after asm blocks that transfer + * control elsewhere. + * + * Early snapshots of gcc 4.5 don't support this and we can't detect + * this in the preprocessor, but we can live with this because they're + * unreleased. Really, we need to have autoconf for the kernel. + */ +#define unreachable() __builtin_unreachable() + +/* Mark a function definition as prohibited from being cloned. */ +#define __noclone __attribute__((__noclone__)) + +#endif /* GCC_VERSION >= 40500 */ + +#if GCC_VERSION >= 40600 +/* + * When used with Link Time Optimization, gcc can optimize away C functions or + * variables which are referenced only from assembly code. __visible tells the + * optimizer that something else uses this function or variable, thus preventing + * this. + */ +#define __visible __attribute__((externally_visible)) #endif -#ifndef __aligned -#define __aligned(x) __attribute__((aligned(x))) + + +#if GCC_VERSION >= 40900 && !defined(__CHECKER__) +/* + * __assume_aligned(n, k): Tell the optimizer that the returned + * pointer can be assumed to be k modulo n. The second argument is + * optional (default 0), so we use a variadic macro to make the + * shorthand. + * + * Beware: Do not apply this to functions which may return + * ERR_PTRs. Also, it is probably unwise to apply it to functions + * returning extra information in the low bits (but in that case the + * compiler should see some alignment anyway, when the return value is + * massaged by 'flags = ptr & 3; ptr &= ~3;'). + */ +#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__))) #endif -#define __printf(a, b) __attribute__((format(printf, a, b))) -#define __scanf(a, b) __attribute__((format(scanf, a, b))) -#define noinline __attribute__((noinline)) -#define __attribute_const__ __attribute__((__const__)) -#define __maybe_unused __attribute__((unused)) -#define __always_unused __attribute__((unused)) -#define __gcc_header(x) #x -#define _gcc_header(x) __gcc_header(linux/compiler-gcc##x.h) -#define gcc_header(x) _gcc_header(x) -#include gcc_header(__GNUC__) +/* + * GCC 'asm goto' miscompiles certain code sequences: + * + * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670 + * + * Work it around via a compiler barrier quirk suggested by Jakub Jelinek. + * + * (asm goto is automatically volatile - the naming reflects this.) + */ +#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0) + +#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP +#if GCC_VERSION >= 40400 +#define __HAVE_BUILTIN_BSWAP32__ +#define __HAVE_BUILTIN_BSWAP64__ +#endif +#if GCC_VERSION >= 40800 || (defined(__powerpc__) && GCC_VERSION >= 40600) +#define __HAVE_BUILTIN_BSWAP16__ +#endif +#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */ + +#if GCC_VERSION >= 50000 +#define KASAN_ABI_VERSION 4 +#elif GCC_VERSION >= 40902 +#define KASAN_ABI_VERSION 3 +#endif + +#if GCC_VERSION >= 40902 +/* + * Tell the compiler that address safety instrumentation (KASAN) + * should not be applied to that function. + * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368 + */ +#define __no_sanitize_address __attribute__((no_sanitize_address)) +#endif + +#endif /* gcc version >= 40000 specific checks */ #if !defined(__noclone) #define __noclone /* not needed */ #endif +#if !defined(__no_sanitize_address) +#define __no_sanitize_address +#endif + /* * A trick to suppress uninitialized variable warning without generating any * code */ #define uninitialized_var(x) x = x - -#ifndef __always_inline -#define __always_inline inline __attribute__((always_inline)) -#endif diff --git a/include/linux/compiler-gcc3.h b/include/linux/compiler-gcc3.h deleted file mode 100644 index 7d89febe4d..0000000000 --- a/include/linux/compiler-gcc3.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __LINUX_COMPILER_H -#error "Please don't include <linux/compiler-gcc3.h> directly, include <linux/compiler.h> instead." -#endif - -#if GCC_VERSION < 30200 -# error Sorry, your compiler is too old - please upgrade it. -#endif - -#if GCC_VERSION >= 30300 -# define __used __attribute__((__used__)) -#else -# define __used __attribute__((__unused__)) -#endif - -#if GCC_VERSION >= 30400 -#define __must_check __attribute__((warn_unused_result)) -#endif - -#ifdef CONFIG_GCOV_KERNEL -# if GCC_VERSION < 30400 -# error "GCOV profiling support for gcc versions below 3.4 not included" -# endif /* __GNUC_MINOR__ */ -#endif /* CONFIG_GCOV_KERNEL */ diff --git a/include/linux/compiler-gcc4.h b/include/linux/compiler-gcc4.h deleted file mode 100644 index 2507fd2a1e..0000000000 --- a/include/linux/compiler-gcc4.h +++ /dev/null @@ -1,88 +0,0 @@ -#ifndef __LINUX_COMPILER_H -#error "Please don't include <linux/compiler-gcc4.h> directly, include <linux/compiler.h> instead." -#endif - -/* GCC 4.1.[01] miscompiles __weak */ -#ifdef __KERNEL__ -# if GCC_VERSION >= 40100 && GCC_VERSION <= 40101 -# error Your version of gcc miscompiles the __weak directive -# endif -#endif - -#define __used __attribute__((__used__)) -#define __must_check __attribute__((warn_unused_result)) -#define __compiler_offsetof(a,b) __builtin_offsetof(a,b) - -#if GCC_VERSION >= 40100 && GCC_VERSION < 40600 -# define __compiletime_object_size(obj) __builtin_object_size(obj, 0) -#endif - -#if GCC_VERSION >= 40300 -/* Mark functions as cold. gcc will assume any path leading to a call - to them will be unlikely. This means a lot of manual unlikely()s - are unnecessary now for any paths leading to the usual suspects - like BUG(), printk(), panic() etc. [but let's keep them for now for - older compilers] - - Early snapshots of gcc 4.3 don't support this and we can't detect this - in the preprocessor, but we can live with this because they're unreleased. - Maketime probing would be overkill here. - - gcc also has a __attribute__((__hot__)) to move hot functions into - a special section, but I don't see any sense in this right now in - the kernel context */ -#define __cold __attribute__((__cold__)) - -#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) - -#ifndef __CHECKER__ -# define __compiletime_warning(message) __attribute__((warning(message))) -# define __compiletime_error(message) __attribute__((error(message))) -#endif /* __CHECKER__ */ -#endif /* GCC_VERSION >= 40300 */ - -#if GCC_VERSION >= 40500 -/* - * Mark a position in code as unreachable. This can be used to - * suppress control flow warnings after asm blocks that transfer - * control elsewhere. - * - * Early snapshots of gcc 4.5 don't support this and we can't detect - * this in the preprocessor, but we can live with this because they're - * unreleased. Really, we need to have autoconf for the kernel. - */ -#define unreachable() __builtin_unreachable() - -/* Mark a function definition as prohibited from being cloned. */ -#define __noclone __attribute__((__noclone__)) - -#endif /* GCC_VERSION >= 40500 */ - -#if GCC_VERSION >= 40600 -/* - * Tell the optimizer that something else uses this function or variable. - */ -#define __visible __attribute__((externally_visible)) -#endif - -/* - * GCC 'asm goto' miscompiles certain code sequences: - * - * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670 - * - * Work it around via a compiler barrier quirk suggested by Jakub Jelinek. - * Fixed in GCC 4.8.2 and later versions. - * - * (asm goto is automatically volatile - the naming reflects this.) - */ -#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0) - -#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP -#if GCC_VERSION >= 40400 -#define __HAVE_BUILTIN_BSWAP32__ -#define __HAVE_BUILTIN_BSWAP64__ -#endif -#if GCC_VERSION >= 40800 || (defined(__powerpc__) && GCC_VERSION >= 40600) -#define __HAVE_BUILTIN_BSWAP16__ -#endif -#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */ diff --git a/include/linux/compiler-gcc5.h b/include/linux/compiler-gcc5.h deleted file mode 100644 index c8c5659525..0000000000 --- a/include/linux/compiler-gcc5.h +++ /dev/null @@ -1,65 +0,0 @@ -#ifndef __LINUX_COMPILER_H -#error "Please don't include <linux/compiler-gcc5.h> directly, include <linux/compiler.h> instead." -#endif - -#define __used __attribute__((__used__)) -#define __must_check __attribute__((warn_unused_result)) -#define __compiler_offsetof(a, b) __builtin_offsetof(a, b) - -/* Mark functions as cold. gcc will assume any path leading to a call - to them will be unlikely. This means a lot of manual unlikely()s - are unnecessary now for any paths leading to the usual suspects - like BUG(), printk(), panic() etc. [but let's keep them for now for - older compilers] - - Early snapshots of gcc 4.3 don't support this and we can't detect this - in the preprocessor, but we can live with this because they're unreleased. - Maketime probing would be overkill here. - - gcc also has a __attribute__((__hot__)) to move hot functions into - a special section, but I don't see any sense in this right now in - the kernel context */ -#define __cold __attribute__((__cold__)) - -#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) - -#ifndef __CHECKER__ -# define __compiletime_warning(message) __attribute__((warning(message))) -# define __compiletime_error(message) __attribute__((error(message))) -#endif /* __CHECKER__ */ - -/* - * Mark a position in code as unreachable. This can be used to - * suppress control flow warnings after asm blocks that transfer - * control elsewhere. - * - * Early snapshots of gcc 4.5 don't support this and we can't detect - * this in the preprocessor, but we can live with this because they're - * unreleased. Really, we need to have autoconf for the kernel. - */ -#define unreachable() __builtin_unreachable() - -/* Mark a function definition as prohibited from being cloned. */ -#define __noclone __attribute__((__noclone__)) - -/* - * Tell the optimizer that something else uses this function or variable. - */ -#define __visible __attribute__((externally_visible)) - -/* - * GCC 'asm goto' miscompiles certain code sequences: - * - * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670 - * - * Work it around via a compiler barrier quirk suggested by Jakub Jelinek. - * - * (asm goto is automatically volatile - the naming reflects this.) - */ -#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0) - -#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP -#define __HAVE_BUILTIN_BSWAP32__ -#define __HAVE_BUILTIN_BSWAP64__ -#define __HAVE_BUILTIN_BSWAP16__ -#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */ diff --git a/include/linux/compiler-intel.h b/include/linux/compiler-intel.h index ba147a1727..d4c71132d0 100644 --- a/include/linux/compiler-intel.h +++ b/include/linux/compiler-intel.h @@ -13,9 +13,14 @@ /* Intel ECC compiler doesn't support gcc specific asm stmts. * It uses intrinsics to do the equivalent things. */ +#undef barrier +#undef barrier_data #undef RELOC_HIDE #undef OPTIMIZER_HIDE_VAR +#define barrier() __memory_barrier() +#define barrier_data(ptr) barrier() + #define RELOC_HIDE(ptr, off) \ ({ unsigned long __ptr; \ __ptr = (unsigned long) (ptr); \ diff --git a/include/linux/compiler.h b/include/linux/compiler.h index d5ad7b1118..020ad16a04 100644 --- a/include/linux/compiler.h +++ b/include/linux/compiler.h @@ -17,6 +17,7 @@ # define __release(x) __context__(x,-1) # define __cond_lock(x,c) ((c) ? ({ __acquire(x); 1; }) : 0) # define __percpu __attribute__((noderef, address_space(3))) +# define __pmem __attribute__((noderef, address_space(5))) #ifdef CONFIG_SPARSE_RCU_POINTER # define __rcu __attribute__((noderef, address_space(4))) #else @@ -42,6 +43,7 @@ extern void __chk_io_ptr(const volatile void __iomem *); # define __cond_lock(x,c) (c) # define __percpu # define __rcu +# define __pmem #endif /* Indirect macros required for expanded argument pasting, eg. __LINE__. */ @@ -54,7 +56,11 @@ extern void __chk_io_ptr(const volatile void __iomem *); #include <linux/compiler-gcc.h> #endif +#if defined(CC_USING_HOTPATCH) && !defined(__CHECKER__) +#define notrace __attribute__((hotpatch(0,0))) +#else #define notrace __attribute__((no_instrument_function)) +#endif /* Intel compiler defines __GNUC__. So we will overwrite implementations * coming from above header files here @@ -138,7 +144,7 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); */ #define if(cond, ...) __trace_if( (cond , ## __VA_ARGS__) ) #define __trace_if(cond) \ - if (__builtin_constant_p((cond)) ? !!(cond) : \ + if (__builtin_constant_p(!!(cond)) ? !!(cond) : \ ({ \ int ______r; \ static struct ftrace_branch_data \ @@ -165,6 +171,10 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); # define barrier() __memory_barrier() #endif +#ifndef barrier_data +# define barrier_data(ptr) barrier() +#endif + /* Unreachable code */ #ifndef unreachable # define unreachable() do { } while (1) @@ -186,6 +196,126 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); # define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __LINE__) #endif +#include <linux/types.h> + +#define __READ_ONCE_SIZE \ +({ \ + switch (size) { \ + case 1: *(__u8 *)res = *(volatile __u8 *)p; break; \ + case 2: *(__u16 *)res = *(volatile __u16 *)p; break; \ + case 4: *(__u32 *)res = *(volatile __u32 *)p; break; \ + case 8: *(__u64 *)res = *(volatile __u64 *)p; break; \ + default: \ + barrier(); \ + __builtin_memcpy((void *)res, (const void *)p, size); \ + barrier(); \ + } \ +}) + +static __always_inline +void __read_once_size(const volatile void *p, void *res, int size) +{ + __READ_ONCE_SIZE; +} + +#ifdef CONFIG_KASAN +/* + * This function is not 'inline' because __no_sanitize_address confilcts + * with inlining. Attempt to inline it may cause a build failure. + * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368 + * '__maybe_unused' allows us to avoid defined-but-not-used warnings. + */ +static __no_sanitize_address __maybe_unused +void __read_once_size_nocheck(const volatile void *p, void *res, int size) +{ + __READ_ONCE_SIZE; +} +#else +static __always_inline +void __read_once_size_nocheck(const volatile void *p, void *res, int size) +{ + __READ_ONCE_SIZE; +} +#endif + +static __always_inline void __write_once_size(volatile void *p, void *res, int size) +{ + switch (size) { + case 1: *(volatile __u8 *)p = *(__u8 *)res; break; + case 2: *(volatile __u16 *)p = *(__u16 *)res; break; + case 4: *(volatile __u32 *)p = *(__u32 *)res; break; + case 8: *(volatile __u64 *)p = *(__u64 *)res; break; + default: + barrier(); + __builtin_memcpy((void *)p, (const void *)res, size); + barrier(); + } +} + +/* + * Prevent the compiler from merging or refetching reads or writes. The + * compiler is also forbidden from reordering successive instances of + * READ_ONCE, WRITE_ONCE and ACCESS_ONCE (see below), but only when the + * compiler is aware of some particular ordering. One way to make the + * compiler aware of ordering is to put the two invocations of READ_ONCE, + * WRITE_ONCE or ACCESS_ONCE() in different C statements. + * + * In contrast to ACCESS_ONCE these two macros will also work on aggregate + * data types like structs or unions. If the size of the accessed data + * type exceeds the word size of the machine (e.g., 32 bits or 64 bits) + * READ_ONCE() and WRITE_ONCE() will fall back to memcpy and print a + * compile-time warning. + * + * Their two major use cases are: (1) Mediating communication between + * process-level code and irq/NMI handlers, all running on the same CPU, + * and (2) Ensuring that the compiler does not fold, spindle, or otherwise + * mutilate accesses that either do not require ordering or that interact + * with an explicit memory barrier or atomic instruction that provides the + * required ordering. + */ + +#define __READ_ONCE(x, check) \ +({ \ + union { typeof(x) __val; char __c[1]; } __u; \ + if (check) \ + __read_once_size(&(x), __u.__c, sizeof(x)); \ + else \ + __read_once_size_nocheck(&(x), __u.__c, sizeof(x)); \ + __u.__val; \ +}) +#define READ_ONCE(x) __READ_ONCE(x, 1) + +/* + * Use READ_ONCE_NOCHECK() instead of READ_ONCE() if you need + * to hide memory access from KASAN. + */ +#define READ_ONCE_NOCHECK(x) __READ_ONCE(x, 0) + +#define WRITE_ONCE(x, val) \ +({ \ + union { typeof(x) __val; char __c[1]; } __u = \ + { .__val = (__force typeof(x)) (val) }; \ + __write_once_size(&(x), __u.__c, sizeof(x)); \ + __u.__val; \ +}) + +/** + * smp_cond_acquire() - Spin wait for cond with ACQUIRE ordering + * @cond: boolean expression to wait for + * + * Equivalent to using smp_load_acquire() on the condition variable but employs + * the control dependency of the wait to reduce the barrier on many platforms. + * + * The control dependency provides a LOAD->STORE order, the additional RMB + * provides LOAD->LOAD order, together they provide LOAD->{LOAD,STORE} order, + * aka. ACQUIRE. + */ +#define smp_cond_acquire(cond) do { \ + while (!(cond)) \ + cpu_relax(); \ + smp_rmb(); /* ctrl + rmb := acquire */ \ +} while (0) + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ @@ -304,6 +434,14 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); #define __visible #endif +/* + * Assume alignment of return value. + */ +#ifndef __assume_aligned +#define __assume_aligned(a, ...) +#endif + + /* Are two types/vars the same type (ignoring qualifiers)? */ #ifndef __same_type # define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b)) @@ -311,7 +449,7 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); /* Is this type a native word size -- useful for atomic operations */ #ifndef __native_word -# define __native_word(t) (sizeof(t) == sizeof(int) || sizeof(t) == sizeof(long)) +# define __native_word(t) (sizeof(t) == sizeof(char) || sizeof(t) == sizeof(short) || sizeof(t) == sizeof(int) || sizeof(t) == sizeof(long)) #endif /* Compile time object size, -1 for unknown */ @@ -373,12 +511,38 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); * to make the compiler aware of ordering is to put the two invocations of * ACCESS_ONCE() in different C statements. * - * This macro does absolutely -nothing- to prevent the CPU from reordering, - * merging, or refetching absolutely anything at any time. Its main intended - * use is to mediate communication between process-level code and irq/NMI - * handlers, all running on the same CPU. + * ACCESS_ONCE will only work on scalar types. For union types, ACCESS_ONCE + * on a union member will work as long as the size of the member matches the + * size of the union and the size is smaller than word size. + * + * The major use cases of ACCESS_ONCE used to be (1) Mediating communication + * between process-level code and irq/NMI handlers, all running on the same CPU, + * and (2) Ensuring that the compiler does not fold, spindle, or otherwise + * mutilate accesses that either do not require ordering or that interact + * with an explicit memory barrier or atomic instruction that provides the + * required ordering. + * + * If possible use READ_ONCE()/WRITE_ONCE() instead. + */ +#define __ACCESS_ONCE(x) ({ \ + __maybe_unused typeof(x) __var = (__force typeof(x)) 0; \ + (volatile typeof(x) *)&(x); }) +#define ACCESS_ONCE(x) (*__ACCESS_ONCE(x)) + +/** + * lockless_dereference() - safely load a pointer for later dereference + * @p: The pointer to load + * + * Similar to rcu_dereference(), but for situations where the pointed-to + * object's lifetime is managed by something other than RCU. That + * "something other" might be reference counting or simple immortality. */ -#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x)) +#define lockless_dereference(p) \ +({ \ + typeof(p) _________p1 = READ_ONCE(p); \ + smp_read_barrier_depends(); /* Dependency order vs. p above. */ \ + (_________p1); \ +}) /* Ignore/forbid kprobes attach on very low level functions marked by this attribute: */ #ifdef CONFIG_KPROBES diff --git a/include/ns16550.h b/include/ns16550.h index 5eeacd6ff9..4e620676c4 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -54,7 +54,6 @@ */ struct ns16550_platdata { unsigned long base; - int reg_offset; int reg_shift; int clock; }; |