diff options
86 files changed, 5809 insertions, 544 deletions
diff --git a/CHANGELOG b/CHANGELOG index c5b9d3fa60d..75ed9d3b918 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -10,6 +10,40 @@ Changes for U-Boot 1.1.4: Increase CFG_VIDEO_LOGO_MAX_SIZE on HH405 board. Patch by Stefan Roese, 07 Oct 2005 +* Add support for OF flat tree for the STXtc board. + Patch by Pantelis Antoniou, 04 Sep 2005 + +* Support passing of OF flat trees to the kernel. + Patch by Pantelis Antoniou, 04 Sep 2005 + +* Cleanup + +* Add support for NetSilicon NS7520 processor. + Patch by Art Shipkowski, 12 May 2005 + +* Add support for AP1000 board. + Patch by James MacAulay, 07 Oct 2005 + +* Eliminate hard-coded address of Ethernet transfer buffer on at91rm9200 + Patch by Anders Larsen, 07 Oct 2005 + + The Atmel errata #11 states that the transfer buffer descriptor + table must be aligned on a 16-word boundary. As it turned out, this + is insufficient - it seems the table must be aligned on a boundary + at least as large as the table itself (in Linux this is not an + issue - the table is aligned on a PAGE_SIZE (4096) boundary). + +* Fixed compilation for ARM when using a (standard) hard-FP toolchain + Patch by Anders Larsen, 07 Oct 2005 + +* Cleanup warnings for cpu/arm720t & cpu/arm1136 files. + sed the linker scripts, rather than pre-process them. + Patch by Peter Pearse, 07 Oct 2005 + +* Update make target for ARM supported boards. + Use lowlevel_init() instead of platformsetup() [rename]. + Patch by Peter Pearse, 06 Oct 2005 + * Fix booting from serial dataflash on AT91RM9200 Patch by Peter Menzebach, 29 Aug 2005 @@ -377,6 +377,10 @@ N: Robert Schwebel E: r.schwebel@pengutronix.de D: Support for csb226, logodl and innokom boards (PXA2xx) +N: Art Shipkowski +E: art@videon-central.com +D: Support for NetSilicon NS7520 + N: Yasushi Shoji E: yashi@atmark-techno.com D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board @@ -443,3 +447,8 @@ N: Alex Zuepke E: azu@sysgo.de D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM W: www.elinos.com + +N: James MacAulay +E: james.macaulay@amirix.com +D: Suppport for Amirix AP1000 +W: www.amirix.com diff --git a/MAINTAINERS b/MAINTAINERS index d251cd8e520..b889195b9f2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -249,11 +249,13 @@ Frank Panno <fpanno@delphintech.com> ep8260 MPC8260 Peter Pearse <peter.pearse@arm.com> - - Integrator/AP CM 926EJ-S, CM7x0T, CM9x0T - Integrator/CP CM 926EJ-S CM920T, CM940T, CM922T-XA10 - Versatile/AB ARM926EJ-S - Versatile/PB ARM926EJ-S + integratorcp All current ARM supplied & + supported core modules + - see http://www.arm.com + /products/DevTools + /Hardware_Platforms.html + versatile ARM926EJ-S + versatile ARM926EJ-S Denis Peter <d.peter@mpl.ch> @@ -61,18 +61,18 @@ LIST_8xx=" \ ######################################################################### LIST_4xx=" \ - ADCIOP AR405 ASH405 bubinga \ - CANBT CPCI2DP CPCI405 CPCI4052 \ - CPCI405AB CPCI440 CPCIISER4 CRAYL1 \ - csb272 csb472 DASA_SIM DP405 \ - DU405 ebony ERIC EXBITGEN \ - G2000 HUB405 JSE KAREF \ - METROBOX MIP405 MIP405T ML2 \ - ml300 ocotea OCRTC ORSG \ - PCI405 PIP405 PLU405 PMC405 \ - PPChameleonEVB sbc405 VOH405 W7OLMC \ - W7OLMG walnut WUH405 XPEDITE1K \ - yellowstone yosemite \ + ADCIOP AP1000 AR405 ASH405 \ + bubinga CANBT CPCI2DP CPCI405 \ + CPCI4052 CPCI405AB CPCI440 CPCIISER4 \ + CRAYL1 csb272 csb472 DASA_SIM \ + DP405 DU405 ebony ERIC \ + EXBITGEN G2000 HUB405 JSE \ + KAREF METROBOX MIP405 MIP405T \ + ML2 ml300 ocotea OCRTC \ + ORSG PCI405 PIP405 PLU405 \ + PMC405 PPChameleonEVB sbc405 VOH405 \ + W7OLMC W7OLMG walnut WUH405 \ + XPEDITE1K yellowstone yosemite \ " ######################################################################### @@ -162,7 +162,7 @@ LIST_SA="assabet dnp1110 gcplus lart shannon" LIST_ARM7=" \ armadillo B2 ep7312 evb4510 \ - impa7 integratorap_CM720T integratorap_CM7TDMI \ + impa7 integratorap ap7 ap720t \ modnet50 \ " @@ -171,32 +171,28 @@ LIST_ARM7=" \ ######################################################################### LIST_ARM9=" \ - at91rm9200dk cmc_pu2 csb637 \ - integratorap_CM920T integratorap_CM920T_ETM \ - integratorap_CM922T_XA10 integratorap_CM926EJ_S \ - integratorap_CM940T integratorap_CM946E_S \ - integratorap_CM966E_S integratorcp_CM920T \ - integratorcp_CM920T_ETM integratorcp_CM922T_XA10 \ - integratorcp_CM926EJ_S integratorcp_CM940T \ - integratorcp_CM946E_S integratorcp_CM966E_S \ - kb9202 lpd7a400 mp2usb mx1ads \ - mx1fs2 omap1510inn omap1610h2 omap1610inn \ - omap730p2 scb9328 smdk2400 smdk2410 \ - trab VCMA9 versatile voiceblue \ + at91rm9200dk cmc_pu2 \ + ap920t ap922_XA10 ap926ejs ap946es \ + ap966 cp920t cp922_XA10 cp926ejs \ + cp946es cp966 lpd7a400 mp2usb \ + mx1ads mx1fs2 omap1510inn omap1610h2 \ + omap1610inn omap730p2 scb9328 smdk2400 \ + smdk2410 trab VCMA9 versatile \ + versatileab versatilepb voiceblue " ######################################################################### ## ARM10 Systems ######################################################################### LIST_ARM10=" \ - integratorcp_CM10220E integratorcp_CM1026EJ_S \ + integratorcp cp1026 \ " ######################################################################### ## ARM11 Systems ######################################################################### LIST_ARM11=" \ - integratorcp_CM1136JF_S omap2420h4 \ + cp1136 omap2420h4 \ " ######################################################################### @@ -721,6 +721,9 @@ xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$( ADCIOP_config: unconfig @./mkconfig $(@:_config=) ppc ppc4xx adciop esd +AP1000_config:unconfig + @./mkconfig $(@:_config=) ppc ppc4xx ap1000 amirix + APC405_config: unconfig @./mkconfig $(@:_config=) ppc ppc4xx apc405 esd @@ -1396,178 +1399,32 @@ csb637_config : unconfig mp2usb_config : unconfig @./mkconfig $(@:_config=) arm arm920t mp2usb NULL at91rm9200 -######################################################################## -## ARM Integrator boards -## There are two variants /AP && /CP -## - many different core modules (CMs) can be used -## - some share characteristics -## Those without specific cpu support can still use U-Boot -## provided the ARM boot monitor (or similar) runs before U-Boot -## to set up the platform e.g. map writeable memory to 0x00000000 -## setup MMU, setup caches etc. -## Ported cores are:- -## ARM926EJ-S -## ARM946E-S -## -######################################################################## -xtract_int_board = $(subst _$(subst integrator$1_,,$(subst _config,,$2)),,$(subst _config,,$2)) -xtract_int_cm = $(subst integrator$1_,,$(subst _config,,$2)) -######################################################################### -## Integrator/AP -######################################################################### -integratorap_config : unconfig - @echo -n "/* Integrator configuration implied " > tmp.fil; \ - echo " by Makefile target */" >> tmp.fil; \ - echo >> tmp.fil - @echo -n "#define CONFIG_INTEGRATOR 1" >> tmp.fil; \ - echo " /* Integrator board */" >> tmp.fil; \ - echo -n "#define CONFIG_ARCH_INTEGRATOR" >> tmp.fil; \ - echo " 1 /* Integrator/AP */" >> tmp.fil; \ - echo "/* Core module not defined */" >> tmp.fil; \ - echo -n "#define CONFIG_ARM_INTCM 1" >> tmp.fil; \ - echo -n " /* Integrator core module " >> tmp.fil; \ - echo "with unknown core */" >> tmp.fil; \ - cpu=arm_intcm; \ - mv tmp.fil ./include/config.h; \ - ubootlds=board/integratorap/u-boot.lds; \ - sed -e 's/cpu\/.*\/st/cpu\/'$$cpu'\/st/' \ - $$ubootlds > $$ubootlds.tmp; \ - mv -f $$ubootlds.tmp $$ubootlds; \ - ./mkconfig -a integratorap arm arm_intcm integratorap; - -integratorap_CM720T_config integratorap_CM7TDMI_config \ -integratorap_CM920T_config integratorap_CM920T_ETM_config \ -integratorap_CM922T_XA10_config integratorap_CM926EJ_S_config \ -integratorap_CM940T_config integratorap_CM946E_S_config \ -integratorap_CM966E_S_config integratorap_CM10200E_config \ -integratorap_CM10220E_config integratorap_CM1026EJ_S_config \ -integratorap_CM1136JF_S_config : unconfig - @echo -n "/* Integrator configuration implied " > tmp.fil; \ - echo " by Makefile target */" >> tmp.fil; \ - echo >> tmp.fil - @echo -n "#define CONFIG_INTEGRATOR 1" >> tmp.fil; \ - echo " /* Integrator board */" >> tmp.fil; \ - echo -n "#define CONFIG_ARCH_INTEGRATOR" >> tmp.fil; \ - echo " 1 /* Integrator/AP */" >> tmp.fil; \ - cm=$(call xtract_int_cm,ap,$@); \ - echo -n "#define CONFIG_$$cm " >> tmp.fil; \ - echo " /* core module */" >> tmp.fil; \ - case $$cm in \ - CM920T) \ - echo -n "#define CONFIG_ARM920" >> tmp.fil; \ - echo -n "T 1 /* CPU" >> tmp.fil; \ - echo -n " core is ARM920T" >> tmp.fil; \ - echo " */" >> tmp.fil; \ - cpu=arm920t;; \ - CM926EJ_S) echo -n "#define CONFIG_ARM926" >> tmp.fil; \ - echo -n "EJ_S 1 /* CPU" >> tmp.fil; \ - echo -n " core is ARM926EJ-S" >> tmp.fil; \ - echo " */" >> tmp.fil; \ - cpu=arm926ejs;; \ - CM946E_S) echo -n "#define CONFIG_ARM946" >> tmp.fil; \ - echo -n "E_S 1 /* CPU" >> tmp.fil; \ - echo -n " core is ARM946E-S" >> tmp.fil; \ - echo " */" >> tmp.fil; \ - cpu=arm946es;; \ - *) echo -n "#define CONFIG_ARM_IN" >> tmp.fil; \ - echo -n "TCM 1 /* Int" >> tmp.fil; \ - echo -n "egrator core module w" >> tmp.fil; \ - echo -n "ith unported core" >> tmp.fil; \ - echo " */" >> tmp.fil; \ - cpu=arm_intcm;; \ - esac; \ - mv tmp.fil ./include/config.h; \ - ubootlds=board/$(call xtract_int_board,ap,$@)/u-boot.lds; \ - sed -e 's/cpu\/.*\/st/cpu\/'$$cpu'\/st/' \ - $$ubootlds > $$ubootlds.tmp; \ - mv -f $$ubootlds.tmp $$ubootlds; \ - ./mkconfig -a $(call xtract_int_board,ap,$@) arm $$cpu \ - $(call xtract_int_board,ap,$@); -######################################################################### -## Integrator/CP -######################################################################### -integratorcp_config : unconfig - @echo -n "/* Integrator configuration implied " > tmp.fil; \ - echo " by Makefile target */" >> tmp.fil; \ - echo >> tmp.fil - @echo -n "#define CONFIG_INTEGRATOR 1" >> tmp.fil; \ - echo " /* Integrator board */" >> tmp.fil; \ - echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> tmp.fil; \ - echo " 1 /* Integrator/CP */" >> tmp.fil; \ - echo "/* Core module not defined */" >> tmp.fil; \ - echo -n "#define CONFIG_ARM_INTCM 1" >> tmp.fil; \ - echo -n " /* Integrator core module " >> tmp.fil; \ - echo "with unknown core */" >> tmp.fil; \ - cpu=arm_intcm; \ - echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil; \ - echo -n " /* CM may not have " >> tmp.fil; \ - echo "multiple SSRAM mapping */" >> tmp.fil; \ - echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil; \ - echo -n " /* CM may not support SPD " >> tmp.fil; \ - echo "query */" >> tmp.fil; \ - echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil; \ - echo -n " /* CM may not support " >> tmp.fil; \ - echo "remapping */" >> tmp.fil; \ - echo -n "#undef CONFIG_CM_INIT " >> tmp.fil; \ - echo -n " /* CM may not have " >> tmp.fil; \ - echo "initialization reg */" >> tmp.fil; \ - echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil; \ - echo -n " /* CM may not have TCRAM */" >> tmp.fil; \ - mv tmp.fil ./include/config.h; \ - ubootlds=board/integratorcp/u-boot.lds; \ - sed -e 's/cpu\/.*\/st/cpu\/'$$cpu'\/st/' \ - $$ubootlds > $$ubootlds.tmp; \ - mv -f $$ubootlds.tmp $$ubootlds; \ - ./mkconfig -a integratorcp arm arm_intcm integratorcp; - -integratorcp_CM920T_config integratorcp_CM920T_ETM_config \ -integratorcp_CM922T_XA10_config integratorcp_CM926EJ_S_config \ -integratorcp_CM940T_config integratorcp_CM946E_S_config \ -integratorcp_CM966E_S_config integratorcp_CM10200E_config \ -integratorcp_CM10220E_config integratorcp_CM1026EJ_S_config \ -integratorcp_CM1136JF_S_config : unconfig - @echo -n "/* Integrator configuration implied " > tmp.fil; \ - echo " by Makefile target */" >> tmp.fil; \ - echo >> tmp.fil - @echo -n "#define CONFIG_INTEGRATOR 1" >> tmp.fil; \ - echo " /* Integrator board */" >> tmp.fil; \ - echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> tmp.fil; \ - echo " 1 /* Integrator/CP */" >> tmp.fil; \ - cm=$(call xtract_int_cm,cp,$@); \ - echo -n "#define CONFIG_$$cm " >> tmp.fil; \ - echo " /* core module */" >> tmp.fil; \ - echo "/* $$cm core module */" >> tmp.fil; \ - case $$cm in \ - CM920T) echo -n "#define CONFIG_ARM920" >> tmp.fil; \ - echo -n "T 1 /* CPU" >> tmp.fil; \ - echo -n " core is ARM920T" >> tmp.fil; \ - echo " */" >> tmp.fil; \ - cpu=arm920t;; \ - CM946E_S) echo -n "#define CONFIG_ARM946" >> tmp.fil; \ - echo -n "E_S 1 /* CPU" >> tmp.fil; \ - echo -n " core is ARM946E-S" >> tmp.fil; \ - echo " */" >> tmp.fil; \ - cpu=arm946es;; \ - CM926EJ_S) echo -n "#define CONFIG_ARM926" >> tmp.fil; \ - echo -n "EJ_S 1 /* CPU" >> tmp.fil; \ - echo -n " core is ARM926EJ-S" >> tmp.fil; \ - echo " */" >> tmp.fil; \ - cpu=arm926ejs;; \ - *) echo -n "#define CONFIG_ARM_IN" >> tmp.fil; \ - echo -n "TCM 1 /* Int" >> tmp.fil; \ - echo -n "egrator core module w" >> tmp.fil; \ - echo -n "ith unported core" >> tmp.fil; \ - echo " */" >> tmp.fil; \ - cpu=arm_intcm;; \ - esac; \ - mv tmp.fil ./include/config.h; \ - ubootlds=board/$(call xtract_int_board,cp,$@)/u-boot.lds; \ - sed -e 's/cpu\/.*\/st/cpu\/'$$cpu'\/st/' \ - $$ubootlds > $$ubootlds.tmp; \ - mv -f $$ubootlds.tmp $$ubootlds; \ - ./mkconfig -a $(call xtract_int_board,cp,$@) arm $$cpu \ - $(call xtract_int_board,cp,$@); +######################################################################## +## ARM Integrator boards - see doc/README-integrator for more info. +integratorap_config \ +ap_config \ +ap966_config \ +ap922_config \ +ap922_XA10_config \ +ap7_config \ +ap720t_config \ +ap920t_config \ +ap926ejs_config \ +ap946es_config: unconfig + @board/integratorap/split_by_variant.sh $@ + +integratorcp_config \ +cp_config \ +cp920t_config \ +cp926ejs_config \ +cp946es_config \ +cp1136_config \ +cp966_config \ +cp922_config \ +cp922_XA10_config \ +cp1026_config: unconfig + @board/integratorcp/split_by_variant.sh $@ kb9202_config : unconfig @./mkconfig $(@:_config=) arm arm920t kb9202 NULL at91rm9200 @@ -1660,8 +1517,13 @@ trab_old_config: unconfig VCMA9_config : unconfig @./mkconfig $(@:_config=) arm arm920t vcma9 mpl s3c24x0 -versatile_config : unconfig - @./mkconfig $(@:_config=) arm arm926ejs versatile +#======================================================================== +# ARM supplied Versatile development boards +#======================================================================== +versatile_config \ +versatileab_config \ +versatilepb_config : unconfig + @board/versatile/split_by_variant.sh $@ voiceblue_smallflash_config \ voiceblue_config: unconfig @@ -1736,6 +1598,9 @@ lubbock_config : unconfig logodl_config : unconfig @./mkconfig $(@:_config=) arm pxa logodl +pxa255_idp_config: unconfig + @./mkconfig $(@:_config=) arm pxa pxa255_idp + wepep250_config : unconfig @./mkconfig $(@:_config=) arm pxa wepep250 @@ -1946,6 +1811,7 @@ clean: rm -f tools/env/fw_printenv tools/env/fw_setenv rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image rm -f board/trab/trab_fkt board/voiceblue/eeprom + rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds clobber: clean find . -type f \( -name .depend \ @@ -261,43 +261,44 @@ The following options need to be configured: PowerPC based boards: --------------------- - CONFIG_ADCIOP CONFIG_GEN860T CONFIG_PCI405 - CONFIG_ADS860 CONFIG_GENIETV CONFIG_PCIPPC2 - CONFIG_AMX860 CONFIG_GTH CONFIG_PCIPPC6 - CONFIG_AR405 CONFIG_gw8260 CONFIG_pcu_e - CONFIG_BAB7xx CONFIG_hermes CONFIG_PIP405 - CONFIG_c2mon CONFIG_hymod CONFIG_PM826 - CONFIG_CANBT CONFIG_IAD210 CONFIG_ppmc8260 - CONFIG_CCM CONFIG_ICU862 CONFIG_QS823 - CONFIG_CMI CONFIG_IP860 CONFIG_QS850 - CONFIG_cogent_mpc8260 CONFIG_IPHASE4539 CONFIG_QS860T - CONFIG_cogent_mpc8xx CONFIG_IVML24 CONFIG_RBC823 - CONFIG_CPCI405 CONFIG_IVML24_128 CONFIG_RPXClassic - CONFIG_CPCI4052 CONFIG_IVML24_256 CONFIG_RPXlite - CONFIG_CPCIISER4 CONFIG_IVMS8 CONFIG_RPXsuper - CONFIG_CPU86 CONFIG_IVMS8_128 CONFIG_rsdproto - CONFIG_CRAYL1 CONFIG_IVMS8_256 CONFIG_sacsng - CONFIG_CSB272 CONFIG_JSE CONFIG_Sandpoint8240 - CONFIG_CU824 CONFIG_LANTEC CONFIG_Sandpoint8245 - CONFIG_DASA_SIM CONFIG_lwmon CONFIG_sbc8260 - CONFIG_DB64360 CONFIG_MBX CONFIG_sbc8560 - CONFIG_DB64460 CONFIG_MBX860T CONFIG_SM850 - CONFIG_DU405 CONFIG_MHPC CONFIG_SPD823TS - CONFIG_DUET_ADS CONFIG_MIP405 CONFIG_STXGP3 - CONFIG_EBONY CONFIG_MOUSSE CONFIG_SXNI855T - CONFIG_ELPPC CONFIG_MPC8260ADS CONFIG_TQM823L - CONFIG_ELPT860 CONFIG_MPC8540ADS CONFIG_TQM8260 - CONFIG_ep8260 CONFIG_MPC8540EVAL CONFIG_TQM850L - CONFIG_ERIC CONFIG_MPC8560ADS CONFIG_TQM855L - CONFIG_ESTEEM192E CONFIG_MUSENKI CONFIG_TQM860L - CONFIG_ETX094 CONFIG_MVS1 CONFIG_TTTech - CONFIG_EVB64260 CONFIG_NETPHONE CONFIG_UTX8245 - CONFIG_FADS823 CONFIG_NETTA CONFIG_V37 - CONFIG_FADS850SAR CONFIG_NETVIA CONFIG_W7OLMC - CONFIG_FADS860T CONFIG_NX823 CONFIG_W7OLMG - CONFIG_FLAGADM CONFIG_OCRTC CONFIG_WALNUT - CONFIG_FPS850L CONFIG_ORSG CONFIG_ZPC1900 - CONFIG_FPS860L CONFIG_OXC CONFIG_ZUMA + CONFIG_ADCIOP CONFIG_GEN860T CONFIG_PCIPPC2 + CONFIG_ADS860 CONFIG_GENIETV CONFIG_PCIPPC6 + CONFIG_AMX860 CONFIG_GTH CONFIG_pcu_e + CONFIG_AP1000 CONFIG_gw8260 CONFIG_PIP405 + CONFIG_AR405 CONFIG_hermes CONFIG_PM826 + CONFIG_BAB7xx CONFIG_hymod CONFIG_ppmc8260 + CONFIG_c2mon CONFIG_IAD210 CONFIG_QS823 + CONFIG_CANBT CONFIG_ICU862 CONFIG_QS850 + CONFIG_CCM CONFIG_IP860 CONFIG_QS860T + CONFIG_CMI CONFIG_IPHASE4539 CONFIG_RBC823 + CONFIG_cogent_mpc8260 CONFIG_IVML24 CONFIG_RPXClassic + CONFIG_cogent_mpc8xx CONFIG_IVML24_128 CONFIG_RPXlite + CONFIG_CPCI405 CONFIG_IVML24_256 CONFIG_RPXsuper + CONFIG_CPCI4052 CONFIG_IVMS8 CONFIG_rsdproto + CONFIG_CPCIISER4 CONFIG_IVMS8_128 CONFIG_sacsng + CONFIG_CPU86 CONFIG_IVMS8_256 CONFIG_Sandpoint8240 + CONFIG_CRAYL1 CONFIG_JSE CONFIG_Sandpoint8245 + CONFIG_CSB272 CONFIG_LANTEC CONFIG_sbc8260 + CONFIG_CU824 CONFIG_lwmon CONFIG_sbc8560 + CONFIG_DASA_SIM CONFIG_MBX CONFIG_SM850 + CONFIG_DB64360 CONFIG_MBX860T CONFIG_SPD823TS + CONFIG_DB64460 CONFIG_MHPC CONFIG_STXGP3 + CONFIG_DU405 CONFIG_MIP405 CONFIG_SXNI855T + CONFIG_DUET_ADS CONFIG_MOUSSE CONFIG_TQM823L + CONFIG_EBONY CONFIG_MPC8260ADS CONFIG_TQM8260 + CONFIG_ELPPC CONFIG_MPC8540ADS CONFIG_TQM850L + CONFIG_ELPT860 CONFIG_MPC8540EVAL CONFIG_TQM855L + CONFIG_ep8260 CONFIG_MPC8560ADS CONFIG_TQM860L + CONFIG_ERIC CONFIG_MUSENKI CONFIG_TTTech + CONFIG_ESTEEM192E CONFIG_MVS1 CONFIG_UTX8245 + CONFIG_ETX094 CONFIG_NETPHONE CONFIG_V37 + CONFIG_EVB64260 CONFIG_NETTA CONFIG_W7OLMC + CONFIG_FADS823 CONFIG_NETVIA CONFIG_W7OLMG + CONFIG_FADS850SAR CONFIG_NX823 CONFIG_WALNUT + CONFIG_FADS860T CONFIG_OCRTC CONFIG_ZPC1900 + CONFIG_FLAGADM CONFIG_ORSG CONFIG_ZUMA + CONFIG_FPS850L CONFIG_OXC + CONFIG_FPS860L CONFIG_PCI405 ARM based boards: ----------------- @@ -398,6 +399,20 @@ The following options need to be configured: expect it to be in bytes, others in MB. Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes. + CONFIG_OF_FLAT_TREE + + New kernel versions are expecting firmware settings to be + passed using flat open firmware trees. + The environment variable "disable_of", when set, disables this + functionality. + + CONFIG_OF_FLAT_TREE_MAX_SIZE + + The maximum size of the constructed OF tree. + + OF_CPU - The proper name of the cpus node. + OF_TBCLK - The timebase frequency. + - Serial Ports: CFG_PL010_SERIAL diff --git a/board/amirix/ap1000/Makefile b/board/amirix/ap1000/Makefile new file mode 100644 index 00000000000..4e1ef217cad --- /dev/null +++ b/board/amirix/ap1000/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o serial.o pci.o powerspan.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c new file mode 100644 index 00000000000..dd836ce221d --- /dev/null +++ b/board/amirix/ap1000/ap1000.c @@ -0,0 +1,699 @@ +/* + * amirix.c: ppcboot platform support for AMIRIX board + * + * Copyright 2002 Mind NV + * Copyright 2003 AMIRIX Systems Inc. + * + * http://www.mind.be/ + * http://www.amirix.com/ + * + * Author : Peter De Schrijver (p2@mind.be) + * Frank Smith (smith@amirix.com) + * + * Derived from : Other platform support files in this tree, ml2 + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL) version 2, incorporated herein by + * reference. Drivers based on or derived from this code fall under the GPL + * and must retain the authorship, copyright and this license notice. This + * file is not a complete program and may only be used when the entire + * program is licensed under the GPL. + * + */ + +#include <common.h> +#include <command.h> +#include <asm/processor.h> + +#include "powerspan.h" +#include "ap1000.h" + +int board_pre_init (void) +{ + return 0; +} + +/** serial number and platform display at startup */ +int checkboard (void) +{ + unsigned char *s = getenv ("serial#"); + unsigned char *e; + + /* After a loadace command, the SystemAce control register is left in a wonky state. */ + /* this code did not work in board_pre_init */ + unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE; + + p[SYSACE_CTRLREG0] = 0x0; + + /* add platform and device to banner */ + switch (get_device ()) { + case AP1xx_AP107_TARGET: + puts (AP1xx_AP107_TARGET_STR); + break; + case AP1xx_AP120_TARGET: + puts (AP1xx_AP120_TARGET_STR); + break; + case AP1xx_AP130_TARGET: + puts (AP1xx_AP130_TARGET_STR); + break; + case AP1xx_AP1070_TARGET: + puts (AP1xx_AP1070_TARGET_STR); + break; + case AP1xx_AP1100_TARGET: + puts (AP1xx_AP1100_TARGET_STR); + break; + default: + puts (AP1xx_UNKNOWN_STR); + break; + } + puts (AP1xx_TARGET_STR); + puts (" with "); + + switch (get_platform ()) { + case AP100_BASELINE_PLATFORM: + case AP1000_BASELINE_PLATFORM: + puts (AP1xx_BASELINE_PLATFORM_STR); + break; + case AP1xx_QUADGE_PLATFORM: + puts (AP1xx_QUADGE_PLATFORM_STR); + break; + case AP1xx_MGT_REF_PLATFORM: + puts (AP1xx_MGT_REF_PLATFORM_STR); + break; + case AP1xx_STANDARD_PLATFORM: + puts (AP1xx_STANDARD_PLATFORM_STR); + break; + case AP1xx_DUAL_PLATFORM: + puts (AP1xx_DUAL_PLATFORM_STR); + break; + case AP1xx_BASE_SRAM_PLATFORM: + puts (AP1xx_BASE_SRAM_PLATFORM_STR); + break; + case AP1xx_PCI_PCB_TESTPLATFORM: + case AP1000_PCI_PCB_TESTPLATFORM: + puts (AP1xx_PCI_PCB_TESTPLATFORM_STR); + break; + case AP1xx_DUAL_GE_MEZZ_TESTPLATFORM: + puts (AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR); + break; + case AP1xx_SFP_MEZZ_TESTPLATFORM: + puts (AP1xx_SFP_MEZZ_TESTPLATFORM_STR); + break; + default: + puts (AP1xx_UNKNOWN_STR); + break; + } + + if ((get_platform () & AP1xx_TESTPLATFORM_MASK) != 0) { + puts (AP1xx_TESTPLATFORM_STR); + } else { + puts (AP1xx_PLATFORM_STR); + } + + putc ('\n'); + + puts ("Serial#: "); + + if (!s) { + printf ("### No HW ID - assuming AMIRIX"); + } else { + for (e = s; *e; ++e) { + if (*e == ' ') + break; + } + + for (; s < e; ++s) { + putc (*s); + } + } + + putc ('\n'); + + return (0); +} + + +long int initdram (int board_type) +{ + unsigned char *s = getenv ("dramsize"); + + if (s != NULL) { + if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) { + s += 2; + } + return simple_strtoul (s, NULL, 16); + } else { + /* give all 64 MB */ + return 64 * 1024 * 1024; + } +} + +unsigned int get_platform (void) +{ + unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR; + + return (*revision_reg_ptr & AP1xx_PLATFORM_MASK); +} + +unsigned int get_device (void) +{ + unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR; + + return (*revision_reg_ptr & AP1xx_TARGET_MASK); +} + +#if 0 /* loadace is not working; it appears to be a hardware issue with the system ace. */ +/* + This function loads FPGA configurations from the SystemACE CompactFlash +*/ +int do_loadace (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE; + int cfg; + + if ((p[SYSACE_STATREG0] & 0x10) == 0) { + p[SYSACE_CTRLREG0] = 0x80; + printf ("\nNo CompactFlash Detected\n\n"); + p[SYSACE_CTRLREG0] = 0x00; + return 1; + } + + /* reset configuration controller: | 0x80 */ + /* select cpflash & ~0x40 */ + /* cfg start | 0x20 */ + /* wait for cfgstart & ~0x10 */ + /* force cfgmode: | 0x08 */ + /* do no force cfgaddr: & ~0x04 */ + /* clear mpulock: & ~0x02 */ + /* do not force lock request & ~0x01 */ + + p[SYSACE_CTRLREG0] = 0x80 | 0x20 | 0x08; + p[SYSACE_CTRLREG1] = 0x00; + + /* force config address if arg2 exists */ + if (argc == 2) { + cfg = simple_strtoul (argv[1], NULL, 10); + + if (cfg > 7) { + printf ("\nInvalid Configuration\n\n"); + p[SYSACE_CTRLREG0] = 0x00; + return 1; + } + /* Set config address */ + p[SYSACE_CTRLREG1] = (cfg << 5); + /* force cfgaddr */ + p[SYSACE_CTRLREG0] |= 0x04; + + } else { + cfg = (p[SYSACE_STATREG1] & 0xE0) >> 5; + } + + /* release configuration controller */ + printf ("\nLoading V2PRO with config %d...\n", cfg); + p[SYSACE_CTRLREG0] &= ~0x80; + + + while ((p[SYSACE_STATREG1] & 0x01) == 0) { + + if (p[SYSACE_ERRREG0] & 0x80) { + /* attempting to load an invalid configuration makes the cpflash */ + /* appear to be removed. Reset here to avoid that problem */ + p[SYSACE_CTRLREG0] = 0x80; + printf ("\nConfiguration %d Read Error\n\n", cfg); + p[SYSACE_CTRLREG0] = 0x00; + return 1; + } + } + + p[SYSACE_CTRLREG0] |= 0x20; + + return 0; +} +#endif + +/** Console command to display and set the software reconfigure byte + * <pre> + * swconfig - display the current value of the software reconfigure byte + * swconfig [#] - change the software reconfigure byte to # + * </pre> + * @param *cmdtp [IN] as passed by run_command (ignored) + * @param flag [IN] as passed by run_command (ignored) + * @param argc [IN] as passed by run_command if 1, display, if 2 change + * @param *argv[] [IN] contains the parameters to use + * @return + * <pre> + * 0 if passed + * -1 if failed + * </pre> + */ +int do_swconfigbyte (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + unsigned char *sector_buffer = NULL; + unsigned char input_char; + int write_result; + unsigned int input_uint; + + /* display value if no argument */ + if (argc < 2) { + printf ("Software configuration byte is currently: 0x%02x\n", + *((unsigned char *) (SW_BYTE_SECTOR_ADDR + + SW_BYTE_SECTOR_OFFSET))); + return 0; + } else if (argc > 3) { + printf ("Too many arguments\n"); + return -1; + } + + /* if 3 arguments, 3rd argument is the address to use */ + if (argc == 3) { + input_uint = simple_strtoul (argv[1], NULL, 16); + sector_buffer = (unsigned char *) input_uint; + } else { + sector_buffer = (unsigned char *) DEFAULT_TEMP_ADDR; + } + + input_char = simple_strtoul (argv[1], NULL, 0); + if ((input_char & ~SW_BYTE_MASK) != 0) { + printf ("Input of 0x%02x will be masked to 0x%02x\n", + input_char, (input_char & SW_BYTE_MASK)); + input_char = input_char & SW_BYTE_MASK; + } + + memcpy (sector_buffer, (void *) SW_BYTE_SECTOR_ADDR, + SW_BYTE_SECTOR_SIZE); + sector_buffer[SW_BYTE_SECTOR_OFFSET] = input_char; + + + printf ("Erasing Flash..."); + if (flash_sect_erase + (SW_BYTE_SECTOR_ADDR, + (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET))) { + return -1; + } + + printf ("Writing to Flash... "); + write_result = + flash_write (sector_buffer, SW_BYTE_SECTOR_ADDR, + SW_BYTE_SECTOR_SIZE); + if (write_result != 0) { + flash_perror (write_result); + return -1; + } else { + printf ("done\n"); + printf ("Software configuration byte is now: 0x%02x\n", + *((unsigned char *) (SW_BYTE_SECTOR_ADDR + + SW_BYTE_SECTOR_OFFSET))); + } + + return 0; +} + +#define ONE_SECOND 1000000 + +int do_pause (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int pause_time; + unsigned int delay_time; + int break_loop = 0; + + /* display value if no argument */ + if (argc < 2) { + pause_time = 1; + } + + else if (argc > 2) { + printf ("Too many arguments\n"); + return -1; + } else { + pause_time = simple_strtoul (argv[1], NULL, 0); + } + + printf ("Pausing with a poll time of %d, press any key to reactivate\n", pause_time); + delay_time = pause_time * ONE_SECOND; + while (break_loop == 0) { + udelay (delay_time); + if (serial_tstc () != 0) { + break_loop = 1; + /* eat user key presses */ + while (serial_tstc () != 0) { + serial_getc (); + } + } + } + + return 0; +} + +int do_swreconfig (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + printf ("Triggering software reconfigure (software config byte is 0x%02x)...\n", + *((unsigned char *) (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET))); + udelay (1000); + *((unsigned char *) AP1000_CPLD_BASE) = 1; + + return 0; +} + +#define GET_DECIMAL(low_byte) ((low_byte >> 5) * 125) +#define TEMP_BUSY_BIT 0x80 +#define TEMP_LHIGH_BIT 0x40 +#define TEMP_LLOW_BIT 0x20 +#define TEMP_EHIGH_BIT 0x10 +#define TEMP_ELOW_BIT 0x08 +#define TEMP_OPEN_BIT 0x04 +#define TEMP_ETHERM_BIT 0x02 +#define TEMP_LTHERM_BIT 0x01 + +int do_temp_sensor (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char cmd; + int ret_val = 0; + unsigned char temp_byte; + int temp; + int temp_low; + int low; + int low_low; + int high; + int high_low; + int therm; + unsigned char user_data[4] = { 0 }; + int user_data_count = 0; + int ii; + + if (argc > 1) { + cmd = argv[1][0]; + } else { + cmd = 's'; /* default to status */ + } + + user_data_count = argc - 2; + for (ii = 0; ii < user_data_count; ii++) { + user_data[ii] = simple_strtoul (argv[2 + ii], NULL, 0); + } + switch (cmd) { + case 's': + if (I2CAccess + (0x2, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + printf ("Status : 0x%02x ", temp_byte); + if (temp_byte & TEMP_BUSY_BIT) + printf ("BUSY "); + + if (temp_byte & TEMP_LHIGH_BIT) + printf ("LHIGH "); + + if (temp_byte & TEMP_LLOW_BIT) + printf ("LLOW "); + + if (temp_byte & TEMP_EHIGH_BIT) + printf ("EHIGH "); + + if (temp_byte & TEMP_ELOW_BIT) + printf ("ELOW "); + + if (temp_byte & TEMP_OPEN_BIT) + printf ("OPEN "); + + if (temp_byte & TEMP_ETHERM_BIT) + printf ("ETHERM "); + + if (temp_byte & TEMP_LTHERM_BIT) + printf ("LTHERM"); + + printf ("\n"); + + if (I2CAccess + (0x3, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + printf ("Config : 0x%02x ", temp_byte); + + if (I2CAccess + (0x4, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + printf ("\n"); + goto fail; + } + printf ("Conversion: 0x%02x\n", temp_byte); + if (I2CAccess + (0x22, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + printf ("Cons Alert: 0x%02x ", temp_byte); + + if (I2CAccess + (0x21, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + printf ("\n"); + goto fail; + } + printf ("Therm Hyst: %d\n", temp_byte); + + if (I2CAccess + (0x0, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + temp = temp_byte; + if (I2CAccess + (0x6, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + low = temp_byte; + if (I2CAccess + (0x5, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + high = temp_byte; + if (I2CAccess + (0x20, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + therm = temp_byte; + printf ("Local Temp: %2d Low: %2d High: %2d THERM: %2d\n", temp, low, high, therm); + + if (I2CAccess + (0x1, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + temp = temp_byte; + if (I2CAccess + (0x10, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + temp_low = temp_byte; + if (I2CAccess + (0x8, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + low = temp_byte; + if (I2CAccess + (0x14, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + low_low = temp_byte; + if (I2CAccess + (0x7, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + high = temp_byte; + if (I2CAccess + (0x13, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + high_low = temp_byte; + if (I2CAccess + (0x19, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + therm = temp_byte; + if (I2CAccess + (0x11, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + printf ("Ext Temp : %2d.%03d Low: %2d.%03d High: %2d.%03d THERM: %2d Offset: %2d\n", temp, GET_DECIMAL (temp_low), low, GET_DECIMAL (low_low), high, GET_DECIMAL (high_low), therm, temp_byte); + break; + case 'l': /* alter local limits : low, high, therm */ + if (argc < 3) { + goto usage; + } + + /* low */ + if (I2CAccess + (0xC, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &user_data[0], I2C_WRITE) != 0) { + goto fail; + } + + if (user_data_count > 1) { + /* high */ + if (I2CAccess + (0xB, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &user_data[1], I2C_WRITE) != 0) { + goto fail; + } + } + + if (user_data_count > 2) { + /* therm */ + if (I2CAccess + (0x20, I2C_SENSOR_DEV, + I2C_SENSOR_CHIP_SEL, &user_data[2], + I2C_WRITE) != 0) { + goto fail; + } + } + break; + case 'e': /* alter external limits: low, high, therm, offset */ + if (argc < 3) { + goto usage; + } + + /* low */ + if (I2CAccess + (0xE, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &user_data[0], I2C_WRITE) != 0) { + goto fail; + } + + if (user_data_count > 1) { + /* high */ + if (I2CAccess + (0xD, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &user_data[1], I2C_WRITE) != 0) { + goto fail; + } + } + + if (user_data_count > 2) { + /* therm */ + if (I2CAccess + (0x19, I2C_SENSOR_DEV, + I2C_SENSOR_CHIP_SEL, &user_data[2], + I2C_WRITE) != 0) { + goto fail; + } + } + + if (user_data_count > 3) { + /* offset */ + if (I2CAccess + (0x11, I2C_SENSOR_DEV, + I2C_SENSOR_CHIP_SEL, &user_data[3], + I2C_WRITE) != 0) { + goto fail; + } + } + break; + case 'c': /* alter config settings: config, conv, cons alert, therm hyst */ + if (argc < 3) { + goto usage; + } + + /* config */ + if (I2CAccess + (0x9, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &user_data[0], I2C_WRITE) != 0) { + goto fail; + } + + if (user_data_count > 1) { + /* conversion */ + if (I2CAccess + (0xA, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &user_data[1], I2C_WRITE) != 0) { + goto fail; + } + } + + if (user_data_count > 2) { + /* cons alert */ + if (I2CAccess + (0x22, I2C_SENSOR_DEV, + I2C_SENSOR_CHIP_SEL, &user_data[2], + I2C_WRITE) != 0) { + goto fail; + } + } + + if (user_data_count > 3) { + /* therm hyst */ + if (I2CAccess + (0x21, I2C_SENSOR_DEV, + I2C_SENSOR_CHIP_SEL, &user_data[3], + I2C_WRITE) != 0) { + goto fail; + } + } + break; + default: + goto usage; + } + + goto done; +fail: + printf ("Access to sensor failed\n"); + ret_val = -1; + goto done; +usage: + printf ("Usage:\n%s\n", cmdtp->help); + +done: + return ret_val; +} + +U_BOOT_CMD (temp, 6, 0, do_temp_sensor, + "temp - interact with the temperature sensor\n", + "temp [s]\n" + " - Show status.\n" + "temp l LOW [HIGH] [THERM]\n" + " - Set local limits.\n" + "temp e LOW [HIGH] [THERM] [OFFSET]\n" + " - Set external limits.\n" + "temp c CONFIG [CONVERSION] [CONS. ALERT] [THERM HYST]\n" + " - Set config options.\n" + "\n" + "All values can be decimal or hex (hex preceded with 0x).\n" + "Only whole numbers are supported for external limits.\n"); + +#if 0 +U_BOOT_CMD (loadace, 2, 0, do_loadace, + "loadace - load fpga configuration from System ACE compact flash\n", + "N\n" + " - Load configuration N (0-7) from System ACE compact flash\n" + "loadace\n" " - loads default configuration\n"); +#endif + +U_BOOT_CMD (swconfig, 2, 0, do_swconfigbyte, + "swconfig- display or modify the software configuration byte\n", + "N [ADDRESS]\n" + " - set software configuration byte to N, optionally use ADDRESS as\n" + " location of buffer for flash copy\n" + "swconfig\n" " - display software configuration byte\n"); + +U_BOOT_CMD (pause, 2, 0, do_pause, + "pause - sleep processor until any key is pressed with poll time of N seconds\n", + "N\n" + " - sleep processor until any key is pressed with poll time of N seconds\n" + "pause\n" + " - sleep processor until any key is pressed with poll time of 1 second\n"); + +U_BOOT_CMD (swrecon, 1, 0, do_swreconfig, + "swrecon - trigger a board reconfigure to the software selected configuration\n", + "\n" + " - trigger a board reconfigure to the software selected configuration\n"); diff --git a/board/amirix/ap1000/ap1000.h b/board/amirix/ap1000/ap1000.h new file mode 100644 index 00000000000..118c4d1b9a6 --- /dev/null +++ b/board/amirix/ap1000/ap1000.h @@ -0,0 +1,173 @@ +/* + * ap1000.h: AP1000 (e.g. AP1070, AP1100) board specific definitions and functions that are needed globally + * + * Author : James MacAulay + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL) version 2, incorporated herein by + * reference. Drivers based on or derived from this code fall under the GPL + * and must retain the authorship, copyright and this license notice. This + * file is not a complete program and may only be used when the entire + * program is licensed under the GPL. + * + */ + +#ifndef __AP1000_H +#define __AP1000_H + +/* + * Revision Register stuff + */ +#define AP1xx_FPGA_REV_ADDR 0x29000000 + +#define AP1xx_PLATFORM_MASK 0xFF000000 +#define AP100_BASELINE_PLATFORM 0x01000000 +#define AP1xx_QUADGE_PLATFORM 0x02000000 +#define AP1xx_MGT_REF_PLATFORM 0x03000000 +#define AP1xx_STANDARD_PLATFORM 0x04000000 +#define AP1xx_DUAL_PLATFORM 0x05000000 +#define AP1xx_BASE_SRAM_PLATFORM 0x06000000 + +#define AP1000_BASELINE_PLATFORM 0x21000000 + +#define AP1xx_TESTPLATFORM_MASK 0xC0000000 +#define AP1xx_PCI_PCB_TESTPLATFORM 0xC0000000 +#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM 0xC1000000 +#define AP1xx_SFP_MEZZ_TESTPLATFORM 0xC2000000 + +#define AP1000_PCI_PCB_TESTPLATFORM 0xC3000000 + +#define AP1xx_TARGET_MASK 0x00FF0000 +#define AP1xx_AP107_TARGET 0x00010000 +#define AP1xx_AP120_TARGET 0x00020000 +#define AP1xx_AP130_TARGET 0x00030000 +#define AP1xx_AP1070_TARGET 0x00040000 +#define AP1xx_AP1100_TARGET 0x00050000 + +#define AP1xx_UNKNOWN_STR "Unknown" + +#define AP1xx_PLATFORM_STR " Platform" +#define AP1xx_BASELINE_PLATFORM_STR "Baseline" +#define AP1xx_QUADGE_PLATFORM_STR "Quad GE" +#define AP1xx_MGT_REF_PLATFORM_STR "MGT Reference" +#define AP1xx_STANDARD_PLATFORM_STR "Standard" +#define AP1xx_DUAL_PLATFORM_STR "Dual" +#define AP1xx_BASE_SRAM_PLATFORM_STR "Baseline with SRAM" + +#define AP1xx_TESTPLATFORM_STR " Test Platform" +#define AP1xx_PCI_PCB_TESTPLATFORM_STR "Base" +#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR "Dual GE Mezzanine" +#define AP1xx_SFP_MEZZ_TESTPLATFORM_STR "SFP Mezzanine" + +#define AP1xx_TARGET_STR " Board" +#define AP1xx_AP107_TARGET_STR "AP107" +#define AP1xx_AP120_TARGET_STR "AP120" +#define AP1xx_AP130_TARGET_STR "AP130" + +#define AP1xx_AP1070_TARGET_STR "AP1070" +#define AP1xx_AP1100_TARGET_STR "AP1100" + +/* + * Flash Stuff + */ +#define AP1xx_PROGRAM_FLASH_INDEX 0 +#define AP1xx_CONFIG_FLASH_INDEX 1 + +/* + * System Ace Stuff + */ +#define AP1000_SYSACE_REGBASE 0x28000000 + +#define SYSACE_STATREG0 0x04 /* 7:0 */ +#define SYSACE_STATREG1 0x05 /* 15:8 */ +#define SYSACE_STATREG2 0x06 /* 23:16 */ +#define SYSACE_STATREG3 0x07 /* 31:24 */ + +#define SYSACE_ERRREG0 0x08 /* 7:0 */ +#define SYSACE_ERRREG1 0x09 /* 15:8 */ +#define SYSACE_ERRREG2 0x0a /* 23:16 */ +#define SYSACE_ERRREG3 0x0b /* 31:24 */ + +#define SYSACE_CTRLREG0 0x18 /* 7:0 */ +#define SYSACE_CTRLREG1 0x19 /* 15:8 */ +#define SYSACE_CTRLREG2 0x1A /* 23:16 */ +#define SYSACE_CTRLREG3 0x1B /* 31:24 */ + +/* + * Software reconfig thing + */ +#define SW_BYTE_SECTOR_ADDR 0x24FE0000 +#define SW_BYTE_SECTOR_OFFSET 0x0001FFFF +#define SW_BYTE_SECTOR_SIZE 0x00020000 +#define SW_BYTE_MASK 0x00000003 + +#define DEFAULT_TEMP_ADDR 0x00100000 + +#define AP1000_CPLD_BASE 0x26000000 + +/* PowerSpan II Stuff */ +#define PSII_SYNC() asm("eieio") +#define PSPAN_BASEADDR 0x30000000 +#define EEPROM_DEFAULT { 0x01, /* Byte 0 - Long Load = 0x02, short = 01, use 0xff for try no load */ \ + 0x0,0x0,0x0, /* Bytes 1 - 3 Power span reserved */ \ + 0x0, /* Byte 4 - Powerspan reserved - start of short load */ \ + 0x0F, /* Byte 5 - Enable PCI 1 & 2 as Bus masters and Memory targets. */ \ + 0x0E, /* Byte 6 - PCI 1 Target image prefetch - on for image 0,1,2, off for i20 & 3. */ \ + 0x00, 0x00, /* Byte 7,8 - PCI-1 Subsystem ID - */ \ + 0x00, 0x00, /* Byte 9,10 - PCI-1 Subsystem Vendor Id - */ \ + 0x00, /* Byte 11 - No PCI interrupt generation on PCI-1 PCI-2 int A */ \ + 0x1F, /* Byte 12 - PCI-1 enable bridge registers, all target images */ \ + 0xBA, /* Byte 13 - Target 0 image 128 Meg(Ram), Target 1 image 64 Meg. (config Flash/CPLD )*/ \ + 0xA0, /* Byte 14 - Target 2 image 64 Meg(program Flash), target 3 64k. */ \ + 0x00, /* Byte 15 - Vital Product Data Disabled. */ \ + 0x88, /* Byte 16 - PCI arbiter config complete, all requests routed through PCI-1, Unlock PCI-1 */ \ + 0x40, /* Byte 17 - Interrupt direction control - PCI-1 Int A out, everything else in. */ \ + 0x00, /* Byte 18 - I2O disabled */ \ + 0x00, /* Byte 19 - PCI-2 Target image prefetch - off for all images. */ \ + 0x00,0x00, /* Bytes 20,21 - PCI 2 Subsystem Id */ \ + 0x00,0x00, /* Bytes 22,23 - PCI 2 Subsystem Vendor id */ \ + 0x0C, /* Byte 24 - PCI-2 BAR enables, target image 0, & 1 */ \ + 0xBB, /* Byte 25 - PCI-2 target 0 - 128 Meg(Ram), target 1 - 128 Meg (program/config flash) */ \ + 0x00, /* Byte 26 - PCI-2 target 2 & 3 unused. */ \ + 0x00,0x00,0x00,0x00,0x00, /* Bytes 27,28,29,30, 31 - Reserved */ \ + /* Long Load Information */ \ + 0x82,0x60, /* Bytes 32,33 - PCI-1 Device ID - Powerspan II */ \ + 0x10,0xE3, /* Bytes 24,35 - PCI-1 Vendor ID - Tundra */ \ + 0x06, /* Byte 36 - PCI-1 Class Base - Bridge device. */ \ + 0x80, /* Byte 37 - PCI-1 Class sub class - Other bridge. */ \ + 0x00, /* Byte 38 - PCI-1 Class programing interface - Other bridge */ \ + 0x01, /* Byte 39 - Power span revision 1. */ \ + 0x6E, /* Byte 40 - PB SI0 enabled, translation enabled, decode enabled, 64 Meg */ \ + 0x40, /* Byte 41 - PB SI0 memory command mode, PCI-1 dest */ \ + 0x22, /* Byte 42 - Prefetch discard after read, PCI-little endian conversion, 32 byte prefetch */ \ + 0x00,0x00, /* Bytes 43, 44 - Translation address for SI0, set to zero for now. */ \ + 0x0E, /* Byte 45 - Translation address (0) and PB bus master enables - all. */ \ + 0x2c,00,00, /* Bytes 46,47,48 - PB SI0 processor base address - 0x2C000000 */ \ + 0x30,00,00, /* Bytes 49,50,51 - PB Address for Powerspan registers - 0x30000000, big Endian */ \ + 0x82,0x60, /* Bytes 52, 53 - PCI-2 Device ID - Powerspan II */ \ + 0x10,0xE3, /* Bytes 54,55 - PCI 2 Vendor Id - Tundra */ \ + 0x06, /* Byte 56 - PCI-2 Class Base - Bridge device */ \ + 0x80, /* Byte 57 - PCI-2 Class sub class - Other Bridge. */ \ + 0x00, /* Byte 58 - PCI-2 class programming interface - Other bridge */ \ + 0x01, /* Byte 59 - PCI-2 class revision 1 */ \ + 0x00,0x00,0x00,0x00 }; /* Bytes 60,61, 62, 63 - Powerspan reserved */ + + +#define EEPROM_LENGTH 64 /* Long Load */ + +#define I2C_SENSOR_DEV 0x9 +#define I2C_SENSOR_CHIP_SEL 0x4 + +/* + * Board Functions + */ +void set_eat_machine_checks(int a_flag); +int get_eat_machine_checks(void); +unsigned int get_platform(void); +unsigned int get_device(void); +void* memcpyb(void * dest,const void *src,size_t count); +int process_bootflag(ulong bootflag); +void user_led_on(void); +void user_led_off(void); + +#endif /* __COMMON_H_ */ diff --git a/board/amirix/ap1000/config.mk b/board/amirix/ap1000/config.mk new file mode 100644 index 00000000000..c09783a6aea --- /dev/null +++ b/board/amirix/ap1000/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# Start at bottom of RAM, but at an aliased address so that it looks +# like it's not in RAM. This is a bit of voodoo to allow it to be +# run from RAM instead of Flash. +TEXT_BASE = 0x08000000 diff --git a/board/amirix/ap1000/flash.c b/board/amirix/ap1000/flash.c new file mode 100644 index 00000000000..1a3b25218c5 --- /dev/null +++ b/board/amirix/ap1000/flash.c @@ -0,0 +1,903 @@ +/** + * @file flash.c + */ + +/* + * (C) Copyright 2003 + * AMIRIX Systems Inc. + * + * Originated from ppcboot-2.0.0/board/esd/cpci440/strataflash.c + * + * (C) Copyright 2002 + * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> + +#undef DEBUG_FLASH +/* + * This file implements a Common Flash Interface (CFI) driver for ppcboot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. + * It has been tested on an Intel Strataflash implementation. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * + * TODO + * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available + * Add support for other command sets Use the PRI and ALT to determine command set + * Verify erase and program timeouts. + */ + +#define FLASH_CMD_CFI 0x98 +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xD0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xD0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 + +#define FLASH_STATUS_DONE 0x80 +#define FLASH_STATUS_ESS 0x40 +#define FLASH_STATUS_ECLBS 0x20 +#define FLASH_STATUS_PSLBS 0x10 +#define FLASH_STATUS_VPENS 0x08 +#define FLASH_STATUS_PSS 0x04 +#define FLASH_STATUS_DPS 0x02 +#define FLASH_STATUS_R 0x01 +#define FLASH_STATUS_PROTECT 0x01 + +#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_CFI_RESP 0x10 +#define FLASH_OFFSET_WTOUT 0x1F +#define FLASH_OFFSET_WBTOUT 0x20 +#define FLASH_OFFSET_ETOUT 0x21 +#define FLASH_OFFSET_CETOUT 0x22 +#define FLASH_OFFSET_WMAX_TOUT 0x23 +#define FLASH_OFFSET_WBMAX_TOUT 0x24 +#define FLASH_OFFSET_EMAX_TOUT 0x25 +#define FLASH_OFFSET_CEMAX_TOUT 0x26 +#define FLASH_OFFSET_SIZE 0x27 +#define FLASH_OFFSET_INTERFACE 0x28 +#define FLASH_OFFSET_BUFFER_SIZE 0x2A +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C +#define FLASH_OFFSET_ERASE_REGIONS 0x2D +#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_USER_PROTECTION 0x85 +#define FLASH_OFFSET_INTEL_PROTECTION 0x81 + +#define FLASH_MAN_CFI 0x01000000 + +typedef union { + unsigned char c; + unsigned short w; + unsigned long l; +} cfiword_t; + +typedef union { + unsigned char *cp; + unsigned short *wp; + unsigned long *lp; +} cfiptr_t; + +#define NUM_ERASE_REGIONS 4 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ + +static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c); +static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf); +static void flash_write_cmd (flash_info_t * info, int sect, uchar offset, + uchar cmd); +static int flash_isequal (flash_info_t * info, int sect, uchar offset, + uchar cmd); +static int flash_isset (flash_info_t * info, int sect, uchar offset, + uchar cmd); +static int flash_detect_cfi (flash_info_t * info); +static ulong flash_get_size (ulong base, int banknum); +static int flash_write_cfiword (flash_info_t * info, ulong dest, + cfiword_t cword); +static int flash_full_status_check (flash_info_t * info, ulong sector, + ulong tout, char *prompt); +#ifdef CFG_FLASH_USE_BUFFER_WRITE +static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, + int len); +#endif +/*----------------------------------------------------------------------- + * create an address based on the offset and the port width + */ +uchar *flash_make_addr (flash_info_t * info, int sect, int offset) +{ + return ((uchar *) (info->start[sect] + (offset * info->chipwidth))); +} + +/*----------------------------------------------------------------------- + * read a character at a port width address + */ +uchar flash_read_uchar (flash_info_t * info, uchar offset) +{ + if (info->portwidth == FLASH_CFI_8BIT) { + volatile uchar *cp; + uchar c; + + cp = flash_make_addr (info, 0, offset); + c = *cp; +#ifdef DEBUG_FLASH + printf ("flash_read_uchar offset=%04x ptr=%08x c=%02x\n", + offset, (unsigned int) cp, c); +#endif + return (c); + + } else if (info->portwidth == FLASH_CFI_16BIT) { + volatile ushort *sp; + ushort s; + uchar c; + + sp = (ushort *) flash_make_addr (info, 0, offset); + s = *sp; + c = (uchar) s; +#ifdef DEBUG_FLASH + printf ("flash_read_uchar offset=%04x ptr=%08x s=%04x c=%02x\n", offset, (unsigned int) sp, s, c); +#endif + return (c); + + } + + return 0; +} + +/*----------------------------------------------------------------------- + * read a short word by swapping for ppc format. + */ +ushort flash_read_ushort (flash_info_t * info, int sect, uchar offset) +{ + if (info->portwidth == FLASH_CFI_8BIT) { + volatile uchar *cp; + uchar c0, c1; + ushort s; + + cp = flash_make_addr (info, 0, offset); + c1 = cp[2]; + c0 = cp[0]; + s = c1 << 8 | c0; +#ifdef DEBUG_FLASH + printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) cp, c1, c0, s); +#endif + return (s); + + } else if (info->portwidth == FLASH_CFI_16BIT) { + volatile ushort *sp; + ushort s; + uchar c0, c1; + + sp = (ushort *) flash_make_addr (info, 0, offset); + s = *sp; + c1 = (uchar) sp[1]; + c0 = (uchar) sp[0]; + s = c1 << 8 | c0; +#ifdef DEBUG_FLASH + printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) sp, c1, c0, s); +#endif + return (s); + + } + + return 0; +} + +/*----------------------------------------------------------------------- + * read a long word by picking the least significant byte of each maiximum + * port size word. Swap for ppc format. + */ +ulong flash_read_long (flash_info_t * info, int sect, uchar offset) +{ + if (info->portwidth == FLASH_CFI_8BIT) { + volatile uchar *cp; + uchar c0, c1, c2, c3; + ulong l; + + cp = flash_make_addr (info, 0, offset); + c3 = cp[6]; + c2 = cp[4]; + c1 = cp[2]; + c0 = cp[0]; + l = c3 << 24 | c2 << 16 | c1 << 8 | c0; +#ifdef DEBUG_FLASH + printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) cp, c3, c2, c1, c0, l); +#endif + return (l); + + } else if (info->portwidth == FLASH_CFI_16BIT) { + volatile ushort *sp; + uchar c0, c1, c2, c3; + ulong l; + + sp = (ushort *) flash_make_addr (info, 0, offset); + c3 = (uchar) sp[3]; + c2 = (uchar) sp[2]; + c1 = (uchar) sp[1]; + c0 = (uchar) sp[0]; + l = c3 << 24 | c2 << 16 | c1 << 8 | c0; +#ifdef DEBUG_FLASH + printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) sp, c3, c2, c1, c0, l); +#endif + return (l); + + } + + return 0; +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size; + + size = 0; + + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[0].portwidth = FLASH_CFI_16BIT; + flash_info[0].chipwidth = FLASH_CFI_16BIT; + size += flash_info[0].size = flash_get_size (CFG_PROGFLASH_BASE, 0); + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 1, flash_info[0].size, flash_info[0].size << 20); + }; + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].portwidth = FLASH_CFI_8BIT; + flash_info[1].chipwidth = FLASH_CFI_16BIT; + size += flash_info[1].size = flash_get_size (CFG_CONFFLASH_BASE, 1); + if (flash_info[1].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 2, flash_info[1].size, flash_info[1].size << 20); + }; + + return (size); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int rcode = 0; + int prot; + int sect; + + if (info->flash_id != FLASH_MAN_CFI) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + flash_write_cmd (info, sect, 0, + FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sect, 0, + FLASH_CMD_BLOCK_ERASE); + flash_write_cmd (info, sect, 0, + FLASH_CMD_ERASE_CONFIRM); + + if (flash_full_status_check + (info, sect, info->erase_blk_tout, "erase")) { + rcode = 1; + } else + printf ("."); + } + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id != FLASH_MAN_CFI) { + printf ("missing or unknown FLASH type\n"); + return; + } + + printf ("CFI conformant FLASH (x%d device in x%d mode)", + (info->chipwidth << 3), (info->portwidth << 3)); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n"); + printf (" %08lX%5s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp; + ulong cp; + int aln; + cfiword_t cword; + int i, rc; + + /* get lower aligned address */ + wp = (addr & ~(info->portwidth - 1)); + + /* handle unaligned start */ + if ((aln = addr - wp) != 0) { + cword.l = 0; + cp = wp; + for (i = 0; i < aln; ++i, ++cp) + flash_add_byte (info, &cword, (*(uchar *) cp)); + + for (; (i < info->portwidth) && (cnt > 0); i++) { + flash_add_byte (info, &cword, *src++); + cnt--; + cp++; + } + for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp) + flash_add_byte (info, &cword, (*(uchar *) cp)); + if ((rc = flash_write_cfiword (info, wp, cword)) != 0) + return rc; + wp = cp; + } +#ifdef CFG_FLASH_USE_BUFFER_WRITE + while (cnt >= info->portwidth) { + i = info->buffer_size > cnt ? cnt : info->buffer_size; + if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) + return rc; + wp += i; + src += i; + cnt -= i; + } +#else + /* handle the aligned part */ + while (cnt >= info->portwidth) { + cword.l = 0; + for (i = 0; i < info->portwidth; i++) { + flash_add_byte (info, &cword, *src++); + } + if ((rc = flash_write_cfiword (info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + } +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + cword.l = 0; + for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) { + flash_add_byte (info, &cword, *src++); + --cnt; + } + for (; i < info->portwidth; ++i, ++cp) { + flash_add_byte (info, &cword, (*(uchar *) cp)); + } + + return flash_write_cfiword (info, wp, cword); +} + +/*----------------------------------------------------------------------- + */ +int flash_real_protect (flash_info_t * info, long sector, int prot) +{ + int retcode = 0; + + flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); + if (prot) + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); + else + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + + if ((retcode = + flash_full_status_check (info, sector, info->erase_blk_tout, + prot ? "protect" : "unprotect")) == 0) { + + info->protect[sector] = prot; + /* Intel's unprotect unprotects all locking */ + if (prot == 0) { + int i; + + for (i = 0; i < info->sector_count; i++) { + if (info->protect[i]) + flash_real_protect (info, i, 1); + } + } + } + + return retcode; +} + +/*----------------------------------------------------------------------- + * wait for XSR.7 to be set. Time out with an error if it does not. + * This routine does not set the flash to read-array mode. + */ +static int flash_status_check (flash_info_t * info, ulong sector, ulong tout, + char *prompt) +{ + ulong start; + + /* Wait for command completion */ + start = get_timer (0); + while (!flash_isset (info, sector, 0, FLASH_STATUS_DONE)) { + if (get_timer (start) > info->erase_blk_tout) { + printf ("Flash %s timeout at address %lx\n", prompt, + info->start[sector]); + flash_write_cmd (info, sector, 0, FLASH_CMD_RESET); + return ERR_TIMOUT; + } + } + return ERR_OK; +} + +/*----------------------------------------------------------------------- + * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. + * This routine sets the flash to read-array mode. + */ +static int flash_full_status_check (flash_info_t * info, ulong sector, + ulong tout, char *prompt) +{ + int retcode; + + retcode = flash_status_check (info, sector, tout, prompt); + if ((retcode == ERR_OK) + && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { + retcode = ERR_INVAL; + printf ("Flash %s error at address %lx\n", prompt, + info->start[sector]); + if (flash_isset + (info, sector, 0, + FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) { + printf ("Command Sequence Error.\n"); + } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) { + printf ("Block Erase Error.\n"); + retcode = ERR_NOT_ERASED; + } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) { + printf ("Locking Error\n"); + } + if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { + printf ("Block locked.\n"); + retcode = ERR_PROTECTED; + } + if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) + printf ("Vpp Low Error.\n"); + } + flash_write_cmd (info, sector, 0, FLASH_CMD_RESET); + return retcode; +} + +/*----------------------------------------------------------------------- + */ +static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) +{ + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cword->c = c; + break; + case FLASH_CFI_16BIT: + cword->w = (cword->w << 8) | c; + break; + case FLASH_CFI_32BIT: + cword->l = (cword->l << 8) | c; + } +} + +/*----------------------------------------------------------------------- + * make a proper sized command based on the port and chip widths + */ +static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) +{ + /*int i; */ + uchar *cp = (uchar *) cmdbuf; + + /* for(i=0; i< info->portwidth; i++) */ + /* *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; */ + if (info->portwidth == FLASH_CFI_8BIT + && info->chipwidth == FLASH_CFI_16BIT) { + cp[0] = cmd; + } else if (info->portwidth == FLASH_CFI_16BIT + && info->chipwidth == FLASH_CFI_16BIT) { + cp[0] = '\0'; + cp[1] = cmd; + }; +} + +/* + * Write a proper sized command to the correct address + */ +static void flash_write_cmd (flash_info_t * info, int sect, uchar offset, + uchar cmd) +{ + + volatile cfiptr_t addr; + cfiword_t cword; + + addr.cp = flash_make_addr (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + *addr.cp = cword.c; + break; + case FLASH_CFI_16BIT: + *addr.wp = cword.w; + break; + case FLASH_CFI_32BIT: + *addr.lp = cword.l; + break; + } +} + +/*----------------------------------------------------------------------- + */ +static int flash_isequal (flash_info_t * info, int sect, uchar offset, + uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + + cptr.cp = flash_make_addr (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + retval = (cptr.cp[0] == cword.c); + break; + case FLASH_CFI_16BIT: + retval = (cptr.wp[0] == cword.w); + break; + case FLASH_CFI_32BIT: + retval = (cptr.lp[0] == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + */ +static int flash_isset (flash_info_t * info, int sect, uchar offset, + uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + + cptr.cp = flash_make_addr (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf + * +*/ +static int flash_detect_cfi (flash_info_t * info) +{ + +#if 0 + for (info->portwidth = FLASH_CFI_8BIT; + info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) { + for (info->chipwidth = FLASH_CFI_BY8; + info->chipwidth <= info->portwidth; + info->chipwidth <<= 1) { + flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd (info, 0, FLASH_OFFSET_CFI, + FLASH_CMD_CFI); + if (flash_isequal + (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') + && flash_isequal (info, 0, + FLASH_OFFSET_CFI_RESP + 1, 'R') + && flash_isequal (info, 0, + FLASH_OFFSET_CFI_RESP + 2, 'Y')) + return 1; + } + } +#endif + flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); + if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && + flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && + flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { + return 1; + } else { + return 0; + }; +} + +/* + * The following code cannot be run from FLASH! + * + */ +static ulong flash_get_size (ulong base, int banknum) +{ + flash_info_t *info = &flash_info[banknum]; + int i, j; + int sect_cnt; + unsigned long sector; + unsigned long tmp; + int size_ratio; + uchar num_erase_regions; + int erase_region_size; + int erase_region_count; + + info->start[0] = base; + + if (flash_detect_cfi (info)) { +#ifdef DEBUG_FLASH + printf ("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ +#endif + size_ratio = 1; /* info->portwidth / info->chipwidth; */ + num_erase_regions = + flash_read_uchar (info, + FLASH_OFFSET_NUM_ERASE_REGIONS); +#ifdef DEBUG_FLASH + printf ("found %d erase regions\n", num_erase_regions); +#endif + sect_cnt = 0; + sector = base; + for (i = 0; i < num_erase_regions; i++) { + if (i > NUM_ERASE_REGIONS) { + printf ("%d erase regions found, only %d used\n", num_erase_regions, NUM_ERASE_REGIONS); + break; + } + tmp = flash_read_long (info, 0, + FLASH_OFFSET_ERASE_REGIONS); + erase_region_count = (tmp & 0xffff) + 1; + tmp >>= 16; + erase_region_size = + (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; + for (j = 0; j < erase_region_count; j++) { + info->start[sect_cnt] = sector; + sector += (erase_region_size * size_ratio); + info->protect[sect_cnt] = + flash_isset (info, sect_cnt, + FLASH_OFFSET_PROTECT, + FLASH_STATUS_PROTECT); + sect_cnt++; + } + } + + info->sector_count = sect_cnt; + /* multiply the size by the number of chips */ + info->size = + (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * + size_ratio; + info->buffer_size = + (1 << + flash_read_ushort (info, 0, + FLASH_OFFSET_BUFFER_SIZE)); + tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT); + info->erase_blk_tout = + (tmp * + (1 << + flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT))); + tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT); + info->buffer_write_tout = + (tmp * + (1 << + flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT))); + tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT); + info->write_tout = + (tmp * + (1 << + flash_read_uchar (info, + FLASH_OFFSET_WMAX_TOUT))) / 1000; + info->flash_id = FLASH_MAN_CFI; + } + + flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); + return (info->size); +} + +/*----------------------------------------------------------------------- + */ +static int flash_write_cfiword (flash_info_t * info, ulong dest, + cfiword_t cword) +{ + + cfiptr_t ctladdr; + cfiptr_t cptr; + int flag; + + ctladdr.cp = flash_make_addr (info, 0, 0); + cptr.cp = (uchar *) dest; + + /* Check if Flash is (sufficiently) erased */ + switch (info->portwidth) { + case FLASH_CFI_8BIT: + flag = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + flag = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + flag = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + return 2; + } + if (!flag) + return 2; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); + + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cptr.cp[0] = cword.c; + break; + case FLASH_CFI_16BIT: + cptr.wp[0] = cword.w; + break; + case FLASH_CFI_32BIT: + cptr.lp[0] = cword.l; + break; + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + return flash_full_status_check (info, 0, info->write_tout, "write"); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static int find_sector (flash_info_t * info, ulong addr) +{ + int sector; + + for (sector = info->sector_count - 1; sector >= 0; sector--) { + if (addr >= info->start[sector]) + break; + } + return sector; +} + +static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, + int len) +{ + + int sector; + int cnt; + int retcode; + volatile cfiptr_t src; + volatile cfiptr_t dst; + + src.cp = cp; + dst.cp = (uchar *) dest; + sector = find_sector (info, dest); + flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + if ((retcode = + flash_status_check (info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + break; + default: + return ERR_INVAL; + break; + } + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) { + switch (info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + default: + return ERR_INVAL; + break; + } + } + flash_write_cmd (info, sector, 0, + FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = + flash_full_status_check (info, sector, + info->buffer_write_tout, + "buffer write"); + } + flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); + return retcode; +} +#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/amirix/ap1000/init.S b/board/amirix/ap1000/init.S new file mode 100644 index 00000000000..3aaa5c2f1a5 --- /dev/null +++ b/board/amirix/ap1000/init.S @@ -0,0 +1,34 @@ +/* + * init.S: Stubs for ppcboot initialization + * + * Copyright 2002 Mind NV + * + * http://www.mind.be/ + * + * Author : Peter De Schrijver (p2@mind.be) + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL) version 2, incorporated herein by + * reference. Drivers based on or derived from this code fall under the GPL + * and must retain the authorship, copyright and this license notice. This + * file is not a complete program and may only be used when the entire + * program is licensed under the GPL. + * + */ + +#include <ppc4xx.h> + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#include <asm/cache.h> +#include <asm/mmu.h> + + + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: + blr + + .globl sdram_init +sdram_init: + blr diff --git a/board/amirix/ap1000/pci.c b/board/amirix/ap1000/pci.c new file mode 100644 index 00000000000..a6436ac5bb3 --- /dev/null +++ b/board/amirix/ap1000/pci.c @@ -0,0 +1,318 @@ +/* + * (C) Copyright 2003 + * AMIRIX Systems Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <pci.h> + +#define PCI_MEM_82559ER_CSR_BASE 0x30200000 +#define PCI_IO_82559ER_CSR_BASE 0x40000200 + +/** AP1100 specific values */ +#define PSII_BASE 0x30000000 /**< PowerSpan II dual bridge local bus register address */ +#define PSII_CONFIG_ADDR 0x30000290 /**< PowerSpan II Configuration Cycle Address configuration register */ +#define PSII_CONFIG_DATA 0x30000294 /**< PowerSpan II Configuration Cycle Data register. */ +#define PSII_CONFIG_DEST_PCI2 0x01000000 /**< PowerSpan II configuration cycle destination selection, set for PCI2 bus */ +#define PSII_PCI_MEM_BASE 0x30200000 /**< Local Bus address for start of PCI memory space on PCI2 bus. */ +#define PSII_PCI_MEM_SIZE 0x1BE00000 /**< PCI Memory space about 510 Meg. */ +#define AP1000_SYS_MEM_START 0x00000000 /**< System memory starts at 0. */ +#define AP1000_SYS_MEM_SIZE 0x08000000 /**< System memory is 128 Meg. */ + +/* static int G_verbosity_level = 1; */ +#define G_verbosity_level 1 + +void write1 (unsigned long addr, unsigned char val) +{ + volatile unsigned char *p = (volatile unsigned char *) addr; + + if (G_verbosity_level > 1) + printf ("write1: addr=%08x val=%02x\n", (unsigned int) addr, + val); + *p = val; + asm ("eieio"); +} + +unsigned char read1 (unsigned long addr) +{ + unsigned char val; + volatile unsigned char *p = (volatile unsigned char *) addr; + + if (G_verbosity_level > 1) + printf ("read1: addr=%08x ", (unsigned int) addr); + val = *p; + asm ("eieio"); + if (G_verbosity_level > 1) + printf ("val=%08x\n", val); + return val; +} + +void write2 (unsigned long addr, unsigned short val) +{ + volatile unsigned short *p = (volatile unsigned short *) addr; + + if (G_verbosity_level > 1) + printf ("write2: addr=%08x val=%04x -> *p=%04x\n", + (unsigned int) addr, val, + ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8)); + + *p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8); + asm ("eieio"); +} + +unsigned short read2 (unsigned long addr) +{ + unsigned short val; + volatile unsigned short *p = (volatile unsigned short *) addr; + + if (G_verbosity_level > 1) + printf ("read2: addr=%08x ", (unsigned int) addr); + val = *p; + val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8); + asm ("eieio"); + if (G_verbosity_level > 1) + printf ("*p=%04x -> val=%04x\n", + ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8), val); + return val; +} + +void write4 (unsigned long addr, unsigned long val) +{ + volatile unsigned long *p = (volatile unsigned long *) addr; + + if (G_verbosity_level > 1) + printf ("write4: addr=%08x val=%08x -> *p=%08x\n", + (unsigned int) addr, (unsigned int) val, + (unsigned int) (((val & 0xFF000000) >> 24) | + ((val & 0x000000FF) << 24) | + ((val & 0x00FF0000) >> 8) | + ((val & 0x0000FF00) << 8))); + + *p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) | + ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8); + asm ("eieio"); +} + +unsigned long read4 (unsigned long addr) +{ + unsigned long val; + volatile unsigned long *p = (volatile unsigned long *) addr; + + if (G_verbosity_level > 1) + printf ("read4: addr=%08x", (unsigned int) addr); + + val = *p; + val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) | + ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8); + asm ("eieio"); + + if (G_verbosity_level > 1) + printf ("*p=%04x -> val=%04x\n", + (unsigned int) (((val & 0xFF000000) >> 24) | + ((val & 0x000000FF) << 24) | + ((val & 0x00FF0000) >> 8) | + ((val & 0x0000FF00) << 8)), + (unsigned int) val); + return val; +} + +void write4be (unsigned long addr, unsigned long val) +{ + volatile unsigned long *p = (volatile unsigned long *) addr; + + if (G_verbosity_level > 1) + printf ("write4: addr=%08x val=%08x\n", (unsigned int) addr, + (unsigned int) val); + *p = val; + asm ("eieio"); +} + +/** One byte configuration write on PSII. + * Currently fixes destination PCI bus to PCI2, onboard + * pci. + * @param hose PCI Host controller information. Ignored. + * @param dev Encoded PCI device/Bus and Function value. + * @param reg PCI Configuration register number. + * @param val Address of location for received byte. + * @return Always Zero. + */ +static int psII_read_config_byte (struct pci_controller *hose, + pci_dev_t dev, int reg, u8 * val) +{ + write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ + (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ + + *val = read1 (PSII_CONFIG_DATA + (reg & 0x03)); + return (0); +} + +/** One byte configuration write on PSII. + * Currently fixes destination bus to PCI2, onboard + * pci. + * @param hose PCI Host controller information. Ignored. + * @param dev Encoded PCI device/Bus and Function value. + * @param reg PCI Configuration register number. + * @param val Output byte. + * @return Always Zero. + */ +static int psII_write_config_byte (struct pci_controller *hose, + pci_dev_t dev, int reg, u8 val) +{ + write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ + (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ + + write1 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned char) val); + + return (0); +} + +/** One word (16 bit) configuration read on PSII. + * Currently fixes destination PCI bus to PCI2, onboard + * pci. + * @param hose PCI Host controller information. Ignored. + * @param dev Encoded PCI device/Bus and Function value. + * @param reg PCI Configuration register number. + * @param val Address of location for received word. + * @return Always Zero. + */ +static int psII_read_config_word (struct pci_controller *hose, + pci_dev_t dev, int reg, u16 * val) +{ + write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ + (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ + + *val = read2 (PSII_CONFIG_DATA + (reg & 0x03)); + return (0); +} + +/** One word (16 bit) configuration write on PSII. + * Currently fixes destination bus to PCI2, onboard + * pci. + * @param hose PCI Host controller information. Ignored. + * @param dev Encoded PCI device/Bus and Function value. + * @param reg PCI Configuration register number. + * @param val Output word. + * @return Always Zero. + */ +static int psII_write_config_word (struct pci_controller *hose, + pci_dev_t dev, int reg, u16 val) +{ + write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ + (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ + + write2 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned short) val); + + return (0); +} + +/** One DWord (32 bit) configuration read on PSII. + * Currently fixes destination PCI bus to PCI2, onboard + * pci. + * @param hose PCI Host controller information. Ignored. + * @param dev Encoded PCI device/Bus and Function value. + * @param reg PCI Configuration register number. + * @param val Address of location for received byte. + * @return Always Zero. + */ +static int psII_read_config_dword (struct pci_controller *hose, + pci_dev_t dev, int reg, u32 * val) +{ + write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ + (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ + + *val = read4 (PSII_CONFIG_DATA); + return (0); +} + +/** One DWord (32 bit) configuration write on PSII. + * Currently fixes destination bus to PCI2, onboard + * pci. + * @param hose PCI Host controller information. Ignored. + * @param dev Encoded PCI device/Bus and Function value. + * @param reg PCI Configuration register number. + * @param val Output Dword. + * @return Always Zero. + */ +static int psII_write_config_dword (struct pci_controller *hose, + pci_dev_t dev, int reg, u32 val) +{ + write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ + (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ + + write4 (PSII_CONFIG_DATA, (unsigned long) val); + + return (0); +} + +static struct pci_config_table ap1000_config_table[] = { +#ifdef CONFIG_AP1000 + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_BUS (CFG_ETH_DEV_FN), PCI_DEV (CFG_ETH_DEV_FN), + PCI_FUNC (CFG_ETH_DEV_FN), + pci_cfgfunc_config_device, + {CFG_ETH_IOBASE, CFG_ETH_MEMBASE, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, +#endif + {} +}; + +static struct pci_controller psII_hose = { + config_table:ap1000_config_table, +}; + +void pci_init_board (void) +{ + struct pci_controller *hose = &psII_hose; + + /* + * Register the hose + */ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* System memory space */ + pci_set_region (hose->regions + 0, + AP1000_SYS_MEM_START, AP1000_SYS_MEM_START, + AP1000_SYS_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI Memory space */ + pci_set_region (hose->regions + 1, + PSII_PCI_MEM_BASE, PSII_PCI_MEM_BASE, + PSII_PCI_MEM_SIZE, PCI_REGION_MEM); + + /* No IO Memory space - for now */ + + pci_set_ops (hose, + psII_read_config_byte, + psII_read_config_word, + psII_read_config_dword, + psII_write_config_byte, + psII_write_config_word, psII_write_config_dword); + + hose->region_count = 2; + + pci_register_hose (hose); + + hose->last_busno = pci_hose_scan (hose); +} diff --git a/board/amirix/ap1000/powerspan.c b/board/amirix/ap1000/powerspan.c new file mode 100644 index 00000000000..f0481553f07 --- /dev/null +++ b/board/amirix/ap1000/powerspan.c @@ -0,0 +1,750 @@ +/** + * @file powerspan.c Source file for PowerSpan II code. + */ + +/* + * (C) Copyright 2005 + * AMIRIX Systems Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/processor.h> +#include "powerspan.h" +#define tolower(x) x +#include "ap1000.h" + +#ifdef INCLUDE_PCI + +/** Write one byte with byte swapping. + * @param addr [IN] the address to write to + * @param val [IN] the value to write + */ +void write1 (unsigned long addr, unsigned char val) +{ + volatile unsigned char *p = (volatile unsigned char *) addr; + +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("write1: addr=%08x val=%02x\n", addr, val); + } +#endif + *p = val; + PSII_SYNC (); +} + +/** Read one byte with byte swapping. + * @param addr [IN] the address to read from + * @return the value at addr + */ +unsigned char read1 (unsigned long addr) +{ + unsigned char val; + volatile unsigned char *p = (volatile unsigned char *) addr; + + val = *p; + PSII_SYNC (); +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("read1: addr=%08x val=%02x\n", addr, val); + } +#endif + return val; +} + +/** Write one 2-byte word with byte swapping. + * @param addr [IN] the address to write to + * @param val [IN] the value to write + */ +void write2 (unsigned long addr, unsigned short val) +{ + volatile unsigned short *p = (volatile unsigned short *) addr; + +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("write2: addr=%08x val=%04x -> *p=%04x\n", addr, val, + ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8)); + } +#endif + *p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8); + PSII_SYNC (); +} + +/** Read one 2-byte word with byte swapping. + * @param addr [IN] the address to read from + * @return the value at addr + */ +unsigned short read2 (unsigned long addr) +{ + unsigned short val; + volatile unsigned short *p = (volatile unsigned short *) addr; + + val = *p; + val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8); + PSII_SYNC (); +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("read2: addr=%08x *p=%04x -> val=%04x\n", addr, *p, + val); + } +#endif + return val; +} + +/** Write one 4-byte word with byte swapping. + * @param addr [IN] the address to write to + * @param val [IN] the value to write + */ +void write4 (unsigned long addr, unsigned long val) +{ + volatile unsigned long *p = (volatile unsigned long *) addr; + +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("write4: addr=%08x val=%08x -> *p=%08x\n", addr, val, + ((val & 0xFF000000) >> 24) | + ((val & 0x000000FF) << 24) | + ((val & 0x00FF0000) >> 8) | + ((val & 0x0000FF00) << 8)); + } +#endif + *p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) | + ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8); + PSII_SYNC (); +} + +/** Read one 4-byte word with byte swapping. + * @param addr [IN] the address to read from + * @return the value at addr + */ +unsigned long read4 (unsigned long addr) +{ + unsigned long val; + volatile unsigned long *p = (volatile unsigned long *) addr; + + val = *p; + val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) | + ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8); + PSII_SYNC (); +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("read4: addr=%08x *p=%08x -> val=%08x\n", addr, *p, + val); + } +#endif + return val; +} + +int PCIReadConfig (int bus, int dev, int fn, int reg, int width, + unsigned long *val) +{ + unsigned int conAdrVal; + unsigned int conDataReg = REG_CONFIG_DATA; + unsigned int status; + int ret_val = 0; + + + /* DEST bit hardcoded to 1: local pci is PCI-2 */ + /* TYPE bit is hardcoded to 1: all config cycles are local */ + conAdrVal = (1 << 24) + | ((bus & 0xFF) << 16) + | ((dev & 0xFF) << 11) + | ((fn & 0x07) << 8) + | (reg & 0xFC); + + /* clear any pending master aborts */ + write4 (REG_P1_CSR, CLEAR_MASTER_ABORT); + + /* Load the conAdrVal value first, then read from pb_conf_data */ + write4 (REG_CONFIG_ADDRESS, conAdrVal); + PSII_SYNC (); + + + /* Note: documentation does not match the pspan library code */ + /* Note: *pData comes back as -1 if device is not present */ + switch (width) { + case 4: + *(unsigned int *) val = read4 (conDataReg); + break; + case 2: + *(unsigned short *) val = read2 (conDataReg); + break; + case 1: + *(unsigned char *) val = read1 (conDataReg); + break; + default: + ret_val = ILLEGAL_REG_OFFSET; + break; + } + PSII_SYNC (); + + /* clear any pending master aborts */ + status = read4 (REG_P1_CSR); + if (status & CLEAR_MASTER_ABORT) { + ret_val = NO_DEVICE_FOUND; + write4 (REG_P1_CSR, CLEAR_MASTER_ABORT); + } + + return ret_val; +} + + +int PCIWriteConfig (int bus, int dev, int fn, int reg, int width, + unsigned long val) +{ + unsigned int conAdrVal; + unsigned int conDataReg = REG_CONFIG_DATA; + unsigned int status; + int ret_val = 0; + + + /* DEST bit hardcoded to 1: local pci is PCI-2 */ + /* TYPE bit is hardcoded to 1: all config cycles are local */ + conAdrVal = (1 << 24) + | ((bus & 0xFF) << 16) + | ((dev & 0xFF) << 11) + | ((fn & 0x07) << 8) + | (reg & 0xFC); + + /* clear any pending master aborts */ + write4 (REG_P1_CSR, CLEAR_MASTER_ABORT); + + /* Load the conAdrVal value first, then read from pb_conf_data */ + write4 (REG_CONFIG_ADDRESS, conAdrVal); + PSII_SYNC (); + + + /* Note: documentation does not match the pspan library code */ + /* Note: *pData comes back as -1 if device is not present */ + switch (width) { + case 4: + write4 (conDataReg, val); + break; + case 2: + write2 (conDataReg, val); + break; + case 1: + write1 (conDataReg, val); + break; + default: + ret_val = ILLEGAL_REG_OFFSET; + break; + } + PSII_SYNC (); + + /* clear any pending master aborts */ + status = read4 (REG_P1_CSR); + if (status & CLEAR_MASTER_ABORT) { + ret_val = NO_DEVICE_FOUND; + write4 (REG_P1_CSR, CLEAR_MASTER_ABORT); + } + + return ret_val; +} + + +int pci_read_config_byte (int bus, int dev, int fn, int reg, + unsigned char *val) +{ + unsigned long read_val; + int ret_val; + + ret_val = PCIReadConfig (bus, dev, fn, reg, 1, &read_val); + *val = read_val & 0xFF; + + return ret_val; +} + +int pci_write_config_byte (int bus, int dev, int fn, int reg, + unsigned char val) +{ + return PCIWriteConfig (bus, dev, fn, reg, 1, val); +} + +int pci_read_config_word (int bus, int dev, int fn, int reg, + unsigned short *val) +{ + unsigned long read_val; + int ret_val; + + ret_val = PCIReadConfig (bus, dev, fn, reg, 2, &read_val); + *val = read_val & 0xFFFF; + + return ret_val; +} + +int pci_write_config_word (int bus, int dev, int fn, int reg, + unsigned short val) +{ + return PCIWriteConfig (bus, dev, fn, reg, 2, val); +} + +int pci_read_config_dword (int bus, int dev, int fn, int reg, + unsigned long *val) +{ + return PCIReadConfig (bus, dev, fn, reg, 4, val); +} + +int pci_write_config_dword (int bus, int dev, int fn, int reg, + unsigned long val) +{ + return PCIWriteConfig (bus, dev, fn, reg, 4, val); +} + +#endif /* INCLUDE_PCI */ + +int I2CAccess (unsigned char theI2CAddress, unsigned char theDevCode, + unsigned char theChipSel, unsigned char *theValue, int RWFlag) +{ + int ret_val = 0; + unsigned int reg_value; + + reg_value = PowerSpanRead (REG_I2C_CSR); + + if (reg_value & I2C_CSR_ACT) { + printf ("Error: I2C busy\n"); + ret_val = I2C_BUSY; + } else { + reg_value = ((theI2CAddress & 0xFF) << 24) + | ((theDevCode & 0x0F) << 12) + | ((theChipSel & 0x07) << 9) + | I2C_CSR_ERR; + if (RWFlag == I2C_WRITE) { + reg_value |= I2C_CSR_RW | ((*theValue & 0xFF) << 16); + } + + PowerSpanWrite (REG_I2C_CSR, reg_value); + udelay (1); + + do { + reg_value = PowerSpanRead (REG_I2C_CSR); + + if ((reg_value & I2C_CSR_ACT) == 0) { + if (reg_value & I2C_CSR_ERR) { + ret_val = I2C_ERR; + } else { + *theValue = + (reg_value & I2C_CSR_DATA) >> + 16; + } + } + } while (reg_value & I2C_CSR_ACT); + } + + return ret_val; +} + +int EEPROMRead (unsigned char theI2CAddress, unsigned char *theValue) +{ + return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL, + theValue, I2C_READ); +} + +int EEPROMWrite (unsigned char theI2CAddress, unsigned char theValue) +{ + return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL, + &theValue, I2C_WRITE); +} + +int do_eeprom (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char cmd; + int ret_val = 0; + unsigned int address = 0; + unsigned char value = 1; + unsigned char read_value; + int ii; + int error = 0; + unsigned char *mem_ptr; + unsigned char default_eeprom[] = EEPROM_DEFAULT; + + if (argc < 2) { + goto usage; + } + + cmd = argv[1][0]; + if (argc > 2) { + address = simple_strtoul (argv[2], NULL, 16); + if (argc > 3) { + value = simple_strtoul (argv[3], NULL, 16) & 0xFF; + } + } + + switch (cmd) { + case 'r': + if (address > 256) { + printf ("Illegal Address\n"); + goto usage; + } + printf ("@0x%x: ", address); + for (ii = 0; ii < value; ii++) { + if (EEPROMRead (address + ii, &read_value) != + 0) { + printf ("Read Error\n"); + } else { + printf ("0x%02x ", read_value); + } + + if (((ii + 1) % 16) == 0) { + printf ("\n"); + } + } + printf ("\n"); + break; + case 'w': + if (address > 256) { + printf ("Illegal Address\n"); + goto usage; + } + if (argc < 4) { + goto usage; + } + if (EEPROMWrite (address, value) != 0) { + printf ("Write Error\n"); + } + break; + case 'g': + if (argc != 3) { + goto usage; + } + mem_ptr = (unsigned char *) address; + for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0)); + ii++) { + if (EEPROMRead (ii, &read_value) != 0) { + printf ("Read Error\n"); + error = 1; + } else { + *mem_ptr = read_value; + mem_ptr++; + } + } + break; + case 'p': + if (argc != 3) { + goto usage; + } + mem_ptr = (unsigned char *) address; + for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0)); + ii++) { + if (EEPROMWrite (ii, *mem_ptr) != 0) { + printf ("Write Error\n"); + error = 1; + } + + mem_ptr++; + } + break; + case 'd': + if (argc != 2) { + goto usage; + } + for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0)); + ii++) { + if (EEPROMWrite (ii, default_eeprom[ii]) != 0) { + printf ("Write Error\n"); + error = 1; + } + } + break; + default: + goto usage; + } + + goto done; + usage: + printf ("Usage:\n%s\n", cmdtp->help); + + done: + return ret_val; + +} + +U_BOOT_CMD (eeprom, 4, 0, do_eeprom, + "eeprom - read/write/copy to/from the PowerSpan II eeprom\n", + "eeprom r OFF [NUM]\n" + " - read NUM words starting at OFF\n" + "eeprom w OFF VAL\n" + " - write word VAL at offset OFF\n" + "eeprom g ADD\n" + " - store contents of eeprom at address ADD\n" + "eeprom p ADD\n" + " - put data stored at address ADD into the eeprom\n" + "eeprom d\n" " - return eeprom to default contents\n"); + +unsigned int PowerSpanRead (unsigned int theOffset) +{ + volatile unsigned int *ptr = + (volatile unsigned int *) (PSPAN_BASEADDR + theOffset); + unsigned int ret_val; + +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("PowerSpanRead: offset=%08x ", theOffset); + } +#endif + ret_val = *ptr; + PSII_SYNC (); + +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("value=%08x\n", ret_val); + } +#endif + + return ret_val; +} + +void PowerSpanWrite (unsigned int theOffset, unsigned int theValue) +{ + volatile unsigned int *ptr = + (volatile unsigned int *) (PSPAN_BASEADDR + theOffset); +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("PowerSpanWrite: offset=%08x val=%02x\n", theOffset, + theValue); + } +#endif + *ptr = theValue; + PSII_SYNC (); +} + +/** + * Sets the indicated bits in the indicated register. + * @param theOffset [IN] the register to access. + * @param theMask [IN] bits set in theMask will be set in the register. + */ +void PowerSpanSetBits (unsigned int theOffset, unsigned int theMask) +{ + volatile unsigned int *ptr = + (volatile unsigned int *) (PSPAN_BASEADDR + theOffset); + unsigned int register_value; + +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("PowerSpanSetBits: offset=%08x mask=%02x\n", + theOffset, theMask); + } +#endif + register_value = *ptr; + PSII_SYNC (); + + register_value |= theMask; + *ptr = register_value; + PSII_SYNC (); +} + +/** + * Clears the indicated bits in the indicated register. + * @param theOffset [IN] the register to access. + * @param theMask [IN] bits set in theMask will be cleared in the register. + */ +void PowerSpanClearBits (unsigned int theOffset, unsigned int theMask) +{ + volatile unsigned int *ptr = + (volatile unsigned int *) (PSPAN_BASEADDR + theOffset); + unsigned int register_value; + +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("PowerSpanClearBits: offset=%08x mask=%02x\n", + theOffset, theMask); + } +#endif + register_value = *ptr; + PSII_SYNC (); + + register_value &= ~theMask; + *ptr = register_value; + PSII_SYNC (); +} + +/** + * Configures a slave image on the local bus, based on the parameters and some hardcoded system values. + * Slave Images are images that cause the PowerSpan II to be a master on the PCI bus. Thus, they + * are outgoing from the standpoint of the local bus. + * @param theImageIndex [IN] the PowerSpan II image to set (assumed to be 0-7). + * @param theBlockSize [IN] the block size of the image (as used by PowerSpan II: PB_SIx_CTL[BS]). + * @param theMemIOFlag [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set. + * @param theEndianness [IN] the endian bits for the image (already shifted, use defines). + * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size). + * @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size). + */ +int SetSlaveImage (int theImageIndex, unsigned int theBlockSize, + int theMemIOFlag, int theEndianness, + unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr) +{ + unsigned int reg_offset = theImageIndex * PB_SLAVE_IMAGE_OFF; + unsigned int reg_value = 0; + + /* Make sure that the Slave Image is disabled */ + PowerSpanClearBits ((REGS_PB_SLAVE_CSR + reg_offset), + PB_SLAVE_CSR_IMG_EN); + + /* Setup the mask required for requested PB Slave Image configuration */ + reg_value = PB_SLAVE_CSR_TA_EN | theEndianness | (theBlockSize << 24); + if (theMemIOFlag == PB_SLAVE_USE_MEM_IO) { + reg_value |= PB_SLAVE_CSR_MEM_IO; + } + + /* hardcoding the following: + TA_EN = 1 + MD_EN = 0 + MODE = 0 + PRKEEP = 0 + RD_AMT = 0 + */ + PowerSpanWrite ((REGS_PB_SLAVE_CSR + reg_offset), reg_value); + + /* these values are not checked by software */ + PowerSpanWrite ((REGS_PB_SLAVE_BADDR + reg_offset), theLocalBaseAddr); + PowerSpanWrite ((REGS_PB_SLAVE_TADDR + reg_offset), thePCIBaseAddr); + + /* Enable the Slave Image */ + PowerSpanSetBits ((REGS_PB_SLAVE_CSR + reg_offset), + PB_SLAVE_CSR_IMG_EN); + + return 0; +} + +/** + * Configures a target image on the local bus, based on the parameters and some hardcoded system values. + * Target Images are used when the PowerSpan II is acting as a target for an access. Thus, they + * are incoming from the standpoint of the local bus. + * In order to behave better on the host PCI bus, if thePCIBaseAddr is NULL (0x00000000), then the PCI + * base address will not be updated; makes sense given that the hosts own memory should be mapped to + * PCI address 0x00000000. + * @param theImageIndex [IN] the PowerSpan II image to set. + * @param theBlockSize [IN] the block size of the image (as used by PowerSpan II: Px_TIx_CTL[BS]). + * @param theMemIOFlag [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set. + * @param theEndianness [IN] the endian bits for the image (already shifted, use defines). + * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size). + * @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size). + */ +int SetTargetImage (int theImageIndex, unsigned int theBlockSize, + int theMemIOFlag, int theEndianness, + unsigned int theLocalBaseAddr, + unsigned int thePCIBaseAddr) +{ + unsigned int csr_reg_offset = theImageIndex * P1_TGT_IMAGE_OFF; + unsigned int pci_reg_offset = theImageIndex * P1_BST_OFF; + unsigned int reg_value = 0; + + /* Make sure that the Slave Image is disabled */ + PowerSpanClearBits ((REGS_P1_TGT_CSR + csr_reg_offset), + PB_SLAVE_CSR_IMG_EN); + + /* Setup the mask required for requested PB Slave Image configuration */ + reg_value = + PX_TGT_CSR_TA_EN | PX_TGT_CSR_BAR_EN | (theBlockSize << 24) | + PX_TGT_CSR_RTT_READ | PX_TGT_CSR_WTT_WFLUSH | theEndianness; + if (theMemIOFlag == PX_TGT_USE_MEM_IO) { + reg_value |= PX_TGT_MEM_IO; + } + + /* hardcoding the following: + TA_EN = 1 + BAR_EN = 1 + MD_EN = 0 + MODE = 0 + DEST = 0 + RTT = 01010 + GBL = 0 + CI = 0 + WTT = 00010 + PRKEEP = 0 + MRA = 0 + RD_AMT = 0 + */ + PowerSpanWrite ((REGS_P1_TGT_CSR + csr_reg_offset), reg_value); + + PowerSpanWrite ((REGS_P1_TGT_TADDR + csr_reg_offset), + theLocalBaseAddr); + + if (thePCIBaseAddr != (unsigned int) NULL) { + PowerSpanWrite ((REGS_P1_BST + pci_reg_offset), + thePCIBaseAddr); + } + + /* Enable the Slave Image */ + PowerSpanSetBits ((REGS_P1_TGT_CSR + csr_reg_offset), + PB_SLAVE_CSR_IMG_EN); + + return 0; +} + +int do_bridge (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char cmd; + int ret_val = 1; + unsigned int image_index; + unsigned int block_size; + unsigned int mem_io; + unsigned int local_addr; + unsigned int pci_addr; + int endianness; + + if (argc != 8) { + goto usage; + } + + cmd = argv[1][0]; + image_index = simple_strtoul (argv[2], NULL, 16); + block_size = simple_strtoul (argv[3], NULL, 16); + mem_io = simple_strtoul (argv[4], NULL, 16); + endianness = argv[5][0]; + local_addr = simple_strtoul (argv[6], NULL, 16); + pci_addr = simple_strtoul (argv[7], NULL, 16); + + + switch (cmd) { + case 'i': + if (tolower (endianness) == 'b') { + endianness = PX_TGT_CSR_BIG_END; + } else if (tolower (endianness) == 'l') { + endianness = PX_TGT_CSR_TRUE_LEND; + } else { + goto usage; + } + SetTargetImage (image_index, block_size, mem_io, + endianness, local_addr, pci_addr); + break; + case 'o': + if (tolower (endianness) == 'b') { + endianness = PB_SLAVE_CSR_BIG_END; + } else if (tolower (endianness) == 'l') { + endianness = PB_SLAVE_CSR_TRUE_LEND; + } else { + goto usage; + } + SetSlaveImage (image_index, block_size, mem_io, + endianness, local_addr, pci_addr); + break; + default: + goto usage; + } + + goto done; +usage: + printf ("Usage:\n%s\n", cmdtp->help); + +done: + return ret_val; +} diff --git a/board/amirix/ap1000/powerspan.h b/board/amirix/ap1000/powerspan.h new file mode 100644 index 00000000000..4e9a8c1bd86 --- /dev/null +++ b/board/amirix/ap1000/powerspan.h @@ -0,0 +1,170 @@ +/** + * @file powerspan.h Header file for PowerSpan II code. + */ + +/* + * (C) Copyright 2005 + * AMIRIX Systems Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef POWERSPAN_H +#define POWERSPAN_H + +#define CLEAR_MASTER_ABORT 0xdeadbeef +#define NO_DEVICE_FOUND -1 +#define ILLEGAL_REG_OFFSET -2 +#define I2C_BUSY -3 +#define I2C_ERR -4 + +#define REG_P1_CSR 0x004 +#define REGS_P1_BST 0x018 +#define REG_P1_ERR_CSR 0x150 +#define REG_P1_MISC_CSR 0x160 +#define REGS_P1_TGT_CSR 0x100 +#define REGS_P1_TGT_TADDR 0x104 +#define REGS_PB_SLAVE_CSR 0x200 +#define REGS_PB_SLAVE_TADDR 0x204 +#define REGS_PB_SLAVE_BADDR 0x208 +#define REG_CONFIG_ADDRESS 0x290 +#define REG_CONFIG_DATA 0x294 +#define REG_PB_ERR_CSR 0x2B0 +#define REG_PB_MISC_CSR 0x2C0 +#define REG_MISC_CSR 0x400 +#define REG_I2C_CSR 0x408 +#define REG_RESET_CSR 0x40C +#define REG_ISR0 0x410 +#define REG_ISR1 0x414 +#define REG_IER0 0x418 +#define REG_MBOX_MAP 0x420 +#define REG_HW_MAP 0x42C +#define REG_IDR 0x444 + +#define CSR_MEMORY_SPACE_ENABLE 0x00000002 +#define CSR_PCI_MASTER_ENABLE 0x00000004 + +#define P1_BST_OFF 0x04 + +#define PX_ERR_ERR_STATUS 0x01000000 + +#define PX_MISC_CSR_MAX_RETRY_MASK 0x00000F00 +#define PX_MISC_CSR_MAX_RETRY 0x00000F00 +#define PX_MISC_REG_BAR_ENABLE 0x00008000 +#define PB_MISC_TEA_ENABLE 0x00000010 +#define PB_MISC_MAC_TEA 0x00000040 + +#define P1_TGT_IMAGE_OFF 0x010 +#define PX_TGT_CSR_IMG_EN 0x80000000 +#define PX_TGT_CSR_TA_EN 0x40000000 +#define PX_TGT_CSR_BAR_EN 0x20000000 +#define PX_TGT_CSR_MD_EN 0x10000000 +#define PX_TGT_CSR_MODE 0x00800000 +#define PX_TGT_CSR_DEST 0x00400000 +#define PX_TGT_CSR_MEM_IO 0x00200000 +#define PX_TGT_CSR_GBL 0x00080000 +#define PX_TGT_CSR_CL 0x00040000 +#define PX_TGT_CSR_PRKEEP 0x00000080 + +#define PX_TGT_CSR_BS_MASK 0x0F000000 +#define PX_TGT_MEM_IO 0x00200000 +#define PX_TGT_CSR_RTT_MASK 0x001F0000 +#define PX_TGT_CSR_RTT_READ 0x000A0000 +#define PX_TGT_CSR_WTT_MASK 0x00001F00 +#define PX_TGT_CSR_WTT_WFLUSH 0x00000200 +#define PX_TGT_CSR_END_MASK 0x00000060 +#define PX_TGT_CSR_BIG_END 0x00000040 +#define PX_TGT_CSR_TRUE_LEND 0x00000060 +#define PX_TGT_CSR_RDAMT_MASK 0x00000007 + +#define PX_TGT_CSR_BS_64MB 0xa +#define PX_TGT_CSR_BS_16MB 0x8 + +#define PX_TGT_USE_MEM_IO 1 +#define PX_TGT_NOT_MEM_IO 0 + +#define PB_SLAVE_IMAGE_OFF 0x010 +#define PB_SLAVE_CSR_IMG_EN 0x80000000 +#define PB_SLAVE_CSR_TA_EN 0x40000000 +#define PB_SLAVE_CSR_MD_EN 0x20000000 +#define PB_SLAVE_CSR_MODE 0x00800000 +#define PB_SLAVE_CSR_DEST 0x00400000 +#define PB_SLAVE_CSR_MEM_IO 0x00200000 +#define PB_SLAVE_CSR_PRKEEP 0x00000080 + +#define PB_SLAVE_CSR_BS_MASK 0x1F000000 +#define PB_SLAVE_CSR_END_MASK 0x00000060 +#define PB_SLAVE_CSR_BIG_END 0x00000040 +#define PB_SLAVE_CSR_TRUE_LEND 0x00000060 +#define PB_SLAVE_CSR_RDAMT_MASK 0x00000007 + +#define PB_SLAVE_USE_MEM_IO 1 +#define PB_SLAVE_NOT_MEM_IO 0 + + +#define MISC_CSR_PCI1_LOCK 0x00000080 + +#define I2C_CSR_ADDR 0xFF000000 /* Specifies I2C Device Address to be Accessed */ +#define I2C_CSR_DATA 0x00FF0000 /* Specifies the Required Data for a Write */ +#define I2C_CSR_DEV_CODE 0x0000F000 /* Device Select. I2C 4-bit Device Code */ +#define I2C_CSR_CS 0x00000E00 /* Chip Select */ +#define I2C_CSR_RW 0x00000100 /* Read/Write */ +#define I2C_CSR_ACT 0x00000080 /* I2C Interface Active */ +#define I2C_CSR_ERR 0x00000040 /* Error */ + +#define I2C_EEPROM_DEV 0xa +#define I2C_EEPROM_CHIP_SEL 0 + +#define I2C_READ 0 +#define I2C_WRITE 1 + +#define RESET_CSR_EEPROM_LOAD 0x00000010 + +#define ISR_CLEAR_ALL 0xFFFFFFFF + +#define IER0_DMA_INTS_EN 0x0F000000 +#define IER0_PCI_1_EN 0x00400000 +#define IER0_HW_INTS_EN 0x003F0000 +#define IER0_MB_INTS_EN 0x000000FF +#define IER0_DEFAULT (IER0_DMA_INTS_EN | IER0_PCI_1_EN | IER0_HW_INTS_EN | IER0_MB_INTS_EN) + +#define MBOX_MAP_TO_INT4 0xCCCCCCCC + +#define HW_MAP_HW4_TO_INT4 0x000C0000 + +#define IDR_PCI_A_OUT 0x40000000 +#define IDR_MBOX_OUT 0x10000000 + + +int pci_read_config_byte(int bus, int dev, int fn, int reg, unsigned char* val); +int pci_write_config_byte(int bus, int dev, int fn, int reg, unsigned char val); +int pci_read_config_word(int bus, int dev, int fn, int reg, unsigned short* val); +int pci_write_config_word(int bus, int dev, int fn, int reg, unsigned short val); +int pci_read_config_dword(int bus, int dev, int fn, int reg, unsigned long* val); +int pci_write_config_dword(int bus, int dev, int fn, int reg, unsigned long val); + +unsigned int PowerSpanRead(unsigned int theOffset); +void PowerSpanWrite(unsigned int theOffset, unsigned int theValue); + +int I2CAccess(unsigned char theI2CAddress, unsigned char theDevCode, unsigned char theChipSel, unsigned char* theValue, int RWFlag); + +int PCIWriteConfig(int bus, int dev, int fn, int reg, int width, unsigned long val); +int PCIReadConfig(int bus, int dev, int fn, int reg, int width, unsigned long* val); + +int SetSlaveImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr); +int SetTargetImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr); + +#endif diff --git a/board/amirix/ap1000/serial.c b/board/amirix/ap1000/serial.c new file mode 100644 index 00000000000..39c41579259 --- /dev/null +++ b/board/amirix/ap1000/serial.c @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2002 + * Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <asm/u-boot.h> +#include <asm/processor.h> +#include <common.h> +#include <command.h> +#include <config.h> + +#include <ns16550.h> + +#if 0 +#include "serial.h" +#endif + +const NS16550_t COM_PORTS[] = + { (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 }; + +#undef CFG_DUART_CHAN +#define CFG_DUART_CHAN gComPort +static int gComPort = 0; + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + + (void) NS16550_init (COM_PORTS[0], clock_divisor); + gComPort = 0; + + return 0; +} + +void serial_putc (const char c) +{ + if (c == '\n') { + NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r'); + } + + NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c); +} + +int serial_getc (void) +{ + return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]); +} + +int serial_tstc (void) +{ + return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]); +} + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + +#ifdef CFG_INIT_CHAN1 + NS16550_reinit (COM_PORTS[0], clock_divisor); +#endif +#ifdef CFG_INIT_CHAN2 + NS16550_reinit (COM_PORTS[1], clock_divisor); +#endif +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +void kgdb_serial_init (void) +{ +} + +void putDebugChar (int c) +{ + serial_putc (c); +} + +void putDebugStr (const char *str) +{ + serial_puts (str); +} + +int getDebugChar (void) +{ + return serial_getc (); +} + +void kgdb_interruptible (int yes) +{ + return; +} +#endif /* CFG_CMD_KGDB */ diff --git a/board/amirix/ap1000/u-boot.lds b/board/amirix/ap1000/u-boot.lds new file mode 100644 index 00000000000..97e8290e4b8 --- /dev/null +++ b/board/amirix/ap1000/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amirix/ap1000/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/armadillo/flash.c b/board/armadillo/flash.c index f25a8e7bba6..037a6430dab 100644 --- a/board/armadillo/flash.c +++ b/board/armadillo/flash.c @@ -118,7 +118,9 @@ void flash_print_info (flash_info_t * info) } printf ("\n"); - Done: +/* +Done: ; +*/ } /* diff --git a/board/barco/barco.c b/board/barco/barco.c index 2fb370098a3..613e72274c8 100644 --- a/board/barco/barco.c +++ b/board/barco/barco.c @@ -90,17 +90,17 @@ long int initdram (int board_type) long mear1; long emear1; - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + size = get_ram_size (CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); + mear1 = mpc824x_mpc107_getreg (MEAR1); + emear1 = mpc824x_mpc107_getreg (EMEAR1); mear1 = (mear1 & 0xFFFFFF00) | ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); emear1 = (emear1 & 0xFFFFFF00) | ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); + mpc824x_mpc107_setreg (MEAR1, mear1); + mpc824x_mpc107_setreg (EMEAR1, emear1); return (size); } @@ -113,11 +113,11 @@ static struct pci_config_table pci_barcohydra_config_table[] = { { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, PCI_ENET1_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, { } }; #endif @@ -128,68 +128,66 @@ struct pci_controller hose = { #endif }; -void pci_init_board(void) +void pci_init_board (void) { - pci_mpc824x_init(&hose); + pci_mpc824x_init (&hose); } -int write_flash(char *addr, char value) +int write_flash (char *addr, char value) { char *adr = (char *)0xFF800000; int cnt = 0; char status,oldstatus; - *(adr+0x55) = 0xAA; - udelay(1); - *(adr+0xAA) = 0x55; - udelay(1); - *(adr+0x55) = 0xA0; - udelay(1); + *(adr+0x55) = 0xAA; udelay (1); + *(adr+0xAA) = 0x55; udelay (1); + *(adr+0x55) = 0xA0; udelay (1); *addr = value; status = *addr; - do{ - + do { oldstatus = status; status = *addr; - if ((oldstatus & 0x40) == (status & 0x40)){ + if ((oldstatus & 0x40) == (status & 0x40)) { return 4; } cnt++; - if (cnt > 10000){ + if (cnt > 10000) { return 2; } - }while( (status & 0x20) == 0 ); + } while ( (status & 0x20) == 0 ); oldstatus = *addr; status = *addr; - if ((oldstatus & 0x40) == (status & 0x40)) return 0; - else { + if ((oldstatus & 0x40) == (status & 0x40)) { + return 0; + } else { *(adr+0x55) = 0xF0; return 1; } } -unsigned update_flash(unsigned char* buf){ - switch((*buf) & 0x3){ - case TRY_WORKING: - printf("found 3 and converted it to 2\n"); - write_flash(buf, (*buf) & 0xFE); - *((unsigned char *)0xFF800000) = 0xF0; - udelay(100); - printf("buf [%#010x] %#010x\n",buf,(*buf)); - case BOOT_WORKING : - return BOOT_WORKING; +unsigned update_flash (unsigned char *buf) +{ + switch ((*buf) & 0x3) { + case TRY_WORKING: + printf ("found 3 and converted it to 2\n"); + write_flash (buf, (*buf) & 0xFE); + *((unsigned char *)0xFF800000) = 0xF0; + udelay (100); + printf ("buf [%#010x] %#010x\n", buf, (*buf)); + /* XXX - fall through??? */ + case BOOT_WORKING : + return BOOT_WORKING; } return BOOT_DEFAULT; } -unsigned scan_flash(void) +unsigned scan_flash (void) { char section[] = "kernel"; - ulong sp; int cfgFileLen = (CFG_FLASH_ERASE_SECTOR_LENGTH >> 1); int sectionPtr = 0; int foundItem = 0; /* 0: None, 1: section found, 2: "=" found */ @@ -198,57 +196,54 @@ unsigned scan_flash(void) buf = (unsigned char*)(CFG_FLASH_RANGE_BASE + CFG_FLASH_RANGE_SIZE \ - CFG_FLASH_ERASE_SECTOR_LENGTH); - for(bufPtr = 0; bufPtr < cfgFileLen; ++bufPtr){ + for (bufPtr = 0; bufPtr < cfgFileLen; ++bufPtr) { if ((buf[bufPtr]==0xFF) && (*(int*)(buf+bufPtr)==0xFFFFFFFF)) { return BOOT_DEFAULT; } - switch(foundItem) - { - /* This is the scanning loop, we try to find a particular - * quoted value - */ - case 0: - if((section[sectionPtr] == 0)){ - ++foundItem; - } - else if(buf[bufPtr] == section[sectionPtr]){ - ++sectionPtr; - } - else { - sectionPtr = 0; - } - break; - case 1: + /* This is the scanning loop, we try to find a particular + * quoted value + */ + switch (foundItem) { + case 0: + if ((section[sectionPtr] == 0)) { ++foundItem; - break; - case 2: - ++foundItem; - break; - case 3: - default: - return update_flash(buf[bufPtr - 1]); + } else if (buf[bufPtr] == section[sectionPtr]) { + ++sectionPtr; + } else { + sectionPtr = 0; + } + break; + case 1: + ++foundItem; + break; + case 2: + ++foundItem; + break; + case 3: + default: + return update_flash (&buf[bufPtr - 1]); } } - printf("Failed to read %s\n",section); + printf ("Failed to read %s\n",section); return BOOT_DEFAULT; } -TSBootInfo* find_boot_info(void) +TSBootInfo* find_boot_info (void) { - unsigned bootimage = scan_flash(); - TSBootInfo* info = (TSBootInfo*)malloc(sizeof(TSBootInfo)); - - switch(bootimage){ - case TRY_WORKING: - info->address = CFG_WORKING_KERNEL_ADDRESS; - break; - case BOOT_WORKING : - info->address = CFG_WORKING_KERNEL_ADDRESS; - break; - case BOOT_DEFAULT: - default: - info->address= CFG_DEFAULT_KERNEL_ADDRESS; + unsigned bootimage = scan_flash (); + TSBootInfo* info = (TSBootInfo*)malloc (sizeof(TSBootInfo)); + + switch (bootimage) { + case TRY_WORKING: + info->address = CFG_WORKING_KERNEL_ADDRESS; + break; + case BOOT_WORKING : + info->address = CFG_WORKING_KERNEL_ADDRESS; + break; + case BOOT_DEFAULT: + default: + info->address= CFG_DEFAULT_KERNEL_ADDRESS; } info->size = *((unsigned int *)(info->address )); @@ -256,43 +251,44 @@ TSBootInfo* find_boot_info(void) return info; } -void barcobcd_boot(void) +void barcobcd_boot (void) { TSBootInfo* start; char *bootm_args[2]; char *buf; int cnt; + extern int do_bootm (cmd_tbl_t *, int, int, char *[]); buf = (char *)(0x00800000); /* make certain there are enough chars to print the command line here! */ - bootm_args[0]=(char *)malloc(16*sizeof(char)); - bootm_args[1]=(char *)malloc(16*sizeof(char)); + bootm_args[0] = (char *)malloc (16*sizeof(char)); + bootm_args[1] = (char *)malloc (16*sizeof(char)); - start = find_boot_info(); + start = find_boot_info (); - printf("Booting kernel at address %#10x with size %#10x\n", + printf ("Booting kernel at address %#10x with size %#10x\n", start->address, start->size); /* give length of the kernel image to bootm */ - sprintf(bootm_args[0],"%x",start->size); + sprintf (bootm_args[0],"%x",start->size); /* give address of the kernel image to bootm */ - sprintf(bootm_args[1],"%x",buf); + sprintf (bootm_args[1],"%x",buf); - printf("flash address: %#10x\n",start->address+8); - printf("buf address: %#10x\n",buf); + printf ("flash address: %#10x\n",start->address+8); + printf ("buf address: %#10x\n",buf); /* aha, we reserve 8 bytes here... */ - for (cnt = 0; cnt < start->size ; cnt++){ + for (cnt = 0; cnt < start->size ; cnt++) { buf[cnt] = ((char *)start->address)[cnt+8]; } /* initialise RAM memory */ *((unsigned int *)0xFEC00000) = 0x00141A98; - do_bootm(NULL,0,2,bootm_args); + do_bootm (NULL,0,2,bootm_args); } -int barcobcd_boot_image(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +int barcobcd_boot_image (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { #if 0 if (argc > 1) { @@ -300,7 +296,7 @@ int barcobcd_boot_image(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } #endif - barcobcd_boot(); + barcobcd_boot (); return 0; } @@ -308,19 +304,19 @@ int barcobcd_boot_image(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* Currently, boot_working and boot_default are the same command. This is * left in here to see what we'll do in the future */ -U_BOOT_CMD( +U_BOOT_CMD ( try_working, 1, 1, barcobcd_boot_image, " try_working - check flash value and boot the appropriate image\n", "\n" ); -U_BOOT_CMD( +U_BOOT_CMD ( boot_working, 1, 1, barcobcd_boot_image, " boot_working - check flash value and boot the appropriate image\n", "\n" ); -U_BOOT_CMD( +U_BOOT_CMD ( boot_default, 1, 1, barcobcd_boot_image, " boot_default - check flash value and boot the appropriate image\n", "\n" @@ -328,13 +324,40 @@ U_BOOT_CMD( /* * We are not using serial communication, so just provide empty functions */ -int serial_init(void){return 0;} -void serial_setbrg(void){} -void serial_putc(const char c){} -void serial_puts(const char *c){} -void serial_addr(unsigned int i){} -int serial_getc(void){return 0;} -int serial_tstc(void){return 0;} - -unsigned long post_word_load(void){return 0l;}; -void post_word_store(unsigned long val){} +int serial_init (void) +{ + return 0; +} +void serial_setbrg (void) +{ + return; +} +void serial_putc (const char c) +{ + return; +} +void serial_puts (const char *c) +{ + return; +} +void serial_addr (unsigned int i) +{ + return; +} +int serial_getc (void) +{ + return 0; +} +int serial_tstc (void) +{ + return 0; +} + +unsigned long post_word_load (void) +{ + return 0l; +} +void post_word_store (unsigned long val) +{ + return; +} diff --git a/board/csb637/config.mk b/board/csb637/config.mk index 7e1457da881..4c6f6311349 100644 --- a/board/csb637/config.mk +++ b/board/csb637/config.mk @@ -1 +1 @@ -TEXT_BASE = 0x23fe0000 +TEXT_BASE = 0x23fc0000 diff --git a/board/integratorap/Makefile b/board/integratorap/Makefile index cf76dedb2da..358df62519a 100644 --- a/board/integratorap/Makefile +++ b/board/integratorap/Makefile @@ -30,7 +30,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a OBJS := integratorap.o flash.o -SOBJS := platform.o memsetup.o +SOBJS := lowlevel_init.o memsetup.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/integratorap/integratorap.c b/board/integratorap/integratorap.c index 4baf39a6778..d4f61d6403d 100644 --- a/board/integratorap/integratorap.c +++ b/board/integratorap/integratorap.c @@ -649,8 +649,3 @@ ulong get_tbclk (void) { return CFG_HZ_CLOCK/div_clock; } - -/* The Integrator/AP timer1 is clocked at 24MHz - * can be divided by 16 or 256 - * and is a 16-bit counter - */ diff --git a/board/integratorap/platform.S b/board/integratorap/lowlevel_init.S index b208adb3713..ab9589c95c4 100644 --- a/board/integratorap/platform.S +++ b/board/integratorap/lowlevel_init.S @@ -37,9 +37,9 @@ reset_cpu: reset_failed: b reset_failed -/* set up the platform, once the cpu has been initialized */ -.globl platformsetup -platformsetup: +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: /* If U-Boot has been run after the ARM boot monitor * then all the necessary actions have been done * otherwise we are running from user flash mapped to 0x00000000 @@ -67,17 +67,17 @@ platformsetup: !defined (CONFIG_CM940T) #ifdef CONFIG_CM_MULTIPLE_SSRAM - /* set simple mapping */ + /* set simple mapping */ and r2,r2,#CMMASK_MAP_SIMPLE -#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */ +#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */ #ifdef CONFIG_CM_TCRAM - /* disable TCRAM */ + /* disable TCRAM */ and r2,r2,#CMMASK_TCRAM_DISABLE -#endif /* #ifdef CONFIG_CM_TCRAM */ +#endif /* #ifdef CONFIG_CM_TCRAM */ #if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \ - defined (CONFIG_CM1136JF_S) + defined (CONFIG_CM1136JF_S) and r2,r2,#CMMASK_LE @@ -89,7 +89,7 @@ platformsetup: #endif /* ARM102xxE value */ - /* read CM_INIT */ + /* read CM_INIT */ mov r0, #CM_BASE ldr r1, [r0, #OS_INIT] /* check against desired bit setting */ @@ -125,28 +125,28 @@ init_reg_OK: .globl dram_query dram_query: stmfd r13!,{r4-r6,lr} - /* set up SDRAM info */ + /* set up SDRAM info */ /* - based on example code from the CM User Guide */ mov r0, #CM_BASE readspdbit: - ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */ - and r1, r1, #0x20 /* mask SPD bit (5) */ - cmp r1, #0x20 /* test if set */ + ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */ + and r1, r1, #0x20 /* mask SPD bit (5) */ + cmp r1, #0x20 /* test if set */ bne readspdbit setupsdram: - add r0, r0, #OS_SPD /* address the copy of the SDP data */ - ldrb r1, [r0, #3] /* number of row address lines */ - ldrb r2, [r0, #4] /* number of column address lines */ - ldrb r3, [r0, #5] /* number of banks */ - ldrb r4, [r0, #31] /* module bank density */ - mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */ - mov r5, r5, ASL#2 /* size in MB */ - mov r0, #CM_BASE /* reload for later code */ - cmp r5, #0x10 /* is it 16MB? */ + add r0, r0, #OS_SPD /* address the copy of the SDP data */ + ldrb r1, [r0, #3] /* number of row address lines */ + ldrb r2, [r0, #4] /* number of column address lines */ + ldrb r3, [r0, #5] /* number of banks */ + ldrb r4, [r0, #31] /* module bank density */ + mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */ + mov r5, r5, ASL#2 /* size in MB */ + mov r0, #CM_BASE /* reload for later code */ + cmp r5, #0x10 /* is it 16MB? */ bne not16 - mov r6, #0x2 /* store size and CAS latency of 2 */ + mov r6, #0x2 /* store size and CAS latency of 2 */ b writesize not16: @@ -197,17 +197,17 @@ cm_remap: orr r1, r1, #CMMASK_REMAP /* set remap and led bits */ str r1, [r0, #OS_CTRL] - /* Now 0x00000000 is writeable, replace the vectors */ - ldr r0, =_start /* r0 <- start of vectors */ - ldr r2, =_armboot_start /* r2 <- past vectors */ - sub r1,r1,r1 /* destination 0x00000000 */ + /* Now 0x00000000 is writeable, replace the vectors */ + ldr r0, =_start /* r0 <- start of vectors */ + ldr r2, =_armboot_start /* r2 <- past vectors */ + sub r1,r1,r1 /* destination 0x00000000 */ copy_vec: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ ble copy_vec - ldmfd r13!,{r4-r10,pc} /* back to caller */ + ldmfd r13!,{r4-r10,pc} /* back to caller */ #endif /* #ifdef CONFIG_CM_REMAP */ diff --git a/board/integratorap/split_by_variant.sh b/board/integratorap/split_by_variant.sh new file mode 100755 index 00000000000..9f71babf35d --- /dev/null +++ b/board/integratorap/split_by_variant.sh @@ -0,0 +1,116 @@ +#!/bin/sh +# --------------------------------------------------------- +# Set the platform defines +# --------------------------------------------------------- +echo -n "/* Integrator configuration implied " > tmp.fil +echo " by Makefile target */" >> tmp.fil +echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil +echo " /* Integrator board */" >> tmp.fil +echo -n "#define CONFIG_ARCH_INTEGRATOR" >> tmp.fil +echo " 1 /* Integrator/AP */" >> tmp.fil +# --------------------------------------------------------- +# Set the core module defines according to Core Module +# --------------------------------------------------------- +cpu="arm_intcm" +variant="unknown core module" + +if [ "$1" == "" ] +then + echo "$0:: No parameters - using arm_intcm" +else + case "$1" in + ap7_config) + cpu="arm_intcm" + variant="unported core module CM7TDMI" + ;; + + ap966) + cpu="arm_intcm" + variant="unported core module CM966E-S" + ;; + + ap922_config) + cpu="arm_intcm" + variant="unported core module CM922T" + ;; + + integratorap_config | \ + ap_config) + cpu="arm_intcm" + variant="unspecified core module" + ;; + + ap720t_config) + cpu="arm720t" + echo -n "#define CONFIG_CM720T" >> tmp.fil + echo " 1 /* CPU core is ARM720T */ " >> tmp.fil + variant="Core module CM720T" + ;; + + ap922_XA10_config) + cpu="arm_intcm" + variant="unported core module CM922T_XA10" + echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil + echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil + ;; + + ap920t_config) + cpu="arm920t" + variant="Core module CM920T" + echo -n "#define CONFIG_CM920T" >> tmp.fil + echo " 1 /* CPU core is ARM920T */" >> tmp.fil + ;; + + ap926ejs_config) + cpu="arm926ejs" + variant="Core module CM926EJ-S" + echo -n "#define CONFIG_CM926EJ_S" >> tmp.fil + echo " 1 /* CPU core is ARM926EJ-S */ " >> tmp.fil + ;; + + ap946es_config) + cpu="arm946es" + variant="Core module CM946E-S" + echo -n "#define CONFIG_CM946E_S" >> tmp.fil + echo " 1 /* CPU core is ARM946E-S */ " >> tmp.fil + ;; + + *) + echo "$0:: Unknown core module" + variant="unknown core module" + cpu="arm_intcm" + ;; + + esac +fi + +if [ "$cpu" == "arm_intcm" ] +then + echo "/* Core module undefined/not ported */" >> tmp.fil + echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil + echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil + echo -n " /* CM may not have " >> tmp.fil + echo "multiple SSRAM mapping */" >> tmp.fil + echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil + echo -n " /* CM may not support SPD " >> tmp.fil + echo "query */" >> tmp.fil + echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil + echo -n " /* CM may not support " >> tmp.fil + echo "remapping */" >> tmp.fil + echo -n "#undef CONFIG_CM_INIT " >> tmp.fil + echo -n " /* CM may not have " >> tmp.fil + echo "initialization reg */" >> tmp.fil + echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil + echo " /* CM may not have TCRAM */" >> tmp.fil +fi +mv tmp.fil ./include/config.h +# --------------------------------------------------------- +# Ensure correct core object loaded first in U-Boot image +# --------------------------------------------------------- +sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' board/integratorap/u-boot.lds.template > board/integratorap/u-boot.lds +# --------------------------------------------------------- +# Complete the configuration +# --------------------------------------------------------- +./mkconfig -a integratorap arm $cpu integratorap; +echo "Variant:: $variant with core $cpu" + diff --git a/board/integratorap/u-boot.lds b/board/integratorap/u-boot.lds.template index cb6ee188b19..0ec8087258a 100644 --- a/board/integratorap/u-boot.lds +++ b/board/integratorap/u-boot.lds.template @@ -20,6 +20,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ +# Template used during configuration to emsure the core module processor code, +# from CPU_FILE, is placed at the start of the image */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) @@ -30,8 +32,8 @@ SECTIONS . = ALIGN(4); .text : { - cpu/arm926ejs/start.o (.text) - *(.text) + CPU_FILE (.text) + *(.text) } .rodata : { *(.rodata) } . = ALIGN(4); diff --git a/board/integratorcp/Makefile b/board/integratorcp/Makefile index 71532d11367..3d589fcd5ad 100644 --- a/board/integratorcp/Makefile +++ b/board/integratorcp/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a OBJS := integratorcp.o flash.o -SOBJS := platform.o memsetup.o +SOBJS := lowlevel_init.o memsetup.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/integratorcp/platform.S b/board/integratorcp/lowlevel_init.S index 612a2c4586a..18f7d2eaebe 100644 --- a/board/integratorcp/platform.S +++ b/board/integratorcp/lowlevel_init.S @@ -37,9 +37,9 @@ reset_cpu: reset_failed: b reset_failed -/* set up the platform, once the cpu has been initialized */ -.globl platformsetup -platformsetup: +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: /* If U-Boot has been run after the ARM boot monitor * then all the necessary actions have been done * otherwise we are running from user flash mapped to 0x00000000 @@ -63,22 +63,22 @@ platformsetup: orr r2,r2,#CMMASK_INIT_102 #else -#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \ - !defined (CONFIG_CM940T) - /* CMxx6 code */ +#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \ + !defined (CONFIG_CM940T) + /* CMxx6 code */ #ifdef CONFIG_CM_MULTIPLE_SSRAM - /* set simple mapping */ + /* set simple mapping */ and r2,r2,#CMMASK_MAP_SIMPLE -#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */ +#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */ #ifdef CONFIG_CM_TCRAM - /* disable TCRAM */ + /* disable TCRAM */ and r2,r2,#CMMASK_TCRAM_DISABLE -#endif /* #ifdef CONFIG_CM_TCRAM */ +#endif /* #ifdef CONFIG_CM_TCRAM */ #if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \ - defined (CONFIG_CM1136JF_S) + defined (CONFIG_CM1136JF_S) and r2,r2,#CMMASK_LE @@ -90,7 +90,7 @@ platformsetup: #endif /* ARM102xxE value */ - /* read CM_INIT */ + /* read CM_INIT */ mov r0, #CM_BASE ldr r1, [r0, #OS_INIT] /* check against desired bit setting */ @@ -121,33 +121,33 @@ init_reg_OK: #ifdef CONFIG_CM_SPD_DETECT /* Fast memory is available for the DRAM data * - ensure it has been transferred, then summarize the data - * into a CM register + * into a CM register */ .globl dram_query dram_query: stmfd r13!,{r4-r6,lr} - /* set up SDRAM info */ + /* set up SDRAM info */ /* - based on example code from the CM User Guide */ mov r0, #CM_BASE readspdbit: ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */ - and r1, r1, #0x20 /* mask SPD bit (5) */ - cmp r1, #0x20 /* test if set */ + and r1, r1, #0x20 /* mask SPD bit (5) */ + cmp r1, #0x20 /* test if set */ bne readspdbit setupsdram: - add r0, r0, #OS_SPD /* address the copy of the SDP data */ - ldrb r1, [r0, #3] /* number of row address lines */ - ldrb r2, [r0, #4] /* number of column address lines */ - ldrb r3, [r0, #5] /* number of banks */ - ldrb r4, [r0, #31] /* module bank density */ - mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */ - mov r5, r5, ASL#2 /* size in MB */ - mov r0, #CM_BASE /* reload for later code */ - cmp r5, #0x10 /* is it 16MB? */ + add r0, r0, #OS_SPD /* address the copy of the SDP data */ + ldrb r1, [r0, #3] /* number of row address lines */ + ldrb r2, [r0, #4] /* number of column address lines */ + ldrb r3, [r0, #5] /* number of banks */ + ldrb r4, [r0, #31] /* module bank density */ + mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */ + mov r5, r5, ASL#2 /* size in MB */ + mov r0, #CM_BASE /* reload for later code */ + cmp r5, #0x10 /* is it 16MB? */ bne not16 - mov r6, #0x2 /* store size and CAS latency of 2 */ + mov r6, #0x2 /* store size and CAS latency of 2 */ b writesize not16: @@ -198,17 +198,17 @@ cm_remap: orr r1, r1, #CMMASK_REMAP /* set remap and led bits */ str r1, [r0, #OS_CTRL] - /* Now 0x00000000 is writeable, replace the vectors */ - ldr r0, =_start /* r0 <- start of vectors */ - ldr r2, =_armboot_start /* r2 <- past vectors */ - sub r1,r1,r1 /* destination 0x00000000 */ + /* Now 0x00000000 is writeable, replace the vectors */ + ldr r0, =_start /* r0 <- start of vectors */ + ldr r2, =_armboot_start /* r2 <- past vectors */ + sub r1,r1,r1 /* destination 0x00000000 */ copy_vec: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ ble copy_vec - ldmfd r13!,{r4-r10,pc} /* back to caller */ + ldmfd r13!,{r4-r10,pc} /* back to caller */ #endif /* #ifdef CONFIG_CM_REMAP */ diff --git a/board/integratorcp/split_by_variant.sh b/board/integratorcp/split_by_variant.sh new file mode 100755 index 00000000000..3a354339d7c --- /dev/null +++ b/board/integratorcp/split_by_variant.sh @@ -0,0 +1,111 @@ +#!/bin/sh +# --------------------------------------------------------- +# Set the platform defines +# --------------------------------------------------------- +echo -n "/* Integrator configuration implied " > tmp.fil +echo " by Makefile target */" >> tmp.fil +echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil +echo " /* Integrator board */" >> tmp.fil +echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> tmp.fil +echo " 1 /* Integrator/CP */" >> tmp.fil + +cpu="arm_intcm" +variant="unknown core module" + +if [ "$1" == "" ] +then + echo "$0:: No parameters - using arm_intcm" +else + case "$1" in + ap966) + cpu="arm_intcm" + variant="unported core module CM966E-S" + ;; + + ap922_config) + cpu="arm_intcm" + variant="unported core module CM922T" + ;; + + integratorcp_config | \ + cp_config) + cpu="arm_intcm" + variant="unspecified core module" + ;; + + cp922_XA10_config) + cpu="arm_intcm" + variant="unported core module CM922T_XA10" + echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil + echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil + ;; + + cp920t_config) + cpu="arm920t" + variant="Core module CM920T" + echo -n "#define CONFIG_CM920T" >> tmp.fil + echo " 1 /* CPU core is ARM920T */" >> tmp.fil + ;; + + cp926ejs_config) + cpu="arm926ejs" + variant="Core module CM926EJ-S" + echo -n "#define CONFIG_CM926EJ_S" >> tmp.fil + echo " 1 /* CPU core is ARM926EJ-S */ " >> tmp.fil + ;; + + + cp946es_config) + cpu="arm946es" + variant="Core module CM946E-S" + echo -n "#define CONFIG_CM946E_S" >> tmp.fil + echo " 1 /* CPU core is ARM946E-S */ " >> tmp.fil + ;; + + cp1136_config) + cpu="arm1136" + variant="Core module CM1136EJF-S" + echo -n "#define CONFIG_CM1136EJF_S" >> tmp.fil + echo " 1 /* CPU core is ARM1136JF-S */ " >> tmp.fil + ;; + + *) + echo "$0:: Unknown core module" + variant="unknown core module" + cpu="arm_intcm" + ;; + + esac + +fi + +if [ "$cpu" == "arm_intcm" ] +then + echo "/* Core module undefined/not ported */" >> tmp.fil + echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil + echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil + echo -n " /* CM may not have " >> tmp.fil + echo "multiple SSRAM mapping */" >> tmp.fil + echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil + echo -n " /* CM may not support SPD " >> tmp.fil + echo "query */" >> tmp.fil + echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil + echo -n " /* CM may not support " >> tmp.fil + echo "remapping */" >> tmp.fil + echo -n "#undef CONFIG_CM_INIT " >> tmp.fil + echo -n " /* CM may not have " >> tmp.fil + echo "initialization reg */" >> tmp.fil + echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil + echo " /* CM may not have TCRAM */" >> tmp.fil +fi +mv tmp.fil ./include/config.h +# --------------------------------------------------------- +# Ensure correct core object loaded first in U-Boot image +# --------------------------------------------------------- +sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' board/integratorcp/u-boot.lds.template > board/integratorcp/u-boot.lds +# --------------------------------------------------------- +# Complete the configuration +# --------------------------------------------------------- +./mkconfig -a integratorcp arm $cpu integratorcp; +echo "Variant:: $variant with core $cpu" + diff --git a/board/integratorcp/u-boot.lds b/board/integratorcp/u-boot.lds.template index cb6ee188b19..0ec8087258a 100644 --- a/board/integratorcp/u-boot.lds +++ b/board/integratorcp/u-boot.lds.template @@ -20,6 +20,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ +# Template used during configuration to emsure the core module processor code, +# from CPU_FILE, is placed at the start of the image */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) @@ -30,8 +32,8 @@ SECTIONS . = ALIGN(4); .text : { - cpu/arm926ejs/start.o (.text) - *(.text) + CPU_FILE (.text) + *(.text) } .rodata : { *(.rodata) } . = ALIGN(4); diff --git a/board/ns9750dev/Makefile b/board/ns9750dev/Makefile index d2718cc683a..fb4333c19c0 100644 --- a/board/ns9750dev/Makefile +++ b/board/ns9750dev/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a OBJS := ns9750dev.o flash.o led.o -SOBJS := platform.o +SOBJS := lowlevel_init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) $(SOBJS) diff --git a/board/ns9750dev/platform.S b/board/ns9750dev/lowlevel_init.S index afcad154082..3a0978663a7 100644 --- a/board/ns9750dev/platform.S +++ b/board/ns9750dev/lowlevel_init.S @@ -75,8 +75,8 @@ _CAS_LATENCY: .word 0x00022000 @ for CAS2 latency #ifndef CONFIG_SKIP_LOWLEVEL_INIT -.globl platformsetup -platformsetup: +.globl lowlevel_init +lowlevel_init: /* U-Boot may be linked to RAM at 0x780000. But this code will run in flash from 0x0. But in order to enable RAM we have to disable the diff --git a/board/omap1510inn/Makefile b/board/omap1510inn/Makefile index bd6285cb231..902b24ea1ac 100644 --- a/board/omap1510inn/Makefile +++ b/board/omap1510inn/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a OBJS := omap1510innovator.o -SOBJS := platform.o +SOBJS := lowlevel_init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/omap1510inn/platform.S b/board/omap1510inn/lowlevel_init.S index 8045e84b2dd..1c68e5b816e 100644 --- a/board/omap1510inn/platform.S +++ b/board/omap1510inn/lowlevel_init.S @@ -39,8 +39,8 @@ _TEXT_BASE: .word TEXT_BASE /* sdram load addr from config.mk */ -.globl platformsetup -platformsetup: +.globl lowlevel_init +lowlevel_init: /* * Configure 1510 pins functions to match our board. diff --git a/board/omap1610inn/Makefile b/board/omap1610inn/Makefile index 4a96b8334be..4560102327e 100644 --- a/board/omap1610inn/Makefile +++ b/board/omap1610inn/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a OBJS := omap1610innovator.o flash.o -SOBJS := platform.o +SOBJS := lowlevel_init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/omap1610inn/platform.S b/board/omap1610inn/lowlevel_init.S index d694f94bb9d..eaf1742cc73 100644 --- a/board/omap1610inn/platform.S +++ b/board/omap1610inn/lowlevel_init.S @@ -37,8 +37,8 @@ _TEXT_BASE: .word TEXT_BASE /* sdram load addr from config.mk */ -.globl platformsetup -platformsetup: +.globl lowlevel_init +lowlevel_init: /*------------------------------------------------------* diff --git a/board/omap2420h4/Makefile b/board/omap2420h4/Makefile index 38dec00d367..ed4786879a1 100644 --- a/board/omap2420h4/Makefile +++ b/board/omap2420h4/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a OBJS := omap2420h4.o mem.o sys_info.o -SOBJS := platform.o +SOBJS := lowlevel_init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/omap2420h4/platform.S b/board/omap2420h4/lowlevel_init.S index 73ba4628575..9752fc488da 100644 --- a/board/omap2420h4/platform.S +++ b/board/omap2420h4/lowlevel_init.S @@ -158,8 +158,8 @@ pll_div_add: pll_div_val: .word DPLL_VAL /* DPLL setting (300MHz default) */ -.globl platformsetup -platformsetup: +.globl lowlevel_init +lowlevel_init: ldr sp, SRAM_STACK str ip, [sp] /* stash old link register */ mov ip, lr /* save link reg across call */ diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c index c729eca0154..6ae1a490a50 100644 --- a/board/omap2420h4/omap2420h4.c +++ b/board/omap2420h4/omap2420h4.c @@ -71,24 +71,6 @@ int board_init (void) ***********************************************************/ void try_unlock_sram(void) { - int mode; - - /* if GP device unlock device SRAM for general use */ - mode = (__raw_readl(CONTROL_STATUS) & (BIT8|BIT9)); - if (mode == GP_DEVICE) { - __raw_writel(0xFF, A_REQINFOPERM0); - __raw_writel(0xCFDE, A_READPERM0); - __raw_writel(0xCFDE, A_WRITEPERM0); - } -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_sram(void) -{ /* if GP device unlock device SRAM for general use */ if (get_device_type() == GP_DEVICE) { __raw_writel(0xFF, A_REQINFOPERM0); diff --git a/board/omap5912osk/Makefile b/board/omap5912osk/Makefile index 64804663a96..4b564217b74 100644 --- a/board/omap5912osk/Makefile +++ b/board/omap5912osk/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a OBJS := omap5912osk.o -SOBJS := platform.o +SOBJS := lowlevel_init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/omap5912osk/platform.S b/board/omap5912osk/lowlevel_init.S index 33c72423ab0..3b9633ad988 100644 --- a/board/omap5912osk/platform.S +++ b/board/omap5912osk/lowlevel_init.S @@ -38,8 +38,8 @@ _TEXT_BASE: .word TEXT_BASE /* sdram load addr from config.mk */ -.globl platformsetup -platformsetup: +.globl lowlevel_init +lowlevel_init: /*------------------------------------------------------* diff --git a/board/omap730p2/Makefile b/board/omap730p2/Makefile index 10585080739..29467ac39e6 100644 --- a/board/omap730p2/Makefile +++ b/board/omap730p2/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a OBJS := omap730p2.o flash.o -SOBJS := platform.o +SOBJS := lowlevel_init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/omap730p2/platform.S b/board/omap730p2/lowlevel_init.S index f30c2424ffb..6c6f48240a2 100644 --- a/board/omap730p2/platform.S +++ b/board/omap730p2/lowlevel_init.S @@ -43,8 +43,8 @@ _TEXT_BASE: .word TEXT_BASE /* sdram load addr from config.mk */ -.globl platformsetup -platformsetup: +.globl lowlevel_init +lowlevel_init: /* Save callers address in r11 - r11 must never be modified */ mov r11, lr diff --git a/board/stxxtc/Makefile b/board/stxxtc/Makefile index 8c529a0611d..11065cfd2c4 100644 --- a/board/stxxtc/Makefile +++ b/board/stxxtc/Makefile @@ -25,11 +25,19 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o +OBJS = $(BOARD).o oftree.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) +%.dtb: %.dts + dtc -f -V 0x10 -I dts -O dtb $< >$@ + +%.c: %.dtb + xxd -i $< \ + | sed -e "s/^unsigned char/const unsigned char/g" \ + | sed -e "s/^unsigned int/const unsigned int/g" > $@ + ######################################################################### .depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) diff --git a/board/sx1/Makefile b/board/sx1/Makefile index 8cd02d1411b..8fbdf2a5e33 100644 --- a/board/sx1/Makefile +++ b/board/sx1/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a OBJS := sx1.o -SOBJS := platform.o +SOBJS := lowlevel_init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/sx1/platform.S b/board/sx1/lowlevel_init.S index bd54df18c44..bdf812e05af 100644 --- a/board/sx1/platform.S +++ b/board/sx1/lowlevel_init.S @@ -39,8 +39,8 @@ _TEXT_BASE: .word TEXT_BASE /* sdram load addr from config.mk */ -.globl platformsetup -platformsetup: +.globl lowlevel_init +lowlevel_init: /* * Configure 1510 pins functions to match our board. diff --git a/board/versatile/Makefile b/board/versatile/Makefile index 42b6ed5b5c9..fbdc627e386 100644 --- a/board/versatile/Makefile +++ b/board/versatile/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a OBJS := versatile.o flash.o -SOBJS := platform.o +SOBJS := lowlevel_init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/versatile/platform.S b/board/versatile/lowlevel_init.S index 68c3e8b1857..bdfce2d3c13 100644 --- a/board/versatile/platform.S +++ b/board/versatile/lowlevel_init.S @@ -26,8 +26,9 @@ #include <config.h> #include <version.h> -.globl platformsetup -platformsetup: +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: /* All done by Versatile's boot monitor! */ mov pc, lr diff --git a/board/versatile/split_by_variant.sh b/board/versatile/split_by_variant.sh new file mode 100755 index 00000000000..35c663e6a55 --- /dev/null +++ b/board/versatile/split_by_variant.sh @@ -0,0 +1,40 @@ +#!/bin/sh +# --------------------------------------------------------- +# Set the core module defines according to Core Module +# --------------------------------------------------------- +# --------------------------------------------------------- +# Set up the Versatile type define +# --------------------------------------------------------- +variant=PB926EJ-S +if [ "$1" == "" ] +then + echo "$0:: No parameters - using versatilepb_config" + echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h + variant=PB926EJ-S +else + case "$1" in + versatilepb_config | \ + versatile_config) + echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h + ;; + + versatileab_config) + echo "#define CONFIG_ARCH_VERSATILE_AB" > ./include/config.h + variant=AB926EJ-S + ;; + + + *) + echo "$0:: Unrecognised config - using versatilepb_config" + echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h + variant=PB926EJ-S + ;; + + esac + +fi +# --------------------------------------------------------- +# Complete the configuration +# --------------------------------------------------------- +./mkconfig -a versatile arm arm926ejs versatile +echo "Variant:: $variant" diff --git a/board/voiceblue/setup.S b/board/voiceblue/setup.S index 4a110e846dc..dcf37b5dce5 100644 --- a/board/voiceblue/setup.S +++ b/board/voiceblue/setup.S @@ -122,8 +122,8 @@ MUX_CONFIG_OFFSETS: .byte 0x0c @ COMP_MODE_CTRL_0 .byte 0xff -.globl platformsetup -platformsetup: +.globl lowlevel_init +lowlevel_init: /* Improve performance a bit... */ mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register diff --git a/common/Makefile b/common/Makefile index 6366e0226a9..7dbf84a555e 100644 --- a/common/Makefile +++ b/common/Makefile @@ -46,7 +46,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \ env_nand.o env_dataflash.o env_flash.o env_eeprom.o \ env_nvram.o env_nowhere.o \ exports.o \ - flash.o fpga.o \ + flash.o fpga.o ft_build.o \ hush.o kgdb.o lcd.o lists.o lynxkdi.o \ memsize.o miiphybb.o miiphyutil.o \ s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \ diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index ab6ccbb07cb..ee1b5c1c242 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -34,6 +34,10 @@ #include <environment.h> #include <asm/byteorder.h> +#ifdef CONFIG_OF_FLAT_TREE +#include <ft_build.h> +#endif + /*cmd_boot.c*/ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); @@ -489,6 +493,11 @@ fixup_silent_linux () } #endif /* CONFIG_SILENT_CONSOLE */ +#ifdef CONFIG_OF_FLAT_TREE +extern const unsigned char oftree_dtb[]; +extern const unsigned int oftree_dtb_len; +#endif + #ifdef CONFIG_PPC static void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, @@ -511,6 +520,9 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, bd_t *kbd; void (*kernel)(bd_t *, ulong, ulong, ulong, ulong); image_header_t *hdr = &header; +#ifdef CONFIG_OF_FLAT_TREE + char *of_flat_tree; +#endif if ((s = getenv ("initrd_high")) != NULL) { /* a value of "no" or a similar string will act like 0, @@ -776,15 +788,26 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, initrd_end = 0; } +#ifdef CONFIG_OF_FLAT_TREE + if (initrd_start == 0) + of_flat_tree = (char *)(((ulong)kbd - OF_FLAT_TREE_MAX_SIZE - + sizeof(bd_t)) & ~0xF); + else + of_flat_tree = (char *)((initrd_start - OF_FLAT_TREE_MAX_SIZE - + sizeof(bd_t)) & ~0xF); +#endif debug ("## Transferring control to Linux (at address %08lx) ...\n", (ulong)kernel); SHOW_BOOT_PROGRESS (15); +#ifndef CONFIG_OF_FLAT_TREE + #if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) unlock_ram_in_cache(); #endif + /* * Linux Kernel Parameters: * r3: ptr to board info data @@ -794,6 +817,25 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, * r7: End of command line string */ (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); + +#else + ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd); + /* ft_dump_blob(of_flat_tree); */ + +#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) + unlock_ram_in_cache(); +#endif + /* + * Linux Kernel Parameters: + * r3: ptr to OF flat tree, followed by the board info data + * r4: initrd_start or 0 if no initrd + * r5: initrd_end - unused if r4 is 0 + * r6: Start of command line string + * r7: End of command line string + */ + (*kernel) ((bd_t *)of_flat_tree, initrd_start, initrd_end, cmd_start, cmd_end); + +#endif } #endif /* CONFIG_PPC */ diff --git a/common/cmd_immap.c b/common/cmd_immap.c index 9db5f2cc46c..f1b05357c8a 100644 --- a/common/cmd_immap.c +++ b/common/cmd_immap.c @@ -318,11 +318,20 @@ int do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { uint rcode = 0; + iopin_t iopin; static uint port = 0; static uint pin = 0; static uint value = 0; - static enum { DIR, PAR, SOR, ODR, DAT, INT } cmd = DAT; - iopin_t iopin; + static enum { + DIR, + PAR, + SOR, + ODR, + DAT, +#if defined(CONFIG_8xx) + INT +#endif + } cmd = DAT; if (argc != 5) { puts ("iopset PORT PIN CMD VALUE\n"); diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c index 7fa5ddcac6c..85a48491b35 100644 --- a/cpu/arm1136/cpu.c +++ b/cpu/arm1136/cpu.c @@ -33,7 +33,9 @@ #include <common.h> #include <command.h> +#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) #include <asm/arch/omap2420.h> +#endif /* read co-processor 15, register #1 (control register) */ static unsigned long read_p15_c1 (void) diff --git a/cpu/arm1136/interrupts.c b/cpu/arm1136/interrupts.c index 23236dcb0ff..1dc36d0344f 100644 --- a/cpu/arm1136/interrupts.c +++ b/cpu/arm1136/interrupts.c @@ -32,7 +32,11 @@ #include <common.h> #include <asm/arch/bits.h> -#include <asm/arch/omap2420.h> + +#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) +# include <asm/arch/omap2420.h> +#endif + #include <asm/proc-armv/ptrace.h> #define TIMER_LOAD_VAL 0 @@ -172,6 +176,10 @@ void do_irq (struct pt_regs *pt_regs) bad_mode (); } +#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR) +/* Use the IntegratorCP function from board/integratorcp.c */ +#else + static ulong timestamp; static ulong lastinc; @@ -189,7 +197,6 @@ int interrupt_init (void) return(0); } - /* * timer without interrupts */ @@ -281,7 +288,6 @@ unsigned long long get_ticks(void) { return get_timer(0); } - /* * This function is derived from PowerPC code (timebase clock frequency). * On ARM it returns the number of timer ticks per second. @@ -292,3 +298,4 @@ ulong get_tbclk (void) tbclk = CFG_HZ; return tbclk; } +#endif /* !Integrator/CP */ diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index c3bf6e37e1c..17c7a834919 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -30,8 +30,9 @@ #include <config.h> #include <version.h> +#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) #include <asm/arch/omap2420.h> - +#endif .globl _start _start: b reset ldr pc, _undefined_instruction @@ -210,7 +211,7 @@ cpu_init_crit: * basic memory. Go here to bump up clock rate and handle wake up conditions. */ mov ip, lr /* persevere link reg across call */ - bl platformsetup /* go setup pll,mux,memory */ + bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ /* @@ -397,6 +398,10 @@ arm1136_cache_flush: mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache mov pc, lr @ back to caller +#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR) +/* Use the IntegratorCP function from board/integratorcp/platform.S */ +#else + .align 5 .globl reset_cpu reset_cpu: @@ -408,3 +413,5 @@ _loop_forever: b _loop_forever rstctl: .word PM_RSTCTRL_WKUP + +#endif diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index fcca360732b..a5b6de76055 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -76,6 +76,8 @@ int cleanup_before_linux (void) #elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) disable_interrupts (); /* Nothing more needed */ +#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) + /* No cleanup before linux for IntegratorAP/CM720T as yet */ #else #error No cleanup_before_linux() defined for this CPU type #endif @@ -245,6 +247,11 @@ int dcache_status (void) return icache_status(); } +#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) + /* No specific cache setup for IntegratorAP/CM720T as yet */ + void icache_enable (void) + { + } #else #error No icache/dcache enable/disable functions defined for this CPU type #endif diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c index d0eaca5e027..da62502d614 100644 --- a/cpu/arm720t/interrupts.c +++ b/cpu/arm720t/interrupts.c @@ -193,6 +193,8 @@ void do_irq (struct pt_regs *pt_regs) /* clear pending interrupt */ PUT_REG( REG_INTPEND, (1<<(pending>>2))); } +#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) + /* No do_irq() for IntegratorAP/CM720T as yet */ #else #error do_irq() not defined for this CPU type #endif @@ -216,6 +218,10 @@ static void timer_isr( void *data) { } #endif +#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) + /* Use IntegratorAP routines in board/integratorap.c */ +#else + static ulong timestamp; static ulong lastdec; @@ -296,6 +302,8 @@ int interrupt_init (void) return (0); } +#endif /* ! IntegratorAP */ + /* * timer without interrupts */ @@ -398,6 +406,8 @@ void udelay (unsigned long usec) } +#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) + /* No timer routines for IntegratorAP/CM720T as yet */ #else #error Timer routines not defined for this CPU type #endif diff --git a/cpu/arm720t/serial_netarm.c b/cpu/arm720t/serial_netarm.c index 5b41949e0a5..5ad98f06fdb 100644 --- a/cpu/arm720t/serial_netarm.c +++ b/cpu/arm720t/serial_netarm.c @@ -35,7 +35,11 @@ #include <asm/hardware.h> #define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA)) +#if !defined(CONFIG_NETARM_NS7520) #define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB)) +#else +#define PORTC (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTC)) +#endif /* wait until transmitter is ready for another character */ #define TXWAITRDY(registers) \ @@ -48,8 +52,13 @@ } +#ifndef CONFIG_UART1_CONSOLE volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(0); volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(1); +#else +volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(1); +volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(0); +#endif extern void _netarm_led_FAIL1(void); @@ -62,8 +71,13 @@ void serial_setbrg (void) DECLARE_GLOBAL_DATA_PTR; /* set 0 ... make sure pins are configured for serial */ +#if !defined(CONFIG_NETARM_NS7520) PORTA = PORTB = NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); +#else + PORTA = NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); + PORTC = NETARM_GEN_PORT_CSF (0xef) | NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); +#endif /* first turn em off */ serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = 0; diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S index eb26476a666..e66d109443a 100644 --- a/cpu/arm720t/start.S +++ b/cpu/arm720t/start.S @@ -272,12 +272,15 @@ cpu_init_crit: str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL] +#ifndef CONFIG_NETARM_PLL_BYPASS ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \ NETARM_GEN_PLL_CTL_POLTST_DEF | \ NETARM_GEN_PLL_CTL_INDIV(1) | \ NETARM_GEN_PLL_CTL_ICP_DEF | \ NETARM_GEN_PLL_CTL_OUTDIV(2) ) str r1, [r0, #+NETARM_GEN_PLL_CONTROL] +#endif + /* * mask all IRQs by clearing all bits in the INTMRs */ @@ -301,6 +304,8 @@ cpu_init_crit: ldr r1, =0x83ffffa0 /* cache-disabled */ str r1, [r0] +#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) + /* No specific initialisation for IntegratorAP/CM720T as yet */ #else #error No cpu_init_crit() defined for current CPU type #endif @@ -316,12 +321,12 @@ cpu_init_crit: str r1, [r0] #endif + mov ip, lr /* * before relocating, we have to setup RAM timing * because memory timing is board-dependent, you will * find a lowlevel_init.S in your board directory. */ - mov ip, lr bl lowlevel_init mov lr, ip @@ -530,6 +535,8 @@ reset_cpu: #elif defined(CONFIG_S3C4510B) /* Nothing done here as reseting the CPU is board specific, depending * on external peripherals such as watchdog timers, etc. */ +#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) + /* No specific reset actions for IntegratorAP/CM720T as yet */ #else #error No reset_cpu() defined for current CPU type #endif diff --git a/cpu/arm920t/at91rm9200/ether.c b/cpu/arm920t/at91rm9200/ether.c index bff95b6eace..ca5b7d198ce 100644 --- a/cpu/arm920t/at91rm9200/ether.c +++ b/cpu/arm920t/at91rm9200/ether.c @@ -44,21 +44,19 @@ typedef struct { #define RBF_LOCAL2 (1<<24) #define RBF_LOCAL1 (1<<23) -/* Emac Buffers in last 512KBytes of SDRAM*/ -/* Be careful, buffer size is limited to 512KBytes !!! */ -#define RBF_FRAMEMAX 100 -/*#define RBF_FRAMEMEM 0x200000 */ -#define RBF_FRAMEMEM 0x21F80000 +#define RBF_FRAMEMAX 64 #define RBF_FRAMELEN 0x600 -#define RBF_FRAMEBTD RBF_FRAMEMEM -#define RBF_FRAMEBUF (RBF_FRAMEMEM + RBF_FRAMEMAX*sizeof(rbf_t)) - - #ifdef CONFIG_DRIVER_ETHER #if (CONFIG_COMMANDS & CFG_CMD_NET) +/* alignment as per Errata #11 (64 bytes) is insufficient! */ +rbf_t rbfdt[RBF_FRAMEMAX] __attribute((aligned(512))); +rbf_t *rbfp; + +unsigned char rbf_framebuf[RBF_FRAMEMAX][RBF_FRAMELEN] __attribute((aligned(4))); + /* structure to interface the PHY */ AT91S_PhyOps PhyOps; @@ -153,9 +151,6 @@ UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac, } -rbf_t *rbfdt; -rbf_t *rbfp; - int eth_init (bd_t * bd) { int ret; @@ -188,9 +183,8 @@ int eth_init (bd_t * bd) p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */ /* Init Ehternet buffers */ - rbfdt = (rbf_t *) RBF_FRAMEBTD; for (i = 0; i < RBF_FRAMEMAX; i++) { - rbfdt[i].addr = RBF_FRAMEBUF + RBF_FRAMELEN * i; + rbfdt[i].addr = (unsigned long)rbf_framebuf[i]; rbfdt[i].size = 0; } rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index 74a97d52903..4603cf57337 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -255,7 +255,6 @@ cpu_init_crit: orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 - /* * before relocating, we have to setup RAM timing * because memory timing is board-dependend, you will @@ -264,7 +263,6 @@ cpu_init_crit: mov ip, lr bl lowlevel_init mov lr, ip - mov pc, lr diff --git a/cpu/arm925t/start.S b/cpu/arm925t/start.S index 238925936ea..acd77426d30 100644 --- a/cpu/arm925t/start.S +++ b/cpu/arm925t/start.S @@ -246,7 +246,7 @@ cpu_init_crit: * Go setup Memory and board specific bits prior to relocation. */ mov ip, lr /* perserve link reg across call */ - bl platformsetup /* go setup pll,mux,memory */ + bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ /* diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S index 5f5a1c59690..fc6b20b21e3 100644 --- a/cpu/arm926ejs/start.S +++ b/cpu/arm926ejs/start.S @@ -222,7 +222,7 @@ cpu_init_crit: * Go setup Memory and board specific bits prior to relocation. */ mov ip, lr /* perserve link reg across call */ - bl platformsetup /* go setup pll,mux,memory */ + bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ /* diff --git a/cpu/arm946es/start.S b/cpu/arm946es/start.S index ef3be8ec935..e8c908bf281 100644 --- a/cpu/arm946es/start.S +++ b/cpu/arm946es/start.S @@ -214,7 +214,7 @@ cpu_init_crit: * Go setup Memory and board specific bits prior to relocation. */ mov ip, lr /* perserve link reg across call */ - bl platformsetup /* go setup memory */ + bl lowlevel_init /* go setup memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ /* diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 469f97d6f0c..cbd7b245553 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -381,6 +381,13 @@ ulong get_OPB_freq (void) extern void get_sys_info (sys_info_t * sysInfo); extern ulong get_PCI_freq (void); +#elif defined(CONFIG_AP1000) +void get_sys_info (sys_info_t * sysInfo) { + sysInfo->freqProcessor = 240 * 1000 * 1000; + sysInfo->freqPLB = 80 * 1000 * 1000; + sysInfo->freqPCI = 33 * 1000 * 1000; +} + #elif defined(CONFIG_405) void get_sys_info (sys_info_t * sysInfo) { diff --git a/doc/README-integrator b/doc/README-integrator index 827221f1ea0..ce8a9d26ad4 100644 --- a/doc/README-integrator +++ b/doc/README-integrator @@ -62,3 +62,49 @@ of the Integrator board itself, has been placed in board/integrator<>/platform.S board/integrator<>/integrator<>.c + +Targets +======= +The U-Boot make targets map to the available core modules as below. + +Integrator/AP is no longer available from ARM. +Core modules marked ** are also no longer available. + +ap720t_config ** CM720T +ap920t_config ** CM920T +ap926ejs_config Integrator Core Module for ARM926EJ-STM +ap946es_config Integrator Core Module for ARM946E-STM +cp920t_config ** CM920T +cp926ejs_config Integrator Core Module for ARM926EJ-STM +cp946es_config Integrator Core Module for ARM946E-STM +cp1136_config Integrator Core Module ARM1136JF-S TM + +The final groups of targets are for core modules where no explicit cpu +code has yet been added to U-Boot i.e. they all use the same U-Boot binary +using the generic "arm_intcm" core: + +ap966_config Integrator Core Module for ARM966E-S TM +ap922_config Integrator Core Module for ARM922T TM with ETM +ap922_XA10_config Integrator Core Module for ARM922T using Altera Excalibur +ap7_config ** CM7TDMI +integratorap_config +ap_config + + +cp966_config Integrator Core Module for ARM966E-S TM +cp922_config Integrator Core Module for ARM922T TM with ETM +cp922_XA10_config Integrator Core Module for ARM922T using Altera Excalibur +cp1026_config Integrator Core Module ARM1026EJ-S TM +integratorcp_config +cp_config + +The Makefile targets call board/integrator<>/split_by_variant.sh +to configure various defines in include/configs/integrator<>.h +to indicate the core module & core configuration and ensure that +board/integrator<>/u-boot.lds loads the cpu object first in the U-Boot image. + +********************************* +Because of this mechanism +> make clean +must be run before each change in configuration +********************************* diff --git a/drivers/Makefile b/drivers/Makefile index 26a556e59ad..e6176ed86ae 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -34,7 +34,7 @@ OBJS = 3c589.o 5701rls.o ali512x.o \ i8042.o i82365.o inca-ip_sw.o keyboard.o \ lan91c96.o \ natsemi.o ne2000.o netarm_eth.o netconsole.o \ - ns16550.o ns8382x.o ns87308.o omap1510_i2c.o \ + ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \ omap24xx_i2c.o pci.o pci_auto.o pci_indirect.o \ pcnet.o plb2800_eth.o \ ps2ser.o ps2mult.o pc_keyb.o \ diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c index ca6bd89b0c5..d8dfb4c3223 100644 --- a/drivers/cfi_flash.c +++ b/drivers/cfi_flash.c @@ -221,7 +221,7 @@ static void flash_printqry (flash_info_t * info, flash_sect_t sect) cfiptr_t cptr; int x, y; - for (x = 0; x < 0x40; x += 16 / info->portwidth) { + for (x = 0; x < 0x40; x += 16U / info->portwidth) { cptr.cp = flash_make_addr (info, sect, x + FLASH_OFFSET_CFI_RESP); @@ -807,7 +807,7 @@ static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) #else for (i = 1; i <= info->portwidth; i++) #endif - *cp++ = (i % info->chipwidth) ? '\0' : cmd; + *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd; } /* diff --git a/drivers/e1000.c b/drivers/e1000.c index cc50c26874f..787134abf91 100644 --- a/drivers/e1000.c +++ b/drivers/e1000.c @@ -112,6 +112,7 @@ static int e1000_detect_gig_phy(struct e1000_hw *hw); readl((a)->hw_addr + E1000_##reg + ((offset) << 2))) #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);} +#ifndef CONFIG_AP1000 /* remove for warnings */ /****************************************************************************** * Raises the EEPROM's clock input. * @@ -478,6 +479,7 @@ e1000_validate_eeprom_checksum(struct eth_device *nic) return -E1000_ERR_EEPROM; } } +#endif /* #ifndef CONFIG_AP1000 */ /****************************************************************************** * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the @@ -488,6 +490,7 @@ e1000_validate_eeprom_checksum(struct eth_device *nic) static int e1000_read_mac_addr(struct eth_device *nic) { +#ifndef CONFIG_AP1000 struct e1000_hw *hw = nic->priv; uint16_t offset; uint16_t eeprom_data; @@ -509,6 +512,32 @@ e1000_read_mac_addr(struct eth_device *nic) /* Invert the last bit if this is the second device */ nic->enetaddr[5] += 1; } +#else + /* + * The AP1000's e1000 has no eeprom; the MAC address is stored in the + * environment variables. Currently this does not support the addition + * of a PMC e1000 card, which is certainly a possibility, so this should + * be updated to properly use the env variable only for the onboard e1000 + */ + + int ii; + char *s, *e; + + DEBUGFUNC(); + + s = getenv ("ethaddr"); + if (s == NULL){ + return -E1000_ERR_EEPROM; + } + else{ + for(ii = 0; ii < 6; ii++) { + nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0; + if (s){ + s = (*e) ? e + 1 : e; + } + } + } +#endif return 0; } @@ -876,6 +905,7 @@ e1000_setup_link(struct eth_device *nic) DEBUGFUNC(); +#ifndef CONFIG_AP1000 /* Read and store word 0x0F of the EEPROM. This word contains bits * that determine the hardware's default PAUSE (flow control) mode, * a bit that determines whether the HW defaults to enabling or @@ -888,6 +918,11 @@ e1000_setup_link(struct eth_device *nic) DEBUGOUT("EEPROM Read Error\n"); return -E1000_ERR_EEPROM; } +#else + /* we have to hardcode the proper value for our hardware. */ + /* this value is for the 82540EM pci card used for prototyping, and it works. */ + eeprom_data = 0xb220; +#endif if (hw->fc == e1000_fc_default) { if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) @@ -2950,12 +2985,14 @@ e1000_initialize(bd_t * bis) free(nic); return 0; } +#ifndef CONFIG_AP1000 if (e1000_validate_eeprom_checksum(nic) < 0) { printf("The EEPROM Checksum Is Not Valid\n"); free(hw); free(nic); return 0; } +#endif e1000_read_mac_addr(nic); E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA); diff --git a/drivers/ns7520_eth.c b/drivers/ns7520_eth.c new file mode 100644 index 00000000000..bcdc27fa85b --- /dev/null +++ b/drivers/ns7520_eth.c @@ -0,0 +1,849 @@ +/*********************************************************************** + * + * Copyright (C) 2005 by Videon Central, Inc. + * + * $Id$ + * @Author: Arthur Shipkowski + * @Descr: Ethernet driver for the NS7520. Uses polled Ethernet, like + * the older netarmeth driver. Note that attempting to filter + * broadcast and multicast out in the SAFR register will cause + * bad things due to released errata. + * @References: [1] NS7520 Hardware Reference, December 2003 + * [2] Intel LXT971 Datasheet #249414 Rev. 02 + * + ***********************************************************************/ + +#include <common.h> + +#if defined(CONFIG_DRIVER_NS7520_ETHERNET) + +#include <net.h> /* NetSendPacket */ +#include <asm/arch/netarm_registers.h> +#include <asm/arch/netarm_dma_module.h> + +#include "ns7520_eth.h" /* for Ethernet and PHY */ + +/** + * Send an error message to the terminal. + */ +#define ERROR(x) \ +do { \ + char *__foo = strrchr(__FILE__, '/'); \ + \ + printf("%s: %d: %s(): ", (__foo == NULL ? __FILE__ : (__foo + 1)), \ + __LINE__, __FUNCTION__); \ + printf x; printf("\n"); \ +} while (0); + +/* some definition to make transistion to linux easier */ + +#define NS7520_DRIVER_NAME "eth" +#define KERN_WARNING "Warning:" +#define KERN_ERR "Error:" +#define KERN_INFO "Info:" + +#if 1 +# define DEBUG +#endif + +#ifdef DEBUG +# define printk printf + +# define DEBUG_INIT 0x0001 +# define DEBUG_MINOR 0x0002 +# define DEBUG_RX 0x0004 +# define DEBUG_TX 0x0008 +# define DEBUG_INT 0x0010 +# define DEBUG_POLL 0x0020 +# define DEBUG_LINK 0x0040 +# define DEBUG_MII 0x0100 +# define DEBUG_MII_LOW 0x0200 +# define DEBUG_MEM 0x0400 +# define DEBUG_ERROR 0x4000 +# define DEBUG_ERROR_CRIT 0x8000 + +static int nDebugLvl = DEBUG_ERROR_CRIT; + +# define DEBUG_ARGS0( FLG, a0 ) if( ( nDebugLvl & (FLG) ) == (FLG) ) \ + printf("%s: " a0, __FUNCTION__, 0, 0, 0, 0, 0, 0 ) +# define DEBUG_ARGS1( FLG, a0, a1 ) if( ( nDebugLvl & (FLG) ) == (FLG)) \ + printf("%s: " a0, __FUNCTION__, (int)(a1), 0, 0, 0, 0, 0 ) +# define DEBUG_ARGS2( FLG, a0, a1, a2 ) if( (nDebugLvl & (FLG)) ==(FLG))\ + printf("%s: " a0, __FUNCTION__, (int)(a1), (int)(a2), 0, 0,0,0 ) +# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) if((nDebugLvl &(FLG))==(FLG))\ + printf("%s: "a0,__FUNCTION__,(int)(a1),(int)(a2),(int)(a3),0,0,0) +# define DEBUG_FN( FLG ) if( (nDebugLvl & (FLG)) == (FLG) ) \ + printf("\r%s:line %d\n", (int)__FUNCTION__, __LINE__, 0,0,0,0); +# define ASSERT( expr, func ) if( !( expr ) ) { \ + printf( "Assertion failed! %s:line %d %s\n", \ + (int)__FUNCTION__,__LINE__,(int)(#expr),0,0,0); \ + func } +#else /* DEBUG */ +# define printk(...) +# define DEBUG_ARGS0( FLG, a0 ) +# define DEBUG_ARGS1( FLG, a0, a1 ) +# define DEBUG_ARGS2( FLG, a0, a1, a2 ) +# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) +# define DEBUG_FN( n ) +# define ASSERT(expr, func) +#endif /* DEBUG */ + +#define NS7520_MII_NEG_DELAY (5*CFG_HZ) /* in s */ +#define TX_TIMEOUT (5*CFG_HZ) /* in s */ +#define RX_STALL_WORKAROUND_CNT 100 + +static int ns7520_eth_reset(void); + +static void ns7520_link_auto_negotiate(void); +static void ns7520_link_update_egcr(void); +static void ns7520_link_print_changed(void); + +/* the PHY stuff */ + +static char ns7520_mii_identify_phy(void); +static unsigned short ns7520_mii_read(unsigned short uiRegister); +static void ns7520_mii_write(unsigned short uiRegister, + unsigned short uiData); +static unsigned int ns7520_mii_get_clock_divisor(unsigned int + unMaxMDIOClk); +static unsigned int ns7520_mii_poll_busy(void); + +static unsigned int nPhyMaxMdioClock = PHY_MDIO_MAX_CLK; +static unsigned int uiLastLinkStatus; +static PhyType phyDetected = PHY_NONE; + +/*********************************************************************** + * @Function: eth_init + * @Return: -1 on failure otherwise 0 + * @Descr: Initializes the ethernet engine and uses either FS Forth's default + * MAC addr or the one in environment + ***********************************************************************/ + +int eth_init(bd_t * pbis) +{ + unsigned char aucMACAddr[6]; + char *pcTmp = getenv("ethaddr"); + char *pcEnd; + int i; + + DEBUG_FN(DEBUG_INIT); + + /* no need to check for hardware */ + + if (!ns7520_eth_reset()) + return -1; + + if (NULL == pcTmp) + return -1; + + for (i = 0; i < 6; i++) { + aucMACAddr[i] = + pcTmp ? simple_strtoul(pcTmp, &pcEnd, 16) : 0; + pcTmp = (*pcTmp) ? pcEnd + 1 : pcEnd; + } + + /* configure ethernet address */ + + *get_eth_reg_addr(NS7520_ETH_SA1) = + aucMACAddr[5] << 8 | aucMACAddr[4]; + *get_eth_reg_addr(NS7520_ETH_SA2) = + aucMACAddr[3] << 8 | aucMACAddr[2]; + *get_eth_reg_addr(NS7520_ETH_SA3) = + aucMACAddr[1] << 8 | aucMACAddr[0]; + + /* enable hardware */ + + *get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN; + *get_eth_reg_addr(NS7520_ETH_SUPP) = NS7520_ETH_SUPP_JABBER; + *get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN; + + /* the linux kernel may give packets < 60 bytes, for example arp */ + *get_eth_reg_addr(NS7520_ETH_MAC2) = NS7520_ETH_MAC2_CRCEN | + NS7520_ETH_MAC2_PADEN | NS7520_ETH_MAC2_HUGE; + + /* Broadcast/multicast allowed; if you don't set this even unicast chokes */ + /* Based on NS7520 errata documentation */ + *get_eth_reg_addr(NS7520_ETH_SAFR) = + NS7520_ETH_SAFR_BROAD | NS7520_ETH_SAFR_PRM; + + /* enable receive and transmit FIFO, use 10/100 Mbps MII */ + *get_eth_reg_addr(NS7520_ETH_EGCR) |= + NS7520_ETH_EGCR_ETXWM_75 | + NS7520_ETH_EGCR_ERX | + NS7520_ETH_EGCR_ERXREG | + NS7520_ETH_EGCR_ERXBR | NS7520_ETH_EGCR_ETX; + + return 0; +} + +/*********************************************************************** + * @Function: eth_send + * @Return: -1 on timeout otherwise 1 + * @Descr: sends one frame by DMA + ***********************************************************************/ + +int eth_send(volatile void *pPacket, int nLen) +{ + int i, length32, retval = 1; + char *pa; + unsigned int *pa32, lastp = 0, rest; + unsigned int status; + + pa = (char *) pPacket; + pa32 = (unsigned int *) pPacket; + length32 = nLen / 4; + rest = nLen % 4; + + /* make sure there's no garbage in the last word */ + switch (rest) { + case 0: + lastp = pa32[length32 - 1]; + length32--; + break; + case 1: + lastp = pa32[length32] & 0x000000ff; + break; + case 2: + lastp = pa32[length32] & 0x0000ffff; + break; + case 3: + lastp = pa32[length32] & 0x00ffffff; + break; + } + + while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) & + NS7520_ETH_EGSR_TXREGE) + == 0) { + } + + /* write to the fifo */ + for (i = 0; i < length32; i++) + *get_eth_reg_addr(NS7520_ETH_FIFO) = pa32[i]; + + /* the last word is written to an extra register, this + starts the transmission */ + *get_eth_reg_addr(NS7520_ETH_FIFOL) = lastp; + + /* Wait for it to be done */ + while ((*get_eth_reg_addr(NS7520_ETH_EGSR) & NS7520_ETH_EGSR_TXBC) + == 0) { + } + status = (*get_eth_reg_addr(NS7520_ETH_ETSR)); + *get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_TXBC; /* Clear it now */ + + if (status & NS7520_ETH_ETSR_TXOK) { + retval = 0; /* We're OK! */ + } else if (status & NS7520_ETH_ETSR_TXDEF) { + printf("Deferred, we'll see.\n"); + retval = 0; + } else if (status & NS7520_ETH_ETSR_TXAL) { + printf("Late collision error, %d collisions.\n", + (*get_eth_reg_addr(NS7520_ETH_ETSR)) & + NS7520_ETH_ETSR_TXCOLC); + } else if (status & NS7520_ETH_ETSR_TXAEC) { + printf("Excessive collisions: %d\n", + (*get_eth_reg_addr(NS7520_ETH_ETSR)) & + NS7520_ETH_ETSR_TXCOLC); + } else if (status & NS7520_ETH_ETSR_TXAED) { + printf("Excessive deferral on xmit.\n"); + } else if (status & NS7520_ETH_ETSR_TXAUR) { + printf("Packet underrun.\n"); + } else if (status & NS7520_ETH_ETSR_TXAJ) { + printf("Jumbo packet error.\n"); + } else { + printf("Error: Should never get here.\n"); + } + + return (retval); +} + +/*********************************************************************** + * @Function: eth_rx + * @Return: size of last frame in bytes or 0 if no frame available + * @Descr: gives one frame to U-Boot which has been copied by DMA engine already + * to NetRxPackets[ 0 ]. + ***********************************************************************/ + +int eth_rx(void) +{ + int i; + unsigned short rxlen; + unsigned short totrxlen = 0; + unsigned int *addr; + unsigned int rxstatus, lastrxlen; + char *pa; + + /* If RXBR is 1, data block was received */ + while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) & + NS7520_ETH_EGSR_RXBR) == NS7520_ETH_EGSR_RXBR) { + + /* get status register and the length of received block */ + rxstatus = *get_eth_reg_addr(NS7520_ETH_ERSR); + rxlen = (rxstatus & NS7520_ETH_ERSR_RXSIZE) >> 16; + + /* clear RXBR to make fifo available */ + *get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_RXBR; + + if (rxstatus & NS7520_ETH_ERSR_ROVER) { + printf("Receive overrun, resetting FIFO.\n"); + *get_eth_reg_addr(NS7520_ETH_EGCR) &= + ~NS7520_ETH_EGCR_ERX; + udelay(20); + *get_eth_reg_addr(NS7520_ETH_EGCR) |= + NS7520_ETH_EGCR_ERX; + } + if (rxlen == 0) { + printf("Nothing.\n"); + return 0; + } + + addr = (unsigned int *) NetRxPackets[0]; + pa = (char *) NetRxPackets[0]; + + /* read the fifo */ + for (i = 0; i < rxlen / 4; i++) { + *addr = *get_eth_reg_addr(NS7520_ETH_FIFO); + addr++; + } + + if ((*get_eth_reg_addr(NS7520_ETH_EGSR)) & + NS7520_ETH_EGSR_RXREGR) { + /* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */ + lastrxlen = + ((*get_eth_reg_addr(NS7520_ETH_EGSR)) & + NS7520_ETH_EGSR_RXFDB_MA) >> 28; + *addr = *get_eth_reg_addr(NS7520_ETH_FIFO); + switch (lastrxlen) { + case 1: + *addr &= 0xff000000; + break; + case 2: + *addr &= 0xffff0000; + break; + case 3: + *addr &= 0xffffff00; + break; + } + } + + /* Pass the packet up to the protocol layers. */ + NetReceive(NetRxPackets[0], rxlen - 4); + totrxlen += rxlen - 4; + } + + return totrxlen; +} + +/*********************************************************************** + * @Function: eth_halt + * @Return: n/a + * @Descr: stops the ethernet engine + ***********************************************************************/ + +void eth_halt(void) +{ + DEBUG_FN(DEBUG_INIT); + + *get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_RXEN; + *get_eth_reg_addr(NS7520_ETH_EGCR) &= ~(NS7520_ETH_EGCR_ERX | + NS7520_ETH_EGCR_ERXDMA | + NS7520_ETH_EGCR_ERXREG | + NS7520_ETH_EGCR_ERXBR | + NS7520_ETH_EGCR_ETX | + NS7520_ETH_EGCR_ETXDMA); +} + +/*********************************************************************** + * @Function: ns7520_eth_reset + * @Return: 0 on failure otherwise 1 + * @Descr: resets the ethernet interface and the PHY, + * performs auto negotiation or fixed modes + ***********************************************************************/ + +static int ns7520_eth_reset(void) +{ + DEBUG_FN(DEBUG_MINOR); + + /* Reset important registers */ + *get_eth_reg_addr(NS7520_ETH_EGCR) = 0; /* Null it out! */ + *get_eth_reg_addr(NS7520_ETH_MAC1) &= NS7520_ETH_MAC1_SRST; + *get_eth_reg_addr(NS7520_ETH_MAC2) = 0; + /* Reset MAC */ + *get_eth_reg_addr(NS7520_ETH_EGCR) |= NS7520_ETH_EGCR_MAC_RES; + udelay(5); + *get_eth_reg_addr(NS7520_ETH_EGCR) &= ~NS7520_ETH_EGCR_MAC_RES; + + /* reset and initialize PHY */ + + *get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_SRST; + + /* we don't support hot plugging of PHY, therefore we don't reset + phyDetected and nPhyMaxMdioClock here. The risk is if the setting is + incorrect the first open + may detect the PHY correctly but succeding will fail + For reseting the PHY and identifying we have to use the standard + MDIO CLOCK value 2.5 MHz only after hardware reset + After having identified the PHY we will do faster */ + + *get_eth_reg_addr(NS7520_ETH_MCFG) = + ns7520_mii_get_clock_divisor(nPhyMaxMdioClock); + + /* reset PHY */ + ns7520_mii_write(PHY_COMMON_CTRL, PHY_COMMON_CTRL_RESET); + ns7520_mii_write(PHY_COMMON_CTRL, 0); + + udelay(3000); /* [2] p.70 says at least 300us reset recovery time. */ + + /* MII clock has been setup to default, ns7520_mii_identify_phy should + work for all */ + + if (!ns7520_mii_identify_phy()) { + printk(KERN_ERR NS7520_DRIVER_NAME + ": Unsupported PHY, aborting\n"); + return 0; + } + + /* now take the highest MDIO clock possible after detection */ + *get_eth_reg_addr(NS7520_ETH_MCFG) = + ns7520_mii_get_clock_divisor(nPhyMaxMdioClock); + + /* PHY has been detected, so there can be no abort reason and we can + finish initializing ethernet */ + + uiLastLinkStatus = 0xff; /* undefined */ + + ns7520_link_auto_negotiate(); + + if (phyDetected == PHY_LXT971A) + /* set LED2 to link mode */ + ns7520_mii_write(PHY_LXT971_LED_CFG, + (PHY_LXT971_LED_CFG_LINK_ACT << + PHY_LXT971_LED_CFG_SHIFT_LED2) | + (PHY_LXT971_LED_CFG_TRANSMIT << + PHY_LXT971_LED_CFG_SHIFT_LED1)); + + return 1; +} + +/*********************************************************************** + * @Function: ns7520_link_auto_negotiate + * @Return: void + * @Descr: performs auto-negotation of link. + ***********************************************************************/ + +static void ns7520_link_auto_negotiate(void) +{ + unsigned long ulStartJiffies; + unsigned short uiStatus; + + DEBUG_FN(DEBUG_LINK); + + /* run auto-negotation */ + /* define what we are capable of */ + ns7520_mii_write(PHY_COMMON_AUTO_ADV, + PHY_COMMON_AUTO_ADV_100BTXFD | + PHY_COMMON_AUTO_ADV_100BTX | + PHY_COMMON_AUTO_ADV_10BTFD | + PHY_COMMON_AUTO_ADV_10BT | + PHY_COMMON_AUTO_ADV_802_3); + /* start auto-negotiation */ + ns7520_mii_write(PHY_COMMON_CTRL, + PHY_COMMON_CTRL_AUTO_NEG | + PHY_COMMON_CTRL_RES_AUTO); + + /* wait for completion */ + + ulStartJiffies = get_timer(0); + while (get_timer(0) < ulStartJiffies + NS7520_MII_NEG_DELAY) { + uiStatus = ns7520_mii_read(PHY_COMMON_STAT); + if ((uiStatus & + (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) + == + (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) { + /* lucky we are, auto-negotiation succeeded */ + ns7520_link_print_changed(); + ns7520_link_update_egcr(); + return; + } + } + + DEBUG_ARGS0(DEBUG_LINK, "auto-negotiation timed out\n"); + /* ignore invalid link settings */ +} + +/*********************************************************************** + * @Function: ns7520_link_update_egcr + * @Return: void + * @Descr: updates the EGCR and MAC2 link status after mode change or + * auto-negotation + ***********************************************************************/ + +static void ns7520_link_update_egcr(void) +{ + unsigned int unEGCR; + unsigned int unMAC2; + unsigned int unIPGT; + + DEBUG_FN(DEBUG_LINK); + + unEGCR = *get_eth_reg_addr(NS7520_ETH_EGCR); + unMAC2 = *get_eth_reg_addr(NS7520_ETH_MAC2); + unIPGT = + *get_eth_reg_addr(NS7520_ETH_IPGT) & ~NS7520_ETH_IPGT_IPGT; + + unEGCR &= ~NS7520_ETH_EGCR_EFULLD; + unMAC2 &= ~NS7520_ETH_MAC2_FULLD; + if ((uiLastLinkStatus & PHY_LXT971_STAT2_DUPLEX_MODE) + == PHY_LXT971_STAT2_DUPLEX_MODE) { + unEGCR |= NS7520_ETH_EGCR_EFULLD; + unMAC2 |= NS7520_ETH_MAC2_FULLD; + unIPGT |= 0x15; /* see [1] p. 167 */ + } else + unIPGT |= 0x12; /* see [1] p. 167 */ + + *get_eth_reg_addr(NS7520_ETH_MAC2) = unMAC2; + *get_eth_reg_addr(NS7520_ETH_EGCR) = unEGCR; + *get_eth_reg_addr(NS7520_ETH_IPGT) = unIPGT; +} + +/*********************************************************************** + * @Function: ns7520_link_print_changed + * @Return: void + * @Descr: checks whether the link status has changed and if so prints + * the new mode + ***********************************************************************/ + +static void ns7520_link_print_changed(void) +{ + unsigned short uiStatus; + unsigned short uiControl; + + DEBUG_FN(DEBUG_LINK); + + uiControl = ns7520_mii_read(PHY_COMMON_CTRL); + + if ((uiControl & PHY_COMMON_CTRL_AUTO_NEG) == + PHY_COMMON_CTRL_AUTO_NEG) { + /* PHY_COMMON_STAT_LNK_STAT is only set on autonegotiation */ + uiStatus = ns7520_mii_read(PHY_COMMON_STAT); + + if (!(uiStatus & PHY_COMMON_STAT_LNK_STAT)) { + printk(KERN_WARNING NS7520_DRIVER_NAME + ": link down\n"); + /* @TODO Linux: carrier_off */ + } else { + /* @TODO Linux: carrier_on */ + if (phyDetected == PHY_LXT971A) { + uiStatus = + ns7520_mii_read(PHY_LXT971_STAT2); + uiStatus &= + (PHY_LXT971_STAT2_100BTX | + PHY_LXT971_STAT2_DUPLEX_MODE | + PHY_LXT971_STAT2_AUTO_NEG); + + /* mask out all uninteresting parts */ + } + /* other PHYs must store there link information in + uiStatus as PHY_LXT971 */ + } + } else { + /* mode has been forced, so uiStatus should be the same as the + last link status, enforce printing */ + uiStatus = uiLastLinkStatus; + uiLastLinkStatus = 0xff; + } + + if (uiStatus != uiLastLinkStatus) { + /* save current link status */ + uiLastLinkStatus = uiStatus; + + /* print new link status */ + + printk(KERN_INFO NS7520_DRIVER_NAME + ": link mode %i Mbps %s duplex %s\n", + (uiStatus & PHY_LXT971_STAT2_100BTX) ? 100 : 10, + (uiStatus & PHY_LXT971_STAT2_DUPLEX_MODE) ? "full" : + "half", + (uiStatus & PHY_LXT971_STAT2_AUTO_NEG) ? "(auto)" : + ""); + } +} + +/*********************************************************************** + * the MII low level stuff + ***********************************************************************/ + +/*********************************************************************** + * @Function: ns7520_mii_identify_phy + * @Return: 1 if supported PHY has been detected otherwise 0 + * @Descr: checks for supported PHY and prints the IDs. + ***********************************************************************/ + +static char ns7520_mii_identify_phy(void) +{ + unsigned short uiID1; + unsigned short uiID2; + unsigned char *szName; + char cRes = 0; + + DEBUG_FN(DEBUG_MII); + + phyDetected = (PhyType) uiID1 = ns7520_mii_read(PHY_COMMON_ID1); + + switch (phyDetected) { + case PHY_LXT971A: + szName = "LXT971A"; + uiID2 = ns7520_mii_read(PHY_COMMON_ID2); + nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK; + cRes = 1; + break; + case PHY_NONE: + default: + /* in case uiID1 == 0 && uiID2 == 0 we may have the wrong + address or reset sets the wrong NS7520_ETH_MCFG_CLKS */ + + uiID2 = 0; + szName = "unknown"; + nPhyMaxMdioClock = PHY_MDIO_MAX_CLK; + phyDetected = PHY_NONE; + } + + printk(KERN_INFO NS7520_DRIVER_NAME + ": PHY (0x%x, 0x%x) = %s detected\n", uiID1, uiID2, szName); + + return cRes; +} + +/*********************************************************************** + * @Function: ns7520_mii_read + * @Return: the data read from PHY register uiRegister + * @Descr: the data read may be invalid if timed out. If so, a message + * is printed but the invalid data is returned. + * The fixed device address is being used. + ***********************************************************************/ + +static unsigned short ns7520_mii_read(unsigned short uiRegister) +{ + DEBUG_FN(DEBUG_MII_LOW); + + /* write MII register to be read */ + *get_eth_reg_addr(NS7520_ETH_MADR) = + CONFIG_PHY_ADDR << 8 | uiRegister; + + *get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ; + + if (!ns7520_mii_poll_busy()) + printk(KERN_WARNING NS7520_DRIVER_NAME + ": MII still busy in read\n"); + /* continue to read */ + + *get_eth_reg_addr(NS7520_ETH_MCMD) = 0; + + return (unsigned short) (*get_eth_reg_addr(NS7520_ETH_MRDD)); +} + +/*********************************************************************** + * @Function: ns7520_mii_write + * @Return: nothing + * @Descr: writes the data to the PHY register. In case of a timeout, + * no special handling is performed but a message printed + * The fixed device address is being used. + ***********************************************************************/ + +static void ns7520_mii_write(unsigned short uiRegister, + unsigned short uiData) +{ + DEBUG_FN(DEBUG_MII_LOW); + + /* write MII register to be written */ + *get_eth_reg_addr(NS7520_ETH_MADR) = + CONFIG_PHY_ADDR << 8 | uiRegister; + + *get_eth_reg_addr(NS7520_ETH_MWTD) = uiData; + + if (!ns7520_mii_poll_busy()) { + printf(KERN_WARNING NS7520_DRIVER_NAME + ": MII still busy in write\n"); + } +} + +/*********************************************************************** + * @Function: ns7520_mii_get_clock_divisor + * @Return: the clock divisor that should be used in NS7520_ETH_MCFG_CLKS + * @Descr: if no clock divisor can be calculated for the + * current SYSCLK and the maximum MDIO Clock, a warning is printed + * and the greatest divisor is taken + ***********************************************************************/ + +static unsigned int ns7520_mii_get_clock_divisor(unsigned int unMaxMDIOClk) +{ + struct { + unsigned int unSysClkDivisor; + unsigned int unClks; /* field for NS7520_ETH_MCFG_CLKS */ + } PHYClockDivisors[] = { + { + 4, NS7520_ETH_MCFG_CLKS_4}, { + 6, NS7520_ETH_MCFG_CLKS_6}, { + 8, NS7520_ETH_MCFG_CLKS_8}, { + 10, NS7520_ETH_MCFG_CLKS_10}, { + 14, NS7520_ETH_MCFG_CLKS_14}, { + 20, NS7520_ETH_MCFG_CLKS_20}, { + 28, NS7520_ETH_MCFG_CLKS_28} + }; + + int nIndexSysClkDiv; + int nArraySize = + sizeof(PHYClockDivisors) / sizeof(PHYClockDivisors[0]); + unsigned int unClks = NS7520_ETH_MCFG_CLKS_28; /* defaults to + greatest div */ + + DEBUG_FN(DEBUG_INIT); + + for (nIndexSysClkDiv = 0; nIndexSysClkDiv < nArraySize; + nIndexSysClkDiv++) { + /* find first sysclock divisor that isn't higher than 2.5 MHz + clock */ + if (NETARM_XTAL_FREQ / + PHYClockDivisors[nIndexSysClkDiv].unSysClkDivisor <= + unMaxMDIOClk) { + unClks = PHYClockDivisors[nIndexSysClkDiv].unClks; + break; + } + } + + DEBUG_ARGS2(DEBUG_INIT, + "Taking MDIO Clock bit mask 0x%0x for max clock %i\n", + unClks, unMaxMDIOClk); + + /* return greatest divisor */ + return unClks; +} + +/*********************************************************************** + * @Function: ns7520_mii_poll_busy + * @Return: 0 if timed out otherwise the remaing timeout + * @Descr: waits until the MII has completed a command or it times out + * code may be interrupted by hard interrupts. + * It is not checked what happens on multiple actions when + * the first is still being busy and we timeout. + ***********************************************************************/ + +static unsigned int ns7520_mii_poll_busy(void) +{ + unsigned int unTimeout = 1000; + + DEBUG_FN(DEBUG_MII_LOW); + + while (((*get_eth_reg_addr(NS7520_ETH_MIND) & NS7520_ETH_MIND_BUSY) + == NS7520_ETH_MIND_BUSY) && unTimeout) + unTimeout--; + + return unTimeout; +} + +/* ---------------------------------------------------------------------------- + * Net+ARM ethernet MII functionality. + */ +#if defined(CONFIG_MII) + +/** + * Maximum MII address we support + */ +#define MII_ADDRESS_MAX (31) + +/** + * Maximum MII register address we support + */ +#define MII_REGISTER_MAX (31) + +/** + * Ethernet MII interface return values for public functions. + */ +enum mii_status { + MII_STATUS_SUCCESS = 0, + MII_STATUS_FAILURE = 1, +}; + +/** + * Read a 16-bit value from an MII register. + */ +extern int miiphy_read(unsigned char const addr, unsigned char const reg, + unsigned short *const value) +{ + int ret = MII_STATUS_FAILURE; + + /* Parameter checks */ + if (addr > MII_ADDRESS_MAX) { + ERROR(("invalid addr, 0x%02X", addr)); + goto miiphy_read_failed_0; + } + + if (reg > MII_REGISTER_MAX) { + ERROR(("invalid reg, 0x%02X", reg)); + goto miiphy_read_failed_0; + } + + if (value == NULL) { + ERROR(("NULL value")); + goto miiphy_read_failed_0; + } + + DEBUG_FN(DEBUG_MII_LOW); + + /* write MII register to be read */ + *get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg; + + *get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ; + + if (!ns7520_mii_poll_busy()) + printk(KERN_WARNING NS7520_DRIVER_NAME + ": MII still busy in read\n"); + /* continue to read */ + + *get_eth_reg_addr(NS7520_ETH_MCMD) = 0; + + *value = (*get_eth_reg_addr(NS7520_ETH_MRDD)); + ret = MII_STATUS_SUCCESS; + /* Fall through */ + + miiphy_read_failed_0: + return (ret); +} + +/** + * Write a 16-bit value to an MII register. + */ +extern int miiphy_write(unsigned char const addr, unsigned char const reg, + unsigned short const value) +{ + int ret = MII_STATUS_FAILURE; + + /* Parameter checks */ + if (addr > MII_ADDRESS_MAX) { + ERROR(("invalid addr, 0x%02X", addr)); + goto miiphy_write_failed_0; + } + + if (reg > MII_REGISTER_MAX) { + ERROR(("invalid reg, 0x%02X", reg)); + goto miiphy_write_failed_0; + } + + /* write MII register to be written */ + *get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg; + + *get_eth_reg_addr(NS7520_ETH_MWTD) = value; + + if (!ns7520_mii_poll_busy()) { + printf(KERN_WARNING NS7520_DRIVER_NAME + ": MII still busy in write\n"); + } + + ret = MII_STATUS_SUCCESS; + /* Fall through */ + + miiphy_write_failed_0: + return (ret); +} +#endif /* defined(CONFIG_MII) */ +#endif /* CONFIG_DRIVER_NS7520_ETHERNET */ diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-arm1136/omap2420.h index 7a7aae6b0e1..d833035a4b3 100644 --- a/include/asm-arm/arch-arm1136/omap2420.h +++ b/include/asm-arm/arch-arm1136/omap2420.h @@ -35,7 +35,7 @@ #define A_REQINFOPERM0 0x68005048 #define A_READPERM0 0x68005050 #define A_WRITEPERM0 0x68005058 -#define GP_DEVICE (BIT8|BIT9) +/* #define GP_DEVICE (BIT8|BIT9) FIXME -- commented out to make compile -- FIXME */ /* L3 Firewall */ #define A_REQINFOPERM0 0x68005048 diff --git a/include/asm-arm/arch-arm720t/hardware.h b/include/asm-arm/arch-arm720t/hardware.h index 9404acd4553..3056ca7f673 100644 --- a/include/asm-arm/arch-arm720t/hardware.h +++ b/include/asm-arm/arch-arm720t/hardware.h @@ -34,6 +34,8 @@ /* include EP7312 specific hardware file if there was one */ #elif defined(CONFIG_ARMADILLO) /* include armadillo specific hardware file if there was one */ +#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) +/* include IntegratorCP/CM720T specific hardware file if there was one */ #else #error No hardware file defined for this configuration #endif diff --git a/include/asm-arm/arch-arm720t/netarm_gen_module.h b/include/asm-arm/arch-arm720t/netarm_gen_module.h index 90d9da81746..13656a3ad2b 100644 --- a/include/asm-arm/arch-arm720t/netarm_gen_module.h +++ b/include/asm-arm/arch-arm720t/netarm_gen_module.h @@ -1,6 +1,9 @@ /* * include/asm-armnommu/arch-netarm/netarm_gen_module.h * + * Copyright (C) 2005 + * Art Shipkowski, Videon Central, Inc., <art@videon-central.com> + * * Copyright (C) 2000, 2001 NETsilicon, Inc. * Copyright (C) 2000, 2001 Red Hat, Inc. * @@ -27,6 +30,8 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * * author(s) : Joe deBlaquiere + * + * Modified to support NS7520 by Art Shipkowski. */ #ifndef __NETARM_GEN_MODULE_REGISTERS_H @@ -49,7 +54,9 @@ #define NETARM_GEN_TIMER2_STATUS (0x1c) #define NETARM_GEN_PORTA (0x20) +#ifndef CONFIG_NETARM_NS7520 #define NETARM_GEN_PORTB (0x24) +#endif #define NETARM_GEN_PORTC (0x28) #define NETARM_GEN_INTR_ENABLE (0x30) @@ -128,8 +135,14 @@ /* PORT C Register ( 0xFFB0_0028 ) */ +#ifndef CONFIG_NETARM_NS7520 #define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00)) #define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00)) +#else +#define NETARM_GEN_PORT_MODE(x) ((x)<<24) +#define NETARM_GEN_PORT_DIR(x) ((x)<<16) +#define NETARM_GEN_PORT_CSF(x) ((x)<<8) +#endif /* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */ @@ -143,10 +156,15 @@ #define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF) #define NETARM_GEN_TSTAT_INTPEN (0x40000000) +#if ~defined(CONFIG_NETARM_NS7520) #define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF) +#else +#define NETARM_GEN_TSTAT_CTC_MASK (0x0FFFFFFF) +#endif /* prescale to msecs conversion */ +#if !defined(CONFIG_NETARM_PLL_BYPASS) #define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \ NETARM_GEN_TSTAT_CTC_MASK ) + \ 1 ) ) / (NETARM_XTAL_FREQ/1000) ) @@ -155,9 +173,7 @@ NETARM_GEN_TSTAT_CTC_MASK ) | \ NETARM_GEN_TCTL_USE_PRESCALE ) -#if 0 -/* ifdef CONFIG_NETARM_PLL_BYPASS else */ -#error test +#else #define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \ NETARM_GEN_TSTAT_CTC_MASK ) + \ 1 ) ) / (NETARM_XTAL_FREQ/1000) ) diff --git a/include/asm-arm/arch-arm720t/netarm_mem_module.h b/include/asm-arm/arch-arm720t/netarm_mem_module.h index 7c63d176a99..f0529fd09b7 100644 --- a/include/asm-arm/arch-arm720t/netarm_mem_module.h +++ b/include/asm-arm/arch-arm720t/netarm_mem_module.h @@ -1,6 +1,9 @@ /* * include/asm-armnommu/arch-netarm/netarm_mem_module.h * + * Copyright (C) 2005 + * Art Shipkowski, Videon Central, Inc., <art@videon-central.com> + * * Copyright (C) 2000, 2001 NETsilicon, Inc. * Copyright (C) 2000, 2001 Red Hat, Inc. * @@ -27,6 +30,8 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * * author(s) : Joe deBlaquiere + * + * Modified to support NS7520 by Art Shipkowski. */ #ifndef __NETARM_MEM_MODULE_REGISTERS_H @@ -154,4 +159,26 @@ #define NETARM_MEM_OPT_WRITE_ASYNC (0x00000000) #define NETARM_MEM_OPT_WRITE_SYNC (0x00000001) +#ifdef CONFIG_NETARM_NS7520 +/* The NS7520 has a second options register for each chip select */ +#define NETARM_MEM_CS0_OPTIONS_B (0x18) +#define NETARM_MEM_CS1_OPTIONS_B (0x28) +#define NETARM_MEM_CS2_OPTIONS_B (0x38) +#define NETARM_MEM_CS3_OPTIONS_B (0x48) +#define NETARM_MEM_CS4_OPTIONS_B (0x58) + +/* Option B Registers (0xFFC0_00x8) */ +#define NETARM_MEM_OPTB_SYNC_1_STAGE (0x00000001) +#define NETARM_MEM_OPTB_SYNC_2_STAGE (0x00000002) +#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000) +#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004) +#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008) +#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C) + +#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000) +#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010) +#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020) +#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030) +#endif + #endif diff --git a/include/asm-arm/arch-arm720t/netarm_registers.h b/include/asm-arm/arch-arm720t/netarm_registers.h index 029c7f4c74e..fa8812879a5 100644 --- a/include/asm-arm/arch-arm720t/netarm_registers.h +++ b/include/asm-arm/arch-arm720t/netarm_registers.h @@ -1,6 +1,9 @@ /* * linux/include/asm-arm/arch-netarm/netarm_registers.h * + * Copyright (C) 2005 + * Art Shipkowski, Videon Central, Inc., <art@videon-central.com> + * * Copyright (C) 2000, 2001 NETsilicon, Inc. * Copyright (C) 2000, 2001 WireSpeed Communications Corporation * @@ -27,6 +30,8 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * * author(s) : Joe deBlaquiere + * + * Modified to support NS7520 by Art Shipkowski. */ #ifndef __NET_ARM_REGISTERS_H @@ -38,6 +43,8 @@ /* the input crystal/clock frequency ( in Hz ) */ #define NETARM_XTAL_FREQ_25MHz (18432000) #define NETARM_XTAL_FREQ_33MHz (23698000) +#define NETARM_XTAL_FREQ_48MHz (48000000) +#define NETARM_XTAL_FREQ_55MHz (55000000) #define NETARM_XTAL_FREQ_EMLIN1 (20000000) /* the frequency of SYS_CLK */ @@ -60,12 +67,22 @@ #define NETARM_PLL_COUNT_VAL 4 #define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz -#else /* CONFIG_NETARM_NET50 */ +#elif defined(CONFIG_NETARM_NET50) /* NET+50 boards: 40 MHz (with NETARM_XTAL_FREQ_25MHz) */ #define NETARM_PLL_COUNT_VAL 8 #define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz +#else /* CONFIG_NETARM_NS7520 */ + +#define NETARM_PLL_COUNT_VAL 0 + +#if defined(CONFIG_BOARD_UNC20) +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_48MHz +#else +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_55MHz +#endif + #endif /* #include "arm_registers.h" */ diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h new file mode 100644 index 00000000000..ba4b1a2bc8c --- /dev/null +++ b/include/configs/AP1000.h @@ -0,0 +1,249 @@ +/* + * AMIRIX.h: AMIRIX specific config options + * + * Author : Frank Smith (smith at amirix dot com) + * + * Derived from : other configuration header files in this tree + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL) version 2, incorporated herein by + * reference. Drivers based on or derived from this code fall under the GPL + * and must retain the authorship, copyright and this license notice. This + * file is not a complete program and may only be used when the entire + * program is licensed under the GPL. + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#undef DEBUG + +#define CONFIG_405 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ + +#define CONFIG_AP1000 1 /* ...on an AP1000 board */ + +#define CONFIG_PCI 1 + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#define CFG_PROMPT "0> " +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CONFIG_COMMAND_EDIT 1 +#define CONFIG_COMMAND_HISTORY 1 +#define CONFIG_COMPLETE_ADDRESSES 1 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_FLASH_USE_BUFFER_WRITE + +#ifdef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#else +#ifdef CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_IN_NVRAM +#endif +#endif + +#define CONFIG_BAUDRATE 57600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#define CONFIG_BOOTCOMMAND "" /* autoboot command */ + +/* Size (bytes) of interrupt driven serial port buffer. + * Set to 0 to use polling instead of interrupts. + * Setting to 0 will also disable RTS/CTS handshaking. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO + +#define CONFIG_BOOTARGS "console=ttyS0,57600" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_IRQ | \ + CFG_CMD_MVENV | \ + CFG_CMD_PCI | \ + CFG_CMD_PING \ + ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SYS_CLK_FREQ 30000000 + +#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +/* usually: (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) */ +#define CFG_PBSIZE (CFG_CBSIZE+4+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_ALT_MEMTEST 1 +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01000000 /* 4 ... 16 MB in DRAM */ + +/* + * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CFG_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ + +#define CFG_NS16550_CLK 40000000 +#define CFG_DUART_CHAN 0 +#define CFG_NS16550_COM1 (0x4C000000 + 0x1000) +#define CFG_NS16550_COM2 (0x4C800000 + 0x1000) +#define CFG_NS16550_REG_SIZE 4 +#define CFG_NS16550 1 +#define CFG_INIT_CHAN1 1 +#define CFG_INIT_CHAN2 0 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +#define CFG_LOAD_ADDR 0x00200000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x20000000 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI 1 +#define CFG_PROGFLASH_BASE CFG_FLASH_BASE +#define CFG_CONFFLASH_BASE 0x24000000 + +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ + +/* BEG ENVIRONNEMENT FLASH */ +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* see README - env sector total size */ +#endif +/* END ENVIRONNEMENT FLASH */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ + +#ifdef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ +#endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + +/* Configuration Port location */ +#define CONFIG_PORT_ADDR 0xF0000500 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ + +#define CFG_INIT_RAM_ADDR 0x400000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + */ +#define SPD_EEPROM_ADDRESS 0x50 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* JFFS2 stuff */ + +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +#define CFG_JFFS2_FIRST_SECTOR 1 + +#define CONFIG_NET_MULTI +#define CONFIG_E1000 + +#define CFG_ETH_DEV_FN 0x0800 +#define CFG_ETH_IOBASE 0x31000000 +#define CFG_ETH_MEMBASE 0x32000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/NC650.h b/include/configs/NC650.h index d24d05f25e1..cd04c1ad5a3 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -99,19 +99,17 @@ #define SCL 0x1000 /* PA 3 */ #define SDA 0x2000 /* PA 2 */ -#define PAR immr->im_ioport.iop_papar -#define DIR immr->im_ioport.iop_padir -#define DAT immr->im_ioport.iop_padat - -#define I2C_INIT {PAR &= ~(SCL | SDA); DIR |= SCL;} -#define I2C_ACTIVE (DIR |= SDA) -#define I2C_TRISTATE (DIR &= ~SDA) -#define I2C_READ ((DAT & SDA) != 0) -#define I2C_SDA(bit) if (bit) DAT |= SDA; \ - else DAT &= ~SDA -#define I2C_SCL(bit) if (bit) DAT |= SCL; \ - else DAT &= ~SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#define __I2C_DIR immr->im_ioport.iop_padir +#define __I2C_DAT immr->im_ioport.iop_padat +#define __I2C_PAR immr->im_ioport.iop_papar +#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \ + __I2C_DIR |= (SDA|SCL); } +#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0) +#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; } +#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; } +#define I2C_DELAY { udelay(5); } +#define I2C_ACTIVE { __I2C_DIR |= SDA; } +#define I2C_TRISTATE { __I2C_DIR &= ~SDA; } #define CONFIG_RTC_PCF8563 #define CFG_I2C_RTC_ADDR 0x51 diff --git a/include/configs/PM854.h b/include/configs/PM854.h index af06efcb328..0b8c71d852b 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -235,7 +235,7 @@ #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_EEPRO100 +/* #define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */ #define CONFIG_E1000 #undef CONFIG_TULIP diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h index af74f9dc07d..99a7b08e4d6 100644 --- a/include/configs/TOP860.h +++ b/include/configs/TOP860.h @@ -181,17 +181,20 @@ #if defined (CONFIG_SOFT_I2C) #define SDA 0x00010 #define SCL 0x00020 -#define DIR immr->im_cpm.cp_pbdir -#define DAT immr->im_cpm.cp_pbdat -#define PAR immr->im_cpm.cp_pbpar -#define ODR immr->im_cpm.cp_pbodr -#define I2C_INIT {PAR&=~(SDA|SCL);ODR&=~(SDA|SCL);DAT|=(SDA|SCL);DIR|=(SDA|SCL);} -#define I2C_READ ((DAT&SDA)?1:0) -#define I2C_SDA(x) {if(x)DAT|=SDA;else DAT&=~SDA;} -#define I2C_SCL(x) {if(x)DAT|=SCL;else DAT&=~SCL;} -#define I2C_DELAY {udelay(5);} -#define I2C_ACTIVE {DIR|=SDA;} -#define I2C_TRISTATE {DIR&=~SDA;} +#define __I2C_DIR immr->im_cpm.cp_pbdir +#define __I2C_DAT immr->im_cpm.cp_pbdat +#define __I2C_PAR immr->im_cpm.cp_pbpar +#define __I2C_ODR immr->im_cpm.cp_pbodr +#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \ + __I2C_ODR &= ~(SDA|SCL); \ + __I2C_DAT |= (SDA|SCL); \ + __I2C_DIR|=(SDA|SCL); } +#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0) +#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; } +#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; } +#define I2C_DELAY { udelay(5); } +#define I2C_ACTIVE { __I2C_DIR |= SDA; } +#define I2C_TRISTATE { __I2C_DIR &= ~SDA; } #endif #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 909d724abc4..a57f7cf9ecb 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -83,7 +83,7 @@ #define CONFIG_PCI_IO_SIZE 0x01000000 #define CONFIG_NET_MULTI 1 -#define CONFIG_EEPRO100 1 +/* #define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 #endif /* CONFIG_STK52XX */ diff --git a/include/configs/TQM8560.h b/include/configs/TQM8560.h index d2c230d563f..04966d77a4a 100644 --- a/include/configs/TQM8560.h +++ b/include/configs/TQM8560.h @@ -283,7 +283,7 @@ #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_EEPRO100 +/* #define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */ #undef CONFIG_TULIP #if !defined(CONFIG_PCI_PNP) diff --git a/include/configs/barco.h b/include/configs/barco.h index 217c00f71b1..624fa1d6e28 100644 --- a/include/configs/barco.h +++ b/include/configs/barco.h @@ -162,7 +162,7 @@ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x000047A4 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ -#define ENV_CRC 0x8BF6F24B +/* #define ENV_CRC 0x8BF6F24B XXX - FIXME: gets defined automatically */ #define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index ffa2678598a..62b90e85fde 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -69,7 +69,7 @@ #define CFG_XLB_PIPELINING 1 #define CONFIG_NET_MULTI 1 -#define CONFIG_EEPRO100 1 +/* #define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index f6e6a609cf2..3ffe6b2e05f 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -574,19 +574,15 @@ typedef unsigned int led_id_t; #define CONFIG_CRC32_VERIFY 1 #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 -/* Note: change below for your network setting!!! - * This was done just to facilitate manufacturing test and configuration. - */ -#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a +/*****************************************************************************/ + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_SERVERIP 192.168.08.1 -#define CONFIG_IPADDR 192.168.08.85 -#define CONFIG_GATEWAYIP 192.168.08.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME stx_xtc -#define CONFIG_ROOTPATH /xtcroot -#define CONFIG_BOOTFILE uImage -#define CONFIG_LOADADDR 0x1000000 +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 +#define OF_CPU "PowerPC,MPC870@0" +#define OF_TBCLK (MPC8XX_HZ / 16) #endif /* __CONFIG_H */ diff --git a/include/ns7520_eth.h b/include/ns7520_eth.h new file mode 100644 index 00000000000..5019802a33d --- /dev/null +++ b/include/ns7520_eth.h @@ -0,0 +1,335 @@ +/*********************************************************************** + * + * Copyright 2003 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id$ + * @Author: Markus Pietrek + * @Descr: Defines the NS7520 ethernet registers. + * Stick with the old ETH prefix names instead going to the + * new EFE names in the manual. + * NS7520_ETH_* refer to NS7520 Hardware + * Reference/January 2003 [1] + * PHY_LXT971_* refer to Intel LXT971 Datasheet + * #249414 Rev. 02 [2] + * Partly derived from netarm_eth_module.h + * + * Modified by Arthur Shipkowski <art@videon-central.com> from the + * Linux version to be properly formatted for U-Boot (i.e. no C++ comments) + * + ***********************************************************************/ + +#ifndef FS_NS7520_ETH_H +#define FS_NS7520_ETH_H + +#ifdef CONFIG_DRIVER_NS7520_ETHERNET + +#include "lxt971a.h" + +/* The port addresses */ + +#define NS7520_ETH_MODULE_BASE (0xFF800000) + +#define get_eth_reg_addr(c) \ + ((volatile unsigned int*) ( NS7520_ETH_MODULE_BASE+(unsigned int) (c))) +#define NS7520_ETH_EGCR (0x0000) /* Ethernet Gen Control */ +#define NS7520_ETH_EGSR (0x0004) /* Ethernet Gen Status */ +#define NS7520_ETH_FIFO (0x0008) /* FIFO Data */ +#define NS7520_ETH_FIFOL (0x000C) /* FIFO Data Last */ +#define NS7520_ETH_ETSR (0x0010) /* Ethernet Transmit Status */ +#define NS7520_ETH_ERSR (0x0014) /* Ethernet Receive Status */ +#define NS7520_ETH_MAC1 (0x0400) /* MAC Config 1 */ +#define NS7520_ETH_MAC2 (0x0404) /* MAC Config 2 */ +#define NS7520_ETH_IPGT (0x0408) /* Back2Back InterPacket Gap */ +#define NS7520_ETH_IPGR (0x040C) /* non back2back InterPacket Gap */ +#define NS7520_ETH_CLRT (0x0410) /* Collision Window/Retry */ +#define NS7520_ETH_MAXF (0x0414) /* Maximum Frame Register */ +#define NS7520_ETH_SUPP (0x0418) /* PHY Support */ +#define NS7520_ETH_TEST (0x041C) /* Test Register */ +#define NS7520_ETH_MCFG (0x0420) /* MII Management Configuration */ +#define NS7520_ETH_MCMD (0x0424) /* MII Management Command */ +#define NS7520_ETH_MADR (0x0428) /* MII Management Address */ +#define NS7520_ETH_MWTD (0x042C) /* MII Management Write Data */ +#define NS7520_ETH_MRDD (0x0430) /* MII Management Read Data */ +#define NS7520_ETH_MIND (0x0434) /* MII Management Indicators */ +#define NS7520_ETH_SMII (0x0438) /* SMII Status Register */ +#define NS7520_ETH_SA1 (0x0440) /* Station Address 1 */ +#define NS7520_ETH_SA2 (0x0444) /* Station Address 2 */ +#define NS7520_ETH_SA3 (0x0448) /* Station Address 3 */ +#define NS7520_ETH_SAFR (0x05C0) /* Station Address Filter */ +#define NS7520_ETH_HT1 (0x05D0) /* Hash Table 1 */ +#define NS7520_ETH_HT2 (0x05D4) /* Hash Table 2 */ +#define NS7520_ETH_HT3 (0x05D8) /* Hash Table 3 */ +#define NS7520_ETH_HT4 (0x05DC) /* Hash Table 4 */ + +/* EGCR Ethernet General Control Register Bit Fields*/ + +#define NS7520_ETH_EGCR_ERX (0x80000000) /* Enable Receive FIFO */ +#define NS7520_ETH_EGCR_ERXDMA (0x40000000) /* Enable Receive DMA */ +#define NS7520_ETH_EGCR_ERXLNG (0x20000000) /* Accept Long packets */ +#define NS7520_ETH_EGCR_ERXSHT (0x10000000) /* Accept Short packets */ +#define NS7520_ETH_EGCR_ERXREG (0x08000000) /* Enable Receive Data Interrupt */ +#define NS7520_ETH_EGCR_ERFIFOH (0x04000000) /* Enable Receive Half-Full Int */ +#define NS7520_ETH_EGCR_ERXBR (0x02000000) /* Enable Receive buffer ready */ +#define NS7520_ETH_EGCR_ERXBAD (0x01000000) /* Accept bad receive packets */ +#define NS7520_ETH_EGCR_ETX (0x00800000) /* Enable Transmit FIFO */ +#define NS7520_ETH_EGCR_ETXDMA (0x00400000) /* Enable Transmit DMA */ +#define NS7520_ETH_EGCR_ETXWM_R (0x00300000) /* Enable Transmit FIFO mark Reserv */ +#define NS7520_ETH_EGCR_ETXWM_75 (0x00200000) /* Enable Transmit FIFO mark 75% */ +#define NS7520_ETH_EGCR_ETXWM_50 (0x00100000) /* Enable Transmit FIFO mark 50% */ +#define NS7520_ETH_EGCR_ETXWM_25 (0x00000000) /* Enable Transmit FIFO mark 25% */ +#define NS7520_ETH_EGCR_ETXREG (0x00080000) /* Enable Transmit Data Read Int */ +#define NS7520_ETH_EGCR_ETFIFOH (0x00040000) /* Enable Transmit Fifo Half Int */ +#define NS7520_ETH_EGCR_ETXBC (0x00020000) /* Enable Transmit Buffer Compl Int */ +#define NS7520_ETH_EGCR_EFULLD (0x00010000) /* Enable Full Duplex Operation */ +#define NS7520_ETH_EGCR_MODE_MA (0x0000C000) /* Mask */ +#define NS7520_ETH_EGCR_MODE_SEE (0x0000C000) /* 10 Mbps SEEQ ENDEC PHY */ +#define NS7520_ETH_EGCR_MODE_LEV (0x00008000) /* 10 Mbps Level1 ENDEC PHY */ +#define NS7520_ETH_EGCR_RES1 (0x00002000) /* Reserved */ +#define NS7520_ETH_EGCR_RXCINV (0x00001000) /* Invert the receive clock input */ +#define NS7520_ETH_EGCR_TXCINV (0x00000800) /* Invert the transmit clock input */ +#define NS7520_ETH_EGCR_PNA (0x00000400) /* pSOS pNA buffer */ +#define NS7520_ETH_EGCR_MAC_RES (0x00000200) /* MAC Software reset */ +#define NS7520_ETH_EGCR_ITXA (0x00000100) /* Insert Transmit Source Address */ +#define NS7520_ETH_EGCR_ENDEC_MA (0x000000FC) /* ENDEC media control bits */ +#define NS7520_ETH_EGCR_EXINT_MA (0x00000003) /* Mask */ +#define NS7520_ETH_EGCR_EXINT_RE (0x00000003) /* Reserved */ +#define NS7520_ETH_EGCR_EXINT_TP (0x00000002) /* TP-PMD Mode */ +#define NS7520_ETH_EGCR_EXINT_10 (0x00000001) /* 10-MBit Mode */ +#define NS7520_ETH_EGCR_EXINT_NO (0x00000000) /* MII normal operation */ + +/* EGSR Ethernet General Status Register Bit Fields*/ + +#define NS7520_ETH_EGSR_RES1 (0xC0000000) /* Reserved */ +#define NS7520_ETH_EGSR_RXFDB_MA (0x30000000) /* Receive FIFO mask */ +#define NS7520_ETH_EGSR_RXFDB_3 (0x30000000) /* Receive FIFO 3 bytes available */ +#define NS7520_ETH_EGSR_RXFDB_2 (0x20000000) /* Receive FIFO 2 bytes available */ +#define NS7520_ETH_EGCR_RXFDB_1 (0x10000000) /* Receive FIFO 1 Bytes available */ +#define NS7520_ETH_EGCR_RXFDB_4 (0x00000000) /* Receive FIFO 4 Bytes available */ +#define NS7520_ETH_EGSR_RXREGR (0x08000000) /* Receive Register Ready */ +#define NS7520_ETH_EGSR_RXFIFOH (0x04000000) /* Receive FIFO Half Full */ +#define NS7520_ETH_EGSR_RXBR (0x02000000) /* Receive Buffer Ready */ +#define NS7520_ETH_EGSR_RXSKIP (0x01000000) /* Receive Buffer Skip */ +#define NS7520_ETH_EGSR_RES2 (0x00F00000) /* Reserved */ +#define NS7520_ETH_EGSR_TXREGE (0x00080000) /* Transmit Register Empty */ +#define NS7520_ETH_EGSR_TXFIFOH (0x00040000) /* Transmit FIFO half empty */ +#define NS7520_ETH_EGSR_TXBC (0x00020000) /* Transmit buffer complete */ +#define NS7520_ETH_EGSR_TXFIFOE (0x00010000) /* Transmit FIFO empty */ +#define NS7520_ETH_EGSR_RXPINS (0x0000FC00) /* ENDEC Phy Status */ +#define NS7520_ETH_EGSR_RES3 (0x000003FF) /* Reserved */ + +/* ETSR Ethernet Transmit Status Register Bit Fields*/ + +#define NS7520_ETH_ETSR_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_ETSR_TXOK (0x00008000) /* Packet transmitted OK */ +#define NS7520_ETH_ETSR_TXBR (0x00004000) /* Broadcast packet transmitted */ +#define NS7520_ETH_ETSR_TXMC (0x00002000) /* Multicast packet transmitted */ +#define NS7520_ETH_ETSR_TXAL (0x00001000) /* Transmit abort - late collision */ +#define NS7520_ETH_ETSR_TXAED (0x00000800) /* Transmit abort - deferral */ +#define NS7520_ETH_ETSR_TXAEC (0x00000400) /* Transmit abort - exc collisions */ +#define NS7520_ETH_ETSR_TXAUR (0x00000200) /* Transmit abort - underrun */ +#define NS7520_ETH_ETSR_TXAJ (0x00000100) /* Transmit abort - jumbo */ +#define NS7520_ETH_ETSR_RES2 (0x00000080) /* Reserved */ +#define NS7520_ETH_ETSR_TXDEF (0x00000040) /* Transmit Packet Deferred */ +#define NS7520_ETH_ETSR_TXCRC (0x00000020) /* Transmit CRC error */ +#define NS7520_ETH_ETSR_RES3 (0x00000010) /* Reserved */ +#define NS7520_ETH_ETSR_TXCOLC (0x0000000F) /* Transmit Collision Count */ + +/* ERSR Ethernet Receive Status Register Bit Fields*/ + +#define NS7520_ETH_ERSR_RXSIZE (0xFFFF0000) /* Receive Buffer Size */ +#define NS7520_ETH_ERSR_RXCE (0x00008000) /* Receive Carrier Event */ +#define NS7520_ETH_ERSR_RXDV (0x00004000) /* Receive Data Violation Event */ +#define NS7520_ETH_ERSR_RXOK (0x00002000) /* Receive Packet OK */ +#define NS7520_ETH_ERSR_RXBR (0x00001000) /* Receive Broadcast Packet */ +#define NS7520_ETH_ERSR_RXMC (0x00000800) /* Receive Multicast Packet */ +#define NS7520_ETH_ERSR_RXCRC (0x00000400) /* Receive Packet has CRC error */ +#define NS7520_ETH_ERSR_RXDR (0x00000200) /* Receive Packet has dribble error */ +#define NS7520_ETH_ERSR_RXCV (0x00000100) /* Receive Packet code violation */ +#define NS7520_ETH_ERSR_RXLNG (0x00000080) /* Receive Packet too long */ +#define NS7520_ETH_ERSR_RXSHT (0x00000040) /* Receive Packet too short */ +#define NS7520_ETH_ERSR_ROVER (0x00000020) /* Recive overflow */ +#define NS7520_ETH_ERSR_RES (0x0000001F) /* Reserved */ + +/* MAC1 MAC Configuration Register 1 Bit Fields*/ + +#define NS7520_ETH_MAC1_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_MAC1_SRST (0x00008000) /* Soft Reset */ +#define NS7520_ETH_MAC1_SIMMRST (0x00004000) /* Simulation Reset */ +#define NS7520_ETH_MAC1_RES2 (0x00003000) /* Reserved */ +#define NS7520_ETH_MAC1_RPEMCSR (0x00000800) /* Reset PEMCS/RX */ +#define NS7520_ETH_MAC1_RPERFUN (0x00000400) /* Reset PERFUN */ +#define NS7520_ETH_MAC1_RPEMCST (0x00000200) /* Reset PEMCS/TX */ +#define NS7520_ETH_MAC1_RPETFUN (0x00000100) /* Reset PETFUN */ +#define NS7520_ETH_MAC1_RES3 (0x000000E0) /* Reserved */ +#define NS7520_ETH_MAC1_LOOPBK (0x00000010) /* Internal Loopback */ +#define NS7520_ETH_MAC1_TXFLOW (0x00000008) /* TX flow control */ +#define NS7520_ETH_MAC1_RXFLOW (0x00000004) /* RX flow control */ +#define NS7520_ETH_MAC1_PALLRX (0x00000002) /* Pass ALL receive frames */ +#define NS7520_ETH_MAC1_RXEN (0x00000001) /* Receive enable */ + +/* MAC Configuration Register 2 Bit Fields*/ + +#define NS7520_ETH_MAC2_RES1 (0xFFFF8000) /* Reserved */ +#define NS7520_ETH_MAC2_EDEFER (0x00004000) /* Excess Deferral */ +#define NS7520_ETH_MAC2_BACKP (0x00002000) /* Backpressure/NO back off */ +#define NS7520_ETH_MAC2_NOBO (0x00001000) /* No back off */ +#define NS7520_ETH_MAC2_RES2 (0x00000C00) /* Reserved */ +#define NS7520_ETH_MAC2_LONGP (0x00000200) /* Long Preable enforcement */ +#define NS7520_ETH_MAC2_PUREP (0x00000100) /* Pure preamble enforcement */ +#define NS7520_ETH_MAC2_AUTOP (0x00000080) /* Auto detect PAD enable */ +#define NS7520_ETH_MAC2_VLANP (0x00000040) /* VLAN pad enable */ +#define NS7520_ETH_MAC2_PADEN (0x00000020) /* PAD/CRC enable */ +#define NS7520_ETH_MAC2_CRCEN (0x00000010) /* CRC enable */ +#define NS7520_ETH_MAC2_DELCRC (0x00000008) /* Delayed CRC */ +#define NS7520_ETH_MAC2_HUGE (0x00000004) /* Huge frame enable */ +#define NS7520_ETH_MAC2_FLENC (0x00000002) /* Frame length checking */ +#define NS7520_ETH_MAC2_FULLD (0x00000001) /* Full duplex */ + +/* IPGT Back-to-Back Inter-Packet-Gap Register Bit Fields*/ + +#define NS7520_ETH_IPGT_RES (0xFFFFFF80) /* Reserved */ +#define NS7520_ETH_IPGT_IPGT (0x0000007F) /* Back-to-Back Interpacket Gap */ + +/* IPGR Non Back-to-Back Inter-Packet-Gap Register Bit Fields*/ + +#define NS7520_ETH_IPGR_RES1 (0xFFFF8000) /* Reserved */ +#define NS7520_ETH_IPGR_IPGR1 (0x00007F00) /* Non Back-to-back Interpacket Gap */ +#define NS7520_ETH_IPGR_RES2 (0x00000080) /* Reserved */ +#define NS7520_ETH_IPGR_IPGR2 (0x0000007F) /* Non back-to-back Interpacket Gap */ + +/* CLRT Collision Windows/Collision Retry Register Bit Fields*/ + +#define NS7520_ETH_CLRT_RES1 (0xFFFFC000) /* Reserved */ +#define NS7520_ETH_CLRT_CWIN (0x00003F00) /* Collision Windows */ +#define NS7520_ETH_CLRT_RES2 (0x000000F0) /* Reserved */ +#define NS7520_ETH_CLRT_RETX (0x0000000F) /* Retransmission maximum */ + +/* MAXF Maximum Frame Register Bit Fields*/ + +#define NS7520_ETH_MAXF_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_MAXF_MAXF (0x0000FFFF) /* Maximum frame length */ + +/* SUPP PHY Support Register Bit Fields*/ + +#define NS7520_ETH_SUPP_RES1 (0xFFFFFF00) /* Reserved */ +#define NS7520_ETH_SUPP_RPE100X (0x00000080) /* Reset PE100X module */ +#define NS7520_ETH_SUPP_FORCEQ (0x00000040) /* Force Quit */ +#define NS7520_ETH_SUPP_NOCIPH (0x00000020) /* No Cipher */ +#define NS7520_ETH_SUPP_DLINKF (0x00000010) /* Disable link fail */ +#define NS7520_ETH_SUPP_RPE10T (0x00000008) /* Reset PE10T module */ +#define NS7520_ETH_SUPP_RES2 (0x00000004) /* Reserved */ +#define NS7520_ETH_SUPP_JABBER (0x00000002) /* Enable Jabber protection */ +#define NS7520_ETH_SUPP_BITMODE (0x00000001) /* Bit Mode */ + +/* TEST Register Bit Fields*/ + +#define NS7520_ETH_TEST_RES1 (0xFFFFFFF8) /* Reserved */ +#define NS7520_ETH_TEST_TBACK (0x00000004) /* Test backpressure */ +#define NS7520_ETH_TEST_TPAUSE (0x00000002) /* Test Pause */ +#define NS7520_ETH_TEST_SPQ (0x00000001) /* Shortcut pause quanta */ + +/* MCFG MII Management Configuration Register Bit Fields*/ + +#define NS7520_ETH_MCFG_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_MCFG_RMIIM (0x00008000) /* Reset MII management */ +#define NS7520_ETH_MCFG_RES2 (0x00007FE0) /* Reserved */ +#define NS7520_ETH_MCFG_CLKS_MA (0x0000001C) /* Clock Select */ +#define NS7520_ETH_MCFG_CLKS_4 (0x00000004) /* Sysclk / 4 */ +#define NS7520_ETH_MCFG_CLKS_6 (0x00000008) /* Sysclk / 6 */ +#define NS7520_ETH_MCFG_CLKS_8 (0x0000000C) /* Sysclk / 8 */ +#define NS7520_ETH_MCFG_CLKS_10 (0x00000010) /* Sysclk / 10 */ +#define NS7520_ETH_MCFG_CLKS_14 (0x00000014) /* Sysclk / 14 */ +#define NS7520_ETH_MCFG_CLKS_20 (0x00000018) /* Sysclk / 20 */ +#define NS7520_ETH_MCFG_CLKS_28 (0x0000001C) /* Sysclk / 28 */ +#define NS7520_ETH_MCFG_SPRE (0x00000002) /* Suppress preamble */ +#define NS7520_ETH_MCFG_SCANI (0x00000001) /* Scan increment */ + +/* MCMD MII Management Command Register Bit Fields*/ + +#define NS7520_ETH_MCMD_RES1 (0xFFFFFFFC) /* Reserved */ +#define NS7520_ETH_MCMD_SCAN (0x00000002) /* Automatically Scan for Read Data */ +#define NS7520_ETH_MCMD_READ (0x00000001) /* Single scan for Read Data */ + +/* MCMD MII Management Address Register Bit Fields*/ + +#define NS7520_ETH_MADR_RES1 (0xFFFFE000) /* Reserved */ +#define NS7520_ETH_MADR_DADR (0x00001F00) /* MII PHY device address */ +#define NS7520_ETH_MADR_RES2 (0x000000E0) /* Reserved */ +#define NS7520_ETH_MADR_RADR (0x0000001F) /* MII PHY register address */ + +/* MWTD MII Management Write Data Register Bit Fields*/ + +#define NS7520_ETH_MWTD_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_MWTD_MWTD (0x0000FFFF) /* MII Write Data */ + +/* MRRD MII Management Read Data Register Bit Fields*/ + +#define NS7520_ETH_MRRD_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_MRRD_MRDD (0x0000FFFF) /* MII Read Data */ + +/* MIND MII Management Indicators Register Bit Fields*/ + +#define NS7520_ETH_MIND_RES1 (0xFFFFFFF8) /* Reserved */ +#define NS7520_ETH_MIND_NVALID (0x00000004) /* Read Data not valid */ +#define NS7520_ETH_MIND_SCAN (0x00000002) /* Automatically scan for read data */ +#define NS7520_ETH_MIND_BUSY (0x00000001) /* MII interface busy */ + +/* SMII Status Register Bit Fields*/ + +#define NS7520_ETH_SMII_RES1 (0xFFFFFFE0) /* Reserved */ +#define NS7520_ETH_SMII_CLASH (0x00000010) /* MAC-to-MAC with PHY */ +#define NS7520_ETH_SMII_JABBER (0x00000008) /* Jabber condition present */ +#define NS7520_ETH_SMII_LINK (0x00000004) /* Link OK */ +#define NS7520_ETH_SMII_DUPLEX (0x00000002) /* Full-duplex operation */ +#define NS7520_ETH_SMII_SPEED (0x00000001) /* 100 Mbps */ + +/* SA1 Station Address 1 Register Bit Fields*/ + +#define NS7520_ETH_SA1_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_SA1_OCTET1 (0x0000FF00) /* Station Address octet 1 */ +#define NS7520_ETH_SA1_OCTET2 (0x000000FF) /* Station Address octet 2 */ + +/* SA2 Station Address 2 Register Bit Fields*/ + +#define NS7520_ETH_SA2_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_SA2_OCTET3 (0x0000FF00) /* Station Address octet 3 */ +#define NS7520_ETH_SA2_OCTET4 (0x000000FF) /* Station Address octet 4 */ + +/* SA3 Station Address 3 Register Bit Fields*/ + +#define NS7520_ETH_SA3_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_SA3_OCTET5 (0x0000FF00) /* Station Address octet 5 */ +#define NS7520_ETH_SA3_OCTET6 (0x000000FF) /* Station Address octet 6 */ + +/* SAFR Station Address Filter Register Bit Fields*/ + +#define NS7520_ETH_SAFR_RES1 (0xFFFFFFF0) /* Reserved */ +#define NS7520_ETH_SAFR_PRO (0x00000008) /* Enable Promiscuous mode */ +#define NS7520_ETH_SAFR_PRM (0x00000004) /* Accept ALL multicast packets */ +#define NS7520_ETH_SAFR_PRA (0x00000002) /* Accept multicast packets table */ +#define NS7520_ETH_SAFR_BROAD (0x00000001) /* Accept ALL Broadcast packets */ + +/* HT1 Hash Table 1 Register Bit Fields*/ + +#define NS7520_ETH_HT1_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_HT1_HT1 (0x0000FFFF) /* CRC value 15-0 */ + +/* HT2 Hash Table 2 Register Bit Fields*/ + +#define NS7520_ETH_HT2_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_HT2_HT2 (0x0000FFFF) /* CRC value 31-16 */ + +/* HT3 Hash Table 3 Register Bit Fields*/ + +#define NS7520_ETH_HT3_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_HT3_HT3 (0x0000FFFF) /* CRC value 47-32 */ + +/* HT4 Hash Table 4 Register Bit Fields*/ + +#define NS7520_ETH_HT4_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_HT4_HT4 (0x0000FFFF) /* CRC value 63-48 */ + +#endif /* CONFIG_DRIVER_NS7520_ETHERNET */ + +#endif /* FS_NS7520_ETH_H */ diff --git a/net/eth.c b/net/eth.c index aa45b75a531..fe1edd13ba8 100644 --- a/net/eth.c +++ b/net/eth.c @@ -125,7 +125,7 @@ int eth_initialize(bd_t *bis) #ifdef CONFIG_DB64460 mv6446x_eth_initialize(bis); #endif -#if defined(CONFIG_4xx) && !defined(CONFIG_IOP480) +#if defined(CONFIG_4xx) && !defined(CONFIG_IOP480) && !defined(CONFIG_AP1000) ppc_4xx_eth_initialize(bis); #endif #ifdef CONFIG_INCA_IP_SWITCH |