Merge tag 'xilinx-for-v2021.01-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2021.01-v2

common:
- Add support for 64bit loadables from SPL

xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format

microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot

zynq:
- Add support for Zturn V5

zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling

versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power

zynq-sdhci:
- Add support for tap delay programming

zynq-spi/zynq-qspi:
- Use clock framework for getting clocks

xilinx-spi:
- Fix some code issues (unused variables)

serial:
- Check return value from clock functions in pl01x

1 files changed, 22 insertions, 0 deletions

diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c
index 01ac3c2094..fb1ceb1318 100644
--- a/test/dm/ofnode.c
+++ b/test/dm/ofnode.c
@@ -207,6 +207,28 @@ static int dm_test_ofnode_read_chosen(struct unit_test_state *uts)
 }
 DM_TEST(dm_test_ofnode_read_chosen, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
 
+static int dm_test_ofnode_read_aliases(struct unit_test_state *uts)
+{
+	const void *val;
+	ofnode node;
+	int size;
+
+	node = ofnode_get_aliases_node("eth3");
+	ut_assert(ofnode_valid(node));
+	ut_asserteq_str("sbe5", ofnode_get_name(node));
+
+	node = ofnode_get_aliases_node("unknown");
+	ut_assert(!ofnode_valid(node));
+
+	val = ofnode_read_aliases_prop("spi0", &size);
+	ut_assertnonnull(val);
+	ut_asserteq(7, size);
+	ut_asserteq_str("/spi@0", (const char *)val);
+
+	return 0;
+}
+DM_TEST(dm_test_ofnode_read_aliases, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
 static int dm_test_ofnode_get_child_count(struct unit_test_state *uts)
 {
 	ofnode node, child_node;