diff options
| author | Simon Glass <sjg@chromium.org> | 2018-11-23 21:29:28 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2018-12-05 06:01:34 -0700 |
| commit | 2a07269062a8e63dadc23be0f8b0d4638da7d2d2 (patch) | |
| tree | 5b0f9056117025030bfdc318c77ab8be99aa91a7 /test | |
| parent | e628bba785a310e80193f9a34c0b53fcb2136c46 (diff) | |
sandbox: sysreset: Update to support power-on reset
If U-Boot is started from SPL or TPL, then those earlier phases deal with
the reset cause. On real hardware this cause may be lost once it is read.
Emulate that behaviour in sandbox by reporting a warm reset when a
previous phase has run since start-up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'test')
| -rw-r--r-- | test/dm/sysreset.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/dm/sysreset.c b/test/dm/sysreset.c index e1b7bf5277..5b2358ef67 100644 --- a/test/dm/sysreset.c +++ b/test/dm/sysreset.c @@ -102,10 +102,10 @@ static int dm_test_sysreset_get_last(struct unit_test_state *uts) /* Device 2 is the cold sysreset device */ ut_assertok(uclass_get_device(UCLASS_SYSRESET, 2, &dev)); - ut_asserteq(SYSRESET_COLD, sysreset_get_last(dev)); + ut_asserteq(SYSRESET_POWER, sysreset_get_last(dev)); /* This is device 0, the non-DT one */ - ut_asserteq(SYSRESET_COLD, sysreset_get_last_walk()); + ut_asserteq(SYSRESET_POWER, sysreset_get_last_walk()); return 0; } |