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authorSimon Glass <sjg@chromium.org>2015-07-06 12:54:24 -0600
committerSimon Glass <sjg@chromium.org>2015-07-21 17:39:30 -0600
commit6a1c7cef14a41ade84bccdded1fd87b908b6958c (patch)
treef411334af8078f63b3767ba6bccc1e1167e4b463 /test/dm
parentc02790ce12f3bf01a49fbef71da64322fde863e6 (diff)
dm: test: Add tests for the clk uclass
Add tests of each API call using a sandbox clock device. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'test/dm')
-rw-r--r--test/dm/Makefile1
-rw-r--r--test/dm/clk.c59
2 files changed, 60 insertions, 0 deletions
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 19ad2fb99f..7947545868 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_UT_DM) += test-uclass.o
# subsystem you must add sandbox tests here.
obj-$(CONFIG_UT_DM) += core.o
ifneq ($(CONFIG_SANDBOX),)
+obj-$(CONFIG_CLK) += clk.o
obj-$(CONFIG_DM_ETH) += eth.o
obj-$(CONFIG_DM_GPIO) += gpio.o
obj-$(CONFIG_DM_I2C) += i2c.o
diff --git a/test/dm/clk.c b/test/dm/clk.c
new file mode 100644
index 0000000000..9ff6d95103
--- /dev/null
+++ b/test/dm/clk.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <asm/test.h>
+#include <dm/test.h>
+#include <linux/err.h>
+#include <test/ut.h>
+
+/* Test that we can find and adjust clocks */
+static int dm_test_clk_base(struct unit_test_state *uts)
+{
+ struct udevice *clk;
+ ulong rate;
+
+ ut_assertok(uclass_get_device(UCLASS_CLK, 0, &clk));
+ rate = clk_get_rate(clk);
+ ut_asserteq(SANDBOX_CLK_RATE, rate);
+ ut_asserteq(-EINVAL, clk_set_rate(clk, 0));
+ ut_assertok(clk_set_rate(clk, rate * 2));
+ ut_asserteq(SANDBOX_CLK_RATE * 2, clk_get_rate(clk));
+
+ return 0;
+}
+DM_TEST(dm_test_clk_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that peripheral clocks work as expected */
+static int dm_test_clk_periph(struct unit_test_state *uts)
+{
+ struct udevice *clk;
+ ulong rate;
+
+ ut_assertok(uclass_get_device(UCLASS_CLK, 0, &clk));
+ rate = clk_set_periph_rate(clk, PERIPH_ID_COUNT, 123);
+ ut_asserteq(-EINVAL, rate);
+ ut_asserteq(1, IS_ERR_VALUE(rate));
+
+ rate = clk_set_periph_rate(clk, PERIPH_ID_SPI, 123);
+ ut_asserteq(0, rate);
+ ut_asserteq(123, clk_get_periph_rate(clk, PERIPH_ID_SPI));
+
+ rate = clk_set_periph_rate(clk, PERIPH_ID_SPI, 1234);
+ ut_asserteq(123, rate);
+
+ rate = clk_set_periph_rate(clk, PERIPH_ID_I2C, 567);
+
+ rate = clk_set_periph_rate(clk, PERIPH_ID_SPI, 1234);
+ ut_asserteq(1234, rate);
+
+ ut_asserteq(567, clk_get_periph_rate(clk, PERIPH_ID_I2C));
+
+ return 0;
+}
+DM_TEST(dm_test_clk_periph, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);