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authorMasahiro Yamada <yamada.m@jp.panasonic.com>2013-10-17 17:34:47 +0900
committerTom Rini <trini@ti.com>2013-10-31 12:53:39 -0400
commitce28d7ac6d64c8a730334c8584742cf7255ad318 (patch)
treed8a3cc7f649f1674f1aeb661e0986a8413b46be2 /spl
parent9d33fb4a5cfe2767f389cc64ba16c21906e36856 (diff)
Makefile: prepare for using Kbuild-style Makefile
Every makefile in sub directories has common lines at the top and the bottom. This commit pushes the common parts into script/Makefile.build. Going forward sub-makefiles only need to describe this part: COBJS := ... COBJS += ... SOBJS := ... But using obj-y is preferable to prepare for switching to Kbuild. The conventional (non-Kbuild) Makefile style is still supported. This is achieved by greping the Makefile before entering into it. U-Boot conventional sub makefiles always include some other makefiles. So the build system searches a line beginning with "include" keyword in the makefile in order to distinguish which style it is. If the Makefile include a "include" line, we assume it is a conventional U-Boot style. Otherwise, it is treated as a Kbuild-style makefile. With this tweak, we can switch sub-makefiles from U-Boot style to Kbuild style little by little. obj-y := foo/ syntax (descending into the sub directory) is not supportd yet. It will be implemented in the upcomming commit. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'spl')
-rw-r--r--spl/Makefile22
1 files changed, 20 insertions, 2 deletions
diff --git a/spl/Makefile b/spl/Makefile
index b366ac2bb75..64ebfb7090e 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -200,11 +200,29 @@ GEN_UBOOT = \
$(obj)$(SPL_BIN): depend $(START) $(LIBS) $(obj)u-boot-spl.lds
$(GEN_UBOOT)
+# Tentative step for Kbuild-style makefiles coexist with conventional U-Boot style makefiles
+# U-Boot conventional sub makefiles always include some other makefiles.
+# So, the build system searches a line beginning with "include" before entering into the sub makefile
+# in order to distinguish which style it is.
+# If the Makefile include a "include" line, we assume it is an U-Boot style makefile.
+# Otherwise, it is treated as a Kbuild-style makefile.
+select_makefile = \
+ if grep -q "^include" $1/Makefile; then \
+ $(MAKE) -C $1; \
+ else \
+ $(MAKE) -C $1 -f $(TOPDIR)/scripts/Makefile.build; \
+ mv $(dir $@)built-in.o $@; \
+ fi
+
+# We do not need to build $(START) explicitly.
+# It is built while we are at $(CPUDIR)/lib$(CPU).o build.
$(START): depend
- $(MAKE) -C $(SRCTREE)/$(START_PATH) $@
+ if grep -q "^include" $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))Makefile; then \
+ $(MAKE) -C $(SRCTREE)/$(START_PATH) $@; \
+ fi
$(LIBS): depend
- $(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))
+ +$(call select_makefile, $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)))
$(obj)u-boot-spl.lds: $(LDSCRIPT) depend
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@