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authorTom Rini <trini@konsulko.com>2020-06-25 09:33:39 -0400
committerTom Rini <trini@konsulko.com>2020-06-25 09:33:39 -0400
commitf0e236c8d6646f6ef0ebf8f043962a07dda3b3a3 (patch)
tree393f3a5a757c2faf8e1506a6a94e70d253b591dd /scripts
parent6ccbd1590fb15b673c90c9ccde5da8dcaaf80a10 (diff)
parentb8fd54d62f92658cbd20ca051304e13eabf24ddd (diff)
Merge tag 'xilinx-for-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2020.10 Versal: - xspi bootmode fix - Removing one clock from clk driver - Align u-boot memory setting with OS by default - Map TCM and OCM by default ZynqMP: - Minor DT improvements - Reduce console buffer for mini configurations - Add fix for AMS - Add support for XDP platform Zynq: - Support for AES engine - Enable bigger memory test by default - Extend documentation for SD preparation - Use different freq for Topic miami board mmc: - minor GD pointer removal net: - Support fixed-link cases by zynq gem - Fix phy looking loop in axi enet driver spi: - Cleanup global macros for xilinx spi drivers firmware: - Add support for pmufw reloading fpga: - Improve error status reporting common: - Remove 4kB addition space for FDT allocation
Diffstat (limited to 'scripts')
-rw-r--r--scripts/config_whitelist.txt17
1 files changed, 0 insertions, 17 deletions
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 1165e88c28..bc3ca6e5b5 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1414,8 +1414,6 @@ CONFIG_RESET_TO_RETRY
CONFIG_RESET_VECTOR_ADDRESS
CONFIG_RESTORE_FLASH
CONFIG_RES_BLOCK_SIZE
-CONFIG_REV1
-CONFIG_REV3
CONFIG_REVISION_TAG
CONFIG_RFSPART
CONFIG_RIO
@@ -2224,10 +2222,6 @@ CONFIG_SYS_DSPI_CTAR0
CONFIG_SYS_DSPI_CTAR1
CONFIG_SYS_DSPI_CTAR2
CONFIG_SYS_DSPI_CTAR3
-CONFIG_SYS_DSPI_CTAR4
-CONFIG_SYS_DSPI_CTAR5
-CONFIG_SYS_DSPI_CTAR6
-CONFIG_SYS_DSPI_CTAR7
CONFIG_SYS_DV_NOR_BOOT_CFG
CONFIG_SYS_EBI_CFGR_VAL
CONFIG_SYS_EBI_CSA_VAL
@@ -3787,14 +3781,6 @@ CONFIG_SYS_SPCR_OPT
CONFIG_SYS_SPCR_TSEC1EP
CONFIG_SYS_SPCR_TSEC2EP
CONFIG_SYS_SPD_BUS_NUM
-CONFIG_SYS_SPI0
-CONFIG_SYS_SPI0_NUM_CS
-CONFIG_SYS_SPI1
-CONFIG_SYS_SPI1_BASE
-CONFIG_SYS_SPI1_NUM_CS
-CONFIG_SYS_SPI2
-CONFIG_SYS_SPI2_BASE
-CONFIG_SYS_SPI2_NUM_CS
CONFIG_SYS_SPI_ARGS_OFFS
CONFIG_SYS_SPI_ARGS_SIZE
CONFIG_SYS_SPI_BASE
@@ -3996,8 +3982,6 @@ CONFIG_SYS_XHCI_USB1_ADDR
CONFIG_SYS_XHCI_USB2_ADDR
CONFIG_SYS_XHCI_USB3_ADDR
CONFIG_SYS_XIMG_LEN
-CONFIG_SYS_ZYNQ_QSPI_WAIT
-CONFIG_SYS_ZYNQ_SPI_WAIT
CONFIG_SYS_i2C_FSL
CONFIG_TAM3517_SETTINGS
CONFIG_TCA642X
@@ -4223,7 +4207,6 @@ CONFIG_X86_MRC_ADDR
CONFIG_X86_REFCODE_ADDR
CONFIG_X86_REFCODE_RUN_ADDR
CONFIG_XGI_XG22_BASE
-CONFIG_XILINX_SPI_IDLE_VAL
CONFIG_XSENGINE
CONFIG_XTFPGA
CONFIG_YAFFSFS_PROVIDE_VALUES