diff options
| author | Dhruva Gole <d-gole@ti.com> | 2022-11-17 17:40:58 +0530 |
|---|---|---|
| committer | Anand Gadiyar <gadiyar@ti.com> | 2022-11-21 09:33:36 -0600 |
| commit | a9df6cd890da6984504c00d466069b960366395e (patch) | |
| tree | 9f458470b8899c8f06c13386114fb3ce857520dc /scripts/basic/fixdep.c | |
| parent | 35c5ec0da0c43660da065ef87b8486c185920675 (diff) | |
mtd: spi-nor-core: Add support for volatile QE bit
Commit a4aa9b7522dc67745795c1e2a76115a616da00ea upstream.
Some of Spansion/Cypress chips support volatile version of configuration
registers and it is recommended to update volatile registers in the field
application due to a risk of the non-volatile registers corruption by
power interrupt. This patch adds a function to set Quad Enable bit in
CFR1 volatile.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Diffstat (limited to 'scripts/basic/fixdep.c')
0 files changed, 0 insertions, 0 deletions