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authorIgor Lisitsin <igor@emcraft.com>2007-03-28 19:06:19 +0400
committerWolfgang Denk <wd@denx.de>2007-06-22 23:21:01 +0200
commita11e06965ec91270c51853407ff1261d3c740386 (patch)
tree438b2a6816ee30034a1c5d979370185570bbdba8 /post/lib_ppc
parent02032e8f14751a1a751b09240a4f1cf9f8a2077f (diff)
Extend POST support for PPC440
Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin <igor@emcraft.com> --
Diffstat (limited to 'post/lib_ppc')
-rw-r--r--post/lib_ppc/asm.S12
-rw-r--r--post/lib_ppc/b.c8
2 files changed, 16 insertions, 4 deletions
diff --git a/post/lib_ppc/asm.S b/post/lib_ppc/asm.S
index a0815a43a7..5e72b3418f 100644
--- a/post/lib_ppc/asm.S
+++ b/post/lib_ppc/asm.S
@@ -34,6 +34,7 @@
/* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */
.global cpu_post_exec_02
cpu_post_exec_02:
+ isync
mflr r0
stwu r0, -4(r1)
@@ -56,6 +57,7 @@ cpu_post_exec_02:
/* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */
.global cpu_post_exec_04
cpu_post_exec_04:
+ isync
mflr r0
stwu r0, -4(r1)
@@ -80,6 +82,7 @@ cpu_post_exec_04:
/* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */
.global cpu_post_exec_12
cpu_post_exec_12:
+ isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@@ -100,6 +103,7 @@ cpu_post_exec_12:
/* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */
.global cpu_post_exec_11
cpu_post_exec_11:
+ isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@@ -119,6 +123,7 @@ cpu_post_exec_11:
/* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */
.global cpu_post_exec_21
cpu_post_exec_21:
+ isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@@ -148,6 +153,7 @@ cpu_post_exec_21:
ulong op2); */
.global cpu_post_exec_22
cpu_post_exec_22:
+ isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@@ -177,6 +183,7 @@ cpu_post_exec_22:
/* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */
.global cpu_post_exec_12w
cpu_post_exec_12w:
+ isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@@ -198,6 +205,7 @@ cpu_post_exec_12w:
/* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */
.global cpu_post_exec_11w
cpu_post_exec_11w:
+ isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@@ -218,6 +226,7 @@ cpu_post_exec_11w:
/* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */
.global cpu_post_exec_22w
cpu_post_exec_22w:
+ isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@@ -241,6 +250,7 @@ cpu_post_exec_22w:
/* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */
.global cpu_post_exec_21w
cpu_post_exec_21w:
+ isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@@ -263,6 +273,7 @@ cpu_post_exec_21w:
/* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */
.global cpu_post_exec_21x
cpu_post_exec_21x:
+ isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@@ -286,6 +297,7 @@ cpu_post_exec_21x:
ulong cr); */
.global cpu_post_exec_31
cpu_post_exec_31:
+ isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
diff --git a/post/lib_ppc/b.c b/post/lib_ppc/b.c
index b4b17c8ff0..6e276c48d5 100644
--- a/post/lib_ppc/b.c
+++ b/post/lib_ppc/b.c
@@ -49,7 +49,7 @@ extern void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump,
ulong cr);
static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi,
- int pjump, int dec, int link, ulong pctr, ulong cr)
+ int pjump, int decr, int link, ulong pctr, ulong cr)
{
int ret = 0;
ulong lr = 0;
@@ -77,7 +77,7 @@ static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi,
ret = pjump == jump ? 0 : -1;
if (ret == 0)
{
- if (dec)
+ if (decr)
ret = pctr == ctr + 1 ? 0 : -1;
else
ret = pctr == ctr ? 0 : -1;
@@ -163,7 +163,7 @@ int cpu_post_test_b (void)
{
for (ctr = 1; ctr <= 2 && ret == 0; ctr++)
{
- int dec = cd < 2;
+ int decr = cd < 2;
int cr = cond ? 0x80000000 : 0x00000000;
int jumpc = cc >= 2 ||
(cc == 0 && !cond) ||
@@ -174,7 +174,7 @@ int cpu_post_test_b (void)
int jump = jumpc && jumpd;
ret = cpu_post_test_bc (link ? OP_BCL : OP_BC,
- (cc << 3) + (cd << 1), 0, jump, dec, link,
+ (cc << 3) + (cd << 1), 0, jump, decr, link,
ctr, cr);
if (ret != 0)