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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2014-03-07 17:28:04 +0100
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2014-03-07 17:28:04 +0100
commitf624e019a3f37ee4415a407afae0e026dd203714 (patch)
tree32621b909de2746fbbabcc874a05078a032613a5 /onenand_ipl
parent5017686683f7c2eb12bb966924c857622e9cdb94 (diff)
Add default VESA VGA vidargs for our now modedb enabled kernel. This allows easy specifying an alternate parallel RGB resolution. While at it further checkpatchify our board file.
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