diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2011-05-03 10:00:14 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2011-08-24 10:01:08 -0700 |
| commit | 9f166c674e09f14fc3133c53d9e61e77897ea3cc (patch) | |
| tree | 6d08172983c412c7c061b2d45cb9e9c352038505 /lib | |
| parent | 1073ac148dd15d8d69e8f77f6e55e608b1215933 (diff) | |
Change the shared memory structure.
This change modifies the shared memory structure such that the fields of
interest for the kernel (vbnv and nvcxt_cache) bubble up to the base of the
structure. The kernel side change requiring this modification is being
submitted under http://codereview.chromium.org/6902164/
Also, this eliminates the gpio array in the shared memory and introduces
fields to convey actual states of the bits of interest (wrote_protect,
recovery and developer mode).
The crossystem changes using this CL are being prepared under
http://codereview.chromium.org/6902172.
The kernel changes using this CL are being reviewed under
http://codereview.chromium.org/6902164/
BUG=chromium-os:12522
TEST=manual
See http://codereview.chromium.org/6902164 for test description.
Change-Id: Ifdba918ff0287e3f11851b95a0919a61370fb564
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/chromeos/os_storage.c | 41 |
1 files changed, 25 insertions, 16 deletions
diff --git a/lib/chromeos/os_storage.c b/lib/chromeos/os_storage.c index 5bb4e80d2be..50c4b0fa6aa 100644 --- a/lib/chromeos/os_storage.c +++ b/lib/chromeos/os_storage.c @@ -12,6 +12,7 @@ #include <malloc.h> #include <part.h> #include <chromeos/os_storage.h> +#include <chromeos/hardware_interface.h> /* TODO For load fmap; remove when not used */ #include <chromeos/firmware_storage.h> @@ -31,6 +32,9 @@ extern uint64_t get_nvcxt_lba(void); #define BACKUP_LBA_OFFSET 0x20 +/* This is used to keep u-boot and kernel in sync */ +#define SHARED_MEM_VERSION 1 + static struct { block_dev_desc_t *dev_desc; ulong offset, limit; @@ -266,18 +270,22 @@ EXIT: gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS-1].size - SZ_1M; struct { - uint32_t total_size; - uint8_t signature[12]; - uint64_t nvcxt_lba; - uint8_t gpio[11]; - uint8_t binf[5]; - uint8_t nvcxt_cache[VBNV_BLOCK_SIZE]; - uint32_t chsw; - uint8_t hwid[256]; - uint8_t fwid[256]; - uint8_t frid[256]; - uint32_t vbnv[2]; - uint8_t shared_data_body[CONFIG_LENGTH_FMAP]; + uint32_t total_size; + uint8_t signature[10]; + uint16_t version; + uint64_t nvcxt_lba; + uint16_t vbnv[2]; + uint8_t nvcxt_cache[VBNV_BLOCK_SIZE]; + uint8_t write_protect_sw; + uint8_t recovery_sw; + uint8_t developer_sw; + uint8_t binf[5]; + uint32_t chsw; + uint8_t hwid[256]; + uint8_t fwid[256]; + uint8_t frid[256]; + uint32_t fmap_base; + uint8_t shared_data_body[CONFIG_LENGTH_FMAP]; } __attribute__((packed)) *sd = kernel_shared_data; int i; @@ -287,6 +295,7 @@ EXIT: memset(sd, '\0', sizeof(*sd)); strcpy((char*) sd->signature, "CHROMEOS"); + sd->version = SHARED_MEM_VERSION; /* * chsw bit value @@ -315,8 +324,10 @@ EXIT: sd->binf[2] = 0; /* active EC firmware */ sd->binf[4] = reason; - /* sd->gpio[i] == 1 if it is active-high */ - sd->gpio[1] = 1; /* only developer mode gpio is active high */ + sd->write_protect_sw = + is_firmware_write_protect_gpio_asserted(); + sd->recovery_sw = is_recovery_mode_gpio_asserted(); + sd->developer_sw = is_developer_mode_gpio_asserted(); sd->vbnv[0] = 0; sd->vbnv[1] = VBNV_BLOCK_SIZE; @@ -338,8 +349,6 @@ EXIT: debug(PREFIX "chsw %08x\n", sd->chsw); for (i = 0; i < 5; i++) debug(PREFIX "binf[%2d] %08x\n", i, sd->binf[i]); - for (i = 0; i < 11; i++) - debug(PREFIX "gpio[%2d] %08x\n", i, sd->gpio[i]); debug(PREFIX "vbnv[ 0] %08x\n", sd->vbnv[0]); debug(PREFIX "vbnv[ 1] %08x\n", sd->vbnv[1]); debug(PREFIX "fmap %08llx\n", sd->fmap_start_address); |