MA-17226 Invalidate the dcache after DMA operation

The main memory contents can spontaneously come to the cache due to
the speculative memory access by the CPU, this may cause coherency
problem if this happens during the DMA operaion is on-going.

Invalidate the dcache range after DMA opeartion but before the main
memory read to avoid coherency problem.

Test: reboot test.

Change-Id: I93824deab9285b5478669e0a311e0b338bf02f8a
Signed-off-by: Ji Luo <ji.luo@nxp.com>

1 files changed, 21 insertions, 0 deletions

diff --git a/lib/trusty/ql-tipc/hwcrypto.c b/lib/trusty/ql-tipc/hwcrypto.c
index 800b759c538..051a505aa9f 100644
--- a/lib/trusty/ql-tipc/hwcrypto.c
+++ b/lib/trusty/ql-tipc/hwcrypto.c
@@ -186,6 +186,12 @@ int hwcrypto_hash(uint32_t in_addr, uint32_t in_len, uint32_t out_addr,
 
     int rc = hwcrypto_do_tipc(HWCRYPTO_HASH, (void*)&req,
                               sizeof(req), NULL, 0, false);
+
+    /* invalidate the dcache again before read to avoid coherency
+     * problem caused by speculative memory access by the CPU.
+     */
+    invalidate_dcache_range(start, end);
+
     return rc;
 }
 
@@ -216,6 +222,11 @@ int hwcrypto_gen_blob(uint32_t plain_pa,
 
     int rc = hwcrypto_do_tipc(HWCRYPTO_ENCAP_BLOB, (void*)&req,
                               sizeof(req), NULL, 0, false);
+
+    /* invalidate the dcache again before read to avoid coherency
+     * problem caused by speculative memory access by the CPU.
+     */
+    invalidate_dcache_range(start, end);
     return rc;
 }
 
@@ -238,6 +249,11 @@ int hwcrypto_gen_rng(uint32_t buf, uint32_t len)
 
     int rc = hwcrypto_do_tipc(HWCRYPTO_GEN_RNG, (void*)&req,
                               sizeof(req), NULL, 0, false);
+
+    /* invalidate the dcache again before read to avoid coherency
+     * problem caused by speculative memory access by the CPU.
+     */
+    invalidate_dcache_range(start, end);
     return rc;
 }
 
@@ -260,6 +276,11 @@ int hwcrypto_gen_bkek(uint32_t buf, uint32_t len)
 
     int rc = hwcrypto_do_tipc(HWCRYPTO_GEN_BKEK, (void*)&req,
                               sizeof(req), NULL, 0, false);
+
+    /* invalidate the dcache again before read to avoid coherency
+     * problem caused by speculative memory access by the CPU.
+     */
+    invalidate_dcache_range(start, end);
     return rc;
 }