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authorBin Meng <bmeng.cn@gmail.com>2016-02-01 01:40:45 -0800
committerBin Meng <bmeng.cn@gmail.com>2016-02-05 12:47:21 +0800
commit79d4eb627cffbc3ab7cefdd623fa39fefaaedbe7 (patch)
tree10b2756494ba0b3d3a0967f1ef82380689612e51 /include
parentec2af6f82d4ee07fa19877e2bb2e5c80d8d6962b (diff)
dm: pch: Add get_io_base op
On some newer chipset (eg: BayTrail), there is an IO base address register on the PCH device which configures the base address of a memory-mapped I/O controller. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include')
-rw-r--r--include/pch.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/include/pch.h b/include/pch.h
index b378865c67..222e9081c3 100644
--- a/include/pch.h
+++ b/include/pch.h
@@ -41,6 +41,15 @@ struct pch_ops {
* @return 0 if OK, -ve on error (e.g. there is no GPIO base)
*/
int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
+
+ /**
+ * get_io_base() - get the address of IO base
+ *
+ * @dev: PCH device to check
+ * @iobasep: Returns address of IO base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no IO base)
+ */
+ int (*get_io_base)(struct udevice *dev, u32 *iobasep);
};
#define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
@@ -73,4 +82,13 @@ int pch_set_spi_protect(struct udevice *dev, bool protect);
*/
int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
+/**
+ * pch_get_io_base() - get the address of IO base
+ *
+ * @dev: PCH device to check
+ * @iobasep: Returns address of IO base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no IO base)
+ */
+int pch_get_io_base(struct udevice *dev, u32 *iobasep);
+
#endif