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authorRon Madrid <ron_madrid@sbcglobal.net>2010-06-01 17:00:49 -0700
committerKim Phillips <kim.phillips@freescale.com>2010-06-04 10:42:59 -0500
commitf986325dd569faeaec4186f678d113505c5c4828 (patch)
treec7553c2b1528f47ba1a6032c7b54e623583eeacb /include
parent9bb3b3d4406c1e388a99f6fb189147d6a06cc2cf (diff)
Update SICRL_USBDR to reflect 4 different settings
This patch changed the SICRL_USBDR define to reflect the 4 different bit settings for this two-bit field. The four different options are '00', '01', '10', and '11'. This patch also corrects the config file for SIMPC8313 and MPC8313ERDB for the appropriate fields. This change only affects the MPC8313 cpu. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/MPC8313ERDB.h2
-rw-r--r--include/configs/SIMPC8313.h2
-rw-r--r--include/mpc83xx.h5
3 files changed, 6 insertions, 3 deletions
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 94695fc285d..9a40adc3550 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -513,7 +513,7 @@
/* System IO Config */
#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
-#define CONFIG_SYS_SICRL SICRL_USBDR /* Enable Internal USB Phy */
+#define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index 9104f1ad36d..eb8657b6be0 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -419,7 +419,7 @@
| SICRH_TSOBI1 \
| SICRH_TSOBI2 )
#define CONFIG_SYS_SICRL ( SICRL_LBC \
- | SICRL_USBDR \
+ | SICRL_USBDR_10 \
| SICRL_ETSEC2_A )
#define CONFIG_SYS_HID0_INIT 0x000000000
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 44115c91b41..5214911d1c9 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -206,7 +206,10 @@
#define SICRL_SPI_B 0x00C00000
#define SICRL_SPI_C 0x00300000
#define SICRL_SPI_D 0x000C0000
-#define SICRL_USBDR 0x00000C00
+#define SICRL_USBDR_11 0x00000C00
+#define SICRL_USBDR_10 0x00000800
+#define SICRL_USBDR_01 0x00000400
+#define SICRL_USBDR_00 0x00000000
#define SICRL_ETSEC1_A 0x0000000C
#define SICRL_ETSEC2_A 0x00000003