* Patch by Dave Peverley, 30 Apr 2004:

  Add support for OMAP730 Perseus2 Development board

* Patch by Alan J. Luse, 29 Apr 2004:
  Fix flash chip-select (OR0) option register setting on FADS boards.

* Patch by Alan J. Luse, 29 Apr 2004:
  Report MII network speed and duplex setting properly when
  auto-negotiate is not enabled.

* Patch by Jarrett Redd, 29 Apr 2004:
  Fix hang on reset on Ocotea board due to flash in wrong mode.

4 files changed, 664 insertions, 0 deletions

diff --git a/include/configs/h2_p2_dbg_board.h b/include/configs/h2_p2_dbg_board.h
new file mode 100644
index 00000000000..8a5ec340260
--- /dev/null
+++ b/include/configs/h2_p2_dbg_board.h
@@ -0,0 +1,145 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   TI H2 and P2 Debug Board hardware map
+ *
+ * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
+ * Author: MPC-Data Limited
+ *	   Dave Peverley
+ *
+ *  This program is free software; you can redistribute	 it and/or modify it
+ *  under  the terms of	 the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the	License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
+ *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
+ *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __INCLUDED_H2_P2_DBH_BOARD_H
+#define __INCLUDED_H2_P2_DBH_BOARD_H
+
+
+#include <asm/arch/sizes.h>
+
+
+/*
+ * The Debug board is designed to function with the P2 Sample, H2
+ * Sample and 1610 Innovator boards. The main difference AFAICT is 
+ * the chip selects used with each system ;
+ *
+ *   P2 Sample : CS1 of OMAP730 is used to select the CPLD & LAN regs
+ *   H2 Sample : CS1a is used to select the CPLD registers.
+ *
+ */
+
+
+
+/***************************************************************************
+ * CPLD Registers
+ **************************************************************************/
+
+#define H2DBG_CPLD_REVISION        0x04000010
+#define H2DBG_BOARD_REVISION       0x04000012
+#define H2DBG_GPIO_REGISTER        0x04000014
+#define H2DBG_LED_CONTROL          0x04000016
+#define H2DBG_MISC_INPUT           0x04000018
+#define H2DBG_LAN_STATUS           0x0400001A
+#define H2DBG_LAN_RESET            0x0400001C
+#define H2DBG_ETH_REG_BASE         0x04000300
+
+
+
+/***************************************************************************
+ * Ethernet Control Registers
+ * These are for the LAN91C96 on the debug board
+ **************************************************************************/
+
+/* Bank 0 in IO space */
+
+#define ETH_TCR            (H2DBG_ETH_REG_BASE + 0x00)   /* Transmit Control Register */
+#define ETH_EPH_STATUS     (H2DBG_ETH_REG_BASE + 0x02)   /* EPH Status Register */
+#define ETH_RCR            (H2DBG_ETH_REG_BASE + 0x04)   /* Receive Control Register */
+#define ETH_COUNTER        (H2DBG_ETH_REG_BASE + 0x06)   /* Counter Register */
+#define ETH_MIR            (H2DBG_ETH_REG_BASE + 0x08)   /* Memory Information Register */
+#define ETH_MCR            (H2DBG_ETH_REG_BASE + 0x0A)   /* Memory Configuration Register */
+
+/* Bank 1 in IO space */
+
+#define ETH_CONFIG         (H2DBG_ETH_REG_BASE + 0x00)   /* Configuration Register */
+#define ETH_BASE           (H2DBG_ETH_REG_BASE + 0x02)   /* Base Address Register */
+#define ETH_IA0            (H2DBG_ETH_REG_BASE + 0x04)   /* Individual Address Register - 0 */
+#define ETH_IA1            (H2DBG_ETH_REG_BASE + 0x05)   /* Individual Address Register - 1 */
+#define ETH_IA2            (H2DBG_ETH_REG_BASE + 0x06)   /* Individual Address Register - 2 */
+#define ETH_IA3            (H2DBG_ETH_REG_BASE + 0x07)   /* Individual Address Register - 3 */
+#define ETH_IA4            (H2DBG_ETH_REG_BASE + 0x08)   /* Individual Address Register - 4 */
+#define ETH_IA5            (H2DBG_ETH_REG_BASE + 0x09)   /* Individual Address Register - 5 */
+#define ETH_GEN_PURPOSE    (H2DBG_ETH_REG_BASE + 0x0A)   /* General Address Registers */
+#define ETH_CONTROL        (H2DBG_ETH_REG_BASE + 0x0B)   /* Control Register */
+
+/* Bank 2 in IO space */
+
+#define ETH_MMU            (H2DBG_ETH_REG_BASE + 0x00)   /* MMU Command Register */
+#define ETH_AUTO_TX_START  (H2DBG_ETH_REG_BASE + 0x01)   /* Auto Tx Start Register */
+#define ETH_PNR            (H2DBG_ETH_REG_BASE + 0x02)   /* Packet Number Register */
+#define ETH_ARR            (H2DBG_ETH_REG_BASE + 0x03)   /* Allocation Result Register */
+#define ETH_FIFO           (H2DBG_ETH_REG_BASE + 0x04)   /* FIFO Ports Register */
+#define ETH_POINTER        (H2DBG_ETH_REG_BASE + 0x06)   /* Pointer Register */
+#define ETH_DATA_HIGH      (H2DBG_ETH_REG_BASE + 0x08)   /* Data High Register */
+#define ETH_DATA_LOW       (H2DBG_ETH_REG_BASE + 0x0A)   /* Data Low Register */
+#define ETH_INT_STATS      (H2DBG_ETH_REG_BASE + 0x0C)   /* Interrupt Status Register - RO */
+#define ETH_INT_ACK        (H2DBG_ETH_REG_BASE + 0x0C)   /* Interrupt Acknowledge Register -WO */
+#define ETH_INT_MASK       (H2DBG_ETH_REG_BASE + 0x0D)   /* Interrupt Mask Register */
+
+
+#ifndef __ASSEMBLY__
+
+/*
+ * A couple of utility inlines to aid debugging using the LED's on the 
+ * debug board.
+ */
+
+static inline void set_led_state(int state)
+{
+	static unsigned long hw_led_state = 0;
+	volatile unsigned short *led_address = 0x04000016;
+
+	hw_led_state = ((unsigned long)state);
+	*((unsigned short *) (led_address)) = (unsigned short) (~hw_led_state & 0xFFFF);
+}
+
+
+static inline void spin_up_leds()
+{                                  
+	volatile int i, j, k;
+
+	for (k = 0; k < 2; k++) {
+		for (i = 0; i < 16; i++) {
+			for (j = 0; j < 5000; j++) {
+				set_led_state(1 << i);
+			}
+		}
+		for (i = 15; i >= 0; i--) {
+			for (j = 0; j < 5000; j++) {
+				set_led_state(1 << i);
+			}
+		}
+	}
+}
+
+#endif    /* !  __ASSEMBLY__ */
+
+#endif    /* !  __INCLUDED_H2_P2_DBH_BOARD_H */
+
diff --git a/include/configs/omap730.h b/include/configs/omap730.h
new file mode 100644
index 00000000000..5fbbeb025e2
--- /dev/null
+++ b/include/configs/omap730.h
@@ -0,0 +1,287 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   OMAP730 hardware map
+ *
+ * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
+ * Author: MPC-Data Limited
+ *	   Dave Peverley
+ *
+ *  This program is free software; you can redistribute	 it and/or modify it
+ *  under  the terms of	 the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the	License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
+ *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
+ *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+
+#ifndef __INCLUDED_OMAP730_H
+#define __INCLUDED_OMAP730_H
+
+#include <asm/arch/sizes.h>
+
+
+
+
+/***************************************************************************
+ * OMAP730 Configuration Registers
+ **************************************************************************/
+
+#define PERSEUS2_MPU_DEV_ID               ((unsigned int)(0xFFFE1000))
+#define PERSEUS2_GSM_DEV_ID0              ((unsigned int)(0xFFFE1000))
+#define PERSEUS2_GDM_DEV_ID1              ((unsigned int)(0xFFFE1002))
+#define DSP_CONF                          ((unsigned int)(0xFFFE1004))
+#define PERSEUS2_MPU_DIE_ID0              ((unsigned int)(0xFFFE1008))
+#define GSM_ASIC_CONF                     ((unsigned int)(0xFFFE1008))
+#define PERSEUS2_MPU_DIE_ID1              ((unsigned int)(0xFFFE100C))
+#define PERSEUS2_MODE1                    ((unsigned int)(0xFFFE1010))
+#define PERSEUS2_GSM_DIE_ID0              ((unsigned int)(0xFFFE1010))
+#define PERSEUS2_GSM_DIE_ID1              ((unsigned int)(0xFFFE1012))
+#define PERSEUS2_MODE2                    ((unsigned int)(0xFFFE1014))
+#define PERSEUS2_GSM_DIE_ID2              ((unsigned int)(0xFFFE1014))
+#define PERSEUS2_GSM_DIE_ID3              ((unsigned int)(0xFFFE1016))
+#define PERSEUS2_ANALOG_CELLS_CONF        ((unsigned int)(0xFFFE1018))
+#define SPECCTL                           ((unsigned int)(0xFFFE101C))
+#define SPARE1                            ((unsigned int)(0xFFFE1020))
+#define SPARE2                            ((unsigned int)(0xFFFE1024))
+#define GSM_PBG_IRQ                       ((unsigned int)(0xFFFE1028))
+#define DMA_REQ_CONF                      ((unsigned int)(0xFFFE1030))
+#define PE_CONF_NO_DUAL                   ((unsigned int)(0xFFFE1060))
+#define PERSEUS2_IO_CONF0                 ((unsigned int)(0xFFFE1070))
+#define PERSEUS2_IO_CONF1                 ((unsigned int)(0xFFFE1074))
+#define PERSEUS2_IO_CONF2                 ((unsigned int)(0xFFFE1078))
+#define PERSEUS2_IO_CONF3                 ((unsigned int)(0xFFFE107C))
+#define PERSEUS2_IO_CONF4                 ((unsigned int)(0xFFFE1080))
+#define PERSEUS2_IO_CONF5                 ((unsigned int)(0xFFFE1084))
+#define PERSEUS2_IO_CONF6                 ((unsigned int)(0xFFFE1088))
+#define PERSEUS2_IO_CONF7                 ((unsigned int)(0xFFFE108C))
+#define PERSEUS2_IO_CONF8                 ((unsigned int)(0xFFFE1090))
+#define PERSEUS2_IO_CONF9                 ((unsigned int)(0xFFFE1094))
+#define PERSEUS2_IO_CONF10                ((unsigned int)(0xFFFE1098))
+#define PERSEUS2_IO_CONF11                ((unsigned int)(0xFFFE109C))
+#define PERSEUS2_IO_CONF12                ((unsigned int)(0xFFFE10A0))
+#define PERSEUS2_IO_CONF13                ((unsigned int)(0xFFFE10A4))
+#define PERSEUS_PCC_CONF_REG              ((unsigned int)(0xFFFE10B4))
+#define BIST_STATUS_INTERNAL              ((unsigned int)(0xFFFE10B8))
+#define BIST_CONTROL                      ((unsigned int)(0xFFFE10C0))
+#define BOOT_ROM_REG                      ((unsigned int)(0xFFFE10C4))
+#define PRODUCTION_ID_REG                 ((unsigned int)(0xFFFE10C8))
+#define BIST_SECROM_SIGNATURE1_INTERNAL   ((unsigned int)(0xFFFE10D0))
+#define BIST_SECROM_SIGNATURE2_INTERNAL   ((unsigned int)(0xFFFE10D4))
+#define BIST_CONTROL_2                    ((unsigned int)(0xFFFE10D8))
+#define DEBUG1                            ((unsigned int)(0xFFFE10E0))
+#define DEBUG2                            ((unsigned int)(0xFFFE10E4))
+#define DEBUG_DMA_IRQ                     ((unsigned int)(0xFFFE10E8))
+
+
+
+
+/***************************************************************************
+ * OMAP730 EMIFS Registers                                       (TRM 2.5.7)
+ **************************************************************************/
+
+#define TCMIF_BASE                 0xFFFECC00
+
+#define EMIFS_LRUREG               (TCMIF_BASE + 0x04)
+#define EMIFS_CONFIG               (TCMIF_BASE + 0x0C)
+#define FLASH_CFG_0                (TCMIF_BASE + 0x10)
+#define FLASH_CFG_1                (TCMIF_BASE + 0x14)
+#define FLASH_CFG_2                (TCMIF_BASE + 0x18)
+#define FLASH_CFG_3                (TCMIF_BASE + 0x1C)
+#define FL_CFG_DYN_WAIT            (TCMIF_BASE + 0x40)
+#define EMIFS_TIMEOUT1_REG         (TCMIF_BASE + 0x28)
+#define EMIFS_TIMEOUT2_REG         (TCMIF_BASE + 0x2C)
+#define EMIFS_TIMEOUT3_REG         (TCMIF_BASE + 0x30)
+#define EMIFS_ABORT_ADDR           (TCMIF_BASE + 0x44)
+#define EMIFS_ABORT_TYPE           (TCMIF_BASE + 0x48)
+#define EMIFS_ABORT_TOUT           (TCMIF_BASE + 0x4C)
+#define FLASH_ACFG_0_1             (TCMIF_BASE + 0x50)
+#define FLASH_ACFG_1_1             (TCMIF_BASE + 0x54)
+#define FLASH_ACFG_2_1             (TCMIF_BASE + 0x58)
+#define FLASH_ACFG_3_1             (TCMIF_BASE + 0x5C)
+
+
+
+/***************************************************************************
+ * OMAP730 Interrupt handlers
+ **************************************************************************/
+
+#define OMAP_IH1_BASE		0xFFFECB00     /* MPU Level 1 IRQ handler */
+#define OMAP_IH2_BASE           0xfffe0000
+
+
+
+/***************************************************************************
+ * OMAP730 Timers
+ *
+ * There are three general purpose OS timers in the 730 that can be 
+ * configured in autoreload or one-shot modes.
+ **************************************************************************/
+
+#define OMAP730_32kHz_TIMER_BASE  0xFFFB9000
+
+/* 32k Timer Registers */
+#define TIMER32k_CR               0x08
+#define TIMER32k_TVR              0x00
+#define TIMER32k_TCR              0x04
+
+/* 32k Timer Control Register definition */
+#define TIMER32k_TSS              (1<<0)
+#define TIMER32k_TRB              (1<<1)
+#define TIMER32k_INT              (1<<2)
+#define TIMER32k_ARL              (1<<3)
+
+/* MPU Timer base addresses  */
+#define OMAP730_MPUTIMER_BASE	0xfffec500
+#define OMAP730_MPUTIMER_OFF	0x00000100
+
+#define OMAP730_TIMER1_BASE	0xFFFEC500
+#define OMAP730_TIMER2_BASE	0xFFFEC600
+#define OMAP730_TIMER3_BASE	0xFFFEC700
+
+/* MPU Timer Register offsets */
+#define CNTL_TIMER	           0x00   /* MPU_CNTL_TIMER */
+#define LOAD_TIM	           0x04   /* MPU_LOAD_TIMER */
+#define READ_TIM	           0x08   /* MPU_READ_TIMER */
+
+/* MPU_CNTL_TIMER register bits */
+#define MPUTIM_FREE               (1<<6)
+#define MPUTIM_CLOCK_ENABLE       (1<<5)
+#define MPUTIM_PTV_MASK           (0x7<<PTV_BIT)
+#define MPUTIM_PTV_BIT            2
+#define MPUTIM_AR                 (1<<1)
+#define MPUTIM_ST                 (1<<0)
+
+
+
+/***************************************************************************
+ * OMAP730 GPIO
+ *
+ * The GPIO control is split over 6 register bases in the OMAP730 to allow
+ * access to all the (6 x 32) GPIO pins!
+ **************************************************************************/
+
+#define OMAP730_GPIO_BASE_1        0xFFFBC000
+#define OMAP730_GPIO_BASE_2        0xFFFBC800
+#define OMAP730_GPIO_BASE_3        0xFFFBD000
+#define OMAP730_GPIO_BASE_4        0xFFFBD800
+#define OMAP730_GPIO_BASE_5        0xFFFBE000
+#define OMAP730_GPIO_BASE_6        0xFFFBE800
+
+#define GPIO_DATA_INPUT            0x00
+#define GPIO_DATA_OUTPUT           0x04
+#define GPIO_DIRECTION_CONTROL     0x08
+#define GPIO_INTERRUPT_CONTROL     0x0C
+#define GPIO_INTERRUPT_MASK        0x10
+#define GPIO_INTERRUPT_STATUS      0x14
+
+#define GPIO_DATA_INPUT_1            ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_1           ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_1     ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_1     ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_1        ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_1      ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_STATUS))
+
+#define GPIO_DATA_INPUT_2            ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_2           ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_2     ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_2     ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_2        ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_2      ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_STATUS))
+
+#define GPIO_DATA_INPUT_3            ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_3           ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_3     ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_3     ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_3        ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_3      ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_STATUS))
+
+#define GPIO_DATA_INPUT_4            ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_4           ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_4     ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_4     ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_4        ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_4      ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_STATUS))
+
+#define GPIO_DATA_INPUT_5            ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_5           ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_5     ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_5     ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_5        ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_5      ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_STATUS))
+
+#define GPIO_DATA_INPUT_6            ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_6           ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_6     ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_6     ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_6        ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_6      ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_STATUS))
+
+
+
+
+/***************************************************************************
+ * OMAP730 Watchdog timers
+ **************************************************************************/
+
+#define WDTIM_BASE                 0xFFFEC800
+#define WDTIM_CONTROL              (WDTIM_BASE + 0x00)    /* MPU_CNTL_TIMER */
+#define WDTIM_LOAD                 (WDTIM_BASE + 0x04)    /* MPU_LOAD_TIMER */
+#define WDTIM_READ                 (WDTIM_BASE + 0x04)    /* MPU_READ_TIMER */
+#define WDTIM_MODE                 (WDTIM_BASE + 0x08)    /* MPU_TIMER_MODE */
+
+
+
+
+/***************************************************************************
+ * OMAP730 Interrupt Registers
+ **************************************************************************/
+
+/* Interrupt Register offsets */
+
+#define IRQ_ITR                               0x00  
+#define IRQ_MIR                               0x04
+#define IRQ_SIR_IRQ                           0x10
+#define IRQ_SIR_FIQ                           0x14
+#define IRQ_CONTROL_REG                       0x18
+#define IRQ_ILR0                              0x1C  /* ILRx == ILR0 + (0x4 * x) */
+#define IRQ_SIR                               0x9C  /* a.k.a.IRQ_ISR */
+#define IRQ_GMIR                              0xA0
+
+#define REG_IHL1_MIR  (OMAP_IH1_BASE + IRQ_MIR)
+#define REG_IHL2_MIR  (OMAP_IH2_BASE + IRQ_MIR)
+
+
+/***************************************************************************
+ * OMAP730 Intersystem Communication Register                      (TRM 4.5)
+ **************************************************************************/
+ 
+ 
+#define ICR_BASE                   0xFFFBB800
+ 
+#define M_ICR                      (ICR_BASE + 0x00)
+#define G_ICR                      (ICR_BASE + 0x02)
+#define M_CTL                      (ICR_BASE + 0x04)
+#define G_CTL                      (ICR_BASE + 0x06)
+#define PM_BA                      (ICR_BASE + 0x0A)
+#define DM_BA                      (ICR_BASE + 0x0C)
+#define RM_BA                      (ICR_BASE + 0x0E)
+#define SSPI_TAS                   (ICR_BASE + 0x12)
+
+
+
+#endif /* ! __INCLUDED_OMAP730_H */
diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h
new file mode 100644
index 00000000000..fe200c1cec5
--- /dev/null
+++ b/include/configs/omap730p2.h
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2003-2004 
+ * MPC Data Limited (http://www.mpc-data.co.uk)
+ * Dave Peverley <dpeverley at mpc-data.co.uk>
+ *
+ * Configuation settings for the TI OMAP Perseus 2 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+
+#define CONFIG_INIT_CRITICAL                 /* undef for developing */
+
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_ARM926EJS           1         /* This is an arm926ejs CPU core  */
+#define CONFIG_OMAP                1         /* in a TI OMAP core    */
+#define CONFIG_OMAP730             1         /* which is in a 730  */
+#define CONFIG_P2_OMAP730          1         /*  a Perseus 2 Board  */
+
+
+/* 
+ * Input clock of PLL 
+ * The OMAP730 Perseus 2 has 13MHz input clock 
+ */
+
+#define CONFIG_SYS_CLK_FREQ        13000000
+
+#undef CONFIG_USE_IRQ                        /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG         1         /* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS   1
+
+
+/*
+ * Size of malloc() pool
+ */
+
+#define CFG_MALLOC_LEN             (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE          128       /* size in bytes reserved for initial data */
+
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE       0x04000300
+#define CONFIG_LAN91C96_EXT_PHY
+
+
+/*
+ * NS16550 Configuration
+ */
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE       (1)
+#define CFG_NS16550_CLK            (48000000)     /* can be 12M/32Khz or 48Mhz */
+#define CFG_NS16550_COM1           0xfffb0000     /* uart1, bluetooth uart
+                                                   * on perseus */
+
+/*
+ * select serial console configuration
+ */
+
+#define CONFIG_SERIAL1             1         /* we use SERIAL 1 on OMAP730 Perseus 2 */
+
+
+#define CONFIG_CONS_INDEX          1
+#define CONFIG_BAUDRATE            115200
+#define CFG_BAUDRATE_TABLE         { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_COMMANDS            (CONFIG_CMD_DFL | CFG_CMD_DHCP)
+#define CONFIG_BOOTP_MASK          CONFIG_BOOTP_DEFAULT
+
+/* 
+ * This must be included AFTER the definition of CONFIG_COMMANDS (if any) 
+ */
+
+#include <cmd_confdefs.h>
+#include <configs/omap730.h>
+#include <configs/h2_p2_dbg_board.h>
+
+#define CONFIG_BOOTDELAY           3
+#define CONFIG_BOOTARGS            "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
+
+#define CONFIG_LOADADDR            0x10000000
+
+#define CONFIG_ETHADDR
+#define CONFIG_NETMASK             255.255.255.0
+#define CONFIG_IPADDR              192.168.0.23
+#define CONFIG_SERVERIP            192.150.0.100
+#define CONFIG_BOOTFILE            "uImage"  /* File to load */
+
+#if defined (CONFIG_COMMANDS) && defined (CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE       115200    /* Speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX      1         /* Which serial port to use */
+#endif
+
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CFG_LONGHELP                                   /* undef to save memory     */
+#define CFG_PROMPT                 "OMAP730 P2 # "     /* Monitor Command Prompt   */
+#define CFG_CBSIZE                 256                 /* Console I/O Buffer Size  */
+/* Print Buffer Size */
+#define CFG_PBSIZE                 (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS                16                  /* max number of command args   */
+#define CFG_BARGSIZE               CFG_CBSIZE          /* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START          0x10000000          /* memtest works on */
+#define CFG_MEMTEST_END            0x12000000          /* 32 MB in DRAM    */
+
+#undef CFG_CLKS_IN_HZ                /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR              0x10000000          /* default load address */
+
+
+/* The OMAP730 has 3 general purpose MPU timers, they can be driven by 
+ * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a 
+ * local divisor.
+ */
+
+#define CFG_TIMERBASE              0xFFFEC500          /* use timer 1 */
+#define CFG_PVT                    7                   /* 2^(pvt+1), divide by 256 */
+#define CFG_HZ                     ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+
+#define CONFIG_STACKSIZE           (128*1024)     /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ       (4*1024)       /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ       (4*1024)       /* FIQ stack */
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+#define CONFIG_NR_DRAM_BANKS       1              /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1               0x10000000     /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE          0x02000000     /* 32 MB */
+
+#if defined(CONFIG_CS0_BOOT)
+#define PHYS_FLASH_1               0x0C000000
+#elif defined(CONFIG_CS3_BOOT)
+#define PHYS_FLASH_1               0x00000000
+#else
+#error Unknown Boot Chip-Select number
+#endif
+
+#define CFG_FLASH_BASE             PHYS_FLASH_1
+
+
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CFG_MAX_FLASH_BANKS        1              /* max number of memory banks */
+#define PHYS_FLASH_SIZE            0x02000000     /* 32MB */
+#define CFG_MAX_FLASH_SECT         (259)          /* max number of sectors on one chip */
+/* addr of environment */
+#define CFG_ENV_ADDR               (CFG_FLASH_BASE + 0x020000)
+
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT        (20*CFG_HZ)   /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT        (20*CFG_HZ)   /* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH        1
+#define CFG_ENV_SIZE               0x20000        /* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET             0x20000        /* environment starts here  */
+
+
+
+#endif    /* ! __CONFIG_H */
diff --git a/include/ns16550.h b/include/ns16550.h
index 4dd39fee328..5890246a877 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -19,6 +19,18 @@ struct NS16550 {
 	unsigned char lsr;		/* 5 */
 	unsigned char msr;		/* 6 */
 	unsigned char scr;		/* 7 */
+#if defined(CONFIG_OMAP730)
+	unsigned char mdr1;		/* 8 */
+	unsigned char reg9;		/* 9 */
+	unsigned char regA;		/* A */
+	unsigned char regB;		/* B */
+	unsigned char regC;		/* C */
+	unsigned char regD;		/* D */
+	unsigned char regE;		/* E */
+	unsigned char regF;		/* F */
+	unsigned char reg10;		/* 10 */
+	unsigned char ssr;		/* 11*/
+#endif
 } __attribute__ ((packed));
 #elif (CFG_NS16550_REG_SIZE == 2)
 struct NS16550 {