Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv

- Update qemu-riscv.rst build instructions.
- Add support for SPI on Kendryte K210.
- Add Microchip PolarFire SoC Icicle Kit support.
- Add support for an early timer.
  - Select TIMER_EARLY to avoid infinite recursion for Trace.

6 files changed, 85 insertions, 41 deletions

diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h
index b2606e794dd..bd9c371f835 100644
--- a/include/configs/ax25-ae350.h
+++ b/include/configs/ax25-ae350.h
@@ -17,6 +17,11 @@
 #endif
 #endif
 
+#define RISCV_MMODE_TIMERBASE           0xe6000000
+#define RISCV_MMODE_TIMER_FREQ          60000000
+
+#define RISCV_SMODE_TIMER_FREQ          60000000
+
 /*
  * CPU and Board Configuration Options
  */
diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h
index 8a7470545b9..24990370cf0 100644
--- a/include/configs/microchip_mpfs_icicle.h
+++ b/include/configs/microchip_mpfs_icicle.h
@@ -7,53 +7,34 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/*
- * CPU and Board Configuration Options
- */
+#include <linux/sizes.h>
 
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_SDRAM_BASE       0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR     (CONFIG_SYS_SDRAM_BASE + SZ_2M)
 
-/*
- * Print Buffer Size
- */
-#define CONFIG_SYS_PBSIZE	\
-	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LOAD_ADDR        (CONFIG_SYS_SDRAM_BASE + SZ_2M)
 
-/*
- * max number of command args
- */
-#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_MALLOC_LEN       SZ_8M
 
-/*
- * Boot Argument Buffer Size
- */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * Size of malloc() pool
- * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough
- */
-#define CONFIG_SYS_MALLOC_LEN	(512 << 10)
+#define CONFIG_SYS_BOOTM_LEN        SZ_64M
 
-/*
- * Physical Memory Map
- */
-#define PHYS_SDRAM_0		0x80000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_0_SIZE	0x40000000 /* 1 GB */
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_0
+#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
 
-/* Init Stack Pointer */
-#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x200000)
+/* Environment options */
 
-#define CONFIG_SYS_LOAD_ADDR	0x80000000 /* SDRAM */
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(DHCP, dhcp, na)
 
-/*
- * memtest works on DRAM
- */
+#include <config_distro_bootcmd.h>
 
-/* When we use RAM as ENV */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"kernel_addr_r=0x84000000\0" \
+	"fdt_addr_r=0x88000000\0" \
+	"scriptaddr=0x88100000\0" \
+	"pxefile_addr_r=0x88200000\0" \
+	"ramdisk_addr_r=0x88300000\0" \
+	BOOTENV
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index a2f33587c24..5291de83f8d 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -29,6 +29,11 @@
 
 #define CONFIG_STANDALONE_LOAD_ADDR	0x80200000
 
+#define RISCV_MMODE_TIMERBASE		0x2000000
+#define RISCV_MMODE_TIMER_FREQ		1000000
+
+#define RISCV_SMODE_TIMER_FREQ		1000000
+
 /* Environment options */
 
 #ifndef CONFIG_SPL_BUILD
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
index c1c79db1474..0d69d1c5482 100644
--- a/include/configs/sifive-fu540.h
+++ b/include/configs/sifive-fu540.h
@@ -36,6 +36,11 @@
 
 #define CONFIG_STANDALONE_LOAD_ADDR	0x80200000
 
+#define RISCV_MMODE_TIMERBASE		0x2000000
+#define RISCV_MMODE_TIMER_FREQ		1000000
+
+#define RISCV_SMODE_TIMER_FREQ		1000000
+
 /* Environment options */
 
 #ifndef CONFIG_SPL_BUILD
diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h
index 36ff522e4b6..08acb25075b 100644
--- a/include/configs/sipeed-maix.h
+++ b/include/configs/sipeed-maix.h
@@ -24,10 +24,13 @@
 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x80060000\0" \
-	"fdt_addr_r=0x80028000\0" \
+	"fdt_addr_r=0x80400000\0" \
 	"scriptaddr=0x80020000\0" \
 	"kernel_addr_r=0x80060000\0" \
-	"fdtfile=kendryte/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
+	"fdtfile=kendryte/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+	"k210_bootcmd=load mmc 0:1 $loadaddr /uImage && " \
+		"load mmc 0:1 $fdt_addr_r /k210.dtb && " \
+		"bootm $loadaddr - $fdt_addr_r\0"
 #endif
 
 #endif /* CONFIGS_SIPEED_MAIX_H */
diff --git a/include/dt-bindings/clock/microchip-mpfs-clock.h b/include/dt-bindings/clock/microchip-mpfs-clock.h
new file mode 100644
index 00000000000..55fe64693f6
--- /dev/null
+++ b/include/dt-bindings/clock/microchip-mpfs-clock.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (C) 2020 Microchip Technology Inc.
+ * Padmarao Begari <padmarao.begari@microchip.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
+#define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
+
+#define CLK_CPU		0
+#define CLK_AXI		1
+#define CLK_AHB		2
+
+#define CLK_ENVM	3
+#define CLK_MAC0	4
+#define CLK_MAC1	5
+#define CLK_MMC		6
+#define CLK_TIMER	7
+#define CLK_MMUART0	8
+#define CLK_MMUART1	9
+#define CLK_MMUART2	10
+#define CLK_MMUART3	11
+#define CLK_MMUART4	12
+#define CLK_SPI0	13
+#define CLK_SPI1	14
+#define CLK_I2C0	15
+#define CLK_I2C1	16
+#define CLK_CAN0	17
+#define CLK_CAN1	18
+#define CLK_USB		19
+#define CLK_RESERVED	20
+#define CLK_RTC		21
+#define CLK_QSPI	22
+#define CLK_GPIO0	23
+#define CLK_GPIO1	24
+#define CLK_GPIO2	25
+#define CLK_DDRC	26
+#define CLK_FIC0	27
+#define CLK_FIC1	28
+#define CLK_FIC2	29
+#define CLK_FIC3	30
+#define CLK_ATHENA	31
+#define CLK_CFM		32
+
+#endif	/* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */