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authorJimmy Zhang <jimmzhang@nvidia.com>2012-05-01 16:35:57 -0700
committerGerrit <chrome-bot@google.com>2012-07-18 23:30:56 -0700
commit48ca7acfd6690b06f7e72a66f5bd741dca36be42 (patch)
tree0baa1c60e1976ed5a7e6593b43ebf67abfc9230c /include
parent13f56163c945c3838f84cb449180595d8581d2ee (diff)
tegra: config: Change load entry to 0x108000/0x80108000
0x108000/0x80108000 is used as tegra2/tegra3's default boot loader entry address. This change makes u-boot to comply with nvidia standard flash tools. BUG=none TEST=run cros_write_firmware with local build u-boot. Kernel boots up fine. Change-Id: I55e9b5d1847cf7e6a94d362935deef5f6855ba5a Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/21979 Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include')
-rw-r--r--include/configs/tegra2-common.h2
-rw-r--r--include/configs/tegra3-common.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index 8396dc4d3b0..9b8f7242da9 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -156,7 +156,7 @@
#define PHYS_SDRAM_1 TEGRA_SDRC_CS0
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_TEXT_BASE 0x00E08000
+#define CONFIG_SYS_TEXT_BASE 0x00108000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define BCT_SDRAM_PARAMS_OFFSET (BCT_OFFSET + 0x88)
diff --git a/include/configs/tegra3-common.h b/include/configs/tegra3-common.h
index ea391c19009..4a42c63e468 100644
--- a/include/configs/tegra3-common.h
+++ b/include/configs/tegra3-common.h
@@ -131,7 +131,7 @@
#define PHYS_SDRAM_1 TEGRA_SDRC_CS0
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GB */
-#define CONFIG_SYS_TEXT_BASE 0x80E08000
+#define CONFIG_SYS_TEXT_BASE 0x80108000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_INITRD_TAG /* enable initrd ATAG */