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authorMarkus Klotzbücher <Markus Klotzbümk@pollux.denx.de>2006-03-06 15:04:25 +0100
committerMarkus Klotzbücher <mk@pollux.denx.de>2006-03-06 15:04:25 +0100
commit43638c674a1bc57eef41439e87c281269a08cb16 (patch)
treec42d1e3340add6c4b4099ea59b603ecffbe0430d /include
parentf9e029184be5ef550d05262e0f150d31fb09d19b (diff)
Cleanup of NAND support of delta board using the Monahans Data Flash
Controller.
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h17
-rw-r--r--include/configs/delta.h22
2 files changed, 37 insertions, 2 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 6236405b3a6..5d36b84b07c 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -880,6 +880,8 @@ typedef void (*ExcpHndlr) (void) ;
#define OMCR9 __REG(0x40A000D4) /* OS Match Control Register 9 */
#define OMCR10 __REG(0x40A000D8) /* OS Match Control Register 10 */
#define OMCR11 __REG(0x40A000DC) /* OS Match Control Register 11 */
+
+#define OSCR_CLK_FREQ 3.250 /* MHz */
#endif /* CONFIG_CPU_MONAHANS */
#define OSSR_M4 (1 << 4) /* Match status channel 4 */
@@ -2132,6 +2134,21 @@ typedef void (*ExcpHndlr) (void) ;
#define MCIO(s) MCIO0
#define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */
+/* Maximum values for NAND Interface Timing Registers in DFC clock
+ * periods */
+#define DFC_MAX_tCH 7
+#define DFC_MAX_tCS 7
+#define DFC_MAX_tWH 7
+#define DFC_MAX_tWP 7
+#define DFC_MAX_tRH 7
+#define DFC_MAX_tRP 15
+#define DFC_MAX_tR 65535
+#define DFC_MAX_tWHR 15
+#define DFC_MAX_tAR 15
+
+#define DFC_CLOCK 104 /* DFC Clock is 104 MHz */
+#define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */
+
#else /* CONFIG_CPU_MONAHANS */
#define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */
diff --git a/include/configs/delta.h b/include/configs/delta.h
index 3a94661cafb..2a0a8fd5eea 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -170,14 +170,32 @@
#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
-/* #define NAND_NO_RB */
#define NAND_DELAY_US 25 /* mk@tbd: could be 0, I guess */
/* nand timeout values */
#define CFG_NAND_PROG_ERASE_TO 3000
#define CFG_NAND_OTHER_TO 100
#define CFG_NAND_SENDCMD_RETRY 3
-#define NAND_ALLOW_ERASE_ALL 1
+#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
+
+/* NAND Timing Parameters (in ns) */
+#define NAND_TIMING_tCH 10
+#define NAND_TIMING_tCS 0
+#define NAND_TIMING_tWH 20
+#define NAND_TIMING_tWP 40
+
+#define NAND_TIMING_tRH 20
+#define NAND_TIMING_tRP 40
+
+#define NAND_TIMING_tR 11123
+/* #define NAND_TIMING_tWHR 110 */
+#define NAND_TIMING_tWHR 100
+#define NAND_TIMING_tAR 10
+
+/* NAND debugging */
+#define CFG_DFC_DEBUG1 /* usefull */
+#undef CFG_DFC_DEBUG2 /* noisy */
+#undef CFG_DFC_DEBUG3 /* extremly noisy */
#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE 1