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authorDhruva Gole <d-gole@ti.com>2022-11-17 17:41:02 +0530
committerAnand Gadiyar <gadiyar@ti.com>2022-11-21 09:33:37 -0600
commit449345c6b7442038205b298fff3a81fedebc16dc (patch)
tree692471d2b52925071695961493dcba3eb9bc5072 /include
parent15d6f04fd76c5646b5b609e2606425182710130b (diff)
mtd: spi-nor-core: Add fixups for Cypress s25hl-t/s25hs-t
Commit 1c3dd193b5ba76da9d5b2b422d04605321a91c94 upstream. The nor->ready() and spansion_sr_ready() introduced earlier in this series are used for multi-die package parts. The nor->quad_enable() sets the volatile QE bit on each die. The nor->erase() is hooked if the device is not configured to uniform sectors, assuming it has 32 x 4KB sectors overlaid on bottom address. Other configurations, top and split, are not supported at this point. Will submit additional patches to support it as needed. The post_bfpt/sfdp() fixes the params wrongly advertised in SFDP. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Signed-off-by: Dhruva Gole <d-gole@ti.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mtd/spi-nor.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 4e6e52ebfc..aa93aabd59 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -128,6 +128,9 @@
#define SPINOR_OP_WRAR 0x71 /* Write any register */
#define SPINOR_REG_ADDR_STR1V 0x00800000
#define SPINOR_REG_ADDR_CFR1V 0x00800002
+#define SPINOR_REG_ADDR_CFR3V 0x00800004
+#define CFR3V_UNHYSA BIT(3) /* Uniform sectors or not */
+#define CFR3V_PGMBUF BIT(4) /* Program buffer size */
/* Used for Micron flashes only. */
#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */