Merge git://git.denx.de/u-boot-rockchip

This adds a new firefly-rk3399 board, MIPI support for rk3399 and
rk3288, rk818 pmic support, mkimage improvements for rockchip and a few
other things.

7 files changed, 326 insertions, 78 deletions

diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index b7b89b08a88..49f56f23de5 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -18,6 +18,9 @@
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
+#if defined(CONFIG_SPL_SPI_SUPPORT)
+#define CONFIG_SPL_SPI_LOAD
+#endif
 
 #define COUNTER_FREQUENCY               24000000
 
diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h
index ecb76c7808a..0798287e6fc 100644
--- a/include/dt-bindings/pinctrl/rockchip.h
+++ b/include/dt-bindings/pinctrl/rockchip.h
@@ -4,7 +4,7 @@
  * Copyright (c) 2013 MundoReader S.L.
  * Author: Heiko Stuebner <heiko@sntech.de>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__
@@ -17,6 +17,39 @@
 #define RK_GPIO4	4
 #define RK_GPIO6	6
 
+#define RK_PA0		0
+#define RK_PA1		1
+#define RK_PA2		2
+#define RK_PA3		3
+#define RK_PA4		4
+#define RK_PA5		5
+#define RK_PA6		6
+#define RK_PA7		7
+#define RK_PB0		8
+#define RK_PB1		9
+#define RK_PB2		10
+#define RK_PB3		11
+#define RK_PB4		12
+#define RK_PB5		13
+#define RK_PB6		14
+#define RK_PB7		15
+#define RK_PC0		16
+#define RK_PC1		17
+#define RK_PC2		18
+#define RK_PC3		19
+#define RK_PC4		20
+#define RK_PC5		21
+#define RK_PC6		22
+#define RK_PC7		23
+#define RK_PD0		24
+#define RK_PD1		25
+#define RK_PD2		26
+#define RK_PD3		27
+#define RK_PD4		28
+#define RK_PD5		29
+#define RK_PD6		30
+#define RK_PD7		31
+
 #define RK_FUNC_GPIO	0
 #define RK_FUNC_1	1
 #define RK_FUNC_2	2
diff --git a/include/dt-bindings/power/rk3399-power.h b/include/dt-bindings/power/rk3399-power.h
new file mode 100644
index 00000000000..168b3bfbd6f
--- /dev/null
+++ b/include/dt-bindings/power/rk3399-power.h
@@ -0,0 +1,53 @@
+#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__
+#define __DT_BINDINGS_POWER_RK3399_POWER_H__
+
+/* VD_CORE_L */
+#define RK3399_PD_A53_L0	0
+#define RK3399_PD_A53_L1	1
+#define RK3399_PD_A53_L2	2
+#define RK3399_PD_A53_L3	3
+#define RK3399_PD_SCU_L		4
+
+/* VD_CORE_B */
+#define RK3399_PD_A72_B0	5
+#define RK3399_PD_A72_B1	6
+#define RK3399_PD_SCU_B		7
+
+/* VD_LOGIC */
+#define RK3399_PD_TCPD0		8
+#define RK3399_PD_TCPD1		9
+#define RK3399_PD_CCI		10
+#define RK3399_PD_CCI0		11
+#define RK3399_PD_CCI1		12
+#define RK3399_PD_PERILP	13
+#define RK3399_PD_PERIHP	14
+#define RK3399_PD_VIO		15
+#define RK3399_PD_VO		16
+#define RK3399_PD_VOPB		17
+#define RK3399_PD_VOPL		18
+#define RK3399_PD_ISP0		19
+#define RK3399_PD_ISP1		20
+#define RK3399_PD_HDCP		21
+#define RK3399_PD_GMAC		22
+#define RK3399_PD_EMMC		23
+#define RK3399_PD_USB3		24
+#define RK3399_PD_EDP		25
+#define RK3399_PD_GIC		26
+#define RK3399_PD_SD		27
+#define RK3399_PD_SDIOAUDIO	28
+#define RK3399_PD_ALIVE		29
+
+/* VD_CENTER */
+#define RK3399_PD_CENTER	30
+#define RK3399_PD_VCODEC	31
+#define RK3399_PD_VDU		32
+#define RK3399_PD_RGA		33
+#define RK3399_PD_IEP		34
+
+/* VD_GPU */
+#define RK3399_PD_GPU		35
+
+/* VD_PMU */
+#define RK3399_PD_PMU		36
+
+#endif
diff --git a/include/i2c_eeprom.h b/include/i2c_eeprom.h
index 04528928126..bb5c6b118b9 100644
--- a/include/i2c_eeprom.h
+++ b/include/i2c_eeprom.h
@@ -20,4 +20,28 @@ struct i2c_eeprom {
 	unsigned pagewidth;
 };
 
+/*
+ * i2c_eeprom_read() - read bytes from an I2C EEPROM chip
+ *
+ * @dev:	Chip to read from
+ * @offset:	Offset within chip to start reading
+ * @buf:	Place to put data
+ * @size:	Number of bytes to read
+ *
+ * @return 0 on success, -ve on failure
+ */
+int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf, int size);
+
+/*
+ * i2c_eeprom_write() - write bytes to an I2C EEPROM chip
+ *
+ * @dev:	Chip to write to
+ * @offset:	Offset within chip to start writing
+ * @buf:	Buffer containing data to write
+ * @size:	Number of bytes to write
+ *
+ * @return 0 on success, -ve on failure
+ */
+int i2c_eeprom_write(struct udevice *dev, int offset, uint8_t *buf, int size);
+
 #endif
diff --git a/include/power/rk808_pmic.h b/include/power/rk808_pmic.h
deleted file mode 100644
index fb0800b9cb5..00000000000
--- a/include/power/rk808_pmic.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (C) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PMIC_RK808_H_
-#define _PMIC_RK808_H_
-
-enum {
-	REG_DCDC_EN			= 0x23,
-	REG_LDO_EN,
-	REG_SLEEP_SET_OFF1,
-	REG_SLEEP_SET_OFF2,
-	REG_DCDC_UV_STS,
-
-	REG_DCDC_UV_ACT,
-	REG_LDO_UV_STS,
-	REG_LDO_UV_ACT,
-	REG_DCDC_PG,
-	REG_LDO_PG,
-	REG_VOUT_MON_TDB,
-	REG_BUCK1_CONFIG,
-	REG_BUCK1_ON_VSEL,
-
-	REG_BUCK1_SLP_VSEL,
-	REG_BUCK1_DVS_VSEL,
-	REG_BUCK2_CONFIG,
-	REG_BUCK2_ON_VSEL,
-	REG_BUCK2_SLP_VSEL,
-	REG_BUCK2_DVS_VSEL,
-	REG_BUCK3_CONFIG,
-	REG_BUCK4_CONFIG,
-
-	REG_BUCK4_ON_VSEL,
-	REG_BUCK4_SLP_VSEL,
-	LDO1_ON_VSEL			= 0x3b,
-	LDO1_SLP_VSEL,
-	LDO2_ON_VSEL,
-	LDO2_SLP_VSEL,
-	LDO3_ON_VSEL,
-
-	LDO3_SLP_VSEL,
-	LDO4_ON_VSEL,
-	LDO4_SLP_VSEL,
-	LDO5_ON_VSEL,
-	LDO5_SLP_VSEL,
-	LDO6_ON_VSEL,
-	LDO6_SLP_VSEL,
-	LDO7_ON_VSEL,
-
-	LDO7_SLP_VSEL,
-	LDO8_ON_VSEL,
-	LDO8_SLP_VSEL,
-	DEVCTRL,
-	INT_STS1,
-	INT_STS_MSK1,
-	INT_STS2,
-	INT_STS_MSK2,
-	IO_POL,
-
-	/* Not sure what this does */
-	DCDC_ILMAX			= 0x90,
-
-	RK808_NUM_OF_REGS,
-};
-
-struct rk808_reg_table {
-	char *name;
-	u8 reg_ctl;
-	u8 reg_vol;
-};
-
-int rk808_spl_configure_buck(struct udevice *pmic, int buck, int uvolt);
-
-#endif
diff --git a/include/power/rk8xx_pmic.h b/include/power/rk8xx_pmic.h
new file mode 100644
index 00000000000..589f8c4e1a9
--- /dev/null
+++ b/include/power/rk8xx_pmic.h
@@ -0,0 +1,193 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PMIC_RK8XX_H_
+#define _PMIC_RK8XX_H_
+
+enum {
+	REG_SECONDS			= 0x00,
+	REG_MINUTES,
+	REG_HOURS,
+	REG_DAYS,
+	REG_MONTHS,
+	REG_YEARS,
+	REG_WEEKS,
+	REG_ALARM_SECONDS,
+	REG_ALARM_MINUTES,
+	REG_ALARM_HOURS,
+	REG_ALARM_DAYS,
+	REG_ALARM_MONTHS,
+	REG_ALARM_YEARS,
+
+	REG_RTC_CTRL			= 0x10,
+	REG_RTC_STATUS,
+	REG_RTC_INT,
+	REG_RTC_COMP_LSB,
+	REG_RTC_COMP_MSB,
+
+	ID_MSB				= 0x17,
+	ID_LSB,
+
+	REG_CLK32OUT			= 0x20,
+	REG_VB_MON,
+	REG_THERMAL,
+	REG_DCDC_EN,
+	REG_LDO_EN,
+	REG_SLEEP_SET_OFF1,
+	REG_SLEEP_SET_OFF2,
+	REG_DCDC_UV_STS,
+	REG_DCDC_UV_ACT,
+	REG_LDO_UV_STS,
+	REG_LDO_UV_ACT,
+	REG_DCDC_PG,
+	REG_LDO_PG,
+	REG_VOUT_MON_TDB,
+	REG_BUCK1_CONFIG,
+	REG_BUCK1_ON_VSEL,
+	REG_BUCK1_SLP_VSEL,
+	REG_BUCK1_DVS_VSEL,
+	REG_BUCK2_CONFIG,
+	REG_BUCK2_ON_VSEL,
+	REG_BUCK2_SLP_VSEL,
+	REG_BUCK2_DVS_VSEL,
+	REG_BUCK3_CONFIG,
+	REG_BUCK4_CONFIG,
+	REG_BUCK4_ON_VSEL,
+	REG_BUCK4_SLP_VSEL,
+	REG_BOOST_CONFIG_REG,
+	REG_LDO1_ON_VSEL,
+	REG_LDO1_SLP_VSEL,
+	REG_LDO2_ON_VSEL,
+	REG_LDO2_SLP_VSEL,
+	REG_LDO3_ON_VSEL,
+	REG_LDO3_SLP_VSEL,
+	REG_LDO4_ON_VSEL,
+	REG_LDO4_SLP_VSEL,
+	REG_LDO5_ON_VSEL,
+	REG_LDO5_SLP_VSEL,
+	REG_LDO6_ON_VSEL,
+	REG_LDO6_SLP_VSEL,
+	REG_LDO7_ON_VSEL,
+	REG_LDO7_SLP_VSEL,
+	REG_LDO8_ON_VSEL,
+	REG_LDO8_SLP_VSEL,
+	REG_DEVCTRL,
+	REG_INT_STS1,
+	REG_INT_STS_MSK1,
+	REG_INT_STS2,
+	REG_INT_STS_MSK2,
+	REG_IO_POL,
+	REG_OTP_VDD_EN,
+	REG_H5V_EN,
+	REG_SLEEP_SET_OFF,
+	REG_BOOST_LDO9_ON_VSEL,
+	REG_BOOST_LDO9_SLP_VSEL,
+	REG_BOOST_CTRL,
+
+	/* Not sure what this does */
+	REG_DCDC_ILMAX			= 0x90,
+	REG_CHRG_COMP			= 0x9a,
+	REG_SUP_STS			= 0xa0,
+	REG_USB_CTRL,
+	REG1_CHRG_CTRL,
+	REG2_CHRG_CTRL,
+	REG3_CHRG_CTRL,
+	REG_BAT_CTRL,
+	REG_BAT_HTS_TS1,
+	REG_BAT_LTS_TS1,
+	REG_BAT_HTS_TS2,
+	REG_BAT_LTS_TS2,
+	REG_TS_CTRL,
+	REG_ADC_CTRL,
+	REG_ON_SOURCE,
+	REG_OFF_SOURCE,
+	REG_GGCON,
+	REG_GGSTS,
+	REG_FRAME_SMP_INTERV,
+	REG_AUTO_SLP_CUR_THR,
+	REG3_GASCNT_CAL,
+	REG2_GASCNT_CAL,
+	REG1_GASCNT_CAL,
+	REG0_GASCNT_CAL,
+	REG3_GASCNT,
+	REG2_GASCNT,
+	REG1_GASCNT,
+	REG0_GASCNT,
+	REGH_BAT_CUR_AVG,
+	REGL_BAT_CUR_AVG,
+	REGH_TS1_ADC,
+	REGL_TS1_ADC,
+	REGH_TS2_ADC,
+	REGL_TS2_ADC,
+	REGH_BAT_OCV,
+	REGL_BAT_OCV,
+	REGH_BAT_VOL,
+	REGL_BAT_VOL,
+	REGH_RELAX_ENTRY_THRES,
+	REGL_RELAX_ENTRY_THRES,
+	REGH_RELAX_EXIT_THRES,
+	REGL_RELAX_EXIT_THRES,
+	REGH_RELAX_VOL1,
+	REGL_RELAX_VOL1,
+	REGH_RELAX_VOL2,
+	REGL_RELAX_VOL2,
+	REGH_BAT_CUR_R_CALC,
+	REGL_BAT_CUR_R_CALC,
+	REGH_BAT_VOL_R_CALC,
+	REGL_BAT_VOL_R_CALC,
+	REGH_CAL_OFFSET,
+	REGL_CAL_OFFSET,
+	REG_NON_ACT_TIMER_CNT,
+	REGH_VCALIB0,
+	REGL_VCALIB0,
+	REGH_VCALIB1,
+	REGL_VCALIB1,
+	REGH_IOFFSET,
+	REGL_IOFFSET,
+	REG_SOC,
+	REG3_REMAIN_CAP,
+	REG2_REMAIN_CAP,
+	REG1_REMAIN_CAP,
+	REG0_REMAIN_CAP,
+	REG_UPDAT_LEVE,
+	REG3_NEW_FCC,
+	REG2_NEW_FCC,
+	REG1_NEW_FCC,
+	REG0_NEW_FCC,
+	REG_NON_ACT_TIMER_CNT_SAVE,
+	REG_OCV_VOL_VALID,
+	REG_REBOOT_CNT,
+	REG_POFFSET,
+	REG_MISC_MARK,
+	REG_HALT_CNT,
+	REGH_CALC_REST,
+	REGL_CALC_REST,
+	SAVE_DATA19,
+	RK808_NUM_OF_REGS,
+};
+
+enum {
+	RK805_ID = 0x8050,
+	RK808_ID = 0x0000,
+	RK818_ID = 0x8180,
+};
+
+#define RK8XX_ID_MSK	0xfff0
+
+struct rk8xx_reg_table {
+	char *name;
+	u8 reg_ctl;
+	u8 reg_vol;
+};
+
+struct rk8xx_priv {
+	int variant;
+};
+
+int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt);
+
+#endif
diff --git a/include/pwm.h b/include/pwm.h
index 851915eb87a..ebee227a670 100644
--- a/include/pwm.h
+++ b/include/pwm.h
@@ -34,6 +34,15 @@ struct pwm_ops {
 	 * @return 0 if OK, -ve on error
 	 */
 	int (*set_enable)(struct udevice *dev, uint channel, bool enable);
+	/**
+	 * set_invert() - Set the PWM invert
+	 *
+	 * @dev:        PWM device to update
+	 * @channel:    PWM channel to update
+	 * @polarity:   true to invert, false to keep normal polarity
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_invert)(struct udevice *dev, uint channel, bool polarity);
 };
 
 #define pwm_get_ops(dev)	((struct pwm_ops *)(dev)->driver->ops)
@@ -60,6 +69,16 @@ int pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
  */
 int pwm_set_enable(struct udevice *dev, uint channel, bool enable);
 
+/**
+ * pwm_set_invert() - Set pwm default polarity
+ *
+ * @dev:	PWM device to update
+ * @channel:	PWM channel to update
+ * @polarity:	true to invert, false to keep normal polarity
+ * @return 0 if OK, -ve on error
+ */
+int pwm_set_invert(struct udevice *dev, uint channel, bool polarity);
+
 /* Legacy interface */
 #ifndef CONFIG_DM_PWM
 int	pwm_init		(int pwm_id, int div, int invert);