diff options
| author | Ye Li <ye.li@nxp.com> | 2018-05-27 23:06:21 -0700 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2018-05-31 06:17:26 -0700 |
| commit | 9fa89220efab2cf36b95b440eeb34fbe1479dcc6 (patch) | |
| tree | 9062793b18b3fe85222250f6c003a91231e97359 /include | |
| parent | a3602fbc7b78bc82eb58160a7c5d94416a91f979 (diff) | |
MLK-18458-2 mx6ull_arm2: Add 14x14 DDR3 ARM2 support
Porting the iMX6ULL 14x14 DDR3 ARM2 board codes from v2017.03.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/mx6ull_ddr3_arm2.h | 104 |
1 files changed, 104 insertions, 0 deletions
diff --git a/include/configs/mx6ull_ddr3_arm2.h b/include/configs/mx6ull_ddr3_arm2.h new file mode 100644 index 00000000000..183e11b1c6e --- /dev/null +++ b/include/configs/mx6ull_ddr3_arm2.h @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL 14x14 DDR3 ARM2. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6ULL_DDR3_ARM2_CONFIG_H +#define __MX6ULL_DDR3_ARM2_CONFIG_H + +#ifdef CONFIG_SPI_BOOT + +#define CONFIG_MXC_SPI +#elif defined CONFIG_NAND_BOOT +#define CONFIG_CMD_NAND +#endif + +#define BOOTARGS_CMA_SIZE "" + +#include "mx6ul_arm2.h" + +#define CONFIG_IOMUX_LPSR + +#define PHYS_SDRAM_SIZE SZ_1G + +/* + * TSC pins conflict with I2C1 bus, so after TSC + * hardware rework, need to disable i2c1 bus, also + * need to disable PMIC and ldo bypass check. + */ +#ifdef CONFIG_MX6ULL_DDR3_ARM2_TSC_REWORK +#undef CONFIG_LDO_BYPASS_CHECK +#undef CONFIG_SYS_I2C_MXC +#undef CONFIG_SYS_I2C +#undef CONFIG_CMD_I2C +#undef CONFIG_POWER_PFUZE100_I2C_ADDR +#undef CONFIG_POWER_PFUZE100 +#undef CONFIG_POWER_I2C +#undef CONFIG_POWER +#endif + +#ifdef CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_CS 0 +#endif + +#ifdef CONFIG_DM_ETH +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 1 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC0" +#endif +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE MII100 +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth1" +#else +#define CONFIG_ETHPRIME "FEC1" +#endif +#endif + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR +#endif + + +/* #define CONFIG_SPLASH_SCREEN*/ +/* #define CONFIG_MXC_EPDC*/ + +/* + * SPLASH SCREEN Configs + */ +#if defined(CONFIG_MXC_EPDC) +/* + * Framebuffer and LCD + */ +#define CONFIG_SPLASH_SCREEN + +#undef LCD_TEST_PATTERN +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */ +#define LCD_BPP LCD_MONOCHROME +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif + +#define CONFIG_MODULE_FUSE +#define CONFIG_OF_SYSTEM_SETUP + +#endif |