Merge with /home/m8/git/u-boot

4 files changed, 609 insertions, 36 deletions

diff --git a/include/asm-ppc/i2c.h b/include/asm-ppc/i2c.h
index 2a4ac0ff36c..fa9d164e9aa 100644
--- a/include/asm-ppc/i2c.h
+++ b/include/asm-ppc/i2c.h
@@ -87,7 +87,7 @@ typedef struct i2c
 #error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h
 #endif
 
-#ifdef CONFIG_MPC8349ADS
+#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
 /*
  * MPC8349 have two i2c bus
  */
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 5d284d46792..f704db63ff5 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -613,9 +613,9 @@ typedef struct gpio8349 {
 typedef struct ddr_cs_bnds{
 	u32 csbnds;
 #define CSBNDS_SA 0x00FF0000
-#define CSBNDS_SA_SHIFT   16
+#define CSBNDS_SA_SHIFT    8
 #define CSBNDS_EA 0x000000FF
-#define CSBNDS_EA_SHIFT    0
+#define CSBNDS_EA_SHIFT   24
 	u8  res0[4];
 } ddr_cs_bnds_t;
 
@@ -652,6 +652,8 @@ typedef struct ddr8349{
 #define TIMING_CFG1_ACTTOACT_SHIFT    4
 #define TIMING_CFG1_WRTORD   0x00000007
 #define TIMING_CFG1_WRTORD_SHIFT      0
+#define TIMING_CFG1_CASLAT_20 0x00030000  /* CAS latency = 2.0 */
+#define TIMING_CFG1_CASLAT_25 0x00040000  /* CAS latency = 2.5 */
 
 	u32 timing_cfg_2;       /**< SDRAM Timing Configuration 2 */
 #define TIMING_CFG2_CPO           0x0F000000
@@ -659,6 +661,7 @@ typedef struct ddr8349{
 #define TIMING_CFG2_ACSM          0x00080000
 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT   10
+#define TIMING_CFG2_CPO_DEF       0x00000000  /* default (= CASLAT + 1) */
 
 	u32 sdram_cfg;          /**< SDRAM Control Configuration */
 #define SDRAM_CFG_MEM_EN     0x80000000
@@ -672,6 +675,7 @@ typedef struct ddr8349{
 #define SDRAM_CFG_8_BE       0x00040000
 #define SDRAM_CFG_NCAP       0x00020000
 #define SDRAM_CFG_2T_EN      0x00008000
+#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
 
 	u8 res2[4];
 	u32 sdram_mode;         /**< SDRAM Mode Configuration */
@@ -679,6 +683,25 @@ typedef struct ddr8349{
 #define SDRAM_MODE_ESD_SHIFT   16
 #define SDRAM_MODE_SD  0x0000FFFF
 #define SDRAM_MODE_SD_SHIFT     0
+#define DDR_MODE_EXT_MODEREG    0x4000  /* select extended mode reg */
+#define DDR_MODE_EXT_OPMODE     0x3FF8  /* operating mode, mask */
+#define DDR_MODE_EXT_OP_NORMAL  0x0000  /* normal operation */
+#define DDR_MODE_QFC            0x0004  /* QFC / compatibility, mask */
+#define DDR_MODE_QFC_COMP       0x0000  /* compatible to older SDRAMs */
+#define DDR_MODE_WEAK           0x0002  /* weak drivers */
+#define DDR_MODE_DLL_DIS        0x0001  /* disable DLL */
+#define DDR_MODE_CASLAT         0x0070  /* CAS latency, mask */
+#define DDR_MODE_CASLAT_15      0x0010  /* CAS latency 1.5 */
+#define DDR_MODE_CASLAT_20      0x0020  /* CAS latency 2 */
+#define DDR_MODE_CASLAT_25      0x0060  /* CAS latency 2.5 */
+#define DDR_MODE_CASLAT_30      0x0030  /* CAS latency 3 */
+#define DDR_MODE_BTYPE_SEQ      0x0000  /* sequential burst */
+#define DDR_MODE_BTYPE_ILVD     0x0008  /* interleaved burst */
+#define DDR_MODE_BLEN_2         0x0001  /* burst length 2 */
+#define DDR_MODE_BLEN_4         0x0002  /* burst length 4 */
+#define DDR_REFINT_166MHZ_7US   1302        /* exact value for 7.8125 µs */
+#define DDR_BSTOPRE     256     /* use 256 cycles as a starting point */
+#define DDR_MODE_MODEREG        0x0000  /* select mode register */
 
 	u8 res3[8];
 	u32 sdram_interval;     /**< SDRAM Interval Configuration */
@@ -688,6 +711,9 @@ typedef struct ddr8349{
 #define SDRAM_INTERVAL_BSTOPRE_SHIFT    0
 	u8   res9[8];
 	u32  sdram_clk_cntl;
+#define DDR_SDRAM_CLK_CNTL_SS_EN		0x80000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05	0x02000000
+
 	u8 res4[0xCCC];
 	u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
 	u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
new file mode 100644
index 00000000000..96a1ad28fc9
--- /dev/null
+++ b/include/configs/TQM834x.h
@@ -0,0 +1,522 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * TQM8349 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define DEBUG
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC83XX		1	/* MPC83XX family */
+#define CONFIG_MPC834X		1	/* MPC834X specific */
+#define CONFIG_TQM834X		1	/* TQM834X board specific */
+
+/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
+#define CFG_IMMRBAR		0xff400000
+
+/* System clock. Primary input clock when in PCI host mode */
+#define CONFIG_83XX_CLKIN	66666000	/* 66,666 MHz */
+
+/*
+ * Local Bus LCRR
+ *    LCRR:  DLL bypass, Clock divider is 8
+ *
+ *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
+ *
+ * External Local Bus rate is
+ *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
+
+/* board pre init: do not call, nothing to do */
+#undef CONFIG_BOARD_EARLY_INIT_F
+
+/* detect the number of flash banks */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define DDR_CASLAT_25				/* CASLAT set to 2.5 */
+#undef CONFIG_DDR_ECC				/* only for ECC DDR module */
+#undef CONFIG_SPD_EEPROM			/* do not use SPD EEPROM for DDR setup */
+
+#undef CFG_DRAM_TEST				/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00000000	/* memtest region */
+#define CFG_MEMTEST_END		0x00100000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_BASE		0x80000000	/* start of FLASH   */
+
+/* buffered writes in the AMD chip set is not supported yet */
+#undef CFG_FLASH_USE_BUFFER_WRITE
+
+/*
+ * FLASH bank number detection
+ */
+
+/*
+ * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
+ * banks has to be determined at runtime and stored in a gloabl variable
+ * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only
+ * used insted of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
+ * should be made sufficiently large to accomodate the number of banks that
+ * might acutally be detected.  Since most (all?) Flash related functions use
+ * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is
+ * defined as tqm834x_num_flash_banks.
+ */
+#define CFG_MAX_FLASH_BANKS_DETECT	2
+#ifndef __ASSEMBLY__ 
+extern int tqm834x_num_flash_banks;
+#endif
+#define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
+
+#define CFG_MAX_FLASH_SECT		512	/* max sectors per device */
+
+/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
+#define CFG_BR0_PRELIM		((CFG_FLASH_BASE & BR_BA) | \
+					BR_MS_GPCM | BR_PS_32 | BR_V)
+
+/* FLASH timing (0x0000_0c54) */
+#define CFG_OR_TIMING_FLASH	(OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \
+					OR_GPCM_SCY_5 | OR_GPCM_TRLX)
+
+#define CFG_PRELIM_OR_AM	0xc0000000	/* OR addr mask: 1 GiB */
+
+#define CFG_OR0_PRELIM		(CFG_PRELIM_OR_AM  | CFG_OR_TIMING_FLASH)
+
+#define CFG_LBLAWAR0_PRELIM	0x8000001D	/* 1 GiB window size (2^(size + 1)) */
+#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* Window base at flash base */
+
+/* disable remaining mappings */
+#define CFG_BR1_PRELIM		0x00000000
+#define CFG_OR1_PRELIM		0x00000000
+#define CFG_LBLAWBAR1_PRELIM	0x00000000
+#define CFG_LBLAWAR1_PRELIM	0x00000000
+
+#define CFG_BR2_PRELIM		0x00000000
+#define CFG_OR2_PRELIM		0x00000000
+#define CFG_LBLAWBAR2_PRELIM	0x00000000
+#define CFG_LBLAWAR2_PRELIM	0x00000000
+
+#define CFG_BR3_PRELIM		0x00000000
+#define CFG_OR3_PRELIM		0x00000000
+#define CFG_LBLAWBAR3_PRELIM	0x00000000
+#define CFG_LBLAWAR3_PRELIM	0x00000000
+
+#define CFG_BR4_PRELIM		0x00000000
+#define CFG_OR4_PRELIM		0x00000000
+#define CFG_LBLAWBAR4_PRELIM	0x00000000
+#define CFG_LBLAWAR4_PRELIM	0x00000000
+
+#define CFG_BR5_PRELIM		0x00000000
+#define CFG_OR5_PRELIM		0x00000000
+#define CFG_LBLAWBAR5_PRELIM	0x00000000
+#define CFG_LBLAWAR5_PRELIM	0x00000000
+
+#define CFG_BR6_PRELIM		0x00000000
+#define CFG_OR6_PRELIM		0x00000000
+#define CFG_LBLAWBAR6_PRELIM	0x00000000
+#define CFG_LBLAWAR6_PRELIM	0x00000000
+
+#define CFG_BR7_PRELIM		0x00000000
+#define CFG_OR7_PRELIM		0x00000000
+#define CFG_LBLAWBAR7_PRELIM	0x00000000
+#define CFG_LBLAWAR7_PRELIM	0x00000000
+
+/*
+ * Monitor config
+ */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0x20000000	/* Initial RAM address */
+#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE  	0x100		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1	(CFG_IMMRBAR + 0x4500)
+#define CFG_NS16550_COM2	(CFG_IMMRBAR + 0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C				/* I2C with hardware support	*/
+#undef CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CFG_I2C_SPEED			400000	/* I2C speed: 400KHz		*/
+#define CFG_I2C_SLAVE			0x7F	/* slave address		*/
+#define CFG_I2C_OFFSET			0x3000
+
+/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x			*/
+#define CFG_I2C_EEPROM_ADDR_LEN		2	/* 16 bit			*/
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 32 bytes per write		*/
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	12	/* 10ms +/- 20%			*/
+#define CFG_I2C_MULTI_EEPROMS		1       /* more than one eeprom		*/
+
+/* I2C RTC */
+#define CONFIG_RTC_DS1337			/* use ds1337 rtc via i2c	*/
+#define CFG_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75			1	/* ON Semi's LM75		*/
+#define CONFIG_DTT_SENSORS		{0}	/* Sensor addresses		*/
+#define CFG_DTT_MAX_TEMP		70
+#define CFG_DTT_LOW_TEMP		-30
+#define CFG_DTT_HYSTERESIS		3
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_MII
+
+#define CFG_TSEC1_OFFSET	0x24000
+#define CFG_TSEC1		(CFG_IMMRBAR + CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET	0x25000
+#define CFG_TSEC2		(CFG_IMMRBAR + CFG_TSEC2_OFFSET)
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI		1
+#endif
+
+#define CONFIG_MPC83XX_TSEC1		1
+#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC83XX_TSEC2		1
+#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR			0
+#define TSEC2_PHY_ADDR			1
+#define TSEC1_PHYIDX			0
+#define TSEC2_PHYIDX			0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME			"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+/* FIXME: Real PCI support will come in a follow-up update. */
+#undef CONFIG_PCI
+
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+#define CFG_PCI2_MEM_BASE	0xA0000000
+#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI2_IO_BASE	0x00000000
+#define CFG_PCI2_IO_PHYS	0xe3000000
+#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+#if defined(CONFIG_PCI)
+
+#define PCI_ALL_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	0xFIXME
+	#define PCI_ENET0_MEMADDR	0xFIXME
+	#define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW			/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID		0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#ifndef CFG_RAMBOOT
+	#define CFG_ENV_IS_IN_FLASH	1
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CFG_ENV_SECT_SIZE	0x20000	/* 256K(one sector) for env */
+	#define CFG_ENV_SIZE		0x2000
+#else
+	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE		1	/* allow baudrate change */
+
+/* Common commands */
+#define CFG_CMD_TQM8349_COMMON	CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\
+				| CFG_CMD_PING | CFG_CMD_EEPROM		\
+				| CFG_CMD_MII | CFG_CMD_JFFS2
+
+#if defined(CFG_RAMBOOT)
+
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PCI	\
+				| CFG_CMD_TQM8349_COMMON)	\
+				&				\
+				~(CFG_CMD_ENV | CFG_CMD_LOADS))
+#else
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL		\
+				| CFG_CMD_TQM8349_COMMON)	\
+				&				\
+				~(CFG_CMD_ENV | CFG_CMD_LOADS))
+#endif
+
+#else /* CFG_RAMBOOT */
+
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI	\
+				| CFG_CMD_TQM8349_COMMON)
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL			\
+				| CFG_CMD_TQM8349_COMMON)
+#endif
+
+#endif /* CFG_RAMBOOT */
+
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory	*/
+#define CFG_LOAD_ADDR		0x2000000	/* default load address */
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ			1000		/* decrementer freq: 1ms ticks */
+
+#undef CONFIG_WATCHDOG				/* watchdog disabled */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/*
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#if defined(PCI_64BIT)
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_64_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII )
+#else
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_32_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII )
+#endif
+
+/* i-cache and d-cache disabled */
+#define CFG_HID0_INIT		0x000000000
+#define CFG_HID0_FINAL		CFG_HID0_INIT
+#define CFG_HID2		0x000000000
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR		D2:DA:5E:44:BC:29
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		1E:F3:40:21:92:53
+#endif
+
+#define CONFIG_IPADDR		192.168.205.1
+
+#define CONFIG_HOSTNAME		tqm8349
+#define CONFIG_ROOTPATH		/opt/eldk/ppc_6xx
+#define CONFIG_BOOTFILE		/tftpboot/tqm83xx/uImage
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+#define CONFIG_LOADADDR		200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=tqm83xx\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;"     \
+		"bootm\0"						\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=/tftpboot/tqm83xx/uImage\0"				\
+	"kernel_addr=80060000\0"					\
+	"ramdisk_addr=80160000\0"					\
+	"load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0"		\
+	"update=protect off 80000000 8003ffff; "			\
+		"era 80000000 8003ffff; cp.b 100000 80000000 40000\0"	\
+	"upd=run load;run update\0"					\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * JFFS2 partitions
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=TQM834x-0"
+
+/* default mtd partition table */
+#define MTDPARTS_DEFAULT	"mtdparts=TQM834x-0:256k(u-boot),128k(env),"\
+						"1m(kernel),2m(initrd),"\
+						"-(user);"\
+
+#endif	/* __CONFIG_H */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 38f7115b189..ea40bad395d 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -98,19 +98,27 @@
 #define BR6 0x5030
 #define BR7 0x5038
 
-#define BR_BA   0xFFFF8000
-#define BR_BA_SHIFT     15
-#define BR_PS   0x00001800
-#define BR_PS_SHIFT     11
-#define BR_DECC 0x00000600
-#define BR_DECC_SHIFT    9
-#define BR_WP   0x00000100
-#define BR_WP_SHIFT      8
-#define BR_MSEL 0x000000E0
-#define BR_MSEL_SHIFT    5
-#define BR_V    0x00000001
-#define BR_V_SHIFT       0
-#define BR_RES  ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
+#define BR_BA		0xFFFF8000
+#define BR_BA_SHIFT		15
+#define BR_PS		0x00001800
+#define BR_PS_SHIFT		11
+#define BR_PS_8		0x00000800  /* Port Size 8 bit */
+#define BR_PS_16	0x00001000  /* Port Size 16 bit */
+#define BR_PS_32	0x00001800  /* Port Size 32 bit */
+#define BR_DECC		0x00000600
+#define BR_DECC_SHIFT		 9
+#define BR_WP		0x00000100
+#define BR_WP_SHIFT		 8
+#define BR_MSEL		0x000000E0
+#define BR_MSEL_SHIFT		 5
+#define BR_MS_GPCM	0x00000000  /* GPCM */
+#define BR_MS_SDRAM	0x00000060  /* SDRAM */
+#define BR_MS_UPMA	0x00000080  /* UPMA */
+#define BR_MS_UPMB	0x000000A0  /* UPMB */
+#define BR_MS_UPMC	0x000000C0  /* UPMC */
+#define BR_V		0x00000001
+#define BR_V_SHIFT		 0
+#define BR_RES		~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
 
 #define OR0 0x5004
 #define OR1 0x500C
@@ -121,26 +129,43 @@
 #define OR6 0x5034
 #define OR7 0x503C
 
-#define OR_GPCM_AM    0xFFFF8000
-#define OR_GPCM_AM_SHIFT      15
-#define OR_GPCM_BCTLD 0x00001000
-#define OR_GPCM_BCTLD_SHIFT   12
-#define OR_GPCM_CSNT  0x00000800
-#define OR_GPCM_CSNT_SHIFT    11
-#define OR_GPCM_ACS   0x00000600
-#define OR_GPCM_ACS_SHIFT      9
-#define OR_GPCM_XACS  0x00000100
-#define OR_GPCM_XACS_SHIFT     8
-#define OR_GPCM_SCY   0x000000F0
-#define OR_GPCM_SCY_SHIFT      4
-#define OR_GPCM_SETA  0x00000008
-#define OR_GPCM_SETA_SHIFT     3
-#define OR_GPCM_TRLX  0x00000004
-#define OR_GPCM_TRLX_SHIFT     2
-#define OR_GPCM_EHTR  0x00000002
-#define OR_GPCM_EHTR_SHIFT     1
-#define OR_GPCM_EAD   0x00000001
-#define OR_GPCM_EAD_SHIFT      0
+#define OR_GPCM_AM		0xFFFF8000
+#define OR_GPCM_AM_SHIFT		15
+#define OR_GPCM_BCTLD		0x00001000
+#define OR_GPCM_BCTLD_SHIFT		12
+#define OR_GPCM_CSNT		0x00000800
+#define OR_GPCM_CSNT_SHIFT		11
+#define OR_GPCM_ACS		0x00000600
+#define OR_GPCM_ACS_SHIFT		 9
+#define OR_GPCM_ACS_0b10	0x00000400
+#define OR_GPCM_ACS_0b11	0x00000600
+#define OR_GPCM_XACS		0x00000100
+#define OR_GPCM_XACS_SHIFT		 8
+#define OR_GPCM_SCY		0x000000F0
+#define OR_GPCM_SCY_SHIFT		 4
+#define OR_GPCM_SCY_1		0x00000010
+#define OR_GPCM_SCY_2		0x00000020
+#define OR_GPCM_SCY_3		0x00000030
+#define OR_GPCM_SCY_4		0x00000040
+#define OR_GPCM_SCY_5		0x00000050
+#define OR_GPCM_SCY_6		0x00000060
+#define OR_GPCM_SCY_7		0x00000070
+#define OR_GPCM_SCY_8		0x00000080
+#define OR_GPCM_SCY_9		0x00000090
+#define OR_GPCM_SCY_10		0x000000a0
+#define OR_GPCM_SCY_11		0x000000b0
+#define OR_GPCM_SCY_12		0x000000c0
+#define OR_GPCM_SCY_13		0x000000d0
+#define OR_GPCM_SCY_14		0x000000e0
+#define OR_GPCM_SCY_15		0x000000f0
+#define OR_GPCM_SETA		0x00000008
+#define OR_GPCM_SETA_SHIFT		 3
+#define OR_GPCM_TRLX		0x00000004
+#define OR_GPCM_TRLX_SHIFT		 2
+#define OR_GPCM_EHTR		0x00000002
+#define OR_GPCM_EHTR_SHIFT		 1
+#define OR_GPCM_EAD		0x00000001
+#define OR_GPCM_EAD_SHIFT		 0
 
 #define OR_UPM_AM    0xFFFF8000
 #define OR_UPM_AM_SHIFT      15