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| author | Haibo Chen <haibo.chen@nxp.com> | 2018-03-14 17:15:23 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2018-04-27 02:30:57 -0700 |
| commit | 1c30a73542990afbe48bf7a398baba9c5efaf4fe (patch) | |
| tree | c51fc611e44de0901aff952d0ba2ce19e4353424 /include | |
| parent | 4ba6e5aa05ec8872426aa68da3879e8fcd835710 (diff) | |
MLK-17586-3 i.MX7ULP: change USDHC clock rate
Change USDHC0 and USDHC1 per clock source from APLL_PFD1,
and set the APll_PFD1 clock rate to 352.8MHz.
Also gate off APll_PFD1/2/3 before boot OS, otherwise set
the clock rate of APll_PFD1/2/3 during OS boot up will triger
some warning message.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 07ef0fab23204684d82f27baf721a72b247f30c5)
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions