diff options
author | Ye Li <ye.li@nxp.com> | 2018-05-30 03:48:45 -0700 |
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committer | Ye Li <ye.li@nxp.com> | 2018-05-31 06:17:30 -0700 |
commit | 0e4da3033f6c2a1b5f4711430723fcc41d482c93 (patch) | |
tree | 6fbd49a94142d55b76a3bdd556bf0d61f03cf2db /include | |
parent | b283cf33edaee442209179927249cdc8e39cb5e2 (diff) |
MLK-18461-2 mx7ulp_arm2: Add 10x10 and 14x14 ARM2 support
Porting the iMX7ULP 10x10 ARM2 and 14x14 ARM2 board codes from v2017.03.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/configs/mx7ulp_arm2.h | 214 |
1 files changed, 214 insertions, 0 deletions
diff --git a/include/configs/mx7ulp_arm2.h b/include/configs/mx7ulp_arm2.h new file mode 100644 index 00000000000..ad3a0d20e84 --- /dev/null +++ b/include/configs/mx7ulp_arm2.h @@ -0,0 +1,214 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7ULP ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7ULP_ARM2_CONFIG_H +#define __MX7ULP_ARM2_CONFIG_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#ifdef CONFIG_SECURE_BOOT +#ifndef CONFIG_CSF_SIZE +#define CONFIG_CSF_SIZE 0x4000 +#endif +#endif + +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + +#define SRC_BASE_ADDR CMC1_RBASE +#define IRAM_BASE_ADDR OCRAM_0_BASE +#define IOMUXC_BASE_ADDR IOMUXC1_RBASE + +/* Fuses */ +#define CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP + +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#ifndef CONFIG_DM_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#else +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */ +#endif +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_ENV_OFFSET (14 * SZ_64K) +#define CONFIG_ENV_SIZE SZ_8K + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG1_RBASE + + +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ + +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +/*#define CONFIG_REVISION_TAG*/ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) + +/* UART */ +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 +#define LPUART_BASE LPUART6_RBASE +#else +#define LPUART_BASE LPUART4_RBASE +#endif + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 256 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_TEXT_BASE 0x67800000 +#define PHYS_SDRAM 0x60000000 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 +#define PHYS_SDRAM_SIZE SZ_1G /*LPDDR2 1G*/ +#define CONFIG_SYS_MEMTEST_END 0x9E000000 +#else +#define PHYS_SDRAM_SIZE SZ_512M +#define CONFIG_SYS_MEMTEST_END 0x7E000000 +#endif +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + +#define CONFIG_LOADADDR 0x60800000 + +#define CONFIG_CMD_MEMTEST + +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 +#define CONFIG_DEFAULT_FDT_FILE "imx7ulp-10x10-arm2.dtb" +#else +#define CONFIG_DEFAULT_FDT_FILE "imx7ulp-14x14-arm2.dtb" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "\0" \ + "initrd_addr=0x63800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttyLP0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x63000000\0" \ + "boot_fdt=try\0" \ + "earlycon=lpuart32,0x402D0010\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi" + + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +/* USB Configs */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +/* QSPI configs */ +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_FSL_QSPI_AHB +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 +#define FSL_QSPI_FLASH_NUM 2 +#define FSL_QSPI_FLASH_SIZE SZ_32M +#else +#define FSL_QSPI_FLASH_NUM 1 +#define FSL_QSPI_FLASH_SIZE SZ_64M +#endif +#define QSPI0_BASE_ADDR 0x410A5000 +#define QSPI0_AMBA_BASE 0xC0000000 +#endif + +#endif /* __CONFIG_H */ |