diff options
| author | Tom Rini <trini@konsulko.com> | 2017-03-14 11:08:10 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-04-05 13:52:01 -0400 |
| commit | ea3310e8aafad1da72d9a5e60568d725cbdefdbd (patch) | |
| tree | 869faa824f09ce4d40f2ce503a607ceb28b5ce91 /include | |
| parent | c3b7cfe15ec1db047182d4ec55a3ce05f19bdf38 (diff) | |
Blackfin: Remove
The architecture is currently unmaintained, remove.
Cc: Benjamin Matthews <mben12@gmail.com>
Cc: Chong Huang <chuang@ucrobotics.com>
Cc: Dimitar Penev <dpn@switchfin.org>
Cc: Haitao Zhang <hzhang@ucrobotics.com>
Cc: I-SYST Micromodule <support@i-syst.com>
Cc: M.Hasewinkel (MHA) <info@ssv-embedded.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Martin Strubel <strubel@section5.ch>
Cc: Peter Meerwald <devel@bct-electronic.com>
Cc: Sonic Zhang <sonic.adi@gmail.com>
Cc: Valentin Yakovenkov <yakovenkov@niistt.ru>
Cc: Wojtek Skulski <info@skutek.com>
Cc: Wojtek Skulski <skulski@pas.rochester.edu>
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include')
37 files changed, 0 insertions, 5137 deletions
diff --git a/include/common.h b/include/common.h index 2cbbd5a60c..8bd4087bab 100644 --- a/include/common.h +++ b/include/common.h @@ -76,9 +76,6 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_4xx #include <asm/ppc4xx.h> #endif -#ifdef CONFIG_BLACKFIN -#include <asm/blackfin.h> -#endif #ifdef CONFIG_SOC_DA8XX #include <asm/arch/hardware.h> #endif diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h deleted file mode 100644 index b96580370d..0000000000 --- a/include/configs/bct-brettl2.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * U-Boot - Configuration file for BF536 brettl2 board - */ - -#ifndef __CONFIG_BCT_BRETTL2_H__ -#define __CONFIG_BCT_BRETTL2_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf536-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 16384000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 24 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 3 -#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000) - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -/* - * SDRAM Settings - */ -#define CONFIG_EBIU_SDRRC_VAL 0x07f6 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC 1 -#define CONFIG_NETCONSOLE 1 -#define CONFIG_HOSTNAME brettl2 -#define CONFIG_IPADDR 192.168.233.224 -#define CONFIG_GATEWAYIP 192.168.233.1 -#define CONFIG_SERVERIP 192.168.233.53 -#define CONFIG_ROOTPATH "/romfs/brettl2" -#endif - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x12000 - -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -#define ENV_IS_EMBEDDED -#else -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif - -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * Misc Settings - */ -#define CONFIG_LOADADDR 0x800000 -#define CONFIG_MISC_INIT_R -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -/* disable unnecessary features */ -#undef CONFIG_BOOTM_RTEMS -#undef CONFIG_BZIP2 -#undef CONFIG_KALLSYMS - -#endif diff --git a/include/configs/bf506f-ezkit.h b/include/configs/bf506f-ezkit.h deleted file mode 100644 index b517af392c..0000000000 --- a/include/configs/bf506f-ezkit.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * U-Boot - Configuration file for BF506F EZ-Kit board - */ - -#ifndef __CONFIG_BF506F_EZKIT_H__ -#define __CONFIG_BF506F_EZKIT_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf506-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 16 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_SIZE 0 - -#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 -#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2 - -#define CONFIG_SYS_MONITOR_BASE (L1_DATA_A_SRAM_END) -#define CONFIG_SYS_MONITOR_LEN (4 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024) - -/* - * Flash Settings - */ -/* -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 71 -#define CONFIG_MONITOR_IS_IN_RAM -*/ - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x400 - -/* - * Misc Settings - */ -#define CONFIG_ICACHE_OFF -#define CONFIG_DCACHE_OFF -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BFIN_SERIAL - -#undef CONFIG_GZIP -#undef CONFIG_ZLIB -#undef CONFIG_BOOTM_RTEMS -#undef CONFIG_BOOTM_LINUX - -#endif diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h deleted file mode 100644 index e3c22869bc..0000000000 --- a/include/configs/bf518f-ezbrd.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * U-Boot - Configuration file for BF518F EZBrd board - */ - -#ifndef __CONFIG_BF518F_EZBRD_H__ -#define __CONFIG_BF518F_EZBRD_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf518-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 16 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -/* This board has a 64meg MT48H32M16 */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x0096 -#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS) - -#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (384 * 1024) - -/* - * Network Settings - */ -#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__) -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_BFIN_MAC_PINS \ - { \ - P_MII0_ETxD0, \ - P_MII0_ETxD1, \ - P_MII0_ETxD2, \ - P_MII0_ETxD3, \ - P_MII0_ETxEN, \ - P_MII0_TxCLK, \ - P_MII0_PHYINT, \ - P_MII0_COL, \ - P_MII0_ERxD0, \ - P_MII0_ERxD1, \ - P_MII0_ERxD2, \ - P_MII0_ERxD3, \ - P_MII0_ERxDV, \ - P_MII0_ERxCLK, \ - P_MII0_CRS, \ - P_MII0_MDC, \ - P_MII0_MDIO, \ - 0 } -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME bf518f-ezbrd -#define CONFIG_PHY_ADDR 3 - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 71 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#endif -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * SDH Settings - */ -#if !defined(__ADSPBF512__) -#define CONFIG_BFIN_SDH -#endif - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf525-ucr2.h b/include/configs/bf525-ucr2.h deleted file mode 100644 index 1c1a08f6fc..0000000000 --- a/include/configs/bf525-ucr2.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * U-Boot - Configuration file for bf525-ucr2 board - * The board includes ADSP-BF525 rev. 0.2, - * 32-bit SDRAM (SAMSUNG K4S561632H-UC75), - * USB 2.0 High Speed OTG USB WIFI, - * SPI flash (cFeon EN25Q128 16 MB), - * Support PPI and ITU-R656, - * See http://www.ucrobotics.com/?q=cn/ucr2 - */ - -#ifndef __CONFIG_BF525_UCR2_H__ -#define __CONFIG_BF525_UCR2_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf525-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 24000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 20 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -/* - * SDRAM reference page - * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram - */ -#define CONFIG_EBIU_SDRRC_VAL 0x3f8 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (320 * 1024) -#define CONFIG_SYS_MALLOC_LEN (320 * 1024) - -/* support for serial flash */ -#define CONFIG_BFIN_SPI -#define CONFIG_SF_DEFAULT_HZ 30000000 - -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Misc Settings - */ -#define CONFIG_UART_CONSOLE 0 - -#define CONFIG_BFIN_SERIAL -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" -#define CONFIG_BOOTCOMMAND "run sfboot" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "sfboot=sf probe 1;" \ - "sf read 0x1000000 0x20000 0x300000;" \ - "bootm 0x1000000\0" - -#endif diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h deleted file mode 100644 index 7d75e73f72..0000000000 --- a/include/configs/bf526-ezbrd.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * U-Boot - Configuration file for BF526 EZBrd board - */ - -#ifndef __CONFIG_BF526_EZBRD_H__ -#define __CONFIG_BF526_EZBRD_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf526-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 16 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -/* This board has a 64meg MT48H32M16 */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x0267 -#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_2 | PASR_ALL | TRAS_6 | TRP_4 | TRCD_2 | TWR_2 | PSS) - -#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) - -/* - * NAND Settings - * (can't be used same time as ethernet) - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -# define CONFIG_BFIN_NFC -# define CONFIG_BFIN_NFC_BOOTROM_ECC -#endif -#ifdef CONFIG_BFIN_NFC -#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 -#define CONFIG_DRIVER_NAND_BFIN -#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_CMD_NAND -#endif - -/* - * Network Settings - */ -#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \ - !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC) -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_RMII -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME bf526-ezbrd - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 71 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#endif -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * USB Settings - */ -#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) -#define CONFIG_USB_MUSB_HCD -#define CONFIG_USB_BLACKFIN -#define CONFIG_USB_MUSB_TIMEOUT 100000 -#endif - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 1 - -/* define to enable run status via led */ - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h deleted file mode 100644 index e433aaa91d..0000000000 --- a/include/configs/bf527-ad7160-eval.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * U-Boot - Configuration file for BF527 AD7160-EVAL board - */ - -#ifndef __CONFIG_BF527_AD7160_EVAL_H__ -#define __CONFIG_BF527_AD7160_EVAL_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf527-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 24000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 25 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x03F6 -#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS) - -#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (640 * 1024) - -/* - * NAND Settings - * (can't be used same time as ethernet) - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -# define CONFIG_BFIN_NFC -# define CONFIG_BFIN_NFC_BOOTROM_ECC -#endif -#ifdef CONFIG_BFIN_NFC -#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 -#define CONFIG_DRIVER_NAND_BFIN -#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 259 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SIZE 0x20000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * SPI_MMC Settings - */ -#define CONFIG_MMC_SPI - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_UART_CONSOLE 0 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h deleted file mode 100644 index d945b8d7bf..0000000000 --- a/include/configs/bf527-ezkit.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * U-Boot - Configuration file for BF537 STAMP board - */ - -#ifndef __CONFIG_BF527_EZKIT_H__ -#define __CONFIG_BF527_EZKIT_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf527-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 21 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x03F6 -#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS) - -#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (640 * 1024) - -/* - * NAND Settings - * (can't be used same time as ethernet) - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -# define CONFIG_BFIN_NFC -# define CONFIG_BFIN_NFC_BOOTROM_ECC -#endif -#ifdef CONFIG_BFIN_NFC -#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 -#define CONFIG_DRIVER_NAND_BFIN -#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif - -/* - * Network Settings - */ -#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \ - !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC) -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_RMII -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME bf527-ezkit - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 259 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SIZE 0x20000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * USB Settings - */ -#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) -#define CONFIG_USB_MUSB_HCD -#define CONFIG_USB_BLACKFIN -#define CONFIG_USB_MUSB_TIMEOUT 100000 -#endif - -/* Don't waste time transferring a logo over the UART */ - -/* - * Video Settings - */ -#ifdef CONFIG_VIDEO -#ifdef CONFIG_BF527_EZKIT_REV_2_1 -# define CONFIG_LQ035Q1_SPI_BUS 0 -# define CONFIG_LQ035Q1_SPI_CS 7 -# define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI -#else -# define CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI -#endif - -#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI -# define EASYLOGO_HEADER <asm/bfin_logo_rgb565_230x230_lzma.h> -#else -# define EASYLOGO_HEADER <asm/bfin_logo_230x230_lzma.h> -#endif -#endif /* CONFIG_VIDEO */ - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 1 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h deleted file mode 100644 index 6b7d19e639..0000000000 --- a/include/configs/bf527-sdp.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * U-Boot - Configuration file for BF527 SDP board - */ - -#ifndef __CONFIG_BF527_SDP_H__ -#define __CONFIG_BF527_SDP_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf527-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 24000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 25 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -#define CONFIG_PLL_LOCKCNT_VAL 0x0200 -#define CONFIG_PLL_CTL_VAL 0x2a00 -#define CONFIG_VR_CTL_VAL 0x7090 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -#define CONFIG_EBIU_SDRRC_VAL 0x00FE -#define CONFIG_EBIU_SDGCTL_VAL 0x8011998d - -#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (640 * 1024) - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 259 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_ALL - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_UART_CONSOLE 0 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h deleted file mode 100644 index e154812abd..0000000000 --- a/include/configs/bf533-ezkit.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * U-Boot - Configuration file for BF533 EZKIT board - */ - -#ifndef __CONFIG_BF533_EZKIT_H__ -#define __CONFIG_BF533_EZKIT_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf533-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 27000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 22 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_SIZE 32 -/* Early EZKITs had 32megs, but later have 64megs */ -#if (CONFIG_MEM_SIZE == 64) -# define CONFIG_MEM_ADD_WDTH 10 -#else -# define CONFIG_MEM_ADD_WDTH 9 -#endif - -#define CONFIG_EBIU_SDRRC_VAL 0x398 -#define CONFIG_EBIU_SDGCTL_VAL 0x91118d - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20310300 -#define SMC91111_EEPROM_INIT() \ - do { \ - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \ - bfin_write_FIO_FLAG_C(PF1); \ - bfin_write_FIO_FLAG_S(PF0); \ - SSYNC(); \ - } while (0) -#define CONFIG_HOSTNAME bf533-ezkit - -/* - * Flash Settings - */ -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 3 -#define CONFIG_SYS_MAX_FLASH_SECT 40 -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR 0x20030000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define FLASH_TOT_SECT 40 - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C_SOFT -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C -#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0 -#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1 -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h deleted file mode 100644 index 516fe2d021..0000000000 --- a/include/configs/bf533-stamp.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * U-Boot - Configuration file for BF533 STAMP board - */ - -#ifndef __CONFIG_BF533_STAMP_H__ -#define __CONFIG_BF533_STAMP_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf533-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 11059200 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 45 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */ - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 11 -#define CONFIG_MEM_SIZE 128 - -#define CONFIG_EBIU_SDRRC_VAL 0x268 -#define CONFIG_EBIU_SDGCTL_VAL 0x911109 - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3 -#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983 - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (384 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20300300 -#define SMC91111_EEPROM_INIT() \ - do { \ - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \ - bfin_write_FIO_FLAG_C(PF1); \ - bfin_write_FIO_FLAG_S(PF0); \ - SSYNC(); \ - } while (0) -#define CONFIG_HOSTNAME bf533-stamp - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0 -/* - * Software (bit-bang) I2C driver configuration - */ -#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3 -#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2 - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_CFI_AMD_RESET -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 67 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -/* -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_ALL -*/ - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#endif -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -#define ENV_IS_EMBEDDED -#else -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C_SOFT -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C -#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3 -#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0 -#endif - -/* - * Compact Flash / IDE / ATA Settings - */ - -/* Enabled below option for CF support */ -/* #define CONFIG_STAMP_CF */ -#if defined(CONFIG_STAMP_CF) -#define CONFIG_MISC_INIT_R -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1) - -#define CONFIG_SYS_ATA_BASE_ADDR 0x20200000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */ - -#define CONFIG_SYS_ATA_STRIDE 2 - -#undef CONFIG_EBIU_AMBCTL1_VAL -#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2 -#endif - -/* - * Misc Settings - */ -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 - -/* FLASH/ETHERNET uses the same async bank */ -#define SHARED_RESOURCES 1 - -/* define to enable boot progress via leds */ -/* #define CONFIG_SHOW_BOOT_PROGRESS */ - -/* define to enable run status via led */ - -/* define to enable splash screen support */ - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h deleted file mode 100644 index 5d57b80c7b..0000000000 --- a/include/configs/bf537-minotaur.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * U-Boot - Configuration file for CSP Minotaur board - * - * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch> - * Minotaur config, brushed up for official uClinux dist. - * Parallel flash support disabled, SPI flash boot command - * added ('run flashboot'). - * - * Flash image map: - * - * 0x00000000 u-boot bootstrap - * 0x00010000 environment - * 0x00020000 u-boot code - * 0x00030000 uImage.initramfs - * - */ - -#ifndef __CONFIG_BF537_MINOTAUR_H__ -#define __CONFIG_BF537_MINOTAUR_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 20 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_SIZE 32 -#define CONFIG_MEM_ADD_WDTH 9 - -#define CONFIG_EBIU_SDRRC_VAL 0x306 -#define CONFIG_EBIU_SDGCTL_VAL 0x91114d - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_SYS_MALLOC_LEN (128 << 10) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define CONFIG_BFIN_MAC -#define CONFIG_NETCONSOLE 1 -#endif -#ifdef CONFIG_BFIN_MAC -#define CONFIG_IPADDR 192.168.0.15 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_HOSTNAME bf537-minotaur -#endif - -#define CONFIG_SYS_AUTOLOAD "no" -#define CONFIG_ROOTPATH "/romfs" - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 - -/* - * Misc Settings - */ -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_ENV_OVERWRITE 1 - -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BFIN_SERIAL - -#define CONFIG_PANIC_HANG 1 -#define CONFIG_RTC_BFIN 1 -#define CONFIG_BOOT_RETRY_TIME -1 -#define CONFIG_LOADS_ECHO 1 - -#define CONFIG_CMD_BOOTLDR -#define CONFIG_CMD_DATE - -#define CONFIG_BOOTCOMMAND "run ramboot" -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" - -#define BOOT_ENV_SETTINGS \ - "update=tftpboot $(loadaddr) u-boot.ldr;" \ - "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \ - "sf erase 0 0x30000;" \ - "sf write $(loadaddr) 0 $(filesize)" \ - "flashboot=sf read 0x1000000 0x30000 0x320000;" \ - "bootm 0x1000000\0" -#ifdef CONFIG_BFIN_MAC -# define NETWORK_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):eth0:off\0" \ - "ramboot=tftpboot $(loadaddr) linux;" \ - "run ramargs;run addip;bootelf\0" \ - "nfsboot=tftpboot $(loadaddr) linux;" \ - "run nfsargs;run addip;bootelf\0" -#else -# define NETWORK_ENV_SETTINGS -#endif -#define CONFIG_EXTRA_ENV_SETTINGS \ - NETWORK_ENV_SETTINGS \ - "ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \ - BOOT_ENV_SETTINGS - -#endif diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h deleted file mode 100644 index 6d80592dc2..0000000000 --- a/include/configs/bf537-pnav.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * U-Boot - Configuration file for BF537 PNAV board - */ - -#ifndef __CONFIG_BF537_PNAV_H__ -#define __CONFIG_BF537_PNAV_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 24576000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 20 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x3b7 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_RMII -#endif -#define CONFIG_HOSTNAME bf537-pnav - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 71 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#else -#define ENV_IS_EMBEDDED -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x20004000 -#define CONFIG_ENV_OFFSET 0x4000 -#endif -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * NAND Settings - */ -#define CONFIG_NAND_PLAT - -#define CONFIG_SYS_NAND_BASE 0x20100000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_WRITE(addr, cmd) \ - do { \ - bfin_write8(addr, cmd); \ - SSYNC(); \ - } while (0) - -#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) -#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12 - -/* - * I2C settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * Misc Settings - */ -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 - -/* JFFS Partition offset set */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 -/* 512k reserved for u-boot */ -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15 - -#define CONFIG_BOOTCOMMAND "run nandboot" -#define CONFIG_BOOTARGS_ROOT "/dev/mtdblock1 rw rootfstype=yaffs" - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h deleted file mode 100644 index 3b69e58dc6..0000000000 --- a/include/configs/bf537-srv1.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * U-Boot - Configuration file for CSP Minotaur board - * - * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch> - * Minotaur config, brushed up for official uClinux dist. - * Parallel flash support disabled, SPI flash boot command - * added ('run flashboot'). - * - * Flash image map: - * - * 0x00000000 u-boot bootstrap - * 0x00010000 environment - * 0x00020000 u-boot code - * 0x00030000 uImage.initramfs - * - */ - -#ifndef __CONFIG_BF537_SRV1_H__ -#define __CONFIG_BF537_SRV1_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 22118400 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 20 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_SIZE 32 -#define CONFIG_MEM_ADD_WDTH 9 - -#define CONFIG_EBIU_SDRRC_VAL 0x2ac -#define CONFIG_EBIU_SDGCTL_VAL 0x91110d - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_SYS_MALLOC_LEN (384 << 10) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define CONFIG_BFIN_MAC -#define CONFIG_NETCONSOLE 1 -#endif -#ifdef CONFIG_BFIN_MAC -#define CONFIG_IPADDR 192.168.0.15 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_HOSTNAME bf537-srv1 -#endif - -#define CONFIG_SYS_AUTOLOAD "no" -#define CONFIG_ROOTPATH "/romfs" - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 - -/* - * Misc Settings - */ -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_ENV_OVERWRITE 1 - -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BFIN_SERIAL - -#define CONFIG_PANIC_HANG 1 -#define CONFIG_RTC_BFIN 1 -#define CONFIG_BOOT_RETRY_TIME -1 -#define CONFIG_LOADS_ECHO 1 - -#define CONFIG_CMD_BOOTLDR -#define CONFIG_CMD_DATE - -#define CONFIG_BOOTCOMMAND "run flashboot" -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" - -#define BOOT_ENV_SETTINGS \ - "update=tftpboot $(loadaddr) u-boot.ldr;" \ - "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \ - "sf erase 0 0x30000;" \ - "sf write $(loadaddr) 0 $(filesize)" \ - "flashboot=sf read 0x1000000 0x30000 0x320000;" \ - "bootm 0x1000000\0" -#ifdef CONFIG_BFIN_MAC -# define NETWORK_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):eth0:off\0" \ - "ramboot=tftpboot $(loadaddr) linux;" \ - "run ramargs;run addip;bootelf\0" \ - "nfsboot=tftpboot $(loadaddr) linux;" \ - "run nfsargs;run addip;bootelf\0" -#else -# define NETWORK_ENV_SETTINGS -#endif -#define CONFIG_EXTRA_ENV_SETTINGS \ - NETWORK_ENV_SETTINGS \ - "ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \ - BOOT_ENV_SETTINGS - -#endif diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h deleted file mode 100644 index 6858153720..0000000000 --- a/include/configs/bf537-stamp.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * U-Boot - Configuration file for BF537 STAMP board - */ - -#ifndef __CONFIG_BF537_STAMP_H__ -#define __CONFIG_BF537_STAMP_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 20 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x306 -#define CONFIG_EBIU_SDGCTL_VAL 0x91114d - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (384 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME bf537-stamp - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_ALL - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#endif -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -#define ENV_IS_EMBEDDED -#else -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * SPI_MMC Settings - */ -#define CONFIG_MMC_SPI - -/* - * NAND Settings - */ -/* #define CONFIG_NAND_PLAT */ -#ifdef CONFIG_NAND_PLAT -#define CONFIG_SYS_NAND_BASE 0x20212000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_WRITE(addr, cmd) \ - do { \ - bfin_write8(addr, cmd); \ - SSYNC(); \ - } while (0) - -#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) -#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3 -#endif /* CONFIG_NAND_PLAT */ - -/* - * CF-CARD IDE-HDD Support - */ - -/* - * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card) - * Strange address mapping Blackfin A13 connects to CF_A0 - */ - -/* #define CONFIG_BFIN_TRUE_IDE */ - -/* - * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card) - * This should be the preferred mode - */ - -/* #define CONFIG_BFIN_CF_IDE */ - -/* - * Add IDE Disk Drive (HDD) support - * See example interface here: - * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin - */ - -/* #define CONFIG_BFIN_HDD_IDE */ - -#if defined(CONFIG_BFIN_CF_IDE) || \ - defined(CONFIG_BFIN_HDD_IDE) || \ - defined(CONFIG_BFIN_TRUE_IDE) -# define CONFIG_BFIN_IDE 1 -# define CONFIG_CMD_IDE -#endif - -#if defined(CONFIG_BFIN_IDE) - -/* - * IDE/ATA stuff - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1) - -#undef CONFIG_EBIU_AMBCTL1_VAL -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3 - -#define CONFIG_CF_ATASEL_DIS 0x20311800 -#define CONFIG_CF_ATASEL_ENA 0x20311802 - -#if defined(CONFIG_BFIN_TRUE_IDE) -/* - * Note that these settings aren't for the most part used in include/ata.h - * when all of the ATA registers are setup - */ -#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */ -#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A13 */ - -#elif defined(CONFIG_BFIN_CF_IDE) -#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */ -#define CONFIG_SYS_ATA_STRIDE 1 /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */ - -#elif defined(CONFIG_BFIN_HDD_IDE) -#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */ -#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */ -#undef CONFIG_SCLK_DIV -#define CONFIG_SCLK_DIV 8 -#endif - -#endif - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 - -/* Define if want to do post memory test */ -#undef CONFIG_POST -#ifdef CONFIG_POST -#define CONFIG_SYS_POST_HOTKEYS_GPIO GPIO_PF5 -#define CONFIG_POST_BSPEC1_GPIO_LEDS \ - GPIO_PF6, GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, -#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \ - GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2, -#define CONFIG_POST_BSPEC2_GPIO_NAMES \ - 10, 11, 12, 13, -#define CONFIG_SYS_POST_FLASH_START 11 -#define CONFIG_SYS_POST_FLASH_END 71 -#endif - -/* These are for board tests */ -#if 0 -#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100" -#endif - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h deleted file mode 100644 index a6d039c96d..0000000000 --- a/include/configs/bf538f-ezkit.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * U-Boot - Configuration file for BF538F EZ-Kit Lite board - */ - -#ifndef __CONFIG_BF538F_EZKIT_H__ -#define __CONFIG_BF538F_EZKIT_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf538-0.4 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 21 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL (0x03F6) -#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_3 | TRP_3 | TRAS_6 | PASR_ALL | CL_3) - -#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | AMBEN_ALL | AMCKEN) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (384 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20310300 -#define CONFIG_HOSTNAME bf538f-ezkit - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 71 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -/* -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_ALL -*/ - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#endif -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -#define ENV_IS_EMBEDDED -#else -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * Misc Settings - */ -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h deleted file mode 100644 index 35cbebdfb8..0000000000 --- a/include/configs/bf548-ezkit.h +++ /dev/null @@ -1,190 +0,0 @@ -/* - * U-Boot - Configuration file for BF548 STAMP board - */ - -#ifndef __CONFIG_BF548_EZKIT_H__ -#define __CONFIG_BF548_EZKIT_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf548-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 21 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE -#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222 -#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021 - -/* Default EZ-Kit bank mapping: - * Async Bank 0 - 32MB Burst Flash - * Async Bank 1 - Ethernet - * Async Bank 2 - Nothing - * Async Bank 3 - Nothing - */ -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 -#define CONFIG_EBIU_FCTL_VAL (BCLK_4) -#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH) - -#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) -#define CONFIG_SYS_MALLOC_LEN (768 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_BASE 0x24000000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_HOSTNAME bf548-ezkit - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 259 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_SIZE 0x20000 -#else -/* The BF548-EZKIT uses a top boot flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_OFFSET (0x1000000 - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SECT_SIZE 0x8000 -#endif - -/* - * NAND Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 -#define CONFIG_BFIN_NFC_BOOTROM_ECC -#define CONFIG_DRIVER_NAND_BFIN -#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * SATA - */ -#if !defined(__ADSPBF544__) -#define CONFIG_LIBATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_LBA48 -#define CONFIG_PATA_BFIN -#define CONFIG_BFIN_ATAPI_BASE_ADDR 0xFFC03800 -#define CONFIG_BFIN_ATA_MODE XFER_PIO_4 -#endif - -/* - * SDH Settings - */ -#if !defined(__ADSPBF544__) -#define CONFIG_BFIN_SDH -#endif - -/* - * USB Settings - */ -#if !defined(__ADSPBF544__) -#define CONFIG_USB_MUSB_HCD -#define CONFIG_USB_BLACKFIN -#define CONFIG_USB_MUSB_TIMEOUT 100000 -#endif - -/* - * Misc Settings - */ -#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 )) -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 1 -#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000 - -#define CONFIG_ADI_GPIO2 - -#ifdef CONFIG_VIDEO -#define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h > -#define CONFIG_DEB_DMA_URGENT -#endif - -/* Define if want to do post memory test */ -#undef CONFIG_POST -#ifdef CONFIG_POST -#define CONFIG_POST_BSPEC1_GPIO_LEDS \ - GPIO_PG6, GPIO_PG7, GPIO_PG8, GPIO_PG9, GPIO_PG10, GPIO_PG11, -#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \ - GPIO_PB8, GPIO_PB9, GPIO_PB10, GPIO_PB11 -#define CONFIG_POST_BSPEC2_GPIO_NAMES \ - 13, 12, 11, 10, -#define CONFIG_SYS_POST_FLASH_START 10 -#define CONFIG_SYS_POST_FLASH_END 127 -#endif - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h deleted file mode 100644 index bf2d7b6a8b..0000000000 --- a/include/configs/bf561-acvilon.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * U-Boot - Configuration file for BF561 Acvilon System On Module - * For more information please go to http://www.niistt.ru/ - */ - -#ifndef __CONFIG_BF561_ACVILON_H__ -#define __CONFIG_BF561_ACVILON_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf561-0.5 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 12000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 50 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 128 - -#define CONFIG_EBIU_SDRRC_VAL 0x300 -#define CONFIG_EBIU_SDGCTL_VAL 0x00B11189 - -#define CONFIG_EBIU_AMGCTL_VAL 0x4e -#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 -#define CONFIG_EBIU_AMBCTL1_VAL 0x99b35554 - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * RTC Settings - */ -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_I2C_DTT_ADDR 0x49 -/*#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3*/ - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DTT - -#if defined(CONFIG_CMD_NET) - -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_32_BIT -/* #define CONFIG_SMC911X_16_BIT */ -#define CONFIG_SMC911X_BASE 0x28000000 - -#endif /* (CONFIG_CMD_NET) */ - -#define CONFIG_HOSTNAME bf561-acvilon - -/* - * I2C Settings - */ -#define CONFIG_HARD_I2C -/* Use 300kHz speed by default */ -#define CONFIG_SYS_I2C_SPEED 0x00 -#define CONFIG_PCA9564_I2C -#define CONFIG_PCA9564_BASE 0x2c000000 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_SF_DEFAULT_SPEED 10000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SECT_SIZE (1056 * 8) -#define CONFIG_ENV_OFFSET ((16 + 256) * 1056) -#define CONFIG_ENV_SIZE (8 * 1056) - -/* - * NAND Settings - * We're using NAND_PLAT driver to make things simplier - */ -#define CONFIG_NAND_PLAT -#define CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x24000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3)) -#define BFIN_NAND_WRITE(addr, cmd) \ - do { \ - bfin_write8(addr, cmd); \ - SSYNC(); \ - } while (0) - -#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) -#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10 - -/* - * Misc Settings - */ -#define CONFIG_UART_CONSOLE 0 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif /* __CONFIG_BF561_ACVILON_H__ */ diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h deleted file mode 100644 index 2fefe98f85..0000000000 --- a/include/configs/bf561-ezkit.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * U-Boot - Configuration file for BF561 EZKIT board - */ - -#ifndef __CONFIG_BF561_EZKIT_H__ -#define __CONFIG_BF561_EZKIT_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf561-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 30000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 20 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 6 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x306 -#define CONFIG_EBIU_SDGCTL_VAL 0x91114d - -#define CONFIG_EBIU_AMGCTL_VAL 0x3F -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x2C010300 -#define CONFIG_SMC_USE_32_BIT 1 -#define CONFIG_HOSTNAME bf561-ezkit - -/* - * Flash Settings - */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_AMD_RESET -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 -/* The BF561-EZKIT uses a top boot flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET (0x800000 - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SECT_SIZE 0x2000 - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C_SOFT -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C -#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0 -#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0 -#endif - -/* - * Misc Settings - */ -#define CONFIG_UART_CONSOLE 0 - -/* - * Run core 1 from L1 SRAM start address when init uboot on core 0 - */ -/* #define CONFIG_CORE1_RUN 1 */ - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h deleted file mode 100644 index 5791810b35..0000000000 --- a/include/configs/bf609-ezkit.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * U-Boot - Configuration file for BF609 EZ-Kit board - */ - -#ifndef __CONFIG_BF609_EZKIT_H__ -#define __CONFIG_BF609_EZKIT_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf609-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* For ez-board version 1.0, else undef this */ -#define CONFIG_BFIN_BOARD_VERSION_1_0 - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SYSCLK_DIV - * SCLK0 = SCLK / SCLK0_DIV - * SCLK1 = SCLK / SCLK1_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ (25000000) -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF (0) - -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-127 (where 0 means 128) */ -#define CONFIG_VCO_MULT (20) - -/* CCLK_DIV controls the core clock divider */ -/* Values can range from 0-31 (where 0 means 32) */ -#define CONFIG_CCLK_DIV (1) -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 0-31 (where 0 means 32) */ -#define CONFIG_SCLK_DIV (4) -/* Values can range from 0-7 (where 0 means 8) */ -#define CONFIG_SCLK0_DIV (1) -#define CONFIG_SCLK1_DIV (1) -/* DCLK_DIV controls the DDR clock divider */ -/* Values can range from 0-31 (where 0 means 32) */ -#define CONFIG_DCLK_DIV (2) -/* OCLK_DIV controls the output clock divider */ -/* Values can range from 0-127 (where 0 means 128) */ -#define CONFIG_OCLK_DIV (16) - -/* - * Memory Settings - */ -#define CONFIG_MEM_SIZE 128 - -#define CONFIG_SMC_GCTL_VAL 0x00000010 -#define CONFIG_SMC_B0CTL_VAL 0x01007011 -#define CONFIG_SMC_B0TIM_VAL 0x08170977 -#define CONFIG_SMC_B0ETIM_VAL 0x00092231 - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) - -#define CONFIG_HW_WATCHDOG -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK -#define CONFIG_NETCONSOLE -#define CONFIG_HOSTNAME "bf609-ezkit" -#define CONFIG_PHY_ADDR 1 -#define CONFIG_DW_PORTS 1 -#define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_MII - -/* i2c Settings */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * Flash Settings - */ -#undef CONFIG_CMD_JFFS2 -#define CONFIG_SYS_FLASH_CFI_WIDTH 2 -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0xb0000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 131 -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI6XX -#define CONFIG_ENV_SPI_MAX_HZ 25000000 -#define CONFIG_SF_DEFAULT_SPEED 25000000 -#define CONFIG_SPI_FLASH_ALL - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_SIZE 0x20000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_SECT_SIZE 0x8000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif - -#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0xB0100000\0" - -/* - * SDH Settings - */ -#define CONFIG_BFIN_SDH - -/* - * Misc Settings - */ -#define CONFIG_UART_CONSOLE 0 - -#define CONFIG_CMD_SOFTSWITCH - -#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4) -#define CONFIG_BFIN_SOFT_SWITCH - -#define CONFIG_ADI_GPIO2 - -#if 0 -#define CONFIG_UART_MEM 1024 -#undef CONFIG_UART_CONSOLE -#undef CONFIG_JTAG_CONSOLE -#undef CONFIG_UART_CONSOLE_IS_JTAG -#endif - -#define CONFIG_BOARD_SIZE_LIMIT $$((512 * 1024)) - -/* - * Run core 1 from L1 SRAM start address when init uboot on core 0 - */ -/* #define CONFIG_CORE1_RUN 1 */ - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> -#endif diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h deleted file mode 100644 index a915b1a2ef..0000000000 --- a/include/configs/bfin_adi_common.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * U-Boot - Common settings for Analog Devices boards - */ - -#ifndef __CONFIG_BFIN_ADI_COMMON_H__ -#define __CONFIG_BFIN_ADI_COMMON_H__ - -/* - * Command Settings - */ -#ifndef _CONFIG_CMD_DEFAULT_H -# ifdef ADI_CMDS_NETWORK -# define CONFIG_BOOTP_SUBNETMASK -# define CONFIG_BOOTP_GATEWAY -# define CONFIG_BOOTP_DNS -# define CONFIG_BOOTP_NTPSERVER -# define CONFIG_BOOTP_RANDOM_DELAY -# define CONFIG_KEEP_SERVERADDR -# ifdef CONFIG_BFIN_MAC -# endif -# endif -# ifdef CONFIG_LIBATA -# define CONFIG_CMD_SATA -# endif -# ifdef CONFIG_MMC -# define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 -# endif -# ifdef CONFIG_MMC_SPI -# define CONFIG_CMD_MMC_SPI -# endif -# ifdef CONFIG_USB -# define CONFIG_CMD_USB_STORAGE -# endif -# if defined(CONFIG_NAND_PLAT) || defined(CONFIG_DRIVER_NAND_BFIN) -# define CONFIG_CMD_NAND -# define CONFIG_CMD_NAND_LOCK_UNLOCK -# endif -# ifdef CONFIG_POST -# define CONFIG_CMD_DIAG -# endif -# ifdef CONFIG_RTC_BFIN -# define CONFIG_CMD_DATE -# ifdef ADI_CMDS_NETWORK -# endif -# endif -# ifdef CONFIG_SPI -# define CONFIG_CMD_EEPROM -# endif -# if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT) -# define CONFIG_SOFT_I2C_READ_REPEATED_START -# endif -# ifdef CONFIG_MTD_NOR_FLASH -# define CONFIG_CMD_JFFS2 -# endif -# ifdef CONFIG_CMD_JFFS2 -# define CONFIG_JFFS2_SUMMARY -# endif -# define CONFIG_CMD_BOOTLDR -# define CONFIG_CMD_CPLBINFO -# define CONFIG_CMD_KGDB -# define CONFIG_CMD_LDRINFO -# define CONFIG_CMD_REGINFO -# define CONFIG_CMD_STRINGS -# if defined(__ADSPBF51x__) || defined(__ADSPBF52x__) || defined(__ADSPBF54x__) -# define CONFIG_CMD_OTP -# define CONFIG_CMD_SPIBOOTLDR -# endif -#endif - -/* - * Console Settings - */ -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_LOADS_ECHO 1 -#define CONFIG_JTAG_CONSOLE -#ifdef CONFIG_UART_CONSOLE -# define CONFIG_BFIN_SERIAL -#endif - -/* - * Debug Settings - */ -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_DEBUG_DUMP 1 -#define CONFIG_KALLSYMS 1 -#define CONFIG_PANIC_HANG 1 - -/* - * Env Settings - */ -#ifndef CONFIG_BOOTCOMMAND -# define CONFIG_BOOTCOMMAND "run ramboot" -#endif -#ifdef CONFIG_VIDEO -# define CONFIG_BOOTARGS_VIDEO "console=tty0 " -#else -# define CONFIG_BOOTARGS_VIDEO "" -#endif -#ifndef CONFIG_BOOTARGS_ROOT -# define CONFIG_BOOTARGS_ROOT "/dev/mtdblock0 rw" -#endif -#ifndef FLASHBOOT_ENV_SETTINGS -# define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20100000\0" -#endif -#define CONFIG_BOOTARGS \ - "root=" CONFIG_BOOTARGS_ROOT " " \ - "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \ - "earlyprintk=" \ - "serial," \ - "uart" __stringify(CONFIG_UART_CONSOLE) "," \ - __stringify(CONFIG_BAUDRATE) " " \ - CONFIG_BOOTARGS_VIDEO \ - "console=ttyBF" __stringify(CONFIG_UART_CONSOLE) "," \ - __stringify(CONFIG_BAUDRATE) -#if defined(CONFIG_CMD_NAND) -# define NAND_ENV_SETTINGS \ - "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \ - "nandboot=" \ - "nand read $(loadaddr) 0x20000 0x100000;" \ - "run nandargs;" \ - "bootm" \ - "\0" -#else -# define NAND_ENV_SETTINGS -#endif -#if defined(CONFIG_CMD_NET) -# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -# define UBOOT_ENV_FILE "u-boot.bin" -# else -# define UBOOT_ENV_FILE "u-boot.ldr" -# endif -# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -# ifdef CONFIG_SPI -# define UBOOT_ENV_UPDATE \ - "eeprom write $(loadaddr) 0x0 $(filesize)" -# else -# ifndef CONFIG_BFIN_SPI_IMG_SIZE -# define CONFIG_BFIN_SPI_IMG_SIZE 0x40000 -# endif -# define UBOOT_ENV_UPDATE \ - "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \ - "sf erase 0 " __stringify(CONFIG_BFIN_SPI_IMG_SIZE) ";" \ - "sf write $(loadaddr) 0 $(filesize)" -# endif -# elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -# define UBOOT_ENV_UPDATE \ - "nand unlock 0 0x40000;" \ - "nand erase 0 0x40000;" \ - "nand write $(loadaddr) 0 0x40000" -# else -# ifndef UBOOT_ENV_UPDATE -# define UBOOT_ENV_UPDATE \ - "protect off 0x20000000 +$(filesize);" \ - "erase 0x20000000 +$(filesize);" \ - "cp.b $(loadaddr) 0x20000000 $(filesize)" -# endif -# endif -# ifdef CONFIG_NETCONSOLE -# define NETCONSOLE_ENV \ - "nc=" \ - "set ncip ${serverip};" \ - "set stdin nc;" \ - "set stdout nc;" \ - "set stderr nc" \ - "\0" -# else -# define NETCONSOLE_ENV -# endif -# define NETWORK_ENV_SETTINGS \ - NETCONSOLE_ENV \ - \ - "ubootfile=" UBOOT_ENV_FILE "\0" \ - "update=" \ - "tftp $(loadaddr) $(ubootfile);" \ - UBOOT_ENV_UPDATE \ - "\0" \ - "addip=set bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \ - "$(hostname):eth0:off" \ - "\0" \ - \ - "ramfile=uImage\0" \ - "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \ - "ramboot=" \ - "tftp $(loadaddr) $(ramfile);" \ - "run ramargs;" \ - "run addip;" \ - "bootm" \ - "\0" \ - \ - "nfsfile=vmImage\0" \ - "nfsargs=set bootargs " \ - "root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \ - "\0" \ - "nfsboot=" \ - "tftp $(loadaddr) $(nfsfile);" \ - "run nfsargs;" \ - "run addip;" \ - "bootm" \ - "\0" -#else -# define NETWORK_ENV_SETTINGS -#endif -#ifndef BOARD_ENV_SETTINGS -# define BOARD_ENV_SETTINGS -#endif -#define CONFIG_EXTRA_ENV_SETTINGS \ - NAND_ENV_SETTINGS \ - NETWORK_ENV_SETTINGS \ - FLASHBOOT_ENV_SETTINGS \ - BOARD_ENV_SETTINGS - -/* - * Network Settings - */ -#ifdef CONFIG_CMD_NET -# define CONFIG_NETMASK 255.255.255.0 -# ifndef CONFIG_IPADDR -# define CONFIG_IPADDR 192.168.0.15 -# define CONFIG_GATEWAYIP 192.168.0.1 -# define CONFIG_SERVERIP 192.168.0.2 -# endif -# ifndef CONFIG_ROOTPATH -# define CONFIG_ROOTPATH "/romfs" -# endif -# ifdef CONFIG_CMD_DHCP -# ifndef CONFIG_SYS_AUTOLOAD -# define CONFIG_SYS_AUTOLOAD "no" -# endif -# endif -# define CONFIG_IP_DEFRAG -# define CONFIG_NET_RETRY_COUNT 20 -#endif - -/* - * Flash Settings - */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 - -/* - * SPI Settings - */ -#ifdef CONFIG_SPI_FLASH_ALL -#endif - -/* - * I2C Settings - */ -#if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT) -# ifndef CONFIG_SYS_I2C_SPEED -# define CONFIG_SYS_I2C_SPEED 50000 -# endif -# ifndef CONFIG_SYS_I2C_SLAVE -# define CONFIG_SYS_I2C_SLAVE 0 -# endif -#endif - -/* - * Misc Settings - */ -#ifndef CONFIG_BOARD_SIZE_LIMIT -# define CONFIG_BOARD_SIZE_LIMIT $$(( 256 * 1024 )) -#endif -#define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */ -#define CONFIG_LZMA -#define CONFIG_MONITOR_IS_IN_RAM -#ifdef CONFIG_HW_WATCHDOG -# define CONFIG_BFIN_WATCHDOG -# ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS -# define CONFIG_WATCHDOG_TIMEOUT_MSECS 5000 -# endif -#endif -#ifndef CONFIG_ADI_GPIO2 -# define CONFIG_ADI_GPIO1 -#endif -#endif diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h deleted file mode 100644 index 4f65a1dec8..0000000000 --- a/include/configs/blackstamp.h +++ /dev/null @@ -1,218 +0,0 @@ -/* - * U-Boot - Configuration file for BlackStamp board - * Configuration by Ben Matthews for UR LLE using bf533-stamp.h - * as a template - * See http://blackfin.uclinux.org/gf/project/blackstamp/ - */ - -#ifndef __CONFIG_BLACKSTAMP_H__ -#define __CONFIG_BLACKSTAMP_H__ - -#include <asm/config-pre.h> - -/* - * Debugging: Set these options if you're having problems - */ -/* - * #define CONFIG_DEBUG_EARLY_SERIAL - * #define DEBUG - * #define CONFIG_DEBUG_DUMP - * #define CONFIG_DEBUG_DUMP_SYMS -*/ -#define CONFIG_PANIC_HANG 0 - -/* CPU Options - * Be sure to set the Silicon Revision Correctly - */ -#define CONFIG_BFIN_CPU bf532-0.5 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * Board settings - */ -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20300300 - -/* FLASH/ETHERNET uses the same address range - * Depending on what you have the CPLD doing - * this probably isn't needed - */ -#define SHARED_RESOURCES 1 - -/* Is I2C bit-banged? */ - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 16 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 3 - -/* - * Network settings - */ - -#ifdef CONFIG_SMC91111 -#define CONFIG_IPADDR 192.168.0.15 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_HOSTNAME blackstamp -#define CONFIG_ROOTPATH "/checkout/uClinux-dist/romfs" -#define CONFIG_SYS_AUTOLOAD "no" -#endif - -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x40000 - -/* - * SDRAM settings & memory map - */ - -#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ -#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_SYS_MALLOC_LEN (384 << 10) - -/* - * Command settings - */ - -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_ENV_OVERWRITE 1 - -#define CONFIG_CMD_BOOTLDR -#define CONFIG_CMD_CPLBINFO -#define CONFIG_CMD_DATE - -#define CONFIG_BOOTCOMMAND "run ramboot" -#define CONFIG_BOOTARGS \ - "root=/dev/mtdblock0 rw " \ - "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \ - "earlyprintk=" \ - "serial," \ - "uart" __stringify(CONFIG_UART_CONSOLE) "," \ - __stringify(CONFIG_BAUDRATE) " " \ - "console=ttyBF0," __stringify(CONFIG_BAUDRATE) - -#if defined(CONFIG_CMD_NET) -# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -# define UBOOT_ENV_FILE "u-boot.bin" -# else -# define UBOOT_ENV_FILE "u-boot.ldr" -# endif -# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -# ifdef CONFIG_SPI -# define UBOOT_ENV_UPDATE \ - "eeprom write $(loadaddr) 0x0 $(filesize)" -# else -# define UBOOT_ENV_UPDATE \ - "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \ - "sf erase 0 0x40000;" \ - "sf write $(loadaddr) 0 $(filesize)" -# endif -# else -# define UBOOT_ENV_UPDATE \ - "protect off 0x20000000 0x2003FFFF;" \ - "erase 0x20000000 0x2003FFFF;" \ - "cp.b $(loadaddr) 0x20000000 $(filesize)" -# endif -# define NETWORK_ENV_SETTINGS \ - "ubootfile=" UBOOT_ENV_FILE "\0" \ - "update=" \ - "tftp $(loadaddr) $(ubootfile);" \ - UBOOT_ENV_UPDATE \ - "\0" \ - "addip=set bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \ - "$(hostname):eth0:off" \ - "\0" \ - "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \ - "ramboot=" \ - "tftp $(loadaddr) uImage;" \ - "run ramargs;" \ - "run addip;" \ - "bootm" \ - "\0" \ - "nfsargs=set bootargs " \ - "root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \ - "\0" \ - "nfsboot=" \ - "tftp $(loadaddr) vmImage;" \ - "run nfsargs;" \ - "run addip;" \ - "bootm" \ - "\0" -#else -# define NETWORK_ENV_SETTINGS -#endif - -/* - * Console settings - */ -#define CONFIG_LOADS_ECHO 1 -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BFIN_SERIAL - -/* - * I2C settings - * By default PF2 is used as SDA and PF3 as SCL on the Stamp board - * Located on the expansion connector on pins 86/85 - * Note these pins are arbitrarily chosen because we aren't using - * them yet. You can (and probably should) change these values! - */ -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF9 -#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF8 -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_RTC_BFIN 1 - -/* - * Serial Flash Infomation - */ -#define CONFIG_BFIN_SPI -/* For the M25P64 SCK Should be Kept < 15Mhz */ -#define CONFIG_ENV_SPI_MAX_HZ 15000000 -#define CONFIG_SF_DEFAULT_SPEED 15000000 - -/* - * FLASH organization and environment definitions - */ - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3 -#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983 -#define CONFIG_EBIU_SDRRC_VAL 0x268 -#define CONFIG_EBIU_SDGCTL_VAL 0x911109 - -#undef CONFIG_CMD_JFFS2 - -#endif diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h deleted file mode 100644 index fe823ba4c7..0000000000 --- a/include/configs/blackvme.h +++ /dev/null @@ -1,222 +0,0 @@ -/* U-Boot for BlackVME. (C) Wojtek Skulski 2010. - * The board includes ADSP-BF561 rev. 0.5, - * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG), - * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell), - * SPI boot flash on PF2 (M25P64 8MB, or M25P128 16 MB), - * FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB), - * Spartan6-LX150 (memory-mapped; both PPIs also connected). - * See http://www.skutek.com - */ - -#ifndef __CONFIG_BLACKVME_H__ -#define __CONFIG_BLACKVME_H__ - -#include <asm/config-pre.h> - -/* Debugging: Set these options if you're having problems - * #define CONFIG_DEBUG_EARLY_SERIAL - * #define DEBUG - * #define CONFIG_DEBUG_DUMP - * #define CONFIG_DEBUG_DUMP_SYMS - * CONFIG_PANIC_HANG means that the board will not auto-reboot - */ -#define CONFIG_PANIC_HANG 0 - -/* CPU Options */ -#define CONFIG_BFIN_CPU bf561-0.5 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * CLOCK SETTINGS CAVEAT - * You CANNOT just change the clock settings, esp. the SCLK. - * The SDRAM timing, SPI baud, and the serial UART baud - * use SCLK frequency to set their own frequencies. Therefore, - * if you change the SCLK_DIV, you may also have to adjust - * SDRAM refresh and other timings. - * -------------------------------------------------------------- - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * 25 * 8 / 1 = 200 MHz - * 25 * 16 / 1 = 400 MHz - * 25 * 24 / 1 = 600 MHz - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - * 25 * 8 / 2 = 100 MHz - * 25 * 24 / 6 = 100 MHz - * 25 * 24 / 5 = 120 MHz - * 25 * 16 / 3 = 133 MHz - * 25 MHz because the oscillator also feeds the ether chip. - * CONFIG_CLKIN_HZ is 25 MHz written in Hz - * CLKIN_HALF controls the DF bit in PLL_CTL - * 0 = CLKIN 1 = CLKIN / 2 - * PLL_BYPASS controls the BYPASS bit in PLL_CTL - * 0 = do not bypass 1 = bypass PLL - * VCO_MULT = MSEL (multiplier) in PLL_CTL - * Values can range from 0-63 (where 0 means 64) - * CCLK_DIV = core clock divider (1, 2, 4, or 8 ONLY) - * SCLK_DIV = system clock divider, 1 to 15 - */ -#define CONFIG_CLKIN_HZ 25000000 -#define CONFIG_CLKIN_HALF 0 -#define CONFIG_PLL_BYPASS 0 -#define CONFIG_VCO_MULT 8 -#define CONFIG_CCLK_DIV 1 -#define CONFIG_SCLK_DIV 2 - -/* - * Ether chip in async memory space AMS3, same as BF561-EZ-KIT. - * Used in 32-bit mode. 16-bit mode not supported. - * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180 - */ -/* - * Network settings using a dedicated 2nd ether card in PC - * Windows will automatically acquire IP of that card - * Then use the dedicated card IP + 1 for the board - * http://docs.blackfin.uclinux.org/doku.php?id=setting_up_the_network - */ -#define CONFIG_DRIVER_AX88180 1 -#define AX88180_BASE 0x2c000000 - -#define CONFIG_HOSTNAME blackvme /* Bfin board */ -#define CONFIG_IPADDR 169.254.144.145 /* Bfin board */ -#define CONFIG_GATEWAYIP 169.254.144.144 /* dedic card */ -#define CONFIG_SERVERIP 169.254.144.144 /* tftp server */ -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_ROOTPATH "/export/uClinux-dist/romfs" /*NFS*/ -#define CFG_AUTOLOAD "no" - -/* - * SDRAM settings & memory map - */ - -#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ -#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ -/* - * SDRAM reference page - * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram - * NOTE: BlackVME populates only SDRAM bank 0 - */ -/* CONFIG_EBIU_SDBCTL_VAL bank ctrl may be needed in future */ -#define CONFIG_EBIU_SDGCTL_VAL 0x91114d /* global control */ -#define CONFIG_EBIU_SDRRC_VAL 0x306 /* refresh rate */ - -/* Async memory global settings. (ASRAM, not SDRAM) - * HRM page 16-10. Global ASRAM control = 0x3F. Six lower bits = 1 - * CLKOUT enabled, all async banks enabled, core has priority - * bank 0&1 16 bit (FPGA) - * bank 2&3 32 bit (ether and USB chips) - */ -#define CONFIG_EBIU_AMGCTL_VAL 0x3F /* ASRAM setup */ - -/* Async mem timing: BF561 HRM page 16-12 and 16-15. - * Default values 0xFFC2 FFC2 are the slowest supported. - * Example settings of CONFIG_EBIU_AMBCTL1_VAL - * 1. EZ-KIT settings: 0xFFC2 7BB0 - * 2. Bank 3 good timing for AX88180 @ 125MHz = 0x8850 xxxx - * See the following page: - * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180 - * 3. Bank 3 timing for AX88180 @ SCLK = 100 MHz: - * AX88180 WEN = 5 clocks REN 6 clocks @ SCLK = 100 MHz - * One extra clock needed because AX88180 is asynchronous to CPU. - */ - /* bank 1 0 */ -#define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2 - /* bank 3 2 */ -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2 - -/* memory layout */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_SYS_MALLOC_LEN (384 << 10) - -/* - * Serial SPI Flash - * For the M25P64 SCK should be kept < 15 MHz - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x40000 - -#define CONFIG_ENV_SPI_MAX_HZ 15000000 -#define CONFIG_SF_DEFAULT_SPEED 15000000 - -/* - * Interactive command settings - */ - -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_AUTO_COMPLETE 1 - -#define CONFIG_CMD_BOOTLDR -#define CONFIG_CMD_CPLBINFO - -/* - * Default: boot from SPI flash. - * "sfboot" is a composite command defined in extra settings - */ -#define CONFIG_BOOTCOMMAND "run sfboot" - -/* - * Console settings - */ -#define CONFIG_LOADS_ECHO 1 -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BFIN_SERIAL - -/* - * U-Boot environment variables. Use "printenv" to examine. - * http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:env - */ -#define CONFIG_BOOTARGS \ - "root=/dev/mtdblock0 rw " \ - "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \ - "earlyprintk=serial,uart0," \ - __stringify(CONFIG_BAUDRATE) " " \ - "console=ttyBF0," __stringify(CONFIG_BAUDRATE) " " - -/* Convenience env variables & commands. - * Reserve kernstart = 0x20000 = 128 kB for U-Boot. - * Reserve kernarea = 0x500000 = 5 MB for kernel (reasonable size). - * U-Boot image is saved at flash offset=0. - * Kernel image is saved at flash offset=$kernstart. - * Instructions. Ksave takes about a minute to complete. - * 1. Update U-Boot: run uget; run usave - * 2. Update kernel: run kget; run ksave - * After updating U-Boot also update the kernel per above instructions - * to make the saved environment consistent with the flash. - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernstart=0x20000\0" \ - "kernarea=0x500000\0" \ - "uget=tftp u-boot.ldr\0" \ - "kget=tftp uImage\0" \ - "usave=sf probe 2; " \ - "sf erase 0 $(kernstart); " \ - "sf write $(fileaddr) 0 $(filesize)\0" \ - "ksave=sf probe 2; " \ - "saveenv; " \ - "echo Now patiently wait for the prompt...; " \ - "sf erase $(kernstart) $(kernarea); " \ - "sf write $(fileaddr) $(kernstart) $(filesize)\0" \ - "sfboot=sf probe 2; " \ - "sf read $(loadaddr) $(kernstart) $(filesize); " \ - "run addip; bootm\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):eth0:off\0" - -/* - * Soft I2C settings (BF561 does not have hard I2C) - * PF12,13 on SPI connector 0. - */ -#ifdef CONFIG_SYS_I2C_SOFT -# define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF12 -# define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF13 -# define CONFIG_SYS_I2C_SPEED 50000 -# define CONFIG_SYS_I2C_SLAVE 0xFE -#endif - -#undef CONFIG_CMD_JFFS2 - -#endif diff --git a/include/configs/br4.h b/include/configs/br4.h deleted file mode 100644 index 8a7a359347..0000000000 --- a/include/configs/br4.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * U-Boot - Configuration file for BR4 Appliance - * - * based on bf537-stamp.h - * Copyright (c) Switchfin Org. <dpn@switchfin.org> - */ - -#ifndef __CONFIG_BR4_H__ -#define __CONFIG_BR4_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 24 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x306 -#define CONFIG_EBIU_SDGCTL_VAL 0x8091998d - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (384 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_NETCONSOLE -#endif -#define CONFIG_HOSTNAME br4 -#define CONFIG_TFTP_BLOCKSIZE 4404 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * NAND Settings - */ -#define CONFIG_NAND_PLAT -#define CONFIG_SYS_NAND_BASE 0x20000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_WRITE(addr, cmd) \ - do { \ - bfin_write8(addr, cmd); \ - SSYNC(); \ - } while (0) - -#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) -#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_GPIO_DEV_READY GPIO_PF9 - -/* - * Misc Settings - */ -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run nandboot" -#define CONFIG_LOADADDR 0x2000000 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -/* - * Overwrite some settings defined in bfin_adi_common.h - */ -#undef NAND_ENV_SETTINGS -#define NAND_ENV_SETTINGS \ - "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \ - "nandboot=" \ - "nand read $(loadaddr) 0x0 0x900000;" \ - "run nandargs;" \ - "bootm" \ - "\0" - -#endif diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h deleted file mode 100644 index 3b6f9baa5d..0000000000 --- a/include/configs/cm-bf527.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * U-Boot - Configuration file for CM-BF527 board - */ - -#ifndef __CONFIG_CM_BF527_H__ -#define __CONFIG_CM_BF527_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf527-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 21 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* Decrease core voltage */ -#define CONFIG_VR_CTL_VAL (VLEV_120 | CLKBUFOE | FREQ_1000) - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -#define CONFIG_EBIU_SDRRC_VAL 0x3f8 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * NAND Settings - * (can't be used sametime as ethernet) - */ -/* #define CONFIG_BFIN_NFC */ -#ifdef CONFIG_BFIN_NFC -#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 -#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_CMD_NAND -#endif - -/* - * Network Settings - */ -#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \ - !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC) -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_RMII -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME cm-bf527 - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 67 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x20008000 -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_SECT_SIZE 0x8000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define FLASHBOOT_ENV_SETTINGS \ - "flashboot=flread 20040000 1000000 300000;" \ - "bootm 0x1000000\0" - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h deleted file mode 100644 index 01a3579974..0000000000 --- a/include/configs/cm-bf533.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * U-Boot - Configuration file for CM-BF533 board - */ - -#ifndef __CONFIG_CM_BF533_H__ -#define __CONFIG_CM_BF533_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf533-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 22 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* Decrease core voltage */ -#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000) - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -#define CONFIG_EBIU_SDRRC_VAL ((((CONFIG_SCLK_HZ / 1000) * 64) / 8192) - (7 + 2)) -#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3) - -#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20200300 -#define CONFIG_HOSTNAME cm-bf533 - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 16 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x10000 - -/* - * Misc Settings - */ -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h deleted file mode 100644 index d9f91b5b9a..0000000000 --- a/include/configs/cm-bf537e.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * U-Boot - Configuration file for CM-BF537E board - */ - -#ifndef __CONFIG_CM_BF537E_H__ -#define __CONFIG_CM_BF537E_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 21 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* Decrease core voltage */ -#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000) - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -#define CONFIG_EBIU_SDRRC_VAL 0x3f8 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_BASE 0x20308000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME cm-bf537e - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 35 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SECT_SIZE 0x8000 -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -#define ENV_IS_EMBEDDED -#endif -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * SPI_MMC Settings - */ -#define CONFIG_MMC_SPI - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define FLASHBOOT_ENV_SETTINGS \ - "flashboot=flread 20040000 1000000 3c0000;" \ - "bootm 0x1000000\0" -#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024)) - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h deleted file mode 100644 index af11ebe5f8..0000000000 --- a/include/configs/cm-bf537u.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * U-Boot - Configuration file for CM-BF537U board - */ - -#ifndef __CONFIG_CM_BF537U_H__ -#define __CONFIG_CM_BF537U_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 30000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 18 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 -/* Core voltage */ -#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000) - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -#define CONFIG_EBIU_SDRRC_VAL 0x3f8 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_BASE 0x20308000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME cm-bf537u - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 35 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SECT_SIZE 0x8000 -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -#define ENV_IS_EMBEDDED -#endif -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * SPI_MMC Settings - */ -#define CONFIG_MMC_SPI - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define FLASHBOOT_ENV_SETTINGS \ - "flashboot=flread 20040000 1000000 300000;" \ - "bootm 0x1000000\0" -#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024)) - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h deleted file mode 100644 index 10e8efde5d..0000000000 --- a/include/configs/cm-bf548.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * U-Boot - Configuration file for cm-bf548 board - */ - -#ifndef __CONFIG_CM_BF548_H__ -#define __CONFIG_CM_BF548_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf548-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 21 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* Decrease core voltage */ -#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000) - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE -#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222 -#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021 - -/* Default bank mapping: - * Async Bank 0 - 32MB Burst Flash - * Async Bank 1 - Ethernet - * Async Bank 2 - Nothing - * Async Bank 3 - Nothing - */ -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 -#define CONFIG_EBIU_FCTL_VAL (BCLK_4) -#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH) - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (640 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_BASE 0x24000000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_HOSTNAME cm-bf548 - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 259 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x20008000 -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * Misc Settings - */ -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 1 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" - -#define CONFIG_ADI_GPIO2 - -#ifndef __ADSPBF542__ -/* Don't waste time transferring a logo over the UART */ -# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) -# define EASYLOGO_HEADER <asm/bfin_logo_230x230_gzip.h> -# endif -# define CONFIG_DEB_DMA_URGENT -#endif - -/* Define if want to do post memory test */ -#undef CONFIG_POST -#ifdef CONFIG_POST -#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */ -#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ -#endif - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h deleted file mode 100644 index ac1646cf71..0000000000 --- a/include/configs/cm-bf561.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * U-Boot - Configuration file for CM-BF561 board - */ - -#ifndef __CONFIG_CM_BF561_H__ -#define __CONFIG_CM_BF561_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf561-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 20 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* Decrease core voltage */ -#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000) - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL ((((CONFIG_SCLK_HZ / 1000) * 64) / 4096) - (7 + 2)) -#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3) - -#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | B3_PEN | B2_PEN | B1_PEN | B0_PEN | AMBEN_ALL | AMCKEN) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_BASE 0x24008000 /* AMS1 */ -#define CONFIG_SMC911X_16_BIT -#define CONFIG_HOSTNAME cm-bf561 - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 67 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * Misc Settings - */ -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/dnp5370.h b/include/configs/dnp5370.h deleted file mode 100644 index 1690dda519..0000000000 --- a/include/configs/dnp5370.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * U-Boot - Configuration file for SSV DNP5370 board - */ - -#ifndef __CONFIG_DNP5370_H__ -#define __CONFIG_DNP5370_H__ - -/* this must come first */ -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -#define CONFIG_CLKIN_HZ 25000000 -#define CONFIG_CLKIN_HALF 0 -#define CONFIG_PLL_BYPASS 0 -#define CONFIG_VCO_MULT 24 -#define CONFIG_CCLK_DIV 1 -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -#define CONFIG_EBIU_SDRRC_VAL 0x03a0 -#define CONFIG_EBIU_SDBCTL_VAL 0x0013 -#define CONFIG_EBIU_SDGCTL_VAL 0x8091998d - -#define CONFIG_EBIU_AMGCTL_VAL 0xF7 -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define CONFIG_ROOTPATH "/romfs" - -#define CONFIG_BFIN_MAC 1 -#define CONFIG_PHY_ADDR 0 -#define CONFIG_RMII 1 - -#endif - -/* - * Flash Settings - * - * Only 3 MB of the 4 MB NOR flash are addressable. - * But limiting the flash size does not seem to work. - * It seems the CFI detection has precedence. - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* (M29W320EB) */ - -/* 512k reserved for u-boot */ -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x20004000 -#define CONFIG_ENV_SIZE 0x00002000 -#define CONFIG_ENV_SECT_SIZE 0x00002000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_OFFSET 0x00004000 /* (CONFIG_ENV_ADDR - CONFIG_FLASH_BASE) */ - -#define ENV_IS_EMBEDDED -#define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); - -/* - * Misc Settings - */ -#define CONFIG_CMD_STRINGS -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_SYS_LONGHELP - -/* This disables the hardware watchdog (not inside the bfin) */ -#define CONFIG_DNP5370_EXT_WD_DISABLE 1 - -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BFIN_SERIAL -#define CONFIG_BOOTCOMMAND "bootm 0x20030000" -#define CONFIG_BOOTARGS "console=ttyBF0,115200 root=/dev/mtdblock3 rootfstype=ext2" - -/* Convenience commands to update Linux in NOR flash */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fetchme=tftpboot 0x01000000 uImage;" \ - "iminfo\0" \ - "flashme=protect off 0x20030000 0x2003ffff;" \ - "erase 0x20030000 0x202effff;" \ - "cp.b 0x01000000 0x20030000 0x2c0000\0" \ - "runme=bootm 0x01000000\0" - -#endif diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h deleted file mode 100644 index 4cd0f77146..0000000000 --- a/include/configs/ibf-dsp561.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * U-Boot - Configuration file for IBF-DSP561 board - */ - -#ifndef __CONFIG_IBF_DSP561__H__ -#define __CONFIG_IBF_DSP561__H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf561-0.5 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 24 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x377 -#define CONFIG_EBIU_SDGCTL_VAL 0x91998d -#define CONFIG_EBIU_SDBCTL_VAL 0x15 - -#define CONFIG_EBIU_AMGCTL_VAL 0x3F -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_DRIVER_AX88180 1 -#define AX88180_BASE 0x2c000000 -#define CONFIG_HOSTNAME ibf-dsp561 - -/* - * Flash Settings - */ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI_AMD_RESET -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */ -/* The BF561-EZKIT uses a top boot flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x12000 /* Total Size of Environment Sector */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -#define ENV_IS_EMBEDDED -#else -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#endif -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0 -#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1 - -/* - * Misc Settings - */ -#define CONFIG_UART_CONSOLE 0 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/ip04.h b/include/configs/ip04.h deleted file mode 100644 index 1531feb83d..0000000000 --- a/include/configs/ip04.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * U-Boot - Configuration file for IP04 board (having BF532 processor) - * - * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com - * - * Copyright (c) 2005-2010 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __CONFIG_IP04_H__ -#define __CONFIG_IP04_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf532-0.5 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 10000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 40 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 3 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x408 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 -#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2 - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_HOSTNAME IP04 - -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_NO_SROM -#define CONFIG_DM9000_BASE 0x20100000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 2) - -/* - * Flash Settings - */ -#define CONFIG_ENV_OVERWRITE 1 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_PREBOOT "echo starting from spi flash" -#define CONFIG_ENV_OFFSET 0x30000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 - -/* - * NAND Settings - */ -#define CONFIG_NAND_PLAT -#define CONFIG_SYS_NAND_BASE 0x20000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_WRITE(addr, cmd) \ - do { \ - bfin_write8(addr, cmd); \ - SSYNC(); \ - } while (0) - -#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) -#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10 - -/* - * Misc Settings - */ -#define CONFIG_UART_CONSOLE 0 - -#undef CONFIG_SHOW_BOOT_PROGRESS -/* Enable this if bootretry required; currently it's disabled */ -#define CONFIG_BOOT_RETRY_TIME -1 -#define CONFIG_BOOTCOMMAND "run nandboot" - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/pr1.h b/include/configs/pr1.h deleted file mode 100644 index d3fba0d3ff..0000000000 --- a/include/configs/pr1.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * U-Boot - Configuration file for PR1 Appliance - * - * based on bf537-stamp.h - * Copyright (c) Switchfin Org. <dpn@switchfin.org> - */ - -#ifndef __CONFIG_PR1_H__ -#define __CONFIG_PR1_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.3 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 24 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 11 -#define CONFIG_MEM_SIZE 128 - -#define CONFIG_EBIU_SDRRC_VAL 0x306 -#define CONFIG_EBIU_SDGCTL_VAL 0x8091998d - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (384 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_NETCONSOLE -#endif -#define CONFIG_HOSTNAME pr1 -#define CONFIG_TFTP_BLOCKSIZE 4404 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * NAND Settings - */ -#define CONFIG_NAND_PLAT -#define CONFIG_SYS_NAND_BASE 0x20000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_WRITE(addr, cmd) \ - do { \ - bfin_write8(addr, cmd); \ - SSYNC(); \ - } while (0) - -#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) -#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_GPIO_DEV_READY GPIO_PF9 - -/* - * Misc Settings - */ -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run nandboot" -#define CONFIG_LOADADDR 0x2000000 - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -/* - * Overwrite some settings defined in bfin_adi_common.h - */ -#undef NAND_ENV_SETTINGS -#define NAND_ENV_SETTINGS \ - "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \ - "nandboot=" \ - "nand read $(loadaddr) 0x0 0x900000;" \ - "run nandargs;" \ - "bootm" \ - "\0" - -#endif diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h deleted file mode 100644 index 7924c8e483..0000000000 --- a/include/configs/tcm-bf518.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * U-Boot - Configuration file for Bluetechnix TCM-BF518 board - */ - -#ifndef __CONFIG_TCM_BF518_H__ -#define __CONFIG_TCM_BF518_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf518-0.0 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 16 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* - * Memory Settings - */ -/* This board has a 32meg MT48H16M16 */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -#define CONFIG_EBIU_SDRRC_VAL 0x3f8 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (384 * 1024) - -/* - * Network Settings - */ -#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__) -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME tcm-bf518 - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 19 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x8000 -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * Misc Settings - */ -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h deleted file mode 100644 index f9d9f84672..0000000000 --- a/include/configs/tcm-bf537.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * U-Boot - Configuration file for TCM-BF537 board - */ - -#ifndef __CONFIG_TCM_BF537_H__ -#define __CONFIG_TCM_BF537_H__ - -#include <asm/config-pre.h> - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 25000000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 21 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - -/* Decrease core voltage */ -#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000) - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 9 -#define CONFIG_MEM_SIZE 32 - -#define CONFIG_EBIU_SDRRC_VAL 0x3f8 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) -#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) -#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_BASE 0x20308000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_NETCONSOLE 1 -#endif -#define CONFIG_HOSTNAME tcm-bf537 - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 67 - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_SECT_SIZE 0x8000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) -#define ENV_IS_EMBEDDED -#endif -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - arch/blackfin/lib/built-in.o (.text*); \ - arch/blackfin/cpu/built-in.o (.text*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text*); -#endif - -/* - * I2C Settings - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_ADI - -/* - * SPI_MMC Settings - */ -#define CONFIG_MMC_SPI - -/* - * Misc Settings - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 -#define CONFIG_BOOTCOMMAND "run flashboot" -#define FLASHBOOT_ENV_SETTINGS \ - "flashboot=flread 20040000 1000000 300000;" \ - "bootm 0x1000000\0" -#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024)) - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include <configs/bfin_adi_common.h> - -#endif diff --git a/include/linux/usb/musb.h b/include/linux/usb/musb.h index 075d222195..e1fdab0c0f 100644 --- a/include/linux/usb/musb.h +++ b/include/linux/usb/musb.h @@ -91,14 +91,6 @@ struct musb_hdrc_config { u8 ram_bits; /* ram address size */ struct musb_hdrc_eps_bits *eps_bits __deprecated; -#ifdef CONFIG_BLACKFIN - /* A GPIO controlling VRSEL in Blackfin */ - unsigned int gpio_vrsel; - unsigned int gpio_vrsel_active; - /* musb CLKIN in Blackfin in MHZ */ - unsigned char clkin; -#endif - }; struct musb_hdrc_platform_data { |